1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <ethdev_driver.h> 20 #include <ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_bus_auxiliary.h> 24 #include <rte_common.h> 25 #include <rte_kvargs.h> 26 #include <rte_rwlock.h> 27 #include <rte_spinlock.h> 28 #include <rte_string_fns.h> 29 #include <rte_alarm.h> 30 #include <rte_eal_paging.h> 31 32 #include <mlx5_glue.h> 33 #include <mlx5_devx_cmds.h> 34 #include <mlx5_common.h> 35 #include <mlx5_common_mp.h> 36 #include <mlx5_common_mr.h> 37 #include <mlx5_malloc.h> 38 39 #include "mlx5_defs.h" 40 #include "mlx5.h" 41 #include "mlx5_common_os.h" 42 #include "mlx5_utils.h" 43 #include "mlx5_rxtx.h" 44 #include "mlx5_rx.h" 45 #include "mlx5_tx.h" 46 #include "mlx5_autoconf.h" 47 #include "mlx5_mr.h" 48 #include "mlx5_flow.h" 49 #include "rte_pmd_mlx5.h" 50 #include "mlx5_verbs.h" 51 #include "mlx5_nl.h" 52 #include "mlx5_devx.h" 53 54 #ifndef HAVE_IBV_MLX5_MOD_MPW 55 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 56 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 57 #endif 58 59 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 60 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 61 #endif 62 63 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 64 65 /* Spinlock for mlx5_shared_data allocation. */ 66 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 67 68 /* Process local data for secondary processes. */ 69 static struct mlx5_local_data mlx5_local_data; 70 71 /* rte flow indexed pool configuration. */ 72 static struct mlx5_indexed_pool_config icfg[] = { 73 { 74 .size = sizeof(struct rte_flow), 75 .trunk_size = 64, 76 .need_lock = 1, 77 .release_mem_en = 0, 78 .malloc = mlx5_malloc, 79 .free = mlx5_free, 80 .per_core_cache = 0, 81 .type = "ctl_flow_ipool", 82 }, 83 { 84 .size = sizeof(struct rte_flow), 85 .trunk_size = 64, 86 .grow_trunk = 3, 87 .grow_shift = 2, 88 .need_lock = 1, 89 .release_mem_en = 0, 90 .malloc = mlx5_malloc, 91 .free = mlx5_free, 92 .per_core_cache = 1 << 14, 93 .type = "rte_flow_ipool", 94 }, 95 { 96 .size = sizeof(struct rte_flow), 97 .trunk_size = 64, 98 .grow_trunk = 3, 99 .grow_shift = 2, 100 .need_lock = 1, 101 .release_mem_en = 0, 102 .malloc = mlx5_malloc, 103 .free = mlx5_free, 104 .per_core_cache = 0, 105 .type = "mcp_flow_ipool", 106 }, 107 }; 108 109 /** 110 * Set the completion channel file descriptor interrupt as non-blocking. 111 * 112 * @param[in] rxq_obj 113 * Pointer to RQ channel object, which includes the channel fd 114 * 115 * @param[out] fd 116 * The file descriptor (representing the intetrrupt) used in this channel. 117 * 118 * @return 119 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 120 */ 121 int 122 mlx5_os_set_nonblock_channel_fd(int fd) 123 { 124 int flags; 125 126 flags = fcntl(fd, F_GETFL); 127 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 128 } 129 130 /** 131 * Get mlx5 device attributes. The glue function query_device_ex() is called 132 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 133 * device attributes from the glue out parameter. 134 * 135 * @param dev 136 * Pointer to ibv context. 137 * 138 * @param device_attr 139 * Pointer to mlx5 device attributes. 140 * 141 * @return 142 * 0 on success, non zero error number otherwise 143 */ 144 int 145 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) 146 { 147 int err; 148 struct ibv_device_attr_ex attr_ex; 149 memset(device_attr, 0, sizeof(*device_attr)); 150 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 151 if (err) 152 return err; 153 154 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 155 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 156 device_attr->max_sge = attr_ex.orig_attr.max_sge; 157 device_attr->max_cq = attr_ex.orig_attr.max_cq; 158 device_attr->max_cqe = attr_ex.orig_attr.max_cqe; 159 device_attr->max_mr = attr_ex.orig_attr.max_mr; 160 device_attr->max_pd = attr_ex.orig_attr.max_pd; 161 device_attr->max_qp = attr_ex.orig_attr.max_qp; 162 device_attr->max_srq = attr_ex.orig_attr.max_srq; 163 device_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr; 164 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 165 device_attr->max_rwq_indirection_table_size = 166 attr_ex.rss_caps.max_rwq_indirection_table_size; 167 device_attr->max_tso = attr_ex.tso_caps.max_tso; 168 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 169 170 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 171 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 172 if (err) 173 return err; 174 175 device_attr->flags = dv_attr.flags; 176 device_attr->comp_mask = dv_attr.comp_mask; 177 #ifdef HAVE_IBV_MLX5_MOD_SWP 178 device_attr->sw_parsing_offloads = 179 dv_attr.sw_parsing_caps.sw_parsing_offloads; 180 #endif 181 device_attr->min_single_stride_log_num_of_bytes = 182 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 183 device_attr->max_single_stride_log_num_of_bytes = 184 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 185 device_attr->min_single_wqe_log_num_of_strides = 186 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 187 device_attr->max_single_wqe_log_num_of_strides = 188 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 189 device_attr->stride_supported_qpts = 190 dv_attr.striding_rq_caps.supported_qpts; 191 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 192 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 193 #endif 194 strlcpy(device_attr->fw_ver, attr_ex.orig_attr.fw_ver, 195 sizeof(device_attr->fw_ver)); 196 197 return err; 198 } 199 200 /** 201 * Verbs callback to allocate a memory. This function should allocate the space 202 * according to the size provided residing inside a huge page. 203 * Please note that all allocation must respect the alignment from libmlx5 204 * (i.e. currently rte_mem_page_size()). 205 * 206 * @param[in] size 207 * The size in bytes of the memory to allocate. 208 * @param[in] data 209 * A pointer to the callback data. 210 * 211 * @return 212 * Allocated buffer, NULL otherwise and rte_errno is set. 213 */ 214 static void * 215 mlx5_alloc_verbs_buf(size_t size, void *data) 216 { 217 struct mlx5_dev_ctx_shared *sh = data; 218 void *ret; 219 size_t alignment = rte_mem_page_size(); 220 if (alignment == (size_t)-1) { 221 DRV_LOG(ERR, "Failed to get mem page size"); 222 rte_errno = ENOMEM; 223 return NULL; 224 } 225 226 MLX5_ASSERT(data != NULL); 227 ret = mlx5_malloc(0, size, alignment, sh->numa_node); 228 if (!ret && size) 229 rte_errno = ENOMEM; 230 return ret; 231 } 232 233 /** 234 * Detect misc5 support or not 235 * 236 * @param[in] priv 237 * Device private data pointer 238 */ 239 #ifdef HAVE_MLX5DV_DR 240 static void 241 __mlx5_discovery_misc5_cap(struct mlx5_priv *priv) 242 { 243 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 244 /* Dummy VxLAN matcher to detect rdma-core misc5 cap 245 * Case: IPv4--->UDP--->VxLAN--->vni 246 */ 247 void *tbl; 248 struct mlx5_flow_dv_match_params matcher_mask; 249 void *match_m; 250 void *matcher; 251 void *headers_m; 252 void *misc5_m; 253 uint32_t *tunnel_header_m; 254 struct mlx5dv_flow_matcher_attr dv_attr; 255 256 memset(&matcher_mask, 0, sizeof(matcher_mask)); 257 matcher_mask.size = sizeof(matcher_mask.buf); 258 match_m = matcher_mask.buf; 259 headers_m = MLX5_ADDR_OF(fte_match_param, match_m, outer_headers); 260 misc5_m = MLX5_ADDR_OF(fte_match_param, 261 match_m, misc_parameters_5); 262 tunnel_header_m = (uint32_t *) 263 MLX5_ADDR_OF(fte_match_set_misc5, 264 misc5_m, tunnel_header_1); 265 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff); 266 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 4); 267 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff); 268 *tunnel_header_m = 0xffffff; 269 270 tbl = mlx5_glue->dr_create_flow_tbl(priv->sh->rx_domain, 1); 271 if (!tbl) { 272 DRV_LOG(INFO, "No SW steering support"); 273 return; 274 } 275 dv_attr.type = IBV_FLOW_ATTR_NORMAL, 276 dv_attr.match_mask = (void *)&matcher_mask, 277 dv_attr.match_criteria_enable = 278 (1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT) | 279 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT); 280 dv_attr.priority = 3; 281 #ifdef HAVE_MLX5DV_DR_ESWITCH 282 void *misc2_m; 283 if (priv->config.dv_esw_en) { 284 /* FDB enabled reg_c_0 */ 285 dv_attr.match_criteria_enable |= 286 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT); 287 misc2_m = MLX5_ADDR_OF(fte_match_param, 288 match_m, misc_parameters_2); 289 MLX5_SET(fte_match_set_misc2, misc2_m, 290 metadata_reg_c_0, 0xffff); 291 } 292 #endif 293 matcher = mlx5_glue->dv_create_flow_matcher(priv->sh->ctx, 294 &dv_attr, tbl); 295 if (matcher) { 296 priv->sh->misc5_cap = 1; 297 mlx5_glue->dv_destroy_flow_matcher(matcher); 298 } 299 mlx5_glue->dr_destroy_flow_tbl(tbl); 300 #else 301 RTE_SET_USED(priv); 302 #endif 303 } 304 #endif 305 306 /** 307 * Verbs callback to free a memory. 308 * 309 * @param[in] ptr 310 * A pointer to the memory to free. 311 * @param[in] data 312 * A pointer to the callback data. 313 */ 314 static void 315 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 316 { 317 MLX5_ASSERT(data != NULL); 318 mlx5_free(ptr); 319 } 320 321 /** 322 * Initialize DR related data within private structure. 323 * Routine checks the reference counter and does actual 324 * resources creation/initialization only if counter is zero. 325 * 326 * @param[in] priv 327 * Pointer to the private device data structure. 328 * 329 * @return 330 * Zero on success, positive error code otherwise. 331 */ 332 static int 333 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 334 { 335 struct mlx5_dev_ctx_shared *sh = priv->sh; 336 char s[MLX5_NAME_SIZE] __rte_unused; 337 int err; 338 339 MLX5_ASSERT(sh && sh->refcnt); 340 if (sh->refcnt > 1) 341 return 0; 342 err = mlx5_alloc_table_hash_list(priv); 343 if (err) 344 goto error; 345 /* The resources below are only valid with DV support. */ 346 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 347 /* Init port id action list. */ 348 snprintf(s, sizeof(s), "%s_port_id_action_list", sh->ibdev_name); 349 sh->port_id_action_list = mlx5_list_create(s, sh, true, 350 flow_dv_port_id_create_cb, 351 flow_dv_port_id_match_cb, 352 flow_dv_port_id_remove_cb, 353 flow_dv_port_id_clone_cb, 354 flow_dv_port_id_clone_free_cb); 355 if (!sh->port_id_action_list) 356 goto error; 357 /* Init push vlan action list. */ 358 snprintf(s, sizeof(s), "%s_push_vlan_action_list", sh->ibdev_name); 359 sh->push_vlan_action_list = mlx5_list_create(s, sh, true, 360 flow_dv_push_vlan_create_cb, 361 flow_dv_push_vlan_match_cb, 362 flow_dv_push_vlan_remove_cb, 363 flow_dv_push_vlan_clone_cb, 364 flow_dv_push_vlan_clone_free_cb); 365 if (!sh->push_vlan_action_list) 366 goto error; 367 /* Init sample action list. */ 368 snprintf(s, sizeof(s), "%s_sample_action_list", sh->ibdev_name); 369 sh->sample_action_list = mlx5_list_create(s, sh, true, 370 flow_dv_sample_create_cb, 371 flow_dv_sample_match_cb, 372 flow_dv_sample_remove_cb, 373 flow_dv_sample_clone_cb, 374 flow_dv_sample_clone_free_cb); 375 if (!sh->sample_action_list) 376 goto error; 377 /* Init dest array action list. */ 378 snprintf(s, sizeof(s), "%s_dest_array_list", sh->ibdev_name); 379 sh->dest_array_list = mlx5_list_create(s, sh, true, 380 flow_dv_dest_array_create_cb, 381 flow_dv_dest_array_match_cb, 382 flow_dv_dest_array_remove_cb, 383 flow_dv_dest_array_clone_cb, 384 flow_dv_dest_array_clone_free_cb); 385 if (!sh->dest_array_list) 386 goto error; 387 #endif 388 #ifdef HAVE_MLX5DV_DR 389 void *domain; 390 391 /* Reference counter is zero, we should initialize structures. */ 392 domain = mlx5_glue->dr_create_domain(sh->ctx, 393 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 394 if (!domain) { 395 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 396 err = errno; 397 goto error; 398 } 399 sh->rx_domain = domain; 400 domain = mlx5_glue->dr_create_domain(sh->ctx, 401 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 402 if (!domain) { 403 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 404 err = errno; 405 goto error; 406 } 407 sh->tx_domain = domain; 408 #ifdef HAVE_MLX5DV_DR_ESWITCH 409 if (priv->config.dv_esw_en) { 410 domain = mlx5_glue->dr_create_domain 411 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 412 if (!domain) { 413 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 414 err = errno; 415 goto error; 416 } 417 sh->fdb_domain = domain; 418 } 419 /* 420 * The drop action is just some dummy placeholder in rdma-core. It 421 * does not belong to domains and has no any attributes, and, can be 422 * shared by the entire device. 423 */ 424 sh->dr_drop_action = mlx5_glue->dr_create_flow_action_drop(); 425 if (!sh->dr_drop_action) { 426 DRV_LOG(ERR, "FDB mlx5dv_dr_create_flow_action_drop"); 427 err = errno; 428 goto error; 429 } 430 #endif 431 if (!sh->tunnel_hub && priv->config.dv_miss_info) 432 err = mlx5_alloc_tunnel_hub(sh); 433 if (err) { 434 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 435 goto error; 436 } 437 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 438 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 439 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 440 if (sh->fdb_domain) 441 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 442 } 443 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 444 if (!priv->config.allow_duplicate_pattern) { 445 #ifndef HAVE_MLX5_DR_ALLOW_DUPLICATE 446 DRV_LOG(WARNING, "Disallow duplicate pattern is not supported - maybe old rdma-core version?"); 447 #endif 448 mlx5_glue->dr_allow_duplicate_rules(sh->rx_domain, 0); 449 mlx5_glue->dr_allow_duplicate_rules(sh->tx_domain, 0); 450 if (sh->fdb_domain) 451 mlx5_glue->dr_allow_duplicate_rules(sh->fdb_domain, 0); 452 } 453 454 __mlx5_discovery_misc5_cap(priv); 455 #endif /* HAVE_MLX5DV_DR */ 456 sh->default_miss_action = 457 mlx5_glue->dr_create_flow_action_default_miss(); 458 if (!sh->default_miss_action) 459 DRV_LOG(WARNING, "Default miss action is not supported."); 460 return 0; 461 error: 462 /* Rollback the created objects. */ 463 if (sh->rx_domain) { 464 mlx5_glue->dr_destroy_domain(sh->rx_domain); 465 sh->rx_domain = NULL; 466 } 467 if (sh->tx_domain) { 468 mlx5_glue->dr_destroy_domain(sh->tx_domain); 469 sh->tx_domain = NULL; 470 } 471 if (sh->fdb_domain) { 472 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 473 sh->fdb_domain = NULL; 474 } 475 if (sh->dr_drop_action) { 476 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 477 sh->dr_drop_action = NULL; 478 } 479 if (sh->pop_vlan_action) { 480 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 481 sh->pop_vlan_action = NULL; 482 } 483 if (sh->encaps_decaps) { 484 mlx5_hlist_destroy(sh->encaps_decaps); 485 sh->encaps_decaps = NULL; 486 } 487 if (sh->modify_cmds) { 488 mlx5_hlist_destroy(sh->modify_cmds); 489 sh->modify_cmds = NULL; 490 } 491 if (sh->tag_table) { 492 /* tags should be destroyed with flow before. */ 493 mlx5_hlist_destroy(sh->tag_table); 494 sh->tag_table = NULL; 495 } 496 if (sh->tunnel_hub) { 497 mlx5_release_tunnel_hub(sh, priv->dev_port); 498 sh->tunnel_hub = NULL; 499 } 500 mlx5_free_table_hash_list(priv); 501 if (sh->port_id_action_list) { 502 mlx5_list_destroy(sh->port_id_action_list); 503 sh->port_id_action_list = NULL; 504 } 505 if (sh->push_vlan_action_list) { 506 mlx5_list_destroy(sh->push_vlan_action_list); 507 sh->push_vlan_action_list = NULL; 508 } 509 if (sh->sample_action_list) { 510 mlx5_list_destroy(sh->sample_action_list); 511 sh->sample_action_list = NULL; 512 } 513 if (sh->dest_array_list) { 514 mlx5_list_destroy(sh->dest_array_list); 515 sh->dest_array_list = NULL; 516 } 517 return err; 518 } 519 520 /** 521 * Destroy DR related data within private structure. 522 * 523 * @param[in] priv 524 * Pointer to the private device data structure. 525 */ 526 void 527 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 528 { 529 struct mlx5_dev_ctx_shared *sh = priv->sh; 530 531 MLX5_ASSERT(sh && sh->refcnt); 532 if (sh->refcnt > 1) 533 return; 534 #ifdef HAVE_MLX5DV_DR 535 if (sh->rx_domain) { 536 mlx5_glue->dr_destroy_domain(sh->rx_domain); 537 sh->rx_domain = NULL; 538 } 539 if (sh->tx_domain) { 540 mlx5_glue->dr_destroy_domain(sh->tx_domain); 541 sh->tx_domain = NULL; 542 } 543 #ifdef HAVE_MLX5DV_DR_ESWITCH 544 if (sh->fdb_domain) { 545 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 546 sh->fdb_domain = NULL; 547 } 548 if (sh->dr_drop_action) { 549 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 550 sh->dr_drop_action = NULL; 551 } 552 #endif 553 if (sh->pop_vlan_action) { 554 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 555 sh->pop_vlan_action = NULL; 556 } 557 #endif /* HAVE_MLX5DV_DR */ 558 if (sh->default_miss_action) 559 mlx5_glue->destroy_flow_action 560 (sh->default_miss_action); 561 if (sh->encaps_decaps) { 562 mlx5_hlist_destroy(sh->encaps_decaps); 563 sh->encaps_decaps = NULL; 564 } 565 if (sh->modify_cmds) { 566 mlx5_hlist_destroy(sh->modify_cmds); 567 sh->modify_cmds = NULL; 568 } 569 if (sh->tag_table) { 570 /* tags should be destroyed with flow before. */ 571 mlx5_hlist_destroy(sh->tag_table); 572 sh->tag_table = NULL; 573 } 574 if (sh->tunnel_hub) { 575 mlx5_release_tunnel_hub(sh, priv->dev_port); 576 sh->tunnel_hub = NULL; 577 } 578 mlx5_free_table_hash_list(priv); 579 if (sh->port_id_action_list) { 580 mlx5_list_destroy(sh->port_id_action_list); 581 sh->port_id_action_list = NULL; 582 } 583 if (sh->push_vlan_action_list) { 584 mlx5_list_destroy(sh->push_vlan_action_list); 585 sh->push_vlan_action_list = NULL; 586 } 587 if (sh->sample_action_list) { 588 mlx5_list_destroy(sh->sample_action_list); 589 sh->sample_action_list = NULL; 590 } 591 if (sh->dest_array_list) { 592 mlx5_list_destroy(sh->dest_array_list); 593 sh->dest_array_list = NULL; 594 } 595 } 596 597 /** 598 * Initialize shared data between primary and secondary process. 599 * 600 * A memzone is reserved by primary process and secondary processes attach to 601 * the memzone. 602 * 603 * @return 604 * 0 on success, a negative errno value otherwise and rte_errno is set. 605 */ 606 static int 607 mlx5_init_shared_data(void) 608 { 609 const struct rte_memzone *mz; 610 int ret = 0; 611 612 rte_spinlock_lock(&mlx5_shared_data_lock); 613 if (mlx5_shared_data == NULL) { 614 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 615 /* Allocate shared memory. */ 616 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 617 sizeof(*mlx5_shared_data), 618 SOCKET_ID_ANY, 0); 619 if (mz == NULL) { 620 DRV_LOG(ERR, 621 "Cannot allocate mlx5 shared data"); 622 ret = -rte_errno; 623 goto error; 624 } 625 mlx5_shared_data = mz->addr; 626 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 627 rte_spinlock_init(&mlx5_shared_data->lock); 628 } else { 629 /* Lookup allocated shared memory. */ 630 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 631 if (mz == NULL) { 632 DRV_LOG(ERR, 633 "Cannot attach mlx5 shared data"); 634 ret = -rte_errno; 635 goto error; 636 } 637 mlx5_shared_data = mz->addr; 638 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 639 } 640 } 641 error: 642 rte_spinlock_unlock(&mlx5_shared_data_lock); 643 return ret; 644 } 645 646 /** 647 * PMD global initialization. 648 * 649 * Independent from individual device, this function initializes global 650 * per-PMD data structures distinguishing primary and secondary processes. 651 * Hence, each initialization is called once per a process. 652 * 653 * @return 654 * 0 on success, a negative errno value otherwise and rte_errno is set. 655 */ 656 static int 657 mlx5_init_once(void) 658 { 659 struct mlx5_shared_data *sd; 660 struct mlx5_local_data *ld = &mlx5_local_data; 661 int ret = 0; 662 663 if (mlx5_init_shared_data()) 664 return -rte_errno; 665 sd = mlx5_shared_data; 666 MLX5_ASSERT(sd); 667 rte_spinlock_lock(&sd->lock); 668 switch (rte_eal_process_type()) { 669 case RTE_PROC_PRIMARY: 670 if (sd->init_done) 671 break; 672 LIST_INIT(&sd->mem_event_cb_list); 673 rte_rwlock_init(&sd->mem_event_rwlock); 674 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 675 mlx5_mr_mem_event_cb, NULL); 676 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 677 mlx5_mp_os_primary_handle); 678 if (ret) 679 goto out; 680 sd->init_done = true; 681 break; 682 case RTE_PROC_SECONDARY: 683 if (ld->init_done) 684 break; 685 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 686 mlx5_mp_os_secondary_handle); 687 if (ret) 688 goto out; 689 ++sd->secondary_cnt; 690 ld->init_done = true; 691 break; 692 default: 693 break; 694 } 695 out: 696 rte_spinlock_unlock(&sd->lock); 697 return ret; 698 } 699 700 /** 701 * Create the Tx queue DevX/Verbs object. 702 * 703 * @param dev 704 * Pointer to Ethernet device. 705 * @param idx 706 * Queue index in DPDK Tx queue array. 707 * 708 * @return 709 * 0 on success, a negative errno value otherwise and rte_errno is set. 710 */ 711 static int 712 mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx) 713 { 714 struct mlx5_priv *priv = dev->data->dev_private; 715 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 716 struct mlx5_txq_ctrl *txq_ctrl = 717 container_of(txq_data, struct mlx5_txq_ctrl, txq); 718 719 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) 720 return mlx5_txq_devx_obj_new(dev, idx); 721 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 722 if (!priv->config.dv_esw_en) 723 return mlx5_txq_devx_obj_new(dev, idx); 724 #endif 725 return mlx5_txq_ibv_obj_new(dev, idx); 726 } 727 728 /** 729 * Release an Tx DevX/verbs queue object. 730 * 731 * @param txq_obj 732 * DevX/Verbs Tx queue object. 733 */ 734 static void 735 mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj) 736 { 737 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { 738 mlx5_txq_devx_obj_release(txq_obj); 739 return; 740 } 741 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 742 if (!txq_obj->txq_ctrl->priv->config.dv_esw_en) { 743 mlx5_txq_devx_obj_release(txq_obj); 744 return; 745 } 746 #endif 747 mlx5_txq_ibv_obj_release(txq_obj); 748 } 749 750 /** 751 * DV flow counter mode detect and config. 752 * 753 * @param dev 754 * Pointer to rte_eth_dev structure. 755 * 756 */ 757 static void 758 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 759 { 760 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 761 struct mlx5_priv *priv = dev->data->dev_private; 762 struct mlx5_dev_ctx_shared *sh = priv->sh; 763 bool fallback; 764 765 #ifndef HAVE_IBV_DEVX_ASYNC 766 fallback = true; 767 #else 768 fallback = false; 769 if (!priv->config.devx || !priv->config.dv_flow_en || 770 !priv->config.hca_attr.flow_counters_dump || 771 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 772 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 773 fallback = true; 774 #endif 775 if (fallback) 776 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 777 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 778 priv->config.hca_attr.flow_counters_dump, 779 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 780 /* Initialize fallback mode only on the port initializes sh. */ 781 if (sh->refcnt == 1) 782 sh->cmng.counter_fallback = fallback; 783 else if (fallback != sh->cmng.counter_fallback) 784 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 785 "with others:%d.", PORT_ID(priv), fallback); 786 #endif 787 } 788 789 /** 790 * DR flow drop action support detect. 791 * 792 * @param dev 793 * Pointer to rte_eth_dev structure. 794 * 795 */ 796 static void 797 mlx5_flow_drop_action_config(struct rte_eth_dev *dev __rte_unused) 798 { 799 #ifdef HAVE_MLX5DV_DR 800 struct mlx5_priv *priv = dev->data->dev_private; 801 802 if (!priv->config.dv_flow_en || !priv->sh->dr_drop_action) 803 return; 804 /** 805 * DR supports drop action placeholder when it is supported; 806 * otherwise, use the queue drop action. 807 */ 808 if (mlx5_flow_discover_dr_action_support(dev)) 809 priv->root_drop_action = priv->drop_queue.hrxq->action; 810 else 811 priv->root_drop_action = priv->sh->dr_drop_action; 812 #endif 813 } 814 815 static void 816 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) 817 { 818 struct mlx5_priv *priv = dev->data->dev_private; 819 void *ctx = priv->sh->ctx; 820 821 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx); 822 if (!priv->q_counters) { 823 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0); 824 struct ibv_wq *wq; 825 826 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created " 827 "by DevX - fall-back to use the kernel driver global " 828 "queue counter.", dev->data->port_id); 829 /* Create WQ by kernel and query its queue counter ID. */ 830 if (cq) { 831 wq = mlx5_glue->create_wq(ctx, 832 &(struct ibv_wq_init_attr){ 833 .wq_type = IBV_WQT_RQ, 834 .max_wr = 1, 835 .max_sge = 1, 836 .pd = priv->sh->pd, 837 .cq = cq, 838 }); 839 if (wq) { 840 /* Counter is assigned only on RDY state. */ 841 int ret = mlx5_glue->modify_wq(wq, 842 &(struct ibv_wq_attr){ 843 .attr_mask = IBV_WQ_ATTR_STATE, 844 .wq_state = IBV_WQS_RDY, 845 }); 846 847 if (ret == 0) 848 mlx5_devx_cmd_wq_query(wq, 849 &priv->counter_set_id); 850 claim_zero(mlx5_glue->destroy_wq(wq)); 851 } 852 claim_zero(mlx5_glue->destroy_cq(cq)); 853 } 854 } else { 855 priv->counter_set_id = priv->q_counters->id; 856 } 857 if (priv->counter_set_id == 0) 858 DRV_LOG(INFO, "Part of the port %d statistics will not be " 859 "available.", dev->data->port_id); 860 } 861 862 /** 863 * Check if representor spawn info match devargs. 864 * 865 * @param spawn 866 * Verbs device parameters (name, port, switch_info) to spawn. 867 * @param eth_da 868 * Device devargs to probe. 869 * 870 * @return 871 * Match result. 872 */ 873 static bool 874 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn, 875 struct rte_eth_devargs *eth_da) 876 { 877 struct mlx5_switch_info *switch_info = &spawn->info; 878 unsigned int p, f; 879 uint16_t id; 880 uint16_t repr_id = mlx5_representor_id_encode(switch_info, 881 eth_da->type); 882 883 switch (eth_da->type) { 884 case RTE_ETH_REPRESENTOR_SF: 885 if (!(spawn->info.port_name == -1 && 886 switch_info->name_type == 887 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 888 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) { 889 rte_errno = EBUSY; 890 return false; 891 } 892 break; 893 case RTE_ETH_REPRESENTOR_VF: 894 /* Allows HPF representor index -1 as exception. */ 895 if (!(spawn->info.port_name == -1 && 896 switch_info->name_type == 897 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 898 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) { 899 rte_errno = EBUSY; 900 return false; 901 } 902 break; 903 case RTE_ETH_REPRESENTOR_NONE: 904 rte_errno = EBUSY; 905 return false; 906 default: 907 rte_errno = ENOTSUP; 908 DRV_LOG(ERR, "unsupported representor type"); 909 return false; 910 } 911 /* Check representor ID: */ 912 for (p = 0; p < eth_da->nb_ports; ++p) { 913 if (spawn->pf_bond < 0) { 914 /* For non-LAG mode, allow and ignore pf. */ 915 switch_info->pf_num = eth_da->ports[p]; 916 repr_id = mlx5_representor_id_encode(switch_info, 917 eth_da->type); 918 } 919 for (f = 0; f < eth_da->nb_representor_ports; ++f) { 920 id = MLX5_REPRESENTOR_ID 921 (eth_da->ports[p], eth_da->type, 922 eth_da->representor_ports[f]); 923 if (repr_id == id) 924 return true; 925 } 926 } 927 rte_errno = EBUSY; 928 return false; 929 } 930 931 932 /** 933 * Spawn an Ethernet device from Verbs information. 934 * 935 * @param dpdk_dev 936 * Backing DPDK device. 937 * @param spawn 938 * Verbs device parameters (name, port, switch_info) to spawn. 939 * @param config 940 * Device configuration parameters. 941 * @param config 942 * Device arguments. 943 * 944 * @return 945 * A valid Ethernet device object on success, NULL otherwise and rte_errno 946 * is set. The following errors are defined: 947 * 948 * EBUSY: device is not supposed to be spawned. 949 * EEXIST: device is already spawned 950 */ 951 static struct rte_eth_dev * 952 mlx5_dev_spawn(struct rte_device *dpdk_dev, 953 struct mlx5_dev_spawn_data *spawn, 954 struct mlx5_dev_config *config, 955 struct rte_eth_devargs *eth_da) 956 { 957 const struct mlx5_switch_info *switch_info = &spawn->info; 958 struct mlx5_dev_ctx_shared *sh = NULL; 959 struct ibv_port_attr port_attr; 960 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 961 struct rte_eth_dev *eth_dev = NULL; 962 struct mlx5_priv *priv = NULL; 963 int err = 0; 964 unsigned int hw_padding = 0; 965 unsigned int mps; 966 unsigned int tunnel_en = 0; 967 unsigned int mpls_en = 0; 968 unsigned int swp = 0; 969 unsigned int mprq = 0; 970 unsigned int mprq_min_stride_size_n = 0; 971 unsigned int mprq_max_stride_size_n = 0; 972 unsigned int mprq_min_stride_num_n = 0; 973 unsigned int mprq_max_stride_num_n = 0; 974 struct rte_ether_addr mac; 975 char name[RTE_ETH_NAME_MAX_LEN]; 976 int own_domain_id = 0; 977 uint16_t port_id; 978 struct mlx5_port_info vport_info = { .query_flags = 0 }; 979 int i; 980 981 /* Determine if this port representor is supposed to be spawned. */ 982 if (switch_info->representor && dpdk_dev->devargs && 983 !mlx5_representor_match(spawn, eth_da)) 984 return NULL; 985 /* Build device name. */ 986 if (spawn->pf_bond < 0) { 987 /* Single device. */ 988 if (!switch_info->representor) 989 strlcpy(name, dpdk_dev->name, sizeof(name)); 990 else 991 err = snprintf(name, sizeof(name), "%s_representor_%s%u", 992 dpdk_dev->name, 993 switch_info->name_type == 994 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 995 switch_info->port_name); 996 } else { 997 /* Bonding device. */ 998 if (!switch_info->representor) { 999 err = snprintf(name, sizeof(name), "%s_%s", 1000 dpdk_dev->name, 1001 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1002 } else { 1003 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u", 1004 dpdk_dev->name, 1005 mlx5_os_get_dev_device_name(spawn->phys_dev), 1006 switch_info->ctrl_num, 1007 switch_info->pf_num, 1008 switch_info->name_type == 1009 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 1010 switch_info->port_name); 1011 } 1012 } 1013 if (err >= (int)sizeof(name)) 1014 DRV_LOG(WARNING, "device name overflow %s", name); 1015 /* check if the device is already spawned */ 1016 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 1017 rte_errno = EEXIST; 1018 return NULL; 1019 } 1020 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 1021 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 1022 struct mlx5_mp_id mp_id; 1023 1024 eth_dev = rte_eth_dev_attach_secondary(name); 1025 if (eth_dev == NULL) { 1026 DRV_LOG(ERR, "can not attach rte ethdev"); 1027 rte_errno = ENOMEM; 1028 return NULL; 1029 } 1030 eth_dev->device = dpdk_dev; 1031 eth_dev->dev_ops = &mlx5_dev_sec_ops; 1032 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1033 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1034 err = mlx5_proc_priv_init(eth_dev); 1035 if (err) 1036 return NULL; 1037 mlx5_mp_id_init(&mp_id, eth_dev->data->port_id); 1038 /* Receive command fd from primary process */ 1039 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 1040 if (err < 0) 1041 goto err_secondary; 1042 /* Remap UAR for Tx queues. */ 1043 err = mlx5_tx_uar_init_secondary(eth_dev, err); 1044 if (err) 1045 goto err_secondary; 1046 /* 1047 * Ethdev pointer is still required as input since 1048 * the primary device is not accessible from the 1049 * secondary process. 1050 */ 1051 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 1052 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 1053 return eth_dev; 1054 err_secondary: 1055 mlx5_dev_close(eth_dev); 1056 return NULL; 1057 } 1058 /* 1059 * Some parameters ("tx_db_nc" in particularly) are needed in 1060 * advance to create dv/verbs device context. We proceed the 1061 * devargs here to get ones, and later proceed devargs again 1062 * to override some hardware settings. 1063 */ 1064 err = mlx5_args(config, dpdk_dev->devargs); 1065 if (err) { 1066 err = rte_errno; 1067 DRV_LOG(ERR, "failed to process device arguments: %s", 1068 strerror(rte_errno)); 1069 goto error; 1070 } 1071 if (config->dv_miss_info) { 1072 if (switch_info->master || switch_info->representor) 1073 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 1074 } 1075 mlx5_malloc_mem_select(config->sys_mem_en); 1076 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 1077 if (!sh) 1078 return NULL; 1079 config->devx = sh->devx; 1080 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 1081 config->dest_tir = 1; 1082 #endif 1083 #ifdef HAVE_IBV_MLX5_MOD_SWP 1084 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 1085 #endif 1086 /* 1087 * Multi-packet send is supported by ConnectX-4 Lx PF as well 1088 * as all ConnectX-5 devices. 1089 */ 1090 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1091 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 1092 #endif 1093 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1094 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 1095 #endif 1096 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 1097 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 1098 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 1099 DRV_LOG(DEBUG, "enhanced MPW is supported"); 1100 mps = MLX5_MPW_ENHANCED; 1101 } else { 1102 DRV_LOG(DEBUG, "MPW is supported"); 1103 mps = MLX5_MPW; 1104 } 1105 } else { 1106 DRV_LOG(DEBUG, "MPW isn't supported"); 1107 mps = MLX5_MPW_DISABLED; 1108 } 1109 #ifdef HAVE_IBV_MLX5_MOD_SWP 1110 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 1111 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 1112 DRV_LOG(DEBUG, "SWP support: %u", swp); 1113 #endif 1114 config->swp = !!swp; 1115 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1116 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 1117 struct mlx5dv_striding_rq_caps mprq_caps = 1118 dv_attr.striding_rq_caps; 1119 1120 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 1121 mprq_caps.min_single_stride_log_num_of_bytes); 1122 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 1123 mprq_caps.max_single_stride_log_num_of_bytes); 1124 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 1125 mprq_caps.min_single_wqe_log_num_of_strides); 1126 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 1127 mprq_caps.max_single_wqe_log_num_of_strides); 1128 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 1129 mprq_caps.supported_qpts); 1130 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 1131 mprq = 1; 1132 mprq_min_stride_size_n = 1133 mprq_caps.min_single_stride_log_num_of_bytes; 1134 mprq_max_stride_size_n = 1135 mprq_caps.max_single_stride_log_num_of_bytes; 1136 mprq_min_stride_num_n = 1137 mprq_caps.min_single_wqe_log_num_of_strides; 1138 mprq_max_stride_num_n = 1139 mprq_caps.max_single_wqe_log_num_of_strides; 1140 } 1141 #endif 1142 /* Rx CQE compression is enabled by default. */ 1143 config->cqe_comp = 1; 1144 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1145 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 1146 tunnel_en = ((dv_attr.tunnel_offloads_caps & 1147 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 1148 (dv_attr.tunnel_offloads_caps & 1149 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && 1150 (dv_attr.tunnel_offloads_caps & 1151 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); 1152 } 1153 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 1154 tunnel_en ? "" : "not "); 1155 #else 1156 DRV_LOG(WARNING, 1157 "tunnel offloading disabled due to old OFED/rdma-core version"); 1158 #endif 1159 config->tunnel_en = tunnel_en; 1160 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 1161 mpls_en = ((dv_attr.tunnel_offloads_caps & 1162 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 1163 (dv_attr.tunnel_offloads_caps & 1164 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 1165 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 1166 mpls_en ? "" : "not "); 1167 #else 1168 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 1169 " old OFED/rdma-core version or firmware configuration"); 1170 #endif 1171 config->mpls_en = mpls_en; 1172 /* Check port status. */ 1173 err = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr); 1174 if (err) { 1175 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1176 goto error; 1177 } 1178 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1179 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1180 err = EINVAL; 1181 goto error; 1182 } 1183 if (port_attr.state != IBV_PORT_ACTIVE) 1184 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 1185 mlx5_glue->port_state_str(port_attr.state), 1186 port_attr.state); 1187 /* Allocate private eth device data. */ 1188 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1189 sizeof(*priv), 1190 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1191 if (priv == NULL) { 1192 DRV_LOG(ERR, "priv allocation failure"); 1193 err = ENOMEM; 1194 goto error; 1195 } 1196 priv->sh = sh; 1197 priv->dev_port = spawn->phys_port; 1198 priv->pci_dev = spawn->pci_dev; 1199 priv->mtu = RTE_ETHER_MTU; 1200 /* Some internal functions rely on Netlink sockets, open them now. */ 1201 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 1202 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1203 priv->representor = !!switch_info->representor; 1204 priv->master = !!switch_info->master; 1205 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1206 priv->vport_meta_tag = 0; 1207 priv->vport_meta_mask = 0; 1208 priv->pf_bond = spawn->pf_bond; 1209 1210 DRV_LOG(DEBUG, 1211 "dev_port=%u bus=%s pci=%s master=%d representor=%d pf_bond=%d\n", 1212 priv->dev_port, dpdk_dev->bus->name, 1213 priv->pci_dev ? priv->pci_dev->name : "NONE", 1214 priv->master, priv->representor, priv->pf_bond); 1215 1216 /* 1217 * If we have E-Switch we should determine the vport attributes. 1218 * E-Switch may use either source vport field or reg_c[0] metadata 1219 * register to match on vport index. The engaged part of metadata 1220 * register is defined by mask. 1221 */ 1222 if (switch_info->representor || switch_info->master) { 1223 err = mlx5_glue->devx_port_query(sh->ctx, 1224 spawn->phys_port, 1225 &vport_info); 1226 if (err) { 1227 DRV_LOG(WARNING, 1228 "can't query devx port %d on device %s", 1229 spawn->phys_port, 1230 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1231 vport_info.query_flags = 0; 1232 } 1233 } 1234 if (vport_info.query_flags & MLX5_PORT_QUERY_REG_C0) { 1235 priv->vport_meta_tag = vport_info.vport_meta_tag; 1236 priv->vport_meta_mask = vport_info.vport_meta_mask; 1237 if (!priv->vport_meta_mask) { 1238 DRV_LOG(ERR, "vport zero mask for port %d" 1239 " on bonding device %s", 1240 spawn->phys_port, 1241 mlx5_os_get_dev_device_name 1242 (spawn->phys_dev)); 1243 err = ENOTSUP; 1244 goto error; 1245 } 1246 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 1247 DRV_LOG(ERR, "invalid vport tag for port %d" 1248 " on bonding device %s", 1249 spawn->phys_port, 1250 mlx5_os_get_dev_device_name 1251 (spawn->phys_dev)); 1252 err = ENOTSUP; 1253 goto error; 1254 } 1255 } 1256 if (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) { 1257 priv->vport_id = vport_info.vport_id; 1258 } else if (spawn->pf_bond >= 0 && 1259 (switch_info->representor || switch_info->master)) { 1260 DRV_LOG(ERR, "can't deduce vport index for port %d" 1261 " on bonding device %s", 1262 spawn->phys_port, 1263 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1264 err = ENOTSUP; 1265 goto error; 1266 } else { 1267 /* 1268 * Suppose vport index in compatible way. Kernel/rdma_core 1269 * support single E-Switch per PF configurations only and 1270 * vport_id field contains the vport index for associated VF, 1271 * which is deduced from representor port name. 1272 * For example, let's have the IB device port 10, it has 1273 * attached network device eth0, which has port name attribute 1274 * pf0vf2, we can deduce the VF number as 2, and set vport index 1275 * as 3 (2+1). This assigning schema should be changed if the 1276 * multiple E-Switch instances per PF configurations or/and PCI 1277 * subfunctions are added. 1278 */ 1279 priv->vport_id = switch_info->representor ? 1280 switch_info->port_name + 1 : -1; 1281 } 1282 priv->representor_id = mlx5_representor_id_encode(switch_info, 1283 eth_da->type); 1284 /* 1285 * Look for sibling devices in order to reuse their switch domain 1286 * if any, otherwise allocate one. 1287 */ 1288 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1289 const struct mlx5_priv *opriv = 1290 rte_eth_devices[port_id].data->dev_private; 1291 1292 if (!opriv || 1293 opriv->sh != priv->sh || 1294 opriv->domain_id == 1295 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1296 continue; 1297 priv->domain_id = opriv->domain_id; 1298 DRV_LOG(DEBUG, "dev_port-%u inherit domain_id=%u\n", 1299 priv->dev_port, priv->domain_id); 1300 break; 1301 } 1302 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1303 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1304 if (err) { 1305 err = rte_errno; 1306 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1307 strerror(rte_errno)); 1308 goto error; 1309 } 1310 own_domain_id = 1; 1311 DRV_LOG(DEBUG, "dev_port-%u new domain_id=%u\n", 1312 priv->dev_port, priv->domain_id); 1313 } 1314 /* Override some values set by hardware configuration. */ 1315 mlx5_args(config, dpdk_dev->devargs); 1316 err = mlx5_dev_check_sibling_config(priv, config, dpdk_dev); 1317 if (err) 1318 goto error; 1319 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1320 IBV_DEVICE_RAW_IP_CSUM); 1321 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1322 (config->hw_csum ? "" : "not ")); 1323 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1324 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1325 DRV_LOG(DEBUG, "counters are not supported"); 1326 #endif 1327 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 1328 if (config->dv_flow_en) { 1329 DRV_LOG(WARNING, "DV flow is not supported"); 1330 config->dv_flow_en = 0; 1331 } 1332 #endif 1333 if (spawn->max_port > UINT8_MAX) { 1334 /* Verbs can't support ports larger than 255 by design. */ 1335 DRV_LOG(ERR, "can't support IB ports > UINT8_MAX"); 1336 err = EINVAL; 1337 goto error; 1338 } 1339 config->ind_table_max_size = 1340 sh->device_attr.max_rwq_indirection_table_size; 1341 /* 1342 * Remove this check once DPDK supports larger/variable 1343 * indirection tables. 1344 */ 1345 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1346 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1347 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1348 config->ind_table_max_size); 1349 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1350 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1351 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1352 (config->hw_vlan_strip ? "" : "not ")); 1353 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1354 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1355 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1356 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1357 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1358 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1359 IBV_DEVICE_PCI_WRITE_END_PADDING); 1360 #endif 1361 if (config->hw_padding && !hw_padding) { 1362 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1363 config->hw_padding = 0; 1364 } else if (config->hw_padding) { 1365 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1366 } 1367 config->tso = (sh->device_attr.max_tso > 0 && 1368 (sh->device_attr.tso_supported_qpts & 1369 (1 << IBV_QPT_RAW_PACKET))); 1370 if (config->tso) 1371 config->tso_max_payload_sz = sh->device_attr.max_tso; 1372 /* 1373 * MPW is disabled by default, while the Enhanced MPW is enabled 1374 * by default. 1375 */ 1376 if (config->mps == MLX5_ARG_UNSET) 1377 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1378 MLX5_MPW_DISABLED; 1379 else 1380 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1381 DRV_LOG(INFO, "%sMPS is %s", 1382 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1383 config->mps == MLX5_MPW ? "legacy " : "", 1384 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1385 if (config->devx) { 1386 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); 1387 if (err) { 1388 err = -err; 1389 goto error; 1390 } 1391 /* Check relax ordering support. */ 1392 if (!haswell_broadwell_cpu) { 1393 sh->cmng.relaxed_ordering_write = 1394 config->hca_attr.relaxed_ordering_write; 1395 sh->cmng.relaxed_ordering_read = 1396 config->hca_attr.relaxed_ordering_read; 1397 } else { 1398 sh->cmng.relaxed_ordering_read = 0; 1399 sh->cmng.relaxed_ordering_write = 0; 1400 } 1401 sh->rq_ts_format = config->hca_attr.rq_ts_format; 1402 sh->sq_ts_format = config->hca_attr.sq_ts_format; 1403 sh->steering_format_version = 1404 config->hca_attr.steering_format_version; 1405 sh->qp_ts_format = config->hca_attr.qp_ts_format; 1406 /* Check for LRO support. */ 1407 if (config->dest_tir && config->hca_attr.lro_cap && 1408 config->dv_flow_en) { 1409 /* TBD check tunnel lro caps. */ 1410 config->lro.supported = config->hca_attr.lro_cap; 1411 DRV_LOG(DEBUG, "Device supports LRO"); 1412 /* 1413 * If LRO timeout is not configured by application, 1414 * use the minimal supported value. 1415 */ 1416 if (!config->lro.timeout) 1417 config->lro.timeout = 1418 config->hca_attr.lro_timer_supported_periods[0]; 1419 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1420 config->lro.timeout); 1421 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1422 "required for coalescing is %d bytes", 1423 config->hca_attr.lro_min_mss_size); 1424 } 1425 #if defined(HAVE_MLX5DV_DR) && \ 1426 (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ 1427 defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) 1428 if (config->hca_attr.qos.sup && 1429 config->hca_attr.qos.flow_meter_old && 1430 config->dv_flow_en) { 1431 uint8_t reg_c_mask = 1432 config->hca_attr.qos.flow_meter_reg_c_ids; 1433 /* 1434 * Meter needs two REG_C's for color match and pre-sfx 1435 * flow match. Here get the REG_C for color match. 1436 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1437 */ 1438 reg_c_mask &= 0xfc; 1439 if (__builtin_popcount(reg_c_mask) < 1) { 1440 priv->mtr_en = 0; 1441 DRV_LOG(WARNING, "No available register for" 1442 " meter."); 1443 } else { 1444 /* 1445 * The meter color register is used by the 1446 * flow-hit feature as well. 1447 * The flow-hit feature must use REG_C_3 1448 * Prefer REG_C_3 if it is available. 1449 */ 1450 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) 1451 priv->mtr_color_reg = REG_C_3; 1452 else 1453 priv->mtr_color_reg = ffs(reg_c_mask) 1454 - 1 + REG_C_0; 1455 priv->mtr_en = 1; 1456 priv->mtr_reg_share = 1457 config->hca_attr.qos.flow_meter; 1458 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1459 priv->mtr_color_reg); 1460 } 1461 } 1462 if (config->hca_attr.qos.sup && 1463 config->hca_attr.qos.flow_meter_aso_sup) { 1464 uint32_t log_obj_size = 1465 rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1); 1466 if (log_obj_size >= 1467 config->hca_attr.qos.log_meter_aso_granularity && 1468 log_obj_size <= 1469 config->hca_attr.qos.log_meter_aso_max_alloc) 1470 sh->meter_aso_en = 1; 1471 } 1472 if (priv->mtr_en) { 1473 err = mlx5_aso_flow_mtrs_mng_init(priv->sh); 1474 if (err) { 1475 err = -err; 1476 goto error; 1477 } 1478 } 1479 if (config->hca_attr.flow.tunnel_header_0_1) 1480 sh->tunnel_header_0_1 = 1; 1481 #endif 1482 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1483 if (config->hca_attr.flow_hit_aso && 1484 priv->mtr_color_reg == REG_C_3) { 1485 sh->flow_hit_aso_en = 1; 1486 err = mlx5_flow_aso_age_mng_init(sh); 1487 if (err) { 1488 err = -err; 1489 goto error; 1490 } 1491 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1492 } 1493 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1494 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \ 1495 defined(HAVE_MLX5_DR_ACTION_ASO_CT) 1496 if (config->hca_attr.ct_offload && 1497 priv->mtr_color_reg == REG_C_3) { 1498 err = mlx5_flow_aso_ct_mng_init(sh); 1499 if (err) { 1500 err = -err; 1501 goto error; 1502 } 1503 DRV_LOG(DEBUG, "CT ASO is supported."); 1504 sh->ct_aso_en = 1; 1505 } 1506 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */ 1507 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1508 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1509 config->dv_flow_en) { 1510 priv->sampler_en = 1; 1511 DRV_LOG(DEBUG, "Sampler enabled!"); 1512 } else { 1513 priv->sampler_en = 0; 1514 if (!config->hca_attr.log_max_ft_sampler_num) 1515 DRV_LOG(WARNING, 1516 "No available register for sampler."); 1517 else 1518 DRV_LOG(DEBUG, "DV flow is not supported!"); 1519 } 1520 #endif 1521 } 1522 if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 && 1523 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) { 1524 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported"); 1525 config->cqe_comp = 0; 1526 } 1527 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 1528 (!config->devx || !config->hca_attr.mini_cqe_resp_flow_tag)) { 1529 DRV_LOG(WARNING, "Flow Tag CQE compression" 1530 " format isn't supported."); 1531 config->cqe_comp = 0; 1532 } 1533 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 1534 (!config->devx || !config->hca_attr.mini_cqe_resp_l3_l4_tag)) { 1535 DRV_LOG(WARNING, "L3/L4 Header CQE compression" 1536 " format isn't supported."); 1537 config->cqe_comp = 0; 1538 } 1539 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported", 1540 config->cqe_comp ? "" : "not "); 1541 if (config->tx_pp) { 1542 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1543 config->hca_attr.dev_freq_khz); 1544 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1545 config->hca_attr.qos.packet_pacing ? "" : "not "); 1546 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1547 config->hca_attr.cross_channel ? "" : "not "); 1548 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1549 config->hca_attr.wqe_index_ignore ? "" : "not "); 1550 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1551 config->hca_attr.non_wire_sq ? "" : "not "); 1552 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1553 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1554 config->hca_attr.log_max_static_sq_wq); 1555 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1556 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1557 if (!config->devx) { 1558 DRV_LOG(ERR, "DevX is required for packet pacing"); 1559 err = ENODEV; 1560 goto error; 1561 } 1562 if (!config->hca_attr.qos.packet_pacing) { 1563 DRV_LOG(ERR, "Packet pacing is not supported"); 1564 err = ENODEV; 1565 goto error; 1566 } 1567 if (!config->hca_attr.cross_channel) { 1568 DRV_LOG(ERR, "Cross channel operations are" 1569 " required for packet pacing"); 1570 err = ENODEV; 1571 goto error; 1572 } 1573 if (!config->hca_attr.wqe_index_ignore) { 1574 DRV_LOG(ERR, "WQE index ignore feature is" 1575 " required for packet pacing"); 1576 err = ENODEV; 1577 goto error; 1578 } 1579 if (!config->hca_attr.non_wire_sq) { 1580 DRV_LOG(ERR, "Non-wire SQ feature is" 1581 " required for packet pacing"); 1582 err = ENODEV; 1583 goto error; 1584 } 1585 if (!config->hca_attr.log_max_static_sq_wq) { 1586 DRV_LOG(ERR, "Static WQE SQ feature is" 1587 " required for packet pacing"); 1588 err = ENODEV; 1589 goto error; 1590 } 1591 if (!config->hca_attr.qos.wqe_rate_pp) { 1592 DRV_LOG(ERR, "WQE rate mode is required" 1593 " for packet pacing"); 1594 err = ENODEV; 1595 goto error; 1596 } 1597 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1598 DRV_LOG(ERR, "DevX does not provide UAR offset," 1599 " can't create queues for packet pacing"); 1600 err = ENODEV; 1601 goto error; 1602 #endif 1603 } 1604 if (config->devx) { 1605 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1606 1607 err = config->hca_attr.access_register_user ? 1608 mlx5_devx_cmd_register_read 1609 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1610 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1611 if (!err) { 1612 uint32_t ts_mode; 1613 1614 /* MTUTC register is read successfully. */ 1615 ts_mode = MLX5_GET(register_mtutc, reg, 1616 time_stamp_mode); 1617 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1618 config->rt_timestamp = 1; 1619 } else { 1620 /* Kernel does not support register reading. */ 1621 if (config->hca_attr.dev_freq_khz == 1622 (NS_PER_S / MS_PER_S)) 1623 config->rt_timestamp = 1; 1624 } 1625 } 1626 /* 1627 * If HW has bug working with tunnel packet decapsulation and 1628 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1629 * bit. Then DEV_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1630 */ 1631 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1632 config->hw_fcs_strip = 0; 1633 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1634 (config->hw_fcs_strip ? "" : "not ")); 1635 if (config->mprq.enabled && mprq) { 1636 if (config->mprq.stride_num_n && 1637 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1638 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1639 config->mprq.stride_num_n = 1640 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1641 mprq_min_stride_num_n), 1642 mprq_max_stride_num_n); 1643 DRV_LOG(WARNING, 1644 "the number of strides" 1645 " for Multi-Packet RQ is out of range," 1646 " setting default value (%u)", 1647 1 << config->mprq.stride_num_n); 1648 } 1649 if (config->mprq.stride_size_n && 1650 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1651 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1652 config->mprq.stride_size_n = 1653 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1654 mprq_min_stride_size_n), 1655 mprq_max_stride_size_n); 1656 DRV_LOG(WARNING, 1657 "the size of a stride" 1658 " for Multi-Packet RQ is out of range," 1659 " setting default value (%u)", 1660 1 << config->mprq.stride_size_n); 1661 } 1662 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1663 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1664 } else if (config->mprq.enabled && !mprq) { 1665 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1666 config->mprq.enabled = 0; 1667 } 1668 if (config->max_dump_files_num == 0) 1669 config->max_dump_files_num = 128; 1670 eth_dev = rte_eth_dev_allocate(name); 1671 if (eth_dev == NULL) { 1672 DRV_LOG(ERR, "can not allocate rte ethdev"); 1673 err = ENOMEM; 1674 goto error; 1675 } 1676 if (priv->representor) { 1677 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1678 eth_dev->data->representor_id = priv->representor_id; 1679 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1680 struct mlx5_priv *opriv = 1681 rte_eth_devices[port_id].data->dev_private; 1682 if (opriv && 1683 opriv->master && 1684 opriv->domain_id == priv->domain_id && 1685 opriv->sh == priv->sh) { 1686 eth_dev->data->backer_port_id = port_id; 1687 break; 1688 } 1689 } 1690 if (port_id >= RTE_MAX_ETHPORTS) 1691 eth_dev->data->backer_port_id = eth_dev->data->port_id; 1692 } 1693 priv->mp_id.port_id = eth_dev->data->port_id; 1694 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1695 /* 1696 * Store associated network device interface index. This index 1697 * is permanent throughout the lifetime of device. So, we may store 1698 * the ifindex here and use the cached value further. 1699 */ 1700 MLX5_ASSERT(spawn->ifindex); 1701 priv->if_index = spawn->ifindex; 1702 eth_dev->data->dev_private = priv; 1703 priv->dev_data = eth_dev->data; 1704 eth_dev->data->mac_addrs = priv->mac; 1705 eth_dev->device = dpdk_dev; 1706 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1707 /* Configure the first MAC address by default. */ 1708 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1709 DRV_LOG(ERR, 1710 "port %u cannot get MAC address, is mlx5_en" 1711 " loaded? (errno: %s)", 1712 eth_dev->data->port_id, strerror(rte_errno)); 1713 err = ENODEV; 1714 goto error; 1715 } 1716 DRV_LOG(INFO, 1717 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT, 1718 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac)); 1719 #ifdef RTE_LIBRTE_MLX5_DEBUG 1720 { 1721 char ifname[MLX5_NAMESIZE]; 1722 1723 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1724 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1725 eth_dev->data->port_id, ifname); 1726 else 1727 DRV_LOG(DEBUG, "port %u ifname is unknown", 1728 eth_dev->data->port_id); 1729 } 1730 #endif 1731 /* Get actual MTU if possible. */ 1732 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1733 if (err) { 1734 err = rte_errno; 1735 goto error; 1736 } 1737 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1738 priv->mtu); 1739 /* Initialize burst functions to prevent crashes before link-up. */ 1740 eth_dev->rx_pkt_burst = removed_rx_burst; 1741 eth_dev->tx_pkt_burst = removed_tx_burst; 1742 eth_dev->dev_ops = &mlx5_dev_ops; 1743 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1744 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1745 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1746 /* Register MAC address. */ 1747 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1748 if (config->vf && config->vf_nl_en) 1749 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1750 mlx5_ifindex(eth_dev), 1751 eth_dev->data->mac_addrs, 1752 MLX5_MAX_MAC_ADDRESSES); 1753 priv->ctrl_flows = 0; 1754 rte_spinlock_init(&priv->flow_list_lock); 1755 TAILQ_INIT(&priv->flow_meters); 1756 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR); 1757 if (!priv->mtr_profile_tbl) 1758 goto error; 1759 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1760 mlx5_glue->dv_set_context_attr(sh->ctx, 1761 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1762 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 1763 .alloc = &mlx5_alloc_verbs_buf, 1764 .free = &mlx5_free_verbs_buf, 1765 .data = sh, 1766 })); 1767 /* Bring Ethernet device up. */ 1768 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1769 eth_dev->data->port_id); 1770 mlx5_set_link_up(eth_dev); 1771 /* 1772 * Even though the interrupt handler is not installed yet, 1773 * interrupts will still trigger on the async_fd from 1774 * Verbs context returned by ibv_open_device(). 1775 */ 1776 mlx5_link_update(eth_dev, 0); 1777 #ifdef HAVE_MLX5DV_DR_ESWITCH 1778 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1779 (switch_info->representor || switch_info->master))) 1780 config->dv_esw_en = 0; 1781 #else 1782 config->dv_esw_en = 0; 1783 #endif 1784 /* Detect minimal data bytes to inline. */ 1785 mlx5_set_min_inline(spawn, config); 1786 /* Store device configuration on private structure. */ 1787 priv->config = *config; 1788 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 1789 icfg[i].release_mem_en = !!config->reclaim_mode; 1790 if (config->reclaim_mode) 1791 icfg[i].per_core_cache = 0; 1792 priv->flows[i] = mlx5_ipool_create(&icfg[i]); 1793 if (!priv->flows[i]) 1794 goto error; 1795 } 1796 /* Create context for virtual machine VLAN workaround. */ 1797 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1798 if (config->dv_flow_en) { 1799 err = mlx5_alloc_shared_dr(priv); 1800 if (err) 1801 goto error; 1802 } 1803 if (config->devx && config->dv_flow_en && config->dest_tir) { 1804 priv->obj_ops = devx_obj_ops; 1805 priv->obj_ops.drop_action_create = 1806 ibv_obj_ops.drop_action_create; 1807 priv->obj_ops.drop_action_destroy = 1808 ibv_obj_ops.drop_action_destroy; 1809 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1810 priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify; 1811 #else 1812 if (config->dv_esw_en) 1813 priv->obj_ops.txq_obj_modify = 1814 ibv_obj_ops.txq_obj_modify; 1815 #endif 1816 /* Use specific wrappers for Tx object. */ 1817 priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new; 1818 priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release; 1819 mlx5_queue_counter_id_prepare(eth_dev); 1820 priv->obj_ops.lb_dummy_queue_create = 1821 mlx5_rxq_ibv_obj_dummy_lb_create; 1822 priv->obj_ops.lb_dummy_queue_release = 1823 mlx5_rxq_ibv_obj_dummy_lb_release; 1824 } else { 1825 priv->obj_ops = ibv_obj_ops; 1826 } 1827 if (config->tx_pp && 1828 (priv->config.dv_esw_en || 1829 priv->obj_ops.txq_obj_new != mlx5_os_txq_obj_new)) { 1830 /* 1831 * HAVE_MLX5DV_DEVX_UAR_OFFSET is required to support 1832 * packet pacing and already checked above. 1833 * Hence, we should only make sure the SQs will be created 1834 * with DevX, not with Verbs. 1835 * Verbs allocates the SQ UAR on its own and it can't be shared 1836 * with Clock Queue UAR as required for Tx scheduling. 1837 */ 1838 DRV_LOG(ERR, "Verbs SQs, UAR can't be shared as required for packet pacing"); 1839 err = ENODEV; 1840 goto error; 1841 } 1842 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1843 if (!priv->drop_queue.hrxq) 1844 goto error; 1845 /* Supported Verbs flow priority number detection. */ 1846 err = mlx5_flow_discover_priorities(eth_dev); 1847 if (err < 0) { 1848 err = -err; 1849 goto error; 1850 } 1851 priv->config.flow_prio = err; 1852 if (!priv->config.dv_esw_en && 1853 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1854 DRV_LOG(WARNING, "metadata mode %u is not supported " 1855 "(no E-Switch)", priv->config.dv_xmeta_en); 1856 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1857 } 1858 mlx5_set_metadata_mask(eth_dev); 1859 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1860 !priv->sh->dv_regc0_mask) { 1861 DRV_LOG(ERR, "metadata mode %u is not supported " 1862 "(no metadata reg_c[0] is available)", 1863 priv->config.dv_xmeta_en); 1864 err = ENOTSUP; 1865 goto error; 1866 } 1867 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true, 1868 mlx5_hrxq_create_cb, 1869 mlx5_hrxq_match_cb, 1870 mlx5_hrxq_remove_cb, 1871 mlx5_hrxq_clone_cb, 1872 mlx5_hrxq_clone_free_cb); 1873 if (!priv->hrxqs) 1874 goto error; 1875 rte_rwlock_init(&priv->ind_tbls_lock); 1876 /* Query availability of metadata reg_c's. */ 1877 err = mlx5_flow_discover_mreg_c(eth_dev); 1878 if (err < 0) { 1879 err = -err; 1880 goto error; 1881 } 1882 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1883 DRV_LOG(DEBUG, 1884 "port %u extensive metadata register is not supported", 1885 eth_dev->data->port_id); 1886 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1887 DRV_LOG(ERR, "metadata mode %u is not supported " 1888 "(no metadata registers available)", 1889 priv->config.dv_xmeta_en); 1890 err = ENOTSUP; 1891 goto error; 1892 } 1893 } 1894 if (priv->config.dv_flow_en && 1895 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1896 mlx5_flow_ext_mreg_supported(eth_dev) && 1897 priv->sh->dv_regc0_mask) { 1898 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1899 MLX5_FLOW_MREG_HTABLE_SZ, 1900 false, true, eth_dev, 1901 flow_dv_mreg_create_cb, 1902 flow_dv_mreg_match_cb, 1903 flow_dv_mreg_remove_cb, 1904 flow_dv_mreg_clone_cb, 1905 flow_dv_mreg_clone_free_cb); 1906 if (!priv->mreg_cp_tbl) { 1907 err = ENOMEM; 1908 goto error; 1909 } 1910 } 1911 rte_spinlock_init(&priv->shared_act_sl); 1912 mlx5_flow_counter_mode_config(eth_dev); 1913 mlx5_flow_drop_action_config(eth_dev); 1914 if (priv->config.dv_flow_en) 1915 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1916 return eth_dev; 1917 error: 1918 if (priv) { 1919 if (priv->mreg_cp_tbl) 1920 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1921 if (priv->sh) 1922 mlx5_os_free_shared_dr(priv); 1923 if (priv->nl_socket_route >= 0) 1924 close(priv->nl_socket_route); 1925 if (priv->nl_socket_rdma >= 0) 1926 close(priv->nl_socket_rdma); 1927 if (priv->vmwa_context) 1928 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1929 if (eth_dev && priv->drop_queue.hrxq) 1930 mlx5_drop_action_destroy(eth_dev); 1931 if (priv->mtr_profile_tbl) 1932 mlx5_l3t_destroy(priv->mtr_profile_tbl); 1933 if (own_domain_id) 1934 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1935 if (priv->hrxqs) 1936 mlx5_list_destroy(priv->hrxqs); 1937 mlx5_free(priv); 1938 if (eth_dev != NULL) 1939 eth_dev->data->dev_private = NULL; 1940 } 1941 if (eth_dev != NULL) { 1942 /* mac_addrs must not be freed alone because part of 1943 * dev_private 1944 **/ 1945 eth_dev->data->mac_addrs = NULL; 1946 rte_eth_dev_release_port(eth_dev); 1947 } 1948 if (sh) 1949 mlx5_free_shared_dev_ctx(sh); 1950 MLX5_ASSERT(err > 0); 1951 rte_errno = err; 1952 return NULL; 1953 } 1954 1955 /** 1956 * Comparison callback to sort device data. 1957 * 1958 * This is meant to be used with qsort(). 1959 * 1960 * @param a[in] 1961 * Pointer to pointer to first data object. 1962 * @param b[in] 1963 * Pointer to pointer to second data object. 1964 * 1965 * @return 1966 * 0 if both objects are equal, less than 0 if the first argument is less 1967 * than the second, greater than 0 otherwise. 1968 */ 1969 static int 1970 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1971 { 1972 const struct mlx5_switch_info *si_a = 1973 &((const struct mlx5_dev_spawn_data *)a)->info; 1974 const struct mlx5_switch_info *si_b = 1975 &((const struct mlx5_dev_spawn_data *)b)->info; 1976 int ret; 1977 1978 /* Master device first. */ 1979 ret = si_b->master - si_a->master; 1980 if (ret) 1981 return ret; 1982 /* Then representor devices. */ 1983 ret = si_b->representor - si_a->representor; 1984 if (ret) 1985 return ret; 1986 /* Unidentified devices come last in no specific order. */ 1987 if (!si_a->representor) 1988 return 0; 1989 /* Order representors by name. */ 1990 return si_a->port_name - si_b->port_name; 1991 } 1992 1993 /** 1994 * Match PCI information for possible slaves of bonding device. 1995 * 1996 * @param[in] ibv_dev 1997 * Pointer to Infiniband device structure. 1998 * @param[in] pci_dev 1999 * Pointer to primary PCI address structure to match. 2000 * @param[in] nl_rdma 2001 * Netlink RDMA group socket handle. 2002 * @param[in] owner 2003 * Rerepsentor owner PF index. 2004 * @param[out] bond_info 2005 * Pointer to bonding information. 2006 * 2007 * @return 2008 * negative value if no bonding device found, otherwise 2009 * positive index of slave PF in bonding. 2010 */ 2011 static int 2012 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, 2013 const struct rte_pci_addr *pci_dev, 2014 int nl_rdma, uint16_t owner, 2015 struct mlx5_bond_info *bond_info) 2016 { 2017 char ifname[IF_NAMESIZE + 1]; 2018 unsigned int ifindex; 2019 unsigned int np, i; 2020 FILE *bond_file = NULL, *file; 2021 int pf = -1; 2022 int ret; 2023 2024 /* 2025 * Try to get master device name. If something goes 2026 * wrong suppose the lack of kernel support and no 2027 * bonding devices. 2028 */ 2029 memset(bond_info, 0, sizeof(*bond_info)); 2030 if (nl_rdma < 0) 2031 return -1; 2032 if (!strstr(ibv_dev->name, "bond")) 2033 return -1; 2034 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name); 2035 if (!np) 2036 return -1; 2037 /* 2038 * The Master device might not be on the predefined 2039 * port (not on port index 1, it is not garanted), 2040 * we have to scan all Infiniband device port and 2041 * find master. 2042 */ 2043 for (i = 1; i <= np; ++i) { 2044 /* Check whether Infiniband port is populated. */ 2045 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i); 2046 if (!ifindex) 2047 continue; 2048 if (!if_indextoname(ifindex, ifname)) 2049 continue; 2050 /* Try to read bonding slave names from sysfs. */ 2051 MKSTR(slaves, 2052 "/sys/class/net/%s/master/bonding/slaves", ifname); 2053 bond_file = fopen(slaves, "r"); 2054 if (bond_file) 2055 break; 2056 } 2057 if (!bond_file) 2058 return -1; 2059 /* Use safe format to check maximal buffer length. */ 2060 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 2061 while (fscanf(bond_file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 2062 char tmp_str[IF_NAMESIZE + 32]; 2063 struct rte_pci_addr pci_addr; 2064 struct mlx5_switch_info info; 2065 2066 /* Process slave interface names in the loop. */ 2067 snprintf(tmp_str, sizeof(tmp_str), 2068 "/sys/class/net/%s", ifname); 2069 if (mlx5_get_pci_addr(tmp_str, &pci_addr)) { 2070 DRV_LOG(WARNING, "can not get PCI address" 2071 " for netdev \"%s\"", ifname); 2072 continue; 2073 } 2074 /* Slave interface PCI address match found. */ 2075 snprintf(tmp_str, sizeof(tmp_str), 2076 "/sys/class/net/%s/phys_port_name", ifname); 2077 file = fopen(tmp_str, "rb"); 2078 if (!file) 2079 break; 2080 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 2081 if (fscanf(file, "%32s", tmp_str) == 1) 2082 mlx5_translate_port_name(tmp_str, &info); 2083 fclose(file); 2084 /* Only process PF ports. */ 2085 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY && 2086 info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 2087 continue; 2088 /* Check max bonding member. */ 2089 if (info.port_name >= MLX5_BOND_MAX_PORTS) { 2090 DRV_LOG(WARNING, "bonding index out of range, " 2091 "please increase MLX5_BOND_MAX_PORTS: %s", 2092 tmp_str); 2093 break; 2094 } 2095 /* Match PCI address, allows BDF0+pfx or BDFx+pfx. */ 2096 if (pci_dev->domain == pci_addr.domain && 2097 pci_dev->bus == pci_addr.bus && 2098 pci_dev->devid == pci_addr.devid && 2099 ((pci_dev->function == 0 && 2100 pci_dev->function + owner == pci_addr.function) || 2101 (pci_dev->function == owner && 2102 pci_addr.function == owner))) 2103 pf = info.port_name; 2104 /* Get ifindex. */ 2105 snprintf(tmp_str, sizeof(tmp_str), 2106 "/sys/class/net/%s/ifindex", ifname); 2107 file = fopen(tmp_str, "rb"); 2108 if (!file) 2109 break; 2110 ret = fscanf(file, "%u", &ifindex); 2111 fclose(file); 2112 if (ret != 1) 2113 break; 2114 /* Save bonding info. */ 2115 strncpy(bond_info->ports[info.port_name].ifname, ifname, 2116 sizeof(bond_info->ports[0].ifname)); 2117 bond_info->ports[info.port_name].pci_addr = pci_addr; 2118 bond_info->ports[info.port_name].ifindex = ifindex; 2119 bond_info->n_port++; 2120 } 2121 if (pf >= 0) { 2122 /* Get bond interface info */ 2123 ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex, 2124 bond_info->ifname); 2125 if (ret) 2126 DRV_LOG(ERR, "unable to get bond info: %s", 2127 strerror(rte_errno)); 2128 else 2129 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 2130 ifindex, bond_info->ifindex, bond_info->ifname); 2131 } 2132 return pf; 2133 } 2134 2135 static void 2136 mlx5_os_config_default(struct mlx5_dev_config *config) 2137 { 2138 memset(config, 0, sizeof(*config)); 2139 config->mps = MLX5_ARG_UNSET; 2140 config->dbnc = MLX5_ARG_UNSET; 2141 config->rx_vec_en = 1; 2142 config->txq_inline_max = MLX5_ARG_UNSET; 2143 config->txq_inline_min = MLX5_ARG_UNSET; 2144 config->txq_inline_mpw = MLX5_ARG_UNSET; 2145 config->txqs_inline = MLX5_ARG_UNSET; 2146 config->vf_nl_en = 1; 2147 config->mr_ext_memseg_en = 1; 2148 config->mr_mempool_reg_en = 1; 2149 config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2150 config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2151 config->dv_esw_en = 1; 2152 config->dv_flow_en = 1; 2153 config->decap_en = 1; 2154 config->log_hp_size = MLX5_ARG_UNSET; 2155 config->allow_duplicate_pattern = 1; 2156 } 2157 2158 /** 2159 * Register a PCI device within bonding. 2160 * 2161 * This function spawns Ethernet devices out of a given PCI device and 2162 * bonding owner PF index. 2163 * 2164 * @param[in] pci_dev 2165 * PCI device information. 2166 * @param[in] req_eth_da 2167 * Requested ethdev device argument. 2168 * @param[in] owner_id 2169 * Requested owner PF port ID within bonding device, default to 0. 2170 * 2171 * @return 2172 * 0 on success, a negative errno value otherwise and rte_errno is set. 2173 */ 2174 static int 2175 mlx5_os_pci_probe_pf(struct rte_pci_device *pci_dev, 2176 struct rte_eth_devargs *req_eth_da, 2177 uint16_t owner_id) 2178 { 2179 struct ibv_device **ibv_list; 2180 /* 2181 * Number of found IB Devices matching with requested PCI BDF. 2182 * nd != 1 means there are multiple IB devices over the same 2183 * PCI device and we have representors and master. 2184 */ 2185 unsigned int nd = 0; 2186 /* 2187 * Number of found IB device Ports. nd = 1 and np = 1..n means 2188 * we have the single multiport IB device, and there may be 2189 * representors attached to some of found ports. 2190 */ 2191 unsigned int np = 0; 2192 /* 2193 * Number of DPDK ethernet devices to Spawn - either over 2194 * multiple IB devices or multiple ports of single IB device. 2195 * Actually this is the number of iterations to spawn. 2196 */ 2197 unsigned int ns = 0; 2198 /* 2199 * Bonding device 2200 * < 0 - no bonding device (single one) 2201 * >= 0 - bonding device (value is slave PF index) 2202 */ 2203 int bd = -1; 2204 struct mlx5_dev_spawn_data *list = NULL; 2205 struct mlx5_dev_config dev_config; 2206 unsigned int dev_config_vf; 2207 struct rte_eth_devargs eth_da = *req_eth_da; 2208 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */ 2209 struct mlx5_bond_info bond_info; 2210 int ret = -1; 2211 2212 errno = 0; 2213 ibv_list = mlx5_glue->get_device_list(&ret); 2214 if (!ibv_list) { 2215 rte_errno = errno ? errno : ENOSYS; 2216 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 2217 return -rte_errno; 2218 } 2219 /* 2220 * First scan the list of all Infiniband devices to find 2221 * matching ones, gathering into the list. 2222 */ 2223 struct ibv_device *ibv_match[ret + 1]; 2224 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 2225 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 2226 unsigned int i; 2227 2228 while (ret-- > 0) { 2229 struct rte_pci_addr pci_addr; 2230 2231 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 2232 bd = mlx5_device_bond_pci_match 2233 (ibv_list[ret], &owner_pci, nl_rdma, owner_id, 2234 &bond_info); 2235 if (bd >= 0) { 2236 /* 2237 * Bonding device detected. Only one match is allowed, 2238 * the bonding is supported over multi-port IB device, 2239 * there should be no matches on representor PCI 2240 * functions or non VF LAG bonding devices with 2241 * specified address. 2242 */ 2243 if (nd) { 2244 DRV_LOG(ERR, 2245 "multiple PCI match on bonding device" 2246 "\"%s\" found", ibv_list[ret]->name); 2247 rte_errno = ENOENT; 2248 ret = -rte_errno; 2249 goto exit; 2250 } 2251 /* Amend owner pci address if owner PF ID specified. */ 2252 if (eth_da.nb_representor_ports) 2253 owner_pci.function += owner_id; 2254 DRV_LOG(INFO, "PCI information matches for" 2255 " slave %d bonding device \"%s\"", 2256 bd, ibv_list[ret]->name); 2257 ibv_match[nd++] = ibv_list[ret]; 2258 break; 2259 } else { 2260 /* Bonding device not found. */ 2261 if (mlx5_get_pci_addr(ibv_list[ret]->ibdev_path, 2262 &pci_addr)) 2263 continue; 2264 if (owner_pci.domain != pci_addr.domain || 2265 owner_pci.bus != pci_addr.bus || 2266 owner_pci.devid != pci_addr.devid || 2267 owner_pci.function != pci_addr.function) 2268 continue; 2269 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 2270 ibv_list[ret]->name); 2271 ibv_match[nd++] = ibv_list[ret]; 2272 } 2273 } 2274 ibv_match[nd] = NULL; 2275 if (!nd) { 2276 /* No device matches, just complain and bail out. */ 2277 DRV_LOG(WARNING, 2278 "no Verbs device matches PCI device " PCI_PRI_FMT "," 2279 " are kernel drivers loaded?", 2280 owner_pci.domain, owner_pci.bus, 2281 owner_pci.devid, owner_pci.function); 2282 rte_errno = ENOENT; 2283 ret = -rte_errno; 2284 goto exit; 2285 } 2286 if (nd == 1) { 2287 /* 2288 * Found single matching device may have multiple ports. 2289 * Each port may be representor, we have to check the port 2290 * number and check the representors existence. 2291 */ 2292 if (nl_rdma >= 0) 2293 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 2294 if (!np) 2295 DRV_LOG(WARNING, "can not get IB device \"%s\"" 2296 " ports number", ibv_match[0]->name); 2297 if (bd >= 0 && !np) { 2298 DRV_LOG(ERR, "can not get ports" 2299 " for bonding device"); 2300 rte_errno = ENOENT; 2301 ret = -rte_errno; 2302 goto exit; 2303 } 2304 } 2305 /* 2306 * Now we can determine the maximal 2307 * amount of devices to be spawned. 2308 */ 2309 list = mlx5_malloc(MLX5_MEM_ZERO, 2310 sizeof(struct mlx5_dev_spawn_data) * 2311 (np ? np : nd), 2312 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2313 if (!list) { 2314 DRV_LOG(ERR, "spawn data array allocation failure"); 2315 rte_errno = ENOMEM; 2316 ret = -rte_errno; 2317 goto exit; 2318 } 2319 if (bd >= 0 || np > 1) { 2320 /* 2321 * Single IB device with multiple ports found, 2322 * it may be E-Switch master device and representors. 2323 * We have to perform identification through the ports. 2324 */ 2325 MLX5_ASSERT(nl_rdma >= 0); 2326 MLX5_ASSERT(ns == 0); 2327 MLX5_ASSERT(nd == 1); 2328 MLX5_ASSERT(np); 2329 for (i = 1; i <= np; ++i) { 2330 list[ns].bond_info = &bond_info; 2331 list[ns].max_port = np; 2332 list[ns].phys_port = i; 2333 list[ns].phys_dev = ibv_match[0]; 2334 list[ns].eth_dev = NULL; 2335 list[ns].pci_dev = pci_dev; 2336 list[ns].pf_bond = bd; 2337 list[ns].ifindex = mlx5_nl_ifindex 2338 (nl_rdma, 2339 mlx5_os_get_dev_device_name 2340 (list[ns].phys_dev), i); 2341 if (!list[ns].ifindex) { 2342 /* 2343 * No network interface index found for the 2344 * specified port, it means there is no 2345 * representor on this port. It's OK, 2346 * there can be disabled ports, for example 2347 * if sriov_numvfs < sriov_totalvfs. 2348 */ 2349 continue; 2350 } 2351 ret = -1; 2352 if (nl_route >= 0) 2353 ret = mlx5_nl_switch_info 2354 (nl_route, 2355 list[ns].ifindex, 2356 &list[ns].info); 2357 if (ret || (!list[ns].info.representor && 2358 !list[ns].info.master)) { 2359 /* 2360 * We failed to recognize representors with 2361 * Netlink, let's try to perform the task 2362 * with sysfs. 2363 */ 2364 ret = mlx5_sysfs_switch_info 2365 (list[ns].ifindex, 2366 &list[ns].info); 2367 } 2368 if (!ret && bd >= 0) { 2369 switch (list[ns].info.name_type) { 2370 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 2371 if (np == 1) { 2372 /* 2373 * Force standalone bonding 2374 * device for ROCE LAG 2375 * confgiurations. 2376 */ 2377 list[ns].info.master = 0; 2378 list[ns].info.representor = 0; 2379 } 2380 if (list[ns].info.port_name == bd) 2381 ns++; 2382 break; 2383 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 2384 /* Fallthrough */ 2385 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 2386 /* Fallthrough */ 2387 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 2388 if (list[ns].info.pf_num == bd) 2389 ns++; 2390 break; 2391 default: 2392 break; 2393 } 2394 continue; 2395 } 2396 if (!ret && (list[ns].info.representor ^ 2397 list[ns].info.master)) 2398 ns++; 2399 } 2400 if (!ns) { 2401 DRV_LOG(ERR, 2402 "unable to recognize master/representors" 2403 " on the IB device with multiple ports"); 2404 rte_errno = ENOENT; 2405 ret = -rte_errno; 2406 goto exit; 2407 } 2408 } else { 2409 /* 2410 * The existence of several matching entries (nd > 1) means 2411 * port representors have been instantiated. No existing Verbs 2412 * call nor sysfs entries can tell them apart, this can only 2413 * be done through Netlink calls assuming kernel drivers are 2414 * recent enough to support them. 2415 * 2416 * In the event of identification failure through Netlink, 2417 * try again through sysfs, then: 2418 * 2419 * 1. A single IB device matches (nd == 1) with single 2420 * port (np=0/1) and is not a representor, assume 2421 * no switch support. 2422 * 2423 * 2. Otherwise no safe assumptions can be made; 2424 * complain louder and bail out. 2425 */ 2426 for (i = 0; i != nd; ++i) { 2427 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2428 list[ns].bond_info = NULL; 2429 list[ns].max_port = 1; 2430 list[ns].phys_port = 1; 2431 list[ns].phys_dev = ibv_match[i]; 2432 list[ns].eth_dev = NULL; 2433 list[ns].pci_dev = pci_dev; 2434 list[ns].pf_bond = -1; 2435 list[ns].ifindex = 0; 2436 if (nl_rdma >= 0) 2437 list[ns].ifindex = mlx5_nl_ifindex 2438 (nl_rdma, 2439 mlx5_os_get_dev_device_name 2440 (list[ns].phys_dev), 1); 2441 if (!list[ns].ifindex) { 2442 char ifname[IF_NAMESIZE]; 2443 2444 /* 2445 * Netlink failed, it may happen with old 2446 * ib_core kernel driver (before 4.16). 2447 * We can assume there is old driver because 2448 * here we are processing single ports IB 2449 * devices. Let's try sysfs to retrieve 2450 * the ifindex. The method works for 2451 * master device only. 2452 */ 2453 if (nd > 1) { 2454 /* 2455 * Multiple devices found, assume 2456 * representors, can not distinguish 2457 * master/representor and retrieve 2458 * ifindex via sysfs. 2459 */ 2460 continue; 2461 } 2462 ret = mlx5_get_ifname_sysfs 2463 (ibv_match[i]->ibdev_path, ifname); 2464 if (!ret) 2465 list[ns].ifindex = 2466 if_nametoindex(ifname); 2467 if (!list[ns].ifindex) { 2468 /* 2469 * No network interface index found 2470 * for the specified device, it means 2471 * there it is neither representor 2472 * nor master. 2473 */ 2474 continue; 2475 } 2476 } 2477 ret = -1; 2478 if (nl_route >= 0) 2479 ret = mlx5_nl_switch_info 2480 (nl_route, 2481 list[ns].ifindex, 2482 &list[ns].info); 2483 if (ret || (!list[ns].info.representor && 2484 !list[ns].info.master)) { 2485 /* 2486 * We failed to recognize representors with 2487 * Netlink, let's try to perform the task 2488 * with sysfs. 2489 */ 2490 ret = mlx5_sysfs_switch_info 2491 (list[ns].ifindex, 2492 &list[ns].info); 2493 } 2494 if (!ret && (list[ns].info.representor ^ 2495 list[ns].info.master)) { 2496 ns++; 2497 } else if ((nd == 1) && 2498 !list[ns].info.representor && 2499 !list[ns].info.master) { 2500 /* 2501 * Single IB device with 2502 * one physical port and 2503 * attached network device. 2504 * May be SRIOV is not enabled 2505 * or there is no representors. 2506 */ 2507 DRV_LOG(INFO, "no E-Switch support detected"); 2508 ns++; 2509 break; 2510 } 2511 } 2512 if (!ns) { 2513 DRV_LOG(ERR, 2514 "unable to recognize master/representors" 2515 " on the multiple IB devices"); 2516 rte_errno = ENOENT; 2517 ret = -rte_errno; 2518 goto exit; 2519 } 2520 /* 2521 * New kernels may add the switch_id attribute for the case 2522 * there is no E-Switch and we wrongly recognized the 2523 * only device as master. Override this if there is the 2524 * single device with single port and new device name 2525 * format present. 2526 */ 2527 if (nd == 1 && 2528 list[0].info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) { 2529 list[0].info.master = 0; 2530 list[0].info.representor = 0; 2531 } 2532 } 2533 MLX5_ASSERT(ns); 2534 /* 2535 * Sort list to probe devices in natural order for users convenience 2536 * (i.e. master first, then representors from lowest to highest ID). 2537 */ 2538 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2539 /* Device specific configuration. */ 2540 switch (pci_dev->id.device_id) { 2541 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2542 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2543 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2544 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2545 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2546 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2547 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: 2548 dev_config_vf = 1; 2549 break; 2550 default: 2551 dev_config_vf = 0; 2552 break; 2553 } 2554 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) { 2555 /* Set devargs default values. */ 2556 if (eth_da.nb_mh_controllers == 0) { 2557 eth_da.nb_mh_controllers = 1; 2558 eth_da.mh_controllers[0] = 0; 2559 } 2560 if (eth_da.nb_ports == 0 && ns > 0) { 2561 if (list[0].pf_bond >= 0 && list[0].info.representor) 2562 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s", 2563 pci_dev->device.devargs->args); 2564 eth_da.nb_ports = 1; 2565 eth_da.ports[0] = list[0].info.pf_num; 2566 } 2567 if (eth_da.nb_representor_ports == 0) { 2568 eth_da.nb_representor_ports = 1; 2569 eth_da.representor_ports[0] = 0; 2570 } 2571 } 2572 for (i = 0; i != ns; ++i) { 2573 uint32_t restore; 2574 2575 /* Default configuration. */ 2576 mlx5_os_config_default(&dev_config); 2577 dev_config.vf = dev_config_vf; 2578 list[i].numa_node = pci_dev->device.numa_node; 2579 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 2580 &list[i], 2581 &dev_config, 2582 ð_da); 2583 if (!list[i].eth_dev) { 2584 if (rte_errno != EBUSY && rte_errno != EEXIST) 2585 break; 2586 /* Device is disabled or already spawned. Ignore it. */ 2587 continue; 2588 } 2589 restore = list[i].eth_dev->data->dev_flags; 2590 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2591 /** 2592 * Each representor has a dedicated interrupts vector. 2593 * rte_eth_copy_pci_info() assigns PF interrupts handle to 2594 * representor eth_dev object because representor and PF 2595 * share the same PCI address. 2596 * Override representor device with a dedicated 2597 * interrupts handle here. 2598 * Representor interrupts handle is released in mlx5_dev_stop(). 2599 */ 2600 if (list[i].info.representor) { 2601 struct rte_intr_handle *intr_handle; 2602 intr_handle = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, 2603 sizeof(*intr_handle), 0, 2604 SOCKET_ID_ANY); 2605 if (!intr_handle) { 2606 DRV_LOG(ERR, 2607 "port %u failed to allocate memory for interrupt handler " 2608 "Rx interrupts will not be supported", 2609 i); 2610 rte_errno = ENOMEM; 2611 ret = -rte_errno; 2612 goto exit; 2613 } 2614 list[i].eth_dev->intr_handle = intr_handle; 2615 } 2616 /* Restore non-PCI flags cleared by the above call. */ 2617 list[i].eth_dev->data->dev_flags |= restore; 2618 rte_eth_dev_probing_finish(list[i].eth_dev); 2619 } 2620 if (i != ns) { 2621 DRV_LOG(ERR, 2622 "probe of PCI device " PCI_PRI_FMT " aborted after" 2623 " encountering an error: %s", 2624 owner_pci.domain, owner_pci.bus, 2625 owner_pci.devid, owner_pci.function, 2626 strerror(rte_errno)); 2627 ret = -rte_errno; 2628 /* Roll back. */ 2629 while (i--) { 2630 if (!list[i].eth_dev) 2631 continue; 2632 mlx5_dev_close(list[i].eth_dev); 2633 /* mac_addrs must not be freed because in dev_private */ 2634 list[i].eth_dev->data->mac_addrs = NULL; 2635 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2636 } 2637 /* Restore original error. */ 2638 rte_errno = -ret; 2639 } else { 2640 ret = 0; 2641 } 2642 exit: 2643 /* 2644 * Do the routine cleanup: 2645 * - close opened Netlink sockets 2646 * - free allocated spawn data array 2647 * - free the Infiniband device list 2648 */ 2649 if (nl_rdma >= 0) 2650 close(nl_rdma); 2651 if (nl_route >= 0) 2652 close(nl_route); 2653 if (list) 2654 mlx5_free(list); 2655 MLX5_ASSERT(ibv_list); 2656 mlx5_glue->free_device_list(ibv_list); 2657 return ret; 2658 } 2659 2660 static int 2661 mlx5_os_parse_eth_devargs(struct rte_device *dev, 2662 struct rte_eth_devargs *eth_da) 2663 { 2664 int ret = 0; 2665 2666 if (dev->devargs == NULL) 2667 return 0; 2668 memset(eth_da, 0, sizeof(*eth_da)); 2669 /* Parse representor information first from class argument. */ 2670 if (dev->devargs->cls_str) 2671 ret = rte_eth_devargs_parse(dev->devargs->cls_str, eth_da); 2672 if (ret != 0) { 2673 DRV_LOG(ERR, "failed to parse device arguments: %s", 2674 dev->devargs->cls_str); 2675 return -rte_errno; 2676 } 2677 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) { 2678 /* Parse legacy device argument */ 2679 ret = rte_eth_devargs_parse(dev->devargs->args, eth_da); 2680 if (ret) { 2681 DRV_LOG(ERR, "failed to parse device arguments: %s", 2682 dev->devargs->args); 2683 return -rte_errno; 2684 } 2685 } 2686 return 0; 2687 } 2688 2689 /** 2690 * Callback to register a PCI device. 2691 * 2692 * This function spawns Ethernet devices out of a given PCI device. 2693 * 2694 * @param[in] pci_dev 2695 * PCI device information. 2696 * 2697 * @return 2698 * 0 on success, a negative errno value otherwise and rte_errno is set. 2699 */ 2700 static int 2701 mlx5_os_pci_probe(struct rte_pci_device *pci_dev) 2702 { 2703 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2704 int ret = 0; 2705 uint16_t p; 2706 2707 ret = mlx5_os_parse_eth_devargs(&pci_dev->device, ð_da); 2708 if (ret != 0) 2709 return ret; 2710 2711 if (eth_da.nb_ports > 0) { 2712 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */ 2713 for (p = 0; p < eth_da.nb_ports; p++) { 2714 ret = mlx5_os_pci_probe_pf(pci_dev, ð_da, 2715 eth_da.ports[p]); 2716 if (ret) 2717 break; 2718 } 2719 if (ret) { 2720 DRV_LOG(ERR, "Probe of PCI device " PCI_PRI_FMT " " 2721 "aborted due to proding failure of PF %u", 2722 pci_dev->addr.domain, pci_dev->addr.bus, 2723 pci_dev->addr.devid, pci_dev->addr.function, 2724 eth_da.ports[p]); 2725 mlx5_net_remove(&pci_dev->device); 2726 } 2727 } else { 2728 ret = mlx5_os_pci_probe_pf(pci_dev, ð_da, 0); 2729 } 2730 return ret; 2731 } 2732 2733 /* Probe a single SF device on auxiliary bus, no representor support. */ 2734 static int 2735 mlx5_os_auxiliary_probe(struct rte_device *dev) 2736 { 2737 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2738 struct mlx5_dev_config config; 2739 struct mlx5_dev_spawn_data spawn = { .pf_bond = -1 }; 2740 struct rte_auxiliary_device *adev = RTE_DEV_TO_AUXILIARY(dev); 2741 struct rte_eth_dev *eth_dev; 2742 int ret = 0; 2743 2744 /* Parse ethdev devargs. */ 2745 ret = mlx5_os_parse_eth_devargs(dev, ð_da); 2746 if (ret != 0) 2747 return ret; 2748 /* Set default config data. */ 2749 mlx5_os_config_default(&config); 2750 config.sf = 1; 2751 /* Init spawn data. */ 2752 spawn.max_port = 1; 2753 spawn.phys_port = 1; 2754 spawn.phys_dev = mlx5_os_get_ibv_dev(dev); 2755 if (spawn.phys_dev == NULL) 2756 return -rte_errno; 2757 ret = mlx5_auxiliary_get_ifindex(dev->name); 2758 if (ret < 0) { 2759 DRV_LOG(ERR, "failed to get ethdev ifindex: %s", dev->name); 2760 return ret; 2761 } 2762 spawn.ifindex = ret; 2763 spawn.numa_node = dev->numa_node; 2764 /* Spawn device. */ 2765 eth_dev = mlx5_dev_spawn(dev, &spawn, &config, ð_da); 2766 if (eth_dev == NULL) 2767 return -rte_errno; 2768 /* Post create. */ 2769 eth_dev->intr_handle = &adev->intr_handle; 2770 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2771 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2772 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_RMV; 2773 eth_dev->data->numa_node = dev->numa_node; 2774 } 2775 rte_eth_dev_probing_finish(eth_dev); 2776 return 0; 2777 } 2778 2779 /** 2780 * Net class driver callback to probe a device. 2781 * 2782 * This function probe PCI bus device(s) or a single SF on auxiliary bus. 2783 * 2784 * @param[in] dev 2785 * Pointer to the generic device. 2786 * 2787 * @return 2788 * 0 on success, the function cannot fail. 2789 */ 2790 int 2791 mlx5_os_net_probe(struct rte_device *dev) 2792 { 2793 int ret; 2794 2795 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 2796 mlx5_pmd_socket_init(); 2797 ret = mlx5_init_once(); 2798 if (ret) { 2799 DRV_LOG(ERR, "unable to init PMD global data: %s", 2800 strerror(rte_errno)); 2801 return -rte_errno; 2802 } 2803 if (mlx5_dev_is_pci(dev)) 2804 return mlx5_os_pci_probe(RTE_DEV_TO_PCI(dev)); 2805 else 2806 return mlx5_os_auxiliary_probe(dev); 2807 } 2808 2809 static int 2810 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config) 2811 { 2812 char *env; 2813 int value; 2814 2815 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2816 /* Get environment variable to store. */ 2817 env = getenv(MLX5_SHUT_UP_BF); 2818 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET; 2819 if (config->dbnc == MLX5_ARG_UNSET) 2820 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1); 2821 else 2822 setenv(MLX5_SHUT_UP_BF, 2823 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1); 2824 return value; 2825 } 2826 2827 static void 2828 mlx5_restore_doorbell_mapping_env(int value) 2829 { 2830 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2831 /* Restore the original environment variable state. */ 2832 if (value == MLX5_ARG_UNSET) 2833 unsetenv(MLX5_SHUT_UP_BF); 2834 else 2835 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); 2836 } 2837 2838 /** 2839 * Extract pdn of PD object using DV API. 2840 * 2841 * @param[in] pd 2842 * Pointer to the verbs PD object. 2843 * @param[out] pdn 2844 * Pointer to the PD object number variable. 2845 * 2846 * @return 2847 * 0 on success, error value otherwise. 2848 */ 2849 int 2850 mlx5_os_get_pdn(void *pd, uint32_t *pdn) 2851 { 2852 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2853 struct mlx5dv_obj obj; 2854 struct mlx5dv_pd pd_info; 2855 int ret = 0; 2856 2857 obj.pd.in = pd; 2858 obj.pd.out = &pd_info; 2859 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 2860 if (ret) { 2861 DRV_LOG(DEBUG, "Fail to get PD object info"); 2862 return ret; 2863 } 2864 *pdn = pd_info.pdn; 2865 return 0; 2866 #else 2867 (void)pd; 2868 (void)pdn; 2869 return -ENOTSUP; 2870 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 2871 } 2872 2873 /** 2874 * Function API to open IB device. 2875 * 2876 * This function calls the Linux glue APIs to open a device. 2877 * 2878 * @param[in] spawn 2879 * Pointer to the IB device attributes (name, port, etc). 2880 * @param[out] config 2881 * Pointer to device configuration structure. 2882 * @param[out] sh 2883 * Pointer to shared context structure. 2884 * 2885 * @return 2886 * 0 on success, a positive error value otherwise. 2887 */ 2888 int 2889 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 2890 const struct mlx5_dev_config *config, 2891 struct mlx5_dev_ctx_shared *sh) 2892 { 2893 int dbmap_env; 2894 int err = 0; 2895 2896 pthread_mutex_init(&sh->txpp.mutex, NULL); 2897 /* 2898 * Configure environment variable "MLX5_BF_SHUT_UP" 2899 * before the device creation. The rdma_core library 2900 * checks the variable at device creation and 2901 * stores the result internally. 2902 */ 2903 dbmap_env = mlx5_config_doorbell_mapping_env(config); 2904 /* Try to open IB device with DV first, then usual Verbs. */ 2905 errno = 0; 2906 sh->ctx = mlx5_glue->dv_open_device(spawn->phys_dev); 2907 if (sh->ctx) { 2908 sh->devx = 1; 2909 DRV_LOG(DEBUG, "DevX is supported"); 2910 /* The device is created, no need for environment. */ 2911 mlx5_restore_doorbell_mapping_env(dbmap_env); 2912 } else { 2913 /* The environment variable is still configured. */ 2914 sh->ctx = mlx5_glue->open_device(spawn->phys_dev); 2915 err = errno ? errno : ENODEV; 2916 /* 2917 * The environment variable is not needed anymore, 2918 * all device creation attempts are completed. 2919 */ 2920 mlx5_restore_doorbell_mapping_env(dbmap_env); 2921 if (!sh->ctx) 2922 return err; 2923 DRV_LOG(DEBUG, "DevX is NOT supported"); 2924 err = 0; 2925 } 2926 if (!err && sh->ctx) { 2927 /* Hint libmlx5 to use PMD allocator for data plane resources */ 2928 mlx5_glue->dv_set_context_attr(sh->ctx, 2929 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 2930 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 2931 .alloc = &mlx5_alloc_verbs_buf, 2932 .free = &mlx5_free_verbs_buf, 2933 .data = sh, 2934 })); 2935 } 2936 return err; 2937 } 2938 2939 /** 2940 * Install shared asynchronous device events handler. 2941 * This function is implemented to support event sharing 2942 * between multiple ports of single IB device. 2943 * 2944 * @param sh 2945 * Pointer to mlx5_dev_ctx_shared object. 2946 */ 2947 void 2948 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2949 { 2950 int ret; 2951 int flags; 2952 2953 sh->intr_handle.fd = -1; 2954 flags = fcntl(((struct ibv_context *)sh->ctx)->async_fd, F_GETFL); 2955 ret = fcntl(((struct ibv_context *)sh->ctx)->async_fd, 2956 F_SETFL, flags | O_NONBLOCK); 2957 if (ret) { 2958 DRV_LOG(INFO, "failed to change file descriptor async event" 2959 " queue"); 2960 } else { 2961 sh->intr_handle.fd = ((struct ibv_context *)sh->ctx)->async_fd; 2962 sh->intr_handle.type = RTE_INTR_HANDLE_EXT; 2963 if (rte_intr_callback_register(&sh->intr_handle, 2964 mlx5_dev_interrupt_handler, sh)) { 2965 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2966 sh->intr_handle.fd = -1; 2967 } 2968 } 2969 if (sh->devx) { 2970 #ifdef HAVE_IBV_DEVX_ASYNC 2971 sh->intr_handle_devx.fd = -1; 2972 sh->devx_comp = 2973 (void *)mlx5_glue->devx_create_cmd_comp(sh->ctx); 2974 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2975 if (!devx_comp) { 2976 DRV_LOG(INFO, "failed to allocate devx_comp."); 2977 return; 2978 } 2979 flags = fcntl(devx_comp->fd, F_GETFL); 2980 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2981 if (ret) { 2982 DRV_LOG(INFO, "failed to change file descriptor" 2983 " devx comp"); 2984 return; 2985 } 2986 sh->intr_handle_devx.fd = devx_comp->fd; 2987 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT; 2988 if (rte_intr_callback_register(&sh->intr_handle_devx, 2989 mlx5_dev_interrupt_handler_devx, sh)) { 2990 DRV_LOG(INFO, "Fail to install the devx shared" 2991 " interrupt."); 2992 sh->intr_handle_devx.fd = -1; 2993 } 2994 #endif /* HAVE_IBV_DEVX_ASYNC */ 2995 } 2996 } 2997 2998 /** 2999 * Uninstall shared asynchronous device events handler. 3000 * This function is implemented to support event sharing 3001 * between multiple ports of single IB device. 3002 * 3003 * @param dev 3004 * Pointer to mlx5_dev_ctx_shared object. 3005 */ 3006 void 3007 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 3008 { 3009 if (sh->intr_handle.fd >= 0) 3010 mlx5_intr_callback_unregister(&sh->intr_handle, 3011 mlx5_dev_interrupt_handler, sh); 3012 #ifdef HAVE_IBV_DEVX_ASYNC 3013 if (sh->intr_handle_devx.fd >= 0) 3014 rte_intr_callback_unregister(&sh->intr_handle_devx, 3015 mlx5_dev_interrupt_handler_devx, sh); 3016 if (sh->devx_comp) 3017 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 3018 #endif 3019 } 3020 3021 /** 3022 * Read statistics by a named counter. 3023 * 3024 * @param[in] priv 3025 * Pointer to the private device data structure. 3026 * @param[in] ctr_name 3027 * Pointer to the name of the statistic counter to read 3028 * @param[out] stat 3029 * Pointer to read statistic value. 3030 * @return 3031 * 0 on success and stat is valud, 1 if failed to read the value 3032 * rte_errno is set. 3033 * 3034 */ 3035 int 3036 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 3037 uint64_t *stat) 3038 { 3039 int fd; 3040 3041 if (priv->sh) { 3042 if (priv->q_counters != NULL && 3043 strcmp(ctr_name, "out_of_buffer") == 0) 3044 return mlx5_devx_cmd_queue_counter_query 3045 (priv->q_counters, 0, (uint32_t *)stat); 3046 MKSTR(path, "%s/ports/%d/hw_counters/%s", 3047 priv->sh->ibdev_path, 3048 priv->dev_port, 3049 ctr_name); 3050 fd = open(path, O_RDONLY); 3051 /* 3052 * in switchdev the file location is not per port 3053 * but rather in <ibdev_path>/hw_counters/<file_name>. 3054 */ 3055 if (fd == -1) { 3056 MKSTR(path1, "%s/hw_counters/%s", 3057 priv->sh->ibdev_path, 3058 ctr_name); 3059 fd = open(path1, O_RDONLY); 3060 } 3061 if (fd != -1) { 3062 char buf[21] = {'\0'}; 3063 ssize_t n = read(fd, buf, sizeof(buf)); 3064 3065 close(fd); 3066 if (n != -1) { 3067 *stat = strtoull(buf, NULL, 10); 3068 return 0; 3069 } 3070 } 3071 } 3072 *stat = 0; 3073 return 1; 3074 } 3075 3076 /** 3077 * Set the reg_mr and dereg_mr call backs 3078 * 3079 * @param reg_mr_cb[out] 3080 * Pointer to reg_mr func 3081 * @param dereg_mr_cb[out] 3082 * Pointer to dereg_mr func 3083 * 3084 */ 3085 void 3086 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 3087 mlx5_dereg_mr_t *dereg_mr_cb) 3088 { 3089 *reg_mr_cb = mlx5_mr_verbs_ops.reg_mr; 3090 *dereg_mr_cb = mlx5_mr_verbs_ops.dereg_mr; 3091 } 3092 3093 /** 3094 * Remove a MAC address from device 3095 * 3096 * @param dev 3097 * Pointer to Ethernet device structure. 3098 * @param index 3099 * MAC address index. 3100 */ 3101 void 3102 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 3103 { 3104 struct mlx5_priv *priv = dev->data->dev_private; 3105 const int vf = priv->config.vf; 3106 3107 if (vf) 3108 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 3109 mlx5_ifindex(dev), priv->mac_own, 3110 &dev->data->mac_addrs[index], index); 3111 } 3112 3113 /** 3114 * Adds a MAC address to the device 3115 * 3116 * @param dev 3117 * Pointer to Ethernet device structure. 3118 * @param mac_addr 3119 * MAC address to register. 3120 * @param index 3121 * MAC address index. 3122 * 3123 * @return 3124 * 0 on success, a negative errno value otherwise 3125 */ 3126 int 3127 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 3128 uint32_t index) 3129 { 3130 struct mlx5_priv *priv = dev->data->dev_private; 3131 const int vf = priv->config.vf; 3132 int ret = 0; 3133 3134 if (vf) 3135 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 3136 mlx5_ifindex(dev), priv->mac_own, 3137 mac, index); 3138 return ret; 3139 } 3140 3141 /** 3142 * Modify a VF MAC address 3143 * 3144 * @param priv 3145 * Pointer to device private data. 3146 * @param mac_addr 3147 * MAC address to modify into. 3148 * @param iface_idx 3149 * Net device interface index 3150 * @param vf_index 3151 * VF index 3152 * 3153 * @return 3154 * 0 on success, a negative errno value otherwise 3155 */ 3156 int 3157 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 3158 unsigned int iface_idx, 3159 struct rte_ether_addr *mac_addr, 3160 int vf_index) 3161 { 3162 return mlx5_nl_vf_mac_addr_modify 3163 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 3164 } 3165 3166 /** 3167 * Set device promiscuous mode 3168 * 3169 * @param dev 3170 * Pointer to Ethernet device structure. 3171 * @param enable 3172 * 0 - promiscuous is disabled, otherwise - enabled 3173 * 3174 * @return 3175 * 0 on success, a negative error value otherwise 3176 */ 3177 int 3178 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 3179 { 3180 struct mlx5_priv *priv = dev->data->dev_private; 3181 3182 return mlx5_nl_promisc(priv->nl_socket_route, 3183 mlx5_ifindex(dev), !!enable); 3184 } 3185 3186 /** 3187 * Set device promiscuous mode 3188 * 3189 * @param dev 3190 * Pointer to Ethernet device structure. 3191 * @param enable 3192 * 0 - all multicase is disabled, otherwise - enabled 3193 * 3194 * @return 3195 * 0 on success, a negative error value otherwise 3196 */ 3197 int 3198 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 3199 { 3200 struct mlx5_priv *priv = dev->data->dev_private; 3201 3202 return mlx5_nl_allmulti(priv->nl_socket_route, 3203 mlx5_ifindex(dev), !!enable); 3204 } 3205 3206 /** 3207 * Flush device MAC addresses 3208 * 3209 * @param dev 3210 * Pointer to Ethernet device structure. 3211 * 3212 */ 3213 void 3214 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 3215 { 3216 struct mlx5_priv *priv = dev->data->dev_private; 3217 3218 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 3219 dev->data->mac_addrs, 3220 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 3221 } 3222