1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <ethdev_driver.h> 20 #include <ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_bus_auxiliary.h> 24 #include <rte_common.h> 25 #include <rte_kvargs.h> 26 #include <rte_rwlock.h> 27 #include <rte_spinlock.h> 28 #include <rte_string_fns.h> 29 #include <rte_alarm.h> 30 #include <rte_eal_paging.h> 31 32 #include <mlx5_glue.h> 33 #include <mlx5_devx_cmds.h> 34 #include <mlx5_common.h> 35 #include <mlx5_common_mp.h> 36 #include <mlx5_common_mr.h> 37 #include <mlx5_malloc.h> 38 39 #include "mlx5_defs.h" 40 #include "mlx5.h" 41 #include "mlx5_common_os.h" 42 #include "mlx5_utils.h" 43 #include "mlx5_rxtx.h" 44 #include "mlx5_rx.h" 45 #include "mlx5_tx.h" 46 #include "mlx5_autoconf.h" 47 #include "mlx5_mr.h" 48 #include "mlx5_flow.h" 49 #include "rte_pmd_mlx5.h" 50 #include "mlx5_verbs.h" 51 #include "mlx5_nl.h" 52 #include "mlx5_devx.h" 53 54 #ifndef HAVE_IBV_MLX5_MOD_MPW 55 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 56 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 57 #endif 58 59 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 60 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 61 #endif 62 63 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 64 65 /* Spinlock for mlx5_shared_data allocation. */ 66 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 67 68 /* Process local data for secondary processes. */ 69 static struct mlx5_local_data mlx5_local_data; 70 71 /* rte flow indexed pool configuration. */ 72 static struct mlx5_indexed_pool_config icfg[] = { 73 { 74 .size = sizeof(struct rte_flow), 75 .trunk_size = 64, 76 .need_lock = 1, 77 .release_mem_en = 0, 78 .malloc = mlx5_malloc, 79 .free = mlx5_free, 80 .per_core_cache = 0, 81 .type = "ctl_flow_ipool", 82 }, 83 { 84 .size = sizeof(struct rte_flow), 85 .trunk_size = 64, 86 .grow_trunk = 3, 87 .grow_shift = 2, 88 .need_lock = 1, 89 .release_mem_en = 0, 90 .malloc = mlx5_malloc, 91 .free = mlx5_free, 92 .per_core_cache = 1 << 14, 93 .type = "rte_flow_ipool", 94 }, 95 { 96 .size = sizeof(struct rte_flow), 97 .trunk_size = 64, 98 .grow_trunk = 3, 99 .grow_shift = 2, 100 .need_lock = 1, 101 .release_mem_en = 0, 102 .malloc = mlx5_malloc, 103 .free = mlx5_free, 104 .per_core_cache = 0, 105 .type = "mcp_flow_ipool", 106 }, 107 }; 108 109 /** 110 * Set the completion channel file descriptor interrupt as non-blocking. 111 * 112 * @param[in] rxq_obj 113 * Pointer to RQ channel object, which includes the channel fd 114 * 115 * @param[out] fd 116 * The file descriptor (representing the intetrrupt) used in this channel. 117 * 118 * @return 119 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 120 */ 121 int 122 mlx5_os_set_nonblock_channel_fd(int fd) 123 { 124 int flags; 125 126 flags = fcntl(fd, F_GETFL); 127 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 128 } 129 130 /** 131 * Get mlx5 device attributes. The glue function query_device_ex() is called 132 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 133 * device attributes from the glue out parameter. 134 * 135 * @param dev 136 * Pointer to ibv context. 137 * 138 * @param device_attr 139 * Pointer to mlx5 device attributes. 140 * 141 * @return 142 * 0 on success, non zero error number otherwise 143 */ 144 int 145 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) 146 { 147 int err; 148 struct ibv_device_attr_ex attr_ex; 149 memset(device_attr, 0, sizeof(*device_attr)); 150 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 151 if (err) 152 return err; 153 154 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 155 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 156 device_attr->max_sge = attr_ex.orig_attr.max_sge; 157 device_attr->max_cq = attr_ex.orig_attr.max_cq; 158 device_attr->max_cqe = attr_ex.orig_attr.max_cqe; 159 device_attr->max_mr = attr_ex.orig_attr.max_mr; 160 device_attr->max_pd = attr_ex.orig_attr.max_pd; 161 device_attr->max_qp = attr_ex.orig_attr.max_qp; 162 device_attr->max_srq = attr_ex.orig_attr.max_srq; 163 device_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr; 164 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 165 device_attr->max_rwq_indirection_table_size = 166 attr_ex.rss_caps.max_rwq_indirection_table_size; 167 device_attr->max_tso = attr_ex.tso_caps.max_tso; 168 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 169 170 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 171 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 172 if (err) 173 return err; 174 175 device_attr->flags = dv_attr.flags; 176 device_attr->comp_mask = dv_attr.comp_mask; 177 #ifdef HAVE_IBV_MLX5_MOD_SWP 178 device_attr->sw_parsing_offloads = 179 dv_attr.sw_parsing_caps.sw_parsing_offloads; 180 #endif 181 device_attr->min_single_stride_log_num_of_bytes = 182 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 183 device_attr->max_single_stride_log_num_of_bytes = 184 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 185 device_attr->min_single_wqe_log_num_of_strides = 186 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 187 device_attr->max_single_wqe_log_num_of_strides = 188 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 189 device_attr->stride_supported_qpts = 190 dv_attr.striding_rq_caps.supported_qpts; 191 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 192 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 193 #endif 194 strlcpy(device_attr->fw_ver, attr_ex.orig_attr.fw_ver, 195 sizeof(device_attr->fw_ver)); 196 197 return err; 198 } 199 200 /** 201 * Verbs callback to allocate a memory. This function should allocate the space 202 * according to the size provided residing inside a huge page. 203 * Please note that all allocation must respect the alignment from libmlx5 204 * (i.e. currently rte_mem_page_size()). 205 * 206 * @param[in] size 207 * The size in bytes of the memory to allocate. 208 * @param[in] data 209 * A pointer to the callback data. 210 * 211 * @return 212 * Allocated buffer, NULL otherwise and rte_errno is set. 213 */ 214 static void * 215 mlx5_alloc_verbs_buf(size_t size, void *data) 216 { 217 struct mlx5_dev_ctx_shared *sh = data; 218 void *ret; 219 size_t alignment = rte_mem_page_size(); 220 if (alignment == (size_t)-1) { 221 DRV_LOG(ERR, "Failed to get mem page size"); 222 rte_errno = ENOMEM; 223 return NULL; 224 } 225 226 MLX5_ASSERT(data != NULL); 227 ret = mlx5_malloc(0, size, alignment, sh->numa_node); 228 if (!ret && size) 229 rte_errno = ENOMEM; 230 return ret; 231 } 232 233 /** 234 * Detect misc5 support or not 235 * 236 * @param[in] priv 237 * Device private data pointer 238 */ 239 #ifdef HAVE_MLX5DV_DR 240 static void 241 __mlx5_discovery_misc5_cap(struct mlx5_priv *priv) 242 { 243 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 244 /* Dummy VxLAN matcher to detect rdma-core misc5 cap 245 * Case: IPv4--->UDP--->VxLAN--->vni 246 */ 247 void *tbl; 248 struct mlx5_flow_dv_match_params matcher_mask; 249 void *match_m; 250 void *matcher; 251 void *headers_m; 252 void *misc5_m; 253 uint32_t *tunnel_header_m; 254 struct mlx5dv_flow_matcher_attr dv_attr; 255 256 memset(&matcher_mask, 0, sizeof(matcher_mask)); 257 matcher_mask.size = sizeof(matcher_mask.buf); 258 match_m = matcher_mask.buf; 259 headers_m = MLX5_ADDR_OF(fte_match_param, match_m, outer_headers); 260 misc5_m = MLX5_ADDR_OF(fte_match_param, 261 match_m, misc_parameters_5); 262 tunnel_header_m = (uint32_t *) 263 MLX5_ADDR_OF(fte_match_set_misc5, 264 misc5_m, tunnel_header_1); 265 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff); 266 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 4); 267 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff); 268 *tunnel_header_m = 0xffffff; 269 270 tbl = mlx5_glue->dr_create_flow_tbl(priv->sh->rx_domain, 1); 271 if (!tbl) { 272 DRV_LOG(INFO, "No SW steering support"); 273 return; 274 } 275 dv_attr.type = IBV_FLOW_ATTR_NORMAL, 276 dv_attr.match_mask = (void *)&matcher_mask, 277 dv_attr.match_criteria_enable = 278 (1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT) | 279 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT); 280 dv_attr.priority = 3; 281 #ifdef HAVE_MLX5DV_DR_ESWITCH 282 void *misc2_m; 283 if (priv->config.dv_esw_en) { 284 /* FDB enabled reg_c_0 */ 285 dv_attr.match_criteria_enable |= 286 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT); 287 misc2_m = MLX5_ADDR_OF(fte_match_param, 288 match_m, misc_parameters_2); 289 MLX5_SET(fte_match_set_misc2, misc2_m, 290 metadata_reg_c_0, 0xffff); 291 } 292 #endif 293 matcher = mlx5_glue->dv_create_flow_matcher(priv->sh->ctx, 294 &dv_attr, tbl); 295 if (matcher) { 296 priv->sh->misc5_cap = 1; 297 mlx5_glue->dv_destroy_flow_matcher(matcher); 298 } 299 mlx5_glue->dr_destroy_flow_tbl(tbl); 300 #else 301 RTE_SET_USED(priv); 302 #endif 303 } 304 #endif 305 306 /** 307 * Verbs callback to free a memory. 308 * 309 * @param[in] ptr 310 * A pointer to the memory to free. 311 * @param[in] data 312 * A pointer to the callback data. 313 */ 314 static void 315 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 316 { 317 MLX5_ASSERT(data != NULL); 318 mlx5_free(ptr); 319 } 320 321 /** 322 * Initialize DR related data within private structure. 323 * Routine checks the reference counter and does actual 324 * resources creation/initialization only if counter is zero. 325 * 326 * @param[in] priv 327 * Pointer to the private device data structure. 328 * 329 * @return 330 * Zero on success, positive error code otherwise. 331 */ 332 static int 333 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 334 { 335 struct mlx5_dev_ctx_shared *sh = priv->sh; 336 char s[MLX5_NAME_SIZE] __rte_unused; 337 int err; 338 339 MLX5_ASSERT(sh && sh->refcnt); 340 if (sh->refcnt > 1) 341 return 0; 342 err = mlx5_alloc_table_hash_list(priv); 343 if (err) 344 goto error; 345 /* The resources below are only valid with DV support. */ 346 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 347 /* Init port id action list. */ 348 snprintf(s, sizeof(s), "%s_port_id_action_list", sh->ibdev_name); 349 sh->port_id_action_list = mlx5_list_create(s, sh, true, 350 flow_dv_port_id_create_cb, 351 flow_dv_port_id_match_cb, 352 flow_dv_port_id_remove_cb, 353 flow_dv_port_id_clone_cb, 354 flow_dv_port_id_clone_free_cb); 355 if (!sh->port_id_action_list) 356 goto error; 357 /* Init push vlan action list. */ 358 snprintf(s, sizeof(s), "%s_push_vlan_action_list", sh->ibdev_name); 359 sh->push_vlan_action_list = mlx5_list_create(s, sh, true, 360 flow_dv_push_vlan_create_cb, 361 flow_dv_push_vlan_match_cb, 362 flow_dv_push_vlan_remove_cb, 363 flow_dv_push_vlan_clone_cb, 364 flow_dv_push_vlan_clone_free_cb); 365 if (!sh->push_vlan_action_list) 366 goto error; 367 /* Init sample action list. */ 368 snprintf(s, sizeof(s), "%s_sample_action_list", sh->ibdev_name); 369 sh->sample_action_list = mlx5_list_create(s, sh, true, 370 flow_dv_sample_create_cb, 371 flow_dv_sample_match_cb, 372 flow_dv_sample_remove_cb, 373 flow_dv_sample_clone_cb, 374 flow_dv_sample_clone_free_cb); 375 if (!sh->sample_action_list) 376 goto error; 377 /* Init dest array action list. */ 378 snprintf(s, sizeof(s), "%s_dest_array_list", sh->ibdev_name); 379 sh->dest_array_list = mlx5_list_create(s, sh, true, 380 flow_dv_dest_array_create_cb, 381 flow_dv_dest_array_match_cb, 382 flow_dv_dest_array_remove_cb, 383 flow_dv_dest_array_clone_cb, 384 flow_dv_dest_array_clone_free_cb); 385 if (!sh->dest_array_list) 386 goto error; 387 #endif 388 #ifdef HAVE_MLX5DV_DR 389 void *domain; 390 391 /* Reference counter is zero, we should initialize structures. */ 392 domain = mlx5_glue->dr_create_domain(sh->ctx, 393 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 394 if (!domain) { 395 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 396 err = errno; 397 goto error; 398 } 399 sh->rx_domain = domain; 400 domain = mlx5_glue->dr_create_domain(sh->ctx, 401 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 402 if (!domain) { 403 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 404 err = errno; 405 goto error; 406 } 407 sh->tx_domain = domain; 408 #ifdef HAVE_MLX5DV_DR_ESWITCH 409 if (priv->config.dv_esw_en) { 410 domain = mlx5_glue->dr_create_domain 411 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 412 if (!domain) { 413 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 414 err = errno; 415 goto error; 416 } 417 sh->fdb_domain = domain; 418 } 419 /* 420 * The drop action is just some dummy placeholder in rdma-core. It 421 * does not belong to domains and has no any attributes, and, can be 422 * shared by the entire device. 423 */ 424 sh->dr_drop_action = mlx5_glue->dr_create_flow_action_drop(); 425 if (!sh->dr_drop_action) { 426 DRV_LOG(ERR, "FDB mlx5dv_dr_create_flow_action_drop"); 427 err = errno; 428 goto error; 429 } 430 #endif 431 if (!sh->tunnel_hub && priv->config.dv_miss_info) 432 err = mlx5_alloc_tunnel_hub(sh); 433 if (err) { 434 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 435 goto error; 436 } 437 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 438 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 439 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 440 if (sh->fdb_domain) 441 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 442 } 443 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 444 if (!priv->config.allow_duplicate_pattern) { 445 #ifndef HAVE_MLX5_DR_ALLOW_DUPLICATE 446 DRV_LOG(WARNING, "Disallow duplicate pattern is not supported - maybe old rdma-core version?"); 447 #endif 448 mlx5_glue->dr_allow_duplicate_rules(sh->rx_domain, 0); 449 mlx5_glue->dr_allow_duplicate_rules(sh->tx_domain, 0); 450 if (sh->fdb_domain) 451 mlx5_glue->dr_allow_duplicate_rules(sh->fdb_domain, 0); 452 } 453 454 __mlx5_discovery_misc5_cap(priv); 455 #endif /* HAVE_MLX5DV_DR */ 456 sh->default_miss_action = 457 mlx5_glue->dr_create_flow_action_default_miss(); 458 if (!sh->default_miss_action) 459 DRV_LOG(WARNING, "Default miss action is not supported."); 460 return 0; 461 error: 462 /* Rollback the created objects. */ 463 if (sh->rx_domain) { 464 mlx5_glue->dr_destroy_domain(sh->rx_domain); 465 sh->rx_domain = NULL; 466 } 467 if (sh->tx_domain) { 468 mlx5_glue->dr_destroy_domain(sh->tx_domain); 469 sh->tx_domain = NULL; 470 } 471 if (sh->fdb_domain) { 472 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 473 sh->fdb_domain = NULL; 474 } 475 if (sh->dr_drop_action) { 476 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 477 sh->dr_drop_action = NULL; 478 } 479 if (sh->pop_vlan_action) { 480 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 481 sh->pop_vlan_action = NULL; 482 } 483 if (sh->encaps_decaps) { 484 mlx5_hlist_destroy(sh->encaps_decaps); 485 sh->encaps_decaps = NULL; 486 } 487 if (sh->modify_cmds) { 488 mlx5_hlist_destroy(sh->modify_cmds); 489 sh->modify_cmds = NULL; 490 } 491 if (sh->tag_table) { 492 /* tags should be destroyed with flow before. */ 493 mlx5_hlist_destroy(sh->tag_table); 494 sh->tag_table = NULL; 495 } 496 if (sh->tunnel_hub) { 497 mlx5_release_tunnel_hub(sh, priv->dev_port); 498 sh->tunnel_hub = NULL; 499 } 500 mlx5_free_table_hash_list(priv); 501 if (sh->port_id_action_list) { 502 mlx5_list_destroy(sh->port_id_action_list); 503 sh->port_id_action_list = NULL; 504 } 505 if (sh->push_vlan_action_list) { 506 mlx5_list_destroy(sh->push_vlan_action_list); 507 sh->push_vlan_action_list = NULL; 508 } 509 if (sh->sample_action_list) { 510 mlx5_list_destroy(sh->sample_action_list); 511 sh->sample_action_list = NULL; 512 } 513 if (sh->dest_array_list) { 514 mlx5_list_destroy(sh->dest_array_list); 515 sh->dest_array_list = NULL; 516 } 517 return err; 518 } 519 520 /** 521 * Destroy DR related data within private structure. 522 * 523 * @param[in] priv 524 * Pointer to the private device data structure. 525 */ 526 void 527 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 528 { 529 struct mlx5_dev_ctx_shared *sh = priv->sh; 530 531 MLX5_ASSERT(sh && sh->refcnt); 532 if (sh->refcnt > 1) 533 return; 534 #ifdef HAVE_MLX5DV_DR 535 if (sh->rx_domain) { 536 mlx5_glue->dr_destroy_domain(sh->rx_domain); 537 sh->rx_domain = NULL; 538 } 539 if (sh->tx_domain) { 540 mlx5_glue->dr_destroy_domain(sh->tx_domain); 541 sh->tx_domain = NULL; 542 } 543 #ifdef HAVE_MLX5DV_DR_ESWITCH 544 if (sh->fdb_domain) { 545 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 546 sh->fdb_domain = NULL; 547 } 548 if (sh->dr_drop_action) { 549 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 550 sh->dr_drop_action = NULL; 551 } 552 #endif 553 if (sh->pop_vlan_action) { 554 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 555 sh->pop_vlan_action = NULL; 556 } 557 #endif /* HAVE_MLX5DV_DR */ 558 if (sh->default_miss_action) 559 mlx5_glue->destroy_flow_action 560 (sh->default_miss_action); 561 if (sh->encaps_decaps) { 562 mlx5_hlist_destroy(sh->encaps_decaps); 563 sh->encaps_decaps = NULL; 564 } 565 if (sh->modify_cmds) { 566 mlx5_hlist_destroy(sh->modify_cmds); 567 sh->modify_cmds = NULL; 568 } 569 if (sh->tag_table) { 570 /* tags should be destroyed with flow before. */ 571 mlx5_hlist_destroy(sh->tag_table); 572 sh->tag_table = NULL; 573 } 574 if (sh->tunnel_hub) { 575 mlx5_release_tunnel_hub(sh, priv->dev_port); 576 sh->tunnel_hub = NULL; 577 } 578 mlx5_free_table_hash_list(priv); 579 if (sh->port_id_action_list) { 580 mlx5_list_destroy(sh->port_id_action_list); 581 sh->port_id_action_list = NULL; 582 } 583 if (sh->push_vlan_action_list) { 584 mlx5_list_destroy(sh->push_vlan_action_list); 585 sh->push_vlan_action_list = NULL; 586 } 587 if (sh->sample_action_list) { 588 mlx5_list_destroy(sh->sample_action_list); 589 sh->sample_action_list = NULL; 590 } 591 if (sh->dest_array_list) { 592 mlx5_list_destroy(sh->dest_array_list); 593 sh->dest_array_list = NULL; 594 } 595 } 596 597 /** 598 * Initialize shared data between primary and secondary process. 599 * 600 * A memzone is reserved by primary process and secondary processes attach to 601 * the memzone. 602 * 603 * @return 604 * 0 on success, a negative errno value otherwise and rte_errno is set. 605 */ 606 static int 607 mlx5_init_shared_data(void) 608 { 609 const struct rte_memzone *mz; 610 int ret = 0; 611 612 rte_spinlock_lock(&mlx5_shared_data_lock); 613 if (mlx5_shared_data == NULL) { 614 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 615 /* Allocate shared memory. */ 616 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 617 sizeof(*mlx5_shared_data), 618 SOCKET_ID_ANY, 0); 619 if (mz == NULL) { 620 DRV_LOG(ERR, 621 "Cannot allocate mlx5 shared data"); 622 ret = -rte_errno; 623 goto error; 624 } 625 mlx5_shared_data = mz->addr; 626 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 627 rte_spinlock_init(&mlx5_shared_data->lock); 628 } else { 629 /* Lookup allocated shared memory. */ 630 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 631 if (mz == NULL) { 632 DRV_LOG(ERR, 633 "Cannot attach mlx5 shared data"); 634 ret = -rte_errno; 635 goto error; 636 } 637 mlx5_shared_data = mz->addr; 638 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 639 } 640 } 641 error: 642 rte_spinlock_unlock(&mlx5_shared_data_lock); 643 return ret; 644 } 645 646 /** 647 * PMD global initialization. 648 * 649 * Independent from individual device, this function initializes global 650 * per-PMD data structures distinguishing primary and secondary processes. 651 * Hence, each initialization is called once per a process. 652 * 653 * @return 654 * 0 on success, a negative errno value otherwise and rte_errno is set. 655 */ 656 static int 657 mlx5_init_once(void) 658 { 659 struct mlx5_shared_data *sd; 660 struct mlx5_local_data *ld = &mlx5_local_data; 661 int ret = 0; 662 663 if (mlx5_init_shared_data()) 664 return -rte_errno; 665 sd = mlx5_shared_data; 666 MLX5_ASSERT(sd); 667 rte_spinlock_lock(&sd->lock); 668 switch (rte_eal_process_type()) { 669 case RTE_PROC_PRIMARY: 670 if (sd->init_done) 671 break; 672 LIST_INIT(&sd->mem_event_cb_list); 673 rte_rwlock_init(&sd->mem_event_rwlock); 674 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 675 mlx5_mr_mem_event_cb, NULL); 676 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 677 mlx5_mp_os_primary_handle); 678 if (ret) 679 goto out; 680 sd->init_done = true; 681 break; 682 case RTE_PROC_SECONDARY: 683 if (ld->init_done) 684 break; 685 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 686 mlx5_mp_os_secondary_handle); 687 if (ret) 688 goto out; 689 ++sd->secondary_cnt; 690 ld->init_done = true; 691 break; 692 default: 693 break; 694 } 695 out: 696 rte_spinlock_unlock(&sd->lock); 697 return ret; 698 } 699 700 /** 701 * Create the Tx queue DevX/Verbs object. 702 * 703 * @param dev 704 * Pointer to Ethernet device. 705 * @param idx 706 * Queue index in DPDK Tx queue array. 707 * 708 * @return 709 * 0 on success, a negative errno value otherwise and rte_errno is set. 710 */ 711 static int 712 mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx) 713 { 714 struct mlx5_priv *priv = dev->data->dev_private; 715 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 716 struct mlx5_txq_ctrl *txq_ctrl = 717 container_of(txq_data, struct mlx5_txq_ctrl, txq); 718 719 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) 720 return mlx5_txq_devx_obj_new(dev, idx); 721 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 722 if (!priv->config.dv_esw_en) 723 return mlx5_txq_devx_obj_new(dev, idx); 724 #endif 725 return mlx5_txq_ibv_obj_new(dev, idx); 726 } 727 728 /** 729 * Release an Tx DevX/verbs queue object. 730 * 731 * @param txq_obj 732 * DevX/Verbs Tx queue object. 733 */ 734 static void 735 mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj) 736 { 737 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { 738 mlx5_txq_devx_obj_release(txq_obj); 739 return; 740 } 741 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 742 if (!txq_obj->txq_ctrl->priv->config.dv_esw_en) { 743 mlx5_txq_devx_obj_release(txq_obj); 744 return; 745 } 746 #endif 747 mlx5_txq_ibv_obj_release(txq_obj); 748 } 749 750 /** 751 * DV flow counter mode detect and config. 752 * 753 * @param dev 754 * Pointer to rte_eth_dev structure. 755 * 756 */ 757 static void 758 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 759 { 760 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 761 struct mlx5_priv *priv = dev->data->dev_private; 762 struct mlx5_dev_ctx_shared *sh = priv->sh; 763 bool fallback; 764 765 #ifndef HAVE_IBV_DEVX_ASYNC 766 fallback = true; 767 #else 768 fallback = false; 769 if (!priv->config.devx || !priv->config.dv_flow_en || 770 !priv->config.hca_attr.flow_counters_dump || 771 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 772 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 773 fallback = true; 774 #endif 775 if (fallback) 776 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 777 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 778 priv->config.hca_attr.flow_counters_dump, 779 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 780 /* Initialize fallback mode only on the port initializes sh. */ 781 if (sh->refcnt == 1) 782 sh->cmng.counter_fallback = fallback; 783 else if (fallback != sh->cmng.counter_fallback) 784 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 785 "with others:%d.", PORT_ID(priv), fallback); 786 #endif 787 } 788 789 static void 790 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) 791 { 792 struct mlx5_priv *priv = dev->data->dev_private; 793 void *ctx = priv->sh->ctx; 794 795 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx); 796 if (!priv->q_counters) { 797 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0); 798 struct ibv_wq *wq; 799 800 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created " 801 "by DevX - fall-back to use the kernel driver global " 802 "queue counter.", dev->data->port_id); 803 /* Create WQ by kernel and query its queue counter ID. */ 804 if (cq) { 805 wq = mlx5_glue->create_wq(ctx, 806 &(struct ibv_wq_init_attr){ 807 .wq_type = IBV_WQT_RQ, 808 .max_wr = 1, 809 .max_sge = 1, 810 .pd = priv->sh->pd, 811 .cq = cq, 812 }); 813 if (wq) { 814 /* Counter is assigned only on RDY state. */ 815 int ret = mlx5_glue->modify_wq(wq, 816 &(struct ibv_wq_attr){ 817 .attr_mask = IBV_WQ_ATTR_STATE, 818 .wq_state = IBV_WQS_RDY, 819 }); 820 821 if (ret == 0) 822 mlx5_devx_cmd_wq_query(wq, 823 &priv->counter_set_id); 824 claim_zero(mlx5_glue->destroy_wq(wq)); 825 } 826 claim_zero(mlx5_glue->destroy_cq(cq)); 827 } 828 } else { 829 priv->counter_set_id = priv->q_counters->id; 830 } 831 if (priv->counter_set_id == 0) 832 DRV_LOG(INFO, "Part of the port %d statistics will not be " 833 "available.", dev->data->port_id); 834 } 835 836 /** 837 * Check if representor spawn info match devargs. 838 * 839 * @param spawn 840 * Verbs device parameters (name, port, switch_info) to spawn. 841 * @param eth_da 842 * Device devargs to probe. 843 * 844 * @return 845 * Match result. 846 */ 847 static bool 848 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn, 849 struct rte_eth_devargs *eth_da) 850 { 851 struct mlx5_switch_info *switch_info = &spawn->info; 852 unsigned int p, f; 853 uint16_t id; 854 uint16_t repr_id = mlx5_representor_id_encode(switch_info, 855 eth_da->type); 856 857 switch (eth_da->type) { 858 case RTE_ETH_REPRESENTOR_SF: 859 if (!(spawn->info.port_name == -1 && 860 switch_info->name_type == 861 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 862 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) { 863 rte_errno = EBUSY; 864 return false; 865 } 866 break; 867 case RTE_ETH_REPRESENTOR_VF: 868 /* Allows HPF representor index -1 as exception. */ 869 if (!(spawn->info.port_name == -1 && 870 switch_info->name_type == 871 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 872 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) { 873 rte_errno = EBUSY; 874 return false; 875 } 876 break; 877 case RTE_ETH_REPRESENTOR_NONE: 878 rte_errno = EBUSY; 879 return false; 880 default: 881 rte_errno = ENOTSUP; 882 DRV_LOG(ERR, "unsupported representor type"); 883 return false; 884 } 885 /* Check representor ID: */ 886 for (p = 0; p < eth_da->nb_ports; ++p) { 887 if (spawn->pf_bond < 0) { 888 /* For non-LAG mode, allow and ignore pf. */ 889 switch_info->pf_num = eth_da->ports[p]; 890 repr_id = mlx5_representor_id_encode(switch_info, 891 eth_da->type); 892 } 893 for (f = 0; f < eth_da->nb_representor_ports; ++f) { 894 id = MLX5_REPRESENTOR_ID 895 (eth_da->ports[p], eth_da->type, 896 eth_da->representor_ports[f]); 897 if (repr_id == id) 898 return true; 899 } 900 } 901 rte_errno = EBUSY; 902 return false; 903 } 904 905 906 /** 907 * Spawn an Ethernet device from Verbs information. 908 * 909 * @param dpdk_dev 910 * Backing DPDK device. 911 * @param spawn 912 * Verbs device parameters (name, port, switch_info) to spawn. 913 * @param config 914 * Device configuration parameters. 915 * @param config 916 * Device arguments. 917 * 918 * @return 919 * A valid Ethernet device object on success, NULL otherwise and rte_errno 920 * is set. The following errors are defined: 921 * 922 * EBUSY: device is not supposed to be spawned. 923 * EEXIST: device is already spawned 924 */ 925 static struct rte_eth_dev * 926 mlx5_dev_spawn(struct rte_device *dpdk_dev, 927 struct mlx5_dev_spawn_data *spawn, 928 struct mlx5_dev_config *config, 929 struct rte_eth_devargs *eth_da) 930 { 931 const struct mlx5_switch_info *switch_info = &spawn->info; 932 struct mlx5_dev_ctx_shared *sh = NULL; 933 struct ibv_port_attr port_attr; 934 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 935 struct rte_eth_dev *eth_dev = NULL; 936 struct mlx5_priv *priv = NULL; 937 int err = 0; 938 unsigned int hw_padding = 0; 939 unsigned int mps; 940 unsigned int tunnel_en = 0; 941 unsigned int mpls_en = 0; 942 unsigned int swp = 0; 943 unsigned int mprq = 0; 944 unsigned int mprq_min_stride_size_n = 0; 945 unsigned int mprq_max_stride_size_n = 0; 946 unsigned int mprq_min_stride_num_n = 0; 947 unsigned int mprq_max_stride_num_n = 0; 948 struct rte_ether_addr mac; 949 char name[RTE_ETH_NAME_MAX_LEN]; 950 int own_domain_id = 0; 951 uint16_t port_id; 952 struct mlx5_port_info vport_info = { .query_flags = 0 }; 953 int i; 954 955 /* Determine if this port representor is supposed to be spawned. */ 956 if (switch_info->representor && dpdk_dev->devargs && 957 !mlx5_representor_match(spawn, eth_da)) 958 return NULL; 959 /* Build device name. */ 960 if (spawn->pf_bond < 0) { 961 /* Single device. */ 962 if (!switch_info->representor) 963 strlcpy(name, dpdk_dev->name, sizeof(name)); 964 else 965 err = snprintf(name, sizeof(name), "%s_representor_%s%u", 966 dpdk_dev->name, 967 switch_info->name_type == 968 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 969 switch_info->port_name); 970 } else { 971 /* Bonding device. */ 972 if (!switch_info->representor) { 973 err = snprintf(name, sizeof(name), "%s_%s", 974 dpdk_dev->name, 975 mlx5_os_get_dev_device_name(spawn->phys_dev)); 976 } else { 977 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u", 978 dpdk_dev->name, 979 mlx5_os_get_dev_device_name(spawn->phys_dev), 980 switch_info->ctrl_num, 981 switch_info->pf_num, 982 switch_info->name_type == 983 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 984 switch_info->port_name); 985 } 986 } 987 if (err >= (int)sizeof(name)) 988 DRV_LOG(WARNING, "device name overflow %s", name); 989 /* check if the device is already spawned */ 990 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 991 rte_errno = EEXIST; 992 return NULL; 993 } 994 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 995 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 996 struct mlx5_mp_id mp_id; 997 998 eth_dev = rte_eth_dev_attach_secondary(name); 999 if (eth_dev == NULL) { 1000 DRV_LOG(ERR, "can not attach rte ethdev"); 1001 rte_errno = ENOMEM; 1002 return NULL; 1003 } 1004 eth_dev->device = dpdk_dev; 1005 eth_dev->dev_ops = &mlx5_dev_sec_ops; 1006 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1007 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1008 err = mlx5_proc_priv_init(eth_dev); 1009 if (err) 1010 return NULL; 1011 mp_id.port_id = eth_dev->data->port_id; 1012 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1013 /* Receive command fd from primary process */ 1014 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 1015 if (err < 0) 1016 goto err_secondary; 1017 /* Remap UAR for Tx queues. */ 1018 err = mlx5_tx_uar_init_secondary(eth_dev, err); 1019 if (err) 1020 goto err_secondary; 1021 /* 1022 * Ethdev pointer is still required as input since 1023 * the primary device is not accessible from the 1024 * secondary process. 1025 */ 1026 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 1027 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 1028 return eth_dev; 1029 err_secondary: 1030 mlx5_dev_close(eth_dev); 1031 return NULL; 1032 } 1033 /* 1034 * Some parameters ("tx_db_nc" in particularly) are needed in 1035 * advance to create dv/verbs device context. We proceed the 1036 * devargs here to get ones, and later proceed devargs again 1037 * to override some hardware settings. 1038 */ 1039 err = mlx5_args(config, dpdk_dev->devargs); 1040 if (err) { 1041 err = rte_errno; 1042 DRV_LOG(ERR, "failed to process device arguments: %s", 1043 strerror(rte_errno)); 1044 goto error; 1045 } 1046 if (config->dv_miss_info) { 1047 if (switch_info->master || switch_info->representor) 1048 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 1049 } 1050 mlx5_malloc_mem_select(config->sys_mem_en); 1051 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 1052 if (!sh) 1053 return NULL; 1054 config->devx = sh->devx; 1055 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 1056 config->dest_tir = 1; 1057 #endif 1058 #ifdef HAVE_IBV_MLX5_MOD_SWP 1059 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 1060 #endif 1061 /* 1062 * Multi-packet send is supported by ConnectX-4 Lx PF as well 1063 * as all ConnectX-5 devices. 1064 */ 1065 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1066 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 1067 #endif 1068 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1069 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 1070 #endif 1071 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 1072 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 1073 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 1074 DRV_LOG(DEBUG, "enhanced MPW is supported"); 1075 mps = MLX5_MPW_ENHANCED; 1076 } else { 1077 DRV_LOG(DEBUG, "MPW is supported"); 1078 mps = MLX5_MPW; 1079 } 1080 } else { 1081 DRV_LOG(DEBUG, "MPW isn't supported"); 1082 mps = MLX5_MPW_DISABLED; 1083 } 1084 #ifdef HAVE_IBV_MLX5_MOD_SWP 1085 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 1086 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 1087 DRV_LOG(DEBUG, "SWP support: %u", swp); 1088 #endif 1089 config->swp = !!swp; 1090 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1091 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 1092 struct mlx5dv_striding_rq_caps mprq_caps = 1093 dv_attr.striding_rq_caps; 1094 1095 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 1096 mprq_caps.min_single_stride_log_num_of_bytes); 1097 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 1098 mprq_caps.max_single_stride_log_num_of_bytes); 1099 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 1100 mprq_caps.min_single_wqe_log_num_of_strides); 1101 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 1102 mprq_caps.max_single_wqe_log_num_of_strides); 1103 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 1104 mprq_caps.supported_qpts); 1105 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 1106 mprq = 1; 1107 mprq_min_stride_size_n = 1108 mprq_caps.min_single_stride_log_num_of_bytes; 1109 mprq_max_stride_size_n = 1110 mprq_caps.max_single_stride_log_num_of_bytes; 1111 mprq_min_stride_num_n = 1112 mprq_caps.min_single_wqe_log_num_of_strides; 1113 mprq_max_stride_num_n = 1114 mprq_caps.max_single_wqe_log_num_of_strides; 1115 } 1116 #endif 1117 /* Rx CQE compression is enabled by default. */ 1118 config->cqe_comp = 1; 1119 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1120 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 1121 tunnel_en = ((dv_attr.tunnel_offloads_caps & 1122 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 1123 (dv_attr.tunnel_offloads_caps & 1124 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && 1125 (dv_attr.tunnel_offloads_caps & 1126 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); 1127 } 1128 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 1129 tunnel_en ? "" : "not "); 1130 #else 1131 DRV_LOG(WARNING, 1132 "tunnel offloading disabled due to old OFED/rdma-core version"); 1133 #endif 1134 config->tunnel_en = tunnel_en; 1135 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 1136 mpls_en = ((dv_attr.tunnel_offloads_caps & 1137 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 1138 (dv_attr.tunnel_offloads_caps & 1139 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 1140 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 1141 mpls_en ? "" : "not "); 1142 #else 1143 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 1144 " old OFED/rdma-core version or firmware configuration"); 1145 #endif 1146 config->mpls_en = mpls_en; 1147 /* Check port status. */ 1148 err = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr); 1149 if (err) { 1150 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1151 goto error; 1152 } 1153 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1154 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1155 err = EINVAL; 1156 goto error; 1157 } 1158 if (port_attr.state != IBV_PORT_ACTIVE) 1159 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 1160 mlx5_glue->port_state_str(port_attr.state), 1161 port_attr.state); 1162 /* Allocate private eth device data. */ 1163 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1164 sizeof(*priv), 1165 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1166 if (priv == NULL) { 1167 DRV_LOG(ERR, "priv allocation failure"); 1168 err = ENOMEM; 1169 goto error; 1170 } 1171 priv->sh = sh; 1172 priv->dev_port = spawn->phys_port; 1173 priv->pci_dev = spawn->pci_dev; 1174 priv->mtu = RTE_ETHER_MTU; 1175 /* Some internal functions rely on Netlink sockets, open them now. */ 1176 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 1177 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1178 priv->representor = !!switch_info->representor; 1179 priv->master = !!switch_info->master; 1180 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1181 priv->vport_meta_tag = 0; 1182 priv->vport_meta_mask = 0; 1183 priv->pf_bond = spawn->pf_bond; 1184 /* 1185 * If we have E-Switch we should determine the vport attributes. 1186 * E-Switch may use either source vport field or reg_c[0] metadata 1187 * register to match on vport index. The engaged part of metadata 1188 * register is defined by mask. 1189 */ 1190 if (switch_info->representor || switch_info->master) { 1191 err = mlx5_glue->devx_port_query(sh->ctx, 1192 spawn->phys_port, 1193 &vport_info); 1194 if (err) { 1195 DRV_LOG(WARNING, 1196 "can't query devx port %d on device %s", 1197 spawn->phys_port, 1198 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1199 vport_info.query_flags = 0; 1200 } 1201 } 1202 if (vport_info.query_flags & MLX5_PORT_QUERY_REG_C0) { 1203 priv->vport_meta_tag = vport_info.vport_meta_tag; 1204 priv->vport_meta_mask = vport_info.vport_meta_mask; 1205 if (!priv->vport_meta_mask) { 1206 DRV_LOG(ERR, "vport zero mask for port %d" 1207 " on bonding device %s", 1208 spawn->phys_port, 1209 mlx5_os_get_dev_device_name 1210 (spawn->phys_dev)); 1211 err = ENOTSUP; 1212 goto error; 1213 } 1214 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 1215 DRV_LOG(ERR, "invalid vport tag for port %d" 1216 " on bonding device %s", 1217 spawn->phys_port, 1218 mlx5_os_get_dev_device_name 1219 (spawn->phys_dev)); 1220 err = ENOTSUP; 1221 goto error; 1222 } 1223 } 1224 if (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) { 1225 priv->vport_id = vport_info.vport_id; 1226 } else if (spawn->pf_bond >= 0 && 1227 (switch_info->representor || switch_info->master)) { 1228 DRV_LOG(ERR, "can't deduce vport index for port %d" 1229 " on bonding device %s", 1230 spawn->phys_port, 1231 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1232 err = ENOTSUP; 1233 goto error; 1234 } else { 1235 /* 1236 * Suppose vport index in compatible way. Kernel/rdma_core 1237 * support single E-Switch per PF configurations only and 1238 * vport_id field contains the vport index for associated VF, 1239 * which is deduced from representor port name. 1240 * For example, let's have the IB device port 10, it has 1241 * attached network device eth0, which has port name attribute 1242 * pf0vf2, we can deduce the VF number as 2, and set vport index 1243 * as 3 (2+1). This assigning schema should be changed if the 1244 * multiple E-Switch instances per PF configurations or/and PCI 1245 * subfunctions are added. 1246 */ 1247 priv->vport_id = switch_info->representor ? 1248 switch_info->port_name + 1 : -1; 1249 } 1250 priv->representor_id = mlx5_representor_id_encode(switch_info, 1251 eth_da->type); 1252 /* 1253 * Look for sibling devices in order to reuse their switch domain 1254 * if any, otherwise allocate one. 1255 */ 1256 MLX5_ETH_FOREACH_DEV(port_id, NULL) { 1257 const struct mlx5_priv *opriv = 1258 rte_eth_devices[port_id].data->dev_private; 1259 1260 if (!opriv || 1261 opriv->sh != priv->sh || 1262 opriv->domain_id == 1263 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1264 continue; 1265 priv->domain_id = opriv->domain_id; 1266 break; 1267 } 1268 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1269 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1270 if (err) { 1271 err = rte_errno; 1272 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1273 strerror(rte_errno)); 1274 goto error; 1275 } 1276 own_domain_id = 1; 1277 } 1278 /* Override some values set by hardware configuration. */ 1279 mlx5_args(config, dpdk_dev->devargs); 1280 err = mlx5_dev_check_sibling_config(priv, config); 1281 if (err) 1282 goto error; 1283 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1284 IBV_DEVICE_RAW_IP_CSUM); 1285 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1286 (config->hw_csum ? "" : "not ")); 1287 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1288 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1289 DRV_LOG(DEBUG, "counters are not supported"); 1290 #endif 1291 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 1292 if (config->dv_flow_en) { 1293 DRV_LOG(WARNING, "DV flow is not supported"); 1294 config->dv_flow_en = 0; 1295 } 1296 #endif 1297 if (spawn->max_port > UINT8_MAX) { 1298 /* Verbs can't support ports larger than 255 by design. */ 1299 DRV_LOG(ERR, "can't support IB ports > UINT8_MAX"); 1300 err = EINVAL; 1301 goto error; 1302 } 1303 config->ind_table_max_size = 1304 sh->device_attr.max_rwq_indirection_table_size; 1305 /* 1306 * Remove this check once DPDK supports larger/variable 1307 * indirection tables. 1308 */ 1309 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1310 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1311 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1312 config->ind_table_max_size); 1313 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1314 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1315 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1316 (config->hw_vlan_strip ? "" : "not ")); 1317 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1318 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1319 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1320 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1321 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1322 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1323 IBV_DEVICE_PCI_WRITE_END_PADDING); 1324 #endif 1325 if (config->hw_padding && !hw_padding) { 1326 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1327 config->hw_padding = 0; 1328 } else if (config->hw_padding) { 1329 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1330 } 1331 config->tso = (sh->device_attr.max_tso > 0 && 1332 (sh->device_attr.tso_supported_qpts & 1333 (1 << IBV_QPT_RAW_PACKET))); 1334 if (config->tso) 1335 config->tso_max_payload_sz = sh->device_attr.max_tso; 1336 /* 1337 * MPW is disabled by default, while the Enhanced MPW is enabled 1338 * by default. 1339 */ 1340 if (config->mps == MLX5_ARG_UNSET) 1341 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1342 MLX5_MPW_DISABLED; 1343 else 1344 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1345 DRV_LOG(INFO, "%sMPS is %s", 1346 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1347 config->mps == MLX5_MPW ? "legacy " : "", 1348 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1349 if (config->devx) { 1350 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); 1351 if (err) { 1352 err = -err; 1353 goto error; 1354 } 1355 /* Check relax ordering support. */ 1356 if (!haswell_broadwell_cpu) { 1357 sh->cmng.relaxed_ordering_write = 1358 config->hca_attr.relaxed_ordering_write; 1359 sh->cmng.relaxed_ordering_read = 1360 config->hca_attr.relaxed_ordering_read; 1361 } else { 1362 sh->cmng.relaxed_ordering_read = 0; 1363 sh->cmng.relaxed_ordering_write = 0; 1364 } 1365 sh->rq_ts_format = config->hca_attr.rq_ts_format; 1366 sh->sq_ts_format = config->hca_attr.sq_ts_format; 1367 sh->steering_format_version = 1368 config->hca_attr.steering_format_version; 1369 sh->qp_ts_format = config->hca_attr.qp_ts_format; 1370 /* Check for LRO support. */ 1371 if (config->dest_tir && config->hca_attr.lro_cap && 1372 config->dv_flow_en) { 1373 /* TBD check tunnel lro caps. */ 1374 config->lro.supported = config->hca_attr.lro_cap; 1375 DRV_LOG(DEBUG, "Device supports LRO"); 1376 /* 1377 * If LRO timeout is not configured by application, 1378 * use the minimal supported value. 1379 */ 1380 if (!config->lro.timeout) 1381 config->lro.timeout = 1382 config->hca_attr.lro_timer_supported_periods[0]; 1383 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1384 config->lro.timeout); 1385 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1386 "required for coalescing is %d bytes", 1387 config->hca_attr.lro_min_mss_size); 1388 } 1389 #if defined(HAVE_MLX5DV_DR) && \ 1390 (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ 1391 defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) 1392 if (config->hca_attr.qos.sup && 1393 config->hca_attr.qos.flow_meter_old && 1394 config->dv_flow_en) { 1395 uint8_t reg_c_mask = 1396 config->hca_attr.qos.flow_meter_reg_c_ids; 1397 /* 1398 * Meter needs two REG_C's for color match and pre-sfx 1399 * flow match. Here get the REG_C for color match. 1400 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1401 */ 1402 reg_c_mask &= 0xfc; 1403 if (__builtin_popcount(reg_c_mask) < 1) { 1404 priv->mtr_en = 0; 1405 DRV_LOG(WARNING, "No available register for" 1406 " meter."); 1407 } else { 1408 /* 1409 * The meter color register is used by the 1410 * flow-hit feature as well. 1411 * The flow-hit feature must use REG_C_3 1412 * Prefer REG_C_3 if it is available. 1413 */ 1414 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) 1415 priv->mtr_color_reg = REG_C_3; 1416 else 1417 priv->mtr_color_reg = ffs(reg_c_mask) 1418 - 1 + REG_C_0; 1419 priv->mtr_en = 1; 1420 priv->mtr_reg_share = 1421 config->hca_attr.qos.flow_meter; 1422 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1423 priv->mtr_color_reg); 1424 } 1425 } 1426 if (config->hca_attr.qos.sup && 1427 config->hca_attr.qos.flow_meter_aso_sup) { 1428 uint32_t log_obj_size = 1429 rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1); 1430 if (log_obj_size >= 1431 config->hca_attr.qos.log_meter_aso_granularity && 1432 log_obj_size <= 1433 config->hca_attr.qos.log_meter_aso_max_alloc) 1434 sh->meter_aso_en = 1; 1435 } 1436 if (priv->mtr_en) { 1437 err = mlx5_aso_flow_mtrs_mng_init(priv->sh); 1438 if (err) { 1439 err = -err; 1440 goto error; 1441 } 1442 } 1443 if (config->hca_attr.flow.tunnel_header_0_1) 1444 sh->tunnel_header_0_1 = 1; 1445 #endif 1446 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1447 if (config->hca_attr.flow_hit_aso && 1448 priv->mtr_color_reg == REG_C_3) { 1449 sh->flow_hit_aso_en = 1; 1450 err = mlx5_flow_aso_age_mng_init(sh); 1451 if (err) { 1452 err = -err; 1453 goto error; 1454 } 1455 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1456 } 1457 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1458 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \ 1459 defined(HAVE_MLX5_DR_ACTION_ASO_CT) 1460 if (config->hca_attr.ct_offload && 1461 priv->mtr_color_reg == REG_C_3) { 1462 err = mlx5_flow_aso_ct_mng_init(sh); 1463 if (err) { 1464 err = -err; 1465 goto error; 1466 } 1467 DRV_LOG(DEBUG, "CT ASO is supported."); 1468 sh->ct_aso_en = 1; 1469 } 1470 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */ 1471 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1472 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1473 config->dv_flow_en) { 1474 priv->sampler_en = 1; 1475 DRV_LOG(DEBUG, "Sampler enabled!"); 1476 } else { 1477 priv->sampler_en = 0; 1478 if (!config->hca_attr.log_max_ft_sampler_num) 1479 DRV_LOG(WARNING, 1480 "No available register for sampler."); 1481 else 1482 DRV_LOG(DEBUG, "DV flow is not supported!"); 1483 } 1484 #endif 1485 } 1486 if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 && 1487 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) { 1488 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported"); 1489 config->cqe_comp = 0; 1490 } 1491 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 1492 (!config->devx || !config->hca_attr.mini_cqe_resp_flow_tag)) { 1493 DRV_LOG(WARNING, "Flow Tag CQE compression" 1494 " format isn't supported."); 1495 config->cqe_comp = 0; 1496 } 1497 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 1498 (!config->devx || !config->hca_attr.mini_cqe_resp_l3_l4_tag)) { 1499 DRV_LOG(WARNING, "L3/L4 Header CQE compression" 1500 " format isn't supported."); 1501 config->cqe_comp = 0; 1502 } 1503 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported", 1504 config->cqe_comp ? "" : "not "); 1505 if (config->tx_pp) { 1506 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1507 config->hca_attr.dev_freq_khz); 1508 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1509 config->hca_attr.qos.packet_pacing ? "" : "not "); 1510 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1511 config->hca_attr.cross_channel ? "" : "not "); 1512 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1513 config->hca_attr.wqe_index_ignore ? "" : "not "); 1514 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1515 config->hca_attr.non_wire_sq ? "" : "not "); 1516 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1517 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1518 config->hca_attr.log_max_static_sq_wq); 1519 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1520 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1521 if (!config->devx) { 1522 DRV_LOG(ERR, "DevX is required for packet pacing"); 1523 err = ENODEV; 1524 goto error; 1525 } 1526 if (!config->hca_attr.qos.packet_pacing) { 1527 DRV_LOG(ERR, "Packet pacing is not supported"); 1528 err = ENODEV; 1529 goto error; 1530 } 1531 if (!config->hca_attr.cross_channel) { 1532 DRV_LOG(ERR, "Cross channel operations are" 1533 " required for packet pacing"); 1534 err = ENODEV; 1535 goto error; 1536 } 1537 if (!config->hca_attr.wqe_index_ignore) { 1538 DRV_LOG(ERR, "WQE index ignore feature is" 1539 " required for packet pacing"); 1540 err = ENODEV; 1541 goto error; 1542 } 1543 if (!config->hca_attr.non_wire_sq) { 1544 DRV_LOG(ERR, "Non-wire SQ feature is" 1545 " required for packet pacing"); 1546 err = ENODEV; 1547 goto error; 1548 } 1549 if (!config->hca_attr.log_max_static_sq_wq) { 1550 DRV_LOG(ERR, "Static WQE SQ feature is" 1551 " required for packet pacing"); 1552 err = ENODEV; 1553 goto error; 1554 } 1555 if (!config->hca_attr.qos.wqe_rate_pp) { 1556 DRV_LOG(ERR, "WQE rate mode is required" 1557 " for packet pacing"); 1558 err = ENODEV; 1559 goto error; 1560 } 1561 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1562 DRV_LOG(ERR, "DevX does not provide UAR offset," 1563 " can't create queues for packet pacing"); 1564 err = ENODEV; 1565 goto error; 1566 #endif 1567 } 1568 if (config->devx) { 1569 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1570 1571 err = config->hca_attr.access_register_user ? 1572 mlx5_devx_cmd_register_read 1573 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1574 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1575 if (!err) { 1576 uint32_t ts_mode; 1577 1578 /* MTUTC register is read successfully. */ 1579 ts_mode = MLX5_GET(register_mtutc, reg, 1580 time_stamp_mode); 1581 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1582 config->rt_timestamp = 1; 1583 } else { 1584 /* Kernel does not support register reading. */ 1585 if (config->hca_attr.dev_freq_khz == 1586 (NS_PER_S / MS_PER_S)) 1587 config->rt_timestamp = 1; 1588 } 1589 } 1590 /* 1591 * If HW has bug working with tunnel packet decapsulation and 1592 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1593 * bit. Then DEV_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1594 */ 1595 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1596 config->hw_fcs_strip = 0; 1597 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1598 (config->hw_fcs_strip ? "" : "not ")); 1599 if (config->mprq.enabled && mprq) { 1600 if (config->mprq.stride_num_n && 1601 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1602 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1603 config->mprq.stride_num_n = 1604 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1605 mprq_min_stride_num_n), 1606 mprq_max_stride_num_n); 1607 DRV_LOG(WARNING, 1608 "the number of strides" 1609 " for Multi-Packet RQ is out of range," 1610 " setting default value (%u)", 1611 1 << config->mprq.stride_num_n); 1612 } 1613 if (config->mprq.stride_size_n && 1614 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1615 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1616 config->mprq.stride_size_n = 1617 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1618 mprq_min_stride_size_n), 1619 mprq_max_stride_size_n); 1620 DRV_LOG(WARNING, 1621 "the size of a stride" 1622 " for Multi-Packet RQ is out of range," 1623 " setting default value (%u)", 1624 1 << config->mprq.stride_size_n); 1625 } 1626 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1627 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1628 } else if (config->mprq.enabled && !mprq) { 1629 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1630 config->mprq.enabled = 0; 1631 } 1632 if (config->max_dump_files_num == 0) 1633 config->max_dump_files_num = 128; 1634 eth_dev = rte_eth_dev_allocate(name); 1635 if (eth_dev == NULL) { 1636 DRV_LOG(ERR, "can not allocate rte ethdev"); 1637 err = ENOMEM; 1638 goto error; 1639 } 1640 if (priv->representor) { 1641 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1642 eth_dev->data->representor_id = priv->representor_id; 1643 } 1644 priv->mp_id.port_id = eth_dev->data->port_id; 1645 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1646 /* 1647 * Store associated network device interface index. This index 1648 * is permanent throughout the lifetime of device. So, we may store 1649 * the ifindex here and use the cached value further. 1650 */ 1651 MLX5_ASSERT(spawn->ifindex); 1652 priv->if_index = spawn->ifindex; 1653 eth_dev->data->dev_private = priv; 1654 priv->dev_data = eth_dev->data; 1655 eth_dev->data->mac_addrs = priv->mac; 1656 eth_dev->device = dpdk_dev; 1657 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1658 /* Configure the first MAC address by default. */ 1659 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1660 DRV_LOG(ERR, 1661 "port %u cannot get MAC address, is mlx5_en" 1662 " loaded? (errno: %s)", 1663 eth_dev->data->port_id, strerror(rte_errno)); 1664 err = ENODEV; 1665 goto error; 1666 } 1667 DRV_LOG(INFO, 1668 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1669 eth_dev->data->port_id, 1670 mac.addr_bytes[0], mac.addr_bytes[1], 1671 mac.addr_bytes[2], mac.addr_bytes[3], 1672 mac.addr_bytes[4], mac.addr_bytes[5]); 1673 #ifdef RTE_LIBRTE_MLX5_DEBUG 1674 { 1675 char ifname[MLX5_NAMESIZE]; 1676 1677 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1678 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1679 eth_dev->data->port_id, ifname); 1680 else 1681 DRV_LOG(DEBUG, "port %u ifname is unknown", 1682 eth_dev->data->port_id); 1683 } 1684 #endif 1685 /* Get actual MTU if possible. */ 1686 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1687 if (err) { 1688 err = rte_errno; 1689 goto error; 1690 } 1691 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1692 priv->mtu); 1693 /* Initialize burst functions to prevent crashes before link-up. */ 1694 eth_dev->rx_pkt_burst = removed_rx_burst; 1695 eth_dev->tx_pkt_burst = removed_tx_burst; 1696 eth_dev->dev_ops = &mlx5_dev_ops; 1697 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1698 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1699 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1700 /* Register MAC address. */ 1701 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1702 if (config->vf && config->vf_nl_en) 1703 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1704 mlx5_ifindex(eth_dev), 1705 eth_dev->data->mac_addrs, 1706 MLX5_MAX_MAC_ADDRESSES); 1707 priv->ctrl_flows = 0; 1708 rte_spinlock_init(&priv->flow_list_lock); 1709 TAILQ_INIT(&priv->flow_meters); 1710 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR); 1711 if (!priv->mtr_profile_tbl) 1712 goto error; 1713 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1714 mlx5_glue->dv_set_context_attr(sh->ctx, 1715 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1716 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 1717 .alloc = &mlx5_alloc_verbs_buf, 1718 .free = &mlx5_free_verbs_buf, 1719 .data = sh, 1720 })); 1721 /* Bring Ethernet device up. */ 1722 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1723 eth_dev->data->port_id); 1724 mlx5_set_link_up(eth_dev); 1725 /* 1726 * Even though the interrupt handler is not installed yet, 1727 * interrupts will still trigger on the async_fd from 1728 * Verbs context returned by ibv_open_device(). 1729 */ 1730 mlx5_link_update(eth_dev, 0); 1731 #ifdef HAVE_MLX5DV_DR_ESWITCH 1732 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1733 (switch_info->representor || switch_info->master))) 1734 config->dv_esw_en = 0; 1735 #else 1736 config->dv_esw_en = 0; 1737 #endif 1738 /* Detect minimal data bytes to inline. */ 1739 mlx5_set_min_inline(spawn, config); 1740 /* Store device configuration on private structure. */ 1741 priv->config = *config; 1742 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 1743 icfg[i].release_mem_en = !!config->reclaim_mode; 1744 if (config->reclaim_mode) 1745 icfg[i].per_core_cache = 0; 1746 priv->flows[i] = mlx5_ipool_create(&icfg[i]); 1747 if (!priv->flows[i]) 1748 goto error; 1749 } 1750 /* Create context for virtual machine VLAN workaround. */ 1751 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1752 if (config->dv_flow_en) { 1753 err = mlx5_alloc_shared_dr(priv); 1754 if (err) 1755 goto error; 1756 } 1757 if (config->devx && config->dv_flow_en && config->dest_tir) { 1758 priv->obj_ops = devx_obj_ops; 1759 priv->obj_ops.drop_action_create = 1760 ibv_obj_ops.drop_action_create; 1761 priv->obj_ops.drop_action_destroy = 1762 ibv_obj_ops.drop_action_destroy; 1763 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1764 priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify; 1765 #else 1766 if (config->dv_esw_en) 1767 priv->obj_ops.txq_obj_modify = 1768 ibv_obj_ops.txq_obj_modify; 1769 #endif 1770 /* Use specific wrappers for Tx object. */ 1771 priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new; 1772 priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release; 1773 mlx5_queue_counter_id_prepare(eth_dev); 1774 priv->obj_ops.lb_dummy_queue_create = 1775 mlx5_rxq_ibv_obj_dummy_lb_create; 1776 priv->obj_ops.lb_dummy_queue_release = 1777 mlx5_rxq_ibv_obj_dummy_lb_release; 1778 } else { 1779 priv->obj_ops = ibv_obj_ops; 1780 } 1781 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1782 if (!priv->drop_queue.hrxq) 1783 goto error; 1784 /* Supported Verbs flow priority number detection. */ 1785 err = mlx5_flow_discover_priorities(eth_dev); 1786 if (err < 0) { 1787 err = -err; 1788 goto error; 1789 } 1790 priv->config.flow_prio = err; 1791 if (!priv->config.dv_esw_en && 1792 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1793 DRV_LOG(WARNING, "metadata mode %u is not supported " 1794 "(no E-Switch)", priv->config.dv_xmeta_en); 1795 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1796 } 1797 mlx5_set_metadata_mask(eth_dev); 1798 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1799 !priv->sh->dv_regc0_mask) { 1800 DRV_LOG(ERR, "metadata mode %u is not supported " 1801 "(no metadata reg_c[0] is available)", 1802 priv->config.dv_xmeta_en); 1803 err = ENOTSUP; 1804 goto error; 1805 } 1806 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true, 1807 mlx5_hrxq_create_cb, 1808 mlx5_hrxq_match_cb, 1809 mlx5_hrxq_remove_cb, 1810 mlx5_hrxq_clone_cb, 1811 mlx5_hrxq_clone_free_cb); 1812 if (!priv->hrxqs) 1813 goto error; 1814 rte_rwlock_init(&priv->ind_tbls_lock); 1815 /* Query availability of metadata reg_c's. */ 1816 err = mlx5_flow_discover_mreg_c(eth_dev); 1817 if (err < 0) { 1818 err = -err; 1819 goto error; 1820 } 1821 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1822 DRV_LOG(DEBUG, 1823 "port %u extensive metadata register is not supported", 1824 eth_dev->data->port_id); 1825 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1826 DRV_LOG(ERR, "metadata mode %u is not supported " 1827 "(no metadata registers available)", 1828 priv->config.dv_xmeta_en); 1829 err = ENOTSUP; 1830 goto error; 1831 } 1832 } 1833 if (priv->config.dv_flow_en && 1834 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1835 mlx5_flow_ext_mreg_supported(eth_dev) && 1836 priv->sh->dv_regc0_mask) { 1837 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1838 MLX5_FLOW_MREG_HTABLE_SZ, 1839 false, true, eth_dev, 1840 flow_dv_mreg_create_cb, 1841 flow_dv_mreg_match_cb, 1842 flow_dv_mreg_remove_cb, 1843 flow_dv_mreg_clone_cb, 1844 flow_dv_mreg_clone_free_cb); 1845 if (!priv->mreg_cp_tbl) { 1846 err = ENOMEM; 1847 goto error; 1848 } 1849 } 1850 rte_spinlock_init(&priv->shared_act_sl); 1851 mlx5_flow_counter_mode_config(eth_dev); 1852 if (priv->config.dv_flow_en) 1853 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1854 return eth_dev; 1855 error: 1856 if (priv) { 1857 if (priv->mreg_cp_tbl) 1858 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1859 if (priv->sh) 1860 mlx5_os_free_shared_dr(priv); 1861 if (priv->nl_socket_route >= 0) 1862 close(priv->nl_socket_route); 1863 if (priv->nl_socket_rdma >= 0) 1864 close(priv->nl_socket_rdma); 1865 if (priv->vmwa_context) 1866 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1867 if (eth_dev && priv->drop_queue.hrxq) 1868 mlx5_drop_action_destroy(eth_dev); 1869 if (priv->mtr_profile_tbl) 1870 mlx5_l3t_destroy(priv->mtr_profile_tbl); 1871 if (own_domain_id) 1872 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1873 if (priv->hrxqs) 1874 mlx5_list_destroy(priv->hrxqs); 1875 mlx5_free(priv); 1876 if (eth_dev != NULL) 1877 eth_dev->data->dev_private = NULL; 1878 } 1879 if (eth_dev != NULL) { 1880 /* mac_addrs must not be freed alone because part of 1881 * dev_private 1882 **/ 1883 eth_dev->data->mac_addrs = NULL; 1884 rte_eth_dev_release_port(eth_dev); 1885 } 1886 if (sh) 1887 mlx5_free_shared_dev_ctx(sh); 1888 MLX5_ASSERT(err > 0); 1889 rte_errno = err; 1890 return NULL; 1891 } 1892 1893 /** 1894 * Comparison callback to sort device data. 1895 * 1896 * This is meant to be used with qsort(). 1897 * 1898 * @param a[in] 1899 * Pointer to pointer to first data object. 1900 * @param b[in] 1901 * Pointer to pointer to second data object. 1902 * 1903 * @return 1904 * 0 if both objects are equal, less than 0 if the first argument is less 1905 * than the second, greater than 0 otherwise. 1906 */ 1907 static int 1908 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1909 { 1910 const struct mlx5_switch_info *si_a = 1911 &((const struct mlx5_dev_spawn_data *)a)->info; 1912 const struct mlx5_switch_info *si_b = 1913 &((const struct mlx5_dev_spawn_data *)b)->info; 1914 int ret; 1915 1916 /* Master device first. */ 1917 ret = si_b->master - si_a->master; 1918 if (ret) 1919 return ret; 1920 /* Then representor devices. */ 1921 ret = si_b->representor - si_a->representor; 1922 if (ret) 1923 return ret; 1924 /* Unidentified devices come last in no specific order. */ 1925 if (!si_a->representor) 1926 return 0; 1927 /* Order representors by name. */ 1928 return si_a->port_name - si_b->port_name; 1929 } 1930 1931 /** 1932 * Match PCI information for possible slaves of bonding device. 1933 * 1934 * @param[in] ibv_dev 1935 * Pointer to Infiniband device structure. 1936 * @param[in] pci_dev 1937 * Pointer to primary PCI address structure to match. 1938 * @param[in] nl_rdma 1939 * Netlink RDMA group socket handle. 1940 * @param[in] owner 1941 * Rerepsentor owner PF index. 1942 * @param[out] bond_info 1943 * Pointer to bonding information. 1944 * 1945 * @return 1946 * negative value if no bonding device found, otherwise 1947 * positive index of slave PF in bonding. 1948 */ 1949 static int 1950 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, 1951 const struct rte_pci_addr *pci_dev, 1952 int nl_rdma, uint16_t owner, 1953 struct mlx5_bond_info *bond_info) 1954 { 1955 char ifname[IF_NAMESIZE + 1]; 1956 unsigned int ifindex; 1957 unsigned int np, i; 1958 FILE *bond_file = NULL, *file; 1959 int pf = -1; 1960 int ret; 1961 1962 /* 1963 * Try to get master device name. If something goes 1964 * wrong suppose the lack of kernel support and no 1965 * bonding devices. 1966 */ 1967 memset(bond_info, 0, sizeof(*bond_info)); 1968 if (nl_rdma < 0) 1969 return -1; 1970 if (!strstr(ibv_dev->name, "bond")) 1971 return -1; 1972 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name); 1973 if (!np) 1974 return -1; 1975 /* 1976 * The Master device might not be on the predefined 1977 * port (not on port index 1, it is not garanted), 1978 * we have to scan all Infiniband device port and 1979 * find master. 1980 */ 1981 for (i = 1; i <= np; ++i) { 1982 /* Check whether Infiniband port is populated. */ 1983 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i); 1984 if (!ifindex) 1985 continue; 1986 if (!if_indextoname(ifindex, ifname)) 1987 continue; 1988 /* Try to read bonding slave names from sysfs. */ 1989 MKSTR(slaves, 1990 "/sys/class/net/%s/master/bonding/slaves", ifname); 1991 bond_file = fopen(slaves, "r"); 1992 if (bond_file) 1993 break; 1994 } 1995 if (!bond_file) 1996 return -1; 1997 /* Use safe format to check maximal buffer length. */ 1998 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1999 while (fscanf(bond_file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 2000 char tmp_str[IF_NAMESIZE + 32]; 2001 struct rte_pci_addr pci_addr; 2002 struct mlx5_switch_info info; 2003 2004 /* Process slave interface names in the loop. */ 2005 snprintf(tmp_str, sizeof(tmp_str), 2006 "/sys/class/net/%s", ifname); 2007 if (mlx5_get_pci_addr(tmp_str, &pci_addr)) { 2008 DRV_LOG(WARNING, "can not get PCI address" 2009 " for netdev \"%s\"", ifname); 2010 continue; 2011 } 2012 /* Slave interface PCI address match found. */ 2013 snprintf(tmp_str, sizeof(tmp_str), 2014 "/sys/class/net/%s/phys_port_name", ifname); 2015 file = fopen(tmp_str, "rb"); 2016 if (!file) 2017 break; 2018 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 2019 if (fscanf(file, "%32s", tmp_str) == 1) 2020 mlx5_translate_port_name(tmp_str, &info); 2021 fclose(file); 2022 /* Only process PF ports. */ 2023 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY && 2024 info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 2025 continue; 2026 /* Check max bonding member. */ 2027 if (info.port_name >= MLX5_BOND_MAX_PORTS) { 2028 DRV_LOG(WARNING, "bonding index out of range, " 2029 "please increase MLX5_BOND_MAX_PORTS: %s", 2030 tmp_str); 2031 break; 2032 } 2033 /* Match PCI address, allows BDF0+pfx or BDFx+pfx. */ 2034 if (pci_dev->domain == pci_addr.domain && 2035 pci_dev->bus == pci_addr.bus && 2036 pci_dev->devid == pci_addr.devid && 2037 ((pci_dev->function == 0 && 2038 pci_dev->function + owner == pci_addr.function) || 2039 (pci_dev->function == owner && 2040 pci_addr.function == owner))) 2041 pf = info.port_name; 2042 /* Get ifindex. */ 2043 snprintf(tmp_str, sizeof(tmp_str), 2044 "/sys/class/net/%s/ifindex", ifname); 2045 file = fopen(tmp_str, "rb"); 2046 if (!file) 2047 break; 2048 ret = fscanf(file, "%u", &ifindex); 2049 fclose(file); 2050 if (ret != 1) 2051 break; 2052 /* Save bonding info. */ 2053 strncpy(bond_info->ports[info.port_name].ifname, ifname, 2054 sizeof(bond_info->ports[0].ifname)); 2055 bond_info->ports[info.port_name].pci_addr = pci_addr; 2056 bond_info->ports[info.port_name].ifindex = ifindex; 2057 bond_info->n_port++; 2058 } 2059 if (pf >= 0) { 2060 /* Get bond interface info */ 2061 ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex, 2062 bond_info->ifname); 2063 if (ret) 2064 DRV_LOG(ERR, "unable to get bond info: %s", 2065 strerror(rte_errno)); 2066 else 2067 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 2068 ifindex, bond_info->ifindex, bond_info->ifname); 2069 } 2070 return pf; 2071 } 2072 2073 static void 2074 mlx5_os_config_default(struct mlx5_dev_config *config) 2075 { 2076 memset(config, 0, sizeof(*config)); 2077 config->mps = MLX5_ARG_UNSET; 2078 config->dbnc = MLX5_ARG_UNSET; 2079 config->rx_vec_en = 1; 2080 config->txq_inline_max = MLX5_ARG_UNSET; 2081 config->txq_inline_min = MLX5_ARG_UNSET; 2082 config->txq_inline_mpw = MLX5_ARG_UNSET; 2083 config->txqs_inline = MLX5_ARG_UNSET; 2084 config->vf_nl_en = 1; 2085 config->mr_ext_memseg_en = 1; 2086 config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2087 config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2088 config->dv_esw_en = 1; 2089 config->dv_flow_en = 1; 2090 config->decap_en = 1; 2091 config->log_hp_size = MLX5_ARG_UNSET; 2092 } 2093 2094 /** 2095 * Register a PCI device within bonding. 2096 * 2097 * This function spawns Ethernet devices out of a given PCI device and 2098 * bonding owner PF index. 2099 * 2100 * @param[in] pci_dev 2101 * PCI device information. 2102 * @param[in] req_eth_da 2103 * Requested ethdev device argument. 2104 * @param[in] owner_id 2105 * Requested owner PF port ID within bonding device, default to 0. 2106 * 2107 * @return 2108 * 0 on success, a negative errno value otherwise and rte_errno is set. 2109 */ 2110 static int 2111 mlx5_os_pci_probe_pf(struct rte_pci_device *pci_dev, 2112 struct rte_eth_devargs *req_eth_da, 2113 uint16_t owner_id) 2114 { 2115 struct ibv_device **ibv_list; 2116 /* 2117 * Number of found IB Devices matching with requested PCI BDF. 2118 * nd != 1 means there are multiple IB devices over the same 2119 * PCI device and we have representors and master. 2120 */ 2121 unsigned int nd = 0; 2122 /* 2123 * Number of found IB device Ports. nd = 1 and np = 1..n means 2124 * we have the single multiport IB device, and there may be 2125 * representors attached to some of found ports. 2126 */ 2127 unsigned int np = 0; 2128 /* 2129 * Number of DPDK ethernet devices to Spawn - either over 2130 * multiple IB devices or multiple ports of single IB device. 2131 * Actually this is the number of iterations to spawn. 2132 */ 2133 unsigned int ns = 0; 2134 /* 2135 * Bonding device 2136 * < 0 - no bonding device (single one) 2137 * >= 0 - bonding device (value is slave PF index) 2138 */ 2139 int bd = -1; 2140 struct mlx5_dev_spawn_data *list = NULL; 2141 struct mlx5_dev_config dev_config; 2142 unsigned int dev_config_vf; 2143 struct rte_eth_devargs eth_da = *req_eth_da; 2144 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */ 2145 struct mlx5_bond_info bond_info; 2146 int ret = -1; 2147 2148 errno = 0; 2149 ibv_list = mlx5_glue->get_device_list(&ret); 2150 if (!ibv_list) { 2151 rte_errno = errno ? errno : ENOSYS; 2152 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 2153 return -rte_errno; 2154 } 2155 /* 2156 * First scan the list of all Infiniband devices to find 2157 * matching ones, gathering into the list. 2158 */ 2159 struct ibv_device *ibv_match[ret + 1]; 2160 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 2161 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 2162 unsigned int i; 2163 2164 while (ret-- > 0) { 2165 struct rte_pci_addr pci_addr; 2166 2167 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 2168 bd = mlx5_device_bond_pci_match 2169 (ibv_list[ret], &owner_pci, nl_rdma, owner_id, 2170 &bond_info); 2171 if (bd >= 0) { 2172 /* 2173 * Bonding device detected. Only one match is allowed, 2174 * the bonding is supported over multi-port IB device, 2175 * there should be no matches on representor PCI 2176 * functions or non VF LAG bonding devices with 2177 * specified address. 2178 */ 2179 if (nd) { 2180 DRV_LOG(ERR, 2181 "multiple PCI match on bonding device" 2182 "\"%s\" found", ibv_list[ret]->name); 2183 rte_errno = ENOENT; 2184 ret = -rte_errno; 2185 goto exit; 2186 } 2187 /* Amend owner pci address if owner PF ID specified. */ 2188 if (eth_da.nb_representor_ports) 2189 owner_pci.function += owner_id; 2190 DRV_LOG(INFO, "PCI information matches for" 2191 " slave %d bonding device \"%s\"", 2192 bd, ibv_list[ret]->name); 2193 ibv_match[nd++] = ibv_list[ret]; 2194 break; 2195 } else { 2196 /* Bonding device not found. */ 2197 if (mlx5_get_pci_addr(ibv_list[ret]->ibdev_path, 2198 &pci_addr)) 2199 continue; 2200 if (owner_pci.domain != pci_addr.domain || 2201 owner_pci.bus != pci_addr.bus || 2202 owner_pci.devid != pci_addr.devid || 2203 owner_pci.function != pci_addr.function) 2204 continue; 2205 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 2206 ibv_list[ret]->name); 2207 ibv_match[nd++] = ibv_list[ret]; 2208 } 2209 } 2210 ibv_match[nd] = NULL; 2211 if (!nd) { 2212 /* No device matches, just complain and bail out. */ 2213 DRV_LOG(WARNING, 2214 "no Verbs device matches PCI device " PCI_PRI_FMT "," 2215 " are kernel drivers loaded?", 2216 owner_pci.domain, owner_pci.bus, 2217 owner_pci.devid, owner_pci.function); 2218 rte_errno = ENOENT; 2219 ret = -rte_errno; 2220 goto exit; 2221 } 2222 if (nd == 1) { 2223 /* 2224 * Found single matching device may have multiple ports. 2225 * Each port may be representor, we have to check the port 2226 * number and check the representors existence. 2227 */ 2228 if (nl_rdma >= 0) 2229 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 2230 if (!np) 2231 DRV_LOG(WARNING, "can not get IB device \"%s\"" 2232 " ports number", ibv_match[0]->name); 2233 if (bd >= 0 && !np) { 2234 DRV_LOG(ERR, "can not get ports" 2235 " for bonding device"); 2236 rte_errno = ENOENT; 2237 ret = -rte_errno; 2238 goto exit; 2239 } 2240 } 2241 /* 2242 * Now we can determine the maximal 2243 * amount of devices to be spawned. 2244 */ 2245 list = mlx5_malloc(MLX5_MEM_ZERO, 2246 sizeof(struct mlx5_dev_spawn_data) * 2247 (np ? np : nd), 2248 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2249 if (!list) { 2250 DRV_LOG(ERR, "spawn data array allocation failure"); 2251 rte_errno = ENOMEM; 2252 ret = -rte_errno; 2253 goto exit; 2254 } 2255 if (bd >= 0 || np > 1) { 2256 /* 2257 * Single IB device with multiple ports found, 2258 * it may be E-Switch master device and representors. 2259 * We have to perform identification through the ports. 2260 */ 2261 MLX5_ASSERT(nl_rdma >= 0); 2262 MLX5_ASSERT(ns == 0); 2263 MLX5_ASSERT(nd == 1); 2264 MLX5_ASSERT(np); 2265 for (i = 1; i <= np; ++i) { 2266 list[ns].bond_info = &bond_info; 2267 list[ns].max_port = np; 2268 list[ns].phys_port = i; 2269 list[ns].phys_dev = ibv_match[0]; 2270 list[ns].eth_dev = NULL; 2271 list[ns].pci_dev = pci_dev; 2272 list[ns].pf_bond = bd; 2273 list[ns].ifindex = mlx5_nl_ifindex 2274 (nl_rdma, 2275 mlx5_os_get_dev_device_name 2276 (list[ns].phys_dev), i); 2277 if (!list[ns].ifindex) { 2278 /* 2279 * No network interface index found for the 2280 * specified port, it means there is no 2281 * representor on this port. It's OK, 2282 * there can be disabled ports, for example 2283 * if sriov_numvfs < sriov_totalvfs. 2284 */ 2285 continue; 2286 } 2287 ret = -1; 2288 if (nl_route >= 0) 2289 ret = mlx5_nl_switch_info 2290 (nl_route, 2291 list[ns].ifindex, 2292 &list[ns].info); 2293 if (ret || (!list[ns].info.representor && 2294 !list[ns].info.master)) { 2295 /* 2296 * We failed to recognize representors with 2297 * Netlink, let's try to perform the task 2298 * with sysfs. 2299 */ 2300 ret = mlx5_sysfs_switch_info 2301 (list[ns].ifindex, 2302 &list[ns].info); 2303 } 2304 if (!ret && bd >= 0) { 2305 switch (list[ns].info.name_type) { 2306 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 2307 if (np == 1) { 2308 /* 2309 * Force standalone bonding 2310 * device for ROCE LAG 2311 * confgiurations. 2312 */ 2313 list[ns].info.master = 0; 2314 list[ns].info.representor = 0; 2315 } 2316 if (list[ns].info.port_name == bd) 2317 ns++; 2318 break; 2319 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 2320 /* Fallthrough */ 2321 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 2322 /* Fallthrough */ 2323 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 2324 if (list[ns].info.pf_num == bd) 2325 ns++; 2326 break; 2327 default: 2328 break; 2329 } 2330 continue; 2331 } 2332 if (!ret && (list[ns].info.representor ^ 2333 list[ns].info.master)) 2334 ns++; 2335 } 2336 if (!ns) { 2337 DRV_LOG(ERR, 2338 "unable to recognize master/representors" 2339 " on the IB device with multiple ports"); 2340 rte_errno = ENOENT; 2341 ret = -rte_errno; 2342 goto exit; 2343 } 2344 } else { 2345 /* 2346 * The existence of several matching entries (nd > 1) means 2347 * port representors have been instantiated. No existing Verbs 2348 * call nor sysfs entries can tell them apart, this can only 2349 * be done through Netlink calls assuming kernel drivers are 2350 * recent enough to support them. 2351 * 2352 * In the event of identification failure through Netlink, 2353 * try again through sysfs, then: 2354 * 2355 * 1. A single IB device matches (nd == 1) with single 2356 * port (np=0/1) and is not a representor, assume 2357 * no switch support. 2358 * 2359 * 2. Otherwise no safe assumptions can be made; 2360 * complain louder and bail out. 2361 */ 2362 for (i = 0; i != nd; ++i) { 2363 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2364 list[ns].bond_info = NULL; 2365 list[ns].max_port = 1; 2366 list[ns].phys_port = 1; 2367 list[ns].phys_dev = ibv_match[i]; 2368 list[ns].eth_dev = NULL; 2369 list[ns].pci_dev = pci_dev; 2370 list[ns].pf_bond = -1; 2371 list[ns].ifindex = 0; 2372 if (nl_rdma >= 0) 2373 list[ns].ifindex = mlx5_nl_ifindex 2374 (nl_rdma, 2375 mlx5_os_get_dev_device_name 2376 (list[ns].phys_dev), 1); 2377 if (!list[ns].ifindex) { 2378 char ifname[IF_NAMESIZE]; 2379 2380 /* 2381 * Netlink failed, it may happen with old 2382 * ib_core kernel driver (before 4.16). 2383 * We can assume there is old driver because 2384 * here we are processing single ports IB 2385 * devices. Let's try sysfs to retrieve 2386 * the ifindex. The method works for 2387 * master device only. 2388 */ 2389 if (nd > 1) { 2390 /* 2391 * Multiple devices found, assume 2392 * representors, can not distinguish 2393 * master/representor and retrieve 2394 * ifindex via sysfs. 2395 */ 2396 continue; 2397 } 2398 ret = mlx5_get_ifname_sysfs 2399 (ibv_match[i]->ibdev_path, ifname); 2400 if (!ret) 2401 list[ns].ifindex = 2402 if_nametoindex(ifname); 2403 if (!list[ns].ifindex) { 2404 /* 2405 * No network interface index found 2406 * for the specified device, it means 2407 * there it is neither representor 2408 * nor master. 2409 */ 2410 continue; 2411 } 2412 } 2413 ret = -1; 2414 if (nl_route >= 0) 2415 ret = mlx5_nl_switch_info 2416 (nl_route, 2417 list[ns].ifindex, 2418 &list[ns].info); 2419 if (ret || (!list[ns].info.representor && 2420 !list[ns].info.master)) { 2421 /* 2422 * We failed to recognize representors with 2423 * Netlink, let's try to perform the task 2424 * with sysfs. 2425 */ 2426 ret = mlx5_sysfs_switch_info 2427 (list[ns].ifindex, 2428 &list[ns].info); 2429 } 2430 if (!ret && (list[ns].info.representor ^ 2431 list[ns].info.master)) { 2432 ns++; 2433 } else if ((nd == 1) && 2434 !list[ns].info.representor && 2435 !list[ns].info.master) { 2436 /* 2437 * Single IB device with 2438 * one physical port and 2439 * attached network device. 2440 * May be SRIOV is not enabled 2441 * or there is no representors. 2442 */ 2443 DRV_LOG(INFO, "no E-Switch support detected"); 2444 ns++; 2445 break; 2446 } 2447 } 2448 if (!ns) { 2449 DRV_LOG(ERR, 2450 "unable to recognize master/representors" 2451 " on the multiple IB devices"); 2452 rte_errno = ENOENT; 2453 ret = -rte_errno; 2454 goto exit; 2455 } 2456 /* 2457 * New kernels may add the switch_id attribute for the case 2458 * there is no E-Switch and we wrongly recognized the 2459 * only device as master. Override this if there is the 2460 * single device with single port and new device name 2461 * format present. 2462 */ 2463 if (nd == 1 && 2464 list[0].info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) { 2465 list[0].info.master = 0; 2466 list[0].info.representor = 0; 2467 } 2468 } 2469 MLX5_ASSERT(ns); 2470 /* 2471 * Sort list to probe devices in natural order for users convenience 2472 * (i.e. master first, then representors from lowest to highest ID). 2473 */ 2474 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2475 /* Device specific configuration. */ 2476 switch (pci_dev->id.device_id) { 2477 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2478 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2479 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2480 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2481 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2482 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2483 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: 2484 dev_config_vf = 1; 2485 break; 2486 default: 2487 dev_config_vf = 0; 2488 break; 2489 } 2490 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) { 2491 /* Set devargs default values. */ 2492 if (eth_da.nb_mh_controllers == 0) { 2493 eth_da.nb_mh_controllers = 1; 2494 eth_da.mh_controllers[0] = 0; 2495 } 2496 if (eth_da.nb_ports == 0 && ns > 0) { 2497 if (list[0].pf_bond >= 0 && list[0].info.representor) 2498 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s", 2499 pci_dev->device.devargs->args); 2500 eth_da.nb_ports = 1; 2501 eth_da.ports[0] = list[0].info.pf_num; 2502 } 2503 if (eth_da.nb_representor_ports == 0) { 2504 eth_da.nb_representor_ports = 1; 2505 eth_da.representor_ports[0] = 0; 2506 } 2507 } 2508 for (i = 0; i != ns; ++i) { 2509 uint32_t restore; 2510 2511 /* Default configuration. */ 2512 mlx5_os_config_default(&dev_config); 2513 dev_config.vf = dev_config_vf; 2514 dev_config.allow_duplicate_pattern = 1; 2515 list[i].numa_node = pci_dev->device.numa_node; 2516 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 2517 &list[i], 2518 &dev_config, 2519 ð_da); 2520 if (!list[i].eth_dev) { 2521 if (rte_errno != EBUSY && rte_errno != EEXIST) 2522 break; 2523 /* Device is disabled or already spawned. Ignore it. */ 2524 continue; 2525 } 2526 restore = list[i].eth_dev->data->dev_flags; 2527 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2528 /* Restore non-PCI flags cleared by the above call. */ 2529 list[i].eth_dev->data->dev_flags |= restore; 2530 rte_eth_dev_probing_finish(list[i].eth_dev); 2531 } 2532 if (i != ns) { 2533 DRV_LOG(ERR, 2534 "probe of PCI device " PCI_PRI_FMT " aborted after" 2535 " encountering an error: %s", 2536 owner_pci.domain, owner_pci.bus, 2537 owner_pci.devid, owner_pci.function, 2538 strerror(rte_errno)); 2539 ret = -rte_errno; 2540 /* Roll back. */ 2541 while (i--) { 2542 if (!list[i].eth_dev) 2543 continue; 2544 mlx5_dev_close(list[i].eth_dev); 2545 /* mac_addrs must not be freed because in dev_private */ 2546 list[i].eth_dev->data->mac_addrs = NULL; 2547 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2548 } 2549 /* Restore original error. */ 2550 rte_errno = -ret; 2551 } else { 2552 ret = 0; 2553 } 2554 exit: 2555 /* 2556 * Do the routine cleanup: 2557 * - close opened Netlink sockets 2558 * - free allocated spawn data array 2559 * - free the Infiniband device list 2560 */ 2561 if (nl_rdma >= 0) 2562 close(nl_rdma); 2563 if (nl_route >= 0) 2564 close(nl_route); 2565 if (list) 2566 mlx5_free(list); 2567 MLX5_ASSERT(ibv_list); 2568 mlx5_glue->free_device_list(ibv_list); 2569 return ret; 2570 } 2571 2572 static int 2573 mlx5_os_parse_eth_devargs(struct rte_device *dev, 2574 struct rte_eth_devargs *eth_da) 2575 { 2576 int ret = 0; 2577 2578 if (dev->devargs == NULL) 2579 return 0; 2580 memset(eth_da, 0, sizeof(*eth_da)); 2581 /* Parse representor information first from class argument. */ 2582 if (dev->devargs->cls_str) 2583 ret = rte_eth_devargs_parse(dev->devargs->cls_str, eth_da); 2584 if (ret != 0) { 2585 DRV_LOG(ERR, "failed to parse device arguments: %s", 2586 dev->devargs->cls_str); 2587 return -rte_errno; 2588 } 2589 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) { 2590 /* Parse legacy device argument */ 2591 ret = rte_eth_devargs_parse(dev->devargs->args, eth_da); 2592 if (ret) { 2593 DRV_LOG(ERR, "failed to parse device arguments: %s", 2594 dev->devargs->args); 2595 return -rte_errno; 2596 } 2597 } 2598 return 0; 2599 } 2600 2601 /** 2602 * Callback to register a PCI device. 2603 * 2604 * This function spawns Ethernet devices out of a given PCI device. 2605 * 2606 * @param[in] pci_dev 2607 * PCI device information. 2608 * 2609 * @return 2610 * 0 on success, a negative errno value otherwise and rte_errno is set. 2611 */ 2612 static int 2613 mlx5_os_pci_probe(struct rte_pci_device *pci_dev) 2614 { 2615 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2616 int ret = 0; 2617 uint16_t p; 2618 2619 ret = mlx5_os_parse_eth_devargs(&pci_dev->device, ð_da); 2620 if (ret != 0) 2621 return ret; 2622 2623 if (eth_da.nb_ports > 0) { 2624 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */ 2625 for (p = 0; p < eth_da.nb_ports; p++) 2626 ret = mlx5_os_pci_probe_pf(pci_dev, ð_da, 2627 eth_da.ports[p]); 2628 } else { 2629 ret = mlx5_os_pci_probe_pf(pci_dev, ð_da, 0); 2630 } 2631 return ret; 2632 } 2633 2634 /* Probe a single SF device on auxiliary bus, no representor support. */ 2635 static int 2636 mlx5_os_auxiliary_probe(struct rte_device *dev) 2637 { 2638 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2639 struct mlx5_dev_config config; 2640 struct mlx5_dev_spawn_data spawn = { .pf_bond = -1 }; 2641 struct rte_auxiliary_device *adev = RTE_DEV_TO_AUXILIARY(dev); 2642 struct rte_eth_dev *eth_dev; 2643 int ret = 0; 2644 2645 /* Parse ethdev devargs. */ 2646 ret = mlx5_os_parse_eth_devargs(dev, ð_da); 2647 if (ret != 0) 2648 return ret; 2649 /* Set default config data. */ 2650 mlx5_os_config_default(&config); 2651 config.sf = 1; 2652 /* Init spawn data. */ 2653 spawn.max_port = 1; 2654 spawn.phys_port = 1; 2655 spawn.phys_dev = mlx5_os_get_ibv_dev(dev); 2656 if (spawn.phys_dev == NULL) 2657 return -rte_errno; 2658 ret = mlx5_auxiliary_get_ifindex(dev->name); 2659 if (ret < 0) { 2660 DRV_LOG(ERR, "failed to get ethdev ifindex: %s", dev->name); 2661 return ret; 2662 } 2663 spawn.ifindex = ret; 2664 spawn.numa_node = dev->numa_node; 2665 /* Spawn device. */ 2666 eth_dev = mlx5_dev_spawn(dev, &spawn, &config, ð_da); 2667 if (eth_dev == NULL) 2668 return -rte_errno; 2669 /* Post create. */ 2670 eth_dev->intr_handle = &adev->intr_handle; 2671 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2672 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2673 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_RMV; 2674 eth_dev->data->numa_node = dev->numa_node; 2675 } 2676 rte_eth_dev_probing_finish(eth_dev); 2677 return 0; 2678 } 2679 2680 /** 2681 * Net class driver callback to probe a device. 2682 * 2683 * This function probe PCI bus device(s) or a single SF on auxiliary bus. 2684 * 2685 * @param[in] dev 2686 * Pointer to the generic device. 2687 * 2688 * @return 2689 * 0 on success, the function cannot fail. 2690 */ 2691 int 2692 mlx5_os_net_probe(struct rte_device *dev) 2693 { 2694 int ret; 2695 2696 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 2697 mlx5_pmd_socket_init(); 2698 ret = mlx5_init_once(); 2699 if (ret) { 2700 DRV_LOG(ERR, "unable to init PMD global data: %s", 2701 strerror(rte_errno)); 2702 return -rte_errno; 2703 } 2704 if (mlx5_dev_is_pci(dev)) 2705 return mlx5_os_pci_probe(RTE_DEV_TO_PCI(dev)); 2706 else 2707 return mlx5_os_auxiliary_probe(dev); 2708 } 2709 2710 static int 2711 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config) 2712 { 2713 char *env; 2714 int value; 2715 2716 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2717 /* Get environment variable to store. */ 2718 env = getenv(MLX5_SHUT_UP_BF); 2719 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET; 2720 if (config->dbnc == MLX5_ARG_UNSET) 2721 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1); 2722 else 2723 setenv(MLX5_SHUT_UP_BF, 2724 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1); 2725 return value; 2726 } 2727 2728 static void 2729 mlx5_restore_doorbell_mapping_env(int value) 2730 { 2731 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2732 /* Restore the original environment variable state. */ 2733 if (value == MLX5_ARG_UNSET) 2734 unsetenv(MLX5_SHUT_UP_BF); 2735 else 2736 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); 2737 } 2738 2739 /** 2740 * Extract pdn of PD object using DV API. 2741 * 2742 * @param[in] pd 2743 * Pointer to the verbs PD object. 2744 * @param[out] pdn 2745 * Pointer to the PD object number variable. 2746 * 2747 * @return 2748 * 0 on success, error value otherwise. 2749 */ 2750 int 2751 mlx5_os_get_pdn(void *pd, uint32_t *pdn) 2752 { 2753 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2754 struct mlx5dv_obj obj; 2755 struct mlx5dv_pd pd_info; 2756 int ret = 0; 2757 2758 obj.pd.in = pd; 2759 obj.pd.out = &pd_info; 2760 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 2761 if (ret) { 2762 DRV_LOG(DEBUG, "Fail to get PD object info"); 2763 return ret; 2764 } 2765 *pdn = pd_info.pdn; 2766 return 0; 2767 #else 2768 (void)pd; 2769 (void)pdn; 2770 return -ENOTSUP; 2771 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 2772 } 2773 2774 /** 2775 * Function API to open IB device. 2776 * 2777 * This function calls the Linux glue APIs to open a device. 2778 * 2779 * @param[in] spawn 2780 * Pointer to the IB device attributes (name, port, etc). 2781 * @param[out] config 2782 * Pointer to device configuration structure. 2783 * @param[out] sh 2784 * Pointer to shared context structure. 2785 * 2786 * @return 2787 * 0 on success, a positive error value otherwise. 2788 */ 2789 int 2790 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 2791 const struct mlx5_dev_config *config, 2792 struct mlx5_dev_ctx_shared *sh) 2793 { 2794 int dbmap_env; 2795 int err = 0; 2796 2797 pthread_mutex_init(&sh->txpp.mutex, NULL); 2798 /* 2799 * Configure environment variable "MLX5_BF_SHUT_UP" 2800 * before the device creation. The rdma_core library 2801 * checks the variable at device creation and 2802 * stores the result internally. 2803 */ 2804 dbmap_env = mlx5_config_doorbell_mapping_env(config); 2805 /* Try to open IB device with DV first, then usual Verbs. */ 2806 errno = 0; 2807 sh->ctx = mlx5_glue->dv_open_device(spawn->phys_dev); 2808 if (sh->ctx) { 2809 sh->devx = 1; 2810 DRV_LOG(DEBUG, "DevX is supported"); 2811 /* The device is created, no need for environment. */ 2812 mlx5_restore_doorbell_mapping_env(dbmap_env); 2813 } else { 2814 /* The environment variable is still configured. */ 2815 sh->ctx = mlx5_glue->open_device(spawn->phys_dev); 2816 err = errno ? errno : ENODEV; 2817 /* 2818 * The environment variable is not needed anymore, 2819 * all device creation attempts are completed. 2820 */ 2821 mlx5_restore_doorbell_mapping_env(dbmap_env); 2822 if (!sh->ctx) 2823 return err; 2824 DRV_LOG(DEBUG, "DevX is NOT supported"); 2825 err = 0; 2826 } 2827 if (!err && sh->ctx) { 2828 /* Hint libmlx5 to use PMD allocator for data plane resources */ 2829 mlx5_glue->dv_set_context_attr(sh->ctx, 2830 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 2831 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 2832 .alloc = &mlx5_alloc_verbs_buf, 2833 .free = &mlx5_free_verbs_buf, 2834 .data = sh, 2835 })); 2836 } 2837 return err; 2838 } 2839 2840 /** 2841 * Install shared asynchronous device events handler. 2842 * This function is implemented to support event sharing 2843 * between multiple ports of single IB device. 2844 * 2845 * @param sh 2846 * Pointer to mlx5_dev_ctx_shared object. 2847 */ 2848 void 2849 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2850 { 2851 int ret; 2852 int flags; 2853 2854 sh->intr_handle.fd = -1; 2855 flags = fcntl(((struct ibv_context *)sh->ctx)->async_fd, F_GETFL); 2856 ret = fcntl(((struct ibv_context *)sh->ctx)->async_fd, 2857 F_SETFL, flags | O_NONBLOCK); 2858 if (ret) { 2859 DRV_LOG(INFO, "failed to change file descriptor async event" 2860 " queue"); 2861 } else { 2862 sh->intr_handle.fd = ((struct ibv_context *)sh->ctx)->async_fd; 2863 sh->intr_handle.type = RTE_INTR_HANDLE_EXT; 2864 if (rte_intr_callback_register(&sh->intr_handle, 2865 mlx5_dev_interrupt_handler, sh)) { 2866 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2867 sh->intr_handle.fd = -1; 2868 } 2869 } 2870 if (sh->devx) { 2871 #ifdef HAVE_IBV_DEVX_ASYNC 2872 sh->intr_handle_devx.fd = -1; 2873 sh->devx_comp = 2874 (void *)mlx5_glue->devx_create_cmd_comp(sh->ctx); 2875 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2876 if (!devx_comp) { 2877 DRV_LOG(INFO, "failed to allocate devx_comp."); 2878 return; 2879 } 2880 flags = fcntl(devx_comp->fd, F_GETFL); 2881 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2882 if (ret) { 2883 DRV_LOG(INFO, "failed to change file descriptor" 2884 " devx comp"); 2885 return; 2886 } 2887 sh->intr_handle_devx.fd = devx_comp->fd; 2888 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT; 2889 if (rte_intr_callback_register(&sh->intr_handle_devx, 2890 mlx5_dev_interrupt_handler_devx, sh)) { 2891 DRV_LOG(INFO, "Fail to install the devx shared" 2892 " interrupt."); 2893 sh->intr_handle_devx.fd = -1; 2894 } 2895 #endif /* HAVE_IBV_DEVX_ASYNC */ 2896 } 2897 } 2898 2899 /** 2900 * Uninstall shared asynchronous device events handler. 2901 * This function is implemented to support event sharing 2902 * between multiple ports of single IB device. 2903 * 2904 * @param dev 2905 * Pointer to mlx5_dev_ctx_shared object. 2906 */ 2907 void 2908 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2909 { 2910 if (sh->intr_handle.fd >= 0) 2911 mlx5_intr_callback_unregister(&sh->intr_handle, 2912 mlx5_dev_interrupt_handler, sh); 2913 #ifdef HAVE_IBV_DEVX_ASYNC 2914 if (sh->intr_handle_devx.fd >= 0) 2915 rte_intr_callback_unregister(&sh->intr_handle_devx, 2916 mlx5_dev_interrupt_handler_devx, sh); 2917 if (sh->devx_comp) 2918 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2919 #endif 2920 } 2921 2922 /** 2923 * Read statistics by a named counter. 2924 * 2925 * @param[in] priv 2926 * Pointer to the private device data structure. 2927 * @param[in] ctr_name 2928 * Pointer to the name of the statistic counter to read 2929 * @param[out] stat 2930 * Pointer to read statistic value. 2931 * @return 2932 * 0 on success and stat is valud, 1 if failed to read the value 2933 * rte_errno is set. 2934 * 2935 */ 2936 int 2937 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2938 uint64_t *stat) 2939 { 2940 int fd; 2941 2942 if (priv->sh) { 2943 if (priv->q_counters != NULL && 2944 strcmp(ctr_name, "out_of_buffer") == 0) 2945 return mlx5_devx_cmd_queue_counter_query 2946 (priv->q_counters, 0, (uint32_t *)stat); 2947 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2948 priv->sh->ibdev_path, 2949 priv->dev_port, 2950 ctr_name); 2951 fd = open(path, O_RDONLY); 2952 /* 2953 * in switchdev the file location is not per port 2954 * but rather in <ibdev_path>/hw_counters/<file_name>. 2955 */ 2956 if (fd == -1) { 2957 MKSTR(path1, "%s/hw_counters/%s", 2958 priv->sh->ibdev_path, 2959 ctr_name); 2960 fd = open(path1, O_RDONLY); 2961 } 2962 if (fd != -1) { 2963 char buf[21] = {'\0'}; 2964 ssize_t n = read(fd, buf, sizeof(buf)); 2965 2966 close(fd); 2967 if (n != -1) { 2968 *stat = strtoull(buf, NULL, 10); 2969 return 0; 2970 } 2971 } 2972 } 2973 *stat = 0; 2974 return 1; 2975 } 2976 2977 /** 2978 * Set the reg_mr and dereg_mr call backs 2979 * 2980 * @param reg_mr_cb[out] 2981 * Pointer to reg_mr func 2982 * @param dereg_mr_cb[out] 2983 * Pointer to dereg_mr func 2984 * 2985 */ 2986 void 2987 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 2988 mlx5_dereg_mr_t *dereg_mr_cb) 2989 { 2990 *reg_mr_cb = mlx5_mr_verbs_ops.reg_mr; 2991 *dereg_mr_cb = mlx5_mr_verbs_ops.dereg_mr; 2992 } 2993 2994 /** 2995 * Remove a MAC address from device 2996 * 2997 * @param dev 2998 * Pointer to Ethernet device structure. 2999 * @param index 3000 * MAC address index. 3001 */ 3002 void 3003 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 3004 { 3005 struct mlx5_priv *priv = dev->data->dev_private; 3006 const int vf = priv->config.vf; 3007 3008 if (vf) 3009 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 3010 mlx5_ifindex(dev), priv->mac_own, 3011 &dev->data->mac_addrs[index], index); 3012 } 3013 3014 /** 3015 * Adds a MAC address to the device 3016 * 3017 * @param dev 3018 * Pointer to Ethernet device structure. 3019 * @param mac_addr 3020 * MAC address to register. 3021 * @param index 3022 * MAC address index. 3023 * 3024 * @return 3025 * 0 on success, a negative errno value otherwise 3026 */ 3027 int 3028 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 3029 uint32_t index) 3030 { 3031 struct mlx5_priv *priv = dev->data->dev_private; 3032 const int vf = priv->config.vf; 3033 int ret = 0; 3034 3035 if (vf) 3036 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 3037 mlx5_ifindex(dev), priv->mac_own, 3038 mac, index); 3039 return ret; 3040 } 3041 3042 /** 3043 * Modify a VF MAC address 3044 * 3045 * @param priv 3046 * Pointer to device private data. 3047 * @param mac_addr 3048 * MAC address to modify into. 3049 * @param iface_idx 3050 * Net device interface index 3051 * @param vf_index 3052 * VF index 3053 * 3054 * @return 3055 * 0 on success, a negative errno value otherwise 3056 */ 3057 int 3058 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 3059 unsigned int iface_idx, 3060 struct rte_ether_addr *mac_addr, 3061 int vf_index) 3062 { 3063 return mlx5_nl_vf_mac_addr_modify 3064 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 3065 } 3066 3067 /** 3068 * Set device promiscuous mode 3069 * 3070 * @param dev 3071 * Pointer to Ethernet device structure. 3072 * @param enable 3073 * 0 - promiscuous is disabled, otherwise - enabled 3074 * 3075 * @return 3076 * 0 on success, a negative error value otherwise 3077 */ 3078 int 3079 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 3080 { 3081 struct mlx5_priv *priv = dev->data->dev_private; 3082 3083 return mlx5_nl_promisc(priv->nl_socket_route, 3084 mlx5_ifindex(dev), !!enable); 3085 } 3086 3087 /** 3088 * Set device promiscuous mode 3089 * 3090 * @param dev 3091 * Pointer to Ethernet device structure. 3092 * @param enable 3093 * 0 - all multicase is disabled, otherwise - enabled 3094 * 3095 * @return 3096 * 0 on success, a negative error value otherwise 3097 */ 3098 int 3099 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 3100 { 3101 struct mlx5_priv *priv = dev->data->dev_private; 3102 3103 return mlx5_nl_allmulti(priv->nl_socket_route, 3104 mlx5_ifindex(dev), !!enable); 3105 } 3106 3107 /** 3108 * Flush device MAC addresses 3109 * 3110 * @param dev 3111 * Pointer to Ethernet device structure. 3112 * 3113 */ 3114 void 3115 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 3116 { 3117 struct mlx5_priv *priv = dev->data->dev_private; 3118 3119 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 3120 dev->data->mac_addrs, 3121 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 3122 } 3123