1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <ethdev_driver.h> 20 #include <ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_bus_auxiliary.h> 24 #include <rte_common.h> 25 #include <rte_kvargs.h> 26 #include <rte_rwlock.h> 27 #include <rte_spinlock.h> 28 #include <rte_string_fns.h> 29 #include <rte_alarm.h> 30 #include <rte_eal_paging.h> 31 32 #include <mlx5_glue.h> 33 #include <mlx5_devx_cmds.h> 34 #include <mlx5_common.h> 35 #include <mlx5_common_mp.h> 36 #include <mlx5_common_mr.h> 37 #include <mlx5_malloc.h> 38 39 #include "mlx5_defs.h" 40 #include "mlx5.h" 41 #include "mlx5_common_os.h" 42 #include "mlx5_utils.h" 43 #include "mlx5_rxtx.h" 44 #include "mlx5_rx.h" 45 #include "mlx5_tx.h" 46 #include "mlx5_autoconf.h" 47 #include "mlx5_flow.h" 48 #include "rte_pmd_mlx5.h" 49 #include "mlx5_verbs.h" 50 #include "mlx5_nl.h" 51 #include "mlx5_devx.h" 52 53 #ifndef HAVE_IBV_MLX5_MOD_MPW 54 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 55 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 56 #endif 57 58 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 59 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 60 #endif 61 62 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 63 64 /* Spinlock for mlx5_shared_data allocation. */ 65 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 66 67 /* Process local data for secondary processes. */ 68 static struct mlx5_local_data mlx5_local_data; 69 70 /* rte flow indexed pool configuration. */ 71 static struct mlx5_indexed_pool_config icfg[] = { 72 { 73 .size = sizeof(struct rte_flow), 74 .trunk_size = 64, 75 .need_lock = 1, 76 .release_mem_en = 0, 77 .malloc = mlx5_malloc, 78 .free = mlx5_free, 79 .per_core_cache = 0, 80 .type = "ctl_flow_ipool", 81 }, 82 { 83 .size = sizeof(struct rte_flow), 84 .trunk_size = 64, 85 .grow_trunk = 3, 86 .grow_shift = 2, 87 .need_lock = 1, 88 .release_mem_en = 0, 89 .malloc = mlx5_malloc, 90 .free = mlx5_free, 91 .per_core_cache = 1 << 14, 92 .type = "rte_flow_ipool", 93 }, 94 { 95 .size = sizeof(struct rte_flow), 96 .trunk_size = 64, 97 .grow_trunk = 3, 98 .grow_shift = 2, 99 .need_lock = 1, 100 .release_mem_en = 0, 101 .malloc = mlx5_malloc, 102 .free = mlx5_free, 103 .per_core_cache = 0, 104 .type = "mcp_flow_ipool", 105 }, 106 }; 107 108 /** 109 * Set the completion channel file descriptor interrupt as non-blocking. 110 * 111 * @param[in] rxq_obj 112 * Pointer to RQ channel object, which includes the channel fd 113 * 114 * @param[out] fd 115 * The file descriptor (representing the intetrrupt) used in this channel. 116 * 117 * @return 118 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 119 */ 120 int 121 mlx5_os_set_nonblock_channel_fd(int fd) 122 { 123 int flags; 124 125 flags = fcntl(fd, F_GETFL); 126 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 127 } 128 129 /** 130 * Get mlx5 device attributes. The glue function query_device_ex() is called 131 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 132 * device attributes from the glue out parameter. 133 * 134 * @param cdev 135 * Pointer to mlx5 device. 136 * 137 * @param device_attr 138 * Pointer to mlx5 device attributes. 139 * 140 * @return 141 * 0 on success, non zero error number otherwise 142 */ 143 int 144 mlx5_os_get_dev_attr(struct mlx5_common_device *cdev, 145 struct mlx5_dev_attr *device_attr) 146 { 147 int err; 148 struct ibv_context *ctx = cdev->ctx; 149 struct ibv_device_attr_ex attr_ex; 150 151 memset(device_attr, 0, sizeof(*device_attr)); 152 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 153 if (err) 154 return err; 155 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 156 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 157 device_attr->max_sge = attr_ex.orig_attr.max_sge; 158 device_attr->max_cq = attr_ex.orig_attr.max_cq; 159 device_attr->max_cqe = attr_ex.orig_attr.max_cqe; 160 device_attr->max_mr = attr_ex.orig_attr.max_mr; 161 device_attr->max_pd = attr_ex.orig_attr.max_pd; 162 device_attr->max_qp = attr_ex.orig_attr.max_qp; 163 device_attr->max_srq = attr_ex.orig_attr.max_srq; 164 device_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr; 165 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 166 device_attr->max_rwq_indirection_table_size = 167 attr_ex.rss_caps.max_rwq_indirection_table_size; 168 device_attr->max_tso = attr_ex.tso_caps.max_tso; 169 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 170 171 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 172 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 173 if (err) 174 return err; 175 176 device_attr->flags = dv_attr.flags; 177 device_attr->comp_mask = dv_attr.comp_mask; 178 #ifdef HAVE_IBV_MLX5_MOD_SWP 179 device_attr->sw_parsing_offloads = 180 dv_attr.sw_parsing_caps.sw_parsing_offloads; 181 #endif 182 device_attr->min_single_stride_log_num_of_bytes = 183 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 184 device_attr->max_single_stride_log_num_of_bytes = 185 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 186 device_attr->min_single_wqe_log_num_of_strides = 187 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 188 device_attr->max_single_wqe_log_num_of_strides = 189 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 190 device_attr->stride_supported_qpts = 191 dv_attr.striding_rq_caps.supported_qpts; 192 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 193 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 194 #endif 195 strlcpy(device_attr->fw_ver, attr_ex.orig_attr.fw_ver, 196 sizeof(device_attr->fw_ver)); 197 198 return err; 199 } 200 201 /** 202 * Detect misc5 support or not 203 * 204 * @param[in] priv 205 * Device private data pointer 206 */ 207 #ifdef HAVE_MLX5DV_DR 208 static void 209 __mlx5_discovery_misc5_cap(struct mlx5_priv *priv) 210 { 211 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 212 /* Dummy VxLAN matcher to detect rdma-core misc5 cap 213 * Case: IPv4--->UDP--->VxLAN--->vni 214 */ 215 void *tbl; 216 struct mlx5_flow_dv_match_params matcher_mask; 217 void *match_m; 218 void *matcher; 219 void *headers_m; 220 void *misc5_m; 221 uint32_t *tunnel_header_m; 222 struct mlx5dv_flow_matcher_attr dv_attr; 223 224 memset(&matcher_mask, 0, sizeof(matcher_mask)); 225 matcher_mask.size = sizeof(matcher_mask.buf); 226 match_m = matcher_mask.buf; 227 headers_m = MLX5_ADDR_OF(fte_match_param, match_m, outer_headers); 228 misc5_m = MLX5_ADDR_OF(fte_match_param, 229 match_m, misc_parameters_5); 230 tunnel_header_m = (uint32_t *) 231 MLX5_ADDR_OF(fte_match_set_misc5, 232 misc5_m, tunnel_header_1); 233 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff); 234 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 4); 235 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff); 236 *tunnel_header_m = 0xffffff; 237 238 tbl = mlx5_glue->dr_create_flow_tbl(priv->sh->rx_domain, 1); 239 if (!tbl) { 240 DRV_LOG(INFO, "No SW steering support"); 241 return; 242 } 243 dv_attr.type = IBV_FLOW_ATTR_NORMAL, 244 dv_attr.match_mask = (void *)&matcher_mask, 245 dv_attr.match_criteria_enable = 246 (1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT) | 247 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT); 248 dv_attr.priority = 3; 249 #ifdef HAVE_MLX5DV_DR_ESWITCH 250 void *misc2_m; 251 if (priv->config.dv_esw_en) { 252 /* FDB enabled reg_c_0 */ 253 dv_attr.match_criteria_enable |= 254 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT); 255 misc2_m = MLX5_ADDR_OF(fte_match_param, 256 match_m, misc_parameters_2); 257 MLX5_SET(fte_match_set_misc2, misc2_m, 258 metadata_reg_c_0, 0xffff); 259 } 260 #endif 261 matcher = mlx5_glue->dv_create_flow_matcher(priv->sh->cdev->ctx, 262 &dv_attr, tbl); 263 if (matcher) { 264 priv->sh->misc5_cap = 1; 265 mlx5_glue->dv_destroy_flow_matcher(matcher); 266 } 267 mlx5_glue->dr_destroy_flow_tbl(tbl); 268 #else 269 RTE_SET_USED(priv); 270 #endif 271 } 272 #endif 273 274 /** 275 * Initialize DR related data within private structure. 276 * Routine checks the reference counter and does actual 277 * resources creation/initialization only if counter is zero. 278 * 279 * @param[in] priv 280 * Pointer to the private device data structure. 281 * 282 * @return 283 * Zero on success, positive error code otherwise. 284 */ 285 static int 286 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 287 { 288 struct mlx5_dev_ctx_shared *sh = priv->sh; 289 char s[MLX5_NAME_SIZE] __rte_unused; 290 int err; 291 292 MLX5_ASSERT(sh && sh->refcnt); 293 if (sh->refcnt > 1) 294 return 0; 295 err = mlx5_alloc_table_hash_list(priv); 296 if (err) 297 goto error; 298 /* The resources below are only valid with DV support. */ 299 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 300 /* Init port id action list. */ 301 snprintf(s, sizeof(s), "%s_port_id_action_list", sh->ibdev_name); 302 sh->port_id_action_list = mlx5_list_create(s, sh, true, 303 flow_dv_port_id_create_cb, 304 flow_dv_port_id_match_cb, 305 flow_dv_port_id_remove_cb, 306 flow_dv_port_id_clone_cb, 307 flow_dv_port_id_clone_free_cb); 308 if (!sh->port_id_action_list) 309 goto error; 310 /* Init push vlan action list. */ 311 snprintf(s, sizeof(s), "%s_push_vlan_action_list", sh->ibdev_name); 312 sh->push_vlan_action_list = mlx5_list_create(s, sh, true, 313 flow_dv_push_vlan_create_cb, 314 flow_dv_push_vlan_match_cb, 315 flow_dv_push_vlan_remove_cb, 316 flow_dv_push_vlan_clone_cb, 317 flow_dv_push_vlan_clone_free_cb); 318 if (!sh->push_vlan_action_list) 319 goto error; 320 /* Init sample action list. */ 321 snprintf(s, sizeof(s), "%s_sample_action_list", sh->ibdev_name); 322 sh->sample_action_list = mlx5_list_create(s, sh, true, 323 flow_dv_sample_create_cb, 324 flow_dv_sample_match_cb, 325 flow_dv_sample_remove_cb, 326 flow_dv_sample_clone_cb, 327 flow_dv_sample_clone_free_cb); 328 if (!sh->sample_action_list) 329 goto error; 330 /* Init dest array action list. */ 331 snprintf(s, sizeof(s), "%s_dest_array_list", sh->ibdev_name); 332 sh->dest_array_list = mlx5_list_create(s, sh, true, 333 flow_dv_dest_array_create_cb, 334 flow_dv_dest_array_match_cb, 335 flow_dv_dest_array_remove_cb, 336 flow_dv_dest_array_clone_cb, 337 flow_dv_dest_array_clone_free_cb); 338 if (!sh->dest_array_list) 339 goto error; 340 /* Init shared flex parsers list, no need lcore_share */ 341 snprintf(s, sizeof(s), "%s_flex_parsers_list", sh->ibdev_name); 342 sh->flex_parsers_dv = mlx5_list_create(s, sh, false, 343 mlx5_flex_parser_create_cb, 344 mlx5_flex_parser_match_cb, 345 mlx5_flex_parser_remove_cb, 346 mlx5_flex_parser_clone_cb, 347 mlx5_flex_parser_clone_free_cb); 348 if (!sh->flex_parsers_dv) 349 goto error; 350 #endif 351 #ifdef HAVE_MLX5DV_DR 352 void *domain; 353 354 /* Reference counter is zero, we should initialize structures. */ 355 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 356 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 357 if (!domain) { 358 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 359 err = errno; 360 goto error; 361 } 362 sh->rx_domain = domain; 363 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 364 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 365 if (!domain) { 366 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 367 err = errno; 368 goto error; 369 } 370 sh->tx_domain = domain; 371 #ifdef HAVE_MLX5DV_DR_ESWITCH 372 if (priv->config.dv_esw_en) { 373 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 374 MLX5DV_DR_DOMAIN_TYPE_FDB); 375 if (!domain) { 376 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 377 err = errno; 378 goto error; 379 } 380 sh->fdb_domain = domain; 381 } 382 /* 383 * The drop action is just some dummy placeholder in rdma-core. It 384 * does not belong to domains and has no any attributes, and, can be 385 * shared by the entire device. 386 */ 387 sh->dr_drop_action = mlx5_glue->dr_create_flow_action_drop(); 388 if (!sh->dr_drop_action) { 389 DRV_LOG(ERR, "FDB mlx5dv_dr_create_flow_action_drop"); 390 err = errno; 391 goto error; 392 } 393 #endif 394 if (!sh->tunnel_hub && priv->config.dv_miss_info) 395 err = mlx5_alloc_tunnel_hub(sh); 396 if (err) { 397 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 398 goto error; 399 } 400 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 401 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 402 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 403 if (sh->fdb_domain) 404 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 405 } 406 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 407 if (!priv->config.allow_duplicate_pattern) { 408 #ifndef HAVE_MLX5_DR_ALLOW_DUPLICATE 409 DRV_LOG(WARNING, "Disallow duplicate pattern is not supported - maybe old rdma-core version?"); 410 #endif 411 mlx5_glue->dr_allow_duplicate_rules(sh->rx_domain, 0); 412 mlx5_glue->dr_allow_duplicate_rules(sh->tx_domain, 0); 413 if (sh->fdb_domain) 414 mlx5_glue->dr_allow_duplicate_rules(sh->fdb_domain, 0); 415 } 416 417 __mlx5_discovery_misc5_cap(priv); 418 #endif /* HAVE_MLX5DV_DR */ 419 sh->default_miss_action = 420 mlx5_glue->dr_create_flow_action_default_miss(); 421 if (!sh->default_miss_action) 422 DRV_LOG(WARNING, "Default miss action is not supported."); 423 LIST_INIT(&sh->shared_rxqs); 424 return 0; 425 error: 426 /* Rollback the created objects. */ 427 if (sh->rx_domain) { 428 mlx5_glue->dr_destroy_domain(sh->rx_domain); 429 sh->rx_domain = NULL; 430 } 431 if (sh->tx_domain) { 432 mlx5_glue->dr_destroy_domain(sh->tx_domain); 433 sh->tx_domain = NULL; 434 } 435 if (sh->fdb_domain) { 436 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 437 sh->fdb_domain = NULL; 438 } 439 if (sh->dr_drop_action) { 440 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 441 sh->dr_drop_action = NULL; 442 } 443 if (sh->pop_vlan_action) { 444 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 445 sh->pop_vlan_action = NULL; 446 } 447 if (sh->encaps_decaps) { 448 mlx5_hlist_destroy(sh->encaps_decaps); 449 sh->encaps_decaps = NULL; 450 } 451 if (sh->modify_cmds) { 452 mlx5_hlist_destroy(sh->modify_cmds); 453 sh->modify_cmds = NULL; 454 } 455 if (sh->tag_table) { 456 /* tags should be destroyed with flow before. */ 457 mlx5_hlist_destroy(sh->tag_table); 458 sh->tag_table = NULL; 459 } 460 if (sh->tunnel_hub) { 461 mlx5_release_tunnel_hub(sh, priv->dev_port); 462 sh->tunnel_hub = NULL; 463 } 464 mlx5_free_table_hash_list(priv); 465 if (sh->port_id_action_list) { 466 mlx5_list_destroy(sh->port_id_action_list); 467 sh->port_id_action_list = NULL; 468 } 469 if (sh->push_vlan_action_list) { 470 mlx5_list_destroy(sh->push_vlan_action_list); 471 sh->push_vlan_action_list = NULL; 472 } 473 if (sh->sample_action_list) { 474 mlx5_list_destroy(sh->sample_action_list); 475 sh->sample_action_list = NULL; 476 } 477 if (sh->dest_array_list) { 478 mlx5_list_destroy(sh->dest_array_list); 479 sh->dest_array_list = NULL; 480 } 481 return err; 482 } 483 484 /** 485 * Destroy DR related data within private structure. 486 * 487 * @param[in] priv 488 * Pointer to the private device data structure. 489 */ 490 void 491 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 492 { 493 struct mlx5_dev_ctx_shared *sh = priv->sh; 494 495 MLX5_ASSERT(sh && sh->refcnt); 496 if (sh->refcnt > 1) 497 return; 498 MLX5_ASSERT(LIST_EMPTY(&sh->shared_rxqs)); 499 #ifdef HAVE_MLX5DV_DR 500 if (sh->rx_domain) { 501 mlx5_glue->dr_destroy_domain(sh->rx_domain); 502 sh->rx_domain = NULL; 503 } 504 if (sh->tx_domain) { 505 mlx5_glue->dr_destroy_domain(sh->tx_domain); 506 sh->tx_domain = NULL; 507 } 508 #ifdef HAVE_MLX5DV_DR_ESWITCH 509 if (sh->fdb_domain) { 510 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 511 sh->fdb_domain = NULL; 512 } 513 if (sh->dr_drop_action) { 514 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 515 sh->dr_drop_action = NULL; 516 } 517 #endif 518 if (sh->pop_vlan_action) { 519 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 520 sh->pop_vlan_action = NULL; 521 } 522 #endif /* HAVE_MLX5DV_DR */ 523 if (sh->default_miss_action) 524 mlx5_glue->destroy_flow_action 525 (sh->default_miss_action); 526 if (sh->encaps_decaps) { 527 mlx5_hlist_destroy(sh->encaps_decaps); 528 sh->encaps_decaps = NULL; 529 } 530 if (sh->modify_cmds) { 531 mlx5_hlist_destroy(sh->modify_cmds); 532 sh->modify_cmds = NULL; 533 } 534 if (sh->tag_table) { 535 /* tags should be destroyed with flow before. */ 536 mlx5_hlist_destroy(sh->tag_table); 537 sh->tag_table = NULL; 538 } 539 if (sh->tunnel_hub) { 540 mlx5_release_tunnel_hub(sh, priv->dev_port); 541 sh->tunnel_hub = NULL; 542 } 543 mlx5_free_table_hash_list(priv); 544 if (sh->port_id_action_list) { 545 mlx5_list_destroy(sh->port_id_action_list); 546 sh->port_id_action_list = NULL; 547 } 548 if (sh->push_vlan_action_list) { 549 mlx5_list_destroy(sh->push_vlan_action_list); 550 sh->push_vlan_action_list = NULL; 551 } 552 if (sh->sample_action_list) { 553 mlx5_list_destroy(sh->sample_action_list); 554 sh->sample_action_list = NULL; 555 } 556 if (sh->dest_array_list) { 557 mlx5_list_destroy(sh->dest_array_list); 558 sh->dest_array_list = NULL; 559 } 560 } 561 562 /** 563 * Initialize shared data between primary and secondary process. 564 * 565 * A memzone is reserved by primary process and secondary processes attach to 566 * the memzone. 567 * 568 * @return 569 * 0 on success, a negative errno value otherwise and rte_errno is set. 570 */ 571 static int 572 mlx5_init_shared_data(void) 573 { 574 const struct rte_memzone *mz; 575 int ret = 0; 576 577 rte_spinlock_lock(&mlx5_shared_data_lock); 578 if (mlx5_shared_data == NULL) { 579 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 580 /* Allocate shared memory. */ 581 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 582 sizeof(*mlx5_shared_data), 583 SOCKET_ID_ANY, 0); 584 if (mz == NULL) { 585 DRV_LOG(ERR, 586 "Cannot allocate mlx5 shared data"); 587 ret = -rte_errno; 588 goto error; 589 } 590 mlx5_shared_data = mz->addr; 591 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 592 rte_spinlock_init(&mlx5_shared_data->lock); 593 } else { 594 /* Lookup allocated shared memory. */ 595 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 596 if (mz == NULL) { 597 DRV_LOG(ERR, 598 "Cannot attach mlx5 shared data"); 599 ret = -rte_errno; 600 goto error; 601 } 602 mlx5_shared_data = mz->addr; 603 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 604 } 605 } 606 error: 607 rte_spinlock_unlock(&mlx5_shared_data_lock); 608 return ret; 609 } 610 611 /** 612 * PMD global initialization. 613 * 614 * Independent from individual device, this function initializes global 615 * per-PMD data structures distinguishing primary and secondary processes. 616 * Hence, each initialization is called once per a process. 617 * 618 * @return 619 * 0 on success, a negative errno value otherwise and rte_errno is set. 620 */ 621 static int 622 mlx5_init_once(void) 623 { 624 struct mlx5_shared_data *sd; 625 struct mlx5_local_data *ld = &mlx5_local_data; 626 int ret = 0; 627 628 if (mlx5_init_shared_data()) 629 return -rte_errno; 630 sd = mlx5_shared_data; 631 MLX5_ASSERT(sd); 632 rte_spinlock_lock(&sd->lock); 633 switch (rte_eal_process_type()) { 634 case RTE_PROC_PRIMARY: 635 if (sd->init_done) 636 break; 637 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 638 mlx5_mp_os_primary_handle); 639 if (ret) 640 goto out; 641 sd->init_done = true; 642 break; 643 case RTE_PROC_SECONDARY: 644 if (ld->init_done) 645 break; 646 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 647 mlx5_mp_os_secondary_handle); 648 if (ret) 649 goto out; 650 ++sd->secondary_cnt; 651 ld->init_done = true; 652 break; 653 default: 654 break; 655 } 656 out: 657 rte_spinlock_unlock(&sd->lock); 658 return ret; 659 } 660 661 /** 662 * DV flow counter mode detect and config. 663 * 664 * @param dev 665 * Pointer to rte_eth_dev structure. 666 * 667 */ 668 static void 669 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 670 { 671 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 672 struct mlx5_priv *priv = dev->data->dev_private; 673 struct mlx5_dev_ctx_shared *sh = priv->sh; 674 bool fallback; 675 676 #ifndef HAVE_IBV_DEVX_ASYNC 677 fallback = true; 678 #else 679 fallback = false; 680 if (!sh->devx || !priv->config.dv_flow_en || 681 !priv->config.hca_attr.flow_counters_dump || 682 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 683 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 684 fallback = true; 685 #endif 686 if (fallback) 687 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 688 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 689 priv->config.hca_attr.flow_counters_dump, 690 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 691 /* Initialize fallback mode only on the port initializes sh. */ 692 if (sh->refcnt == 1) 693 sh->cmng.counter_fallback = fallback; 694 else if (fallback != sh->cmng.counter_fallback) 695 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 696 "with others:%d.", PORT_ID(priv), fallback); 697 #endif 698 } 699 700 /** 701 * DR flow drop action support detect. 702 * 703 * @param dev 704 * Pointer to rte_eth_dev structure. 705 * 706 */ 707 static void 708 mlx5_flow_drop_action_config(struct rte_eth_dev *dev __rte_unused) 709 { 710 #ifdef HAVE_MLX5DV_DR 711 struct mlx5_priv *priv = dev->data->dev_private; 712 713 if (!priv->config.dv_flow_en || !priv->sh->dr_drop_action) 714 return; 715 /** 716 * DR supports drop action placeholder when it is supported; 717 * otherwise, use the queue drop action. 718 */ 719 if (!priv->sh->drop_action_check_flag) { 720 if (!mlx5_flow_discover_dr_action_support(dev)) 721 priv->sh->dr_drop_action_en = 1; 722 priv->sh->drop_action_check_flag = 1; 723 } 724 if (priv->sh->dr_drop_action_en) 725 priv->root_drop_action = priv->sh->dr_drop_action; 726 else 727 priv->root_drop_action = priv->drop_queue.hrxq->action; 728 #endif 729 } 730 731 static void 732 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) 733 { 734 struct mlx5_priv *priv = dev->data->dev_private; 735 void *ctx = priv->sh->cdev->ctx; 736 737 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx); 738 if (!priv->q_counters) { 739 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0); 740 struct ibv_wq *wq; 741 742 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created " 743 "by DevX - fall-back to use the kernel driver global " 744 "queue counter.", dev->data->port_id); 745 /* Create WQ by kernel and query its queue counter ID. */ 746 if (cq) { 747 wq = mlx5_glue->create_wq(ctx, 748 &(struct ibv_wq_init_attr){ 749 .wq_type = IBV_WQT_RQ, 750 .max_wr = 1, 751 .max_sge = 1, 752 .pd = priv->sh->cdev->pd, 753 .cq = cq, 754 }); 755 if (wq) { 756 /* Counter is assigned only on RDY state. */ 757 int ret = mlx5_glue->modify_wq(wq, 758 &(struct ibv_wq_attr){ 759 .attr_mask = IBV_WQ_ATTR_STATE, 760 .wq_state = IBV_WQS_RDY, 761 }); 762 763 if (ret == 0) 764 mlx5_devx_cmd_wq_query(wq, 765 &priv->counter_set_id); 766 claim_zero(mlx5_glue->destroy_wq(wq)); 767 } 768 claim_zero(mlx5_glue->destroy_cq(cq)); 769 } 770 } else { 771 priv->counter_set_id = priv->q_counters->id; 772 } 773 if (priv->counter_set_id == 0) 774 DRV_LOG(INFO, "Part of the port %d statistics will not be " 775 "available.", dev->data->port_id); 776 } 777 778 /** 779 * Check if representor spawn info match devargs. 780 * 781 * @param spawn 782 * Verbs device parameters (name, port, switch_info) to spawn. 783 * @param eth_da 784 * Device devargs to probe. 785 * 786 * @return 787 * Match result. 788 */ 789 static bool 790 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn, 791 struct rte_eth_devargs *eth_da) 792 { 793 struct mlx5_switch_info *switch_info = &spawn->info; 794 unsigned int p, f; 795 uint16_t id; 796 uint16_t repr_id = mlx5_representor_id_encode(switch_info, 797 eth_da->type); 798 799 switch (eth_da->type) { 800 case RTE_ETH_REPRESENTOR_SF: 801 if (!(spawn->info.port_name == -1 && 802 switch_info->name_type == 803 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 804 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) { 805 rte_errno = EBUSY; 806 return false; 807 } 808 break; 809 case RTE_ETH_REPRESENTOR_VF: 810 /* Allows HPF representor index -1 as exception. */ 811 if (!(spawn->info.port_name == -1 && 812 switch_info->name_type == 813 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 814 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) { 815 rte_errno = EBUSY; 816 return false; 817 } 818 break; 819 case RTE_ETH_REPRESENTOR_NONE: 820 rte_errno = EBUSY; 821 return false; 822 default: 823 rte_errno = ENOTSUP; 824 DRV_LOG(ERR, "unsupported representor type"); 825 return false; 826 } 827 /* Check representor ID: */ 828 for (p = 0; p < eth_da->nb_ports; ++p) { 829 if (spawn->pf_bond < 0) { 830 /* For non-LAG mode, allow and ignore pf. */ 831 switch_info->pf_num = eth_da->ports[p]; 832 repr_id = mlx5_representor_id_encode(switch_info, 833 eth_da->type); 834 } 835 for (f = 0; f < eth_da->nb_representor_ports; ++f) { 836 id = MLX5_REPRESENTOR_ID 837 (eth_da->ports[p], eth_da->type, 838 eth_da->representor_ports[f]); 839 if (repr_id == id) 840 return true; 841 } 842 } 843 rte_errno = EBUSY; 844 return false; 845 } 846 847 /** 848 * Spawn an Ethernet device from Verbs information. 849 * 850 * @param dpdk_dev 851 * Backing DPDK device. 852 * @param spawn 853 * Verbs device parameters (name, port, switch_info) to spawn. 854 * @param config 855 * Device configuration parameters. 856 * @param eth_da 857 * Device arguments. 858 * 859 * @return 860 * A valid Ethernet device object on success, NULL otherwise and rte_errno 861 * is set. The following errors are defined: 862 * 863 * EBUSY: device is not supposed to be spawned. 864 * EEXIST: device is already spawned 865 */ 866 static struct rte_eth_dev * 867 mlx5_dev_spawn(struct rte_device *dpdk_dev, 868 struct mlx5_dev_spawn_data *spawn, 869 struct mlx5_dev_config *config, 870 struct rte_eth_devargs *eth_da) 871 { 872 const struct mlx5_switch_info *switch_info = &spawn->info; 873 struct mlx5_dev_ctx_shared *sh = NULL; 874 struct ibv_port_attr port_attr = { .state = IBV_PORT_NOP }; 875 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 876 struct rte_eth_dev *eth_dev = NULL; 877 struct mlx5_priv *priv = NULL; 878 int err = 0; 879 unsigned int hw_padding = 0; 880 unsigned int mps; 881 unsigned int mpls_en = 0; 882 unsigned int swp = 0; 883 unsigned int mprq = 0; 884 unsigned int mprq_min_stride_size_n = 0; 885 unsigned int mprq_max_stride_size_n = 0; 886 unsigned int mprq_min_stride_num_n = 0; 887 unsigned int mprq_max_stride_num_n = 0; 888 struct rte_ether_addr mac; 889 char name[RTE_ETH_NAME_MAX_LEN]; 890 int own_domain_id = 0; 891 uint16_t port_id; 892 struct mlx5_port_info vport_info = { .query_flags = 0 }; 893 int nl_rdma = -1; 894 int i; 895 896 /* Determine if this port representor is supposed to be spawned. */ 897 if (switch_info->representor && dpdk_dev->devargs && 898 !mlx5_representor_match(spawn, eth_da)) 899 return NULL; 900 /* Build device name. */ 901 if (spawn->pf_bond < 0) { 902 /* Single device. */ 903 if (!switch_info->representor) 904 strlcpy(name, dpdk_dev->name, sizeof(name)); 905 else 906 err = snprintf(name, sizeof(name), "%s_representor_%s%u", 907 dpdk_dev->name, 908 switch_info->name_type == 909 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 910 switch_info->port_name); 911 } else { 912 /* Bonding device. */ 913 if (!switch_info->representor) { 914 err = snprintf(name, sizeof(name), "%s_%s", 915 dpdk_dev->name, spawn->phys_dev_name); 916 } else { 917 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u", 918 dpdk_dev->name, spawn->phys_dev_name, 919 switch_info->ctrl_num, 920 switch_info->pf_num, 921 switch_info->name_type == 922 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 923 switch_info->port_name); 924 } 925 } 926 if (err >= (int)sizeof(name)) 927 DRV_LOG(WARNING, "device name overflow %s", name); 928 /* check if the device is already spawned */ 929 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 930 rte_errno = EEXIST; 931 return NULL; 932 } 933 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 934 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 935 struct mlx5_mp_id mp_id; 936 937 eth_dev = rte_eth_dev_attach_secondary(name); 938 if (eth_dev == NULL) { 939 DRV_LOG(ERR, "can not attach rte ethdev"); 940 rte_errno = ENOMEM; 941 return NULL; 942 } 943 eth_dev->device = dpdk_dev; 944 eth_dev->dev_ops = &mlx5_dev_sec_ops; 945 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 946 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 947 err = mlx5_proc_priv_init(eth_dev); 948 if (err) 949 return NULL; 950 mlx5_mp_id_init(&mp_id, eth_dev->data->port_id); 951 /* Receive command fd from primary process */ 952 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 953 if (err < 0) 954 goto err_secondary; 955 /* Remap UAR for Tx queues. */ 956 err = mlx5_tx_uar_init_secondary(eth_dev, err); 957 if (err) 958 goto err_secondary; 959 /* 960 * Ethdev pointer is still required as input since 961 * the primary device is not accessible from the 962 * secondary process. 963 */ 964 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 965 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 966 return eth_dev; 967 err_secondary: 968 mlx5_dev_close(eth_dev); 969 return NULL; 970 } 971 /* 972 * Some parameters ("tx_db_nc" in particularly) are needed in 973 * advance to create dv/verbs device context. We proceed the 974 * devargs here to get ones, and later proceed devargs again 975 * to override some hardware settings. 976 */ 977 err = mlx5_args(config, dpdk_dev->devargs); 978 if (err) { 979 err = rte_errno; 980 DRV_LOG(ERR, "failed to process device arguments: %s", 981 strerror(rte_errno)); 982 goto error; 983 } 984 if (config->dv_miss_info) { 985 if (switch_info->master || switch_info->representor) 986 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 987 } 988 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 989 if (!sh) 990 return NULL; 991 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 992 config->dest_tir = 1; 993 #endif 994 #ifdef HAVE_IBV_MLX5_MOD_SWP 995 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 996 #endif 997 /* 998 * Multi-packet send is supported by ConnectX-4 Lx PF as well 999 * as all ConnectX-5 devices. 1000 */ 1001 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1002 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 1003 #endif 1004 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1005 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 1006 #endif 1007 mlx5_glue->dv_query_device(sh->cdev->ctx, &dv_attr); 1008 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 1009 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 1010 DRV_LOG(DEBUG, "enhanced MPW is supported"); 1011 mps = MLX5_MPW_ENHANCED; 1012 } else { 1013 DRV_LOG(DEBUG, "MPW is supported"); 1014 mps = MLX5_MPW; 1015 } 1016 } else { 1017 DRV_LOG(DEBUG, "MPW isn't supported"); 1018 mps = MLX5_MPW_DISABLED; 1019 } 1020 #ifdef HAVE_IBV_MLX5_MOD_SWP 1021 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 1022 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 1023 DRV_LOG(DEBUG, "SWP support: %u", swp); 1024 #endif 1025 config->swp = swp & (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP | 1026 MLX5_SW_PARSING_TSO_CAP); 1027 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1028 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 1029 struct mlx5dv_striding_rq_caps mprq_caps = 1030 dv_attr.striding_rq_caps; 1031 1032 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 1033 mprq_caps.min_single_stride_log_num_of_bytes); 1034 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 1035 mprq_caps.max_single_stride_log_num_of_bytes); 1036 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 1037 mprq_caps.min_single_wqe_log_num_of_strides); 1038 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 1039 mprq_caps.max_single_wqe_log_num_of_strides); 1040 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 1041 mprq_caps.supported_qpts); 1042 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 1043 mprq = 1; 1044 mprq_min_stride_size_n = 1045 mprq_caps.min_single_stride_log_num_of_bytes; 1046 mprq_max_stride_size_n = 1047 mprq_caps.max_single_stride_log_num_of_bytes; 1048 mprq_min_stride_num_n = 1049 mprq_caps.min_single_wqe_log_num_of_strides; 1050 mprq_max_stride_num_n = 1051 mprq_caps.max_single_wqe_log_num_of_strides; 1052 } 1053 #endif 1054 /* Rx CQE compression is enabled by default. */ 1055 config->cqe_comp = 1; 1056 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1057 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 1058 config->tunnel_en = dv_attr.tunnel_offloads_caps & 1059 (MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN | 1060 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE | 1061 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE); 1062 } 1063 if (config->tunnel_en) { 1064 DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s", 1065 config->tunnel_en & 1066 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN ? "[VXLAN]" : "", 1067 config->tunnel_en & 1068 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE ? "[GRE]" : "", 1069 config->tunnel_en & 1070 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE ? "[GENEVE]" : "" 1071 ); 1072 } else { 1073 DRV_LOG(DEBUG, "tunnel offloading is not supported"); 1074 } 1075 #else 1076 DRV_LOG(WARNING, 1077 "tunnel offloading disabled due to old OFED/rdma-core version"); 1078 #endif 1079 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 1080 mpls_en = ((dv_attr.tunnel_offloads_caps & 1081 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 1082 (dv_attr.tunnel_offloads_caps & 1083 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 1084 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 1085 mpls_en ? "" : "not "); 1086 #else 1087 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 1088 " old OFED/rdma-core version or firmware configuration"); 1089 #endif 1090 config->mpls_en = mpls_en; 1091 nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1092 /* Check port status. */ 1093 if (spawn->phys_port <= UINT8_MAX) { 1094 /* Legacy Verbs api only support u8 port number. */ 1095 err = mlx5_glue->query_port(sh->cdev->ctx, spawn->phys_port, 1096 &port_attr); 1097 if (err) { 1098 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1099 goto error; 1100 } 1101 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1102 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1103 err = EINVAL; 1104 goto error; 1105 } 1106 } else if (nl_rdma >= 0) { 1107 /* IB doesn't allow more than 255 ports, must be Ethernet. */ 1108 err = mlx5_nl_port_state(nl_rdma, 1109 spawn->phys_dev_name, 1110 spawn->phys_port); 1111 if (err < 0) { 1112 DRV_LOG(INFO, "Failed to get netlink port state: %s", 1113 strerror(rte_errno)); 1114 err = -rte_errno; 1115 goto error; 1116 } 1117 port_attr.state = (enum ibv_port_state)err; 1118 } 1119 if (port_attr.state != IBV_PORT_ACTIVE) 1120 DRV_LOG(INFO, "port is not active: \"%s\" (%d)", 1121 mlx5_glue->port_state_str(port_attr.state), 1122 port_attr.state); 1123 /* Allocate private eth device data. */ 1124 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1125 sizeof(*priv), 1126 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1127 if (priv == NULL) { 1128 DRV_LOG(ERR, "priv allocation failure"); 1129 err = ENOMEM; 1130 goto error; 1131 } 1132 priv->sh = sh; 1133 priv->dev_port = spawn->phys_port; 1134 priv->pci_dev = spawn->pci_dev; 1135 priv->mtu = RTE_ETHER_MTU; 1136 /* Some internal functions rely on Netlink sockets, open them now. */ 1137 priv->nl_socket_rdma = nl_rdma; 1138 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1139 priv->representor = !!switch_info->representor; 1140 priv->master = !!switch_info->master; 1141 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1142 priv->vport_meta_tag = 0; 1143 priv->vport_meta_mask = 0; 1144 priv->pf_bond = spawn->pf_bond; 1145 1146 DRV_LOG(DEBUG, 1147 "dev_port=%u bus=%s pci=%s master=%d representor=%d pf_bond=%d\n", 1148 priv->dev_port, dpdk_dev->bus->name, 1149 priv->pci_dev ? priv->pci_dev->name : "NONE", 1150 priv->master, priv->representor, priv->pf_bond); 1151 1152 /* 1153 * If we have E-Switch we should determine the vport attributes. 1154 * E-Switch may use either source vport field or reg_c[0] metadata 1155 * register to match on vport index. The engaged part of metadata 1156 * register is defined by mask. 1157 */ 1158 if (switch_info->representor || switch_info->master) { 1159 err = mlx5_glue->devx_port_query(sh->cdev->ctx, 1160 spawn->phys_port, 1161 &vport_info); 1162 if (err) { 1163 DRV_LOG(WARNING, 1164 "Cannot query devx port %d on device %s", 1165 spawn->phys_port, spawn->phys_dev_name); 1166 vport_info.query_flags = 0; 1167 } 1168 } 1169 if (vport_info.query_flags & MLX5_PORT_QUERY_REG_C0) { 1170 priv->vport_meta_tag = vport_info.vport_meta_tag; 1171 priv->vport_meta_mask = vport_info.vport_meta_mask; 1172 if (!priv->vport_meta_mask) { 1173 DRV_LOG(ERR, 1174 "vport zero mask for port %d on bonding device %s", 1175 spawn->phys_port, spawn->phys_dev_name); 1176 err = ENOTSUP; 1177 goto error; 1178 } 1179 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 1180 DRV_LOG(ERR, 1181 "Invalid vport tag for port %d on bonding device %s", 1182 spawn->phys_port, spawn->phys_dev_name); 1183 err = ENOTSUP; 1184 goto error; 1185 } 1186 } 1187 if (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) { 1188 priv->vport_id = vport_info.vport_id; 1189 } else if (spawn->pf_bond >= 0 && 1190 (switch_info->representor || switch_info->master)) { 1191 DRV_LOG(ERR, 1192 "Cannot deduce vport index for port %d on bonding device %s", 1193 spawn->phys_port, spawn->phys_dev_name); 1194 err = ENOTSUP; 1195 goto error; 1196 } else { 1197 /* 1198 * Suppose vport index in compatible way. Kernel/rdma_core 1199 * support single E-Switch per PF configurations only and 1200 * vport_id field contains the vport index for associated VF, 1201 * which is deduced from representor port name. 1202 * For example, let's have the IB device port 10, it has 1203 * attached network device eth0, which has port name attribute 1204 * pf0vf2, we can deduce the VF number as 2, and set vport index 1205 * as 3 (2+1). This assigning schema should be changed if the 1206 * multiple E-Switch instances per PF configurations or/and PCI 1207 * subfunctions are added. 1208 */ 1209 priv->vport_id = switch_info->representor ? 1210 switch_info->port_name + 1 : -1; 1211 } 1212 priv->representor_id = mlx5_representor_id_encode(switch_info, 1213 eth_da->type); 1214 /* 1215 * Look for sibling devices in order to reuse their switch domain 1216 * if any, otherwise allocate one. 1217 */ 1218 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1219 const struct mlx5_priv *opriv = 1220 rte_eth_devices[port_id].data->dev_private; 1221 1222 if (!opriv || 1223 opriv->sh != priv->sh || 1224 opriv->domain_id == 1225 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1226 continue; 1227 priv->domain_id = opriv->domain_id; 1228 DRV_LOG(DEBUG, "dev_port-%u inherit domain_id=%u\n", 1229 priv->dev_port, priv->domain_id); 1230 break; 1231 } 1232 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1233 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1234 if (err) { 1235 err = rte_errno; 1236 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1237 strerror(rte_errno)); 1238 goto error; 1239 } 1240 own_domain_id = 1; 1241 DRV_LOG(DEBUG, "dev_port-%u new domain_id=%u\n", 1242 priv->dev_port, priv->domain_id); 1243 } 1244 /* Override some values set by hardware configuration. */ 1245 mlx5_args(config, dpdk_dev->devargs); 1246 err = mlx5_dev_check_sibling_config(priv, config, dpdk_dev); 1247 if (err) 1248 goto error; 1249 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1250 IBV_DEVICE_RAW_IP_CSUM); 1251 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1252 (config->hw_csum ? "" : "not ")); 1253 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1254 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1255 DRV_LOG(DEBUG, "counters are not supported"); 1256 #endif 1257 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 1258 if (config->dv_flow_en) { 1259 DRV_LOG(WARNING, "DV flow is not supported"); 1260 config->dv_flow_en = 0; 1261 } 1262 #endif 1263 config->ind_table_max_size = 1264 sh->device_attr.max_rwq_indirection_table_size; 1265 /* 1266 * Remove this check once DPDK supports larger/variable 1267 * indirection tables. 1268 */ 1269 if (config->ind_table_max_size > (unsigned int)RTE_ETH_RSS_RETA_SIZE_512) 1270 config->ind_table_max_size = RTE_ETH_RSS_RETA_SIZE_512; 1271 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1272 config->ind_table_max_size); 1273 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1274 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1275 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1276 (config->hw_vlan_strip ? "" : "not ")); 1277 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1278 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1279 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1280 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1281 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1282 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1283 IBV_DEVICE_PCI_WRITE_END_PADDING); 1284 #endif 1285 if (config->hw_padding && !hw_padding) { 1286 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1287 config->hw_padding = 0; 1288 } else if (config->hw_padding) { 1289 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1290 } 1291 config->tso = (sh->device_attr.max_tso > 0 && 1292 (sh->device_attr.tso_supported_qpts & 1293 (1 << IBV_QPT_RAW_PACKET))); 1294 if (config->tso) 1295 config->tso_max_payload_sz = sh->device_attr.max_tso; 1296 /* 1297 * MPW is disabled by default, while the Enhanced MPW is enabled 1298 * by default. 1299 */ 1300 if (config->mps == MLX5_ARG_UNSET) 1301 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1302 MLX5_MPW_DISABLED; 1303 else 1304 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1305 DRV_LOG(INFO, "%sMPS is %s", 1306 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1307 config->mps == MLX5_MPW ? "legacy " : "", 1308 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1309 if (sh->devx) { 1310 config->hca_attr = sh->cdev->config.hca_attr; 1311 sh->steering_format_version = 1312 config->hca_attr.steering_format_version; 1313 /* Check for LRO support. */ 1314 if (config->dest_tir && config->hca_attr.lro_cap && 1315 config->dv_flow_en) { 1316 /* TBD check tunnel lro caps. */ 1317 config->lro.supported = config->hca_attr.lro_cap; 1318 DRV_LOG(DEBUG, "Device supports LRO"); 1319 /* 1320 * If LRO timeout is not configured by application, 1321 * use the minimal supported value. 1322 */ 1323 if (!config->lro.timeout) 1324 config->lro.timeout = 1325 config->hca_attr.lro_timer_supported_periods[0]; 1326 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1327 config->lro.timeout); 1328 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1329 "required for coalescing is %d bytes", 1330 config->hca_attr.lro_min_mss_size); 1331 } 1332 #if defined(HAVE_MLX5DV_DR) && \ 1333 (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ 1334 defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) 1335 if (config->hca_attr.qos.sup && 1336 config->hca_attr.qos.flow_meter_old && 1337 config->dv_flow_en) { 1338 uint8_t reg_c_mask = 1339 config->hca_attr.qos.flow_meter_reg_c_ids; 1340 /* 1341 * Meter needs two REG_C's for color match and pre-sfx 1342 * flow match. Here get the REG_C for color match. 1343 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1344 */ 1345 reg_c_mask &= 0xfc; 1346 if (__builtin_popcount(reg_c_mask) < 1) { 1347 priv->mtr_en = 0; 1348 DRV_LOG(WARNING, "No available register for" 1349 " meter."); 1350 } else { 1351 /* 1352 * The meter color register is used by the 1353 * flow-hit feature as well. 1354 * The flow-hit feature must use REG_C_3 1355 * Prefer REG_C_3 if it is available. 1356 */ 1357 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) 1358 priv->mtr_color_reg = REG_C_3; 1359 else 1360 priv->mtr_color_reg = ffs(reg_c_mask) 1361 - 1 + REG_C_0; 1362 priv->mtr_en = 1; 1363 priv->mtr_reg_share = 1364 config->hca_attr.qos.flow_meter; 1365 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1366 priv->mtr_color_reg); 1367 } 1368 } 1369 if (config->hca_attr.qos.sup && 1370 config->hca_attr.qos.flow_meter_aso_sup) { 1371 uint32_t log_obj_size = 1372 rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1); 1373 if (log_obj_size >= 1374 config->hca_attr.qos.log_meter_aso_granularity && 1375 log_obj_size <= 1376 config->hca_attr.qos.log_meter_aso_max_alloc) 1377 sh->meter_aso_en = 1; 1378 } 1379 if (priv->mtr_en) { 1380 err = mlx5_aso_flow_mtrs_mng_init(priv->sh); 1381 if (err) { 1382 err = -err; 1383 goto error; 1384 } 1385 } 1386 if (config->hca_attr.flow.tunnel_header_0_1) 1387 sh->tunnel_header_0_1 = 1; 1388 #endif 1389 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1390 if (config->hca_attr.flow_hit_aso && 1391 priv->mtr_color_reg == REG_C_3) { 1392 sh->flow_hit_aso_en = 1; 1393 err = mlx5_flow_aso_age_mng_init(sh); 1394 if (err) { 1395 err = -err; 1396 goto error; 1397 } 1398 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1399 } 1400 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1401 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \ 1402 defined(HAVE_MLX5_DR_ACTION_ASO_CT) 1403 if (config->hca_attr.ct_offload && 1404 priv->mtr_color_reg == REG_C_3) { 1405 err = mlx5_flow_aso_ct_mng_init(sh); 1406 if (err) { 1407 err = -err; 1408 goto error; 1409 } 1410 DRV_LOG(DEBUG, "CT ASO is supported."); 1411 sh->ct_aso_en = 1; 1412 } 1413 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */ 1414 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1415 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1416 config->dv_flow_en) { 1417 priv->sampler_en = 1; 1418 DRV_LOG(DEBUG, "Sampler enabled!"); 1419 } else { 1420 priv->sampler_en = 0; 1421 if (!config->hca_attr.log_max_ft_sampler_num) 1422 DRV_LOG(WARNING, 1423 "No available register for sampler."); 1424 else 1425 DRV_LOG(DEBUG, "DV flow is not supported!"); 1426 } 1427 #endif 1428 } 1429 if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 && 1430 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) { 1431 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported"); 1432 config->cqe_comp = 0; 1433 } 1434 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 1435 (!sh->devx || !config->hca_attr.mini_cqe_resp_flow_tag)) { 1436 DRV_LOG(WARNING, "Flow Tag CQE compression" 1437 " format isn't supported."); 1438 config->cqe_comp = 0; 1439 } 1440 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 1441 (!sh->devx || !config->hca_attr.mini_cqe_resp_l3_l4_tag)) { 1442 DRV_LOG(WARNING, "L3/L4 Header CQE compression" 1443 " format isn't supported."); 1444 config->cqe_comp = 0; 1445 } 1446 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported", 1447 config->cqe_comp ? "" : "not "); 1448 if (config->tx_pp) { 1449 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1450 config->hca_attr.dev_freq_khz); 1451 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1452 config->hca_attr.qos.packet_pacing ? "" : "not "); 1453 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1454 config->hca_attr.cross_channel ? "" : "not "); 1455 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1456 config->hca_attr.wqe_index_ignore ? "" : "not "); 1457 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1458 config->hca_attr.non_wire_sq ? "" : "not "); 1459 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1460 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1461 config->hca_attr.log_max_static_sq_wq); 1462 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1463 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1464 if (!sh->devx) { 1465 DRV_LOG(ERR, "DevX is required for packet pacing"); 1466 err = ENODEV; 1467 goto error; 1468 } 1469 if (!config->hca_attr.qos.packet_pacing) { 1470 DRV_LOG(ERR, "Packet pacing is not supported"); 1471 err = ENODEV; 1472 goto error; 1473 } 1474 if (!config->hca_attr.cross_channel) { 1475 DRV_LOG(ERR, "Cross channel operations are" 1476 " required for packet pacing"); 1477 err = ENODEV; 1478 goto error; 1479 } 1480 if (!config->hca_attr.wqe_index_ignore) { 1481 DRV_LOG(ERR, "WQE index ignore feature is" 1482 " required for packet pacing"); 1483 err = ENODEV; 1484 goto error; 1485 } 1486 if (!config->hca_attr.non_wire_sq) { 1487 DRV_LOG(ERR, "Non-wire SQ feature is" 1488 " required for packet pacing"); 1489 err = ENODEV; 1490 goto error; 1491 } 1492 if (!config->hca_attr.log_max_static_sq_wq) { 1493 DRV_LOG(ERR, "Static WQE SQ feature is" 1494 " required for packet pacing"); 1495 err = ENODEV; 1496 goto error; 1497 } 1498 if (!config->hca_attr.qos.wqe_rate_pp) { 1499 DRV_LOG(ERR, "WQE rate mode is required" 1500 " for packet pacing"); 1501 err = ENODEV; 1502 goto error; 1503 } 1504 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1505 DRV_LOG(ERR, "DevX does not provide UAR offset," 1506 " can't create queues for packet pacing"); 1507 err = ENODEV; 1508 goto error; 1509 #endif 1510 } 1511 if (sh->devx) { 1512 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1513 1514 err = config->hca_attr.access_register_user ? 1515 mlx5_devx_cmd_register_read 1516 (sh->cdev->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1517 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1518 if (!err) { 1519 uint32_t ts_mode; 1520 1521 /* MTUTC register is read successfully. */ 1522 ts_mode = MLX5_GET(register_mtutc, reg, 1523 time_stamp_mode); 1524 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1525 config->rt_timestamp = 1; 1526 } else { 1527 /* Kernel does not support register reading. */ 1528 if (config->hca_attr.dev_freq_khz == 1529 (NS_PER_S / MS_PER_S)) 1530 config->rt_timestamp = 1; 1531 } 1532 } 1533 /* 1534 * If HW has bug working with tunnel packet decapsulation and 1535 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1536 * bit. Then RTE_ETH_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1537 */ 1538 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1539 config->hw_fcs_strip = 0; 1540 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1541 (config->hw_fcs_strip ? "" : "not ")); 1542 if (config->mprq.enabled && mprq) { 1543 if (config->mprq.stride_num_n && 1544 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1545 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1546 config->mprq.stride_num_n = 1547 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1548 mprq_min_stride_num_n), 1549 mprq_max_stride_num_n); 1550 DRV_LOG(WARNING, 1551 "the number of strides" 1552 " for Multi-Packet RQ is out of range," 1553 " setting default value (%u)", 1554 1 << config->mprq.stride_num_n); 1555 } 1556 if (config->mprq.stride_size_n && 1557 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1558 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1559 config->mprq.stride_size_n = 1560 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1561 mprq_min_stride_size_n), 1562 mprq_max_stride_size_n); 1563 DRV_LOG(WARNING, 1564 "the size of a stride" 1565 " for Multi-Packet RQ is out of range," 1566 " setting default value (%u)", 1567 1 << config->mprq.stride_size_n); 1568 } 1569 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1570 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1571 } else if (config->mprq.enabled && !mprq) { 1572 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1573 config->mprq.enabled = 0; 1574 } 1575 if (config->max_dump_files_num == 0) 1576 config->max_dump_files_num = 128; 1577 eth_dev = rte_eth_dev_allocate(name); 1578 if (eth_dev == NULL) { 1579 DRV_LOG(ERR, "can not allocate rte ethdev"); 1580 err = ENOMEM; 1581 goto error; 1582 } 1583 if (priv->representor) { 1584 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1585 eth_dev->data->representor_id = priv->representor_id; 1586 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1587 struct mlx5_priv *opriv = 1588 rte_eth_devices[port_id].data->dev_private; 1589 if (opriv && 1590 opriv->master && 1591 opriv->domain_id == priv->domain_id && 1592 opriv->sh == priv->sh) { 1593 eth_dev->data->backer_port_id = port_id; 1594 break; 1595 } 1596 } 1597 if (port_id >= RTE_MAX_ETHPORTS) 1598 eth_dev->data->backer_port_id = eth_dev->data->port_id; 1599 } 1600 priv->mp_id.port_id = eth_dev->data->port_id; 1601 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1602 /* 1603 * Store associated network device interface index. This index 1604 * is permanent throughout the lifetime of device. So, we may store 1605 * the ifindex here and use the cached value further. 1606 */ 1607 MLX5_ASSERT(spawn->ifindex); 1608 priv->if_index = spawn->ifindex; 1609 priv->lag_affinity_idx = sh->refcnt - 1; 1610 eth_dev->data->dev_private = priv; 1611 priv->dev_data = eth_dev->data; 1612 eth_dev->data->mac_addrs = priv->mac; 1613 eth_dev->device = dpdk_dev; 1614 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1615 /* Configure the first MAC address by default. */ 1616 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1617 DRV_LOG(ERR, 1618 "port %u cannot get MAC address, is mlx5_en" 1619 " loaded? (errno: %s)", 1620 eth_dev->data->port_id, strerror(rte_errno)); 1621 err = ENODEV; 1622 goto error; 1623 } 1624 DRV_LOG(INFO, 1625 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT, 1626 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac)); 1627 #ifdef RTE_LIBRTE_MLX5_DEBUG 1628 { 1629 char ifname[MLX5_NAMESIZE]; 1630 1631 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1632 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1633 eth_dev->data->port_id, ifname); 1634 else 1635 DRV_LOG(DEBUG, "port %u ifname is unknown", 1636 eth_dev->data->port_id); 1637 } 1638 #endif 1639 /* Get actual MTU if possible. */ 1640 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1641 if (err) { 1642 err = rte_errno; 1643 goto error; 1644 } 1645 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1646 priv->mtu); 1647 /* Initialize burst functions to prevent crashes before link-up. */ 1648 eth_dev->rx_pkt_burst = removed_rx_burst; 1649 eth_dev->tx_pkt_burst = removed_tx_burst; 1650 eth_dev->dev_ops = &mlx5_dev_ops; 1651 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1652 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1653 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1654 /* Register MAC address. */ 1655 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1656 if (config->vf && config->vf_nl_en) 1657 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1658 mlx5_ifindex(eth_dev), 1659 eth_dev->data->mac_addrs, 1660 MLX5_MAX_MAC_ADDRESSES); 1661 priv->ctrl_flows = 0; 1662 rte_spinlock_init(&priv->flow_list_lock); 1663 TAILQ_INIT(&priv->flow_meters); 1664 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR); 1665 if (!priv->mtr_profile_tbl) 1666 goto error; 1667 /* Bring Ethernet device up. */ 1668 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1669 eth_dev->data->port_id); 1670 mlx5_set_link_up(eth_dev); 1671 /* 1672 * Even though the interrupt handler is not installed yet, 1673 * interrupts will still trigger on the async_fd from 1674 * Verbs context returned by ibv_open_device(). 1675 */ 1676 mlx5_link_update(eth_dev, 0); 1677 #ifdef HAVE_MLX5DV_DR_ESWITCH 1678 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1679 (switch_info->representor || switch_info->master))) 1680 config->dv_esw_en = 0; 1681 #else 1682 config->dv_esw_en = 0; 1683 #endif 1684 /* Detect minimal data bytes to inline. */ 1685 mlx5_set_min_inline(spawn, config); 1686 /* Store device configuration on private structure. */ 1687 priv->config = *config; 1688 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 1689 icfg[i].release_mem_en = !!config->reclaim_mode; 1690 if (config->reclaim_mode) 1691 icfg[i].per_core_cache = 0; 1692 priv->flows[i] = mlx5_ipool_create(&icfg[i]); 1693 if (!priv->flows[i]) 1694 goto error; 1695 } 1696 /* Create context for virtual machine VLAN workaround. */ 1697 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1698 if (config->dv_flow_en) { 1699 err = mlx5_alloc_shared_dr(priv); 1700 if (err) 1701 goto error; 1702 if (mlx5_flex_item_port_init(eth_dev) < 0) 1703 goto error; 1704 } 1705 if (sh->devx && config->dv_flow_en && config->dest_tir) { 1706 priv->obj_ops = devx_obj_ops; 1707 mlx5_queue_counter_id_prepare(eth_dev); 1708 priv->obj_ops.lb_dummy_queue_create = 1709 mlx5_rxq_ibv_obj_dummy_lb_create; 1710 priv->obj_ops.lb_dummy_queue_release = 1711 mlx5_rxq_ibv_obj_dummy_lb_release; 1712 } else if (spawn->max_port > UINT8_MAX) { 1713 /* Verbs can't support ports larger than 255 by design. */ 1714 DRV_LOG(ERR, "must enable DV and ESW when RDMA link ports > 255"); 1715 err = ENOTSUP; 1716 goto error; 1717 } else { 1718 priv->obj_ops = ibv_obj_ops; 1719 } 1720 if (config->tx_pp && 1721 (priv->config.dv_esw_en || 1722 priv->obj_ops.txq_obj_new != mlx5_txq_devx_obj_new)) { 1723 /* 1724 * HAVE_MLX5DV_DEVX_UAR_OFFSET is required to support 1725 * packet pacing and already checked above. 1726 * Hence, we should only make sure the SQs will be created 1727 * with DevX, not with Verbs. 1728 * Verbs allocates the SQ UAR on its own and it can't be shared 1729 * with Clock Queue UAR as required for Tx scheduling. 1730 */ 1731 DRV_LOG(ERR, "Verbs SQs, UAR can't be shared as required for packet pacing"); 1732 err = ENODEV; 1733 goto error; 1734 } 1735 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1736 if (!priv->drop_queue.hrxq) 1737 goto error; 1738 /* Port representor shares the same max prioirity with pf port. */ 1739 if (!priv->sh->flow_priority_check_flag) { 1740 /* Supported Verbs flow priority number detection. */ 1741 err = mlx5_flow_discover_priorities(eth_dev); 1742 priv->sh->flow_max_priority = err; 1743 priv->sh->flow_priority_check_flag = 1; 1744 } else { 1745 err = priv->sh->flow_max_priority; 1746 } 1747 if (err < 0) { 1748 err = -err; 1749 goto error; 1750 } 1751 if (!priv->config.dv_esw_en && 1752 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1753 DRV_LOG(WARNING, "metadata mode %u is not supported " 1754 "(no E-Switch)", priv->config.dv_xmeta_en); 1755 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1756 } 1757 mlx5_set_metadata_mask(eth_dev); 1758 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1759 !priv->sh->dv_regc0_mask) { 1760 DRV_LOG(ERR, "metadata mode %u is not supported " 1761 "(no metadata reg_c[0] is available)", 1762 priv->config.dv_xmeta_en); 1763 err = ENOTSUP; 1764 goto error; 1765 } 1766 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true, 1767 mlx5_hrxq_create_cb, 1768 mlx5_hrxq_match_cb, 1769 mlx5_hrxq_remove_cb, 1770 mlx5_hrxq_clone_cb, 1771 mlx5_hrxq_clone_free_cb); 1772 if (!priv->hrxqs) 1773 goto error; 1774 rte_rwlock_init(&priv->ind_tbls_lock); 1775 /* Query availability of metadata reg_c's. */ 1776 if (!priv->sh->metadata_regc_check_flag) { 1777 err = mlx5_flow_discover_mreg_c(eth_dev); 1778 if (err < 0) { 1779 err = -err; 1780 goto error; 1781 } 1782 } 1783 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1784 DRV_LOG(DEBUG, 1785 "port %u extensive metadata register is not supported", 1786 eth_dev->data->port_id); 1787 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1788 DRV_LOG(ERR, "metadata mode %u is not supported " 1789 "(no metadata registers available)", 1790 priv->config.dv_xmeta_en); 1791 err = ENOTSUP; 1792 goto error; 1793 } 1794 } 1795 if (priv->config.dv_flow_en && 1796 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1797 mlx5_flow_ext_mreg_supported(eth_dev) && 1798 priv->sh->dv_regc0_mask) { 1799 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1800 MLX5_FLOW_MREG_HTABLE_SZ, 1801 false, true, eth_dev, 1802 flow_dv_mreg_create_cb, 1803 flow_dv_mreg_match_cb, 1804 flow_dv_mreg_remove_cb, 1805 flow_dv_mreg_clone_cb, 1806 flow_dv_mreg_clone_free_cb); 1807 if (!priv->mreg_cp_tbl) { 1808 err = ENOMEM; 1809 goto error; 1810 } 1811 } 1812 rte_spinlock_init(&priv->shared_act_sl); 1813 mlx5_flow_counter_mode_config(eth_dev); 1814 mlx5_flow_drop_action_config(eth_dev); 1815 if (priv->config.dv_flow_en) 1816 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1817 return eth_dev; 1818 error: 1819 if (priv) { 1820 if (priv->mreg_cp_tbl) 1821 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1822 if (priv->sh) 1823 mlx5_os_free_shared_dr(priv); 1824 if (priv->nl_socket_route >= 0) 1825 close(priv->nl_socket_route); 1826 if (priv->vmwa_context) 1827 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1828 if (eth_dev && priv->drop_queue.hrxq) 1829 mlx5_drop_action_destroy(eth_dev); 1830 if (priv->mtr_profile_tbl) 1831 mlx5_l3t_destroy(priv->mtr_profile_tbl); 1832 if (own_domain_id) 1833 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1834 if (priv->hrxqs) 1835 mlx5_list_destroy(priv->hrxqs); 1836 if (eth_dev && priv->flex_item_map) 1837 mlx5_flex_item_port_cleanup(eth_dev); 1838 mlx5_free(priv); 1839 if (eth_dev != NULL) 1840 eth_dev->data->dev_private = NULL; 1841 } 1842 if (eth_dev != NULL) { 1843 /* mac_addrs must not be freed alone because part of 1844 * dev_private 1845 **/ 1846 eth_dev->data->mac_addrs = NULL; 1847 rte_eth_dev_release_port(eth_dev); 1848 } 1849 if (sh) 1850 mlx5_free_shared_dev_ctx(sh); 1851 if (nl_rdma >= 0) 1852 close(nl_rdma); 1853 MLX5_ASSERT(err > 0); 1854 rte_errno = err; 1855 return NULL; 1856 } 1857 1858 /** 1859 * Comparison callback to sort device data. 1860 * 1861 * This is meant to be used with qsort(). 1862 * 1863 * @param a[in] 1864 * Pointer to pointer to first data object. 1865 * @param b[in] 1866 * Pointer to pointer to second data object. 1867 * 1868 * @return 1869 * 0 if both objects are equal, less than 0 if the first argument is less 1870 * than the second, greater than 0 otherwise. 1871 */ 1872 static int 1873 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1874 { 1875 const struct mlx5_switch_info *si_a = 1876 &((const struct mlx5_dev_spawn_data *)a)->info; 1877 const struct mlx5_switch_info *si_b = 1878 &((const struct mlx5_dev_spawn_data *)b)->info; 1879 int ret; 1880 1881 /* Master device first. */ 1882 ret = si_b->master - si_a->master; 1883 if (ret) 1884 return ret; 1885 /* Then representor devices. */ 1886 ret = si_b->representor - si_a->representor; 1887 if (ret) 1888 return ret; 1889 /* Unidentified devices come last in no specific order. */ 1890 if (!si_a->representor) 1891 return 0; 1892 /* Order representors by name. */ 1893 return si_a->port_name - si_b->port_name; 1894 } 1895 1896 /** 1897 * Match PCI information for possible slaves of bonding device. 1898 * 1899 * @param[in] ibdev_name 1900 * Name of Infiniband device. 1901 * @param[in] pci_dev 1902 * Pointer to primary PCI address structure to match. 1903 * @param[in] nl_rdma 1904 * Netlink RDMA group socket handle. 1905 * @param[in] owner 1906 * Representor owner PF index. 1907 * @param[out] bond_info 1908 * Pointer to bonding information. 1909 * 1910 * @return 1911 * negative value if no bonding device found, otherwise 1912 * positive index of slave PF in bonding. 1913 */ 1914 static int 1915 mlx5_device_bond_pci_match(const char *ibdev_name, 1916 const struct rte_pci_addr *pci_dev, 1917 int nl_rdma, uint16_t owner, 1918 struct mlx5_bond_info *bond_info) 1919 { 1920 char ifname[IF_NAMESIZE + 1]; 1921 unsigned int ifindex; 1922 unsigned int np, i; 1923 FILE *bond_file = NULL, *file; 1924 int pf = -1; 1925 int ret; 1926 uint8_t cur_guid[32] = {0}; 1927 uint8_t guid[32] = {0}; 1928 1929 /* 1930 * Try to get master device name. If something goes wrong suppose 1931 * the lack of kernel support and no bonding devices. 1932 */ 1933 memset(bond_info, 0, sizeof(*bond_info)); 1934 if (nl_rdma < 0) 1935 return -1; 1936 if (!strstr(ibdev_name, "bond")) 1937 return -1; 1938 np = mlx5_nl_portnum(nl_rdma, ibdev_name); 1939 if (!np) 1940 return -1; 1941 if (mlx5_get_device_guid(pci_dev, cur_guid, sizeof(cur_guid)) < 0) 1942 return -1; 1943 /* 1944 * The master device might not be on the predefined port(not on port 1945 * index 1, it is not guaranteed), we have to scan all Infiniband 1946 * device ports and find master. 1947 */ 1948 for (i = 1; i <= np; ++i) { 1949 /* Check whether Infiniband port is populated. */ 1950 ifindex = mlx5_nl_ifindex(nl_rdma, ibdev_name, i); 1951 if (!ifindex) 1952 continue; 1953 if (!if_indextoname(ifindex, ifname)) 1954 continue; 1955 /* Try to read bonding slave names from sysfs. */ 1956 MKSTR(slaves, 1957 "/sys/class/net/%s/master/bonding/slaves", ifname); 1958 bond_file = fopen(slaves, "r"); 1959 if (bond_file) 1960 break; 1961 } 1962 if (!bond_file) 1963 return -1; 1964 /* Use safe format to check maximal buffer length. */ 1965 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1966 while (fscanf(bond_file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1967 char tmp_str[IF_NAMESIZE + 32]; 1968 struct rte_pci_addr pci_addr; 1969 struct mlx5_switch_info info; 1970 int ret; 1971 1972 /* Process slave interface names in the loop. */ 1973 snprintf(tmp_str, sizeof(tmp_str), 1974 "/sys/class/net/%s", ifname); 1975 if (mlx5_get_pci_addr(tmp_str, &pci_addr)) { 1976 DRV_LOG(WARNING, 1977 "Cannot get PCI address for netdev \"%s\".", 1978 ifname); 1979 continue; 1980 } 1981 /* Slave interface PCI address match found. */ 1982 snprintf(tmp_str, sizeof(tmp_str), 1983 "/sys/class/net/%s/phys_port_name", ifname); 1984 file = fopen(tmp_str, "rb"); 1985 if (!file) 1986 break; 1987 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1988 if (fscanf(file, "%32s", tmp_str) == 1) 1989 mlx5_translate_port_name(tmp_str, &info); 1990 fclose(file); 1991 /* Only process PF ports. */ 1992 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY && 1993 info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1994 continue; 1995 /* Check max bonding member. */ 1996 if (info.port_name >= MLX5_BOND_MAX_PORTS) { 1997 DRV_LOG(WARNING, "bonding index out of range, " 1998 "please increase MLX5_BOND_MAX_PORTS: %s", 1999 tmp_str); 2000 break; 2001 } 2002 /* Get ifindex. */ 2003 snprintf(tmp_str, sizeof(tmp_str), 2004 "/sys/class/net/%s/ifindex", ifname); 2005 file = fopen(tmp_str, "rb"); 2006 if (!file) 2007 break; 2008 ret = fscanf(file, "%u", &ifindex); 2009 fclose(file); 2010 if (ret != 1) 2011 break; 2012 /* Save bonding info. */ 2013 strncpy(bond_info->ports[info.port_name].ifname, ifname, 2014 sizeof(bond_info->ports[0].ifname)); 2015 bond_info->ports[info.port_name].pci_addr = pci_addr; 2016 bond_info->ports[info.port_name].ifindex = ifindex; 2017 bond_info->n_port++; 2018 /* 2019 * Under socket direct mode, bonding will use 2020 * system_image_guid as identification. 2021 * After OFED 5.4, guid is readable (ret >= 0) under sysfs. 2022 * All bonding members should have the same guid even if driver 2023 * is using PCIe BDF. 2024 */ 2025 ret = mlx5_get_device_guid(&pci_addr, guid, sizeof(guid)); 2026 if (ret < 0) 2027 break; 2028 else if (ret > 0) { 2029 if (!memcmp(guid, cur_guid, sizeof(guid)) && 2030 owner == info.port_name && 2031 (owner != 0 || (owner == 0 && 2032 !rte_pci_addr_cmp(pci_dev, &pci_addr)))) 2033 pf = info.port_name; 2034 } else if (pci_dev->domain == pci_addr.domain && 2035 pci_dev->bus == pci_addr.bus && 2036 pci_dev->devid == pci_addr.devid && 2037 ((pci_dev->function == 0 && 2038 pci_dev->function + owner == pci_addr.function) || 2039 (pci_dev->function == owner && 2040 pci_addr.function == owner))) 2041 pf = info.port_name; 2042 } 2043 if (pf >= 0) { 2044 /* Get bond interface info */ 2045 ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex, 2046 bond_info->ifname); 2047 if (ret) 2048 DRV_LOG(ERR, "unable to get bond info: %s", 2049 strerror(rte_errno)); 2050 else 2051 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 2052 ifindex, bond_info->ifindex, bond_info->ifname); 2053 } 2054 if (owner == 0 && pf != 0) { 2055 DRV_LOG(INFO, "PCIe instance %04x:%02x:%02x.%x isn't bonding owner", 2056 pci_dev->domain, pci_dev->bus, pci_dev->devid, 2057 pci_dev->function); 2058 } 2059 return pf; 2060 } 2061 2062 static void 2063 mlx5_os_config_default(struct mlx5_dev_config *config) 2064 { 2065 memset(config, 0, sizeof(*config)); 2066 config->mps = MLX5_ARG_UNSET; 2067 config->rx_vec_en = 1; 2068 config->txq_inline_max = MLX5_ARG_UNSET; 2069 config->txq_inline_min = MLX5_ARG_UNSET; 2070 config->txq_inline_mpw = MLX5_ARG_UNSET; 2071 config->txqs_inline = MLX5_ARG_UNSET; 2072 config->vf_nl_en = 1; 2073 config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2074 config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2075 config->dv_esw_en = 1; 2076 config->dv_flow_en = 1; 2077 config->decap_en = 1; 2078 config->log_hp_size = MLX5_ARG_UNSET; 2079 config->allow_duplicate_pattern = 1; 2080 } 2081 2082 /** 2083 * Register a PCI device within bonding. 2084 * 2085 * This function spawns Ethernet devices out of a given PCI device and 2086 * bonding owner PF index. 2087 * 2088 * @param[in] cdev 2089 * Pointer to common mlx5 device structure. 2090 * @param[in] req_eth_da 2091 * Requested ethdev device argument. 2092 * @param[in] owner_id 2093 * Requested owner PF port ID within bonding device, default to 0. 2094 * 2095 * @return 2096 * 0 on success, a negative errno value otherwise and rte_errno is set. 2097 */ 2098 static int 2099 mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, 2100 struct rte_eth_devargs *req_eth_da, 2101 uint16_t owner_id) 2102 { 2103 struct ibv_device **ibv_list; 2104 /* 2105 * Number of found IB Devices matching with requested PCI BDF. 2106 * nd != 1 means there are multiple IB devices over the same 2107 * PCI device and we have representors and master. 2108 */ 2109 unsigned int nd = 0; 2110 /* 2111 * Number of found IB device Ports. nd = 1 and np = 1..n means 2112 * we have the single multiport IB device, and there may be 2113 * representors attached to some of found ports. 2114 */ 2115 unsigned int np = 0; 2116 /* 2117 * Number of DPDK ethernet devices to Spawn - either over 2118 * multiple IB devices or multiple ports of single IB device. 2119 * Actually this is the number of iterations to spawn. 2120 */ 2121 unsigned int ns = 0; 2122 /* 2123 * Bonding device 2124 * < 0 - no bonding device (single one) 2125 * >= 0 - bonding device (value is slave PF index) 2126 */ 2127 int bd = -1; 2128 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev); 2129 struct mlx5_dev_spawn_data *list = NULL; 2130 struct mlx5_dev_config dev_config; 2131 unsigned int dev_config_vf; 2132 struct rte_eth_devargs eth_da = *req_eth_da; 2133 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */ 2134 struct mlx5_bond_info bond_info; 2135 int ret = -1; 2136 2137 errno = 0; 2138 ibv_list = mlx5_glue->get_device_list(&ret); 2139 if (!ibv_list) { 2140 rte_errno = errno ? errno : ENOSYS; 2141 DRV_LOG(ERR, "Cannot list devices, is ib_uverbs loaded?"); 2142 return -rte_errno; 2143 } 2144 /* 2145 * First scan the list of all Infiniband devices to find 2146 * matching ones, gathering into the list. 2147 */ 2148 struct ibv_device *ibv_match[ret + 1]; 2149 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 2150 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 2151 unsigned int i; 2152 2153 while (ret-- > 0) { 2154 struct rte_pci_addr pci_addr; 2155 2156 DRV_LOG(DEBUG, "Checking device \"%s\"", ibv_list[ret]->name); 2157 bd = mlx5_device_bond_pci_match(ibv_list[ret]->name, &owner_pci, 2158 nl_rdma, owner_id, &bond_info); 2159 if (bd >= 0) { 2160 /* 2161 * Bonding device detected. Only one match is allowed, 2162 * the bonding is supported over multi-port IB device, 2163 * there should be no matches on representor PCI 2164 * functions or non VF LAG bonding devices with 2165 * specified address. 2166 */ 2167 if (nd) { 2168 DRV_LOG(ERR, 2169 "multiple PCI match on bonding device" 2170 "\"%s\" found", ibv_list[ret]->name); 2171 rte_errno = ENOENT; 2172 ret = -rte_errno; 2173 goto exit; 2174 } 2175 /* Amend owner pci address if owner PF ID specified. */ 2176 if (eth_da.nb_representor_ports) 2177 owner_pci.function += owner_id; 2178 DRV_LOG(INFO, 2179 "PCI information matches for slave %d bonding device \"%s\"", 2180 bd, ibv_list[ret]->name); 2181 ibv_match[nd++] = ibv_list[ret]; 2182 break; 2183 } else { 2184 /* Bonding device not found. */ 2185 if (mlx5_get_pci_addr(ibv_list[ret]->ibdev_path, 2186 &pci_addr)) 2187 continue; 2188 if (owner_pci.domain != pci_addr.domain || 2189 owner_pci.bus != pci_addr.bus || 2190 owner_pci.devid != pci_addr.devid || 2191 owner_pci.function != pci_addr.function) 2192 continue; 2193 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 2194 ibv_list[ret]->name); 2195 ibv_match[nd++] = ibv_list[ret]; 2196 } 2197 } 2198 ibv_match[nd] = NULL; 2199 if (!nd) { 2200 /* No device matches, just complain and bail out. */ 2201 DRV_LOG(WARNING, 2202 "No Verbs device matches PCI device " PCI_PRI_FMT "," 2203 " are kernel drivers loaded?", 2204 owner_pci.domain, owner_pci.bus, 2205 owner_pci.devid, owner_pci.function); 2206 rte_errno = ENOENT; 2207 ret = -rte_errno; 2208 goto exit; 2209 } 2210 if (nd == 1) { 2211 /* 2212 * Found single matching device may have multiple ports. 2213 * Each port may be representor, we have to check the port 2214 * number and check the representors existence. 2215 */ 2216 if (nl_rdma >= 0) 2217 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 2218 if (!np) 2219 DRV_LOG(WARNING, 2220 "Cannot get IB device \"%s\" ports number.", 2221 ibv_match[0]->name); 2222 if (bd >= 0 && !np) { 2223 DRV_LOG(ERR, "Cannot get ports for bonding device."); 2224 rte_errno = ENOENT; 2225 ret = -rte_errno; 2226 goto exit; 2227 } 2228 } 2229 /* Now we can determine the maximal amount of devices to be spawned. */ 2230 list = mlx5_malloc(MLX5_MEM_ZERO, 2231 sizeof(struct mlx5_dev_spawn_data) * (np ? np : nd), 2232 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2233 if (!list) { 2234 DRV_LOG(ERR, "Spawn data array allocation failure."); 2235 rte_errno = ENOMEM; 2236 ret = -rte_errno; 2237 goto exit; 2238 } 2239 if (bd >= 0 || np > 1) { 2240 /* 2241 * Single IB device with multiple ports found, 2242 * it may be E-Switch master device and representors. 2243 * We have to perform identification through the ports. 2244 */ 2245 MLX5_ASSERT(nl_rdma >= 0); 2246 MLX5_ASSERT(ns == 0); 2247 MLX5_ASSERT(nd == 1); 2248 MLX5_ASSERT(np); 2249 for (i = 1; i <= np; ++i) { 2250 list[ns].bond_info = &bond_info; 2251 list[ns].max_port = np; 2252 list[ns].phys_port = i; 2253 list[ns].phys_dev_name = ibv_match[0]->name; 2254 list[ns].eth_dev = NULL; 2255 list[ns].pci_dev = pci_dev; 2256 list[ns].cdev = cdev; 2257 list[ns].pf_bond = bd; 2258 list[ns].ifindex = mlx5_nl_ifindex(nl_rdma, 2259 ibv_match[0]->name, 2260 i); 2261 if (!list[ns].ifindex) { 2262 /* 2263 * No network interface index found for the 2264 * specified port, it means there is no 2265 * representor on this port. It's OK, 2266 * there can be disabled ports, for example 2267 * if sriov_numvfs < sriov_totalvfs. 2268 */ 2269 continue; 2270 } 2271 ret = -1; 2272 if (nl_route >= 0) 2273 ret = mlx5_nl_switch_info(nl_route, 2274 list[ns].ifindex, 2275 &list[ns].info); 2276 if (ret || (!list[ns].info.representor && 2277 !list[ns].info.master)) { 2278 /* 2279 * We failed to recognize representors with 2280 * Netlink, let's try to perform the task 2281 * with sysfs. 2282 */ 2283 ret = mlx5_sysfs_switch_info(list[ns].ifindex, 2284 &list[ns].info); 2285 } 2286 if (!ret && bd >= 0) { 2287 switch (list[ns].info.name_type) { 2288 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 2289 if (np == 1) { 2290 /* 2291 * Force standalone bonding 2292 * device for ROCE LAG 2293 * confgiurations. 2294 */ 2295 list[ns].info.master = 0; 2296 list[ns].info.representor = 0; 2297 } 2298 if (list[ns].info.port_name == bd) 2299 ns++; 2300 break; 2301 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 2302 /* Fallthrough */ 2303 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 2304 /* Fallthrough */ 2305 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 2306 if (list[ns].info.pf_num == bd) 2307 ns++; 2308 break; 2309 default: 2310 break; 2311 } 2312 continue; 2313 } 2314 if (!ret && (list[ns].info.representor ^ 2315 list[ns].info.master)) 2316 ns++; 2317 } 2318 if (!ns) { 2319 DRV_LOG(ERR, 2320 "Unable to recognize master/representors on the IB device with multiple ports."); 2321 rte_errno = ENOENT; 2322 ret = -rte_errno; 2323 goto exit; 2324 } 2325 } else { 2326 /* 2327 * The existence of several matching entries (nd > 1) means 2328 * port representors have been instantiated. No existing Verbs 2329 * call nor sysfs entries can tell them apart, this can only 2330 * be done through Netlink calls assuming kernel drivers are 2331 * recent enough to support them. 2332 * 2333 * In the event of identification failure through Netlink, 2334 * try again through sysfs, then: 2335 * 2336 * 1. A single IB device matches (nd == 1) with single 2337 * port (np=0/1) and is not a representor, assume 2338 * no switch support. 2339 * 2340 * 2. Otherwise no safe assumptions can be made; 2341 * complain louder and bail out. 2342 */ 2343 for (i = 0; i != nd; ++i) { 2344 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2345 list[ns].bond_info = NULL; 2346 list[ns].max_port = 1; 2347 list[ns].phys_port = 1; 2348 list[ns].phys_dev_name = ibv_match[i]->name; 2349 list[ns].eth_dev = NULL; 2350 list[ns].pci_dev = pci_dev; 2351 list[ns].cdev = cdev; 2352 list[ns].pf_bond = -1; 2353 list[ns].ifindex = 0; 2354 if (nl_rdma >= 0) 2355 list[ns].ifindex = mlx5_nl_ifindex 2356 (nl_rdma, 2357 ibv_match[i]->name, 2358 1); 2359 if (!list[ns].ifindex) { 2360 char ifname[IF_NAMESIZE]; 2361 2362 /* 2363 * Netlink failed, it may happen with old 2364 * ib_core kernel driver (before 4.16). 2365 * We can assume there is old driver because 2366 * here we are processing single ports IB 2367 * devices. Let's try sysfs to retrieve 2368 * the ifindex. The method works for 2369 * master device only. 2370 */ 2371 if (nd > 1) { 2372 /* 2373 * Multiple devices found, assume 2374 * representors, can not distinguish 2375 * master/representor and retrieve 2376 * ifindex via sysfs. 2377 */ 2378 continue; 2379 } 2380 ret = mlx5_get_ifname_sysfs 2381 (ibv_match[i]->ibdev_path, ifname); 2382 if (!ret) 2383 list[ns].ifindex = 2384 if_nametoindex(ifname); 2385 if (!list[ns].ifindex) { 2386 /* 2387 * No network interface index found 2388 * for the specified device, it means 2389 * there it is neither representor 2390 * nor master. 2391 */ 2392 continue; 2393 } 2394 } 2395 ret = -1; 2396 if (nl_route >= 0) 2397 ret = mlx5_nl_switch_info(nl_route, 2398 list[ns].ifindex, 2399 &list[ns].info); 2400 if (ret || (!list[ns].info.representor && 2401 !list[ns].info.master)) { 2402 /* 2403 * We failed to recognize representors with 2404 * Netlink, let's try to perform the task 2405 * with sysfs. 2406 */ 2407 ret = mlx5_sysfs_switch_info(list[ns].ifindex, 2408 &list[ns].info); 2409 } 2410 if (!ret && (list[ns].info.representor ^ 2411 list[ns].info.master)) { 2412 ns++; 2413 } else if ((nd == 1) && 2414 !list[ns].info.representor && 2415 !list[ns].info.master) { 2416 /* 2417 * Single IB device with one physical port and 2418 * attached network device. 2419 * May be SRIOV is not enabled or there is no 2420 * representors. 2421 */ 2422 DRV_LOG(INFO, "No E-Switch support detected."); 2423 ns++; 2424 break; 2425 } 2426 } 2427 if (!ns) { 2428 DRV_LOG(ERR, 2429 "Unable to recognize master/representors on the multiple IB devices."); 2430 rte_errno = ENOENT; 2431 ret = -rte_errno; 2432 goto exit; 2433 } 2434 /* 2435 * New kernels may add the switch_id attribute for the case 2436 * there is no E-Switch and we wrongly recognized the only 2437 * device as master. Override this if there is the single 2438 * device with single port and new device name format present. 2439 */ 2440 if (nd == 1 && 2441 list[0].info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) { 2442 list[0].info.master = 0; 2443 list[0].info.representor = 0; 2444 } 2445 } 2446 MLX5_ASSERT(ns); 2447 /* 2448 * Sort list to probe devices in natural order for users convenience 2449 * (i.e. master first, then representors from lowest to highest ID). 2450 */ 2451 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2452 /* Device specific configuration. */ 2453 switch (pci_dev->id.device_id) { 2454 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2455 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2456 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2457 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2458 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2459 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2460 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: 2461 dev_config_vf = 1; 2462 break; 2463 default: 2464 dev_config_vf = 0; 2465 break; 2466 } 2467 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) { 2468 /* Set devargs default values. */ 2469 if (eth_da.nb_mh_controllers == 0) { 2470 eth_da.nb_mh_controllers = 1; 2471 eth_da.mh_controllers[0] = 0; 2472 } 2473 if (eth_da.nb_ports == 0 && ns > 0) { 2474 if (list[0].pf_bond >= 0 && list[0].info.representor) 2475 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s", 2476 pci_dev->device.devargs->args); 2477 eth_da.nb_ports = 1; 2478 eth_da.ports[0] = list[0].info.pf_num; 2479 } 2480 if (eth_da.nb_representor_ports == 0) { 2481 eth_da.nb_representor_ports = 1; 2482 eth_da.representor_ports[0] = 0; 2483 } 2484 } 2485 for (i = 0; i != ns; ++i) { 2486 uint32_t restore; 2487 2488 /* Default configuration. */ 2489 mlx5_os_config_default(&dev_config); 2490 dev_config.vf = dev_config_vf; 2491 list[i].eth_dev = mlx5_dev_spawn(cdev->dev, &list[i], 2492 &dev_config, ð_da); 2493 if (!list[i].eth_dev) { 2494 if (rte_errno != EBUSY && rte_errno != EEXIST) 2495 break; 2496 /* Device is disabled or already spawned. Ignore it. */ 2497 continue; 2498 } 2499 restore = list[i].eth_dev->data->dev_flags; 2500 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2501 /** 2502 * Each representor has a dedicated interrupts vector. 2503 * rte_eth_copy_pci_info() assigns PF interrupts handle to 2504 * representor eth_dev object because representor and PF 2505 * share the same PCI address. 2506 * Override representor device with a dedicated 2507 * interrupts handle here. 2508 * Representor interrupts handle is released in mlx5_dev_stop(). 2509 */ 2510 if (list[i].info.representor) { 2511 struct rte_intr_handle *intr_handle = 2512 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2513 if (intr_handle == NULL) { 2514 DRV_LOG(ERR, 2515 "port %u failed to allocate memory for interrupt handler " 2516 "Rx interrupts will not be supported", 2517 i); 2518 rte_errno = ENOMEM; 2519 ret = -rte_errno; 2520 goto exit; 2521 } 2522 list[i].eth_dev->intr_handle = intr_handle; 2523 } 2524 /* Restore non-PCI flags cleared by the above call. */ 2525 list[i].eth_dev->data->dev_flags |= restore; 2526 rte_eth_dev_probing_finish(list[i].eth_dev); 2527 } 2528 if (i != ns) { 2529 DRV_LOG(ERR, 2530 "probe of PCI device " PCI_PRI_FMT " aborted after" 2531 " encountering an error: %s", 2532 owner_pci.domain, owner_pci.bus, 2533 owner_pci.devid, owner_pci.function, 2534 strerror(rte_errno)); 2535 ret = -rte_errno; 2536 /* Roll back. */ 2537 while (i--) { 2538 if (!list[i].eth_dev) 2539 continue; 2540 mlx5_dev_close(list[i].eth_dev); 2541 /* mac_addrs must not be freed because in dev_private */ 2542 list[i].eth_dev->data->mac_addrs = NULL; 2543 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2544 } 2545 /* Restore original error. */ 2546 rte_errno = -ret; 2547 } else { 2548 ret = 0; 2549 } 2550 exit: 2551 /* 2552 * Do the routine cleanup: 2553 * - close opened Netlink sockets 2554 * - free allocated spawn data array 2555 * - free the Infiniband device list 2556 */ 2557 if (nl_rdma >= 0) 2558 close(nl_rdma); 2559 if (nl_route >= 0) 2560 close(nl_route); 2561 if (list) 2562 mlx5_free(list); 2563 MLX5_ASSERT(ibv_list); 2564 mlx5_glue->free_device_list(ibv_list); 2565 return ret; 2566 } 2567 2568 static int 2569 mlx5_os_parse_eth_devargs(struct rte_device *dev, 2570 struct rte_eth_devargs *eth_da) 2571 { 2572 int ret = 0; 2573 2574 if (dev->devargs == NULL) 2575 return 0; 2576 memset(eth_da, 0, sizeof(*eth_da)); 2577 /* Parse representor information first from class argument. */ 2578 if (dev->devargs->cls_str) 2579 ret = rte_eth_devargs_parse(dev->devargs->cls_str, eth_da); 2580 if (ret != 0) { 2581 DRV_LOG(ERR, "failed to parse device arguments: %s", 2582 dev->devargs->cls_str); 2583 return -rte_errno; 2584 } 2585 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) { 2586 /* Parse legacy device argument */ 2587 ret = rte_eth_devargs_parse(dev->devargs->args, eth_da); 2588 if (ret) { 2589 DRV_LOG(ERR, "failed to parse device arguments: %s", 2590 dev->devargs->args); 2591 return -rte_errno; 2592 } 2593 } 2594 return 0; 2595 } 2596 2597 /** 2598 * Callback to register a PCI device. 2599 * 2600 * This function spawns Ethernet devices out of a given PCI device. 2601 * 2602 * @param[in] cdev 2603 * Pointer to common mlx5 device structure. 2604 * 2605 * @return 2606 * 0 on success, a negative errno value otherwise and rte_errno is set. 2607 */ 2608 static int 2609 mlx5_os_pci_probe(struct mlx5_common_device *cdev) 2610 { 2611 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev); 2612 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2613 int ret = 0; 2614 uint16_t p; 2615 2616 ret = mlx5_os_parse_eth_devargs(cdev->dev, ð_da); 2617 if (ret != 0) 2618 return ret; 2619 2620 if (eth_da.nb_ports > 0) { 2621 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */ 2622 for (p = 0; p < eth_da.nb_ports; p++) { 2623 ret = mlx5_os_pci_probe_pf(cdev, ð_da, 2624 eth_da.ports[p]); 2625 if (ret) 2626 break; 2627 } 2628 if (ret) { 2629 DRV_LOG(ERR, "Probe of PCI device " PCI_PRI_FMT " " 2630 "aborted due to proding failure of PF %u", 2631 pci_dev->addr.domain, pci_dev->addr.bus, 2632 pci_dev->addr.devid, pci_dev->addr.function, 2633 eth_da.ports[p]); 2634 mlx5_net_remove(cdev); 2635 } 2636 } else { 2637 ret = mlx5_os_pci_probe_pf(cdev, ð_da, 0); 2638 } 2639 return ret; 2640 } 2641 2642 /* Probe a single SF device on auxiliary bus, no representor support. */ 2643 static int 2644 mlx5_os_auxiliary_probe(struct mlx5_common_device *cdev) 2645 { 2646 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2647 struct mlx5_dev_config config; 2648 struct mlx5_dev_spawn_data spawn = { .pf_bond = -1 }; 2649 struct rte_device *dev = cdev->dev; 2650 struct rte_auxiliary_device *adev = RTE_DEV_TO_AUXILIARY(dev); 2651 struct rte_eth_dev *eth_dev; 2652 int ret = 0; 2653 2654 /* Parse ethdev devargs. */ 2655 ret = mlx5_os_parse_eth_devargs(dev, ð_da); 2656 if (ret != 0) 2657 return ret; 2658 /* Set default config data. */ 2659 mlx5_os_config_default(&config); 2660 config.sf = 1; 2661 /* Init spawn data. */ 2662 spawn.max_port = 1; 2663 spawn.phys_port = 1; 2664 spawn.phys_dev_name = mlx5_os_get_ctx_device_name(cdev->ctx); 2665 ret = mlx5_auxiliary_get_ifindex(dev->name); 2666 if (ret < 0) { 2667 DRV_LOG(ERR, "failed to get ethdev ifindex: %s", dev->name); 2668 return ret; 2669 } 2670 spawn.ifindex = ret; 2671 spawn.cdev = cdev; 2672 /* Spawn device. */ 2673 eth_dev = mlx5_dev_spawn(dev, &spawn, &config, ð_da); 2674 if (eth_dev == NULL) 2675 return -rte_errno; 2676 /* Post create. */ 2677 eth_dev->intr_handle = adev->intr_handle; 2678 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2679 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2680 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_RMV; 2681 eth_dev->data->numa_node = dev->numa_node; 2682 } 2683 rte_eth_dev_probing_finish(eth_dev); 2684 return 0; 2685 } 2686 2687 /** 2688 * Net class driver callback to probe a device. 2689 * 2690 * This function probe PCI bus device(s) or a single SF on auxiliary bus. 2691 * 2692 * @param[in] cdev 2693 * Pointer to the common mlx5 device. 2694 * 2695 * @return 2696 * 0 on success, a negative errno value otherwise and rte_errno is set. 2697 */ 2698 int 2699 mlx5_os_net_probe(struct mlx5_common_device *cdev) 2700 { 2701 int ret; 2702 2703 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 2704 mlx5_pmd_socket_init(); 2705 ret = mlx5_init_once(); 2706 if (ret) { 2707 DRV_LOG(ERR, "Unable to init PMD global data: %s", 2708 strerror(rte_errno)); 2709 return -rte_errno; 2710 } 2711 if (mlx5_dev_is_pci(cdev->dev)) 2712 return mlx5_os_pci_probe(cdev); 2713 else 2714 return mlx5_os_auxiliary_probe(cdev); 2715 } 2716 2717 /** 2718 * Cleanup resources when the last device is closed. 2719 */ 2720 void 2721 mlx5_os_net_cleanup(void) 2722 { 2723 mlx5_pmd_socket_uninit(); 2724 } 2725 2726 /** 2727 * Install shared asynchronous device events handler. 2728 * This function is implemented to support event sharing 2729 * between multiple ports of single IB device. 2730 * 2731 * @param sh 2732 * Pointer to mlx5_dev_ctx_shared object. 2733 */ 2734 void 2735 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2736 { 2737 int ret; 2738 int flags; 2739 struct ibv_context *ctx = sh->cdev->ctx; 2740 2741 sh->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2742 if (sh->intr_handle == NULL) { 2743 DRV_LOG(ERR, "Fail to allocate intr_handle"); 2744 rte_errno = ENOMEM; 2745 return; 2746 } 2747 rte_intr_fd_set(sh->intr_handle, -1); 2748 2749 flags = fcntl(ctx->async_fd, F_GETFL); 2750 ret = fcntl(ctx->async_fd, F_SETFL, flags | O_NONBLOCK); 2751 if (ret) { 2752 DRV_LOG(INFO, "failed to change file descriptor async event" 2753 " queue"); 2754 } else { 2755 rte_intr_fd_set(sh->intr_handle, ctx->async_fd); 2756 rte_intr_type_set(sh->intr_handle, RTE_INTR_HANDLE_EXT); 2757 if (rte_intr_callback_register(sh->intr_handle, 2758 mlx5_dev_interrupt_handler, sh)) { 2759 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2760 rte_intr_fd_set(sh->intr_handle, -1); 2761 } 2762 } 2763 if (sh->devx) { 2764 #ifdef HAVE_IBV_DEVX_ASYNC 2765 sh->intr_handle_devx = 2766 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2767 if (!sh->intr_handle_devx) { 2768 DRV_LOG(ERR, "Fail to allocate intr_handle"); 2769 rte_errno = ENOMEM; 2770 return; 2771 } 2772 rte_intr_fd_set(sh->intr_handle_devx, -1); 2773 sh->devx_comp = (void *)mlx5_glue->devx_create_cmd_comp(ctx); 2774 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2775 if (!devx_comp) { 2776 DRV_LOG(INFO, "failed to allocate devx_comp."); 2777 return; 2778 } 2779 flags = fcntl(devx_comp->fd, F_GETFL); 2780 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2781 if (ret) { 2782 DRV_LOG(INFO, "failed to change file descriptor" 2783 " devx comp"); 2784 return; 2785 } 2786 rte_intr_fd_set(sh->intr_handle_devx, devx_comp->fd); 2787 rte_intr_type_set(sh->intr_handle_devx, 2788 RTE_INTR_HANDLE_EXT); 2789 if (rte_intr_callback_register(sh->intr_handle_devx, 2790 mlx5_dev_interrupt_handler_devx, sh)) { 2791 DRV_LOG(INFO, "Fail to install the devx shared" 2792 " interrupt."); 2793 rte_intr_fd_set(sh->intr_handle_devx, -1); 2794 } 2795 #endif /* HAVE_IBV_DEVX_ASYNC */ 2796 } 2797 } 2798 2799 /** 2800 * Uninstall shared asynchronous device events handler. 2801 * This function is implemented to support event sharing 2802 * between multiple ports of single IB device. 2803 * 2804 * @param dev 2805 * Pointer to mlx5_dev_ctx_shared object. 2806 */ 2807 void 2808 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2809 { 2810 if (rte_intr_fd_get(sh->intr_handle) >= 0) 2811 mlx5_intr_callback_unregister(sh->intr_handle, 2812 mlx5_dev_interrupt_handler, sh); 2813 rte_intr_instance_free(sh->intr_handle); 2814 #ifdef HAVE_IBV_DEVX_ASYNC 2815 if (rte_intr_fd_get(sh->intr_handle_devx) >= 0) 2816 rte_intr_callback_unregister(sh->intr_handle_devx, 2817 mlx5_dev_interrupt_handler_devx, sh); 2818 rte_intr_instance_free(sh->intr_handle_devx); 2819 if (sh->devx_comp) 2820 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2821 #endif 2822 } 2823 2824 /** 2825 * Read statistics by a named counter. 2826 * 2827 * @param[in] priv 2828 * Pointer to the private device data structure. 2829 * @param[in] ctr_name 2830 * Pointer to the name of the statistic counter to read 2831 * @param[out] stat 2832 * Pointer to read statistic value. 2833 * @return 2834 * 0 on success and stat is valud, 1 if failed to read the value 2835 * rte_errno is set. 2836 * 2837 */ 2838 int 2839 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2840 uint64_t *stat) 2841 { 2842 int fd; 2843 2844 if (priv->sh) { 2845 if (priv->q_counters != NULL && 2846 strcmp(ctr_name, "out_of_buffer") == 0) 2847 return mlx5_devx_cmd_queue_counter_query 2848 (priv->q_counters, 0, (uint32_t *)stat); 2849 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2850 priv->sh->ibdev_path, 2851 priv->dev_port, 2852 ctr_name); 2853 fd = open(path, O_RDONLY); 2854 /* 2855 * in switchdev the file location is not per port 2856 * but rather in <ibdev_path>/hw_counters/<file_name>. 2857 */ 2858 if (fd == -1) { 2859 MKSTR(path1, "%s/hw_counters/%s", 2860 priv->sh->ibdev_path, 2861 ctr_name); 2862 fd = open(path1, O_RDONLY); 2863 } 2864 if (fd != -1) { 2865 char buf[21] = {'\0'}; 2866 ssize_t n = read(fd, buf, sizeof(buf)); 2867 2868 close(fd); 2869 if (n != -1) { 2870 *stat = strtoull(buf, NULL, 10); 2871 return 0; 2872 } 2873 } 2874 } 2875 *stat = 0; 2876 return 1; 2877 } 2878 2879 /** 2880 * Remove a MAC address from device 2881 * 2882 * @param dev 2883 * Pointer to Ethernet device structure. 2884 * @param index 2885 * MAC address index. 2886 */ 2887 void 2888 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2889 { 2890 struct mlx5_priv *priv = dev->data->dev_private; 2891 const int vf = priv->config.vf; 2892 2893 if (vf) 2894 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2895 mlx5_ifindex(dev), priv->mac_own, 2896 &dev->data->mac_addrs[index], index); 2897 } 2898 2899 /** 2900 * Adds a MAC address to the device 2901 * 2902 * @param dev 2903 * Pointer to Ethernet device structure. 2904 * @param mac_addr 2905 * MAC address to register. 2906 * @param index 2907 * MAC address index. 2908 * 2909 * @return 2910 * 0 on success, a negative errno value otherwise 2911 */ 2912 int 2913 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2914 uint32_t index) 2915 { 2916 struct mlx5_priv *priv = dev->data->dev_private; 2917 const int vf = priv->config.vf; 2918 int ret = 0; 2919 2920 if (vf) 2921 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2922 mlx5_ifindex(dev), priv->mac_own, 2923 mac, index); 2924 return ret; 2925 } 2926 2927 /** 2928 * Modify a VF MAC address 2929 * 2930 * @param priv 2931 * Pointer to device private data. 2932 * @param mac_addr 2933 * MAC address to modify into. 2934 * @param iface_idx 2935 * Net device interface index 2936 * @param vf_index 2937 * VF index 2938 * 2939 * @return 2940 * 0 on success, a negative errno value otherwise 2941 */ 2942 int 2943 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2944 unsigned int iface_idx, 2945 struct rte_ether_addr *mac_addr, 2946 int vf_index) 2947 { 2948 return mlx5_nl_vf_mac_addr_modify 2949 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2950 } 2951 2952 /** 2953 * Set device promiscuous mode 2954 * 2955 * @param dev 2956 * Pointer to Ethernet device structure. 2957 * @param enable 2958 * 0 - promiscuous is disabled, otherwise - enabled 2959 * 2960 * @return 2961 * 0 on success, a negative error value otherwise 2962 */ 2963 int 2964 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2965 { 2966 struct mlx5_priv *priv = dev->data->dev_private; 2967 2968 return mlx5_nl_promisc(priv->nl_socket_route, 2969 mlx5_ifindex(dev), !!enable); 2970 } 2971 2972 /** 2973 * Set device promiscuous mode 2974 * 2975 * @param dev 2976 * Pointer to Ethernet device structure. 2977 * @param enable 2978 * 0 - all multicase is disabled, otherwise - enabled 2979 * 2980 * @return 2981 * 0 on success, a negative error value otherwise 2982 */ 2983 int 2984 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2985 { 2986 struct mlx5_priv *priv = dev->data->dev_private; 2987 2988 return mlx5_nl_allmulti(priv->nl_socket_route, 2989 mlx5_ifindex(dev), !!enable); 2990 } 2991 2992 /** 2993 * Flush device MAC addresses 2994 * 2995 * @param dev 2996 * Pointer to Ethernet device structure. 2997 * 2998 */ 2999 void 3000 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 3001 { 3002 struct mlx5_priv *priv = dev->data->dev_private; 3003 3004 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 3005 dev->data->mac_addrs, 3006 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 3007 } 3008