1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2015 Intel Corporation 3 */ 4 5 #include <stdio.h> 6 #include <stdint.h> 7 #include <stdarg.h> 8 #include <errno.h> 9 #include <sys/queue.h> 10 11 #include <rte_interrupts.h> 12 #include <rte_log.h> 13 #include <rte_debug.h> 14 #include <rte_pci.h> 15 #include <rte_ether.h> 16 #include <rte_ethdev_driver.h> 17 #include <rte_malloc.h> 18 19 #include "ixgbe_logs.h" 20 #include "base/ixgbe_api.h" 21 #include "base/ixgbe_common.h" 22 #include "ixgbe_ethdev.h" 23 24 /* To get PBALLOC (Packet Buffer Allocation) bits from FDIRCTRL value */ 25 #define FDIRCTRL_PBALLOC_MASK 0x03 26 27 /* For calculating memory required for FDIR filters */ 28 #define PBALLOC_SIZE_SHIFT 15 29 30 /* Number of bits used to mask bucket hash for different pballoc sizes */ 31 #define PERFECT_BUCKET_64KB_HASH_MASK 0x07FF /* 11 bits */ 32 #define PERFECT_BUCKET_128KB_HASH_MASK 0x0FFF /* 12 bits */ 33 #define PERFECT_BUCKET_256KB_HASH_MASK 0x1FFF /* 13 bits */ 34 #define SIG_BUCKET_64KB_HASH_MASK 0x1FFF /* 13 bits */ 35 #define SIG_BUCKET_128KB_HASH_MASK 0x3FFF /* 14 bits */ 36 #define SIG_BUCKET_256KB_HASH_MASK 0x7FFF /* 15 bits */ 37 #define IXGBE_DEFAULT_FLEXBYTES_OFFSET 12 /* default flexbytes offset in bytes */ 38 #define IXGBE_FDIR_MAX_FLEX_LEN 2 /* len in bytes of flexbytes */ 39 #define IXGBE_MAX_FLX_SOURCE_OFF 62 40 #define IXGBE_FDIRCTRL_FLEX_MASK (0x1F << IXGBE_FDIRCTRL_FLEX_SHIFT) 41 #define IXGBE_FDIRCMD_CMD_INTERVAL_US 10 42 43 #define IXGBE_FDIR_FLOW_TYPES ( \ 44 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \ 45 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \ 46 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \ 47 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \ 48 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \ 49 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \ 50 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \ 51 (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER)) 52 53 #define IPV6_ADDR_TO_MASK(ipaddr, ipv6m) do { \ 54 uint8_t ipv6_addr[16]; \ 55 uint8_t i; \ 56 rte_memcpy(ipv6_addr, (ipaddr), sizeof(ipv6_addr));\ 57 (ipv6m) = 0; \ 58 for (i = 0; i < sizeof(ipv6_addr); i++) { \ 59 if (ipv6_addr[i] == UINT8_MAX) \ 60 (ipv6m) |= 1 << i; \ 61 else if (ipv6_addr[i] != 0) { \ 62 PMD_DRV_LOG(ERR, " invalid IPv6 address mask."); \ 63 return -EINVAL; \ 64 } \ 65 } \ 66 } while (0) 67 68 #define IPV6_MASK_TO_ADDR(ipv6m, ipaddr) do { \ 69 uint8_t ipv6_addr[16]; \ 70 uint8_t i; \ 71 for (i = 0; i < sizeof(ipv6_addr); i++) { \ 72 if ((ipv6m) & (1 << i)) \ 73 ipv6_addr[i] = UINT8_MAX; \ 74 else \ 75 ipv6_addr[i] = 0; \ 76 } \ 77 rte_memcpy((ipaddr), ipv6_addr, sizeof(ipv6_addr));\ 78 } while (0) 79 80 #define DEFAULT_VXLAN_PORT 4789 81 #define IXGBE_FDIRIP6M_INNER_MAC_SHIFT 4 82 83 static int fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash); 84 static int fdir_set_input_mask(struct rte_eth_dev *dev, 85 const struct rte_eth_fdir_masks *input_mask); 86 static int fdir_set_input_mask_82599(struct rte_eth_dev *dev); 87 static int fdir_set_input_mask_x550(struct rte_eth_dev *dev); 88 static int ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev, 89 const struct rte_eth_fdir_flex_conf *conf, uint32_t *fdirctrl); 90 static int fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl); 91 static int ixgbe_fdir_filter_to_atr_input( 92 const struct rte_eth_fdir_filter *fdir_filter, 93 union ixgbe_atr_input *input, 94 enum rte_fdir_mode mode); 95 static uint32_t ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input, 96 uint32_t key); 97 static uint32_t atr_compute_sig_hash_82599(union ixgbe_atr_input *input, 98 enum rte_fdir_pballoc_type pballoc); 99 static uint32_t atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 100 enum rte_fdir_pballoc_type pballoc); 101 static int fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 102 union ixgbe_atr_input *input, uint8_t queue, 103 uint32_t fdircmd, uint32_t fdirhash, 104 enum rte_fdir_mode mode); 105 static int fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 106 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd, 107 uint32_t fdirhash); 108 static int ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev, 109 const struct rte_eth_fdir_filter *fdir_filter, 110 bool del, 111 bool update); 112 static int ixgbe_fdir_flush(struct rte_eth_dev *dev); 113 static void ixgbe_fdir_info_get(struct rte_eth_dev *dev, 114 struct rte_eth_fdir_info *fdir_info); 115 static void ixgbe_fdir_stats_get(struct rte_eth_dev *dev, 116 struct rte_eth_fdir_stats *fdir_stats); 117 118 /** 119 * This function is based on ixgbe_fdir_enable_82599() in base/ixgbe_82599.c. 120 * It adds extra configuration of fdirctrl that is common for all filter types. 121 * 122 * Initialize Flow Director control registers 123 * @hw: pointer to hardware structure 124 * @fdirctrl: value to write to flow director control register 125 **/ 126 static int 127 fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl) 128 { 129 int i; 130 131 PMD_INIT_FUNC_TRACE(); 132 133 /* Prime the keys for hashing */ 134 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 135 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); 136 137 /* 138 * Continue setup of fdirctrl register bits: 139 * Set the maximum length per hash bucket to 0xA filters 140 * Send interrupt when 64 filters are left 141 */ 142 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 143 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 144 145 /* 146 * Poll init-done after we write the register. Estimated times: 147 * 10G: PBALLOC = 11b, timing is 60us 148 * 1G: PBALLOC = 11b, timing is 600us 149 * 100M: PBALLOC = 11b, timing is 6ms 150 * 151 * Multiple these timings by 4 if under full Rx load 152 * 153 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 154 * 1 msec per poll time. If we're at line rate and drop to 100M, then 155 * this might not finish in our poll time, but we can live with that 156 * for now. 157 */ 158 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 159 IXGBE_WRITE_FLUSH(hw); 160 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 161 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 162 IXGBE_FDIRCTRL_INIT_DONE) 163 break; 164 msec_delay(1); 165 } 166 167 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 168 PMD_INIT_LOG(ERR, "Flow Director poll time exceeded during enabling!"); 169 return -ETIMEDOUT; 170 } 171 return 0; 172 } 173 174 /* 175 * Set appropriate bits in fdirctrl for: variable reporting levels, moving 176 * flexbytes matching field, and drop queue (only for perfect matching mode). 177 */ 178 static inline int 179 configure_fdir_flags(const struct rte_fdir_conf *conf, uint32_t *fdirctrl) 180 { 181 *fdirctrl = 0; 182 183 switch (conf->pballoc) { 184 case RTE_FDIR_PBALLOC_64K: 185 /* 8k - 1 signature filters */ 186 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; 187 break; 188 case RTE_FDIR_PBALLOC_128K: 189 /* 16k - 1 signature filters */ 190 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; 191 break; 192 case RTE_FDIR_PBALLOC_256K: 193 /* 32k - 1 signature filters */ 194 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; 195 break; 196 default: 197 /* bad value */ 198 PMD_INIT_LOG(ERR, "Invalid fdir_conf->pballoc value"); 199 return -EINVAL; 200 }; 201 202 /* status flags: write hash & swindex in the rx descriptor */ 203 switch (conf->status) { 204 case RTE_FDIR_NO_REPORT_STATUS: 205 /* do nothing, default mode */ 206 break; 207 case RTE_FDIR_REPORT_STATUS: 208 /* report status when the packet matches a fdir rule */ 209 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS; 210 break; 211 case RTE_FDIR_REPORT_STATUS_ALWAYS: 212 /* always report status */ 213 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS; 214 break; 215 default: 216 /* bad value */ 217 PMD_INIT_LOG(ERR, "Invalid fdir_conf->status value"); 218 return -EINVAL; 219 }; 220 221 *fdirctrl |= (IXGBE_DEFAULT_FLEXBYTES_OFFSET / sizeof(uint16_t)) << 222 IXGBE_FDIRCTRL_FLEX_SHIFT; 223 224 if (conf->mode >= RTE_FDIR_MODE_PERFECT && 225 conf->mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) { 226 *fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH; 227 *fdirctrl |= (conf->drop_queue << IXGBE_FDIRCTRL_DROP_Q_SHIFT); 228 if (conf->mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) 229 *fdirctrl |= (IXGBE_FDIRCTRL_FILTERMODE_MACVLAN 230 << IXGBE_FDIRCTRL_FILTERMODE_SHIFT); 231 else if (conf->mode == RTE_FDIR_MODE_PERFECT_TUNNEL) 232 *fdirctrl |= (IXGBE_FDIRCTRL_FILTERMODE_CLOUD 233 << IXGBE_FDIRCTRL_FILTERMODE_SHIFT); 234 } 235 236 return 0; 237 } 238 239 /** 240 * Reverse the bits in FDIR registers that store 2 x 16 bit masks. 241 * 242 * @hi_dword: Bits 31:16 mask to be bit swapped. 243 * @lo_dword: Bits 15:0 mask to be bit swapped. 244 * 245 * Flow director uses several registers to store 2 x 16 bit masks with the 246 * bits reversed such as FDIRTCPM, FDIRUDPM. The LS bit of the 247 * mask affects the MS bit/byte of the target. This function reverses the 248 * bits in these masks. 249 * **/ 250 static inline uint32_t 251 reverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword) 252 { 253 uint32_t mask = hi_dword << 16; 254 255 mask |= lo_dword; 256 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); 257 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); 258 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); 259 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); 260 } 261 262 /* 263 * This references ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c, 264 * but makes use of the rte_fdir_masks structure to see which bits to set. 265 */ 266 static int 267 fdir_set_input_mask_82599(struct rte_eth_dev *dev) 268 { 269 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 270 struct ixgbe_hw_fdir_info *info = 271 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private); 272 /* 273 * mask VM pool and DIPv6 since there are currently not supported 274 * mask FLEX byte, it will be set in flex_conf 275 */ 276 uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6; 277 uint32_t fdirtcpm; /* TCP source and destination port masks. */ 278 uint32_t fdiripv6m; /* IPv6 source and destination masks. */ 279 volatile uint32_t *reg; 280 281 PMD_INIT_FUNC_TRACE(); 282 283 /* 284 * Program the relevant mask registers. If src/dst_port or src/dst_addr 285 * are zero, then assume a full mask for that field. Also assume that 286 * a VLAN of 0 is unspecified, so mask that out as well. L4type 287 * cannot be masked out in this implementation. 288 */ 289 if (info->mask.dst_port_mask == 0 && info->mask.src_port_mask == 0) 290 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */ 291 fdirm |= IXGBE_FDIRM_L4P; 292 293 if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0x0FFF)) 294 /* mask VLAN Priority */ 295 fdirm |= IXGBE_FDIRM_VLANP; 296 else if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0xE000)) 297 /* mask VLAN ID */ 298 fdirm |= IXGBE_FDIRM_VLANID; 299 else if (info->mask.vlan_tci_mask == 0) 300 /* mask VLAN ID and Priority */ 301 fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP; 302 else if (info->mask.vlan_tci_mask != rte_cpu_to_be_16(0xEFFF)) { 303 PMD_INIT_LOG(ERR, "invalid vlan_tci_mask"); 304 return -EINVAL; 305 } 306 307 /* flex byte mask */ 308 if (info->mask.flex_bytes_mask == 0) 309 fdirm |= IXGBE_FDIRM_FLEX; 310 311 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 312 313 /* store the TCP/UDP port masks, bit reversed from port layout */ 314 fdirtcpm = reverse_fdir_bitmasks( 315 rte_be_to_cpu_16(info->mask.dst_port_mask), 316 rte_be_to_cpu_16(info->mask.src_port_mask)); 317 318 /* write all the same so that UDP, TCP and SCTP use the same mask 319 * (little-endian) 320 */ 321 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); 322 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); 323 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm); 324 325 /* Store source and destination IPv4 masks (big-endian), 326 * can not use IXGBE_WRITE_REG. 327 */ 328 reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRSIP4M); 329 *reg = ~(info->mask.src_ipv4_mask); 330 reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRDIP4M); 331 *reg = ~(info->mask.dst_ipv4_mask); 332 333 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE) { 334 /* 335 * Store source and destination IPv6 masks (bit reversed) 336 */ 337 fdiripv6m = (info->mask.dst_ipv6_mask << 16) | 338 info->mask.src_ipv6_mask; 339 340 IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, ~fdiripv6m); 341 } 342 343 return IXGBE_SUCCESS; 344 } 345 346 /* 347 * This references ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c, 348 * but makes use of the rte_fdir_masks structure to see which bits to set. 349 */ 350 static int 351 fdir_set_input_mask_x550(struct rte_eth_dev *dev) 352 { 353 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 354 struct ixgbe_hw_fdir_info *info = 355 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private); 356 /* mask VM pool and DIPv6 since there are currently not supported 357 * mask FLEX byte, it will be set in flex_conf 358 */ 359 uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6 | 360 IXGBE_FDIRM_FLEX; 361 uint32_t fdiripv6m; 362 enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode; 363 uint16_t mac_mask; 364 365 PMD_INIT_FUNC_TRACE(); 366 367 /* set the default UDP port for VxLAN */ 368 if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) 369 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, DEFAULT_VXLAN_PORT); 370 371 /* some bits must be set for mac vlan or tunnel mode */ 372 fdirm |= IXGBE_FDIRM_L4P | IXGBE_FDIRM_L3P; 373 374 if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0x0FFF)) 375 /* mask VLAN Priority */ 376 fdirm |= IXGBE_FDIRM_VLANP; 377 else if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0xE000)) 378 /* mask VLAN ID */ 379 fdirm |= IXGBE_FDIRM_VLANID; 380 else if (info->mask.vlan_tci_mask == 0) 381 /* mask VLAN ID and Priority */ 382 fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP; 383 else if (info->mask.vlan_tci_mask != rte_cpu_to_be_16(0xEFFF)) { 384 PMD_INIT_LOG(ERR, "invalid vlan_tci_mask"); 385 return -EINVAL; 386 } 387 388 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 389 390 fdiripv6m = ((u32)0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT); 391 fdiripv6m |= IXGBE_FDIRIP6M_ALWAYS_MASK; 392 if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) 393 fdiripv6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE | 394 IXGBE_FDIRIP6M_TNI_VNI; 395 396 if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) { 397 mac_mask = info->mask.mac_addr_byte_mask; 398 fdiripv6m |= (mac_mask << IXGBE_FDIRIP6M_INNER_MAC_SHIFT) 399 & IXGBE_FDIRIP6M_INNER_MAC; 400 401 switch (info->mask.tunnel_type_mask) { 402 case 0: 403 /* Mask turnnel type */ 404 fdiripv6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE; 405 break; 406 case 1: 407 break; 408 default: 409 PMD_INIT_LOG(ERR, "invalid tunnel_type_mask"); 410 return -EINVAL; 411 } 412 413 switch (rte_be_to_cpu_32(info->mask.tunnel_id_mask)) { 414 case 0x0: 415 /* Mask vxlan id */ 416 fdiripv6m |= IXGBE_FDIRIP6M_TNI_VNI; 417 break; 418 case 0x00FFFFFF: 419 fdiripv6m |= IXGBE_FDIRIP6M_TNI_VNI_24; 420 break; 421 case 0xFFFFFFFF: 422 break; 423 default: 424 PMD_INIT_LOG(ERR, "invalid tunnel_id_mask"); 425 return -EINVAL; 426 } 427 } 428 429 IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, fdiripv6m); 430 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF); 431 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF); 432 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF); 433 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF); 434 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF); 435 436 return IXGBE_SUCCESS; 437 } 438 439 static int 440 ixgbe_fdir_store_input_mask_82599(struct rte_eth_dev *dev, 441 const struct rte_eth_fdir_masks *input_mask) 442 { 443 struct ixgbe_hw_fdir_info *info = 444 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private); 445 uint16_t dst_ipv6m = 0; 446 uint16_t src_ipv6m = 0; 447 448 memset(&info->mask, 0, sizeof(struct ixgbe_hw_fdir_mask)); 449 info->mask.vlan_tci_mask = input_mask->vlan_tci_mask; 450 info->mask.src_port_mask = input_mask->src_port_mask; 451 info->mask.dst_port_mask = input_mask->dst_port_mask; 452 info->mask.src_ipv4_mask = input_mask->ipv4_mask.src_ip; 453 info->mask.dst_ipv4_mask = input_mask->ipv4_mask.dst_ip; 454 IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.src_ip, src_ipv6m); 455 IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.dst_ip, dst_ipv6m); 456 info->mask.src_ipv6_mask = src_ipv6m; 457 info->mask.dst_ipv6_mask = dst_ipv6m; 458 459 return IXGBE_SUCCESS; 460 } 461 462 static int 463 ixgbe_fdir_store_input_mask_x550(struct rte_eth_dev *dev, 464 const struct rte_eth_fdir_masks *input_mask) 465 { 466 struct ixgbe_hw_fdir_info *info = 467 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private); 468 469 memset(&info->mask, 0, sizeof(struct ixgbe_hw_fdir_mask)); 470 info->mask.vlan_tci_mask = input_mask->vlan_tci_mask; 471 info->mask.mac_addr_byte_mask = input_mask->mac_addr_byte_mask; 472 info->mask.tunnel_type_mask = input_mask->tunnel_type_mask; 473 info->mask.tunnel_id_mask = input_mask->tunnel_id_mask; 474 475 return IXGBE_SUCCESS; 476 } 477 478 static int 479 ixgbe_fdir_store_input_mask(struct rte_eth_dev *dev, 480 const struct rte_eth_fdir_masks *input_mask) 481 { 482 enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode; 483 484 if (mode >= RTE_FDIR_MODE_SIGNATURE && 485 mode <= RTE_FDIR_MODE_PERFECT) 486 return ixgbe_fdir_store_input_mask_82599(dev, input_mask); 487 else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN && 488 mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) 489 return ixgbe_fdir_store_input_mask_x550(dev, input_mask); 490 491 PMD_DRV_LOG(ERR, "Not supported fdir mode - %d!", mode); 492 return -ENOTSUP; 493 } 494 495 int 496 ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev) 497 { 498 enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode; 499 500 if (mode >= RTE_FDIR_MODE_SIGNATURE && 501 mode <= RTE_FDIR_MODE_PERFECT) 502 return fdir_set_input_mask_82599(dev); 503 else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN && 504 mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) 505 return fdir_set_input_mask_x550(dev); 506 507 PMD_DRV_LOG(ERR, "Not supported fdir mode - %d!", mode); 508 return -ENOTSUP; 509 } 510 511 int 512 ixgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev, 513 uint16_t offset) 514 { 515 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 516 uint32_t fdirctrl; 517 int i; 518 519 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 520 521 fdirctrl &= ~IXGBE_FDIRCTRL_FLEX_MASK; 522 fdirctrl |= ((offset >> 1) /* convert to word offset */ 523 << IXGBE_FDIRCTRL_FLEX_SHIFT); 524 525 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 526 IXGBE_WRITE_FLUSH(hw); 527 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 528 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 529 IXGBE_FDIRCTRL_INIT_DONE) 530 break; 531 msec_delay(1); 532 } 533 return 0; 534 } 535 536 static int 537 fdir_set_input_mask(struct rte_eth_dev *dev, 538 const struct rte_eth_fdir_masks *input_mask) 539 { 540 int ret; 541 542 ret = ixgbe_fdir_store_input_mask(dev, input_mask); 543 if (ret) 544 return ret; 545 546 return ixgbe_fdir_set_input_mask(dev); 547 } 548 549 /* 550 * ixgbe_check_fdir_flex_conf -check if the flex payload and mask configuration 551 * arguments are valid 552 */ 553 static int 554 ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev, 555 const struct rte_eth_fdir_flex_conf *conf, uint32_t *fdirctrl) 556 { 557 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 558 struct ixgbe_hw_fdir_info *info = 559 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private); 560 const struct rte_eth_flex_payload_cfg *flex_cfg; 561 const struct rte_eth_fdir_flex_mask *flex_mask; 562 uint32_t fdirm; 563 uint16_t flexbytes = 0; 564 uint16_t i; 565 566 fdirm = IXGBE_READ_REG(hw, IXGBE_FDIRM); 567 568 if (conf == NULL) { 569 PMD_DRV_LOG(ERR, "NULL pointer."); 570 return -EINVAL; 571 } 572 573 for (i = 0; i < conf->nb_payloads; i++) { 574 flex_cfg = &conf->flex_set[i]; 575 if (flex_cfg->type != RTE_ETH_RAW_PAYLOAD) { 576 PMD_DRV_LOG(ERR, "unsupported payload type."); 577 return -EINVAL; 578 } 579 if (((flex_cfg->src_offset[0] & 0x1) == 0) && 580 (flex_cfg->src_offset[1] == flex_cfg->src_offset[0] + 1) && 581 (flex_cfg->src_offset[0] <= IXGBE_MAX_FLX_SOURCE_OFF)) { 582 *fdirctrl &= ~IXGBE_FDIRCTRL_FLEX_MASK; 583 *fdirctrl |= 584 (flex_cfg->src_offset[0] / sizeof(uint16_t)) << 585 IXGBE_FDIRCTRL_FLEX_SHIFT; 586 } else { 587 PMD_DRV_LOG(ERR, "invalid flexbytes arguments."); 588 return -EINVAL; 589 } 590 } 591 592 for (i = 0; i < conf->nb_flexmasks; i++) { 593 flex_mask = &conf->flex_mask[i]; 594 if (flex_mask->flow_type != RTE_ETH_FLOW_UNKNOWN) { 595 PMD_DRV_LOG(ERR, "flexmask should be set globally."); 596 return -EINVAL; 597 } 598 flexbytes = (uint16_t)(((flex_mask->mask[0] << 8) & 0xFF00) | 599 ((flex_mask->mask[1]) & 0xFF)); 600 if (flexbytes == UINT16_MAX) 601 fdirm &= ~IXGBE_FDIRM_FLEX; 602 else if (flexbytes != 0) { 603 /* IXGBE_FDIRM_FLEX is set by default when set mask */ 604 PMD_DRV_LOG(ERR, " invalid flexbytes mask arguments."); 605 return -EINVAL; 606 } 607 } 608 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 609 info->mask.flex_bytes_mask = flexbytes ? UINT16_MAX : 0; 610 info->flex_bytes_offset = (uint8_t)((*fdirctrl & 611 IXGBE_FDIRCTRL_FLEX_MASK) >> 612 IXGBE_FDIRCTRL_FLEX_SHIFT); 613 return 0; 614 } 615 616 int 617 ixgbe_fdir_configure(struct rte_eth_dev *dev) 618 { 619 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 620 int err; 621 uint32_t fdirctrl, pbsize; 622 int i; 623 enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode; 624 625 PMD_INIT_FUNC_TRACE(); 626 627 if (hw->mac.type != ixgbe_mac_82599EB && 628 hw->mac.type != ixgbe_mac_X540 && 629 hw->mac.type != ixgbe_mac_X550 && 630 hw->mac.type != ixgbe_mac_X550EM_x && 631 hw->mac.type != ixgbe_mac_X550EM_a) 632 return -ENOSYS; 633 634 /* x550 supports mac-vlan and tunnel mode but other NICs not */ 635 if (hw->mac.type != ixgbe_mac_X550 && 636 hw->mac.type != ixgbe_mac_X550EM_x && 637 hw->mac.type != ixgbe_mac_X550EM_a && 638 mode != RTE_FDIR_MODE_SIGNATURE && 639 mode != RTE_FDIR_MODE_PERFECT) 640 return -ENOSYS; 641 642 err = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl); 643 if (err) 644 return err; 645 646 /* 647 * Before enabling Flow Director, the Rx Packet Buffer size 648 * must be reduced. The new value is the current size minus 649 * flow director memory usage size. 650 */ 651 pbsize = (1 << (PBALLOC_SIZE_SHIFT + (fdirctrl & FDIRCTRL_PBALLOC_MASK))); 652 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 653 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize)); 654 655 /* 656 * The defaults in the HW for RX PB 1-7 are not zero and so should be 657 * initialized to zero for non DCB mode otherwise actual total RX PB 658 * would be bigger than programmed and filter space would run into 659 * the PB 0 region. 660 */ 661 for (i = 1; i < 8; i++) 662 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 663 664 err = fdir_set_input_mask(dev, &dev->data->dev_conf.fdir_conf.mask); 665 if (err < 0) { 666 PMD_INIT_LOG(ERR, " Error on setting FD mask"); 667 return err; 668 } 669 err = ixgbe_set_fdir_flex_conf(dev, 670 &dev->data->dev_conf.fdir_conf.flex_conf, &fdirctrl); 671 if (err < 0) { 672 PMD_INIT_LOG(ERR, " Error on setting FD flexible arguments."); 673 return err; 674 } 675 676 err = fdir_enable_82599(hw, fdirctrl); 677 if (err < 0) { 678 PMD_INIT_LOG(ERR, " Error on enabling FD."); 679 return err; 680 } 681 return 0; 682 } 683 684 /* 685 * Convert DPDK rte_eth_fdir_filter struct to ixgbe_atr_input union that is used 686 * by the IXGBE driver code. 687 */ 688 static int 689 ixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_filter, 690 union ixgbe_atr_input *input, enum rte_fdir_mode mode) 691 { 692 input->formatted.vlan_id = fdir_filter->input.flow_ext.vlan_tci; 693 input->formatted.flex_bytes = (uint16_t)( 694 (fdir_filter->input.flow_ext.flexbytes[1] << 8 & 0xFF00) | 695 (fdir_filter->input.flow_ext.flexbytes[0] & 0xFF)); 696 697 switch (fdir_filter->input.flow_type) { 698 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 699 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 700 break; 701 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 702 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 703 break; 704 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP: 705 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 706 break; 707 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 708 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4; 709 break; 710 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 711 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV6; 712 break; 713 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 714 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 715 break; 716 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP: 717 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV6; 718 break; 719 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 720 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV6; 721 break; 722 default: 723 break; 724 } 725 726 switch (fdir_filter->input.flow_type) { 727 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 728 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 729 input->formatted.src_port = 730 fdir_filter->input.flow.udp4_flow.src_port; 731 input->formatted.dst_port = 732 fdir_filter->input.flow.udp4_flow.dst_port; 733 /* fall-through */ 734 /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/ 735 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP: 736 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 737 input->formatted.src_ip[0] = 738 fdir_filter->input.flow.ip4_flow.src_ip; 739 input->formatted.dst_ip[0] = 740 fdir_filter->input.flow.ip4_flow.dst_ip; 741 break; 742 743 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 744 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 745 input->formatted.src_port = 746 fdir_filter->input.flow.udp6_flow.src_port; 747 input->formatted.dst_port = 748 fdir_filter->input.flow.udp6_flow.dst_port; 749 /* fall-through */ 750 /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/ 751 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP: 752 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 753 rte_memcpy(input->formatted.src_ip, 754 fdir_filter->input.flow.ipv6_flow.src_ip, 755 sizeof(input->formatted.src_ip)); 756 rte_memcpy(input->formatted.dst_ip, 757 fdir_filter->input.flow.ipv6_flow.dst_ip, 758 sizeof(input->formatted.dst_ip)); 759 break; 760 default: 761 break; 762 } 763 764 if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) { 765 rte_memcpy( 766 input->formatted.inner_mac, 767 fdir_filter->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 768 sizeof(input->formatted.inner_mac)); 769 } else if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) { 770 rte_memcpy( 771 input->formatted.inner_mac, 772 fdir_filter->input.flow.tunnel_flow.mac_addr.addr_bytes, 773 sizeof(input->formatted.inner_mac)); 774 input->formatted.tunnel_type = 775 fdir_filter->input.flow.tunnel_flow.tunnel_type; 776 input->formatted.tni_vni = 777 fdir_filter->input.flow.tunnel_flow.tunnel_id; 778 } 779 780 return 0; 781 } 782 783 /* 784 * The below function is taken from the FreeBSD IXGBE drivers release 785 * 2.3.8. The only change is not to mask hash_result with IXGBE_ATR_HASH_MASK 786 * before returning, as the signature hash can use 16bits. 787 * 788 * The newer driver has optimised functions for calculating bucket and 789 * signature hashes. However they don't support IPv6 type packets for signature 790 * filters so are not used here. 791 * 792 * Note that the bkt_hash field in the ixgbe_atr_input structure is also never 793 * set. 794 * 795 * Compute the hashes for SW ATR 796 * @stream: input bitstream to compute the hash on 797 * @key: 32-bit hash key 798 **/ 799 static uint32_t 800 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input, 801 uint32_t key) 802 { 803 /* 804 * The algorithm is as follows: 805 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350 806 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n] 807 * and A[n] x B[n] is bitwise AND between same length strings 808 * 809 * K[n] is 16 bits, defined as: 810 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15] 811 * for n modulo 32 < 15, K[n] = 812 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))] 813 * 814 * S[n] is 16 bits, defined as: 815 * for n >= 15, S[n] = S[n:n - 15] 816 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))] 817 * 818 * To simplify for programming, the algorithm is implemented 819 * in software this way: 820 * 821 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0] 822 * 823 * for (i = 0; i < 352; i+=32) 824 * hi_hash_dword[31:0] ^= Stream[(i+31):i]; 825 * 826 * lo_hash_dword[15:0] ^= Stream[15:0]; 827 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16]; 828 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0]; 829 * 830 * hi_hash_dword[31:0] ^= Stream[351:320]; 831 * 832 * if (key[0]) 833 * hash[15:0] ^= Stream[15:0]; 834 * 835 * for (i = 0; i < 16; i++) { 836 * if (key[i]) 837 * hash[15:0] ^= lo_hash_dword[(i+15):i]; 838 * if (key[i + 16]) 839 * hash[15:0] ^= hi_hash_dword[(i+15):i]; 840 * } 841 * 842 */ 843 __be32 common_hash_dword = 0; 844 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 845 u32 hash_result = 0; 846 u8 i; 847 848 /* record the flow_vm_vlan bits as they are a key part to the hash */ 849 flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]); 850 851 /* generate common hash dword */ 852 for (i = 1; i <= 13; i++) 853 common_hash_dword ^= atr_input->dword_stream[i]; 854 855 hi_hash_dword = IXGBE_NTOHL(common_hash_dword); 856 857 /* low dword is word swapped version of common */ 858 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 859 860 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 861 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 862 863 /* Process bits 0 and 16 */ 864 if (key & 0x0001) 865 hash_result ^= lo_hash_dword; 866 if (key & 0x00010000) 867 hash_result ^= hi_hash_dword; 868 869 /* 870 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 871 * delay this because bit 0 of the stream should not be processed 872 * so we do not add the vlan until after bit 0 was processed 873 */ 874 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 875 876 877 /* process the remaining 30 bits in the key 2 bits at a time */ 878 for (i = 15; i; i--) { 879 if (key & (0x0001 << i)) 880 hash_result ^= lo_hash_dword >> i; 881 if (key & (0x00010000 << i)) 882 hash_result ^= hi_hash_dword >> i; 883 } 884 885 return hash_result; 886 } 887 888 static uint32_t 889 atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 890 enum rte_fdir_pballoc_type pballoc) 891 { 892 if (pballoc == RTE_FDIR_PBALLOC_256K) 893 return ixgbe_atr_compute_hash_82599(input, 894 IXGBE_ATR_BUCKET_HASH_KEY) & 895 PERFECT_BUCKET_256KB_HASH_MASK; 896 else if (pballoc == RTE_FDIR_PBALLOC_128K) 897 return ixgbe_atr_compute_hash_82599(input, 898 IXGBE_ATR_BUCKET_HASH_KEY) & 899 PERFECT_BUCKET_128KB_HASH_MASK; 900 else 901 return ixgbe_atr_compute_hash_82599(input, 902 IXGBE_ATR_BUCKET_HASH_KEY) & 903 PERFECT_BUCKET_64KB_HASH_MASK; 904 } 905 906 /** 907 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete 908 * @hw: pointer to hardware structure 909 */ 910 static inline int 911 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, uint32_t *fdircmd) 912 { 913 int i; 914 915 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { 916 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); 917 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK)) 918 return 0; 919 rte_delay_us(IXGBE_FDIRCMD_CMD_INTERVAL_US); 920 } 921 922 return -ETIMEDOUT; 923 } 924 925 /* 926 * Calculate the hash value needed for signature-match filters. In the FreeBSD 927 * driver, this is done by the optimised function 928 * ixgbe_atr_compute_sig_hash_82599(). However that can't be used here as it 929 * doesn't support calculating a hash for an IPv6 filter. 930 */ 931 static uint32_t 932 atr_compute_sig_hash_82599(union ixgbe_atr_input *input, 933 enum rte_fdir_pballoc_type pballoc) 934 { 935 uint32_t bucket_hash, sig_hash; 936 937 if (pballoc == RTE_FDIR_PBALLOC_256K) 938 bucket_hash = ixgbe_atr_compute_hash_82599(input, 939 IXGBE_ATR_BUCKET_HASH_KEY) & 940 SIG_BUCKET_256KB_HASH_MASK; 941 else if (pballoc == RTE_FDIR_PBALLOC_128K) 942 bucket_hash = ixgbe_atr_compute_hash_82599(input, 943 IXGBE_ATR_BUCKET_HASH_KEY) & 944 SIG_BUCKET_128KB_HASH_MASK; 945 else 946 bucket_hash = ixgbe_atr_compute_hash_82599(input, 947 IXGBE_ATR_BUCKET_HASH_KEY) & 948 SIG_BUCKET_64KB_HASH_MASK; 949 950 sig_hash = ixgbe_atr_compute_hash_82599(input, 951 IXGBE_ATR_SIGNATURE_HASH_KEY); 952 953 return (sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT) | bucket_hash; 954 } 955 956 /* 957 * This is based on ixgbe_fdir_write_perfect_filter_82599() in 958 * base/ixgbe_82599.c, with the ability to set extra flags in FDIRCMD register 959 * added, and IPv6 support also added. The hash value is also pre-calculated 960 * as the pballoc value is needed to do it. 961 */ 962 static int 963 fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 964 union ixgbe_atr_input *input, uint8_t queue, 965 uint32_t fdircmd, uint32_t fdirhash, 966 enum rte_fdir_mode mode) 967 { 968 uint32_t fdirport, fdirvlan; 969 u32 addr_low, addr_high; 970 u32 tunnel_type = 0; 971 int err = 0; 972 volatile uint32_t *reg; 973 974 if (mode == RTE_FDIR_MODE_PERFECT) { 975 /* record the IPv4 address (big-endian) 976 * can not use IXGBE_WRITE_REG. 977 */ 978 reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRIPSA); 979 *reg = input->formatted.src_ip[0]; 980 reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRIPDA); 981 *reg = input->formatted.dst_ip[0]; 982 983 /* record source and destination port (little-endian)*/ 984 fdirport = IXGBE_NTOHS(input->formatted.dst_port); 985 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; 986 fdirport |= IXGBE_NTOHS(input->formatted.src_port); 987 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); 988 } else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN && 989 mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) { 990 /* for mac vlan and tunnel modes */ 991 addr_low = ((u32)input->formatted.inner_mac[0] | 992 ((u32)input->formatted.inner_mac[1] << 8) | 993 ((u32)input->formatted.inner_mac[2] << 16) | 994 ((u32)input->formatted.inner_mac[3] << 24)); 995 addr_high = ((u32)input->formatted.inner_mac[4] | 996 ((u32)input->formatted.inner_mac[5] << 8)); 997 998 if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) { 999 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), addr_low); 1000 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), addr_high); 1001 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), 0); 1002 } else { 1003 /* tunnel mode */ 1004 if (input->formatted.tunnel_type != 1005 RTE_FDIR_TUNNEL_TYPE_NVGRE) 1006 tunnel_type = 0x80000000; 1007 tunnel_type |= addr_high; 1008 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), addr_low); 1009 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), tunnel_type); 1010 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), 1011 input->formatted.tni_vni); 1012 } 1013 } 1014 1015 /* record vlan (little-endian) and flex_bytes(big-endian) */ 1016 fdirvlan = input->formatted.flex_bytes; 1017 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; 1018 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id); 1019 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); 1020 1021 /* configure FDIRHASH register */ 1022 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1023 1024 /* 1025 * flush all previous writes to make certain registers are 1026 * programmed prior to issuing the command 1027 */ 1028 IXGBE_WRITE_FLUSH(hw); 1029 1030 /* configure FDIRCMD register */ 1031 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW | 1032 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1033 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1034 fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1035 fdircmd |= (uint32_t)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; 1036 1037 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1038 1039 PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash); 1040 1041 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1042 if (err < 0) 1043 PMD_DRV_LOG(ERR, "Timeout writing flow director filter."); 1044 1045 return err; 1046 } 1047 1048 /** 1049 * This function is based on ixgbe_atr_add_signature_filter_82599() in 1050 * base/ixgbe_82599.c, but uses a pre-calculated hash value. It also supports 1051 * setting extra fields in the FDIRCMD register, and removes the code that was 1052 * verifying the flow_type field. According to the documentation, a flow type of 1053 * 00 (i.e. not TCP, UDP, or SCTP) is not supported, however it appears to 1054 * work ok... 1055 * 1056 * Adds a signature hash filter 1057 * @hw: pointer to hardware structure 1058 * @input: unique input dword 1059 * @queue: queue index to direct traffic to 1060 * @fdircmd: any extra flags to set in fdircmd register 1061 * @fdirhash: pre-calculated hash value for the filter 1062 **/ 1063 static int 1064 fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 1065 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd, 1066 uint32_t fdirhash) 1067 { 1068 int err = 0; 1069 1070 PMD_INIT_FUNC_TRACE(); 1071 1072 /* configure FDIRCMD register */ 1073 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW | 1074 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1075 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1076 fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1077 1078 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1079 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1080 1081 PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash); 1082 1083 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1084 if (err < 0) 1085 PMD_DRV_LOG(ERR, "Timeout writing flow director filter."); 1086 1087 return err; 1088 } 1089 1090 /* 1091 * This is based on ixgbe_fdir_erase_perfect_filter_82599() in 1092 * base/ixgbe_82599.c. It is modified to take in the hash as a parameter so 1093 * that it can be used for removing signature and perfect filters. 1094 */ 1095 static int 1096 fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash) 1097 { 1098 uint32_t fdircmd = 0; 1099 int err = 0; 1100 1101 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1102 1103 /* flush hash to HW */ 1104 IXGBE_WRITE_FLUSH(hw); 1105 1106 /* Query if filter is present */ 1107 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); 1108 1109 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1110 if (err < 0) { 1111 PMD_INIT_LOG(ERR, "Timeout querying for flow director filter."); 1112 return err; 1113 } 1114 1115 /* if filter exists in hardware then remove it */ 1116 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) { 1117 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1118 IXGBE_WRITE_FLUSH(hw); 1119 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1120 IXGBE_FDIRCMD_CMD_REMOVE_FLOW); 1121 } 1122 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1123 if (err < 0) 1124 PMD_INIT_LOG(ERR, "Timeout erasing flow director filter."); 1125 return err; 1126 1127 } 1128 1129 static inline struct ixgbe_fdir_filter * 1130 ixgbe_fdir_filter_lookup(struct ixgbe_hw_fdir_info *fdir_info, 1131 union ixgbe_atr_input *key) 1132 { 1133 int ret; 1134 1135 ret = rte_hash_lookup(fdir_info->hash_handle, (const void *)key); 1136 if (ret < 0) 1137 return NULL; 1138 1139 return fdir_info->hash_map[ret]; 1140 } 1141 1142 static inline int 1143 ixgbe_insert_fdir_filter(struct ixgbe_hw_fdir_info *fdir_info, 1144 struct ixgbe_fdir_filter *fdir_filter) 1145 { 1146 int ret; 1147 1148 ret = rte_hash_add_key(fdir_info->hash_handle, 1149 &fdir_filter->ixgbe_fdir); 1150 1151 if (ret < 0) { 1152 PMD_DRV_LOG(ERR, 1153 "Failed to insert fdir filter to hash table %d!", 1154 ret); 1155 return ret; 1156 } 1157 1158 fdir_info->hash_map[ret] = fdir_filter; 1159 1160 TAILQ_INSERT_TAIL(&fdir_info->fdir_list, fdir_filter, entries); 1161 1162 return 0; 1163 } 1164 1165 static inline int 1166 ixgbe_remove_fdir_filter(struct ixgbe_hw_fdir_info *fdir_info, 1167 union ixgbe_atr_input *key) 1168 { 1169 int ret; 1170 struct ixgbe_fdir_filter *fdir_filter; 1171 1172 ret = rte_hash_del_key(fdir_info->hash_handle, key); 1173 1174 if (ret < 0) { 1175 PMD_DRV_LOG(ERR, "No such fdir filter to delete %d!", ret); 1176 return ret; 1177 } 1178 1179 fdir_filter = fdir_info->hash_map[ret]; 1180 fdir_info->hash_map[ret] = NULL; 1181 1182 TAILQ_REMOVE(&fdir_info->fdir_list, fdir_filter, entries); 1183 rte_free(fdir_filter); 1184 1185 return 0; 1186 } 1187 1188 static int 1189 ixgbe_interpret_fdir_filter(struct rte_eth_dev *dev, 1190 const struct rte_eth_fdir_filter *fdir_filter, 1191 struct ixgbe_fdir_rule *rule) 1192 { 1193 enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode; 1194 int err; 1195 1196 memset(rule, 0, sizeof(struct ixgbe_fdir_rule)); 1197 1198 err = ixgbe_fdir_filter_to_atr_input(fdir_filter, 1199 &rule->ixgbe_fdir, 1200 fdir_mode); 1201 if (err) 1202 return err; 1203 1204 rule->mode = fdir_mode; 1205 if (fdir_filter->action.behavior == RTE_ETH_FDIR_REJECT) 1206 rule->fdirflags = IXGBE_FDIRCMD_DROP; 1207 rule->queue = fdir_filter->action.rx_queue; 1208 rule->soft_id = fdir_filter->soft_id; 1209 1210 return 0; 1211 } 1212 1213 int 1214 ixgbe_fdir_filter_program(struct rte_eth_dev *dev, 1215 struct ixgbe_fdir_rule *rule, 1216 bool del, 1217 bool update) 1218 { 1219 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1220 uint32_t fdircmd_flags; 1221 uint32_t fdirhash; 1222 uint8_t queue; 1223 bool is_perfect = FALSE; 1224 int err; 1225 struct ixgbe_hw_fdir_info *info = 1226 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private); 1227 enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode; 1228 struct ixgbe_fdir_filter *node; 1229 bool add_node = FALSE; 1230 1231 if (fdir_mode == RTE_FDIR_MODE_NONE || 1232 fdir_mode != rule->mode) 1233 return -ENOTSUP; 1234 1235 /* 1236 * Sanity check for x550. 1237 * When adding a new filter with flow type set to IPv4, 1238 * the flow director mask should be configed before, 1239 * and the L4 protocol and ports are masked. 1240 */ 1241 if ((!del) && 1242 (hw->mac.type == ixgbe_mac_X550 || 1243 hw->mac.type == ixgbe_mac_X550EM_x || 1244 hw->mac.type == ixgbe_mac_X550EM_a) && 1245 (rule->ixgbe_fdir.formatted.flow_type == 1246 IXGBE_ATR_FLOW_TYPE_IPV4 || 1247 rule->ixgbe_fdir.formatted.flow_type == 1248 IXGBE_ATR_FLOW_TYPE_IPV6) && 1249 (info->mask.src_port_mask != 0 || 1250 info->mask.dst_port_mask != 0) && 1251 (rule->mode != RTE_FDIR_MODE_PERFECT_MAC_VLAN && 1252 rule->mode != RTE_FDIR_MODE_PERFECT_TUNNEL)) { 1253 PMD_DRV_LOG(ERR, "By this device," 1254 " IPv4 is not supported without" 1255 " L4 protocol and ports masked!"); 1256 return -ENOTSUP; 1257 } 1258 1259 if (fdir_mode >= RTE_FDIR_MODE_PERFECT && 1260 fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) 1261 is_perfect = TRUE; 1262 1263 if (is_perfect) { 1264 if (rule->ixgbe_fdir.formatted.flow_type & 1265 IXGBE_ATR_L4TYPE_IPV6_MASK) { 1266 PMD_DRV_LOG(ERR, "IPv6 is not supported in" 1267 " perfect mode!"); 1268 return -ENOTSUP; 1269 } 1270 fdirhash = atr_compute_perfect_hash_82599(&rule->ixgbe_fdir, 1271 dev->data->dev_conf.fdir_conf.pballoc); 1272 fdirhash |= rule->soft_id << 1273 IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1274 } else 1275 fdirhash = atr_compute_sig_hash_82599(&rule->ixgbe_fdir, 1276 dev->data->dev_conf.fdir_conf.pballoc); 1277 1278 if (del) { 1279 err = ixgbe_remove_fdir_filter(info, &rule->ixgbe_fdir); 1280 if (err < 0) 1281 return err; 1282 1283 err = fdir_erase_filter_82599(hw, fdirhash); 1284 if (err < 0) 1285 PMD_DRV_LOG(ERR, "Fail to delete FDIR filter!"); 1286 else 1287 PMD_DRV_LOG(DEBUG, "Success to delete FDIR filter!"); 1288 return err; 1289 } 1290 /* add or update an fdir filter*/ 1291 fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0; 1292 if (rule->fdirflags & IXGBE_FDIRCMD_DROP) { 1293 if (is_perfect) { 1294 queue = dev->data->dev_conf.fdir_conf.drop_queue; 1295 fdircmd_flags |= IXGBE_FDIRCMD_DROP; 1296 } else { 1297 PMD_DRV_LOG(ERR, "Drop option is not supported in" 1298 " signature mode."); 1299 return -EINVAL; 1300 } 1301 } else if (rule->queue < IXGBE_MAX_RX_QUEUE_NUM) 1302 queue = (uint8_t)rule->queue; 1303 else 1304 return -EINVAL; 1305 1306 node = ixgbe_fdir_filter_lookup(info, &rule->ixgbe_fdir); 1307 if (node) { 1308 if (update) { 1309 node->fdirflags = fdircmd_flags; 1310 node->fdirhash = fdirhash; 1311 node->queue = queue; 1312 } else { 1313 PMD_DRV_LOG(ERR, "Conflict with existing fdir filter!"); 1314 return -EINVAL; 1315 } 1316 } else { 1317 add_node = TRUE; 1318 node = rte_zmalloc("ixgbe_fdir", 1319 sizeof(struct ixgbe_fdir_filter), 1320 0); 1321 if (!node) 1322 return -ENOMEM; 1323 rte_memcpy(&node->ixgbe_fdir, 1324 &rule->ixgbe_fdir, 1325 sizeof(union ixgbe_atr_input)); 1326 node->fdirflags = fdircmd_flags; 1327 node->fdirhash = fdirhash; 1328 node->queue = queue; 1329 1330 err = ixgbe_insert_fdir_filter(info, node); 1331 if (err < 0) { 1332 rte_free(node); 1333 return err; 1334 } 1335 } 1336 1337 if (is_perfect) { 1338 err = fdir_write_perfect_filter_82599(hw, &rule->ixgbe_fdir, 1339 queue, fdircmd_flags, 1340 fdirhash, fdir_mode); 1341 } else { 1342 err = fdir_add_signature_filter_82599(hw, &rule->ixgbe_fdir, 1343 queue, fdircmd_flags, 1344 fdirhash); 1345 } 1346 if (err < 0) { 1347 PMD_DRV_LOG(ERR, "Fail to add FDIR filter!"); 1348 1349 if (add_node) 1350 (void)ixgbe_remove_fdir_filter(info, &rule->ixgbe_fdir); 1351 } else { 1352 PMD_DRV_LOG(DEBUG, "Success to add FDIR filter"); 1353 } 1354 1355 return err; 1356 } 1357 1358 /* ixgbe_add_del_fdir_filter - add or remove a flow diretor filter. 1359 * @dev: pointer to the structure rte_eth_dev 1360 * @fdir_filter: fdir filter entry 1361 * @del: 1 - delete, 0 - add 1362 * @update: 1 - update 1363 */ 1364 static int 1365 ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev, 1366 const struct rte_eth_fdir_filter *fdir_filter, 1367 bool del, 1368 bool update) 1369 { 1370 struct ixgbe_fdir_rule rule; 1371 int err; 1372 1373 err = ixgbe_interpret_fdir_filter(dev, fdir_filter, &rule); 1374 1375 if (err) 1376 return err; 1377 1378 return ixgbe_fdir_filter_program(dev, &rule, del, update); 1379 } 1380 1381 static int 1382 ixgbe_fdir_flush(struct rte_eth_dev *dev) 1383 { 1384 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1385 struct ixgbe_hw_fdir_info *info = 1386 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private); 1387 int ret; 1388 1389 ret = ixgbe_reinit_fdir_tables_82599(hw); 1390 if (ret < 0) { 1391 PMD_INIT_LOG(ERR, "Failed to re-initialize FD table."); 1392 return ret; 1393 } 1394 1395 info->f_add = 0; 1396 info->f_remove = 0; 1397 info->add = 0; 1398 info->remove = 0; 1399 1400 return ret; 1401 } 1402 1403 #define FDIRENTRIES_NUM_SHIFT 10 1404 static void 1405 ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info) 1406 { 1407 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1408 struct ixgbe_hw_fdir_info *info = 1409 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private); 1410 uint32_t fdirctrl, max_num, i; 1411 uint8_t offset; 1412 1413 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1414 offset = ((fdirctrl & IXGBE_FDIRCTRL_FLEX_MASK) >> 1415 IXGBE_FDIRCTRL_FLEX_SHIFT) * sizeof(uint16_t); 1416 1417 fdir_info->mode = dev->data->dev_conf.fdir_conf.mode; 1418 max_num = (1 << (FDIRENTRIES_NUM_SHIFT + 1419 (fdirctrl & FDIRCTRL_PBALLOC_MASK))); 1420 if (fdir_info->mode >= RTE_FDIR_MODE_PERFECT && 1421 fdir_info->mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) 1422 fdir_info->guarant_spc = max_num; 1423 else if (fdir_info->mode == RTE_FDIR_MODE_SIGNATURE) 1424 fdir_info->guarant_spc = max_num * 4; 1425 1426 fdir_info->mask.vlan_tci_mask = info->mask.vlan_tci_mask; 1427 fdir_info->mask.ipv4_mask.src_ip = info->mask.src_ipv4_mask; 1428 fdir_info->mask.ipv4_mask.dst_ip = info->mask.dst_ipv4_mask; 1429 IPV6_MASK_TO_ADDR(info->mask.src_ipv6_mask, 1430 fdir_info->mask.ipv6_mask.src_ip); 1431 IPV6_MASK_TO_ADDR(info->mask.dst_ipv6_mask, 1432 fdir_info->mask.ipv6_mask.dst_ip); 1433 fdir_info->mask.src_port_mask = info->mask.src_port_mask; 1434 fdir_info->mask.dst_port_mask = info->mask.dst_port_mask; 1435 fdir_info->mask.mac_addr_byte_mask = info->mask.mac_addr_byte_mask; 1436 fdir_info->mask.tunnel_id_mask = info->mask.tunnel_id_mask; 1437 fdir_info->mask.tunnel_type_mask = info->mask.tunnel_type_mask; 1438 fdir_info->max_flexpayload = IXGBE_FDIR_MAX_FLEX_LEN; 1439 1440 if (fdir_info->mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN || 1441 fdir_info->mode == RTE_FDIR_MODE_PERFECT_TUNNEL) 1442 fdir_info->flow_types_mask[0] = 0ULL; 1443 else 1444 fdir_info->flow_types_mask[0] = IXGBE_FDIR_FLOW_TYPES; 1445 for (i = 1; i < RTE_FLOW_MASK_ARRAY_SIZE; i++) 1446 fdir_info->flow_types_mask[i] = 0ULL; 1447 1448 fdir_info->flex_payload_unit = sizeof(uint16_t); 1449 fdir_info->max_flex_payload_segment_num = 1; 1450 fdir_info->flex_payload_limit = IXGBE_MAX_FLX_SOURCE_OFF; 1451 fdir_info->flex_conf.nb_payloads = 1; 1452 fdir_info->flex_conf.flex_set[0].type = RTE_ETH_RAW_PAYLOAD; 1453 fdir_info->flex_conf.flex_set[0].src_offset[0] = offset; 1454 fdir_info->flex_conf.flex_set[0].src_offset[1] = offset + 1; 1455 fdir_info->flex_conf.nb_flexmasks = 1; 1456 fdir_info->flex_conf.flex_mask[0].flow_type = RTE_ETH_FLOW_UNKNOWN; 1457 fdir_info->flex_conf.flex_mask[0].mask[0] = 1458 (uint8_t)(info->mask.flex_bytes_mask & 0x00FF); 1459 fdir_info->flex_conf.flex_mask[0].mask[1] = 1460 (uint8_t)((info->mask.flex_bytes_mask & 0xFF00) >> 8); 1461 } 1462 1463 static void 1464 ixgbe_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *fdir_stats) 1465 { 1466 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1467 struct ixgbe_hw_fdir_info *info = 1468 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private); 1469 uint32_t reg, max_num; 1470 enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode; 1471 1472 /* Get the information from registers */ 1473 reg = IXGBE_READ_REG(hw, IXGBE_FDIRFREE); 1474 info->collision = (uint16_t)((reg & IXGBE_FDIRFREE_COLL_MASK) >> 1475 IXGBE_FDIRFREE_COLL_SHIFT); 1476 info->free = (uint16_t)((reg & IXGBE_FDIRFREE_FREE_MASK) >> 1477 IXGBE_FDIRFREE_FREE_SHIFT); 1478 1479 reg = IXGBE_READ_REG(hw, IXGBE_FDIRLEN); 1480 info->maxhash = (uint16_t)((reg & IXGBE_FDIRLEN_MAXHASH_MASK) >> 1481 IXGBE_FDIRLEN_MAXHASH_SHIFT); 1482 info->maxlen = (uint8_t)((reg & IXGBE_FDIRLEN_MAXLEN_MASK) >> 1483 IXGBE_FDIRLEN_MAXLEN_SHIFT); 1484 1485 reg = IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); 1486 info->remove += (reg & IXGBE_FDIRUSTAT_REMOVE_MASK) >> 1487 IXGBE_FDIRUSTAT_REMOVE_SHIFT; 1488 info->add += (reg & IXGBE_FDIRUSTAT_ADD_MASK) >> 1489 IXGBE_FDIRUSTAT_ADD_SHIFT; 1490 1491 reg = IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT) & 0xFFFF; 1492 info->f_remove += (reg & IXGBE_FDIRFSTAT_FREMOVE_MASK) >> 1493 IXGBE_FDIRFSTAT_FREMOVE_SHIFT; 1494 info->f_add += (reg & IXGBE_FDIRFSTAT_FADD_MASK) >> 1495 IXGBE_FDIRFSTAT_FADD_SHIFT; 1496 1497 /* Copy the new information in the fdir parameter */ 1498 fdir_stats->collision = info->collision; 1499 fdir_stats->free = info->free; 1500 fdir_stats->maxhash = info->maxhash; 1501 fdir_stats->maxlen = info->maxlen; 1502 fdir_stats->remove = info->remove; 1503 fdir_stats->add = info->add; 1504 fdir_stats->f_remove = info->f_remove; 1505 fdir_stats->f_add = info->f_add; 1506 1507 reg = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1508 max_num = (1 << (FDIRENTRIES_NUM_SHIFT + 1509 (reg & FDIRCTRL_PBALLOC_MASK))); 1510 if (fdir_mode >= RTE_FDIR_MODE_PERFECT && 1511 fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) 1512 fdir_stats->guarant_cnt = max_num - fdir_stats->free; 1513 else if (fdir_mode == RTE_FDIR_MODE_SIGNATURE) 1514 fdir_stats->guarant_cnt = max_num * 4 - fdir_stats->free; 1515 1516 } 1517 1518 /* 1519 * ixgbe_fdir_ctrl_func - deal with all operations on flow director. 1520 * @dev: pointer to the structure rte_eth_dev 1521 * @filter_op:operation will be taken 1522 * @arg: a pointer to specific structure corresponding to the filter_op 1523 */ 1524 int 1525 ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev, 1526 enum rte_filter_op filter_op, void *arg) 1527 { 1528 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1529 int ret = 0; 1530 1531 if (hw->mac.type != ixgbe_mac_82599EB && 1532 hw->mac.type != ixgbe_mac_X540 && 1533 hw->mac.type != ixgbe_mac_X550 && 1534 hw->mac.type != ixgbe_mac_X550EM_x && 1535 hw->mac.type != ixgbe_mac_X550EM_a) 1536 return -ENOTSUP; 1537 1538 if (filter_op == RTE_ETH_FILTER_NOP) 1539 return 0; 1540 1541 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 1542 return -EINVAL; 1543 1544 switch (filter_op) { 1545 case RTE_ETH_FILTER_ADD: 1546 ret = ixgbe_add_del_fdir_filter(dev, 1547 (struct rte_eth_fdir_filter *)arg, FALSE, FALSE); 1548 break; 1549 case RTE_ETH_FILTER_UPDATE: 1550 ret = ixgbe_add_del_fdir_filter(dev, 1551 (struct rte_eth_fdir_filter *)arg, FALSE, TRUE); 1552 break; 1553 case RTE_ETH_FILTER_DELETE: 1554 ret = ixgbe_add_del_fdir_filter(dev, 1555 (struct rte_eth_fdir_filter *)arg, TRUE, FALSE); 1556 break; 1557 case RTE_ETH_FILTER_FLUSH: 1558 ret = ixgbe_fdir_flush(dev); 1559 break; 1560 case RTE_ETH_FILTER_INFO: 1561 ixgbe_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg); 1562 break; 1563 case RTE_ETH_FILTER_STATS: 1564 ixgbe_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg); 1565 break; 1566 default: 1567 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 1568 ret = -EINVAL; 1569 break; 1570 } 1571 return ret; 1572 } 1573 1574 /* restore flow director filter */ 1575 void 1576 ixgbe_fdir_filter_restore(struct rte_eth_dev *dev) 1577 { 1578 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1579 struct ixgbe_hw_fdir_info *fdir_info = 1580 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private); 1581 struct ixgbe_fdir_filter *node; 1582 bool is_perfect = FALSE; 1583 enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode; 1584 1585 if (fdir_mode >= RTE_FDIR_MODE_PERFECT && 1586 fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) 1587 is_perfect = TRUE; 1588 1589 if (is_perfect) { 1590 TAILQ_FOREACH(node, &fdir_info->fdir_list, entries) { 1591 (void)fdir_write_perfect_filter_82599(hw, 1592 &node->ixgbe_fdir, 1593 node->queue, 1594 node->fdirflags, 1595 node->fdirhash, 1596 fdir_mode); 1597 } 1598 } else { 1599 TAILQ_FOREACH(node, &fdir_info->fdir_list, entries) { 1600 (void)fdir_add_signature_filter_82599(hw, 1601 &node->ixgbe_fdir, 1602 node->queue, 1603 node->fdirflags, 1604 node->fdirhash); 1605 } 1606 } 1607 } 1608 1609 /* remove all the flow director filters */ 1610 int 1611 ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev) 1612 { 1613 struct ixgbe_hw_fdir_info *fdir_info = 1614 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private); 1615 struct ixgbe_fdir_filter *fdir_filter; 1616 struct ixgbe_fdir_filter *filter_flag; 1617 int ret = 0; 1618 1619 /* flush flow director */ 1620 rte_hash_reset(fdir_info->hash_handle); 1621 memset(fdir_info->hash_map, 0, 1622 sizeof(struct ixgbe_fdir_filter *) * IXGBE_MAX_FDIR_FILTER_NUM); 1623 filter_flag = TAILQ_FIRST(&fdir_info->fdir_list); 1624 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 1625 TAILQ_REMOVE(&fdir_info->fdir_list, 1626 fdir_filter, 1627 entries); 1628 rte_free(fdir_filter); 1629 } 1630 1631 if (filter_flag != NULL) 1632 ret = ixgbe_fdir_flush(dev); 1633 1634 return ret; 1635 } 1636