1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2016 Intel Corporation 3 */ 4 5 #ifndef _IXGBE_ETHDEV_H_ 6 #define _IXGBE_ETHDEV_H_ 7 #include "base/ixgbe_type.h" 8 #include "base/ixgbe_dcb.h" 9 #include "base/ixgbe_dcb_82599.h" 10 #include "base/ixgbe_dcb_82598.h" 11 #include "ixgbe_bypass.h" 12 #ifdef RTE_LIBRTE_SECURITY 13 #include "ixgbe_ipsec.h" 14 #endif 15 #include <rte_time.h> 16 #include <rte_hash.h> 17 #include <rte_pci.h> 18 #include <rte_bus_pci.h> 19 #include <rte_tm_driver.h> 20 21 /* need update link, bit flag */ 22 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0) 23 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1) 24 #define IXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2) 25 #define IXGBE_FLAG_MACSEC (uint32_t)(1 << 3) 26 #define IXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4) 27 28 /* 29 * Defines that were not part of ixgbe_type.h as they are not used by the 30 * FreeBSD driver. 31 */ 32 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */ 33 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */ 34 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */ 35 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30 36 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3 37 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */ 38 #define IXGBE_NB_STAT_MAPPING_REGS 32 39 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */ 40 #define IXGBE_VFTA_SIZE 128 41 #define IXGBE_VLAN_TAG_SIZE 4 42 #define IXGBE_MAX_RX_QUEUE_NUM 128 43 #define IXGBE_MAX_INTR_QUEUE_NUM 15 44 #define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM 45 #define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM 46 #define IXGBE_NONE_MODE_TX_NB_QUEUES 64 47 48 #ifndef NBBY 49 #define NBBY 8 /* number of bits in a byte */ 50 #endif 51 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY)) 52 53 /* EITR Interval is in 2048ns uinits for 1G and 10G link */ 54 #define IXGBE_EITR_INTERVAL_UNIT_NS 2048 55 #define IXGBE_EITR_ITR_INT_SHIFT 3 56 #define IXGBE_EITR_INTERVAL_US(us) \ 57 (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \ 58 IXGBE_EITR_ITR_INT_MASK) 59 60 61 /* Loopback operation modes */ 62 /* 82599 specific loopback operation types */ 63 #define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */ 64 #define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */ 65 66 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */ 67 68 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF 69 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \ 70 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT) 71 72 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8 73 74 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */ 75 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */ 76 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */ 77 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */ 78 79 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */ 80 #define IXGBE_ETQF_SHIFT 16 81 #define IXGBE_ETQF_UP_EN 0x00080000 82 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */ 83 #define IXGBE_ETQF_MAX_PRI 7 84 85 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */ 86 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */ 87 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */ 88 89 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000 90 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */ 91 #define IXGBE_L34T_IMIR_LLI 0x00100000 92 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000 93 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21 94 #define IXGBE_5TUPLE_MAX_PRI 7 95 #define IXGBE_5TUPLE_MIN_PRI 1 96 97 #define IXGBE_RSS_OFFLOAD_ALL ( \ 98 ETH_RSS_IPV4 | \ 99 ETH_RSS_NONFRAG_IPV4_TCP | \ 100 ETH_RSS_NONFRAG_IPV4_UDP | \ 101 ETH_RSS_IPV6 | \ 102 ETH_RSS_NONFRAG_IPV6_TCP | \ 103 ETH_RSS_NONFRAG_IPV6_UDP | \ 104 ETH_RSS_IPV6_EX | \ 105 ETH_RSS_IPV6_TCP_EX | \ 106 ETH_RSS_IPV6_UDP_EX) 107 108 #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */ 109 #define IXGBE_VF_MAXMSIVECTOR 1 110 111 #define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 112 #define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 113 114 #define IXGBE_SECTX_MINSECIFG_MASK 0x0000000F 115 116 #define IXGBE_MACSEC_PNTHRSH 0xFFFFFE00 117 118 #define IXGBE_MAX_FDIR_FILTER_NUM (1024 * 32) 119 #define IXGBE_MAX_L2_TN_FILTER_NUM 128 120 121 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\ 122 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\ 123 return -ENOTSUP;\ 124 } while (0) 125 126 #define MAC_TYPE_FILTER_SUP(type) do {\ 127 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\ 128 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\ 129 (type) != ixgbe_mac_X550EM_a)\ 130 return -ENOTSUP;\ 131 } while (0) 132 133 /* Link speed for X550 auto negotiation */ 134 #define IXGBE_LINK_SPEED_X550_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \ 135 IXGBE_LINK_SPEED_1GB_FULL | \ 136 IXGBE_LINK_SPEED_2_5GB_FULL | \ 137 IXGBE_LINK_SPEED_5GB_FULL | \ 138 IXGBE_LINK_SPEED_10GB_FULL) 139 140 /* 141 * Information about the fdir mode. 142 */ 143 struct ixgbe_hw_fdir_mask { 144 uint16_t vlan_tci_mask; 145 uint32_t src_ipv4_mask; 146 uint32_t dst_ipv4_mask; 147 uint16_t src_ipv6_mask; 148 uint16_t dst_ipv6_mask; 149 uint16_t src_port_mask; 150 uint16_t dst_port_mask; 151 uint16_t flex_bytes_mask; 152 uint8_t mac_addr_byte_mask; 153 uint32_t tunnel_id_mask; 154 uint8_t tunnel_type_mask; 155 }; 156 157 struct ixgbe_fdir_filter { 158 TAILQ_ENTRY(ixgbe_fdir_filter) entries; 159 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/ 160 uint32_t fdirflags; /* drop or forward */ 161 uint32_t fdirhash; /* hash value for fdir */ 162 uint8_t queue; /* assigned rx queue */ 163 }; 164 165 /* list of fdir filters */ 166 TAILQ_HEAD(ixgbe_fdir_filter_list, ixgbe_fdir_filter); 167 168 struct ixgbe_fdir_rule { 169 struct ixgbe_hw_fdir_mask mask; 170 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/ 171 bool b_spec; /* If TRUE, ixgbe_fdir, fdirflags, queue have meaning. */ 172 bool b_mask; /* If TRUE, mask has meaning. */ 173 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */ 174 uint32_t fdirflags; /* drop or forward */ 175 uint32_t soft_id; /* an unique value for this rule */ 176 uint8_t queue; /* assigned rx queue */ 177 uint8_t flex_bytes_offset; 178 }; 179 180 struct ixgbe_hw_fdir_info { 181 struct ixgbe_hw_fdir_mask mask; 182 uint8_t flex_bytes_offset; 183 uint16_t collision; 184 uint16_t free; 185 uint16_t maxhash; 186 uint8_t maxlen; 187 uint64_t add; 188 uint64_t remove; 189 uint64_t f_add; 190 uint64_t f_remove; 191 struct ixgbe_fdir_filter_list fdir_list; /* filter list*/ 192 /* store the pointers of the filters, index is the hash value. */ 193 struct ixgbe_fdir_filter **hash_map; 194 struct rte_hash *hash_handle; /* cuckoo hash handler */ 195 bool mask_added; /* If already got mask from consistent filter */ 196 }; 197 198 struct ixgbe_rte_flow_rss_conf { 199 struct rte_eth_rss_conf rss_conf; /**< RSS parameters. */ 200 uint16_t num; /**< Number of entries in queue[]. */ 201 uint16_t queue[IXGBE_MAX_RX_QUEUE_NUM]; /**< Queues indices to use. */ 202 }; 203 204 /* structure for interrupt relative data */ 205 struct ixgbe_interrupt { 206 uint32_t flags; 207 uint32_t mask; 208 /*to save original mask during delayed handler */ 209 uint32_t mask_original; 210 }; 211 212 struct ixgbe_stat_mapping_registers { 213 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS]; 214 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS]; 215 }; 216 217 struct ixgbe_vfta { 218 uint32_t vfta[IXGBE_VFTA_SIZE]; 219 }; 220 221 struct ixgbe_hwstrip { 222 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE]; 223 }; 224 225 /* 226 * VF data which used by PF host only 227 */ 228 #define IXGBE_MAX_VF_MC_ENTRIES 30 229 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */ 230 #define IXGBE_MAX_UTA 128 231 232 struct ixgbe_uta_info { 233 uint8_t uc_filter_type; 234 uint16_t uta_in_use; 235 uint32_t uta_shadow[IXGBE_MAX_UTA]; 236 }; 237 238 #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */ 239 240 struct ixgbe_mirror_info { 241 struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES]; 242 /**< store PF mirror rules configuration*/ 243 }; 244 245 struct ixgbe_vf_info { 246 uint8_t vf_mac_addresses[ETHER_ADDR_LEN]; 247 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 248 uint16_t num_vf_mc_hashes; 249 uint16_t default_vf_vlan_id; 250 uint16_t vlans_enabled; 251 bool clear_to_send; 252 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF]; 253 uint16_t vlan_count; 254 uint8_t spoofchk_enabled; 255 uint8_t api_version; 256 }; 257 258 /* 259 * Possible l4type of 5tuple filters. 260 */ 261 enum ixgbe_5tuple_protocol { 262 IXGBE_FILTER_PROTOCOL_TCP = 0, 263 IXGBE_FILTER_PROTOCOL_UDP, 264 IXGBE_FILTER_PROTOCOL_SCTP, 265 IXGBE_FILTER_PROTOCOL_NONE, 266 }; 267 268 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter); 269 270 struct ixgbe_5tuple_filter_info { 271 uint32_t dst_ip; 272 uint32_t src_ip; 273 uint16_t dst_port; 274 uint16_t src_port; 275 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */ 276 uint8_t priority; /* seven levels (001b-111b), 111b is highest, 277 used when more than one filter matches. */ 278 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */ 279 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */ 280 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */ 281 src_port_mask:1, /* if mask is 1b, do not compare src port. */ 282 proto_mask:1; /* if mask is 1b, do not compare protocol. */ 283 }; 284 285 /* 5tuple filter structure */ 286 struct ixgbe_5tuple_filter { 287 TAILQ_ENTRY(ixgbe_5tuple_filter) entries; 288 uint16_t index; /* the index of 5tuple filter */ 289 struct ixgbe_5tuple_filter_info filter_info; 290 uint16_t queue; /* rx queue assigned to */ 291 }; 292 293 #define IXGBE_5TUPLE_ARRAY_SIZE \ 294 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \ 295 (sizeof(uint32_t) * NBBY)) 296 297 struct ixgbe_ethertype_filter { 298 uint16_t ethertype; 299 uint32_t etqf; 300 uint32_t etqs; 301 /** 302 * If this filter is added by configuration, 303 * it should not be removed. 304 */ 305 bool conf; 306 }; 307 308 /* 309 * Structure to store filters' info. 310 */ 311 struct ixgbe_filter_info { 312 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */ 313 /* store used ethertype filters*/ 314 struct ixgbe_ethertype_filter ethertype_filters[IXGBE_MAX_ETQF_FILTERS]; 315 /* Bit mask for every used 5tuple filter */ 316 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE]; 317 struct ixgbe_5tuple_filter_list fivetuple_list; 318 /* store the SYN filter info */ 319 uint32_t syn_info; 320 /* store the rss filter info */ 321 struct ixgbe_rte_flow_rss_conf rss_info; 322 }; 323 324 struct ixgbe_l2_tn_key { 325 enum rte_eth_tunnel_type l2_tn_type; 326 uint32_t tn_id; 327 }; 328 329 struct ixgbe_l2_tn_filter { 330 TAILQ_ENTRY(ixgbe_l2_tn_filter) entries; 331 struct ixgbe_l2_tn_key key; 332 uint32_t pool; 333 }; 334 335 TAILQ_HEAD(ixgbe_l2_tn_filter_list, ixgbe_l2_tn_filter); 336 337 struct ixgbe_l2_tn_info { 338 struct ixgbe_l2_tn_filter_list l2_tn_list; 339 struct ixgbe_l2_tn_filter **hash_map; 340 struct rte_hash *hash_handle; 341 bool e_tag_en; /* e-tag enabled */ 342 bool e_tag_fwd_en; /* e-tag based forwarding enabled */ 343 bool e_tag_ether_type; /* ether type for e-tag */ 344 }; 345 346 struct rte_flow { 347 enum rte_filter_type filter_type; 348 void *rule; 349 }; 350 351 /* 352 * Statistics counters collected by the MACsec 353 */ 354 struct ixgbe_macsec_stats { 355 /* TX port statistics */ 356 uint64_t out_pkts_untagged; 357 uint64_t out_pkts_encrypted; 358 uint64_t out_pkts_protected; 359 uint64_t out_octets_encrypted; 360 uint64_t out_octets_protected; 361 362 /* RX port statistics */ 363 uint64_t in_pkts_untagged; 364 uint64_t in_pkts_badtag; 365 uint64_t in_pkts_nosci; 366 uint64_t in_pkts_unknownsci; 367 uint64_t in_octets_decrypted; 368 uint64_t in_octets_validated; 369 370 /* RX SC statistics */ 371 uint64_t in_pkts_unchecked; 372 uint64_t in_pkts_delayed; 373 uint64_t in_pkts_late; 374 375 /* RX SA statistics */ 376 uint64_t in_pkts_ok; 377 uint64_t in_pkts_invalid; 378 uint64_t in_pkts_notvalid; 379 uint64_t in_pkts_unusedsa; 380 uint64_t in_pkts_notusingsa; 381 }; 382 383 /* The configuration of bandwidth */ 384 struct ixgbe_bw_conf { 385 uint8_t tc_num; /* Number of TCs. */ 386 }; 387 388 /* Struct to store Traffic Manager shaper profile. */ 389 struct ixgbe_tm_shaper_profile { 390 TAILQ_ENTRY(ixgbe_tm_shaper_profile) node; 391 uint32_t shaper_profile_id; 392 uint32_t reference_count; 393 struct rte_tm_shaper_params profile; 394 }; 395 396 TAILQ_HEAD(ixgbe_shaper_profile_list, ixgbe_tm_shaper_profile); 397 398 /* node type of Traffic Manager */ 399 enum ixgbe_tm_node_type { 400 IXGBE_TM_NODE_TYPE_PORT, 401 IXGBE_TM_NODE_TYPE_TC, 402 IXGBE_TM_NODE_TYPE_QUEUE, 403 IXGBE_TM_NODE_TYPE_MAX, 404 }; 405 406 /* Struct to store Traffic Manager node configuration. */ 407 struct ixgbe_tm_node { 408 TAILQ_ENTRY(ixgbe_tm_node) node; 409 uint32_t id; 410 uint32_t priority; 411 uint32_t weight; 412 uint32_t reference_count; 413 uint16_t no; 414 struct ixgbe_tm_node *parent; 415 struct ixgbe_tm_shaper_profile *shaper_profile; 416 struct rte_tm_node_params params; 417 }; 418 419 TAILQ_HEAD(ixgbe_tm_node_list, ixgbe_tm_node); 420 421 /* The configuration of Traffic Manager */ 422 struct ixgbe_tm_conf { 423 struct ixgbe_shaper_profile_list shaper_profile_list; 424 struct ixgbe_tm_node *root; /* root node - port */ 425 struct ixgbe_tm_node_list tc_list; /* node list for all the TCs */ 426 struct ixgbe_tm_node_list queue_list; /* node list for all the queues */ 427 /** 428 * The number of added TC nodes. 429 * It should be no more than the TC number of this port. 430 */ 431 uint32_t nb_tc_node; 432 /** 433 * The number of added queue nodes. 434 * It should be no more than the queue number of this port. 435 */ 436 uint32_t nb_queue_node; 437 /** 438 * This flag is used to check if APP can change the TM node 439 * configuration. 440 * When it's true, means the configuration is applied to HW, 441 * APP should not change the configuration. 442 * As we don't support on-the-fly configuration, when starting 443 * the port, APP should call the hierarchy_commit API to set this 444 * flag to true. When stopping the port, this flag should be set 445 * to false. 446 */ 447 bool committed; 448 }; 449 450 /* 451 * Structure to store private data for each driver instance (for each port). 452 */ 453 struct ixgbe_adapter { 454 struct ixgbe_hw hw; 455 struct ixgbe_hw_stats stats; 456 struct ixgbe_macsec_stats macsec_stats; 457 struct ixgbe_hw_fdir_info fdir; 458 struct ixgbe_interrupt intr; 459 struct ixgbe_stat_mapping_registers stat_mappings; 460 struct ixgbe_vfta shadow_vfta; 461 struct ixgbe_hwstrip hwstrip; 462 struct ixgbe_dcb_config dcb_config; 463 struct ixgbe_mirror_info mr_data; 464 struct ixgbe_vf_info *vfdata; 465 struct ixgbe_uta_info uta_info; 466 #ifdef RTE_LIBRTE_IXGBE_BYPASS 467 struct ixgbe_bypass_info bps; 468 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 469 struct ixgbe_filter_info filter; 470 struct ixgbe_l2_tn_info l2_tn; 471 struct ixgbe_bw_conf bw_conf; 472 #ifdef RTE_LIBRTE_SECURITY 473 struct ixgbe_ipsec ipsec; 474 #endif 475 bool rx_bulk_alloc_allowed; 476 bool rx_vec_allowed; 477 struct rte_timecounter systime_tc; 478 struct rte_timecounter rx_tstamp_tc; 479 struct rte_timecounter tx_tstamp_tc; 480 struct ixgbe_tm_conf tm_conf; 481 }; 482 483 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\ 484 (&((struct ixgbe_adapter *)adapter)->hw) 485 486 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \ 487 (&((struct ixgbe_adapter *)adapter)->stats) 488 489 #define IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(adapter) \ 490 (&((struct ixgbe_adapter *)adapter)->macsec_stats) 491 492 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \ 493 (&((struct ixgbe_adapter *)adapter)->intr) 494 495 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \ 496 (&((struct ixgbe_adapter *)adapter)->fdir) 497 498 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \ 499 (&((struct ixgbe_adapter *)adapter)->stat_mappings) 500 501 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \ 502 (&((struct ixgbe_adapter *)adapter)->shadow_vfta) 503 504 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \ 505 (&((struct ixgbe_adapter *)adapter)->hwstrip) 506 507 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \ 508 (&((struct ixgbe_adapter *)adapter)->dcb_config) 509 510 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \ 511 (&((struct ixgbe_adapter *)adapter)->vfdata) 512 513 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \ 514 (&((struct ixgbe_adapter *)adapter)->mr_data) 515 516 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \ 517 (&((struct ixgbe_adapter *)adapter)->uta_info) 518 519 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \ 520 (&((struct ixgbe_adapter *)adapter)->filter) 521 522 #define IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(adapter) \ 523 (&((struct ixgbe_adapter *)adapter)->l2_tn) 524 525 #define IXGBE_DEV_PRIVATE_TO_BW_CONF(adapter) \ 526 (&((struct ixgbe_adapter *)adapter)->bw_conf) 527 528 #define IXGBE_DEV_PRIVATE_TO_TM_CONF(adapter) \ 529 (&((struct ixgbe_adapter *)adapter)->tm_conf) 530 531 #define IXGBE_DEV_PRIVATE_TO_IPSEC(adapter)\ 532 (&((struct ixgbe_adapter *)adapter)->ipsec) 533 534 /* 535 * RX/TX function prototypes 536 */ 537 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev); 538 539 void ixgbe_dev_free_queues(struct rte_eth_dev *dev); 540 541 void ixgbe_dev_rx_queue_release(void *rxq); 542 543 void ixgbe_dev_tx_queue_release(void *txq); 544 545 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, 546 uint16_t nb_rx_desc, unsigned int socket_id, 547 const struct rte_eth_rxconf *rx_conf, 548 struct rte_mempool *mb_pool); 549 550 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, 551 uint16_t nb_tx_desc, unsigned int socket_id, 552 const struct rte_eth_txconf *tx_conf); 553 554 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, 555 uint16_t rx_queue_id); 556 557 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset); 558 559 int ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset); 560 int ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset); 561 562 int ixgbe_dev_rx_init(struct rte_eth_dev *dev); 563 564 void ixgbe_dev_tx_init(struct rte_eth_dev *dev); 565 566 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev); 567 568 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); 569 570 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); 571 572 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); 573 574 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); 575 576 void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 577 struct rte_eth_rxq_info *qinfo); 578 579 void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 580 struct rte_eth_txq_info *qinfo); 581 582 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev); 583 584 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev); 585 586 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev); 587 588 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 589 uint16_t nb_pkts); 590 591 uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts, 592 uint16_t nb_pkts); 593 594 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue, 595 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 596 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, 597 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 598 599 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 600 uint16_t nb_pkts); 601 602 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts, 603 uint16_t nb_pkts); 604 605 uint16_t ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 606 uint16_t nb_pkts); 607 608 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 609 struct rte_eth_rss_conf *rss_conf); 610 611 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 612 struct rte_eth_rss_conf *rss_conf); 613 614 uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type); 615 616 uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx); 617 618 uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type); 619 620 uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i); 621 622 bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type); 623 624 int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 625 struct rte_eth_ntuple_filter *filter, 626 bool add); 627 int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 628 struct rte_eth_ethertype_filter *filter, 629 bool add); 630 int ixgbe_syn_filter_set(struct rte_eth_dev *dev, 631 struct rte_eth_syn_filter *filter, 632 bool add); 633 int 634 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 635 struct rte_eth_l2_tunnel_conf *l2_tunnel, 636 bool restore); 637 int 638 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 639 struct rte_eth_l2_tunnel_conf *l2_tunnel); 640 void ixgbe_filterlist_init(void); 641 void ixgbe_filterlist_flush(void); 642 /* 643 * Flow director function prototypes 644 */ 645 int ixgbe_fdir_configure(struct rte_eth_dev *dev); 646 int ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev); 647 int ixgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev, 648 uint16_t offset); 649 int ixgbe_fdir_filter_program(struct rte_eth_dev *dev, 650 struct ixgbe_fdir_rule *rule, 651 bool del, bool update); 652 653 void ixgbe_configure_dcb(struct rte_eth_dev *dev); 654 655 /* 656 * misc function prototypes 657 */ 658 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev); 659 660 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev); 661 662 void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev); 663 664 void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev); 665 666 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev); 667 668 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev); 669 670 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev); 671 672 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev); 673 674 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val); 675 676 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev, 677 enum rte_filter_op filter_op, void *arg); 678 void ixgbe_fdir_filter_restore(struct rte_eth_dev *dev); 679 int ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev); 680 681 extern const struct rte_flow_ops ixgbe_flow_ops; 682 683 void ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev); 684 void ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev); 685 void ixgbe_clear_syn_filter(struct rte_eth_dev *dev); 686 int ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev); 687 688 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw); 689 690 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw); 691 692 int ixgbe_vt_check(struct ixgbe_hw *hw); 693 int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 694 uint16_t tx_rate, uint64_t q_msk); 695 bool is_ixgbe_supported(struct rte_eth_dev *dev); 696 int ixgbe_tm_ops_get(struct rte_eth_dev *dev, void *ops); 697 void ixgbe_tm_conf_init(struct rte_eth_dev *dev); 698 void ixgbe_tm_conf_uninit(struct rte_eth_dev *dev); 699 int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx, 700 uint16_t tx_rate); 701 int ixgbe_config_rss_filter(struct rte_eth_dev *dev, 702 struct ixgbe_rte_flow_rss_conf *conf, bool add); 703 704 static inline int 705 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info, 706 uint16_t ethertype) 707 { 708 int i; 709 710 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 711 if (filter_info->ethertype_filters[i].ethertype == ethertype && 712 (filter_info->ethertype_mask & (1 << i))) 713 return i; 714 } 715 return -1; 716 } 717 718 static inline int 719 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info, 720 struct ixgbe_ethertype_filter *ethertype_filter) 721 { 722 int i; 723 724 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 725 if (!(filter_info->ethertype_mask & (1 << i))) { 726 filter_info->ethertype_mask |= 1 << i; 727 filter_info->ethertype_filters[i].ethertype = 728 ethertype_filter->ethertype; 729 filter_info->ethertype_filters[i].etqf = 730 ethertype_filter->etqf; 731 filter_info->ethertype_filters[i].etqs = 732 ethertype_filter->etqs; 733 filter_info->ethertype_filters[i].conf = 734 ethertype_filter->conf; 735 return i; 736 } 737 } 738 return -1; 739 } 740 741 static inline int 742 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info, 743 uint8_t idx) 744 { 745 if (idx >= IXGBE_MAX_ETQF_FILTERS) 746 return -1; 747 filter_info->ethertype_mask &= ~(1 << idx); 748 filter_info->ethertype_filters[idx].ethertype = 0; 749 filter_info->ethertype_filters[idx].etqf = 0; 750 filter_info->ethertype_filters[idx].etqs = 0; 751 filter_info->ethertype_filters[idx].etqs = FALSE; 752 return idx; 753 } 754 755 #endif /* _IXGBE_ETHDEV_H_ */ 756