1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2016 Intel Corporation 3 */ 4 5 #ifndef _IXGBE_ETHDEV_H_ 6 #define _IXGBE_ETHDEV_H_ 7 8 #include <stdint.h> 9 10 #include "base/ixgbe_type.h" 11 #include "base/ixgbe_dcb.h" 12 #include "base/ixgbe_dcb_82599.h" 13 #include "base/ixgbe_dcb_82598.h" 14 #include "ixgbe_bypass.h" 15 #ifdef RTE_LIBRTE_SECURITY 16 #include "ixgbe_ipsec.h" 17 #endif 18 #include <rte_flow.h> 19 #include <rte_time.h> 20 #include <rte_hash.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_tm_driver.h> 24 25 /* need update link, bit flag */ 26 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0) 27 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1) 28 #define IXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2) 29 #define IXGBE_FLAG_MACSEC (uint32_t)(1 << 3) 30 #define IXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4) 31 32 /* 33 * Defines that were not part of ixgbe_type.h as they are not used by the 34 * FreeBSD driver. 35 */ 36 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */ 37 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */ 38 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */ 39 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30 40 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3 41 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */ 42 #define IXGBE_NB_STAT_MAPPING_REGS 32 43 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */ 44 #define IXGBE_VFTA_SIZE 128 45 #define IXGBE_VLAN_TAG_SIZE 4 46 #define IXGBE_HKEY_MAX_INDEX 10 47 #define IXGBE_MAX_RX_QUEUE_NUM 128 48 #define IXGBE_MAX_INTR_QUEUE_NUM 15 49 #define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM 50 #define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM 51 #define IXGBE_NONE_MODE_TX_NB_QUEUES 64 52 53 #ifndef NBBY 54 #define NBBY 8 /* number of bits in a byte */ 55 #endif 56 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY)) 57 58 /* EITR Interval is in 2048ns uinits for 1G and 10G link */ 59 #define IXGBE_EITR_INTERVAL_UNIT_NS 2048 60 #define IXGBE_EITR_ITR_INT_SHIFT 3 61 #define IXGBE_EITR_INTERVAL_US(us) \ 62 (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \ 63 IXGBE_EITR_ITR_INT_MASK) 64 65 #define IXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */ 66 67 /* Loopback operation modes */ 68 #define IXGBE_LPBK_NONE 0x0 /* Default value. Loopback is disabled. */ 69 #define IXGBE_LPBK_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */ 70 /* X540-X550 specific loopback operations */ 71 #define IXGBE_MII_AUTONEG_ENABLE 0x1000 /* Auto-negociation enable (default = 1) */ 72 73 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */ 74 75 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF 76 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \ 77 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT) 78 79 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8 80 81 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */ 82 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */ 83 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */ 84 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */ 85 86 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */ 87 #define IXGBE_ETQF_SHIFT 16 88 #define IXGBE_ETQF_UP_EN 0x00080000 89 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */ 90 #define IXGBE_ETQF_MAX_PRI 7 91 92 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */ 93 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */ 94 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */ 95 96 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000 97 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */ 98 #define IXGBE_L34T_IMIR_LLI 0x00100000 99 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000 100 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21 101 #define IXGBE_5TUPLE_MAX_PRI 7 102 #define IXGBE_5TUPLE_MIN_PRI 1 103 104 /* bit of VXLAN tunnel type | 7 bits of zeros | 8 bits of zeros*/ 105 #define IXGBE_FDIR_VXLAN_TUNNEL_TYPE 0x8000 106 /* bit of NVGRE tunnel type | 7 bits of zeros | 8 bits of zeros*/ 107 #define IXGBE_FDIR_NVGRE_TUNNEL_TYPE 0x0 108 109 #define IXGBE_RSS_OFFLOAD_ALL ( \ 110 ETH_RSS_IPV4 | \ 111 ETH_RSS_NONFRAG_IPV4_TCP | \ 112 ETH_RSS_NONFRAG_IPV4_UDP | \ 113 ETH_RSS_IPV6 | \ 114 ETH_RSS_NONFRAG_IPV6_TCP | \ 115 ETH_RSS_NONFRAG_IPV6_UDP | \ 116 ETH_RSS_IPV6_EX | \ 117 ETH_RSS_IPV6_TCP_EX | \ 118 ETH_RSS_IPV6_UDP_EX) 119 120 #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */ 121 #define IXGBE_VF_MAXMSIVECTOR 1 122 123 #define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 124 #define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 125 126 #define IXGBE_SECTX_MINSECIFG_MASK 0x0000000F 127 128 #define IXGBE_MACSEC_PNTHRSH 0xFFFFFE00 129 130 #define IXGBE_MAX_FDIR_FILTER_NUM (1024 * 32) 131 #define IXGBE_MAX_L2_TN_FILTER_NUM 128 132 133 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\ 134 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\ 135 return -ENOTSUP;\ 136 } while (0) 137 138 #define MAC_TYPE_FILTER_SUP(type) do {\ 139 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\ 140 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\ 141 (type) != ixgbe_mac_X550EM_a)\ 142 return -ENOTSUP;\ 143 } while (0) 144 145 /* Link speed for X550 auto negotiation */ 146 #define IXGBE_LINK_SPEED_X550_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \ 147 IXGBE_LINK_SPEED_1GB_FULL | \ 148 IXGBE_LINK_SPEED_2_5GB_FULL | \ 149 IXGBE_LINK_SPEED_5GB_FULL | \ 150 IXGBE_LINK_SPEED_10GB_FULL) 151 152 /* 153 * Information about the fdir mode. 154 */ 155 struct ixgbe_hw_fdir_mask { 156 uint16_t vlan_tci_mask; 157 uint32_t src_ipv4_mask; 158 uint32_t dst_ipv4_mask; 159 uint16_t src_ipv6_mask; 160 uint16_t dst_ipv6_mask; 161 uint16_t src_port_mask; 162 uint16_t dst_port_mask; 163 uint16_t flex_bytes_mask; 164 uint8_t mac_addr_byte_mask; 165 uint32_t tunnel_id_mask; 166 uint8_t tunnel_type_mask; 167 }; 168 169 struct ixgbe_fdir_filter { 170 TAILQ_ENTRY(ixgbe_fdir_filter) entries; 171 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/ 172 uint32_t fdirflags; /* drop or forward */ 173 uint32_t fdirhash; /* hash value for fdir */ 174 uint8_t queue; /* assigned rx queue */ 175 }; 176 177 /* list of fdir filters */ 178 TAILQ_HEAD(ixgbe_fdir_filter_list, ixgbe_fdir_filter); 179 180 struct ixgbe_fdir_rule { 181 struct ixgbe_hw_fdir_mask mask; 182 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/ 183 bool b_spec; /* If TRUE, ixgbe_fdir, fdirflags, queue have meaning. */ 184 bool b_mask; /* If TRUE, mask has meaning. */ 185 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */ 186 uint32_t fdirflags; /* drop or forward */ 187 uint32_t soft_id; /* an unique value for this rule */ 188 uint8_t queue; /* assigned rx queue */ 189 uint8_t flex_bytes_offset; 190 }; 191 192 struct ixgbe_hw_fdir_info { 193 struct ixgbe_hw_fdir_mask mask; 194 uint8_t flex_bytes_offset; 195 uint16_t collision; 196 uint16_t free; 197 uint16_t maxhash; 198 uint8_t maxlen; 199 uint64_t add; 200 uint64_t remove; 201 uint64_t f_add; 202 uint64_t f_remove; 203 struct ixgbe_fdir_filter_list fdir_list; /* filter list*/ 204 /* store the pointers of the filters, index is the hash value. */ 205 struct ixgbe_fdir_filter **hash_map; 206 struct rte_hash *hash_handle; /* cuckoo hash handler */ 207 bool mask_added; /* If already got mask from consistent filter */ 208 }; 209 210 struct ixgbe_rte_flow_rss_conf { 211 struct rte_flow_action_rss conf; /**< RSS parameters. */ 212 uint8_t key[IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t)]; /* Hash key. */ 213 uint16_t queue[IXGBE_MAX_RX_QUEUE_NUM]; /**< Queues indices to use. */ 214 }; 215 216 /* structure for interrupt relative data */ 217 struct ixgbe_interrupt { 218 uint32_t flags; 219 uint32_t mask; 220 /*to save original mask during delayed handler */ 221 uint32_t mask_original; 222 }; 223 224 struct ixgbe_stat_mapping_registers { 225 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS]; 226 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS]; 227 }; 228 229 struct ixgbe_vfta { 230 uint32_t vfta[IXGBE_VFTA_SIZE]; 231 }; 232 233 struct ixgbe_hwstrip { 234 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE]; 235 }; 236 237 /* 238 * VF data which used by PF host only 239 */ 240 #define IXGBE_MAX_VF_MC_ENTRIES 30 241 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */ 242 #define IXGBE_MAX_UTA 128 243 244 struct ixgbe_uta_info { 245 uint8_t uc_filter_type; 246 uint16_t uta_in_use; 247 uint32_t uta_shadow[IXGBE_MAX_UTA]; 248 }; 249 250 #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */ 251 252 struct ixgbe_mirror_info { 253 struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES]; 254 /**< store PF mirror rules configuration*/ 255 }; 256 257 struct ixgbe_vf_info { 258 uint8_t vf_mac_addresses[ETHER_ADDR_LEN]; 259 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 260 uint16_t num_vf_mc_hashes; 261 uint16_t default_vf_vlan_id; 262 uint16_t vlans_enabled; 263 bool clear_to_send; 264 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF]; 265 uint16_t vlan_count; 266 uint8_t spoofchk_enabled; 267 uint8_t api_version; 268 uint16_t switch_domain_id; 269 }; 270 271 /* 272 * Possible l4type of 5tuple filters. 273 */ 274 enum ixgbe_5tuple_protocol { 275 IXGBE_FILTER_PROTOCOL_TCP = 0, 276 IXGBE_FILTER_PROTOCOL_UDP, 277 IXGBE_FILTER_PROTOCOL_SCTP, 278 IXGBE_FILTER_PROTOCOL_NONE, 279 }; 280 281 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter); 282 283 struct ixgbe_5tuple_filter_info { 284 uint32_t dst_ip; 285 uint32_t src_ip; 286 uint16_t dst_port; 287 uint16_t src_port; 288 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */ 289 uint8_t priority; /* seven levels (001b-111b), 111b is highest, 290 used when more than one filter matches. */ 291 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */ 292 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */ 293 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */ 294 src_port_mask:1, /* if mask is 1b, do not compare src port. */ 295 proto_mask:1; /* if mask is 1b, do not compare protocol. */ 296 }; 297 298 /* 5tuple filter structure */ 299 struct ixgbe_5tuple_filter { 300 TAILQ_ENTRY(ixgbe_5tuple_filter) entries; 301 uint16_t index; /* the index of 5tuple filter */ 302 struct ixgbe_5tuple_filter_info filter_info; 303 uint16_t queue; /* rx queue assigned to */ 304 }; 305 306 #define IXGBE_5TUPLE_ARRAY_SIZE \ 307 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \ 308 (sizeof(uint32_t) * NBBY)) 309 310 struct ixgbe_ethertype_filter { 311 uint16_t ethertype; 312 uint32_t etqf; 313 uint32_t etqs; 314 /** 315 * If this filter is added by configuration, 316 * it should not be removed. 317 */ 318 bool conf; 319 }; 320 321 /* 322 * Structure to store filters' info. 323 */ 324 struct ixgbe_filter_info { 325 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */ 326 /* store used ethertype filters*/ 327 struct ixgbe_ethertype_filter ethertype_filters[IXGBE_MAX_ETQF_FILTERS]; 328 /* Bit mask for every used 5tuple filter */ 329 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE]; 330 struct ixgbe_5tuple_filter_list fivetuple_list; 331 /* store the SYN filter info */ 332 uint32_t syn_info; 333 /* store the rss filter info */ 334 struct ixgbe_rte_flow_rss_conf rss_info; 335 }; 336 337 struct ixgbe_l2_tn_key { 338 enum rte_eth_tunnel_type l2_tn_type; 339 uint32_t tn_id; 340 }; 341 342 struct ixgbe_l2_tn_filter { 343 TAILQ_ENTRY(ixgbe_l2_tn_filter) entries; 344 struct ixgbe_l2_tn_key key; 345 uint32_t pool; 346 }; 347 348 TAILQ_HEAD(ixgbe_l2_tn_filter_list, ixgbe_l2_tn_filter); 349 350 struct ixgbe_l2_tn_info { 351 struct ixgbe_l2_tn_filter_list l2_tn_list; 352 struct ixgbe_l2_tn_filter **hash_map; 353 struct rte_hash *hash_handle; 354 bool e_tag_en; /* e-tag enabled */ 355 bool e_tag_fwd_en; /* e-tag based forwarding enabled */ 356 bool e_tag_ether_type; /* ether type for e-tag */ 357 }; 358 359 struct rte_flow { 360 enum rte_filter_type filter_type; 361 void *rule; 362 }; 363 364 /* 365 * Statistics counters collected by the MACsec 366 */ 367 struct ixgbe_macsec_stats { 368 /* TX port statistics */ 369 uint64_t out_pkts_untagged; 370 uint64_t out_pkts_encrypted; 371 uint64_t out_pkts_protected; 372 uint64_t out_octets_encrypted; 373 uint64_t out_octets_protected; 374 375 /* RX port statistics */ 376 uint64_t in_pkts_untagged; 377 uint64_t in_pkts_badtag; 378 uint64_t in_pkts_nosci; 379 uint64_t in_pkts_unknownsci; 380 uint64_t in_octets_decrypted; 381 uint64_t in_octets_validated; 382 383 /* RX SC statistics */ 384 uint64_t in_pkts_unchecked; 385 uint64_t in_pkts_delayed; 386 uint64_t in_pkts_late; 387 388 /* RX SA statistics */ 389 uint64_t in_pkts_ok; 390 uint64_t in_pkts_invalid; 391 uint64_t in_pkts_notvalid; 392 uint64_t in_pkts_unusedsa; 393 uint64_t in_pkts_notusingsa; 394 }; 395 396 /* The configuration of bandwidth */ 397 struct ixgbe_bw_conf { 398 uint8_t tc_num; /* Number of TCs. */ 399 }; 400 401 /* Struct to store Traffic Manager shaper profile. */ 402 struct ixgbe_tm_shaper_profile { 403 TAILQ_ENTRY(ixgbe_tm_shaper_profile) node; 404 uint32_t shaper_profile_id; 405 uint32_t reference_count; 406 struct rte_tm_shaper_params profile; 407 }; 408 409 TAILQ_HEAD(ixgbe_shaper_profile_list, ixgbe_tm_shaper_profile); 410 411 /* node type of Traffic Manager */ 412 enum ixgbe_tm_node_type { 413 IXGBE_TM_NODE_TYPE_PORT, 414 IXGBE_TM_NODE_TYPE_TC, 415 IXGBE_TM_NODE_TYPE_QUEUE, 416 IXGBE_TM_NODE_TYPE_MAX, 417 }; 418 419 /* Struct to store Traffic Manager node configuration. */ 420 struct ixgbe_tm_node { 421 TAILQ_ENTRY(ixgbe_tm_node) node; 422 uint32_t id; 423 uint32_t priority; 424 uint32_t weight; 425 uint32_t reference_count; 426 uint16_t no; 427 struct ixgbe_tm_node *parent; 428 struct ixgbe_tm_shaper_profile *shaper_profile; 429 struct rte_tm_node_params params; 430 }; 431 432 TAILQ_HEAD(ixgbe_tm_node_list, ixgbe_tm_node); 433 434 /* The configuration of Traffic Manager */ 435 struct ixgbe_tm_conf { 436 struct ixgbe_shaper_profile_list shaper_profile_list; 437 struct ixgbe_tm_node *root; /* root node - port */ 438 struct ixgbe_tm_node_list tc_list; /* node list for all the TCs */ 439 struct ixgbe_tm_node_list queue_list; /* node list for all the queues */ 440 /** 441 * The number of added TC nodes. 442 * It should be no more than the TC number of this port. 443 */ 444 uint32_t nb_tc_node; 445 /** 446 * The number of added queue nodes. 447 * It should be no more than the queue number of this port. 448 */ 449 uint32_t nb_queue_node; 450 /** 451 * This flag is used to check if APP can change the TM node 452 * configuration. 453 * When it's true, means the configuration is applied to HW, 454 * APP should not change the configuration. 455 * As we don't support on-the-fly configuration, when starting 456 * the port, APP should call the hierarchy_commit API to set this 457 * flag to true. When stopping the port, this flag should be set 458 * to false. 459 */ 460 bool committed; 461 }; 462 463 /* 464 * Structure to store private data for each driver instance (for each port). 465 */ 466 struct ixgbe_adapter { 467 struct ixgbe_hw hw; 468 struct ixgbe_hw_stats stats; 469 struct ixgbe_macsec_stats macsec_stats; 470 struct ixgbe_hw_fdir_info fdir; 471 struct ixgbe_interrupt intr; 472 struct ixgbe_stat_mapping_registers stat_mappings; 473 struct ixgbe_vfta shadow_vfta; 474 struct ixgbe_hwstrip hwstrip; 475 struct ixgbe_dcb_config dcb_config; 476 struct ixgbe_mirror_info mr_data; 477 struct ixgbe_vf_info *vfdata; 478 struct ixgbe_uta_info uta_info; 479 #ifdef RTE_LIBRTE_IXGBE_BYPASS 480 struct ixgbe_bypass_info bps; 481 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 482 struct ixgbe_filter_info filter; 483 struct ixgbe_l2_tn_info l2_tn; 484 struct ixgbe_bw_conf bw_conf; 485 #ifdef RTE_LIBRTE_SECURITY 486 struct ixgbe_ipsec ipsec; 487 #endif 488 bool rx_bulk_alloc_allowed; 489 bool rx_vec_allowed; 490 struct rte_timecounter systime_tc; 491 struct rte_timecounter rx_tstamp_tc; 492 struct rte_timecounter tx_tstamp_tc; 493 struct ixgbe_tm_conf tm_conf; 494 495 /* For RSS reta table update */ 496 uint8_t rss_reta_updated; 497 }; 498 499 struct ixgbe_vf_representor { 500 uint16_t vf_id; 501 uint16_t switch_domain_id; 502 struct rte_eth_dev *pf_ethdev; 503 }; 504 505 int ixgbe_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params); 506 int ixgbe_vf_representor_uninit(struct rte_eth_dev *ethdev); 507 508 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\ 509 (&((struct ixgbe_adapter *)adapter)->hw) 510 511 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \ 512 (&((struct ixgbe_adapter *)adapter)->stats) 513 514 #define IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(adapter) \ 515 (&((struct ixgbe_adapter *)adapter)->macsec_stats) 516 517 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \ 518 (&((struct ixgbe_adapter *)adapter)->intr) 519 520 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \ 521 (&((struct ixgbe_adapter *)adapter)->fdir) 522 523 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \ 524 (&((struct ixgbe_adapter *)adapter)->stat_mappings) 525 526 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \ 527 (&((struct ixgbe_adapter *)adapter)->shadow_vfta) 528 529 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \ 530 (&((struct ixgbe_adapter *)adapter)->hwstrip) 531 532 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \ 533 (&((struct ixgbe_adapter *)adapter)->dcb_config) 534 535 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \ 536 (&((struct ixgbe_adapter *)adapter)->vfdata) 537 538 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \ 539 (&((struct ixgbe_adapter *)adapter)->mr_data) 540 541 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \ 542 (&((struct ixgbe_adapter *)adapter)->uta_info) 543 544 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \ 545 (&((struct ixgbe_adapter *)adapter)->filter) 546 547 #define IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(adapter) \ 548 (&((struct ixgbe_adapter *)adapter)->l2_tn) 549 550 #define IXGBE_DEV_PRIVATE_TO_BW_CONF(adapter) \ 551 (&((struct ixgbe_adapter *)adapter)->bw_conf) 552 553 #define IXGBE_DEV_PRIVATE_TO_TM_CONF(adapter) \ 554 (&((struct ixgbe_adapter *)adapter)->tm_conf) 555 556 #define IXGBE_DEV_PRIVATE_TO_IPSEC(adapter)\ 557 (&((struct ixgbe_adapter *)adapter)->ipsec) 558 559 /* 560 * RX/TX function prototypes 561 */ 562 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev); 563 564 void ixgbe_dev_free_queues(struct rte_eth_dev *dev); 565 566 void ixgbe_dev_rx_queue_release(void *rxq); 567 568 void ixgbe_dev_tx_queue_release(void *txq); 569 570 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, 571 uint16_t nb_rx_desc, unsigned int socket_id, 572 const struct rte_eth_rxconf *rx_conf, 573 struct rte_mempool *mb_pool); 574 575 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, 576 uint16_t nb_tx_desc, unsigned int socket_id, 577 const struct rte_eth_txconf *tx_conf); 578 579 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, 580 uint16_t rx_queue_id); 581 582 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset); 583 584 int ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset); 585 int ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset); 586 587 int ixgbe_dev_rx_init(struct rte_eth_dev *dev); 588 589 void ixgbe_dev_tx_init(struct rte_eth_dev *dev); 590 591 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev); 592 593 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); 594 595 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); 596 597 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); 598 599 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); 600 601 void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 602 struct rte_eth_rxq_info *qinfo); 603 604 void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 605 struct rte_eth_txq_info *qinfo); 606 607 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev); 608 609 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev); 610 611 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev); 612 613 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 614 uint16_t nb_pkts); 615 616 uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts, 617 uint16_t nb_pkts); 618 619 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue, 620 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 621 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, 622 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 623 624 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 625 uint16_t nb_pkts); 626 627 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts, 628 uint16_t nb_pkts); 629 630 uint16_t ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 631 uint16_t nb_pkts); 632 633 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 634 struct rte_eth_rss_conf *rss_conf); 635 636 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 637 struct rte_eth_rss_conf *rss_conf); 638 639 uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type); 640 641 uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx); 642 643 uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type); 644 645 uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i); 646 647 bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type); 648 649 int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 650 struct rte_eth_ntuple_filter *filter, 651 bool add); 652 int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 653 struct rte_eth_ethertype_filter *filter, 654 bool add); 655 int ixgbe_syn_filter_set(struct rte_eth_dev *dev, 656 struct rte_eth_syn_filter *filter, 657 bool add); 658 int 659 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 660 struct rte_eth_l2_tunnel_conf *l2_tunnel, 661 bool restore); 662 int 663 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 664 struct rte_eth_l2_tunnel_conf *l2_tunnel); 665 void ixgbe_filterlist_init(void); 666 void ixgbe_filterlist_flush(void); 667 /* 668 * Flow director function prototypes 669 */ 670 int ixgbe_fdir_configure(struct rte_eth_dev *dev); 671 int ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev); 672 int ixgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev, 673 uint16_t offset); 674 int ixgbe_fdir_filter_program(struct rte_eth_dev *dev, 675 struct ixgbe_fdir_rule *rule, 676 bool del, bool update); 677 678 void ixgbe_configure_dcb(struct rte_eth_dev *dev); 679 680 int 681 ixgbe_dev_link_update_share(struct rte_eth_dev *dev, 682 int wait_to_complete, int vf); 683 684 /* 685 * misc function prototypes 686 */ 687 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev); 688 689 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev); 690 691 void ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev); 692 693 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev); 694 695 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev); 696 697 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev); 698 699 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev); 700 701 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val); 702 703 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev, 704 enum rte_filter_op filter_op, void *arg); 705 void ixgbe_fdir_filter_restore(struct rte_eth_dev *dev); 706 int ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev); 707 708 extern const struct rte_flow_ops ixgbe_flow_ops; 709 710 void ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev); 711 void ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev); 712 void ixgbe_clear_syn_filter(struct rte_eth_dev *dev); 713 int ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev); 714 715 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw); 716 717 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw); 718 719 int ixgbe_vt_check(struct ixgbe_hw *hw); 720 int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 721 uint16_t tx_rate, uint64_t q_msk); 722 bool is_ixgbe_supported(struct rte_eth_dev *dev); 723 int ixgbe_tm_ops_get(struct rte_eth_dev *dev, void *ops); 724 void ixgbe_tm_conf_init(struct rte_eth_dev *dev); 725 void ixgbe_tm_conf_uninit(struct rte_eth_dev *dev); 726 int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx, 727 uint16_t tx_rate); 728 int ixgbe_rss_conf_init(struct ixgbe_rte_flow_rss_conf *out, 729 const struct rte_flow_action_rss *in); 730 int ixgbe_action_rss_same(const struct rte_flow_action_rss *comp, 731 const struct rte_flow_action_rss *with); 732 int ixgbe_config_rss_filter(struct rte_eth_dev *dev, 733 struct ixgbe_rte_flow_rss_conf *conf, bool add); 734 735 static inline int 736 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info, 737 uint16_t ethertype) 738 { 739 int i; 740 741 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 742 if (filter_info->ethertype_filters[i].ethertype == ethertype && 743 (filter_info->ethertype_mask & (1 << i))) 744 return i; 745 } 746 return -1; 747 } 748 749 static inline int 750 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info, 751 struct ixgbe_ethertype_filter *ethertype_filter) 752 { 753 int i; 754 755 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 756 if (!(filter_info->ethertype_mask & (1 << i))) { 757 filter_info->ethertype_mask |= 1 << i; 758 filter_info->ethertype_filters[i].ethertype = 759 ethertype_filter->ethertype; 760 filter_info->ethertype_filters[i].etqf = 761 ethertype_filter->etqf; 762 filter_info->ethertype_filters[i].etqs = 763 ethertype_filter->etqs; 764 filter_info->ethertype_filters[i].conf = 765 ethertype_filter->conf; 766 return i; 767 } 768 } 769 return -1; 770 } 771 772 static inline int 773 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info, 774 uint8_t idx) 775 { 776 if (idx >= IXGBE_MAX_ETQF_FILTERS) 777 return -1; 778 filter_info->ethertype_mask &= ~(1 << idx); 779 filter_info->ethertype_filters[idx].ethertype = 0; 780 filter_info->ethertype_filters[idx].etqf = 0; 781 filter_info->ethertype_filters[idx].etqs = 0; 782 filter_info->ethertype_filters[idx].etqs = FALSE; 783 return idx; 784 } 785 786 #endif /* _IXGBE_ETHDEV_H_ */ 787