1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2016 Intel Corporation 3 */ 4 5 #ifndef _IXGBE_ETHDEV_H_ 6 #define _IXGBE_ETHDEV_H_ 7 8 #include <stdint.h> 9 10 #include "base/ixgbe_type.h" 11 #include "base/ixgbe_dcb.h" 12 #include "base/ixgbe_dcb_82599.h" 13 #include "base/ixgbe_dcb_82598.h" 14 #include "ixgbe_bypass.h" 15 #ifdef RTE_LIB_SECURITY 16 #include "ixgbe_ipsec.h" 17 #endif 18 #include <rte_flow.h> 19 #include <rte_time.h> 20 #include <rte_hash.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_tm_driver.h> 24 25 /* need update link, bit flag */ 26 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0) 27 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1) 28 #define IXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2) 29 #define IXGBE_FLAG_MACSEC (uint32_t)(1 << 3) 30 #define IXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4) 31 32 /* 33 * Defines that were not part of ixgbe_type.h as they are not used by the 34 * FreeBSD driver. 35 */ 36 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */ 37 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */ 38 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */ 39 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30 40 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3 41 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */ 42 #define IXGBE_NB_STAT_MAPPING_REGS 32 43 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */ 44 #define IXGBE_VFTA_SIZE 128 45 #define IXGBE_VLAN_TAG_SIZE 4 46 #define IXGBE_HKEY_MAX_INDEX 10 47 #define IXGBE_MAX_RX_QUEUE_NUM 128 48 #define IXGBE_MAX_INTR_QUEUE_NUM 15 49 #define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM 50 #define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM 51 #define IXGBE_NONE_MODE_TX_NB_QUEUES 64 52 53 #ifndef NBBY 54 #define NBBY 8 /* number of bits in a byte */ 55 #endif 56 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY)) 57 58 /* EITR Interval is in 2048ns uinits for 1G and 10G link */ 59 #define IXGBE_EITR_INTERVAL_UNIT_NS 2048 60 #define IXGBE_EITR_ITR_INT_SHIFT 3 61 #define IXGBE_EITR_INTERVAL_US(us) \ 62 (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \ 63 IXGBE_EITR_ITR_INT_MASK) 64 65 #define IXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */ 66 67 /* Loopback operation modes */ 68 #define IXGBE_LPBK_NONE 0x0 /* Default value. Loopback is disabled. */ 69 #define IXGBE_LPBK_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */ 70 /* X540-X550 specific loopback operations */ 71 #define IXGBE_MII_AUTONEG_ENABLE 0x1000 /* Auto-negociation enable (default = 1) */ 72 73 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */ 74 75 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF 76 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \ 77 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT) 78 79 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8 80 81 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */ 82 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */ 83 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */ 84 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */ 85 86 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */ 87 #define IXGBE_ETQF_SHIFT 16 88 #define IXGBE_ETQF_UP_EN 0x00080000 89 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */ 90 #define IXGBE_ETQF_MAX_PRI 7 91 92 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */ 93 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */ 94 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */ 95 96 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000 97 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */ 98 #define IXGBE_L34T_IMIR_LLI 0x00100000 99 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000 100 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21 101 #define IXGBE_5TUPLE_MAX_PRI 7 102 #define IXGBE_5TUPLE_MIN_PRI 1 103 104 /* The overhead from MTU to max frame size. */ 105 #define IXGBE_ETH_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN) 106 107 /* The max frame size with default MTU */ 108 #define IXGBE_ETH_MAX_LEN (RTE_ETHER_MTU + IXGBE_ETH_OVERHEAD) 109 110 /* bit of VXLAN tunnel type | 7 bits of zeros | 8 bits of zeros*/ 111 #define IXGBE_FDIR_VXLAN_TUNNEL_TYPE 0x8000 112 /* bit of NVGRE tunnel type | 7 bits of zeros | 8 bits of zeros*/ 113 #define IXGBE_FDIR_NVGRE_TUNNEL_TYPE 0x0 114 115 #define IXGBE_RSS_OFFLOAD_ALL ( \ 116 ETH_RSS_IPV4 | \ 117 ETH_RSS_NONFRAG_IPV4_TCP | \ 118 ETH_RSS_NONFRAG_IPV4_UDP | \ 119 ETH_RSS_IPV6 | \ 120 ETH_RSS_NONFRAG_IPV6_TCP | \ 121 ETH_RSS_NONFRAG_IPV6_UDP | \ 122 ETH_RSS_IPV6_EX | \ 123 ETH_RSS_IPV6_TCP_EX | \ 124 ETH_RSS_IPV6_UDP_EX) 125 126 #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */ 127 #define IXGBE_VF_MAXMSIVECTOR 1 128 129 #define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 130 #define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 131 132 #define IXGBE_SECTX_MINSECIFG_MASK 0x0000000F 133 134 #define IXGBE_MACSEC_PNTHRSH 0xFFFFFE00 135 136 #define IXGBE_MAX_FDIR_FILTER_NUM (1024 * 32) 137 #define IXGBE_MAX_L2_TN_FILTER_NUM 128 138 139 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\ 140 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\ 141 return -ENOTSUP;\ 142 } while (0) 143 144 #define MAC_TYPE_FILTER_SUP(type) do {\ 145 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\ 146 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\ 147 (type) != ixgbe_mac_X550EM_a)\ 148 return -ENOTSUP;\ 149 } while (0) 150 151 /* Link speed for X550 auto negotiation */ 152 #define IXGBE_LINK_SPEED_X550_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \ 153 IXGBE_LINK_SPEED_1GB_FULL | \ 154 IXGBE_LINK_SPEED_2_5GB_FULL | \ 155 IXGBE_LINK_SPEED_5GB_FULL | \ 156 IXGBE_LINK_SPEED_10GB_FULL) 157 158 /* 159 * Information about the fdir mode. 160 */ 161 struct ixgbe_hw_fdir_mask { 162 uint16_t vlan_tci_mask; 163 uint32_t src_ipv4_mask; 164 uint32_t dst_ipv4_mask; 165 uint16_t src_ipv6_mask; 166 uint16_t dst_ipv6_mask; 167 uint16_t src_port_mask; 168 uint16_t dst_port_mask; 169 uint16_t flex_bytes_mask; 170 uint8_t mac_addr_byte_mask; 171 uint32_t tunnel_id_mask; 172 uint8_t tunnel_type_mask; 173 }; 174 175 struct ixgbe_fdir_filter { 176 TAILQ_ENTRY(ixgbe_fdir_filter) entries; 177 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/ 178 uint32_t fdirflags; /* drop or forward */ 179 uint32_t fdirhash; /* hash value for fdir */ 180 uint8_t queue; /* assigned rx queue */ 181 }; 182 183 /* list of fdir filters */ 184 TAILQ_HEAD(ixgbe_fdir_filter_list, ixgbe_fdir_filter); 185 186 struct ixgbe_fdir_rule { 187 struct ixgbe_hw_fdir_mask mask; 188 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/ 189 bool b_spec; /* If TRUE, ixgbe_fdir, fdirflags, queue have meaning. */ 190 bool b_mask; /* If TRUE, mask has meaning. */ 191 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */ 192 uint32_t fdirflags; /* drop or forward */ 193 uint32_t soft_id; /* an unique value for this rule */ 194 uint8_t queue; /* assigned rx queue */ 195 uint8_t flex_bytes_offset; 196 }; 197 198 struct ixgbe_hw_fdir_info { 199 struct ixgbe_hw_fdir_mask mask; 200 uint8_t flex_bytes_offset; 201 uint16_t collision; 202 uint16_t free; 203 uint16_t maxhash; 204 uint8_t maxlen; 205 uint64_t add; 206 uint64_t remove; 207 uint64_t f_add; 208 uint64_t f_remove; 209 struct ixgbe_fdir_filter_list fdir_list; /* filter list*/ 210 /* store the pointers of the filters, index is the hash value. */ 211 struct ixgbe_fdir_filter **hash_map; 212 struct rte_hash *hash_handle; /* cuckoo hash handler */ 213 bool mask_added; /* If already got mask from consistent filter */ 214 }; 215 216 struct ixgbe_rte_flow_rss_conf { 217 struct rte_flow_action_rss conf; /**< RSS parameters. */ 218 uint8_t key[IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t)]; /* Hash key. */ 219 uint16_t queue[IXGBE_MAX_RX_QUEUE_NUM]; /**< Queues indices to use. */ 220 }; 221 222 /* structure for interrupt relative data */ 223 struct ixgbe_interrupt { 224 uint32_t flags; 225 uint32_t mask; 226 /*to save original mask during delayed handler */ 227 uint32_t mask_original; 228 }; 229 230 struct ixgbe_stat_mapping_registers { 231 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS]; 232 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS]; 233 }; 234 235 struct ixgbe_vfta { 236 uint32_t vfta[IXGBE_VFTA_SIZE]; 237 }; 238 239 struct ixgbe_hwstrip { 240 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE]; 241 }; 242 243 /* 244 * VF data which used by PF host only 245 */ 246 #define IXGBE_MAX_VF_MC_ENTRIES 30 247 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */ 248 #define IXGBE_MAX_UTA 128 249 250 struct ixgbe_uta_info { 251 uint8_t uc_filter_type; 252 uint16_t uta_in_use; 253 uint32_t uta_shadow[IXGBE_MAX_UTA]; 254 }; 255 256 #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */ 257 258 struct ixgbe_mirror_info { 259 struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES]; 260 /**< store PF mirror rules configuration*/ 261 }; 262 263 struct ixgbe_vf_info { 264 uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN]; 265 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 266 uint16_t num_vf_mc_hashes; 267 uint16_t default_vf_vlan_id; 268 uint16_t vlans_enabled; 269 bool clear_to_send; 270 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF]; 271 uint16_t vlan_count; 272 uint8_t spoofchk_enabled; 273 uint8_t api_version; 274 uint16_t switch_domain_id; 275 uint16_t xcast_mode; 276 uint16_t mac_count; 277 }; 278 279 /* 280 * Possible l4type of 5tuple filters. 281 */ 282 enum ixgbe_5tuple_protocol { 283 IXGBE_FILTER_PROTOCOL_TCP = 0, 284 IXGBE_FILTER_PROTOCOL_UDP, 285 IXGBE_FILTER_PROTOCOL_SCTP, 286 IXGBE_FILTER_PROTOCOL_NONE, 287 }; 288 289 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter); 290 291 struct ixgbe_5tuple_filter_info { 292 uint32_t dst_ip; 293 uint32_t src_ip; 294 uint16_t dst_port; 295 uint16_t src_port; 296 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */ 297 uint8_t priority; /* seven levels (001b-111b), 111b is highest, 298 used when more than one filter matches. */ 299 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */ 300 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */ 301 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */ 302 src_port_mask:1, /* if mask is 1b, do not compare src port. */ 303 proto_mask:1; /* if mask is 1b, do not compare protocol. */ 304 }; 305 306 /* 5tuple filter structure */ 307 struct ixgbe_5tuple_filter { 308 TAILQ_ENTRY(ixgbe_5tuple_filter) entries; 309 uint16_t index; /* the index of 5tuple filter */ 310 struct ixgbe_5tuple_filter_info filter_info; 311 uint16_t queue; /* rx queue assigned to */ 312 }; 313 314 #define IXGBE_5TUPLE_ARRAY_SIZE \ 315 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \ 316 (sizeof(uint32_t) * NBBY)) 317 318 struct ixgbe_ethertype_filter { 319 uint16_t ethertype; 320 uint32_t etqf; 321 uint32_t etqs; 322 /** 323 * If this filter is added by configuration, 324 * it should not be removed. 325 */ 326 bool conf; 327 }; 328 329 /* 330 * Structure to store filters' info. 331 */ 332 struct ixgbe_filter_info { 333 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */ 334 /* store used ethertype filters*/ 335 struct ixgbe_ethertype_filter ethertype_filters[IXGBE_MAX_ETQF_FILTERS]; 336 /* Bit mask for every used 5tuple filter */ 337 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE]; 338 struct ixgbe_5tuple_filter_list fivetuple_list; 339 /* store the SYN filter info */ 340 uint32_t syn_info; 341 /* store the rss filter info */ 342 struct ixgbe_rte_flow_rss_conf rss_info; 343 }; 344 345 struct ixgbe_l2_tn_key { 346 enum rte_eth_tunnel_type l2_tn_type; 347 uint32_t tn_id; 348 }; 349 350 struct ixgbe_l2_tn_filter { 351 TAILQ_ENTRY(ixgbe_l2_tn_filter) entries; 352 struct ixgbe_l2_tn_key key; 353 uint32_t pool; 354 }; 355 356 TAILQ_HEAD(ixgbe_l2_tn_filter_list, ixgbe_l2_tn_filter); 357 358 struct ixgbe_l2_tn_info { 359 struct ixgbe_l2_tn_filter_list l2_tn_list; 360 struct ixgbe_l2_tn_filter **hash_map; 361 struct rte_hash *hash_handle; 362 bool e_tag_en; /* e-tag enabled */ 363 bool e_tag_fwd_en; /* e-tag based forwarding enabled */ 364 uint16_t e_tag_ether_type; /* ether type for e-tag */ 365 }; 366 367 struct rte_flow { 368 enum rte_filter_type filter_type; 369 void *rule; 370 }; 371 372 struct ixgbe_macsec_setting { 373 uint8_t offload_en; 374 uint8_t encrypt_en; 375 uint8_t replayprotect_en; 376 }; 377 378 /* 379 * Statistics counters collected by the MACsec 380 */ 381 struct ixgbe_macsec_stats { 382 /* TX port statistics */ 383 uint64_t out_pkts_untagged; 384 uint64_t out_pkts_encrypted; 385 uint64_t out_pkts_protected; 386 uint64_t out_octets_encrypted; 387 uint64_t out_octets_protected; 388 389 /* RX port statistics */ 390 uint64_t in_pkts_untagged; 391 uint64_t in_pkts_badtag; 392 uint64_t in_pkts_nosci; 393 uint64_t in_pkts_unknownsci; 394 uint64_t in_octets_decrypted; 395 uint64_t in_octets_validated; 396 397 /* RX SC statistics */ 398 uint64_t in_pkts_unchecked; 399 uint64_t in_pkts_delayed; 400 uint64_t in_pkts_late; 401 402 /* RX SA statistics */ 403 uint64_t in_pkts_ok; 404 uint64_t in_pkts_invalid; 405 uint64_t in_pkts_notvalid; 406 uint64_t in_pkts_unusedsa; 407 uint64_t in_pkts_notusingsa; 408 }; 409 410 /* The configuration of bandwidth */ 411 struct ixgbe_bw_conf { 412 uint8_t tc_num; /* Number of TCs. */ 413 }; 414 415 /* Struct to store Traffic Manager shaper profile. */ 416 struct ixgbe_tm_shaper_profile { 417 TAILQ_ENTRY(ixgbe_tm_shaper_profile) node; 418 uint32_t shaper_profile_id; 419 uint32_t reference_count; 420 struct rte_tm_shaper_params profile; 421 }; 422 423 TAILQ_HEAD(ixgbe_shaper_profile_list, ixgbe_tm_shaper_profile); 424 425 /* node type of Traffic Manager */ 426 enum ixgbe_tm_node_type { 427 IXGBE_TM_NODE_TYPE_PORT, 428 IXGBE_TM_NODE_TYPE_TC, 429 IXGBE_TM_NODE_TYPE_QUEUE, 430 IXGBE_TM_NODE_TYPE_MAX, 431 }; 432 433 /* Struct to store Traffic Manager node configuration. */ 434 struct ixgbe_tm_node { 435 TAILQ_ENTRY(ixgbe_tm_node) node; 436 uint32_t id; 437 uint32_t priority; 438 uint32_t weight; 439 uint32_t reference_count; 440 uint16_t no; 441 struct ixgbe_tm_node *parent; 442 struct ixgbe_tm_shaper_profile *shaper_profile; 443 struct rte_tm_node_params params; 444 }; 445 446 TAILQ_HEAD(ixgbe_tm_node_list, ixgbe_tm_node); 447 448 /* The configuration of Traffic Manager */ 449 struct ixgbe_tm_conf { 450 struct ixgbe_shaper_profile_list shaper_profile_list; 451 struct ixgbe_tm_node *root; /* root node - port */ 452 struct ixgbe_tm_node_list tc_list; /* node list for all the TCs */ 453 struct ixgbe_tm_node_list queue_list; /* node list for all the queues */ 454 /** 455 * The number of added TC nodes. 456 * It should be no more than the TC number of this port. 457 */ 458 uint32_t nb_tc_node; 459 /** 460 * The number of added queue nodes. 461 * It should be no more than the queue number of this port. 462 */ 463 uint32_t nb_queue_node; 464 /** 465 * This flag is used to check if APP can change the TM node 466 * configuration. 467 * When it's true, means the configuration is applied to HW, 468 * APP should not change the configuration. 469 * As we don't support on-the-fly configuration, when starting 470 * the port, APP should call the hierarchy_commit API to set this 471 * flag to true. When stopping the port, this flag should be set 472 * to false. 473 */ 474 bool committed; 475 }; 476 477 /* 478 * Structure to store private data for each driver instance (for each port). 479 */ 480 struct ixgbe_adapter { 481 struct ixgbe_hw hw; 482 struct ixgbe_hw_stats stats; 483 struct ixgbe_macsec_stats macsec_stats; 484 struct ixgbe_macsec_setting macsec_setting; 485 struct ixgbe_hw_fdir_info fdir; 486 struct ixgbe_interrupt intr; 487 struct ixgbe_stat_mapping_registers stat_mappings; 488 struct ixgbe_vfta shadow_vfta; 489 struct ixgbe_hwstrip hwstrip; 490 struct ixgbe_dcb_config dcb_config; 491 struct ixgbe_mirror_info mr_data; 492 struct ixgbe_vf_info *vfdata; 493 struct ixgbe_uta_info uta_info; 494 #ifdef RTE_LIBRTE_IXGBE_BYPASS 495 struct ixgbe_bypass_info bps; 496 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 497 struct ixgbe_filter_info filter; 498 struct ixgbe_l2_tn_info l2_tn; 499 struct ixgbe_bw_conf bw_conf; 500 #ifdef RTE_LIB_SECURITY 501 struct ixgbe_ipsec ipsec; 502 #endif 503 bool rx_bulk_alloc_allowed; 504 bool rx_vec_allowed; 505 struct rte_timecounter systime_tc; 506 struct rte_timecounter rx_tstamp_tc; 507 struct rte_timecounter tx_tstamp_tc; 508 struct ixgbe_tm_conf tm_conf; 509 510 /* For RSS reta table update */ 511 uint8_t rss_reta_updated; 512 513 /* Used for VF link sync with PF's physical and logical (by checking 514 * mailbox status) link status. 515 */ 516 uint8_t pflink_fullchk; 517 uint8_t mac_ctrl_frame_fwd; 518 rte_atomic32_t link_thread_running; 519 pthread_t link_thread_tid; 520 }; 521 522 struct ixgbe_vf_representor { 523 uint16_t vf_id; 524 uint16_t switch_domain_id; 525 struct rte_eth_dev *pf_ethdev; 526 }; 527 528 int ixgbe_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params); 529 int ixgbe_vf_representor_uninit(struct rte_eth_dev *ethdev); 530 531 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\ 532 (&((struct ixgbe_adapter *)adapter)->hw) 533 534 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \ 535 (&((struct ixgbe_adapter *)adapter)->stats) 536 537 #define IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(adapter) \ 538 (&((struct ixgbe_adapter *)adapter)->macsec_stats) 539 540 #define IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(adapter) \ 541 (&((struct ixgbe_adapter *)adapter)->macsec_setting) 542 543 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \ 544 (&((struct ixgbe_adapter *)adapter)->intr) 545 546 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \ 547 (&((struct ixgbe_adapter *)adapter)->fdir) 548 549 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \ 550 (&((struct ixgbe_adapter *)adapter)->stat_mappings) 551 552 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \ 553 (&((struct ixgbe_adapter *)adapter)->shadow_vfta) 554 555 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \ 556 (&((struct ixgbe_adapter *)adapter)->hwstrip) 557 558 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \ 559 (&((struct ixgbe_adapter *)adapter)->dcb_config) 560 561 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \ 562 (&((struct ixgbe_adapter *)adapter)->vfdata) 563 564 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \ 565 (&((struct ixgbe_adapter *)adapter)->mr_data) 566 567 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \ 568 (&((struct ixgbe_adapter *)adapter)->uta_info) 569 570 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \ 571 (&((struct ixgbe_adapter *)adapter)->filter) 572 573 #define IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(adapter) \ 574 (&((struct ixgbe_adapter *)adapter)->l2_tn) 575 576 #define IXGBE_DEV_PRIVATE_TO_BW_CONF(adapter) \ 577 (&((struct ixgbe_adapter *)adapter)->bw_conf) 578 579 #define IXGBE_DEV_PRIVATE_TO_TM_CONF(adapter) \ 580 (&((struct ixgbe_adapter *)adapter)->tm_conf) 581 582 #define IXGBE_DEV_PRIVATE_TO_IPSEC(adapter)\ 583 (&((struct ixgbe_adapter *)adapter)->ipsec) 584 585 /* 586 * RX/TX function prototypes 587 */ 588 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev); 589 590 void ixgbe_dev_free_queues(struct rte_eth_dev *dev); 591 592 void ixgbe_dev_rx_queue_release(void *rxq); 593 594 void ixgbe_dev_tx_queue_release(void *txq); 595 596 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, 597 uint16_t nb_rx_desc, unsigned int socket_id, 598 const struct rte_eth_rxconf *rx_conf, 599 struct rte_mempool *mb_pool); 600 601 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, 602 uint16_t nb_tx_desc, unsigned int socket_id, 603 const struct rte_eth_txconf *tx_conf); 604 605 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, 606 uint16_t rx_queue_id); 607 608 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset); 609 610 int ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset); 611 int ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset); 612 613 int ixgbe_dev_rx_init(struct rte_eth_dev *dev); 614 615 void ixgbe_dev_tx_init(struct rte_eth_dev *dev); 616 617 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev); 618 619 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); 620 621 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); 622 623 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); 624 625 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); 626 627 void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 628 struct rte_eth_rxq_info *qinfo); 629 630 void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 631 struct rte_eth_txq_info *qinfo); 632 633 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev); 634 635 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev); 636 637 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev); 638 639 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 640 uint16_t nb_pkts); 641 642 uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts, 643 uint16_t nb_pkts); 644 645 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue, 646 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 647 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, 648 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 649 650 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 651 uint16_t nb_pkts); 652 653 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts, 654 uint16_t nb_pkts); 655 656 uint16_t ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 657 uint16_t nb_pkts); 658 659 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 660 struct rte_eth_rss_conf *rss_conf); 661 662 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 663 struct rte_eth_rss_conf *rss_conf); 664 665 uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type); 666 667 uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx); 668 669 uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type); 670 671 uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i); 672 673 bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type); 674 675 int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 676 struct rte_eth_ntuple_filter *filter, 677 bool add); 678 int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 679 struct rte_eth_ethertype_filter *filter, 680 bool add); 681 int ixgbe_syn_filter_set(struct rte_eth_dev *dev, 682 struct rte_eth_syn_filter *filter, 683 bool add); 684 685 /** 686 * l2 tunnel configuration. 687 */ 688 struct ixgbe_l2_tunnel_conf { 689 enum rte_eth_tunnel_type l2_tunnel_type; 690 uint16_t ether_type; /* ether type in l2 header */ 691 uint32_t tunnel_id; /* port tag id for e-tag */ 692 uint16_t vf_id; /* VF id for tag insertion */ 693 uint32_t pool; /* destination pool for tag based forwarding */ 694 }; 695 696 int 697 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 698 struct ixgbe_l2_tunnel_conf *l2_tunnel, 699 bool restore); 700 int 701 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 702 struct ixgbe_l2_tunnel_conf *l2_tunnel); 703 void ixgbe_filterlist_init(void); 704 void ixgbe_filterlist_flush(void); 705 /* 706 * Flow director function prototypes 707 */ 708 int ixgbe_fdir_configure(struct rte_eth_dev *dev); 709 int ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev); 710 int ixgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev, 711 uint16_t offset); 712 int ixgbe_fdir_filter_program(struct rte_eth_dev *dev, 713 struct ixgbe_fdir_rule *rule, 714 bool del, bool update); 715 void ixgbe_fdir_info_get(struct rte_eth_dev *dev, 716 struct rte_eth_fdir_info *fdir_info); 717 void ixgbe_fdir_stats_get(struct rte_eth_dev *dev, 718 struct rte_eth_fdir_stats *fdir_stats); 719 720 void ixgbe_configure_dcb(struct rte_eth_dev *dev); 721 722 int 723 ixgbe_dev_link_update_share(struct rte_eth_dev *dev, 724 int wait_to_complete, int vf); 725 726 /* 727 * misc function prototypes 728 */ 729 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev); 730 731 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev); 732 733 void ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev); 734 735 int ixgbe_pf_host_init(struct rte_eth_dev *eth_dev); 736 737 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev); 738 739 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev); 740 741 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev); 742 743 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val); 744 745 void ixgbe_fdir_filter_restore(struct rte_eth_dev *dev); 746 int ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev); 747 748 extern const struct rte_flow_ops ixgbe_flow_ops; 749 750 void ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev); 751 void ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev); 752 void ixgbe_clear_syn_filter(struct rte_eth_dev *dev); 753 int ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev); 754 755 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw); 756 757 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw); 758 759 int ixgbe_vt_check(struct ixgbe_hw *hw); 760 int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 761 uint16_t tx_rate, uint64_t q_msk); 762 bool is_ixgbe_supported(struct rte_eth_dev *dev); 763 int ixgbe_tm_ops_get(struct rte_eth_dev *dev, void *ops); 764 void ixgbe_tm_conf_init(struct rte_eth_dev *dev); 765 void ixgbe_tm_conf_uninit(struct rte_eth_dev *dev); 766 int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx, 767 uint16_t tx_rate); 768 int ixgbe_rss_conf_init(struct ixgbe_rte_flow_rss_conf *out, 769 const struct rte_flow_action_rss *in); 770 int ixgbe_action_rss_same(const struct rte_flow_action_rss *comp, 771 const struct rte_flow_action_rss *with); 772 int ixgbe_config_rss_filter(struct rte_eth_dev *dev, 773 struct ixgbe_rte_flow_rss_conf *conf, bool add); 774 775 void ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev, 776 struct ixgbe_macsec_setting *macsec_setting); 777 778 void ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev); 779 780 void ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev, 781 struct ixgbe_macsec_setting *macsec_setting); 782 783 void ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev); 784 785 static inline int 786 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info, 787 uint16_t ethertype) 788 { 789 int i; 790 791 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 792 if (filter_info->ethertype_filters[i].ethertype == ethertype && 793 (filter_info->ethertype_mask & (1 << i))) 794 return i; 795 } 796 return -1; 797 } 798 799 static inline int 800 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info, 801 struct ixgbe_ethertype_filter *ethertype_filter) 802 { 803 int i; 804 805 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 806 if (!(filter_info->ethertype_mask & (1 << i))) { 807 filter_info->ethertype_mask |= 1 << i; 808 filter_info->ethertype_filters[i].ethertype = 809 ethertype_filter->ethertype; 810 filter_info->ethertype_filters[i].etqf = 811 ethertype_filter->etqf; 812 filter_info->ethertype_filters[i].etqs = 813 ethertype_filter->etqs; 814 filter_info->ethertype_filters[i].conf = 815 ethertype_filter->conf; 816 return i; 817 } 818 } 819 return -1; 820 } 821 822 static inline int 823 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info, 824 uint8_t idx) 825 { 826 if (idx >= IXGBE_MAX_ETQF_FILTERS) 827 return -1; 828 filter_info->ethertype_mask &= ~(1 << idx); 829 filter_info->ethertype_filters[idx].ethertype = 0; 830 filter_info->ethertype_filters[idx].etqf = 0; 831 filter_info->ethertype_filters[idx].etqs = 0; 832 filter_info->ethertype_filters[idx].etqs = FALSE; 833 return idx; 834 } 835 836 #endif /* _IXGBE_ETHDEV_H_ */ 837