1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <inttypes.h> 13 #include <rte_string_fns.h> 14 #include <rte_byteorder.h> 15 #include <rte_common.h> 16 #include <rte_cycles.h> 17 18 #include <rte_interrupts.h> 19 #include <rte_log.h> 20 #include <rte_debug.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_branch_prediction.h> 24 #include <rte_memory.h> 25 #include <rte_kvargs.h> 26 #include <rte_eal.h> 27 #include <rte_alarm.h> 28 #include <rte_ether.h> 29 #include <ethdev_driver.h> 30 #include <ethdev_pci.h> 31 #include <rte_malloc.h> 32 #include <rte_random.h> 33 #include <rte_dev.h> 34 #include <rte_hash_crc.h> 35 #ifdef RTE_LIB_SECURITY 36 #include <rte_security_driver.h> 37 #endif 38 39 #include "ixgbe_logs.h" 40 #include "base/ixgbe_api.h" 41 #include "base/ixgbe_vf.h" 42 #include "base/ixgbe_common.h" 43 #include "ixgbe_ethdev.h" 44 #include "ixgbe_bypass.h" 45 #include "ixgbe_rxtx.h" 46 #include "base/ixgbe_type.h" 47 #include "base/ixgbe_phy.h" 48 #include "base/ixgbe_osdep.h" 49 #include "ixgbe_regs.h" 50 51 /* 52 * High threshold controlling when to start sending XOFF frames. Must be at 53 * least 8 bytes less than receive packet buffer size. This value is in units 54 * of 1024 bytes. 55 */ 56 #define IXGBE_FC_HI 0x80 57 58 /* 59 * Low threshold controlling when to start sending XON frames. This value is 60 * in units of 1024 bytes. 61 */ 62 #define IXGBE_FC_LO 0x40 63 64 /* Timer value included in XOFF frames. */ 65 #define IXGBE_FC_PAUSE 0x680 66 67 /*Default value of Max Rx Queue*/ 68 #define IXGBE_MAX_RX_QUEUE_NUM 128 69 70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */ 71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */ 72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */ 73 74 #define IXGBE_MMW_SIZE_DEFAULT 0x4 75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14 76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */ 77 78 /* 79 * Default values for RX/TX configuration 80 */ 81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32 82 #define IXGBE_DEFAULT_RX_PTHRESH 8 83 #define IXGBE_DEFAULT_RX_HTHRESH 8 84 #define IXGBE_DEFAULT_RX_WTHRESH 0 85 86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32 87 #define IXGBE_DEFAULT_TX_PTHRESH 32 88 #define IXGBE_DEFAULT_TX_HTHRESH 0 89 #define IXGBE_DEFAULT_TX_WTHRESH 0 90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32 91 92 /* Bit shift and mask */ 93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2) 94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t) 95 #define IXGBE_8_BIT_WIDTH CHAR_BIT 96 #define IXGBE_8_BIT_MASK UINT8_MAX 97 98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */ 99 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0])) 101 102 /* Additional timesync values. */ 103 #define NSEC_PER_SEC 1000000000L 104 #define IXGBE_INCVAL_10GB 0x66666666 105 #define IXGBE_INCVAL_1GB 0x40000000 106 #define IXGBE_INCVAL_100 0x50000000 107 #define IXGBE_INCVAL_SHIFT_10GB 28 108 #define IXGBE_INCVAL_SHIFT_1GB 24 109 #define IXGBE_INCVAL_SHIFT_100 21 110 #define IXGBE_INCVAL_SHIFT_82599 7 111 #define IXGBE_INCPER_SHIFT_82599 24 112 113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL 114 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000 117 #define IXGBE_ETAG_ETYPE 0x00005084 118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff 119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000 120 #define IXGBE_RAH_ADTYPE 0x40000000 121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff 122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */ 125 #define IXGBE_QDE_STRIP_TAG 0x00000004 126 #define IXGBE_VTEICR_MASK 0x07 127 128 #define IXGBE_EXVET_VET_EXT_SHIFT 16 129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000 130 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk" 132 133 static const char * const ixgbevf_valid_arguments[] = { 134 IXGBEVF_DEVARG_PFLINK_FULLCHK, 135 NULL 136 }; 137 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev); 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev); 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev); 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev); 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev); 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev); 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev); 146 static int ixgbe_dev_start(struct rte_eth_dev *dev); 147 static int ixgbe_dev_stop(struct rte_eth_dev *dev); 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev); 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev); 150 static int ixgbe_dev_close(struct rte_eth_dev *dev); 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev); 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev, 157 int wait_to_complete); 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev, 159 struct rte_eth_stats *stats); 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev, 161 struct rte_eth_xstat *xstats, unsigned n); 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, 163 struct rte_eth_xstat *xstats, unsigned n); 164 static int 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 166 uint64_t *values, unsigned int n); 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev); 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev); 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 170 struct rte_eth_xstat_name *xstats_names, 171 unsigned int size); 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev, 173 struct rte_eth_xstat_name *xstats_names, unsigned limit); 174 static int ixgbe_dev_xstats_get_names_by_id( 175 struct rte_eth_dev *dev, 176 const uint64_t *ids, 177 struct rte_eth_xstat_name *xstats_names, 178 unsigned int limit); 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 180 uint16_t queue_id, 181 uint8_t stat_idx, 182 uint8_t is_rx); 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 184 size_t fw_size); 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev, 186 struct rte_eth_dev_info *dev_info); 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev, 189 struct rte_eth_dev_info *dev_info); 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 191 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev, 193 uint16_t vlan_id, int on); 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 195 enum rte_vlan_type vlan_type, 196 uint16_t tpid_id); 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, 198 uint16_t queue, bool on); 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, 200 int on); 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, 202 int mask); 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask); 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask); 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue); 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue); 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev); 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev); 209 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev); 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev); 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, 213 struct rte_eth_fc_conf *fc_conf); 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, 215 struct rte_eth_fc_conf *fc_conf); 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 217 struct rte_eth_pfc_conf *pfc_conf); 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 219 struct rte_eth_rss_reta_entry64 *reta_conf, 220 uint16_t reta_size); 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 222 struct rte_eth_rss_reta_entry64 *reta_conf, 223 uint16_t reta_size); 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev); 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev); 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev); 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev); 230 static void ixgbe_dev_interrupt_handler(void *param); 231 static void ixgbe_dev_interrupt_delayed_handler(void *param); 232 static void *ixgbe_dev_setup_link_thread_handler(void *param); 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, 234 uint32_t timeout_ms); 235 236 static int ixgbe_add_rar(struct rte_eth_dev *dev, 237 struct rte_ether_addr *mac_addr, 238 uint32_t index, uint32_t pool); 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index); 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, 241 struct rte_ether_addr *mac_addr); 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config); 243 static bool is_device_supported(struct rte_eth_dev *dev, 244 struct rte_pci_driver *drv); 245 246 /* For Virtual Function support */ 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev); 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev); 249 static int ixgbevf_dev_configure(struct rte_eth_dev *dev); 250 static int ixgbevf_dev_start(struct rte_eth_dev *dev); 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev, 252 int wait_to_complete); 253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev); 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev); 255 static int ixgbevf_dev_reset(struct rte_eth_dev *dev); 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev); 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev); 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev, 259 struct rte_eth_stats *stats); 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev); 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, 262 uint16_t vlan_id, int on); 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, 264 uint16_t queue, int on); 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask); 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask); 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on); 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 269 uint16_t queue_id); 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 271 uint16_t queue_id); 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 273 uint8_t queue, uint8_t msix_vector); 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev); 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev); 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev); 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev); 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev); 279 280 /* For Eth VMDQ APIs support */ 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct 282 rte_ether_addr * mac_addr, uint8_t on); 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on); 284 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 285 uint16_t queue_id); 286 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 287 uint16_t queue_id); 288 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 289 uint8_t queue, uint8_t msix_vector); 290 static void ixgbe_configure_msix(struct rte_eth_dev *dev); 291 292 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev, 293 struct rte_ether_addr *mac_addr, 294 uint32_t index, uint32_t pool); 295 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index); 296 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 297 struct rte_ether_addr *mac_addr); 298 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 299 struct ixgbe_5tuple_filter *filter); 300 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 301 struct ixgbe_5tuple_filter *filter); 302 static int ixgbe_dev_flow_ops_get(struct rte_eth_dev *dev, 303 const struct rte_flow_ops **ops); 304 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 305 306 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 307 struct rte_ether_addr *mc_addr_set, 308 uint32_t nb_mc_addr); 309 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 310 struct rte_eth_dcb_info *dcb_info); 311 312 static int ixgbe_get_reg_length(struct rte_eth_dev *dev); 313 static int ixgbe_get_regs(struct rte_eth_dev *dev, 314 struct rte_dev_reg_info *regs); 315 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev); 316 static int ixgbe_get_eeprom(struct rte_eth_dev *dev, 317 struct rte_dev_eeprom_info *eeprom); 318 static int ixgbe_set_eeprom(struct rte_eth_dev *dev, 319 struct rte_dev_eeprom_info *eeprom); 320 321 static int ixgbe_get_module_info(struct rte_eth_dev *dev, 322 struct rte_eth_dev_module_info *modinfo); 323 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 324 struct rte_dev_eeprom_info *info); 325 326 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev); 327 static int ixgbevf_get_regs(struct rte_eth_dev *dev, 328 struct rte_dev_reg_info *regs); 329 330 static int ixgbe_timesync_enable(struct rte_eth_dev *dev); 331 static int ixgbe_timesync_disable(struct rte_eth_dev *dev); 332 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 333 struct timespec *timestamp, 334 uint32_t flags); 335 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 336 struct timespec *timestamp); 337 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 338 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev, 339 struct timespec *timestamp); 340 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev, 341 const struct timespec *timestamp); 342 static void ixgbevf_dev_interrupt_handler(void *param); 343 344 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 345 struct rte_eth_udp_tunnel *udp_tunnel); 346 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 347 struct rte_eth_udp_tunnel *udp_tunnel); 348 static int ixgbe_filter_restore(struct rte_eth_dev *dev); 349 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev); 350 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw); 351 352 /* 353 * Define VF Stats MACRO for Non "cleared on read" register 354 */ 355 #define UPDATE_VF_STAT(reg, last, cur) \ 356 { \ 357 uint32_t latest = IXGBE_READ_REG(hw, reg); \ 358 cur += (latest - last) & UINT_MAX; \ 359 last = latest; \ 360 } 361 362 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \ 363 { \ 364 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \ 365 u64 new_msb = IXGBE_READ_REG(hw, msb); \ 366 u64 latest = ((new_msb << 32) | new_lsb); \ 367 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \ 368 last = latest; \ 369 } 370 371 #define IXGBE_SET_HWSTRIP(h, q) do {\ 372 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 373 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 374 (h)->bitmap[idx] |= 1 << bit;\ 375 } while (0) 376 377 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\ 378 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 379 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 380 (h)->bitmap[idx] &= ~(1 << bit);\ 381 } while (0) 382 383 #define IXGBE_GET_HWSTRIP(h, q, r) do {\ 384 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 385 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 386 (r) = (h)->bitmap[idx] >> bit & 1;\ 387 } while (0) 388 389 /* 390 * The set of PCI devices this driver supports 391 */ 392 static const struct rte_pci_id pci_id_ixgbe_map[] = { 393 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) }, 394 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) }, 395 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) }, 396 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) }, 397 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) }, 398 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) }, 399 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) }, 400 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) }, 401 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) }, 402 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) }, 403 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) }, 404 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) }, 405 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) }, 406 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) }, 407 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) }, 408 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) }, 409 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) }, 410 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) }, 411 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) }, 412 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) }, 413 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) }, 414 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) }, 415 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) }, 416 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) }, 417 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) }, 418 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) }, 419 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) }, 420 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) }, 421 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) }, 422 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) }, 423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) }, 424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) }, 425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) }, 426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) }, 427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) }, 428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) }, 429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) }, 430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) }, 431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) }, 432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) }, 433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) }, 434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) }, 435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) }, 436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) }, 437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) }, 438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) }, 439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) }, 440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) }, 441 #ifdef RTE_LIBRTE_IXGBE_BYPASS 442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) }, 443 #endif 444 { .vendor_id = 0, /* sentinel */ }, 445 }; 446 447 /* 448 * The set of PCI devices this driver supports (for 82599 VF) 449 */ 450 static const struct rte_pci_id pci_id_ixgbevf_map[] = { 451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) }, 452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) }, 453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) }, 454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) }, 455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) }, 456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) }, 457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) }, 458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) }, 459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) }, 460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) }, 461 { .vendor_id = 0, /* sentinel */ }, 462 }; 463 464 static const struct rte_eth_desc_lim rx_desc_lim = { 465 .nb_max = IXGBE_MAX_RING_DESC, 466 .nb_min = IXGBE_MIN_RING_DESC, 467 .nb_align = IXGBE_RXD_ALIGN, 468 }; 469 470 static const struct rte_eth_desc_lim tx_desc_lim = { 471 .nb_max = IXGBE_MAX_RING_DESC, 472 .nb_min = IXGBE_MIN_RING_DESC, 473 .nb_align = IXGBE_TXD_ALIGN, 474 .nb_seg_max = IXGBE_TX_MAX_SEG, 475 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG, 476 }; 477 478 static const struct eth_dev_ops ixgbe_eth_dev_ops = { 479 .dev_configure = ixgbe_dev_configure, 480 .dev_start = ixgbe_dev_start, 481 .dev_stop = ixgbe_dev_stop, 482 .dev_set_link_up = ixgbe_dev_set_link_up, 483 .dev_set_link_down = ixgbe_dev_set_link_down, 484 .dev_close = ixgbe_dev_close, 485 .dev_reset = ixgbe_dev_reset, 486 .promiscuous_enable = ixgbe_dev_promiscuous_enable, 487 .promiscuous_disable = ixgbe_dev_promiscuous_disable, 488 .allmulticast_enable = ixgbe_dev_allmulticast_enable, 489 .allmulticast_disable = ixgbe_dev_allmulticast_disable, 490 .link_update = ixgbe_dev_link_update, 491 .stats_get = ixgbe_dev_stats_get, 492 .xstats_get = ixgbe_dev_xstats_get, 493 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id, 494 .stats_reset = ixgbe_dev_stats_reset, 495 .xstats_reset = ixgbe_dev_xstats_reset, 496 .xstats_get_names = ixgbe_dev_xstats_get_names, 497 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id, 498 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set, 499 .fw_version_get = ixgbe_fw_version_get, 500 .dev_infos_get = ixgbe_dev_info_get, 501 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 502 .mtu_set = ixgbe_dev_mtu_set, 503 .vlan_filter_set = ixgbe_vlan_filter_set, 504 .vlan_tpid_set = ixgbe_vlan_tpid_set, 505 .vlan_offload_set = ixgbe_vlan_offload_set, 506 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set, 507 .rx_queue_start = ixgbe_dev_rx_queue_start, 508 .rx_queue_stop = ixgbe_dev_rx_queue_stop, 509 .tx_queue_start = ixgbe_dev_tx_queue_start, 510 .tx_queue_stop = ixgbe_dev_tx_queue_stop, 511 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 512 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable, 513 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable, 514 .rx_queue_release = ixgbe_dev_rx_queue_release, 515 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 516 .tx_queue_release = ixgbe_dev_tx_queue_release, 517 .dev_led_on = ixgbe_dev_led_on, 518 .dev_led_off = ixgbe_dev_led_off, 519 .flow_ctrl_get = ixgbe_flow_ctrl_get, 520 .flow_ctrl_set = ixgbe_flow_ctrl_set, 521 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set, 522 .mac_addr_add = ixgbe_add_rar, 523 .mac_addr_remove = ixgbe_remove_rar, 524 .mac_addr_set = ixgbe_set_default_mac_addr, 525 .uc_hash_table_set = ixgbe_uc_hash_table_set, 526 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set, 527 .set_queue_rate_limit = ixgbe_set_queue_rate_limit, 528 .reta_update = ixgbe_dev_rss_reta_update, 529 .reta_query = ixgbe_dev_rss_reta_query, 530 .rss_hash_update = ixgbe_dev_rss_hash_update, 531 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 532 .flow_ops_get = ixgbe_dev_flow_ops_get, 533 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 534 .rxq_info_get = ixgbe_rxq_info_get, 535 .txq_info_get = ixgbe_txq_info_get, 536 .timesync_enable = ixgbe_timesync_enable, 537 .timesync_disable = ixgbe_timesync_disable, 538 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp, 539 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp, 540 .get_reg = ixgbe_get_regs, 541 .get_eeprom_length = ixgbe_get_eeprom_length, 542 .get_eeprom = ixgbe_get_eeprom, 543 .set_eeprom = ixgbe_set_eeprom, 544 .get_module_info = ixgbe_get_module_info, 545 .get_module_eeprom = ixgbe_get_module_eeprom, 546 .get_dcb_info = ixgbe_dev_get_dcb_info, 547 .timesync_adjust_time = ixgbe_timesync_adjust_time, 548 .timesync_read_time = ixgbe_timesync_read_time, 549 .timesync_write_time = ixgbe_timesync_write_time, 550 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add, 551 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del, 552 .tm_ops_get = ixgbe_tm_ops_get, 553 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup, 554 .get_monitor_addr = ixgbe_get_monitor_addr, 555 }; 556 557 /* 558 * dev_ops for virtual function, bare necessities for basic vf 559 * operation have been implemented 560 */ 561 static const struct eth_dev_ops ixgbevf_eth_dev_ops = { 562 .dev_configure = ixgbevf_dev_configure, 563 .dev_start = ixgbevf_dev_start, 564 .dev_stop = ixgbevf_dev_stop, 565 .link_update = ixgbevf_dev_link_update, 566 .stats_get = ixgbevf_dev_stats_get, 567 .xstats_get = ixgbevf_dev_xstats_get, 568 .stats_reset = ixgbevf_dev_stats_reset, 569 .xstats_reset = ixgbevf_dev_stats_reset, 570 .xstats_get_names = ixgbevf_dev_xstats_get_names, 571 .dev_close = ixgbevf_dev_close, 572 .dev_reset = ixgbevf_dev_reset, 573 .promiscuous_enable = ixgbevf_dev_promiscuous_enable, 574 .promiscuous_disable = ixgbevf_dev_promiscuous_disable, 575 .allmulticast_enable = ixgbevf_dev_allmulticast_enable, 576 .allmulticast_disable = ixgbevf_dev_allmulticast_disable, 577 .dev_infos_get = ixgbevf_dev_info_get, 578 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 579 .mtu_set = ixgbevf_dev_set_mtu, 580 .vlan_filter_set = ixgbevf_vlan_filter_set, 581 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set, 582 .vlan_offload_set = ixgbevf_vlan_offload_set, 583 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 584 .rx_queue_release = ixgbe_dev_rx_queue_release, 585 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 586 .tx_queue_release = ixgbe_dev_tx_queue_release, 587 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable, 588 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable, 589 .mac_addr_add = ixgbevf_add_mac_addr, 590 .mac_addr_remove = ixgbevf_remove_mac_addr, 591 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 592 .rxq_info_get = ixgbe_rxq_info_get, 593 .txq_info_get = ixgbe_txq_info_get, 594 .mac_addr_set = ixgbevf_set_default_mac_addr, 595 .get_reg = ixgbevf_get_regs, 596 .reta_update = ixgbe_dev_rss_reta_update, 597 .reta_query = ixgbe_dev_rss_reta_query, 598 .rss_hash_update = ixgbe_dev_rss_hash_update, 599 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 600 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup, 601 .get_monitor_addr = ixgbe_get_monitor_addr, 602 }; 603 604 /* store statistics names and its offset in stats structure */ 605 struct rte_ixgbe_xstats_name_off { 606 char name[RTE_ETH_XSTATS_NAME_SIZE]; 607 unsigned offset; 608 }; 609 610 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = { 611 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)}, 612 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)}, 613 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)}, 614 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)}, 615 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)}, 616 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)}, 617 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)}, 618 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)}, 619 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)}, 620 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)}, 621 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)}, 622 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)}, 623 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)}, 624 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)}, 625 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 626 prc1023)}, 627 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 628 prc1522)}, 629 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)}, 630 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)}, 631 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)}, 632 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)}, 633 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)}, 634 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)}, 635 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)}, 636 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)}, 637 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)}, 638 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)}, 639 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)}, 640 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)}, 641 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)}, 642 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)}, 643 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)}, 644 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)}, 645 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 646 ptc1023)}, 647 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 648 ptc1522)}, 649 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)}, 650 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)}, 651 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)}, 652 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)}, 653 654 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats, 655 fdirustat_add)}, 656 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats, 657 fdirustat_remove)}, 658 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats, 659 fdirfstat_fadd)}, 660 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats, 661 fdirfstat_fremove)}, 662 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats, 663 fdirmatch)}, 664 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats, 665 fdirmiss)}, 666 667 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)}, 668 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)}, 669 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, 670 fclast)}, 671 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)}, 672 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)}, 673 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)}, 674 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)}, 675 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats, 676 fcoe_noddp)}, 677 {"rx_fcoe_no_direct_data_placement_ext_buff", 678 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)}, 679 680 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 681 lxontxc)}, 682 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 683 lxonrxc)}, 684 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 685 lxofftxc)}, 686 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 687 lxoffrxc)}, 688 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)}, 689 }; 690 691 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \ 692 sizeof(rte_ixgbe_stats_strings[0])) 693 694 /* MACsec statistics */ 695 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = { 696 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 697 out_pkts_untagged)}, 698 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats, 699 out_pkts_encrypted)}, 700 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats, 701 out_pkts_protected)}, 702 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats, 703 out_octets_encrypted)}, 704 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats, 705 out_octets_protected)}, 706 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 707 in_pkts_untagged)}, 708 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats, 709 in_pkts_badtag)}, 710 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats, 711 in_pkts_nosci)}, 712 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats, 713 in_pkts_unknownsci)}, 714 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats, 715 in_octets_decrypted)}, 716 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats, 717 in_octets_validated)}, 718 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats, 719 in_pkts_unchecked)}, 720 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats, 721 in_pkts_delayed)}, 722 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats, 723 in_pkts_late)}, 724 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats, 725 in_pkts_ok)}, 726 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats, 727 in_pkts_invalid)}, 728 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats, 729 in_pkts_notvalid)}, 730 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats, 731 in_pkts_unusedsa)}, 732 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats, 733 in_pkts_notusingsa)}, 734 }; 735 736 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \ 737 sizeof(rte_ixgbe_macsec_strings[0])) 738 739 /* Per-queue statistics */ 740 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = { 741 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)}, 742 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)}, 743 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)}, 744 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)}, 745 }; 746 747 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \ 748 sizeof(rte_ixgbe_rxq_strings[0])) 749 #define IXGBE_NB_RXQ_PRIO_VALUES 8 750 751 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = { 752 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)}, 753 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)}, 754 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats, 755 pxon2offc)}, 756 }; 757 758 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \ 759 sizeof(rte_ixgbe_txq_strings[0])) 760 #define IXGBE_NB_TXQ_PRIO_VALUES 8 761 762 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = { 763 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)}, 764 }; 765 766 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \ 767 sizeof(rte_ixgbevf_stats_strings[0])) 768 769 /* 770 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h. 771 */ 772 static inline int 773 ixgbe_is_sfp(struct ixgbe_hw *hw) 774 { 775 switch (hw->phy.type) { 776 case ixgbe_phy_sfp_avago: 777 case ixgbe_phy_sfp_ftl: 778 case ixgbe_phy_sfp_intel: 779 case ixgbe_phy_sfp_unknown: 780 case ixgbe_phy_sfp_passive_tyco: 781 case ixgbe_phy_sfp_passive_unknown: 782 return 1; 783 default: 784 return 0; 785 } 786 } 787 788 static inline int32_t 789 ixgbe_pf_reset_hw(struct ixgbe_hw *hw) 790 { 791 uint32_t ctrl_ext; 792 int32_t status; 793 794 status = ixgbe_reset_hw(hw); 795 796 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 797 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 798 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 799 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 800 IXGBE_WRITE_FLUSH(hw); 801 802 if (status == IXGBE_ERR_SFP_NOT_PRESENT) 803 status = IXGBE_SUCCESS; 804 return status; 805 } 806 807 static inline void 808 ixgbe_enable_intr(struct rte_eth_dev *dev) 809 { 810 struct ixgbe_interrupt *intr = 811 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 812 struct ixgbe_hw *hw = 813 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 814 815 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask); 816 IXGBE_WRITE_FLUSH(hw); 817 } 818 819 /* 820 * This function is based on ixgbe_disable_intr() in base/ixgbe.h. 821 */ 822 static void 823 ixgbe_disable_intr(struct ixgbe_hw *hw) 824 { 825 PMD_INIT_FUNC_TRACE(); 826 827 if (hw->mac.type == ixgbe_mac_82598EB) { 828 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0); 829 } else { 830 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000); 831 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0); 832 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0); 833 } 834 IXGBE_WRITE_FLUSH(hw); 835 } 836 837 /* 838 * This function resets queue statistics mapping registers. 839 * From Niantic datasheet, Initialization of Statistics section: 840 * "...if software requires the queue counters, the RQSMR and TQSM registers 841 * must be re-programmed following a device reset. 842 */ 843 static void 844 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw) 845 { 846 uint32_t i; 847 848 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) { 849 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0); 850 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0); 851 } 852 } 853 854 855 static int 856 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 857 uint16_t queue_id, 858 uint8_t stat_idx, 859 uint8_t is_rx) 860 { 861 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8 862 #define NB_QMAP_FIELDS_PER_QSM_REG 4 863 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f 864 865 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 866 struct ixgbe_stat_mapping_registers *stat_mappings = 867 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private); 868 uint32_t qsmr_mask = 0; 869 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK; 870 uint32_t q_map; 871 uint8_t n, offset; 872 873 if ((hw->mac.type != ixgbe_mac_82599EB) && 874 (hw->mac.type != ixgbe_mac_X540) && 875 (hw->mac.type != ixgbe_mac_X550) && 876 (hw->mac.type != ixgbe_mac_X550EM_x) && 877 (hw->mac.type != ixgbe_mac_X550EM_a)) 878 return -ENOSYS; 879 880 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d", 881 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 882 queue_id, stat_idx); 883 884 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG); 885 if (n >= IXGBE_NB_STAT_MAPPING_REGS) { 886 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded"); 887 return -EIO; 888 } 889 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG); 890 891 /* Now clear any previous stat_idx set */ 892 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 893 if (!is_rx) 894 stat_mappings->tqsm[n] &= ~clearing_mask; 895 else 896 stat_mappings->rqsmr[n] &= ~clearing_mask; 897 898 q_map = (uint32_t)stat_idx; 899 q_map &= QMAP_FIELD_RESERVED_BITS_MASK; 900 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 901 if (!is_rx) 902 stat_mappings->tqsm[n] |= qsmr_mask; 903 else 904 stat_mappings->rqsmr[n] |= qsmr_mask; 905 906 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d", 907 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 908 queue_id, stat_idx); 909 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n, 910 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]); 911 912 /* Now write the mapping in the appropriate register */ 913 if (is_rx) { 914 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d", 915 stat_mappings->rqsmr[n], n); 916 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]); 917 } else { 918 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d", 919 stat_mappings->tqsm[n], n); 920 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]); 921 } 922 return 0; 923 } 924 925 static void 926 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev) 927 { 928 struct ixgbe_stat_mapping_registers *stat_mappings = 929 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private); 930 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 931 int i; 932 933 /* write whatever was in stat mapping table to the NIC */ 934 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) { 935 /* rx */ 936 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]); 937 938 /* tx */ 939 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]); 940 } 941 } 942 943 static void 944 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config) 945 { 946 uint8_t i; 947 struct ixgbe_dcb_tc_config *tc; 948 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS; 949 950 dcb_config->num_tcs.pg_tcs = dcb_max_tc; 951 dcb_config->num_tcs.pfc_tcs = dcb_max_tc; 952 for (i = 0; i < dcb_max_tc; i++) { 953 tc = &dcb_config->tc_config[i]; 954 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i; 955 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 956 (uint8_t)(100/dcb_max_tc + (i & 1)); 957 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i; 958 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 959 (uint8_t)(100/dcb_max_tc + (i & 1)); 960 tc->pfc = ixgbe_dcb_pfc_disabled; 961 } 962 963 /* Initialize default user to priority mapping, UPx->TC0 */ 964 tc = &dcb_config->tc_config[0]; 965 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 966 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 967 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) { 968 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100; 969 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100; 970 } 971 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal; 972 dcb_config->pfc_mode_enable = false; 973 dcb_config->vt_mode = true; 974 dcb_config->round_robin_enable = false; 975 /* support all DCB capabilities in 82599 */ 976 dcb_config->support.capabilities = 0xFF; 977 978 /*we only support 4 Tcs for X540, X550 */ 979 if (hw->mac.type == ixgbe_mac_X540 || 980 hw->mac.type == ixgbe_mac_X550 || 981 hw->mac.type == ixgbe_mac_X550EM_x || 982 hw->mac.type == ixgbe_mac_X550EM_a) { 983 dcb_config->num_tcs.pg_tcs = 4; 984 dcb_config->num_tcs.pfc_tcs = 4; 985 } 986 } 987 988 /* 989 * Ensure that all locks are released before first NVM or PHY access 990 */ 991 static void 992 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw) 993 { 994 uint16_t mask; 995 996 /* 997 * Phy lock should not fail in this early stage. If this is the case, 998 * it is due to an improper exit of the application. 999 * So force the release of the faulty lock. Release of common lock 1000 * is done automatically by swfw_sync function. 1001 */ 1002 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func; 1003 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1004 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func); 1005 } 1006 ixgbe_release_swfw_semaphore(hw, mask); 1007 1008 /* 1009 * These ones are more tricky since they are common to all ports; but 1010 * swfw_sync retries last long enough (1s) to be almost sure that if 1011 * lock can not be taken it is due to an improper lock of the 1012 * semaphore. 1013 */ 1014 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM; 1015 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1016 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 1017 } 1018 ixgbe_release_swfw_semaphore(hw, mask); 1019 } 1020 1021 /* 1022 * This function is based on code in ixgbe_attach() in base/ixgbe.c. 1023 * It returns 0 on success. 1024 */ 1025 static int 1026 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) 1027 { 1028 struct ixgbe_adapter *ad = eth_dev->data->dev_private; 1029 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1030 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 1031 struct ixgbe_hw *hw = 1032 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1033 struct ixgbe_vfta *shadow_vfta = 1034 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1035 struct ixgbe_hwstrip *hwstrip = 1036 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1037 struct ixgbe_dcb_config *dcb_config = 1038 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private); 1039 struct ixgbe_filter_info *filter_info = 1040 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1041 struct ixgbe_bw_conf *bw_conf = 1042 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private); 1043 uint32_t ctrl_ext; 1044 uint16_t csum; 1045 int diag, i, ret; 1046 1047 PMD_INIT_FUNC_TRACE(); 1048 1049 ixgbe_dev_macsec_setting_reset(eth_dev); 1050 1051 eth_dev->dev_ops = &ixgbe_eth_dev_ops; 1052 eth_dev->rx_queue_count = ixgbe_dev_rx_queue_count; 1053 eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status; 1054 eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status; 1055 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1056 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1057 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts; 1058 1059 /* 1060 * For secondary processes, we don't initialise any further as primary 1061 * has already done this work. Only check we don't need a different 1062 * RX and TX function. 1063 */ 1064 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1065 struct ixgbe_tx_queue *txq; 1066 /* TX queue function in primary, set by last queue initialized 1067 * Tx queue may not initialized by primary process 1068 */ 1069 if (eth_dev->data->tx_queues) { 1070 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1]; 1071 ixgbe_set_tx_function(eth_dev, txq); 1072 } else { 1073 /* Use default TX function if we get here */ 1074 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. " 1075 "Using default TX function."); 1076 } 1077 1078 ixgbe_set_rx_function(eth_dev); 1079 1080 return 0; 1081 } 1082 1083 rte_atomic32_clear(&ad->link_thread_running); 1084 rte_eth_copy_pci_info(eth_dev, pci_dev); 1085 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1086 1087 /* Vendor and Device ID need to be set before init of shared code */ 1088 hw->device_id = pci_dev->id.device_id; 1089 hw->vendor_id = pci_dev->id.vendor_id; 1090 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1091 hw->allow_unsupported_sfp = 1; 1092 1093 /* Initialize the shared code (base driver) */ 1094 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1095 diag = ixgbe_bypass_init_shared_code(hw); 1096 #else 1097 diag = ixgbe_init_shared_code(hw); 1098 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1099 1100 if (diag != IXGBE_SUCCESS) { 1101 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag); 1102 return -EIO; 1103 } 1104 1105 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 1106 PMD_INIT_LOG(ERR, "\nERROR: " 1107 "Firmware recovery mode detected. Limiting functionality.\n" 1108 "Refer to the Intel(R) Ethernet Adapters and Devices " 1109 "User Guide for details on firmware recovery mode."); 1110 return -EIO; 1111 } 1112 1113 /* pick up the PCI bus settings for reporting later */ 1114 ixgbe_get_bus_info(hw); 1115 1116 /* Unlock any pending hardware semaphore */ 1117 ixgbe_swfw_lock_reset(hw); 1118 1119 #ifdef RTE_LIB_SECURITY 1120 /* Initialize security_ctx only for primary process*/ 1121 if (ixgbe_ipsec_ctx_create(eth_dev)) 1122 return -ENOMEM; 1123 #endif 1124 1125 /* Initialize DCB configuration*/ 1126 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config)); 1127 ixgbe_dcb_init(hw, dcb_config); 1128 /* Get Hardware Flow Control setting */ 1129 hw->fc.requested_mode = ixgbe_fc_none; 1130 hw->fc.current_mode = ixgbe_fc_none; 1131 hw->fc.pause_time = IXGBE_FC_PAUSE; 1132 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 1133 hw->fc.low_water[i] = IXGBE_FC_LO; 1134 hw->fc.high_water[i] = IXGBE_FC_HI; 1135 } 1136 hw->fc.send_xon = 1; 1137 1138 /* Make sure we have a good EEPROM before we read from it */ 1139 diag = ixgbe_validate_eeprom_checksum(hw, &csum); 1140 if (diag != IXGBE_SUCCESS) { 1141 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag); 1142 return -EIO; 1143 } 1144 1145 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1146 diag = ixgbe_bypass_init_hw(hw); 1147 #else 1148 diag = ixgbe_init_hw(hw); 1149 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1150 1151 /* 1152 * Devices with copper phys will fail to initialise if ixgbe_init_hw() 1153 * is called too soon after the kernel driver unbinding/binding occurs. 1154 * The failure occurs in ixgbe_identify_phy_generic() for all devices, 1155 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is 1156 * also called. See ixgbe_identify_phy_82599(). The reason for the 1157 * failure is not known, and only occuts when virtualisation features 1158 * are disabled in the bios. A delay of 100ms was found to be enough by 1159 * trial-and-error, and is doubled to be safe. 1160 */ 1161 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) { 1162 rte_delay_ms(200); 1163 diag = ixgbe_init_hw(hw); 1164 } 1165 1166 if (diag == IXGBE_ERR_SFP_NOT_PRESENT) 1167 diag = IXGBE_SUCCESS; 1168 1169 if (diag == IXGBE_ERR_EEPROM_VERSION) { 1170 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/" 1171 "LOM. Please be aware there may be issues associated " 1172 "with your hardware."); 1173 PMD_INIT_LOG(ERR, "If you are experiencing problems " 1174 "please contact your Intel or hardware representative " 1175 "who provided you with this hardware."); 1176 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED) 1177 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module"); 1178 if (diag) { 1179 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag); 1180 return -EIO; 1181 } 1182 1183 /* Reset the hw statistics */ 1184 ixgbe_dev_stats_reset(eth_dev); 1185 1186 /* disable interrupt */ 1187 ixgbe_disable_intr(hw); 1188 1189 /* reset mappings for queue statistics hw counters*/ 1190 ixgbe_reset_qstat_mappings(hw); 1191 1192 /* Allocate memory for storing MAC addresses */ 1193 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN * 1194 hw->mac.num_rar_entries, 0); 1195 if (eth_dev->data->mac_addrs == NULL) { 1196 PMD_INIT_LOG(ERR, 1197 "Failed to allocate %u bytes needed to store " 1198 "MAC addresses", 1199 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1200 return -ENOMEM; 1201 } 1202 /* Copy the permanent MAC address */ 1203 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr, 1204 ð_dev->data->mac_addrs[0]); 1205 1206 /* Allocate memory for storing hash filter MAC addresses */ 1207 eth_dev->data->hash_mac_addrs = rte_zmalloc( 1208 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0); 1209 if (eth_dev->data->hash_mac_addrs == NULL) { 1210 PMD_INIT_LOG(ERR, 1211 "Failed to allocate %d bytes needed to store MAC addresses", 1212 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC); 1213 rte_free(eth_dev->data->mac_addrs); 1214 eth_dev->data->mac_addrs = NULL; 1215 return -ENOMEM; 1216 } 1217 1218 /* initialize the vfta */ 1219 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1220 1221 /* initialize the hw strip bitmap*/ 1222 memset(hwstrip, 0, sizeof(*hwstrip)); 1223 1224 /* initialize PF if max_vfs not zero */ 1225 ret = ixgbe_pf_host_init(eth_dev); 1226 if (ret) 1227 goto err_pf_host_init; 1228 1229 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 1230 /* let hardware know driver is loaded */ 1231 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD; 1232 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 1233 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 1234 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 1235 IXGBE_WRITE_FLUSH(hw); 1236 1237 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 1238 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d", 1239 (int) hw->mac.type, (int) hw->phy.type, 1240 (int) hw->phy.sfp_type); 1241 else 1242 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d", 1243 (int) hw->mac.type, (int) hw->phy.type); 1244 1245 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 1246 eth_dev->data->port_id, pci_dev->id.vendor_id, 1247 pci_dev->id.device_id); 1248 1249 rte_intr_callback_register(intr_handle, 1250 ixgbe_dev_interrupt_handler, eth_dev); 1251 1252 /* enable uio/vfio intr/eventfd mapping */ 1253 rte_intr_enable(intr_handle); 1254 1255 /* enable support intr */ 1256 ixgbe_enable_intr(eth_dev); 1257 1258 /* initialize filter info */ 1259 memset(filter_info, 0, 1260 sizeof(struct ixgbe_filter_info)); 1261 1262 /* initialize 5tuple filter list */ 1263 TAILQ_INIT(&filter_info->fivetuple_list); 1264 1265 /* initialize flow director filter list & hash */ 1266 ret = ixgbe_fdir_filter_init(eth_dev); 1267 if (ret) 1268 goto err_fdir_filter_init; 1269 1270 /* initialize l2 tunnel filter list & hash */ 1271 ret = ixgbe_l2_tn_filter_init(eth_dev); 1272 if (ret) 1273 goto err_l2_tn_filter_init; 1274 1275 /* initialize flow filter lists */ 1276 ixgbe_filterlist_init(); 1277 1278 /* initialize bandwidth configuration info */ 1279 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf)); 1280 1281 /* initialize Traffic Manager configuration */ 1282 ixgbe_tm_conf_init(eth_dev); 1283 1284 return 0; 1285 1286 err_l2_tn_filter_init: 1287 ixgbe_fdir_filter_uninit(eth_dev); 1288 err_fdir_filter_init: 1289 ixgbe_disable_intr(hw); 1290 rte_intr_disable(intr_handle); 1291 rte_intr_callback_unregister(intr_handle, 1292 ixgbe_dev_interrupt_handler, eth_dev); 1293 ixgbe_pf_host_uninit(eth_dev); 1294 err_pf_host_init: 1295 rte_free(eth_dev->data->mac_addrs); 1296 eth_dev->data->mac_addrs = NULL; 1297 rte_free(eth_dev->data->hash_mac_addrs); 1298 eth_dev->data->hash_mac_addrs = NULL; 1299 return ret; 1300 } 1301 1302 static int 1303 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1304 { 1305 PMD_INIT_FUNC_TRACE(); 1306 1307 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1308 return 0; 1309 1310 ixgbe_dev_close(eth_dev); 1311 1312 return 0; 1313 } 1314 1315 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev) 1316 { 1317 struct ixgbe_filter_info *filter_info = 1318 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1319 struct ixgbe_5tuple_filter *p_5tuple; 1320 1321 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) { 1322 TAILQ_REMOVE(&filter_info->fivetuple_list, 1323 p_5tuple, 1324 entries); 1325 rte_free(p_5tuple); 1326 } 1327 memset(filter_info->fivetuple_mask, 0, 1328 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE); 1329 1330 return 0; 1331 } 1332 1333 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev) 1334 { 1335 struct ixgbe_hw_fdir_info *fdir_info = 1336 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1337 struct ixgbe_fdir_filter *fdir_filter; 1338 1339 if (fdir_info->hash_map) 1340 rte_free(fdir_info->hash_map); 1341 if (fdir_info->hash_handle) 1342 rte_hash_free(fdir_info->hash_handle); 1343 1344 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 1345 TAILQ_REMOVE(&fdir_info->fdir_list, 1346 fdir_filter, 1347 entries); 1348 rte_free(fdir_filter); 1349 } 1350 1351 return 0; 1352 } 1353 1354 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev) 1355 { 1356 struct ixgbe_l2_tn_info *l2_tn_info = 1357 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1358 struct ixgbe_l2_tn_filter *l2_tn_filter; 1359 1360 if (l2_tn_info->hash_map) 1361 rte_free(l2_tn_info->hash_map); 1362 if (l2_tn_info->hash_handle) 1363 rte_hash_free(l2_tn_info->hash_handle); 1364 1365 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 1366 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, 1367 l2_tn_filter, 1368 entries); 1369 rte_free(l2_tn_filter); 1370 } 1371 1372 return 0; 1373 } 1374 1375 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev) 1376 { 1377 struct ixgbe_hw_fdir_info *fdir_info = 1378 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1379 char fdir_hash_name[RTE_HASH_NAMESIZE]; 1380 struct rte_hash_parameters fdir_hash_params = { 1381 .name = fdir_hash_name, 1382 .entries = IXGBE_MAX_FDIR_FILTER_NUM, 1383 .key_len = sizeof(union ixgbe_atr_input), 1384 .hash_func = rte_hash_crc, 1385 .hash_func_init_val = 0, 1386 .socket_id = rte_socket_id(), 1387 }; 1388 1389 TAILQ_INIT(&fdir_info->fdir_list); 1390 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 1391 "fdir_%s", eth_dev->device->name); 1392 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params); 1393 if (!fdir_info->hash_handle) { 1394 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 1395 return -EINVAL; 1396 } 1397 fdir_info->hash_map = rte_zmalloc("ixgbe", 1398 sizeof(struct ixgbe_fdir_filter *) * 1399 IXGBE_MAX_FDIR_FILTER_NUM, 1400 0); 1401 if (!fdir_info->hash_map) { 1402 PMD_INIT_LOG(ERR, 1403 "Failed to allocate memory for fdir hash map!"); 1404 rte_hash_free(fdir_info->hash_handle); 1405 return -ENOMEM; 1406 } 1407 fdir_info->mask_added = FALSE; 1408 1409 return 0; 1410 } 1411 1412 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) 1413 { 1414 struct ixgbe_l2_tn_info *l2_tn_info = 1415 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1416 char l2_tn_hash_name[RTE_HASH_NAMESIZE]; 1417 struct rte_hash_parameters l2_tn_hash_params = { 1418 .name = l2_tn_hash_name, 1419 .entries = IXGBE_MAX_L2_TN_FILTER_NUM, 1420 .key_len = sizeof(struct ixgbe_l2_tn_key), 1421 .hash_func = rte_hash_crc, 1422 .hash_func_init_val = 0, 1423 .socket_id = rte_socket_id(), 1424 }; 1425 1426 TAILQ_INIT(&l2_tn_info->l2_tn_list); 1427 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE, 1428 "l2_tn_%s", eth_dev->device->name); 1429 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params); 1430 if (!l2_tn_info->hash_handle) { 1431 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!"); 1432 return -EINVAL; 1433 } 1434 l2_tn_info->hash_map = rte_zmalloc("ixgbe", 1435 sizeof(struct ixgbe_l2_tn_filter *) * 1436 IXGBE_MAX_L2_TN_FILTER_NUM, 1437 0); 1438 if (!l2_tn_info->hash_map) { 1439 PMD_INIT_LOG(ERR, 1440 "Failed to allocate memory for L2 TN hash map!"); 1441 rte_hash_free(l2_tn_info->hash_handle); 1442 return -ENOMEM; 1443 } 1444 l2_tn_info->e_tag_en = FALSE; 1445 l2_tn_info->e_tag_fwd_en = FALSE; 1446 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG; 1447 1448 return 0; 1449 } 1450 /* 1451 * Negotiate mailbox API version with the PF. 1452 * After reset API version is always set to the basic one (ixgbe_mbox_api_10). 1453 * Then we try to negotiate starting with the most recent one. 1454 * If all negotiation attempts fail, then we will proceed with 1455 * the default one (ixgbe_mbox_api_10). 1456 */ 1457 static void 1458 ixgbevf_negotiate_api(struct ixgbe_hw *hw) 1459 { 1460 int32_t i; 1461 1462 /* start with highest supported, proceed down */ 1463 static const enum ixgbe_pfvf_api_rev sup_ver[] = { 1464 ixgbe_mbox_api_13, 1465 ixgbe_mbox_api_12, 1466 ixgbe_mbox_api_11, 1467 ixgbe_mbox_api_10, 1468 }; 1469 1470 for (i = 0; 1471 i != RTE_DIM(sup_ver) && 1472 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0; 1473 i++) 1474 ; 1475 } 1476 1477 static void 1478 generate_random_mac_addr(struct rte_ether_addr *mac_addr) 1479 { 1480 uint64_t random; 1481 1482 /* Set Organizationally Unique Identifier (OUI) prefix. */ 1483 mac_addr->addr_bytes[0] = 0x00; 1484 mac_addr->addr_bytes[1] = 0x09; 1485 mac_addr->addr_bytes[2] = 0xC0; 1486 /* Force indication of locally assigned MAC address. */ 1487 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR; 1488 /* Generate the last 3 bytes of the MAC address with a random number. */ 1489 random = rte_rand(); 1490 memcpy(&mac_addr->addr_bytes[3], &random, 3); 1491 } 1492 1493 static int 1494 devarg_handle_int(__rte_unused const char *key, const char *value, 1495 void *extra_args) 1496 { 1497 uint16_t *n = extra_args; 1498 1499 if (value == NULL || extra_args == NULL) 1500 return -EINVAL; 1501 1502 *n = (uint16_t)strtoul(value, NULL, 0); 1503 if (*n == USHRT_MAX && errno == ERANGE) 1504 return -1; 1505 1506 return 0; 1507 } 1508 1509 static void 1510 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter, 1511 struct rte_devargs *devargs) 1512 { 1513 struct rte_kvargs *kvlist; 1514 uint16_t pflink_fullchk; 1515 1516 if (devargs == NULL) 1517 return; 1518 1519 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments); 1520 if (kvlist == NULL) 1521 return; 1522 1523 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 && 1524 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK, 1525 devarg_handle_int, &pflink_fullchk) == 0 && 1526 pflink_fullchk == 1) 1527 adapter->pflink_fullchk = 1; 1528 1529 rte_kvargs_free(kvlist); 1530 } 1531 1532 /* 1533 * Virtual Function device init 1534 */ 1535 static int 1536 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev) 1537 { 1538 int diag; 1539 uint32_t tc, tcs; 1540 struct ixgbe_adapter *ad = eth_dev->data->dev_private; 1541 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1542 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 1543 struct ixgbe_hw *hw = 1544 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1545 struct ixgbe_vfta *shadow_vfta = 1546 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1547 struct ixgbe_hwstrip *hwstrip = 1548 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1549 struct rte_ether_addr *perm_addr = 1550 (struct rte_ether_addr *)hw->mac.perm_addr; 1551 1552 PMD_INIT_FUNC_TRACE(); 1553 1554 eth_dev->dev_ops = &ixgbevf_eth_dev_ops; 1555 eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status; 1556 eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status; 1557 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1558 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1559 1560 /* for secondary processes, we don't initialise any further as primary 1561 * has already done this work. Only check we don't need a different 1562 * RX function 1563 */ 1564 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1565 struct ixgbe_tx_queue *txq; 1566 /* TX queue function in primary, set by last queue initialized 1567 * Tx queue may not initialized by primary process 1568 */ 1569 if (eth_dev->data->tx_queues) { 1570 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1]; 1571 ixgbe_set_tx_function(eth_dev, txq); 1572 } else { 1573 /* Use default TX function if we get here */ 1574 PMD_INIT_LOG(NOTICE, 1575 "No TX queues configured yet. Using default TX function."); 1576 } 1577 1578 ixgbe_set_rx_function(eth_dev); 1579 1580 return 0; 1581 } 1582 1583 rte_atomic32_clear(&ad->link_thread_running); 1584 ixgbevf_parse_devargs(eth_dev->data->dev_private, 1585 pci_dev->device.devargs); 1586 1587 rte_eth_copy_pci_info(eth_dev, pci_dev); 1588 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1589 1590 hw->device_id = pci_dev->id.device_id; 1591 hw->vendor_id = pci_dev->id.vendor_id; 1592 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1593 1594 /* initialize the vfta */ 1595 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1596 1597 /* initialize the hw strip bitmap*/ 1598 memset(hwstrip, 0, sizeof(*hwstrip)); 1599 1600 /* Initialize the shared code (base driver) */ 1601 diag = ixgbe_init_shared_code(hw); 1602 if (diag != IXGBE_SUCCESS) { 1603 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag); 1604 return -EIO; 1605 } 1606 1607 /* init_mailbox_params */ 1608 hw->mbx.ops.init_params(hw); 1609 1610 /* Reset the hw statistics */ 1611 ixgbevf_dev_stats_reset(eth_dev); 1612 1613 /* Disable the interrupts for VF */ 1614 ixgbevf_intr_disable(eth_dev); 1615 1616 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */ 1617 diag = hw->mac.ops.reset_hw(hw); 1618 1619 /* 1620 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when 1621 * the underlying PF driver has not assigned a MAC address to the VF. 1622 * In this case, assign a random MAC address. 1623 */ 1624 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) { 1625 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1626 /* 1627 * This error code will be propagated to the app by 1628 * rte_eth_dev_reset, so use a public error code rather than 1629 * the internal-only IXGBE_ERR_RESET_FAILED 1630 */ 1631 return -EAGAIN; 1632 } 1633 1634 /* negotiate mailbox API version to use with the PF. */ 1635 ixgbevf_negotiate_api(hw); 1636 1637 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */ 1638 ixgbevf_get_queues(hw, &tcs, &tc); 1639 1640 /* Allocate memory for storing MAC addresses */ 1641 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN * 1642 hw->mac.num_rar_entries, 0); 1643 if (eth_dev->data->mac_addrs == NULL) { 1644 PMD_INIT_LOG(ERR, 1645 "Failed to allocate %u bytes needed to store " 1646 "MAC addresses", 1647 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1648 return -ENOMEM; 1649 } 1650 1651 /* Generate a random MAC address, if none was assigned by PF. */ 1652 if (rte_is_zero_ether_addr(perm_addr)) { 1653 generate_random_mac_addr(perm_addr); 1654 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1); 1655 if (diag) { 1656 rte_free(eth_dev->data->mac_addrs); 1657 eth_dev->data->mac_addrs = NULL; 1658 return diag; 1659 } 1660 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF"); 1661 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address " 1662 RTE_ETHER_ADDR_PRT_FMT, 1663 RTE_ETHER_ADDR_BYTES(perm_addr)); 1664 } 1665 1666 /* Copy the permanent MAC address */ 1667 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]); 1668 1669 /* reset the hardware with the new settings */ 1670 diag = hw->mac.ops.start_hw(hw); 1671 switch (diag) { 1672 case 0: 1673 break; 1674 1675 default: 1676 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1677 rte_free(eth_dev->data->mac_addrs); 1678 eth_dev->data->mac_addrs = NULL; 1679 return -EIO; 1680 } 1681 1682 rte_intr_callback_register(intr_handle, 1683 ixgbevf_dev_interrupt_handler, eth_dev); 1684 rte_intr_enable(intr_handle); 1685 ixgbevf_intr_enable(eth_dev); 1686 1687 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s", 1688 eth_dev->data->port_id, pci_dev->id.vendor_id, 1689 pci_dev->id.device_id, "ixgbe_mac_82599_vf"); 1690 1691 return 0; 1692 } 1693 1694 /* Virtual Function device uninit */ 1695 1696 static int 1697 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev) 1698 { 1699 PMD_INIT_FUNC_TRACE(); 1700 1701 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1702 return 0; 1703 1704 ixgbevf_dev_close(eth_dev); 1705 1706 return 0; 1707 } 1708 1709 static int 1710 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1711 struct rte_pci_device *pci_dev) 1712 { 1713 char name[RTE_ETH_NAME_MAX_LEN]; 1714 struct rte_eth_dev *pf_ethdev; 1715 struct rte_eth_devargs eth_da; 1716 int i, retval; 1717 1718 if (pci_dev->device.devargs) { 1719 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 1720 ð_da); 1721 if (retval) 1722 return retval; 1723 } else 1724 memset(ð_da, 0, sizeof(eth_da)); 1725 1726 if (eth_da.nb_representor_ports > 0 && 1727 eth_da.type != RTE_ETH_REPRESENTOR_VF) { 1728 PMD_DRV_LOG(ERR, "unsupported representor type: %s\n", 1729 pci_dev->device.devargs->args); 1730 return -ENOTSUP; 1731 } 1732 1733 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 1734 sizeof(struct ixgbe_adapter), 1735 eth_dev_pci_specific_init, pci_dev, 1736 eth_ixgbe_dev_init, NULL); 1737 1738 if (retval || eth_da.nb_representor_ports < 1) 1739 return retval; 1740 1741 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1742 if (pf_ethdev == NULL) 1743 return -ENODEV; 1744 1745 /* probe VF representor ports */ 1746 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1747 struct ixgbe_vf_info *vfinfo; 1748 struct ixgbe_vf_representor representor; 1749 1750 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA( 1751 pf_ethdev->data->dev_private); 1752 if (vfinfo == NULL) { 1753 PMD_DRV_LOG(ERR, 1754 "no virtual functions supported by PF"); 1755 break; 1756 } 1757 1758 representor.vf_id = eth_da.representor_ports[i]; 1759 representor.switch_domain_id = vfinfo->switch_domain_id; 1760 representor.pf_ethdev = pf_ethdev; 1761 1762 /* representor port net_bdf_port */ 1763 snprintf(name, sizeof(name), "net_%s_representor_%d", 1764 pci_dev->device.name, 1765 eth_da.representor_ports[i]); 1766 1767 retval = rte_eth_dev_create(&pci_dev->device, name, 1768 sizeof(struct ixgbe_vf_representor), NULL, NULL, 1769 ixgbe_vf_representor_init, &representor); 1770 1771 if (retval) 1772 PMD_DRV_LOG(ERR, "failed to create ixgbe vf " 1773 "representor %s.", name); 1774 } 1775 1776 return 0; 1777 } 1778 1779 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev) 1780 { 1781 struct rte_eth_dev *ethdev; 1782 1783 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1784 if (!ethdev) 1785 return 0; 1786 1787 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 1788 return rte_eth_dev_pci_generic_remove(pci_dev, 1789 ixgbe_vf_representor_uninit); 1790 else 1791 return rte_eth_dev_pci_generic_remove(pci_dev, 1792 eth_ixgbe_dev_uninit); 1793 } 1794 1795 static struct rte_pci_driver rte_ixgbe_pmd = { 1796 .id_table = pci_id_ixgbe_map, 1797 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1798 .probe = eth_ixgbe_pci_probe, 1799 .remove = eth_ixgbe_pci_remove, 1800 }; 1801 1802 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1803 struct rte_pci_device *pci_dev) 1804 { 1805 return rte_eth_dev_pci_generic_probe(pci_dev, 1806 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init); 1807 } 1808 1809 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev) 1810 { 1811 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit); 1812 } 1813 1814 /* 1815 * virtual function driver struct 1816 */ 1817 static struct rte_pci_driver rte_ixgbevf_pmd = { 1818 .id_table = pci_id_ixgbevf_map, 1819 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1820 .probe = eth_ixgbevf_pci_probe, 1821 .remove = eth_ixgbevf_pci_remove, 1822 }; 1823 1824 static int 1825 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1826 { 1827 struct ixgbe_hw *hw = 1828 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1829 struct ixgbe_vfta *shadow_vfta = 1830 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1831 uint32_t vfta; 1832 uint32_t vid_idx; 1833 uint32_t vid_bit; 1834 1835 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 1836 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 1837 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx)); 1838 if (on) 1839 vfta |= vid_bit; 1840 else 1841 vfta &= ~vid_bit; 1842 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta); 1843 1844 /* update local VFTA copy */ 1845 shadow_vfta->vfta[vid_idx] = vfta; 1846 1847 return 0; 1848 } 1849 1850 static void 1851 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 1852 { 1853 if (on) 1854 ixgbe_vlan_hw_strip_enable(dev, queue); 1855 else 1856 ixgbe_vlan_hw_strip_disable(dev, queue); 1857 } 1858 1859 static int 1860 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1861 enum rte_vlan_type vlan_type, 1862 uint16_t tpid) 1863 { 1864 struct ixgbe_hw *hw = 1865 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1866 int ret = 0; 1867 uint32_t reg; 1868 uint32_t qinq; 1869 1870 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1871 qinq &= IXGBE_DMATXCTL_GDV; 1872 1873 switch (vlan_type) { 1874 case RTE_ETH_VLAN_TYPE_INNER: 1875 if (qinq) { 1876 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1877 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1878 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1879 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1880 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1881 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1882 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1883 } else { 1884 ret = -ENOTSUP; 1885 PMD_DRV_LOG(ERR, "Inner type is not supported" 1886 " by single VLAN"); 1887 } 1888 break; 1889 case RTE_ETH_VLAN_TYPE_OUTER: 1890 if (qinq) { 1891 /* Only the high 16-bits is valid */ 1892 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid << 1893 IXGBE_EXVET_VET_EXT_SHIFT); 1894 } else { 1895 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1896 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1897 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1898 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1899 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1900 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1901 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1902 } 1903 1904 break; 1905 default: 1906 ret = -EINVAL; 1907 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type); 1908 break; 1909 } 1910 1911 return ret; 1912 } 1913 1914 void 1915 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev) 1916 { 1917 struct ixgbe_hw *hw = 1918 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1919 uint32_t vlnctrl; 1920 1921 PMD_INIT_FUNC_TRACE(); 1922 1923 /* Filter Table Disable */ 1924 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1925 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 1926 1927 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1928 } 1929 1930 void 1931 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1932 { 1933 struct ixgbe_hw *hw = 1934 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1935 struct ixgbe_vfta *shadow_vfta = 1936 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1937 uint32_t vlnctrl; 1938 uint16_t i; 1939 1940 PMD_INIT_FUNC_TRACE(); 1941 1942 /* Filter Table Enable */ 1943 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1944 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; 1945 vlnctrl |= IXGBE_VLNCTRL_VFE; 1946 1947 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1948 1949 /* write whatever is in local vfta copy */ 1950 for (i = 0; i < IXGBE_VFTA_SIZE; i++) 1951 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]); 1952 } 1953 1954 static void 1955 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on) 1956 { 1957 struct ixgbe_hwstrip *hwstrip = 1958 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private); 1959 struct ixgbe_rx_queue *rxq; 1960 1961 if (queue >= IXGBE_MAX_RX_QUEUE_NUM) 1962 return; 1963 1964 if (on) 1965 IXGBE_SET_HWSTRIP(hwstrip, queue); 1966 else 1967 IXGBE_CLEAR_HWSTRIP(hwstrip, queue); 1968 1969 if (queue >= dev->data->nb_rx_queues) 1970 return; 1971 1972 rxq = dev->data->rx_queues[queue]; 1973 1974 if (on) { 1975 rxq->vlan_flags = RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED; 1976 rxq->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 1977 } else { 1978 rxq->vlan_flags = RTE_MBUF_F_RX_VLAN; 1979 rxq->offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 1980 } 1981 } 1982 1983 static void 1984 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue) 1985 { 1986 struct ixgbe_hw *hw = 1987 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1988 uint32_t ctrl; 1989 1990 PMD_INIT_FUNC_TRACE(); 1991 1992 if (hw->mac.type == ixgbe_mac_82598EB) { 1993 /* No queue level support */ 1994 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 1995 return; 1996 } 1997 1998 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 1999 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2000 ctrl &= ~IXGBE_RXDCTL_VME; 2001 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2002 2003 /* record those setting for HW strip per queue */ 2004 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0); 2005 } 2006 2007 static void 2008 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue) 2009 { 2010 struct ixgbe_hw *hw = 2011 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2012 uint32_t ctrl; 2013 2014 PMD_INIT_FUNC_TRACE(); 2015 2016 if (hw->mac.type == ixgbe_mac_82598EB) { 2017 /* No queue level supported */ 2018 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2019 return; 2020 } 2021 2022 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2023 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2024 ctrl |= IXGBE_RXDCTL_VME; 2025 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2026 2027 /* record those setting for HW strip per queue */ 2028 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1); 2029 } 2030 2031 static void 2032 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev) 2033 { 2034 struct ixgbe_hw *hw = 2035 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2036 uint32_t ctrl; 2037 2038 PMD_INIT_FUNC_TRACE(); 2039 2040 /* DMATXCTRL: Geric Double VLAN Disable */ 2041 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2042 ctrl &= ~IXGBE_DMATXCTL_GDV; 2043 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2044 2045 /* CTRL_EXT: Global Double VLAN Disable */ 2046 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2047 ctrl &= ~IXGBE_EXTENDED_VLAN; 2048 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2049 2050 } 2051 2052 static void 2053 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) 2054 { 2055 struct ixgbe_hw *hw = 2056 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2057 uint32_t ctrl; 2058 2059 PMD_INIT_FUNC_TRACE(); 2060 2061 /* DMATXCTRL: Geric Double VLAN Enable */ 2062 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2063 ctrl |= IXGBE_DMATXCTL_GDV; 2064 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2065 2066 /* CTRL_EXT: Global Double VLAN Enable */ 2067 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2068 ctrl |= IXGBE_EXTENDED_VLAN; 2069 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2070 2071 /* Clear pooling mode of PFVTCTL. It's required by X550. */ 2072 if (hw->mac.type == ixgbe_mac_X550 || 2073 hw->mac.type == ixgbe_mac_X550EM_x || 2074 hw->mac.type == ixgbe_mac_X550EM_a) { 2075 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 2076 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 2077 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 2078 } 2079 2080 /* 2081 * VET EXT field in the EXVET register = 0x8100 by default 2082 * So no need to change. Same to VT field of DMATXCTL register 2083 */ 2084 } 2085 2086 void 2087 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev) 2088 { 2089 struct ixgbe_hw *hw = 2090 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2091 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 2092 uint32_t ctrl; 2093 uint16_t i; 2094 struct ixgbe_rx_queue *rxq; 2095 bool on; 2096 2097 PMD_INIT_FUNC_TRACE(); 2098 2099 if (hw->mac.type == ixgbe_mac_82598EB) { 2100 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) { 2101 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2102 ctrl |= IXGBE_VLNCTRL_VME; 2103 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2104 } else { 2105 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2106 ctrl &= ~IXGBE_VLNCTRL_VME; 2107 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2108 } 2109 } else { 2110 /* 2111 * Other 10G NIC, the VLAN strip can be setup 2112 * per queue in RXDCTL 2113 */ 2114 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2115 rxq = dev->data->rx_queues[i]; 2116 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx)); 2117 if (rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) { 2118 ctrl |= IXGBE_RXDCTL_VME; 2119 on = TRUE; 2120 } else { 2121 ctrl &= ~IXGBE_RXDCTL_VME; 2122 on = FALSE; 2123 } 2124 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl); 2125 2126 /* record those setting for HW strip per queue */ 2127 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on); 2128 } 2129 } 2130 } 2131 2132 static void 2133 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask) 2134 { 2135 uint16_t i; 2136 struct rte_eth_rxmode *rxmode; 2137 struct ixgbe_rx_queue *rxq; 2138 2139 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 2140 rxmode = &dev->data->dev_conf.rxmode; 2141 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 2142 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2143 rxq = dev->data->rx_queues[i]; 2144 rxq->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 2145 } 2146 else 2147 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2148 rxq = dev->data->rx_queues[i]; 2149 rxq->offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 2150 } 2151 } 2152 } 2153 2154 static int 2155 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask) 2156 { 2157 struct rte_eth_rxmode *rxmode; 2158 rxmode = &dev->data->dev_conf.rxmode; 2159 2160 if (mask & RTE_ETH_VLAN_STRIP_MASK) 2161 ixgbe_vlan_hw_strip_config(dev); 2162 2163 if (mask & RTE_ETH_VLAN_FILTER_MASK) { 2164 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) 2165 ixgbe_vlan_hw_filter_enable(dev); 2166 else 2167 ixgbe_vlan_hw_filter_disable(dev); 2168 } 2169 2170 if (mask & RTE_ETH_VLAN_EXTEND_MASK) { 2171 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) 2172 ixgbe_vlan_hw_extend_enable(dev); 2173 else 2174 ixgbe_vlan_hw_extend_disable(dev); 2175 } 2176 2177 return 0; 2178 } 2179 2180 static int 2181 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2182 { 2183 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 2184 2185 ixgbe_vlan_offload_config(dev, mask); 2186 2187 return 0; 2188 } 2189 2190 static void 2191 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev) 2192 { 2193 struct ixgbe_hw *hw = 2194 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2195 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */ 2196 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2197 2198 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */ 2199 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl); 2200 } 2201 2202 static int 2203 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q) 2204 { 2205 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2206 2207 switch (nb_rx_q) { 2208 case 1: 2209 case 2: 2210 RTE_ETH_DEV_SRIOV(dev).active = RTE_ETH_64_POOLS; 2211 break; 2212 case 4: 2213 RTE_ETH_DEV_SRIOV(dev).active = RTE_ETH_32_POOLS; 2214 break; 2215 default: 2216 return -EINVAL; 2217 } 2218 2219 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 2220 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2221 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 2222 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2223 return 0; 2224 } 2225 2226 static int 2227 ixgbe_check_mq_mode(struct rte_eth_dev *dev) 2228 { 2229 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 2230 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2231 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2232 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2233 2234 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 2235 /* check multi-queue mode */ 2236 switch (dev_conf->rxmode.mq_mode) { 2237 case RTE_ETH_MQ_RX_VMDQ_DCB: 2238 PMD_INIT_LOG(INFO, "RTE_ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV"); 2239 break; 2240 case RTE_ETH_MQ_RX_VMDQ_DCB_RSS: 2241 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */ 2242 PMD_INIT_LOG(ERR, "SRIOV active," 2243 " unsupported mq_mode rx %d.", 2244 dev_conf->rxmode.mq_mode); 2245 return -EINVAL; 2246 case RTE_ETH_MQ_RX_RSS: 2247 case RTE_ETH_MQ_RX_VMDQ_RSS: 2248 dev->data->dev_conf.rxmode.mq_mode = RTE_ETH_MQ_RX_VMDQ_RSS; 2249 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) 2250 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) { 2251 PMD_INIT_LOG(ERR, "SRIOV is active," 2252 " invalid queue number" 2253 " for VMDQ RSS, allowed" 2254 " value are 1, 2 or 4."); 2255 return -EINVAL; 2256 } 2257 break; 2258 case RTE_ETH_MQ_RX_VMDQ_ONLY: 2259 case RTE_ETH_MQ_RX_NONE: 2260 /* if nothing mq mode configure, use default scheme */ 2261 dev->data->dev_conf.rxmode.mq_mode = RTE_ETH_MQ_RX_VMDQ_ONLY; 2262 break; 2263 default: /* RTE_ETH_MQ_RX_DCB, RTE_ETH_MQ_RX_DCB_RSS or RTE_ETH_MQ_TX_DCB*/ 2264 /* SRIOV only works in VMDq enable mode */ 2265 PMD_INIT_LOG(ERR, "SRIOV is active," 2266 " wrong mq_mode rx %d.", 2267 dev_conf->rxmode.mq_mode); 2268 return -EINVAL; 2269 } 2270 2271 switch (dev_conf->txmode.mq_mode) { 2272 case RTE_ETH_MQ_TX_VMDQ_DCB: 2273 PMD_INIT_LOG(INFO, "RTE_ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV"); 2274 dev->data->dev_conf.txmode.mq_mode = RTE_ETH_MQ_TX_VMDQ_DCB; 2275 break; 2276 default: /* RTE_ETH_MQ_TX_VMDQ_ONLY or RTE_ETH_MQ_TX_NONE */ 2277 dev->data->dev_conf.txmode.mq_mode = RTE_ETH_MQ_TX_VMDQ_ONLY; 2278 break; 2279 } 2280 2281 /* check valid queue number */ 2282 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) || 2283 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) { 2284 PMD_INIT_LOG(ERR, "SRIOV is active," 2285 " nb_rx_q=%d nb_tx_q=%d queue number" 2286 " must be less than or equal to %d.", 2287 nb_rx_q, nb_tx_q, 2288 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool); 2289 return -EINVAL; 2290 } 2291 } else { 2292 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_DCB_RSS) { 2293 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is" 2294 " not supported."); 2295 return -EINVAL; 2296 } 2297 /* check configuration for vmdb+dcb mode */ 2298 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_DCB) { 2299 const struct rte_eth_vmdq_dcb_conf *conf; 2300 2301 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2302 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.", 2303 IXGBE_VMDQ_DCB_NB_QUEUES); 2304 return -EINVAL; 2305 } 2306 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf; 2307 if (!(conf->nb_queue_pools == RTE_ETH_16_POOLS || 2308 conf->nb_queue_pools == RTE_ETH_32_POOLS)) { 2309 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2310 " nb_queue_pools must be %d or %d.", 2311 RTE_ETH_16_POOLS, RTE_ETH_32_POOLS); 2312 return -EINVAL; 2313 } 2314 } 2315 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB) { 2316 const struct rte_eth_vmdq_dcb_tx_conf *conf; 2317 2318 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2319 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d", 2320 IXGBE_VMDQ_DCB_NB_QUEUES); 2321 return -EINVAL; 2322 } 2323 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf; 2324 if (!(conf->nb_queue_pools == RTE_ETH_16_POOLS || 2325 conf->nb_queue_pools == RTE_ETH_32_POOLS)) { 2326 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2327 " nb_queue_pools != %d and" 2328 " nb_queue_pools != %d.", 2329 RTE_ETH_16_POOLS, RTE_ETH_32_POOLS); 2330 return -EINVAL; 2331 } 2332 } 2333 2334 /* For DCB mode check our configuration before we go further */ 2335 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_DCB) { 2336 const struct rte_eth_dcb_rx_conf *conf; 2337 2338 conf = &dev_conf->rx_adv_conf.dcb_rx_conf; 2339 if (!(conf->nb_tcs == RTE_ETH_4_TCS || 2340 conf->nb_tcs == RTE_ETH_8_TCS)) { 2341 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2342 " and nb_tcs != %d.", 2343 RTE_ETH_4_TCS, RTE_ETH_8_TCS); 2344 return -EINVAL; 2345 } 2346 } 2347 2348 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_DCB) { 2349 const struct rte_eth_dcb_tx_conf *conf; 2350 2351 conf = &dev_conf->tx_adv_conf.dcb_tx_conf; 2352 if (!(conf->nb_tcs == RTE_ETH_4_TCS || 2353 conf->nb_tcs == RTE_ETH_8_TCS)) { 2354 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2355 " and nb_tcs != %d.", 2356 RTE_ETH_4_TCS, RTE_ETH_8_TCS); 2357 return -EINVAL; 2358 } 2359 } 2360 2361 /* 2362 * When DCB/VT is off, maximum number of queues changes, 2363 * except for 82598EB, which remains constant. 2364 */ 2365 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_NONE && 2366 hw->mac.type != ixgbe_mac_82598EB) { 2367 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) { 2368 PMD_INIT_LOG(ERR, 2369 "Neither VT nor DCB are enabled, " 2370 "nb_tx_q > %d.", 2371 IXGBE_NONE_MODE_TX_NB_QUEUES); 2372 return -EINVAL; 2373 } 2374 } 2375 } 2376 return 0; 2377 } 2378 2379 static int 2380 ixgbe_dev_configure(struct rte_eth_dev *dev) 2381 { 2382 struct ixgbe_interrupt *intr = 2383 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2384 struct ixgbe_adapter *adapter = dev->data->dev_private; 2385 int ret; 2386 2387 PMD_INIT_FUNC_TRACE(); 2388 2389 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 2390 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; 2391 2392 /* multiple queue mode checking */ 2393 ret = ixgbe_check_mq_mode(dev); 2394 if (ret != 0) { 2395 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.", 2396 ret); 2397 return ret; 2398 } 2399 2400 /* set flag to update link status after init */ 2401 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2402 2403 /* 2404 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 2405 * allocation or vector Rx preconditions we will reset it. 2406 */ 2407 adapter->rx_bulk_alloc_allowed = true; 2408 adapter->rx_vec_allowed = true; 2409 2410 return 0; 2411 } 2412 2413 static void 2414 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) 2415 { 2416 struct ixgbe_hw *hw = 2417 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2418 struct ixgbe_interrupt *intr = 2419 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2420 uint32_t gpie; 2421 2422 /* only set up it on X550EM_X */ 2423 if (hw->mac.type == ixgbe_mac_X550EM_x) { 2424 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 2425 gpie |= IXGBE_SDP0_GPIEN_X550EM_x; 2426 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 2427 if (hw->phy.type == ixgbe_phy_x550em_ext_t) 2428 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x; 2429 } 2430 } 2431 2432 int 2433 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 2434 uint16_t tx_rate, uint64_t q_msk) 2435 { 2436 struct ixgbe_hw *hw; 2437 struct ixgbe_vf_info *vfinfo; 2438 struct rte_eth_link link; 2439 uint8_t nb_q_per_pool; 2440 uint32_t queue_stride; 2441 uint32_t queue_idx, idx = 0, vf_idx; 2442 uint32_t queue_end; 2443 uint16_t total_rate = 0; 2444 struct rte_pci_device *pci_dev; 2445 int ret; 2446 2447 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2448 ret = rte_eth_link_get_nowait(dev->data->port_id, &link); 2449 if (ret < 0) 2450 return ret; 2451 2452 if (vf >= pci_dev->max_vfs) 2453 return -EINVAL; 2454 2455 if (tx_rate > link.link_speed) 2456 return -EINVAL; 2457 2458 if (q_msk == 0) 2459 return 0; 2460 2461 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2462 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 2463 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2464 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2465 queue_idx = vf * queue_stride; 2466 queue_end = queue_idx + nb_q_per_pool - 1; 2467 if (queue_end >= hw->mac.max_tx_queues) 2468 return -EINVAL; 2469 2470 if (vfinfo) { 2471 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) { 2472 if (vf_idx == vf) 2473 continue; 2474 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate); 2475 idx++) 2476 total_rate += vfinfo[vf_idx].tx_rate[idx]; 2477 } 2478 } else { 2479 return -EINVAL; 2480 } 2481 2482 /* Store tx_rate for this vf. */ 2483 for (idx = 0; idx < nb_q_per_pool; idx++) { 2484 if (((uint64_t)0x1 << idx) & q_msk) { 2485 if (vfinfo[vf].tx_rate[idx] != tx_rate) 2486 vfinfo[vf].tx_rate[idx] = tx_rate; 2487 total_rate += tx_rate; 2488 } 2489 } 2490 2491 if (total_rate > dev->data->dev_link.link_speed) { 2492 /* Reset stored TX rate of the VF if it causes exceed 2493 * link speed. 2494 */ 2495 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate)); 2496 return -EINVAL; 2497 } 2498 2499 /* Set RTTBCNRC of each queue/pool for vf X */ 2500 for (; queue_idx <= queue_end; queue_idx++) { 2501 if (0x1 & q_msk) 2502 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate); 2503 q_msk = q_msk >> 1; 2504 } 2505 2506 return 0; 2507 } 2508 2509 static int 2510 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw) 2511 { 2512 struct ixgbe_adapter *adapter = dev->data->dev_private; 2513 int err; 2514 uint32_t mflcn; 2515 2516 ixgbe_setup_fc(hw); 2517 2518 err = ixgbe_fc_enable(hw); 2519 2520 /* Not negotiated is not an error case */ 2521 if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) { 2522 /* 2523 *check if we want to forward MAC frames - driver doesn't 2524 *have native capability to do that, 2525 *so we'll write the registers ourselves 2526 */ 2527 2528 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2529 2530 /* set or clear MFLCN.PMCF bit depending on configuration */ 2531 if (adapter->mac_ctrl_frame_fwd != 0) 2532 mflcn |= IXGBE_MFLCN_PMCF; 2533 else 2534 mflcn &= ~IXGBE_MFLCN_PMCF; 2535 2536 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn); 2537 IXGBE_WRITE_FLUSH(hw); 2538 2539 return 0; 2540 } 2541 return err; 2542 } 2543 2544 /* 2545 * Configure device link speed and setup link. 2546 * It returns 0 on success. 2547 */ 2548 static int 2549 ixgbe_dev_start(struct rte_eth_dev *dev) 2550 { 2551 struct ixgbe_hw *hw = 2552 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2553 struct ixgbe_vf_info *vfinfo = 2554 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2555 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2556 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 2557 uint32_t intr_vector = 0; 2558 int err; 2559 bool link_up = false, negotiate = 0; 2560 uint32_t speed = 0; 2561 uint32_t allowed_speeds = 0; 2562 int mask = 0; 2563 int status; 2564 uint16_t vf, idx; 2565 uint32_t *link_speeds; 2566 struct ixgbe_tm_conf *tm_conf = 2567 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2568 struct ixgbe_macsec_setting *macsec_setting = 2569 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 2570 2571 PMD_INIT_FUNC_TRACE(); 2572 2573 /* Stop the link setup handler before resetting the HW. */ 2574 ixgbe_dev_wait_setup_link_complete(dev, 0); 2575 2576 /* disable uio/vfio intr/eventfd mapping */ 2577 rte_intr_disable(intr_handle); 2578 2579 /* stop adapter */ 2580 hw->adapter_stopped = 0; 2581 ixgbe_stop_adapter(hw); 2582 2583 /* reinitialize adapter 2584 * this calls reset and start 2585 */ 2586 status = ixgbe_pf_reset_hw(hw); 2587 if (status != 0) 2588 return -1; 2589 hw->mac.ops.start_hw(hw); 2590 hw->mac.get_link_status = true; 2591 2592 /* configure PF module if SRIOV enabled */ 2593 ixgbe_pf_host_configure(dev); 2594 2595 ixgbe_dev_phy_intr_setup(dev); 2596 2597 /* check and configure queue intr-vector mapping */ 2598 if ((rte_intr_cap_multiple(intr_handle) || 2599 !RTE_ETH_DEV_SRIOV(dev).active) && 2600 dev->data->dev_conf.intr_conf.rxq != 0) { 2601 intr_vector = dev->data->nb_rx_queues; 2602 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) { 2603 PMD_INIT_LOG(ERR, "At most %d intr queues supported", 2604 IXGBE_MAX_INTR_QUEUE_NUM); 2605 return -ENOTSUP; 2606 } 2607 if (rte_intr_efd_enable(intr_handle, intr_vector)) 2608 return -1; 2609 } 2610 2611 if (rte_intr_dp_is_en(intr_handle)) { 2612 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec", 2613 dev->data->nb_rx_queues)) { 2614 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 2615 " intr_vec", dev->data->nb_rx_queues); 2616 return -ENOMEM; 2617 } 2618 } 2619 2620 /* configure MSI-X for sleep until Rx interrupt */ 2621 ixgbe_configure_msix(dev); 2622 2623 /* initialize transmission unit */ 2624 ixgbe_dev_tx_init(dev); 2625 2626 /* This can fail when allocating mbufs for descriptor rings */ 2627 err = ixgbe_dev_rx_init(dev); 2628 if (err) { 2629 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 2630 goto error; 2631 } 2632 2633 mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK | 2634 RTE_ETH_VLAN_EXTEND_MASK; 2635 err = ixgbe_vlan_offload_config(dev, mask); 2636 if (err) { 2637 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 2638 goto error; 2639 } 2640 2641 if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_ONLY) { 2642 /* Enable vlan filtering for VMDq */ 2643 ixgbe_vmdq_vlan_hw_filter_enable(dev); 2644 } 2645 2646 /* Configure DCB hw */ 2647 ixgbe_configure_dcb(dev); 2648 2649 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) { 2650 err = ixgbe_fdir_configure(dev); 2651 if (err) 2652 goto error; 2653 } 2654 2655 /* Restore vf rate limit */ 2656 if (vfinfo != NULL) { 2657 for (vf = 0; vf < pci_dev->max_vfs; vf++) 2658 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++) 2659 if (vfinfo[vf].tx_rate[idx] != 0) 2660 ixgbe_set_vf_rate_limit( 2661 dev, vf, 2662 vfinfo[vf].tx_rate[idx], 2663 1 << idx); 2664 } 2665 2666 ixgbe_restore_statistics_mapping(dev); 2667 2668 err = ixgbe_flow_ctrl_enable(dev, hw); 2669 if (err < 0) { 2670 PMD_INIT_LOG(ERR, "enable flow ctrl err"); 2671 goto error; 2672 } 2673 2674 err = ixgbe_dev_rxtx_start(dev); 2675 if (err < 0) { 2676 PMD_INIT_LOG(ERR, "Unable to start rxtx queues"); 2677 goto error; 2678 } 2679 2680 /* Skip link setup if loopback mode is enabled. */ 2681 if (dev->data->dev_conf.lpbk_mode != 0) { 2682 err = ixgbe_check_supported_loopback_mode(dev); 2683 if (err < 0) { 2684 PMD_INIT_LOG(ERR, "Unsupported loopback mode"); 2685 goto error; 2686 } else { 2687 goto skip_link_setup; 2688 } 2689 } 2690 2691 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) { 2692 err = hw->mac.ops.setup_sfp(hw); 2693 if (err) 2694 goto error; 2695 } 2696 2697 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2698 /* Turn on the copper */ 2699 ixgbe_set_phy_power(hw, true); 2700 } else { 2701 /* Turn on the laser */ 2702 ixgbe_enable_tx_laser(hw); 2703 } 2704 2705 err = ixgbe_check_link(hw, &speed, &link_up, 0); 2706 if (err) 2707 goto error; 2708 dev->data->dev_link.link_status = link_up; 2709 2710 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate); 2711 if (err) 2712 goto error; 2713 2714 switch (hw->mac.type) { 2715 case ixgbe_mac_X550: 2716 case ixgbe_mac_X550EM_x: 2717 case ixgbe_mac_X550EM_a: 2718 allowed_speeds = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G | 2719 RTE_ETH_LINK_SPEED_2_5G | RTE_ETH_LINK_SPEED_5G | 2720 RTE_ETH_LINK_SPEED_10G; 2721 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 2722 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 2723 allowed_speeds = RTE_ETH_LINK_SPEED_10M | 2724 RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G; 2725 break; 2726 default: 2727 allowed_speeds = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G | 2728 RTE_ETH_LINK_SPEED_10G; 2729 } 2730 2731 link_speeds = &dev->data->dev_conf.link_speeds; 2732 2733 /* Ignore autoneg flag bit and check the validity of 2734 * link_speed 2735 */ 2736 if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) { 2737 PMD_INIT_LOG(ERR, "Invalid link setting"); 2738 goto error; 2739 } 2740 2741 speed = 0x0; 2742 if (*link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) { 2743 switch (hw->mac.type) { 2744 case ixgbe_mac_82598EB: 2745 speed = IXGBE_LINK_SPEED_82598_AUTONEG; 2746 break; 2747 case ixgbe_mac_82599EB: 2748 case ixgbe_mac_X540: 2749 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2750 break; 2751 case ixgbe_mac_X550: 2752 case ixgbe_mac_X550EM_x: 2753 case ixgbe_mac_X550EM_a: 2754 speed = IXGBE_LINK_SPEED_X550_AUTONEG; 2755 break; 2756 default: 2757 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2758 } 2759 } else { 2760 if (*link_speeds & RTE_ETH_LINK_SPEED_10G) 2761 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2762 if (*link_speeds & RTE_ETH_LINK_SPEED_5G) 2763 speed |= IXGBE_LINK_SPEED_5GB_FULL; 2764 if (*link_speeds & RTE_ETH_LINK_SPEED_2_5G) 2765 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 2766 if (*link_speeds & RTE_ETH_LINK_SPEED_1G) 2767 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2768 if (*link_speeds & RTE_ETH_LINK_SPEED_100M) 2769 speed |= IXGBE_LINK_SPEED_100_FULL; 2770 if (*link_speeds & RTE_ETH_LINK_SPEED_10M) 2771 speed |= IXGBE_LINK_SPEED_10_FULL; 2772 } 2773 2774 err = ixgbe_setup_link(hw, speed, link_up); 2775 if (err) 2776 goto error; 2777 2778 skip_link_setup: 2779 2780 if (rte_intr_allow_others(intr_handle)) { 2781 /* check if lsc interrupt is enabled */ 2782 if (dev->data->dev_conf.intr_conf.lsc != 0) 2783 ixgbe_dev_lsc_interrupt_setup(dev, TRUE); 2784 else 2785 ixgbe_dev_lsc_interrupt_setup(dev, FALSE); 2786 ixgbe_dev_macsec_interrupt_setup(dev); 2787 } else { 2788 rte_intr_callback_unregister(intr_handle, 2789 ixgbe_dev_interrupt_handler, dev); 2790 if (dev->data->dev_conf.intr_conf.lsc != 0) 2791 PMD_INIT_LOG(INFO, "lsc won't enable because of" 2792 " no intr multiplex"); 2793 } 2794 2795 /* check if rxq interrupt is enabled */ 2796 if (dev->data->dev_conf.intr_conf.rxq != 0 && 2797 rte_intr_dp_is_en(intr_handle)) 2798 ixgbe_dev_rxq_interrupt_setup(dev); 2799 2800 /* enable uio/vfio intr/eventfd mapping */ 2801 rte_intr_enable(intr_handle); 2802 2803 /* resume enabled intr since hw reset */ 2804 ixgbe_enable_intr(dev); 2805 ixgbe_l2_tunnel_conf(dev); 2806 ixgbe_filter_restore(dev); 2807 2808 if (tm_conf->root && !tm_conf->committed) 2809 PMD_DRV_LOG(WARNING, 2810 "please call hierarchy_commit() " 2811 "before starting the port"); 2812 2813 /* wait for the controller to acquire link */ 2814 err = ixgbe_wait_for_link_up(hw); 2815 if (err) 2816 goto error; 2817 2818 /* 2819 * Update link status right before return, because it may 2820 * start link configuration process in a separate thread. 2821 */ 2822 ixgbe_dev_link_update(dev, 0); 2823 2824 /* setup the macsec setting register */ 2825 if (macsec_setting->offload_en) 2826 ixgbe_dev_macsec_register_enable(dev, macsec_setting); 2827 2828 return 0; 2829 2830 error: 2831 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err); 2832 ixgbe_dev_clear_queues(dev); 2833 return -EIO; 2834 } 2835 2836 /* 2837 * Stop device: disable rx and tx functions to allow for reconfiguring. 2838 */ 2839 static int 2840 ixgbe_dev_stop(struct rte_eth_dev *dev) 2841 { 2842 struct rte_eth_link link; 2843 struct ixgbe_adapter *adapter = dev->data->dev_private; 2844 struct ixgbe_hw *hw = 2845 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2846 struct ixgbe_vf_info *vfinfo = 2847 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2848 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2849 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 2850 int vf; 2851 struct ixgbe_tm_conf *tm_conf = 2852 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2853 2854 if (hw->adapter_stopped) 2855 return 0; 2856 2857 PMD_INIT_FUNC_TRACE(); 2858 2859 ixgbe_dev_wait_setup_link_complete(dev, 0); 2860 2861 /* disable interrupts */ 2862 ixgbe_disable_intr(hw); 2863 2864 /* reset the NIC */ 2865 ixgbe_pf_reset_hw(hw); 2866 hw->adapter_stopped = 0; 2867 2868 /* stop adapter */ 2869 ixgbe_stop_adapter(hw); 2870 2871 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++) 2872 vfinfo[vf].clear_to_send = false; 2873 2874 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2875 /* Turn off the copper */ 2876 ixgbe_set_phy_power(hw, false); 2877 } else { 2878 /* Turn off the laser */ 2879 ixgbe_disable_tx_laser(hw); 2880 } 2881 2882 ixgbe_dev_clear_queues(dev); 2883 2884 /* Clear stored conf */ 2885 dev->data->scattered_rx = 0; 2886 dev->data->lro = 0; 2887 2888 /* Clear recorded link status */ 2889 memset(&link, 0, sizeof(link)); 2890 rte_eth_linkstatus_set(dev, &link); 2891 2892 if (!rte_intr_allow_others(intr_handle)) 2893 /* resume to the default handler */ 2894 rte_intr_callback_register(intr_handle, 2895 ixgbe_dev_interrupt_handler, 2896 (void *)dev); 2897 2898 /* Clean datapath event and queue/vec mapping */ 2899 rte_intr_efd_disable(intr_handle); 2900 rte_intr_vec_list_free(intr_handle); 2901 2902 /* reset hierarchy commit */ 2903 tm_conf->committed = false; 2904 2905 adapter->rss_reta_updated = 0; 2906 2907 hw->adapter_stopped = true; 2908 dev->data->dev_started = 0; 2909 2910 return 0; 2911 } 2912 2913 /* 2914 * Set device link up: enable tx. 2915 */ 2916 static int 2917 ixgbe_dev_set_link_up(struct rte_eth_dev *dev) 2918 { 2919 struct ixgbe_hw *hw = 2920 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2921 if (hw->mac.type == ixgbe_mac_82599EB) { 2922 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2923 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2924 /* Not supported in bypass mode */ 2925 PMD_INIT_LOG(ERR, "Set link up is not supported " 2926 "by device id 0x%x", hw->device_id); 2927 return -ENOTSUP; 2928 } 2929 #endif 2930 } 2931 2932 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2933 /* Turn on the copper */ 2934 ixgbe_set_phy_power(hw, true); 2935 } else { 2936 /* Turn on the laser */ 2937 ixgbe_enable_tx_laser(hw); 2938 ixgbe_dev_link_update(dev, 0); 2939 } 2940 2941 return 0; 2942 } 2943 2944 /* 2945 * Set device link down: disable tx. 2946 */ 2947 static int 2948 ixgbe_dev_set_link_down(struct rte_eth_dev *dev) 2949 { 2950 struct ixgbe_hw *hw = 2951 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2952 if (hw->mac.type == ixgbe_mac_82599EB) { 2953 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2954 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2955 /* Not supported in bypass mode */ 2956 PMD_INIT_LOG(ERR, "Set link down is not supported " 2957 "by device id 0x%x", hw->device_id); 2958 return -ENOTSUP; 2959 } 2960 #endif 2961 } 2962 2963 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2964 /* Turn off the copper */ 2965 ixgbe_set_phy_power(hw, false); 2966 } else { 2967 /* Turn off the laser */ 2968 ixgbe_disable_tx_laser(hw); 2969 ixgbe_dev_link_update(dev, 0); 2970 } 2971 2972 return 0; 2973 } 2974 2975 /* 2976 * Reset and stop device. 2977 */ 2978 static int 2979 ixgbe_dev_close(struct rte_eth_dev *dev) 2980 { 2981 struct ixgbe_hw *hw = 2982 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2983 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2984 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 2985 int retries = 0; 2986 int ret; 2987 2988 PMD_INIT_FUNC_TRACE(); 2989 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2990 return 0; 2991 2992 ixgbe_pf_reset_hw(hw); 2993 2994 ret = ixgbe_dev_stop(dev); 2995 2996 ixgbe_dev_free_queues(dev); 2997 2998 ixgbe_disable_pcie_master(hw); 2999 3000 /* reprogram the RAR[0] in case user changed it. */ 3001 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 3002 3003 /* Unlock any pending hardware semaphore */ 3004 ixgbe_swfw_lock_reset(hw); 3005 3006 /* disable uio intr before callback unregister */ 3007 rte_intr_disable(intr_handle); 3008 3009 do { 3010 ret = rte_intr_callback_unregister(intr_handle, 3011 ixgbe_dev_interrupt_handler, dev); 3012 if (ret >= 0 || ret == -ENOENT) { 3013 break; 3014 } else if (ret != -EAGAIN) { 3015 PMD_INIT_LOG(ERR, 3016 "intr callback unregister failed: %d", 3017 ret); 3018 } 3019 rte_delay_ms(100); 3020 } while (retries++ < (10 + IXGBE_LINK_UP_TIME)); 3021 3022 /* cancel the delay handler before remove dev */ 3023 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev); 3024 3025 /* uninitialize PF if max_vfs not zero */ 3026 ixgbe_pf_host_uninit(dev); 3027 3028 /* remove all the fdir filters & hash */ 3029 ixgbe_fdir_filter_uninit(dev); 3030 3031 /* remove all the L2 tunnel filters & hash */ 3032 ixgbe_l2_tn_filter_uninit(dev); 3033 3034 /* Remove all ntuple filters of the device */ 3035 ixgbe_ntuple_filter_uninit(dev); 3036 3037 /* clear all the filters list */ 3038 ixgbe_filterlist_flush(); 3039 3040 /* Remove all Traffic Manager configuration */ 3041 ixgbe_tm_conf_uninit(dev); 3042 3043 #ifdef RTE_LIB_SECURITY 3044 rte_free(dev->security_ctx); 3045 #endif 3046 3047 return ret; 3048 } 3049 3050 /* 3051 * Reset PF device. 3052 */ 3053 static int 3054 ixgbe_dev_reset(struct rte_eth_dev *dev) 3055 { 3056 int ret; 3057 3058 /* When a DPDK PMD PF begin to reset PF port, it should notify all 3059 * its VF to make them align with it. The detailed notification 3060 * mechanism is PMD specific. As to ixgbe PF, it is rather complex. 3061 * To avoid unexpected behavior in VF, currently reset of PF with 3062 * SR-IOV activation is not supported. It might be supported later. 3063 */ 3064 if (dev->data->sriov.active) 3065 return -ENOTSUP; 3066 3067 ret = eth_ixgbe_dev_uninit(dev); 3068 if (ret) 3069 return ret; 3070 3071 ret = eth_ixgbe_dev_init(dev, NULL); 3072 3073 return ret; 3074 } 3075 3076 static void 3077 ixgbe_read_stats_registers(struct ixgbe_hw *hw, 3078 struct ixgbe_hw_stats *hw_stats, 3079 struct ixgbe_macsec_stats *macsec_stats, 3080 uint64_t *total_missed_rx, uint64_t *total_qbrc, 3081 uint64_t *total_qprc, uint64_t *total_qprdc) 3082 { 3083 uint32_t bprc, lxon, lxoff, total; 3084 uint32_t delta_gprc = 0; 3085 unsigned i; 3086 /* Workaround for RX byte count not including CRC bytes when CRC 3087 * strip is enabled. CRC bytes are removed from counters when crc_strip 3088 * is disabled. 3089 */ 3090 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) & 3091 IXGBE_HLREG0_RXCRCSTRP); 3092 3093 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 3094 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC); 3095 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC); 3096 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC); 3097 3098 for (i = 0; i < 8; i++) { 3099 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 3100 3101 /* global total per queue */ 3102 hw_stats->mpc[i] += mp; 3103 /* Running comprehensive total for stats display */ 3104 *total_missed_rx += hw_stats->mpc[i]; 3105 if (hw->mac.type == ixgbe_mac_82598EB) { 3106 hw_stats->rnbc[i] += 3107 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 3108 hw_stats->pxonrxc[i] += 3109 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 3110 hw_stats->pxoffrxc[i] += 3111 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 3112 } else { 3113 hw_stats->pxonrxc[i] += 3114 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 3115 hw_stats->pxoffrxc[i] += 3116 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 3117 hw_stats->pxon2offc[i] += 3118 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 3119 } 3120 hw_stats->pxontxc[i] += 3121 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 3122 hw_stats->pxofftxc[i] += 3123 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 3124 } 3125 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3126 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 3127 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 3128 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 3129 3130 delta_gprc += delta_qprc; 3131 3132 hw_stats->qprc[i] += delta_qprc; 3133 hw_stats->qptc[i] += delta_qptc; 3134 3135 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 3136 hw_stats->qbrc[i] += 3137 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32); 3138 if (crc_strip == 0) 3139 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN; 3140 3141 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 3142 hw_stats->qbtc[i] += 3143 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32); 3144 3145 hw_stats->qprdc[i] += delta_qprdc; 3146 *total_qprdc += hw_stats->qprdc[i]; 3147 3148 *total_qprc += hw_stats->qprc[i]; 3149 *total_qbrc += hw_stats->qbrc[i]; 3150 } 3151 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC); 3152 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC); 3153 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 3154 3155 /* 3156 * An errata states that gprc actually counts good + missed packets: 3157 * Workaround to set gprc to summated queue packet receives 3158 */ 3159 hw_stats->gprc = *total_qprc; 3160 3161 if (hw->mac.type != ixgbe_mac_82598EB) { 3162 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 3163 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32); 3164 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 3165 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32); 3166 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 3167 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32); 3168 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 3169 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 3170 } else { 3171 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 3172 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 3173 /* 82598 only has a counter in the high register */ 3174 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 3175 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 3176 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 3177 } 3178 uint64_t old_tpr = hw_stats->tpr; 3179 3180 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 3181 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT); 3182 3183 if (crc_strip == 0) 3184 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN; 3185 3186 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC); 3187 hw_stats->gptc += delta_gptc; 3188 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN; 3189 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN; 3190 3191 /* 3192 * Workaround: mprc hardware is incorrectly counting 3193 * broadcasts, so for now we subtract those. 3194 */ 3195 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 3196 hw_stats->bprc += bprc; 3197 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 3198 if (hw->mac.type == ixgbe_mac_82598EB) 3199 hw_stats->mprc -= bprc; 3200 3201 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 3202 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 3203 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 3204 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 3205 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 3206 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 3207 3208 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 3209 hw_stats->lxontxc += lxon; 3210 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 3211 hw_stats->lxofftxc += lxoff; 3212 total = lxon + lxoff; 3213 3214 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 3215 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 3216 hw_stats->gptc -= total; 3217 hw_stats->mptc -= total; 3218 hw_stats->ptc64 -= total; 3219 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN; 3220 3221 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 3222 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 3223 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 3224 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 3225 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC); 3226 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC); 3227 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC); 3228 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 3229 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 3230 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 3231 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 3232 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 3233 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 3234 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC); 3235 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 3236 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST); 3237 /* Only read FCOE on 82599 */ 3238 if (hw->mac.type != ixgbe_mac_82598EB) { 3239 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 3240 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 3241 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 3242 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 3243 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 3244 } 3245 3246 /* Flow Director Stats registers */ 3247 if (hw->mac.type != ixgbe_mac_82598EB) { 3248 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 3249 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 3250 hw_stats->fdirustat_add += IXGBE_READ_REG(hw, 3251 IXGBE_FDIRUSTAT) & 0xFFFF; 3252 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw, 3253 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF; 3254 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw, 3255 IXGBE_FDIRFSTAT) & 0xFFFF; 3256 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw, 3257 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF; 3258 } 3259 /* MACsec Stats registers */ 3260 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT); 3261 macsec_stats->out_pkts_encrypted += 3262 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE); 3263 macsec_stats->out_pkts_protected += 3264 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP); 3265 macsec_stats->out_octets_encrypted += 3266 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE); 3267 macsec_stats->out_octets_protected += 3268 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP); 3269 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT); 3270 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD); 3271 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI); 3272 macsec_stats->in_pkts_unknownsci += 3273 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI); 3274 macsec_stats->in_octets_decrypted += 3275 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD); 3276 macsec_stats->in_octets_validated += 3277 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV); 3278 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH); 3279 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY); 3280 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE); 3281 for (i = 0; i < 2; i++) { 3282 macsec_stats->in_pkts_ok += 3283 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i)); 3284 macsec_stats->in_pkts_invalid += 3285 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i)); 3286 macsec_stats->in_pkts_notvalid += 3287 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i)); 3288 } 3289 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA); 3290 macsec_stats->in_pkts_notusingsa += 3291 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA); 3292 } 3293 3294 /* 3295 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c 3296 */ 3297 static int 3298 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3299 { 3300 struct ixgbe_hw *hw = 3301 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3302 struct ixgbe_hw_stats *hw_stats = 3303 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3304 struct ixgbe_macsec_stats *macsec_stats = 3305 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3306 dev->data->dev_private); 3307 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3308 unsigned i; 3309 3310 total_missed_rx = 0; 3311 total_qbrc = 0; 3312 total_qprc = 0; 3313 total_qprdc = 0; 3314 3315 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3316 &total_qbrc, &total_qprc, &total_qprdc); 3317 3318 if (stats == NULL) 3319 return -EINVAL; 3320 3321 /* Fill out the rte_eth_stats statistics structure */ 3322 stats->ipackets = total_qprc; 3323 stats->ibytes = total_qbrc; 3324 stats->opackets = hw_stats->gptc; 3325 stats->obytes = hw_stats->gotc; 3326 3327 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3328 stats->q_ipackets[i] = hw_stats->qprc[i]; 3329 stats->q_opackets[i] = hw_stats->qptc[i]; 3330 stats->q_ibytes[i] = hw_stats->qbrc[i]; 3331 stats->q_obytes[i] = hw_stats->qbtc[i]; 3332 stats->q_errors[i] = hw_stats->qprdc[i]; 3333 } 3334 3335 /* Rx Errors */ 3336 stats->imissed = total_missed_rx; 3337 stats->ierrors = hw_stats->crcerrs + 3338 hw_stats->mspdc + 3339 hw_stats->rlec + 3340 hw_stats->ruc + 3341 hw_stats->roc + 3342 hw_stats->illerrc + 3343 hw_stats->errbc + 3344 hw_stats->rfc + 3345 hw_stats->fccrc + 3346 hw_stats->fclast; 3347 3348 /* 3349 * 82599 errata, UDP frames with a 0 checksum can be marked as checksum 3350 * errors. 3351 */ 3352 if (hw->mac.type != ixgbe_mac_82599EB) 3353 stats->ierrors += hw_stats->xec; 3354 3355 /* Tx Errors */ 3356 stats->oerrors = 0; 3357 return 0; 3358 } 3359 3360 static int 3361 ixgbe_dev_stats_reset(struct rte_eth_dev *dev) 3362 { 3363 struct ixgbe_hw_stats *stats = 3364 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3365 3366 /* HW registers are cleared on read */ 3367 ixgbe_dev_stats_get(dev, NULL); 3368 3369 /* Reset software totals */ 3370 memset(stats, 0, sizeof(*stats)); 3371 3372 return 0; 3373 } 3374 3375 /* This function calculates the number of xstats based on the current config */ 3376 static unsigned 3377 ixgbe_xstats_calc_num(void) { 3378 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS + 3379 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) + 3380 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES); 3381 } 3382 3383 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3384 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size) 3385 { 3386 const unsigned cnt_stats = ixgbe_xstats_calc_num(); 3387 unsigned stat, i, count; 3388 3389 if (xstats_names != NULL) { 3390 count = 0; 3391 3392 /* Note: limit >= cnt_stats checked upstream 3393 * in rte_eth_xstats_names() 3394 */ 3395 3396 /* Extended stats from ixgbe_hw_stats */ 3397 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3398 strlcpy(xstats_names[count].name, 3399 rte_ixgbe_stats_strings[i].name, 3400 sizeof(xstats_names[count].name)); 3401 count++; 3402 } 3403 3404 /* MACsec Stats */ 3405 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3406 strlcpy(xstats_names[count].name, 3407 rte_ixgbe_macsec_strings[i].name, 3408 sizeof(xstats_names[count].name)); 3409 count++; 3410 } 3411 3412 /* RX Priority Stats */ 3413 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3414 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3415 snprintf(xstats_names[count].name, 3416 sizeof(xstats_names[count].name), 3417 "rx_priority%u_%s", i, 3418 rte_ixgbe_rxq_strings[stat].name); 3419 count++; 3420 } 3421 } 3422 3423 /* TX Priority Stats */ 3424 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3425 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3426 snprintf(xstats_names[count].name, 3427 sizeof(xstats_names[count].name), 3428 "tx_priority%u_%s", i, 3429 rte_ixgbe_txq_strings[stat].name); 3430 count++; 3431 } 3432 } 3433 } 3434 return cnt_stats; 3435 } 3436 3437 static int ixgbe_dev_xstats_get_names_by_id( 3438 struct rte_eth_dev *dev, 3439 const uint64_t *ids, 3440 struct rte_eth_xstat_name *xstats_names, 3441 unsigned int limit) 3442 { 3443 if (!ids) { 3444 const unsigned int cnt_stats = ixgbe_xstats_calc_num(); 3445 unsigned int stat, i, count; 3446 3447 if (xstats_names != NULL) { 3448 count = 0; 3449 3450 /* Note: limit >= cnt_stats checked upstream 3451 * in rte_eth_xstats_names() 3452 */ 3453 3454 /* Extended stats from ixgbe_hw_stats */ 3455 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3456 strlcpy(xstats_names[count].name, 3457 rte_ixgbe_stats_strings[i].name, 3458 sizeof(xstats_names[count].name)); 3459 count++; 3460 } 3461 3462 /* MACsec Stats */ 3463 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3464 strlcpy(xstats_names[count].name, 3465 rte_ixgbe_macsec_strings[i].name, 3466 sizeof(xstats_names[count].name)); 3467 count++; 3468 } 3469 3470 /* RX Priority Stats */ 3471 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3472 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3473 snprintf(xstats_names[count].name, 3474 sizeof(xstats_names[count].name), 3475 "rx_priority%u_%s", i, 3476 rte_ixgbe_rxq_strings[stat].name); 3477 count++; 3478 } 3479 } 3480 3481 /* TX Priority Stats */ 3482 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3483 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3484 snprintf(xstats_names[count].name, 3485 sizeof(xstats_names[count].name), 3486 "tx_priority%u_%s", i, 3487 rte_ixgbe_txq_strings[stat].name); 3488 count++; 3489 } 3490 } 3491 } 3492 return cnt_stats; 3493 } 3494 3495 uint16_t i; 3496 uint16_t size = ixgbe_xstats_calc_num(); 3497 struct rte_eth_xstat_name xstats_names_copy[size]; 3498 3499 ixgbe_dev_xstats_get_names_by_id(dev, NULL, xstats_names_copy, 3500 size); 3501 3502 for (i = 0; i < limit; i++) { 3503 if (ids[i] >= size) { 3504 PMD_INIT_LOG(ERR, "id value isn't valid"); 3505 return -1; 3506 } 3507 strcpy(xstats_names[i].name, 3508 xstats_names_copy[ids[i]].name); 3509 } 3510 return limit; 3511 } 3512 3513 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3514 struct rte_eth_xstat_name *xstats_names, unsigned limit) 3515 { 3516 unsigned i; 3517 3518 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL) 3519 return -ENOMEM; 3520 3521 if (xstats_names != NULL) 3522 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) 3523 strlcpy(xstats_names[i].name, 3524 rte_ixgbevf_stats_strings[i].name, 3525 sizeof(xstats_names[i].name)); 3526 return IXGBEVF_NB_XSTATS; 3527 } 3528 3529 static int 3530 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3531 unsigned n) 3532 { 3533 struct ixgbe_hw *hw = 3534 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3535 struct ixgbe_hw_stats *hw_stats = 3536 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3537 struct ixgbe_macsec_stats *macsec_stats = 3538 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3539 dev->data->dev_private); 3540 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3541 unsigned i, stat, count = 0; 3542 3543 count = ixgbe_xstats_calc_num(); 3544 3545 if (n < count) 3546 return count; 3547 3548 total_missed_rx = 0; 3549 total_qbrc = 0; 3550 total_qprc = 0; 3551 total_qprdc = 0; 3552 3553 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3554 &total_qbrc, &total_qprc, &total_qprdc); 3555 3556 /* If this is a reset xstats is NULL, and we have cleared the 3557 * registers by reading them. 3558 */ 3559 if (!xstats) 3560 return 0; 3561 3562 /* Extended stats from ixgbe_hw_stats */ 3563 count = 0; 3564 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3565 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3566 rte_ixgbe_stats_strings[i].offset); 3567 xstats[count].id = count; 3568 count++; 3569 } 3570 3571 /* MACsec Stats */ 3572 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3573 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) + 3574 rte_ixgbe_macsec_strings[i].offset); 3575 xstats[count].id = count; 3576 count++; 3577 } 3578 3579 /* RX Priority Stats */ 3580 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3581 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3582 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3583 rte_ixgbe_rxq_strings[stat].offset + 3584 (sizeof(uint64_t) * i)); 3585 xstats[count].id = count; 3586 count++; 3587 } 3588 } 3589 3590 /* TX Priority Stats */ 3591 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3592 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3593 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3594 rte_ixgbe_txq_strings[stat].offset + 3595 (sizeof(uint64_t) * i)); 3596 xstats[count].id = count; 3597 count++; 3598 } 3599 } 3600 return count; 3601 } 3602 3603 static int 3604 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 3605 uint64_t *values, unsigned int n) 3606 { 3607 if (!ids) { 3608 struct ixgbe_hw *hw = 3609 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3610 struct ixgbe_hw_stats *hw_stats = 3611 IXGBE_DEV_PRIVATE_TO_STATS( 3612 dev->data->dev_private); 3613 struct ixgbe_macsec_stats *macsec_stats = 3614 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3615 dev->data->dev_private); 3616 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3617 unsigned int i, stat, count = 0; 3618 3619 count = ixgbe_xstats_calc_num(); 3620 3621 if (!ids && n < count) 3622 return count; 3623 3624 total_missed_rx = 0; 3625 total_qbrc = 0; 3626 total_qprc = 0; 3627 total_qprdc = 0; 3628 3629 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, 3630 &total_missed_rx, &total_qbrc, &total_qprc, 3631 &total_qprdc); 3632 3633 /* If this is a reset xstats is NULL, and we have cleared the 3634 * registers by reading them. 3635 */ 3636 if (!ids && !values) 3637 return 0; 3638 3639 /* Extended stats from ixgbe_hw_stats */ 3640 count = 0; 3641 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3642 values[count] = *(uint64_t *)(((char *)hw_stats) + 3643 rte_ixgbe_stats_strings[i].offset); 3644 count++; 3645 } 3646 3647 /* MACsec Stats */ 3648 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3649 values[count] = *(uint64_t *)(((char *)macsec_stats) + 3650 rte_ixgbe_macsec_strings[i].offset); 3651 count++; 3652 } 3653 3654 /* RX Priority Stats */ 3655 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3656 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3657 values[count] = 3658 *(uint64_t *)(((char *)hw_stats) + 3659 rte_ixgbe_rxq_strings[stat].offset + 3660 (sizeof(uint64_t) * i)); 3661 count++; 3662 } 3663 } 3664 3665 /* TX Priority Stats */ 3666 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3667 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3668 values[count] = 3669 *(uint64_t *)(((char *)hw_stats) + 3670 rte_ixgbe_txq_strings[stat].offset + 3671 (sizeof(uint64_t) * i)); 3672 count++; 3673 } 3674 } 3675 return count; 3676 } 3677 3678 uint16_t i; 3679 uint16_t size = ixgbe_xstats_calc_num(); 3680 uint64_t values_copy[size]; 3681 3682 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size); 3683 3684 for (i = 0; i < n; i++) { 3685 if (ids[i] >= size) { 3686 PMD_INIT_LOG(ERR, "id value isn't valid"); 3687 return -1; 3688 } 3689 values[i] = values_copy[ids[i]]; 3690 } 3691 return n; 3692 } 3693 3694 static int 3695 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev) 3696 { 3697 struct ixgbe_hw_stats *stats = 3698 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3699 struct ixgbe_macsec_stats *macsec_stats = 3700 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3701 dev->data->dev_private); 3702 3703 unsigned count = ixgbe_xstats_calc_num(); 3704 3705 /* HW registers are cleared on read */ 3706 ixgbe_dev_xstats_get(dev, NULL, count); 3707 3708 /* Reset software totals */ 3709 memset(stats, 0, sizeof(*stats)); 3710 memset(macsec_stats, 0, sizeof(*macsec_stats)); 3711 3712 return 0; 3713 } 3714 3715 static void 3716 ixgbevf_update_stats(struct rte_eth_dev *dev) 3717 { 3718 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3719 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3720 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3721 3722 /* Good Rx packet, include VF loopback */ 3723 UPDATE_VF_STAT(IXGBE_VFGPRC, 3724 hw_stats->last_vfgprc, hw_stats->vfgprc); 3725 3726 /* Good Rx octets, include VF loopback */ 3727 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB, 3728 hw_stats->last_vfgorc, hw_stats->vfgorc); 3729 3730 /* Good Tx packet, include VF loopback */ 3731 UPDATE_VF_STAT(IXGBE_VFGPTC, 3732 hw_stats->last_vfgptc, hw_stats->vfgptc); 3733 3734 /* Good Tx octets, include VF loopback */ 3735 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB, 3736 hw_stats->last_vfgotc, hw_stats->vfgotc); 3737 3738 /* Rx Multicst Packet */ 3739 UPDATE_VF_STAT(IXGBE_VFMPRC, 3740 hw_stats->last_vfmprc, hw_stats->vfmprc); 3741 } 3742 3743 static int 3744 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3745 unsigned n) 3746 { 3747 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3748 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3749 unsigned i; 3750 3751 if (n < IXGBEVF_NB_XSTATS) 3752 return IXGBEVF_NB_XSTATS; 3753 3754 ixgbevf_update_stats(dev); 3755 3756 if (!xstats) 3757 return 0; 3758 3759 /* Extended stats */ 3760 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) { 3761 xstats[i].id = i; 3762 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + 3763 rte_ixgbevf_stats_strings[i].offset); 3764 } 3765 3766 return IXGBEVF_NB_XSTATS; 3767 } 3768 3769 static int 3770 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3771 { 3772 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3773 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3774 3775 ixgbevf_update_stats(dev); 3776 3777 if (stats == NULL) 3778 return -EINVAL; 3779 3780 stats->ipackets = hw_stats->vfgprc; 3781 stats->ibytes = hw_stats->vfgorc; 3782 stats->opackets = hw_stats->vfgptc; 3783 stats->obytes = hw_stats->vfgotc; 3784 return 0; 3785 } 3786 3787 static int 3788 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev) 3789 { 3790 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3791 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3792 3793 /* Sync HW register to the last stats */ 3794 ixgbevf_dev_stats_get(dev, NULL); 3795 3796 /* reset HW current stats*/ 3797 hw_stats->vfgprc = 0; 3798 hw_stats->vfgorc = 0; 3799 hw_stats->vfgptc = 0; 3800 hw_stats->vfgotc = 0; 3801 hw_stats->vfmprc = 0; 3802 3803 return 0; 3804 } 3805 3806 static int 3807 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 3808 { 3809 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3810 u16 eeprom_verh, eeprom_verl; 3811 u32 etrack_id; 3812 int ret; 3813 3814 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh); 3815 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl); 3816 3817 etrack_id = (eeprom_verh << 16) | eeprom_verl; 3818 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id); 3819 if (ret < 0) 3820 return -EINVAL; 3821 3822 ret += 1; /* add the size of '\0' */ 3823 if (fw_size < (size_t)ret) 3824 return ret; 3825 else 3826 return 0; 3827 } 3828 3829 static int 3830 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3831 { 3832 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3833 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3834 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 3835 3836 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3837 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3838 if (RTE_ETH_DEV_SRIOV(dev).active == 0) { 3839 /* 3840 * When DCB/VT is off, maximum number of queues changes, 3841 * except for 82598EB, which remains constant. 3842 */ 3843 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_NONE && 3844 hw->mac.type != ixgbe_mac_82598EB) 3845 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES; 3846 } 3847 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */ 3848 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */ 3849 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3850 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3851 dev_info->max_vfs = pci_dev->max_vfs; 3852 if (hw->mac.type == ixgbe_mac_82598EB) 3853 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS; 3854 else 3855 dev_info->max_vmdq_pools = RTE_ETH_64_POOLS; 3856 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD; 3857 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 3858 dev_info->vmdq_queue_num = dev_info->max_rx_queues; 3859 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3860 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3861 dev_info->rx_queue_offload_capa); 3862 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3863 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3864 3865 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3866 .rx_thresh = { 3867 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3868 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3869 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3870 }, 3871 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3872 .rx_drop_en = 0, 3873 .offloads = 0, 3874 }; 3875 3876 dev_info->default_txconf = (struct rte_eth_txconf) { 3877 .tx_thresh = { 3878 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3879 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3880 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3881 }, 3882 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3883 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3884 .offloads = 0, 3885 }; 3886 3887 dev_info->rx_desc_lim = rx_desc_lim; 3888 dev_info->tx_desc_lim = tx_desc_lim; 3889 3890 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 3891 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 3892 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 3893 3894 dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G; 3895 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 3896 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 3897 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M | 3898 RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G; 3899 3900 if (hw->mac.type == ixgbe_mac_X540 || 3901 hw->mac.type == ixgbe_mac_X540_vf || 3902 hw->mac.type == ixgbe_mac_X550 || 3903 hw->mac.type == ixgbe_mac_X550_vf) { 3904 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_100M; 3905 } 3906 if (hw->mac.type == ixgbe_mac_X550) { 3907 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_2_5G; 3908 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_5G; 3909 } 3910 3911 /* Driver-preferred Rx/Tx parameters */ 3912 dev_info->default_rxportconf.burst_size = 32; 3913 dev_info->default_txportconf.burst_size = 32; 3914 dev_info->default_rxportconf.nb_queues = 1; 3915 dev_info->default_txportconf.nb_queues = 1; 3916 dev_info->default_rxportconf.ring_size = 256; 3917 dev_info->default_txportconf.ring_size = 256; 3918 3919 return 0; 3920 } 3921 3922 static const uint32_t * 3923 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 3924 { 3925 static const uint32_t ptypes[] = { 3926 /* For non-vec functions, 3927 * refers to ixgbe_rxd_pkt_info_to_pkt_type(); 3928 * for vec functions, 3929 * refers to _recv_raw_pkts_vec(). 3930 */ 3931 RTE_PTYPE_L2_ETHER, 3932 RTE_PTYPE_L3_IPV4, 3933 RTE_PTYPE_L3_IPV4_EXT, 3934 RTE_PTYPE_L3_IPV6, 3935 RTE_PTYPE_L3_IPV6_EXT, 3936 RTE_PTYPE_L4_SCTP, 3937 RTE_PTYPE_L4_TCP, 3938 RTE_PTYPE_L4_UDP, 3939 RTE_PTYPE_TUNNEL_IP, 3940 RTE_PTYPE_INNER_L3_IPV6, 3941 RTE_PTYPE_INNER_L3_IPV6_EXT, 3942 RTE_PTYPE_INNER_L4_TCP, 3943 RTE_PTYPE_INNER_L4_UDP, 3944 RTE_PTYPE_UNKNOWN 3945 }; 3946 3947 if (dev->rx_pkt_burst == ixgbe_recv_pkts || 3948 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc || 3949 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc || 3950 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc) 3951 return ptypes; 3952 3953 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON) 3954 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec || 3955 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec) 3956 return ptypes; 3957 #endif 3958 return NULL; 3959 } 3960 3961 static int 3962 ixgbevf_dev_info_get(struct rte_eth_dev *dev, 3963 struct rte_eth_dev_info *dev_info) 3964 { 3965 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3966 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3967 3968 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3969 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3970 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */ 3971 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */ 3972 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD; 3973 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3974 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3975 dev_info->max_vfs = pci_dev->max_vfs; 3976 if (hw->mac.type == ixgbe_mac_82598EB) 3977 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS; 3978 else 3979 dev_info->max_vmdq_pools = RTE_ETH_64_POOLS; 3980 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3981 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3982 dev_info->rx_queue_offload_capa); 3983 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3984 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3985 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 3986 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 3987 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 3988 3989 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3990 .rx_thresh = { 3991 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3992 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3993 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3994 }, 3995 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3996 .rx_drop_en = 0, 3997 .offloads = 0, 3998 }; 3999 4000 dev_info->default_txconf = (struct rte_eth_txconf) { 4001 .tx_thresh = { 4002 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 4003 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 4004 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 4005 }, 4006 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 4007 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 4008 .offloads = 0, 4009 }; 4010 4011 dev_info->rx_desc_lim = rx_desc_lim; 4012 dev_info->tx_desc_lim = tx_desc_lim; 4013 4014 return 0; 4015 } 4016 4017 static int 4018 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4019 bool *link_up, int wait_to_complete) 4020 { 4021 struct ixgbe_adapter *adapter = container_of(hw, 4022 struct ixgbe_adapter, hw); 4023 struct ixgbe_mbx_info *mbx = &hw->mbx; 4024 struct ixgbe_mac_info *mac = &hw->mac; 4025 uint32_t links_reg, in_msg; 4026 int ret_val = 0; 4027 4028 /* If we were hit with a reset drop the link */ 4029 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout) 4030 mac->get_link_status = true; 4031 4032 if (!mac->get_link_status) 4033 goto out; 4034 4035 /* if link status is down no point in checking to see if pf is up */ 4036 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 4037 if (!(links_reg & IXGBE_LINKS_UP)) 4038 goto out; 4039 4040 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs 4041 * before the link status is correct 4042 */ 4043 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) { 4044 int i; 4045 4046 for (i = 0; i < 5; i++) { 4047 rte_delay_us(100); 4048 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 4049 4050 if (!(links_reg & IXGBE_LINKS_UP)) 4051 goto out; 4052 } 4053 } 4054 4055 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 4056 case IXGBE_LINKS_SPEED_10G_82599: 4057 *speed = IXGBE_LINK_SPEED_10GB_FULL; 4058 if (hw->mac.type >= ixgbe_mac_X550) { 4059 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4060 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4061 } 4062 break; 4063 case IXGBE_LINKS_SPEED_1G_82599: 4064 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4065 break; 4066 case IXGBE_LINKS_SPEED_100_82599: 4067 *speed = IXGBE_LINK_SPEED_100_FULL; 4068 if (hw->mac.type == ixgbe_mac_X550) { 4069 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4070 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4071 } 4072 break; 4073 case IXGBE_LINKS_SPEED_10_X550EM_A: 4074 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4075 /* Since Reserved in older MAC's */ 4076 if (hw->mac.type >= ixgbe_mac_X550) 4077 *speed = IXGBE_LINK_SPEED_10_FULL; 4078 break; 4079 default: 4080 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4081 } 4082 4083 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) { 4084 if (*speed == IXGBE_LINK_SPEED_UNKNOWN) 4085 mac->get_link_status = true; 4086 else 4087 mac->get_link_status = false; 4088 4089 goto out; 4090 } 4091 4092 /* if the read failed it could just be a mailbox collision, best wait 4093 * until we are called again and don't report an error 4094 */ 4095 if (mbx->ops.read(hw, &in_msg, 1, 0)) 4096 goto out; 4097 4098 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) { 4099 /* msg is not CTS and is NACK we must have lost CTS status */ 4100 if (in_msg & IXGBE_VT_MSGTYPE_NACK) 4101 mac->get_link_status = false; 4102 goto out; 4103 } 4104 4105 /* the pf is talking, if we timed out in the past we reinit */ 4106 if (!mbx->timeout) { 4107 ret_val = -1; 4108 goto out; 4109 } 4110 4111 /* if we passed all the tests above then the link is up and we no 4112 * longer need to check for link 4113 */ 4114 mac->get_link_status = false; 4115 4116 out: 4117 *link_up = !mac->get_link_status; 4118 return ret_val; 4119 } 4120 4121 /* 4122 * If @timeout_ms was 0, it means that it will not return until link complete. 4123 * It returns 1 on complete, return 0 on timeout. 4124 */ 4125 static int 4126 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms) 4127 { 4128 #define WARNING_TIMEOUT 9000 /* 9s in total */ 4129 struct ixgbe_adapter *ad = dev->data->dev_private; 4130 uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT; 4131 4132 while (rte_atomic32_read(&ad->link_thread_running)) { 4133 msec_delay(1); 4134 timeout--; 4135 4136 if (timeout_ms) { 4137 if (!timeout) 4138 return 0; 4139 } else if (!timeout) { 4140 /* It will not return until link complete */ 4141 timeout = WARNING_TIMEOUT; 4142 PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!"); 4143 } 4144 } 4145 4146 return 1; 4147 } 4148 4149 static void * 4150 ixgbe_dev_setup_link_thread_handler(void *param) 4151 { 4152 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4153 struct ixgbe_adapter *ad = dev->data->dev_private; 4154 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4155 struct ixgbe_interrupt *intr = 4156 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4157 u32 speed; 4158 bool autoneg = false; 4159 4160 pthread_detach(pthread_self()); 4161 speed = hw->phy.autoneg_advertised; 4162 if (!speed) 4163 ixgbe_get_link_capabilities(hw, &speed, &autoneg); 4164 4165 ixgbe_setup_link(hw, speed, true); 4166 4167 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 4168 rte_atomic32_clear(&ad->link_thread_running); 4169 return NULL; 4170 } 4171 4172 /* 4173 * In freebsd environment, nic_uio drivers do not support interrupts, 4174 * rte_intr_callback_register() will fail to register interrupts. 4175 * We can not make link status to change from down to up by interrupt 4176 * callback. So we need to wait for the controller to acquire link 4177 * when ports start. 4178 * It returns 0 on link up. 4179 */ 4180 static int 4181 ixgbe_wait_for_link_up(struct ixgbe_hw *hw) 4182 { 4183 #ifdef RTE_EXEC_ENV_FREEBSD 4184 int err, i; 4185 bool link_up = false; 4186 uint32_t speed = 0; 4187 const int nb_iter = 25; 4188 4189 for (i = 0; i < nb_iter; i++) { 4190 err = ixgbe_check_link(hw, &speed, &link_up, 0); 4191 if (err) 4192 return err; 4193 if (link_up) 4194 return 0; 4195 msec_delay(200); 4196 } 4197 4198 return 0; 4199 #else 4200 RTE_SET_USED(hw); 4201 return 0; 4202 #endif 4203 } 4204 4205 /* return 0 means link status changed, -1 means not changed */ 4206 int 4207 ixgbe_dev_link_update_share(struct rte_eth_dev *dev, 4208 int wait_to_complete, int vf) 4209 { 4210 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4211 struct ixgbe_adapter *ad = dev->data->dev_private; 4212 struct rte_eth_link link; 4213 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4214 struct ixgbe_interrupt *intr = 4215 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4216 bool link_up; 4217 int diag; 4218 int wait = 1; 4219 u32 esdp_reg; 4220 4221 memset(&link, 0, sizeof(link)); 4222 link.link_status = RTE_ETH_LINK_DOWN; 4223 link.link_speed = RTE_ETH_SPEED_NUM_NONE; 4224 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX; 4225 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 4226 RTE_ETH_LINK_SPEED_FIXED); 4227 4228 hw->mac.get_link_status = true; 4229 4230 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) 4231 return rte_eth_linkstatus_set(dev, &link); 4232 4233 /* check if it needs to wait to complete, if lsc interrupt is enabled */ 4234 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0) 4235 wait = 0; 4236 4237 /* BSD has no interrupt mechanism, so force NIC status synchronization. */ 4238 #ifdef RTE_EXEC_ENV_FREEBSD 4239 wait = 1; 4240 #endif 4241 4242 if (vf) 4243 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait); 4244 else 4245 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait); 4246 4247 if (diag != 0) { 4248 link.link_speed = RTE_ETH_SPEED_NUM_100M; 4249 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 4250 return rte_eth_linkstatus_set(dev, &link); 4251 } 4252 4253 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) { 4254 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 4255 if ((esdp_reg & IXGBE_ESDP_SDP3)) 4256 link_up = 0; 4257 } 4258 4259 if (link_up == 0) { 4260 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) { 4261 ixgbe_dev_wait_setup_link_complete(dev, 0); 4262 if (rte_atomic32_test_and_set(&ad->link_thread_running)) { 4263 /* To avoid race condition between threads, set 4264 * the IXGBE_FLAG_NEED_LINK_CONFIG flag only 4265 * when there is no link thread running. 4266 */ 4267 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 4268 if (rte_ctrl_thread_create(&ad->link_thread_tid, 4269 "ixgbe-link-handler", 4270 NULL, 4271 ixgbe_dev_setup_link_thread_handler, 4272 dev) < 0) { 4273 PMD_DRV_LOG(ERR, 4274 "Create link thread failed!"); 4275 rte_atomic32_clear(&ad->link_thread_running); 4276 } 4277 } else { 4278 PMD_DRV_LOG(ERR, 4279 "Other link thread is running now!"); 4280 } 4281 } 4282 return rte_eth_linkstatus_set(dev, &link); 4283 } 4284 4285 link.link_status = RTE_ETH_LINK_UP; 4286 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 4287 4288 switch (link_speed) { 4289 default: 4290 case IXGBE_LINK_SPEED_UNKNOWN: 4291 link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN; 4292 break; 4293 4294 case IXGBE_LINK_SPEED_10_FULL: 4295 link.link_speed = RTE_ETH_SPEED_NUM_10M; 4296 break; 4297 4298 case IXGBE_LINK_SPEED_100_FULL: 4299 link.link_speed = RTE_ETH_SPEED_NUM_100M; 4300 break; 4301 4302 case IXGBE_LINK_SPEED_1GB_FULL: 4303 link.link_speed = RTE_ETH_SPEED_NUM_1G; 4304 break; 4305 4306 case IXGBE_LINK_SPEED_2_5GB_FULL: 4307 link.link_speed = RTE_ETH_SPEED_NUM_2_5G; 4308 break; 4309 4310 case IXGBE_LINK_SPEED_5GB_FULL: 4311 link.link_speed = RTE_ETH_SPEED_NUM_5G; 4312 break; 4313 4314 case IXGBE_LINK_SPEED_10GB_FULL: 4315 link.link_speed = RTE_ETH_SPEED_NUM_10G; 4316 break; 4317 } 4318 4319 return rte_eth_linkstatus_set(dev, &link); 4320 } 4321 4322 static int 4323 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4324 { 4325 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0); 4326 } 4327 4328 static int 4329 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4330 { 4331 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1); 4332 } 4333 4334 static int 4335 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 4336 { 4337 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4338 uint32_t fctrl; 4339 4340 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4341 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4342 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4343 4344 return 0; 4345 } 4346 4347 static int 4348 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 4349 { 4350 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4351 uint32_t fctrl; 4352 4353 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4354 fctrl &= (~IXGBE_FCTRL_UPE); 4355 if (dev->data->all_multicast == 1) 4356 fctrl |= IXGBE_FCTRL_MPE; 4357 else 4358 fctrl &= (~IXGBE_FCTRL_MPE); 4359 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4360 4361 return 0; 4362 } 4363 4364 static int 4365 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 4366 { 4367 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4368 uint32_t fctrl; 4369 4370 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4371 fctrl |= IXGBE_FCTRL_MPE; 4372 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4373 4374 return 0; 4375 } 4376 4377 static int 4378 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 4379 { 4380 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4381 uint32_t fctrl; 4382 4383 if (dev->data->promiscuous == 1) 4384 return 0; /* must remain in all_multicast mode */ 4385 4386 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4387 fctrl &= (~IXGBE_FCTRL_MPE); 4388 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4389 4390 return 0; 4391 } 4392 4393 /** 4394 * It clears the interrupt causes and enables the interrupt. 4395 * It will be called once only during nic initialized. 4396 * 4397 * @param dev 4398 * Pointer to struct rte_eth_dev. 4399 * @param on 4400 * Enable or Disable. 4401 * 4402 * @return 4403 * - On success, zero. 4404 * - On failure, a negative value. 4405 */ 4406 static int 4407 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 4408 { 4409 struct ixgbe_interrupt *intr = 4410 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4411 4412 ixgbe_dev_link_status_print(dev); 4413 if (on) 4414 intr->mask |= IXGBE_EICR_LSC; 4415 else 4416 intr->mask &= ~IXGBE_EICR_LSC; 4417 4418 return 0; 4419 } 4420 4421 /** 4422 * It clears the interrupt causes and enables the interrupt. 4423 * It will be called once only during nic initialized. 4424 * 4425 * @param dev 4426 * Pointer to struct rte_eth_dev. 4427 * 4428 * @return 4429 * - On success, zero. 4430 * - On failure, a negative value. 4431 */ 4432 static int 4433 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev) 4434 { 4435 struct ixgbe_interrupt *intr = 4436 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4437 4438 intr->mask |= IXGBE_EICR_RTX_QUEUE; 4439 4440 return 0; 4441 } 4442 4443 /** 4444 * It clears the interrupt causes and enables the interrupt. 4445 * It will be called once only during nic initialized. 4446 * 4447 * @param dev 4448 * Pointer to struct rte_eth_dev. 4449 * 4450 * @return 4451 * - On success, zero. 4452 * - On failure, a negative value. 4453 */ 4454 static int 4455 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev) 4456 { 4457 struct ixgbe_interrupt *intr = 4458 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4459 4460 intr->mask |= IXGBE_EICR_LINKSEC; 4461 4462 return 0; 4463 } 4464 4465 /* 4466 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update. 4467 * 4468 * @param dev 4469 * Pointer to struct rte_eth_dev. 4470 * 4471 * @return 4472 * - On success, zero. 4473 * - On failure, a negative value. 4474 */ 4475 static int 4476 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev) 4477 { 4478 uint32_t eicr; 4479 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4480 struct ixgbe_interrupt *intr = 4481 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4482 4483 /* clear all cause mask */ 4484 ixgbe_disable_intr(hw); 4485 4486 /* read-on-clear nic registers here */ 4487 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4488 PMD_DRV_LOG(DEBUG, "eicr %x", eicr); 4489 4490 intr->flags = 0; 4491 4492 /* set flag for async link update */ 4493 if (eicr & IXGBE_EICR_LSC) 4494 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 4495 4496 if (eicr & IXGBE_EICR_MAILBOX) 4497 intr->flags |= IXGBE_FLAG_MAILBOX; 4498 4499 if (eicr & IXGBE_EICR_LINKSEC) 4500 intr->flags |= IXGBE_FLAG_MACSEC; 4501 4502 if (hw->mac.type == ixgbe_mac_X550EM_x && 4503 hw->phy.type == ixgbe_phy_x550em_ext_t && 4504 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x)) 4505 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT; 4506 4507 return 0; 4508 } 4509 4510 /** 4511 * It gets and then prints the link status. 4512 * 4513 * @param dev 4514 * Pointer to struct rte_eth_dev. 4515 * 4516 * @return 4517 * - On success, zero. 4518 * - On failure, a negative value. 4519 */ 4520 static void 4521 ixgbe_dev_link_status_print(struct rte_eth_dev *dev) 4522 { 4523 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4524 struct rte_eth_link link; 4525 4526 rte_eth_linkstatus_get(dev, &link); 4527 4528 if (link.link_status) { 4529 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", 4530 (int)(dev->data->port_id), 4531 (unsigned)link.link_speed, 4532 link.link_duplex == RTE_ETH_LINK_FULL_DUPLEX ? 4533 "full-duplex" : "half-duplex"); 4534 } else { 4535 PMD_INIT_LOG(INFO, " Port %d: Link Down", 4536 (int)(dev->data->port_id)); 4537 } 4538 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 4539 pci_dev->addr.domain, 4540 pci_dev->addr.bus, 4541 pci_dev->addr.devid, 4542 pci_dev->addr.function); 4543 } 4544 4545 /* 4546 * It executes link_update after knowing an interrupt occurred. 4547 * 4548 * @param dev 4549 * Pointer to struct rte_eth_dev. 4550 * 4551 * @return 4552 * - On success, zero. 4553 * - On failure, a negative value. 4554 */ 4555 static int 4556 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev) 4557 { 4558 struct ixgbe_interrupt *intr = 4559 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4560 int64_t timeout; 4561 struct ixgbe_hw *hw = 4562 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4563 4564 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags); 4565 4566 if (intr->flags & IXGBE_FLAG_MAILBOX) { 4567 ixgbe_pf_mbx_process(dev); 4568 intr->flags &= ~IXGBE_FLAG_MAILBOX; 4569 } 4570 4571 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4572 ixgbe_handle_lasi(hw); 4573 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4574 } 4575 4576 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4577 struct rte_eth_link link; 4578 4579 /* get the link status before link update, for predicting later */ 4580 rte_eth_linkstatus_get(dev, &link); 4581 4582 ixgbe_dev_link_update(dev, 0); 4583 4584 /* likely to up */ 4585 if (!link.link_status) 4586 /* handle it 1 sec later, wait it being stable */ 4587 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT; 4588 /* likely to down */ 4589 else 4590 /* handle it 4 sec later, wait it being stable */ 4591 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT; 4592 4593 ixgbe_dev_link_status_print(dev); 4594 if (rte_eal_alarm_set(timeout * 1000, 4595 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0) 4596 PMD_DRV_LOG(ERR, "Error setting alarm"); 4597 else { 4598 /* remember original mask */ 4599 intr->mask_original = intr->mask; 4600 /* only disable lsc interrupt */ 4601 intr->mask &= ~IXGBE_EIMS_LSC; 4602 } 4603 } 4604 4605 PMD_DRV_LOG(DEBUG, "enable intr immediately"); 4606 ixgbe_enable_intr(dev); 4607 4608 return 0; 4609 } 4610 4611 /** 4612 * Interrupt handler which shall be registered for alarm callback for delayed 4613 * handling specific interrupt to wait for the stable nic state. As the 4614 * NIC interrupt state is not stable for ixgbe after link is just down, 4615 * it needs to wait 4 seconds to get the stable status. 4616 * 4617 * @param handle 4618 * Pointer to interrupt handle. 4619 * @param param 4620 * The address of parameter (struct rte_eth_dev *) registered before. 4621 * 4622 * @return 4623 * void 4624 */ 4625 static void 4626 ixgbe_dev_interrupt_delayed_handler(void *param) 4627 { 4628 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4629 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4630 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 4631 struct ixgbe_interrupt *intr = 4632 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4633 struct ixgbe_hw *hw = 4634 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4635 uint32_t eicr; 4636 4637 ixgbe_disable_intr(hw); 4638 4639 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4640 if (eicr & IXGBE_EICR_MAILBOX) 4641 ixgbe_pf_mbx_process(dev); 4642 4643 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4644 ixgbe_handle_lasi(hw); 4645 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4646 } 4647 4648 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4649 ixgbe_dev_link_update(dev, 0); 4650 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 4651 ixgbe_dev_link_status_print(dev); 4652 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 4653 } 4654 4655 if (intr->flags & IXGBE_FLAG_MACSEC) { 4656 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL); 4657 intr->flags &= ~IXGBE_FLAG_MACSEC; 4658 } 4659 4660 /* restore original mask */ 4661 intr->mask = intr->mask_original; 4662 intr->mask_original = 0; 4663 4664 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr); 4665 ixgbe_enable_intr(dev); 4666 rte_intr_ack(intr_handle); 4667 } 4668 4669 /** 4670 * Interrupt handler triggered by NIC for handling 4671 * specific interrupt. 4672 * 4673 * @param handle 4674 * Pointer to interrupt handle. 4675 * @param param 4676 * The address of parameter (struct rte_eth_dev *) registered before. 4677 * 4678 * @return 4679 * void 4680 */ 4681 static void 4682 ixgbe_dev_interrupt_handler(void *param) 4683 { 4684 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4685 4686 ixgbe_dev_interrupt_get_status(dev); 4687 ixgbe_dev_interrupt_action(dev); 4688 } 4689 4690 static int 4691 ixgbe_dev_led_on(struct rte_eth_dev *dev) 4692 { 4693 struct ixgbe_hw *hw; 4694 4695 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4696 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4697 } 4698 4699 static int 4700 ixgbe_dev_led_off(struct rte_eth_dev *dev) 4701 { 4702 struct ixgbe_hw *hw; 4703 4704 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4705 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4706 } 4707 4708 static int 4709 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4710 { 4711 struct ixgbe_hw *hw; 4712 uint32_t mflcn_reg; 4713 uint32_t fccfg_reg; 4714 int rx_pause; 4715 int tx_pause; 4716 4717 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4718 4719 fc_conf->pause_time = hw->fc.pause_time; 4720 fc_conf->high_water = hw->fc.high_water[0]; 4721 fc_conf->low_water = hw->fc.low_water[0]; 4722 fc_conf->send_xon = hw->fc.send_xon; 4723 fc_conf->autoneg = !hw->fc.disable_fc_autoneg; 4724 4725 /* 4726 * Return rx_pause status according to actual setting of 4727 * MFLCN register. 4728 */ 4729 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4730 if (mflcn_reg & IXGBE_MFLCN_PMCF) 4731 fc_conf->mac_ctrl_frame_fwd = 1; 4732 else 4733 fc_conf->mac_ctrl_frame_fwd = 0; 4734 4735 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE)) 4736 rx_pause = 1; 4737 else 4738 rx_pause = 0; 4739 4740 /* 4741 * Return tx_pause status according to actual setting of 4742 * FCCFG register. 4743 */ 4744 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4745 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY)) 4746 tx_pause = 1; 4747 else 4748 tx_pause = 0; 4749 4750 if (rx_pause && tx_pause) 4751 fc_conf->mode = RTE_ETH_FC_FULL; 4752 else if (rx_pause) 4753 fc_conf->mode = RTE_ETH_FC_RX_PAUSE; 4754 else if (tx_pause) 4755 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 4756 else 4757 fc_conf->mode = RTE_ETH_FC_NONE; 4758 4759 return 0; 4760 } 4761 4762 static int 4763 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4764 { 4765 struct ixgbe_hw *hw; 4766 struct ixgbe_adapter *adapter = dev->data->dev_private; 4767 int err; 4768 uint32_t rx_buf_size; 4769 uint32_t max_high_water; 4770 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4771 ixgbe_fc_none, 4772 ixgbe_fc_rx_pause, 4773 ixgbe_fc_tx_pause, 4774 ixgbe_fc_full 4775 }; 4776 4777 PMD_INIT_FUNC_TRACE(); 4778 4779 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4780 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)); 4781 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4782 4783 /* 4784 * At least reserve one Ethernet frame for watermark 4785 * high_water/low_water in kilo bytes for ixgbe 4786 */ 4787 max_high_water = (rx_buf_size - 4788 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4789 if ((fc_conf->high_water > max_high_water) || 4790 (fc_conf->high_water < fc_conf->low_water)) { 4791 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4792 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4793 return -EINVAL; 4794 } 4795 4796 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode]; 4797 hw->fc.pause_time = fc_conf->pause_time; 4798 hw->fc.high_water[0] = fc_conf->high_water; 4799 hw->fc.low_water[0] = fc_conf->low_water; 4800 hw->fc.send_xon = fc_conf->send_xon; 4801 hw->fc.disable_fc_autoneg = !fc_conf->autoneg; 4802 adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; 4803 4804 err = ixgbe_flow_ctrl_enable(dev, hw); 4805 if (err < 0) { 4806 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err); 4807 return -EIO; 4808 } 4809 return err; 4810 } 4811 4812 /** 4813 * ixgbe_pfc_enable_generic - Enable flow control 4814 * @hw: pointer to hardware structure 4815 * @tc_num: traffic class number 4816 * Enable flow control according to the current settings. 4817 */ 4818 static int 4819 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num) 4820 { 4821 int ret_val = 0; 4822 uint32_t mflcn_reg, fccfg_reg; 4823 uint32_t reg; 4824 uint32_t fcrtl, fcrth; 4825 uint8_t i; 4826 uint8_t nb_rx_en; 4827 4828 /* Validate the water mark configuration */ 4829 if (!hw->fc.pause_time) { 4830 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4831 goto out; 4832 } 4833 4834 /* Low water mark of zero causes XOFF floods */ 4835 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 4836 /* High/Low water can not be 0 */ 4837 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) { 4838 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4839 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4840 goto out; 4841 } 4842 4843 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) { 4844 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4845 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4846 goto out; 4847 } 4848 } 4849 /* Negotiate the fc mode to use */ 4850 ixgbe_fc_autoneg(hw); 4851 4852 /* Disable any previous flow control settings */ 4853 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4854 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE); 4855 4856 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4857 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 4858 4859 switch (hw->fc.current_mode) { 4860 case ixgbe_fc_none: 4861 /* 4862 * If the count of enabled RX Priority Flow control >1, 4863 * and the TX pause can not be disabled 4864 */ 4865 nb_rx_en = 0; 4866 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4867 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4868 if (reg & IXGBE_FCRTH_FCEN) 4869 nb_rx_en++; 4870 } 4871 if (nb_rx_en > 1) 4872 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4873 break; 4874 case ixgbe_fc_rx_pause: 4875 /* 4876 * Rx Flow control is enabled and Tx Flow control is 4877 * disabled by software override. Since there really 4878 * isn't a way to advertise that we are capable of RX 4879 * Pause ONLY, we will advertise that we support both 4880 * symmetric and asymmetric Rx PAUSE. Later, we will 4881 * disable the adapter's ability to send PAUSE frames. 4882 */ 4883 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4884 /* 4885 * If the count of enabled RX Priority Flow control >1, 4886 * and the TX pause can not be disabled 4887 */ 4888 nb_rx_en = 0; 4889 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4890 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4891 if (reg & IXGBE_FCRTH_FCEN) 4892 nb_rx_en++; 4893 } 4894 if (nb_rx_en > 1) 4895 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4896 break; 4897 case ixgbe_fc_tx_pause: 4898 /* 4899 * Tx Flow control is enabled, and Rx Flow control is 4900 * disabled by software override. 4901 */ 4902 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4903 break; 4904 case ixgbe_fc_full: 4905 /* Flow control (both Rx and Tx) is enabled by SW override. */ 4906 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4907 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4908 break; 4909 default: 4910 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly"); 4911 ret_val = IXGBE_ERR_CONFIG; 4912 goto out; 4913 } 4914 4915 /* Set 802.3x based flow control settings. */ 4916 mflcn_reg |= IXGBE_MFLCN_DPF; 4917 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 4918 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 4919 4920 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 4921 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 4922 hw->fc.high_water[tc_num]) { 4923 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE; 4924 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl); 4925 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN; 4926 } else { 4927 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0); 4928 /* 4929 * In order to prevent Tx hangs when the internal Tx 4930 * switch is enabled we must set the high water mark 4931 * to the maximum FCRTH value. This allows the Tx 4932 * switch to function even under heavy Rx workloads. 4933 */ 4934 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32; 4935 } 4936 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth); 4937 4938 /* Configure pause time (2 TCs per register) */ 4939 reg = hw->fc.pause_time * 0x00010001; 4940 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 4941 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 4942 4943 /* Configure flow control refresh threshold value */ 4944 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 4945 4946 out: 4947 return ret_val; 4948 } 4949 4950 static int 4951 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num) 4952 { 4953 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4954 int32_t ret_val = IXGBE_NOT_IMPLEMENTED; 4955 4956 if (hw->mac.type != ixgbe_mac_82598EB) { 4957 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num); 4958 } 4959 return ret_val; 4960 } 4961 4962 static int 4963 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf) 4964 { 4965 int err; 4966 uint32_t rx_buf_size; 4967 uint32_t max_high_water; 4968 uint8_t tc_num; 4969 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 4970 struct ixgbe_hw *hw = 4971 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4972 struct ixgbe_dcb_config *dcb_config = 4973 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 4974 4975 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4976 ixgbe_fc_none, 4977 ixgbe_fc_rx_pause, 4978 ixgbe_fc_tx_pause, 4979 ixgbe_fc_full 4980 }; 4981 4982 PMD_INIT_FUNC_TRACE(); 4983 4984 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map); 4985 tc_num = map[pfc_conf->priority]; 4986 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)); 4987 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4988 /* 4989 * At least reserve one Ethernet frame for watermark 4990 * high_water/low_water in kilo bytes for ixgbe 4991 */ 4992 max_high_water = (rx_buf_size - 4993 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4994 if ((pfc_conf->fc.high_water > max_high_water) || 4995 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) { 4996 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4997 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4998 return -EINVAL; 4999 } 5000 5001 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode]; 5002 hw->fc.pause_time = pfc_conf->fc.pause_time; 5003 hw->fc.send_xon = pfc_conf->fc.send_xon; 5004 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water; 5005 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; 5006 5007 err = ixgbe_dcb_pfc_enable(dev, tc_num); 5008 5009 /* Not negotiated is not an error case */ 5010 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) 5011 return 0; 5012 5013 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err); 5014 return -EIO; 5015 } 5016 5017 static int 5018 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 5019 struct rte_eth_rss_reta_entry64 *reta_conf, 5020 uint16_t reta_size) 5021 { 5022 uint16_t i, sp_reta_size; 5023 uint8_t j, mask; 5024 uint32_t reta, r; 5025 uint16_t idx, shift; 5026 struct ixgbe_adapter *adapter = dev->data->dev_private; 5027 struct rte_eth_dev_data *dev_data = dev->data; 5028 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5029 uint32_t reta_reg; 5030 5031 PMD_INIT_FUNC_TRACE(); 5032 5033 if (!dev_data->dev_started) { 5034 PMD_DRV_LOG(ERR, 5035 "port %d must be started before rss reta update", 5036 dev_data->port_id); 5037 return -EIO; 5038 } 5039 5040 if (!ixgbe_rss_update_sp(hw->mac.type)) { 5041 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " 5042 "NIC."); 5043 return -ENOTSUP; 5044 } 5045 5046 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 5047 if (reta_size != sp_reta_size) { 5048 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 5049 "(%d) doesn't match the number hardware can supported " 5050 "(%d)", reta_size, sp_reta_size); 5051 return -EINVAL; 5052 } 5053 5054 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 5055 idx = i / RTE_ETH_RETA_GROUP_SIZE; 5056 shift = i % RTE_ETH_RETA_GROUP_SIZE; 5057 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 5058 IXGBE_4_BIT_MASK); 5059 if (!mask) 5060 continue; 5061 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 5062 if (mask == IXGBE_4_BIT_MASK) 5063 r = 0; 5064 else 5065 r = IXGBE_READ_REG(hw, reta_reg); 5066 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) { 5067 if (mask & (0x1 << j)) 5068 reta |= reta_conf[idx].reta[shift + j] << 5069 (CHAR_BIT * j); 5070 else 5071 reta |= r & (IXGBE_8_BIT_MASK << 5072 (CHAR_BIT * j)); 5073 } 5074 IXGBE_WRITE_REG(hw, reta_reg, reta); 5075 } 5076 adapter->rss_reta_updated = 1; 5077 5078 return 0; 5079 } 5080 5081 static int 5082 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 5083 struct rte_eth_rss_reta_entry64 *reta_conf, 5084 uint16_t reta_size) 5085 { 5086 uint16_t i, sp_reta_size; 5087 uint8_t j, mask; 5088 uint32_t reta; 5089 uint16_t idx, shift; 5090 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5091 uint32_t reta_reg; 5092 5093 PMD_INIT_FUNC_TRACE(); 5094 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 5095 if (reta_size != sp_reta_size) { 5096 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 5097 "(%d) doesn't match the number hardware can supported " 5098 "(%d)", reta_size, sp_reta_size); 5099 return -EINVAL; 5100 } 5101 5102 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 5103 idx = i / RTE_ETH_RETA_GROUP_SIZE; 5104 shift = i % RTE_ETH_RETA_GROUP_SIZE; 5105 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 5106 IXGBE_4_BIT_MASK); 5107 if (!mask) 5108 continue; 5109 5110 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 5111 reta = IXGBE_READ_REG(hw, reta_reg); 5112 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) { 5113 if (mask & (0x1 << j)) 5114 reta_conf[idx].reta[shift + j] = 5115 ((reta >> (CHAR_BIT * j)) & 5116 IXGBE_8_BIT_MASK); 5117 } 5118 } 5119 5120 return 0; 5121 } 5122 5123 static int 5124 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 5125 uint32_t index, uint32_t pool) 5126 { 5127 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5128 uint32_t enable_addr = 1; 5129 5130 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes, 5131 pool, enable_addr); 5132 } 5133 5134 static void 5135 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) 5136 { 5137 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5138 5139 ixgbe_clear_rar(hw, index); 5140 } 5141 5142 static int 5143 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 5144 { 5145 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5146 5147 ixgbe_remove_rar(dev, 0); 5148 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs); 5149 5150 return 0; 5151 } 5152 5153 static bool 5154 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 5155 { 5156 if (strcmp(dev->device->driver->name, drv->driver.name)) 5157 return false; 5158 5159 return true; 5160 } 5161 5162 bool 5163 is_ixgbe_supported(struct rte_eth_dev *dev) 5164 { 5165 return is_device_supported(dev, &rte_ixgbe_pmd); 5166 } 5167 5168 static int 5169 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 5170 { 5171 uint32_t hlreg0; 5172 uint32_t maxfrs; 5173 struct ixgbe_hw *hw; 5174 struct rte_eth_dev_info dev_info; 5175 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD; 5176 int ret; 5177 5178 ret = ixgbe_dev_info_get(dev, &dev_info); 5179 if (ret != 0) 5180 return ret; 5181 5182 /* check that mtu is within the allowed range */ 5183 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) 5184 return -EINVAL; 5185 5186 /* If device is started, refuse mtu that requires the support of 5187 * scattered packets when this feature has not been enabled before. 5188 */ 5189 if (dev->data->dev_started && !dev->data->scattered_rx && 5190 frame_size + 2 * RTE_VLAN_HLEN > 5191 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) { 5192 PMD_INIT_LOG(ERR, "Stop port first."); 5193 return -EINVAL; 5194 } 5195 5196 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5197 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 5198 5199 /* switch to jumbo mode if needed */ 5200 if (mtu > RTE_ETHER_MTU) 5201 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 5202 else 5203 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; 5204 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 5205 5206 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS); 5207 maxfrs &= 0x0000FFFF; 5208 maxfrs |= (frame_size << 16); 5209 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs); 5210 5211 return 0; 5212 } 5213 5214 /* 5215 * Virtual Function operations 5216 */ 5217 static void 5218 ixgbevf_intr_disable(struct rte_eth_dev *dev) 5219 { 5220 struct ixgbe_interrupt *intr = 5221 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5222 struct ixgbe_hw *hw = 5223 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5224 5225 PMD_INIT_FUNC_TRACE(); 5226 5227 /* Clear interrupt mask to stop from interrupts being generated */ 5228 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK); 5229 5230 IXGBE_WRITE_FLUSH(hw); 5231 5232 /* Clear mask value. */ 5233 intr->mask = 0; 5234 } 5235 5236 static void 5237 ixgbevf_intr_enable(struct rte_eth_dev *dev) 5238 { 5239 struct ixgbe_interrupt *intr = 5240 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5241 struct ixgbe_hw *hw = 5242 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5243 5244 PMD_INIT_FUNC_TRACE(); 5245 5246 /* VF enable interrupt autoclean */ 5247 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK); 5248 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK); 5249 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK); 5250 5251 IXGBE_WRITE_FLUSH(hw); 5252 5253 /* Save IXGBE_VTEIMS value to mask. */ 5254 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK; 5255 } 5256 5257 static int 5258 ixgbevf_dev_configure(struct rte_eth_dev *dev) 5259 { 5260 struct rte_eth_conf *conf = &dev->data->dev_conf; 5261 struct ixgbe_adapter *adapter = dev->data->dev_private; 5262 5263 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d", 5264 dev->data->port_id); 5265 5266 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 5267 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; 5268 5269 /* 5270 * VF has no ability to enable/disable HW CRC 5271 * Keep the persistent behavior the same as Host PF 5272 */ 5273 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC 5274 if (conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) { 5275 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip"); 5276 conf->rxmode.offloads &= ~RTE_ETH_RX_OFFLOAD_KEEP_CRC; 5277 } 5278 #else 5279 if (!(conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)) { 5280 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip"); 5281 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_KEEP_CRC; 5282 } 5283 #endif 5284 5285 /* 5286 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 5287 * allocation or vector Rx preconditions we will reset it. 5288 */ 5289 adapter->rx_bulk_alloc_allowed = true; 5290 adapter->rx_vec_allowed = true; 5291 5292 return 0; 5293 } 5294 5295 static int 5296 ixgbevf_dev_start(struct rte_eth_dev *dev) 5297 { 5298 struct ixgbe_hw *hw = 5299 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5300 uint32_t intr_vector = 0; 5301 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5302 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 5303 5304 int err, mask = 0; 5305 5306 PMD_INIT_FUNC_TRACE(); 5307 5308 /* Stop the link setup handler before resetting the HW. */ 5309 ixgbe_dev_wait_setup_link_complete(dev, 0); 5310 5311 err = hw->mac.ops.reset_hw(hw); 5312 5313 /** 5314 * In this case, reuses the MAC address assigned by VF 5315 * initialization. 5316 */ 5317 if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) { 5318 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err); 5319 return err; 5320 } 5321 5322 hw->mac.get_link_status = true; 5323 5324 /* negotiate mailbox API version to use with the PF. */ 5325 ixgbevf_negotiate_api(hw); 5326 5327 ixgbevf_dev_tx_init(dev); 5328 5329 /* This can fail when allocating mbufs for descriptor rings */ 5330 err = ixgbevf_dev_rx_init(dev); 5331 if (err) { 5332 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err); 5333 ixgbe_dev_clear_queues(dev); 5334 return err; 5335 } 5336 5337 /* Set vfta */ 5338 ixgbevf_set_vfta_all(dev, 1); 5339 5340 /* Set HW strip */ 5341 mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK | 5342 RTE_ETH_VLAN_EXTEND_MASK; 5343 err = ixgbevf_vlan_offload_config(dev, mask); 5344 if (err) { 5345 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err); 5346 ixgbe_dev_clear_queues(dev); 5347 return err; 5348 } 5349 5350 ixgbevf_dev_rxtx_start(dev); 5351 5352 /* check and configure queue intr-vector mapping */ 5353 if (rte_intr_cap_multiple(intr_handle) && 5354 dev->data->dev_conf.intr_conf.rxq) { 5355 /* According to datasheet, only vector 0/1/2 can be used, 5356 * now only one vector is used for Rx queue 5357 */ 5358 intr_vector = 1; 5359 if (rte_intr_efd_enable(intr_handle, intr_vector)) { 5360 ixgbe_dev_clear_queues(dev); 5361 return -1; 5362 } 5363 } 5364 5365 if (rte_intr_dp_is_en(intr_handle)) { 5366 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec", 5367 dev->data->nb_rx_queues)) { 5368 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 5369 " intr_vec", dev->data->nb_rx_queues); 5370 ixgbe_dev_clear_queues(dev); 5371 return -ENOMEM; 5372 } 5373 } 5374 ixgbevf_configure_msix(dev); 5375 5376 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt 5377 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ). 5378 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( ) 5379 * is not cleared, it will fail when following rte_intr_enable( ) tries 5380 * to map Rx queue interrupt to other VFIO vectors. 5381 * So clear uio/vfio intr/evevnfd first to avoid failure. 5382 */ 5383 rte_intr_disable(intr_handle); 5384 5385 rte_intr_enable(intr_handle); 5386 5387 /* Re-enable interrupt for VF */ 5388 ixgbevf_intr_enable(dev); 5389 5390 /* 5391 * Update link status right before return, because it may 5392 * start link configuration process in a separate thread. 5393 */ 5394 ixgbevf_dev_link_update(dev, 0); 5395 5396 hw->adapter_stopped = false; 5397 5398 return 0; 5399 } 5400 5401 static int 5402 ixgbevf_dev_stop(struct rte_eth_dev *dev) 5403 { 5404 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5405 struct ixgbe_adapter *adapter = dev->data->dev_private; 5406 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5407 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 5408 5409 if (hw->adapter_stopped) 5410 return 0; 5411 5412 PMD_INIT_FUNC_TRACE(); 5413 5414 ixgbe_dev_wait_setup_link_complete(dev, 0); 5415 5416 ixgbevf_intr_disable(dev); 5417 5418 dev->data->dev_started = 0; 5419 hw->adapter_stopped = 1; 5420 ixgbe_stop_adapter(hw); 5421 5422 /* 5423 * Clear what we set, but we still keep shadow_vfta to 5424 * restore after device starts 5425 */ 5426 ixgbevf_set_vfta_all(dev, 0); 5427 5428 /* Clear stored conf */ 5429 dev->data->scattered_rx = 0; 5430 5431 ixgbe_dev_clear_queues(dev); 5432 5433 /* Clean datapath event and queue/vec mapping */ 5434 rte_intr_efd_disable(intr_handle); 5435 rte_intr_vec_list_free(intr_handle); 5436 5437 adapter->rss_reta_updated = 0; 5438 5439 return 0; 5440 } 5441 5442 static int 5443 ixgbevf_dev_close(struct rte_eth_dev *dev) 5444 { 5445 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5446 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5447 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 5448 int ret; 5449 5450 PMD_INIT_FUNC_TRACE(); 5451 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5452 return 0; 5453 5454 ixgbe_reset_hw(hw); 5455 5456 ret = ixgbevf_dev_stop(dev); 5457 5458 ixgbe_dev_free_queues(dev); 5459 5460 /** 5461 * Remove the VF MAC address ro ensure 5462 * that the VF traffic goes to the PF 5463 * after stop, close and detach of the VF 5464 **/ 5465 ixgbevf_remove_mac_addr(dev, 0); 5466 5467 rte_intr_disable(intr_handle); 5468 rte_intr_callback_unregister(intr_handle, 5469 ixgbevf_dev_interrupt_handler, dev); 5470 5471 return ret; 5472 } 5473 5474 /* 5475 * Reset VF device 5476 */ 5477 static int 5478 ixgbevf_dev_reset(struct rte_eth_dev *dev) 5479 { 5480 int ret; 5481 5482 ret = eth_ixgbevf_dev_uninit(dev); 5483 if (ret) 5484 return ret; 5485 5486 ret = eth_ixgbevf_dev_init(dev); 5487 5488 return ret; 5489 } 5490 5491 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) 5492 { 5493 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5494 struct ixgbe_vfta *shadow_vfta = 5495 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5496 int i = 0, j = 0, vfta = 0, mask = 1; 5497 5498 for (i = 0; i < IXGBE_VFTA_SIZE; i++) { 5499 vfta = shadow_vfta->vfta[i]; 5500 if (vfta) { 5501 mask = 1; 5502 for (j = 0; j < 32; j++) { 5503 if (vfta & mask) 5504 ixgbe_set_vfta(hw, (i<<5)+j, 0, 5505 on, false); 5506 mask <<= 1; 5507 } 5508 } 5509 } 5510 5511 } 5512 5513 static int 5514 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 5515 { 5516 struct ixgbe_hw *hw = 5517 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5518 struct ixgbe_vfta *shadow_vfta = 5519 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5520 uint32_t vid_idx = 0; 5521 uint32_t vid_bit = 0; 5522 int ret = 0; 5523 5524 PMD_INIT_FUNC_TRACE(); 5525 5526 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */ 5527 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false); 5528 if (ret) { 5529 PMD_INIT_LOG(ERR, "Unable to set VF vlan"); 5530 return ret; 5531 } 5532 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 5533 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 5534 5535 /* Save what we set and retore it after device reset */ 5536 if (on) 5537 shadow_vfta->vfta[vid_idx] |= vid_bit; 5538 else 5539 shadow_vfta->vfta[vid_idx] &= ~vid_bit; 5540 5541 return 0; 5542 } 5543 5544 static void 5545 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 5546 { 5547 struct ixgbe_hw *hw = 5548 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5549 uint32_t ctrl; 5550 5551 PMD_INIT_FUNC_TRACE(); 5552 5553 if (queue >= hw->mac.max_rx_queues) 5554 return; 5555 5556 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 5557 if (on) 5558 ctrl |= IXGBE_RXDCTL_VME; 5559 else 5560 ctrl &= ~IXGBE_RXDCTL_VME; 5561 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 5562 5563 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on); 5564 } 5565 5566 static int 5567 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask) 5568 { 5569 struct ixgbe_rx_queue *rxq; 5570 uint16_t i; 5571 int on = 0; 5572 5573 /* VF function only support hw strip feature, others are not support */ 5574 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 5575 for (i = 0; i < dev->data->nb_rx_queues; i++) { 5576 rxq = dev->data->rx_queues[i]; 5577 on = !!(rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP); 5578 ixgbevf_vlan_strip_queue_set(dev, i, on); 5579 } 5580 } 5581 5582 return 0; 5583 } 5584 5585 static int 5586 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 5587 { 5588 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 5589 5590 ixgbevf_vlan_offload_config(dev, mask); 5591 5592 return 0; 5593 } 5594 5595 int 5596 ixgbe_vt_check(struct ixgbe_hw *hw) 5597 { 5598 uint32_t reg_val; 5599 5600 /* if Virtualization Technology is enabled */ 5601 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 5602 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) { 5603 PMD_INIT_LOG(ERR, "VT must be enabled for this setting"); 5604 return -1; 5605 } 5606 5607 return 0; 5608 } 5609 5610 static uint32_t 5611 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr) 5612 { 5613 uint32_t vector = 0; 5614 5615 switch (hw->mac.mc_filter_type) { 5616 case 0: /* use bits [47:36] of the address */ 5617 vector = ((uc_addr->addr_bytes[4] >> 4) | 5618 (((uint16_t)uc_addr->addr_bytes[5]) << 4)); 5619 break; 5620 case 1: /* use bits [46:35] of the address */ 5621 vector = ((uc_addr->addr_bytes[4] >> 3) | 5622 (((uint16_t)uc_addr->addr_bytes[5]) << 5)); 5623 break; 5624 case 2: /* use bits [45:34] of the address */ 5625 vector = ((uc_addr->addr_bytes[4] >> 2) | 5626 (((uint16_t)uc_addr->addr_bytes[5]) << 6)); 5627 break; 5628 case 3: /* use bits [43:32] of the address */ 5629 vector = ((uc_addr->addr_bytes[4]) | 5630 (((uint16_t)uc_addr->addr_bytes[5]) << 8)); 5631 break; 5632 default: /* Invalid mc_filter_type */ 5633 break; 5634 } 5635 5636 /* vector can only be 12-bits or boundary will be exceeded */ 5637 vector &= 0xFFF; 5638 return vector; 5639 } 5640 5641 static int 5642 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, 5643 struct rte_ether_addr *mac_addr, uint8_t on) 5644 { 5645 uint32_t vector; 5646 uint32_t uta_idx; 5647 uint32_t reg_val; 5648 uint32_t uta_shift; 5649 uint32_t rc; 5650 const uint32_t ixgbe_uta_idx_mask = 0x7F; 5651 const uint32_t ixgbe_uta_bit_shift = 5; 5652 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1; 5653 const uint32_t bit1 = 0x1; 5654 5655 struct ixgbe_hw *hw = 5656 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5657 struct ixgbe_uta_info *uta_info = 5658 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5659 5660 /* The UTA table only exists on 82599 hardware and newer */ 5661 if (hw->mac.type < ixgbe_mac_82599EB) 5662 return -ENOTSUP; 5663 5664 vector = ixgbe_uta_vector(hw, mac_addr); 5665 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask; 5666 uta_shift = vector & ixgbe_uta_bit_mask; 5667 5668 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0); 5669 if (rc == on) 5670 return 0; 5671 5672 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx)); 5673 if (on) { 5674 uta_info->uta_in_use++; 5675 reg_val |= (bit1 << uta_shift); 5676 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift); 5677 } else { 5678 uta_info->uta_in_use--; 5679 reg_val &= ~(bit1 << uta_shift); 5680 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift); 5681 } 5682 5683 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val); 5684 5685 if (uta_info->uta_in_use > 0) 5686 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 5687 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 5688 else 5689 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 5690 5691 return 0; 5692 } 5693 5694 static int 5695 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) 5696 { 5697 int i; 5698 struct ixgbe_hw *hw = 5699 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5700 struct ixgbe_uta_info *uta_info = 5701 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5702 5703 /* The UTA table only exists on 82599 hardware and newer */ 5704 if (hw->mac.type < ixgbe_mac_82599EB) 5705 return -ENOTSUP; 5706 5707 if (on) { 5708 for (i = 0; i < RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5709 uta_info->uta_shadow[i] = ~0; 5710 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); 5711 } 5712 } else { 5713 for (i = 0; i < RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5714 uta_info->uta_shadow[i] = 0; 5715 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 5716 } 5717 } 5718 return 0; 5719 5720 } 5721 5722 uint32_t 5723 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val) 5724 { 5725 uint32_t new_val = orig_val; 5726 5727 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_UNTAG) 5728 new_val |= IXGBE_VMOLR_AUPE; 5729 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_HASH_MC) 5730 new_val |= IXGBE_VMOLR_ROMPE; 5731 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_HASH_UC) 5732 new_val |= IXGBE_VMOLR_ROPE; 5733 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_BROADCAST) 5734 new_val |= IXGBE_VMOLR_BAM; 5735 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_MULTICAST) 5736 new_val |= IXGBE_VMOLR_MPE; 5737 5738 return new_val; 5739 } 5740 5741 static int 5742 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5743 { 5744 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5745 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 5746 struct ixgbe_interrupt *intr = 5747 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5748 struct ixgbe_hw *hw = 5749 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5750 uint32_t vec = IXGBE_MISC_VEC_ID; 5751 5752 if (rte_intr_allow_others(intr_handle)) 5753 vec = IXGBE_RX_VEC_START; 5754 intr->mask |= (1 << vec); 5755 RTE_SET_USED(queue_id); 5756 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5757 5758 rte_intr_ack(intr_handle); 5759 5760 return 0; 5761 } 5762 5763 static int 5764 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5765 { 5766 struct ixgbe_interrupt *intr = 5767 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5768 struct ixgbe_hw *hw = 5769 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5770 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5771 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 5772 uint32_t vec = IXGBE_MISC_VEC_ID; 5773 5774 if (rte_intr_allow_others(intr_handle)) 5775 vec = IXGBE_RX_VEC_START; 5776 intr->mask &= ~(1 << vec); 5777 RTE_SET_USED(queue_id); 5778 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5779 5780 return 0; 5781 } 5782 5783 static int 5784 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5785 { 5786 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5787 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 5788 uint32_t mask; 5789 struct ixgbe_hw *hw = 5790 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5791 struct ixgbe_interrupt *intr = 5792 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5793 5794 if (queue_id < 16) { 5795 ixgbe_disable_intr(hw); 5796 intr->mask |= (1 << queue_id); 5797 ixgbe_enable_intr(dev); 5798 } else if (queue_id < 32) { 5799 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5800 mask &= (1 << queue_id); 5801 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5802 } else if (queue_id < 64) { 5803 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5804 mask &= (1 << (queue_id - 32)); 5805 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5806 } 5807 rte_intr_ack(intr_handle); 5808 5809 return 0; 5810 } 5811 5812 static int 5813 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5814 { 5815 uint32_t mask; 5816 struct ixgbe_hw *hw = 5817 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5818 struct ixgbe_interrupt *intr = 5819 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5820 5821 if (queue_id < 16) { 5822 ixgbe_disable_intr(hw); 5823 intr->mask &= ~(1 << queue_id); 5824 ixgbe_enable_intr(dev); 5825 } else if (queue_id < 32) { 5826 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5827 mask &= ~(1 << queue_id); 5828 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5829 } else if (queue_id < 64) { 5830 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5831 mask &= ~(1 << (queue_id - 32)); 5832 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5833 } 5834 5835 return 0; 5836 } 5837 5838 static void 5839 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 5840 uint8_t queue, uint8_t msix_vector) 5841 { 5842 uint32_t tmp, idx; 5843 5844 if (direction == -1) { 5845 /* other causes */ 5846 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5847 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC); 5848 tmp &= ~0xFF; 5849 tmp |= msix_vector; 5850 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp); 5851 } else { 5852 /* rx or tx cause */ 5853 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5854 idx = ((16 * (queue & 1)) + (8 * direction)); 5855 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1)); 5856 tmp &= ~(0xFF << idx); 5857 tmp |= (msix_vector << idx); 5858 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp); 5859 } 5860 } 5861 5862 /** 5863 * set the IVAR registers, mapping interrupt causes to vectors 5864 * @param hw 5865 * pointer to ixgbe_hw struct 5866 * @direction 5867 * 0 for Rx, 1 for Tx, -1 for other causes 5868 * @queue 5869 * queue to map the corresponding interrupt to 5870 * @msix_vector 5871 * the vector to map to the corresponding queue 5872 */ 5873 static void 5874 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 5875 uint8_t queue, uint8_t msix_vector) 5876 { 5877 uint32_t tmp, idx; 5878 5879 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5880 if (hw->mac.type == ixgbe_mac_82598EB) { 5881 if (direction == -1) 5882 direction = 0; 5883 idx = (((direction * 64) + queue) >> 2) & 0x1F; 5884 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx)); 5885 tmp &= ~(0xFF << (8 * (queue & 0x3))); 5886 tmp |= (msix_vector << (8 * (queue & 0x3))); 5887 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp); 5888 } else if ((hw->mac.type == ixgbe_mac_82599EB) || 5889 (hw->mac.type == ixgbe_mac_X540) || 5890 (hw->mac.type == ixgbe_mac_X550) || 5891 (hw->mac.type == ixgbe_mac_X550EM_x)) { 5892 if (direction == -1) { 5893 /* other causes */ 5894 idx = ((queue & 1) * 8); 5895 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC); 5896 tmp &= ~(0xFF << idx); 5897 tmp |= (msix_vector << idx); 5898 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp); 5899 } else { 5900 /* rx or tx causes */ 5901 idx = ((16 * (queue & 1)) + (8 * direction)); 5902 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 5903 tmp &= ~(0xFF << idx); 5904 tmp |= (msix_vector << idx); 5905 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp); 5906 } 5907 } 5908 } 5909 5910 static void 5911 ixgbevf_configure_msix(struct rte_eth_dev *dev) 5912 { 5913 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5914 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 5915 struct ixgbe_hw *hw = 5916 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5917 uint32_t q_idx; 5918 uint32_t vector_idx = IXGBE_MISC_VEC_ID; 5919 uint32_t base = IXGBE_MISC_VEC_ID; 5920 5921 /* Configure VF other cause ivar */ 5922 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx); 5923 5924 /* won't configure msix register if no mapping is done 5925 * between intr vector and event fd. 5926 */ 5927 if (!rte_intr_dp_is_en(intr_handle)) 5928 return; 5929 5930 if (rte_intr_allow_others(intr_handle)) { 5931 base = IXGBE_RX_VEC_START; 5932 vector_idx = IXGBE_RX_VEC_START; 5933 } 5934 5935 /* Configure all RX queues of VF */ 5936 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) { 5937 /* Force all queue use vector 0, 5938 * as IXGBE_VF_MAXMSIVECTOR = 1 5939 */ 5940 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx); 5941 rte_intr_vec_list_index_set(intr_handle, q_idx, 5942 vector_idx); 5943 if (vector_idx < base + rte_intr_nb_efd_get(intr_handle) 5944 - 1) 5945 vector_idx++; 5946 } 5947 5948 /* As RX queue setting above show, all queues use the vector 0. 5949 * Set only the ITR value of IXGBE_MISC_VEC_ID. 5950 */ 5951 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID), 5952 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 5953 | IXGBE_EITR_CNT_WDIS); 5954 } 5955 5956 /** 5957 * Sets up the hardware to properly generate MSI-X interrupts 5958 * @hw 5959 * board private structure 5960 */ 5961 static void 5962 ixgbe_configure_msix(struct rte_eth_dev *dev) 5963 { 5964 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5965 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 5966 struct ixgbe_hw *hw = 5967 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5968 uint32_t queue_id, base = IXGBE_MISC_VEC_ID; 5969 uint32_t vec = IXGBE_MISC_VEC_ID; 5970 uint32_t mask; 5971 uint32_t gpie; 5972 5973 /* won't configure msix register if no mapping is done 5974 * between intr vector and event fd 5975 * but if misx has been enabled already, need to configure 5976 * auto clean, auto mask and throttling. 5977 */ 5978 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 5979 if (!rte_intr_dp_is_en(intr_handle) && 5980 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT))) 5981 return; 5982 5983 if (rte_intr_allow_others(intr_handle)) 5984 vec = base = IXGBE_RX_VEC_START; 5985 5986 /* setup GPIE for MSI-x mode */ 5987 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 5988 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5989 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME; 5990 /* auto clearing and auto setting corresponding bits in EIMS 5991 * when MSI-X interrupt is triggered 5992 */ 5993 if (hw->mac.type == ixgbe_mac_82598EB) { 5994 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5995 } else { 5996 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5997 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5998 } 5999 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 6000 6001 /* Populate the IVAR table and set the ITR values to the 6002 * corresponding register. 6003 */ 6004 if (rte_intr_dp_is_en(intr_handle)) { 6005 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; 6006 queue_id++) { 6007 /* by default, 1:1 mapping */ 6008 ixgbe_set_ivar_map(hw, 0, queue_id, vec); 6009 rte_intr_vec_list_index_set(intr_handle, 6010 queue_id, vec); 6011 if (vec < base + rte_intr_nb_efd_get(intr_handle) 6012 - 1) 6013 vec++; 6014 } 6015 6016 switch (hw->mac.type) { 6017 case ixgbe_mac_82598EB: 6018 ixgbe_set_ivar_map(hw, -1, 6019 IXGBE_IVAR_OTHER_CAUSES_INDEX, 6020 IXGBE_MISC_VEC_ID); 6021 break; 6022 case ixgbe_mac_82599EB: 6023 case ixgbe_mac_X540: 6024 case ixgbe_mac_X550: 6025 case ixgbe_mac_X550EM_x: 6026 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID); 6027 break; 6028 default: 6029 break; 6030 } 6031 } 6032 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID), 6033 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 6034 | IXGBE_EITR_CNT_WDIS); 6035 6036 /* set up to autoclear timer, and the vectors */ 6037 mask = IXGBE_EIMS_ENABLE_MASK; 6038 mask &= ~(IXGBE_EIMS_OTHER | 6039 IXGBE_EIMS_MAILBOX | 6040 IXGBE_EIMS_LSC); 6041 6042 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask); 6043 } 6044 6045 int 6046 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, 6047 uint16_t queue_idx, uint16_t tx_rate) 6048 { 6049 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6050 uint32_t rf_dec, rf_int; 6051 uint32_t bcnrc_val; 6052 uint16_t link_speed = dev->data->dev_link.link_speed; 6053 6054 if (queue_idx >= hw->mac.max_tx_queues) 6055 return -EINVAL; 6056 6057 if (tx_rate != 0) { 6058 /* Calculate the rate factor values to set */ 6059 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate; 6060 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate; 6061 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate; 6062 6063 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA; 6064 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) & 6065 IXGBE_RTTBCNRC_RF_INT_MASK_M); 6066 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK); 6067 } else { 6068 bcnrc_val = 0; 6069 } 6070 6071 /* 6072 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 6073 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise 6074 * set as 0x4. 6075 */ 6076 if (dev->data->mtu + IXGBE_ETH_OVERHEAD >= IXGBE_MAX_JUMBO_FRAME_SIZE) 6077 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, IXGBE_MMW_SIZE_JUMBO_FRAME); 6078 else 6079 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, IXGBE_MMW_SIZE_DEFAULT); 6080 6081 /* Set RTTBCNRC of queue X */ 6082 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx); 6083 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 6084 IXGBE_WRITE_FLUSH(hw); 6085 6086 return 0; 6087 } 6088 6089 static int 6090 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 6091 __rte_unused uint32_t index, 6092 __rte_unused uint32_t pool) 6093 { 6094 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6095 int diag; 6096 6097 /* 6098 * On a 82599 VF, adding again the same MAC addr is not an idempotent 6099 * operation. Trap this case to avoid exhausting the [very limited] 6100 * set of PF resources used to store VF MAC addresses. 6101 */ 6102 if (memcmp(hw->mac.perm_addr, mac_addr, 6103 sizeof(struct rte_ether_addr)) == 0) 6104 return -1; 6105 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6106 if (diag != 0) 6107 PMD_DRV_LOG(ERR, "Unable to add MAC address " 6108 RTE_ETHER_ADDR_PRT_FMT " - diag=%d", 6109 RTE_ETHER_ADDR_BYTES(mac_addr), diag); 6110 return diag; 6111 } 6112 6113 static void 6114 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index) 6115 { 6116 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6117 struct rte_ether_addr *perm_addr = 6118 (struct rte_ether_addr *)hw->mac.perm_addr; 6119 struct rte_ether_addr *mac_addr; 6120 uint32_t i; 6121 int diag; 6122 6123 /* 6124 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does 6125 * not support the deletion of a given MAC address. 6126 * Instead, it imposes to delete all MAC addresses, then to add again 6127 * all MAC addresses with the exception of the one to be deleted. 6128 */ 6129 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL); 6130 6131 /* 6132 * Add again all MAC addresses, with the exception of the deleted one 6133 * and of the permanent MAC address. 6134 */ 6135 for (i = 0, mac_addr = dev->data->mac_addrs; 6136 i < hw->mac.num_rar_entries; i++, mac_addr++) { 6137 /* Skip the deleted MAC address */ 6138 if (i == index) 6139 continue; 6140 /* Skip NULL MAC addresses */ 6141 if (rte_is_zero_ether_addr(mac_addr)) 6142 continue; 6143 /* Skip the permanent MAC address */ 6144 if (memcmp(perm_addr, mac_addr, 6145 sizeof(struct rte_ether_addr)) == 0) 6146 continue; 6147 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6148 if (diag != 0) 6149 PMD_DRV_LOG(ERR, 6150 "Adding again MAC address " 6151 RTE_ETHER_ADDR_PRT_FMT " failed " 6152 "diag=%d", RTE_ETHER_ADDR_BYTES(mac_addr), 6153 diag); 6154 } 6155 } 6156 6157 static int 6158 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 6159 struct rte_ether_addr *addr) 6160 { 6161 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6162 6163 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0); 6164 6165 return 0; 6166 } 6167 6168 int 6169 ixgbe_syn_filter_set(struct rte_eth_dev *dev, 6170 struct rte_eth_syn_filter *filter, 6171 bool add) 6172 { 6173 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6174 struct ixgbe_filter_info *filter_info = 6175 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6176 uint32_t syn_info; 6177 uint32_t synqf; 6178 6179 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6180 return -EINVAL; 6181 6182 syn_info = filter_info->syn_info; 6183 6184 if (add) { 6185 if (syn_info & IXGBE_SYN_FILTER_ENABLE) 6186 return -EINVAL; 6187 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) & 6188 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE); 6189 6190 if (filter->hig_pri) 6191 synqf |= IXGBE_SYN_FILTER_SYNQFP; 6192 else 6193 synqf &= ~IXGBE_SYN_FILTER_SYNQFP; 6194 } else { 6195 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6196 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE)) 6197 return -ENOENT; 6198 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE); 6199 } 6200 6201 filter_info->syn_info = synqf; 6202 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 6203 IXGBE_WRITE_FLUSH(hw); 6204 return 0; 6205 } 6206 6207 6208 static inline enum ixgbe_5tuple_protocol 6209 convert_protocol_type(uint8_t protocol_value) 6210 { 6211 if (protocol_value == IPPROTO_TCP) 6212 return IXGBE_FILTER_PROTOCOL_TCP; 6213 else if (protocol_value == IPPROTO_UDP) 6214 return IXGBE_FILTER_PROTOCOL_UDP; 6215 else if (protocol_value == IPPROTO_SCTP) 6216 return IXGBE_FILTER_PROTOCOL_SCTP; 6217 else 6218 return IXGBE_FILTER_PROTOCOL_NONE; 6219 } 6220 6221 /* inject a 5-tuple filter to HW */ 6222 static inline void 6223 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev, 6224 struct ixgbe_5tuple_filter *filter) 6225 { 6226 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6227 int i; 6228 uint32_t ftqf, sdpqf; 6229 uint32_t l34timir = 0; 6230 uint8_t mask = 0xff; 6231 6232 i = filter->index; 6233 6234 sdpqf = (uint32_t)(filter->filter_info.dst_port << 6235 IXGBE_SDPQF_DSTPORT_SHIFT); 6236 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT); 6237 6238 ftqf = (uint32_t)(filter->filter_info.proto & 6239 IXGBE_FTQF_PROTOCOL_MASK); 6240 ftqf |= (uint32_t)((filter->filter_info.priority & 6241 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT); 6242 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */ 6243 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK; 6244 if (filter->filter_info.dst_ip_mask == 0) 6245 mask &= IXGBE_FTQF_DEST_ADDR_MASK; 6246 if (filter->filter_info.src_port_mask == 0) 6247 mask &= IXGBE_FTQF_SOURCE_PORT_MASK; 6248 if (filter->filter_info.dst_port_mask == 0) 6249 mask &= IXGBE_FTQF_DEST_PORT_MASK; 6250 if (filter->filter_info.proto_mask == 0) 6251 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK; 6252 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT; 6253 ftqf |= IXGBE_FTQF_POOL_MASK_EN; 6254 ftqf |= IXGBE_FTQF_QUEUE_ENABLE; 6255 6256 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip); 6257 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip); 6258 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf); 6259 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf); 6260 6261 l34timir |= IXGBE_L34T_IMIR_RESERVE; 6262 l34timir |= (uint32_t)(filter->queue << 6263 IXGBE_L34T_IMIR_QUEUE_SHIFT); 6264 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir); 6265 } 6266 6267 /* 6268 * add a 5tuple filter 6269 * 6270 * @param 6271 * dev: Pointer to struct rte_eth_dev. 6272 * index: the index the filter allocates. 6273 * filter: pointer to the filter that will be added. 6274 * rx_queue: the queue id the filter assigned to. 6275 * 6276 * @return 6277 * - On success, zero. 6278 * - On failure, a negative value. 6279 */ 6280 static int 6281 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 6282 struct ixgbe_5tuple_filter *filter) 6283 { 6284 struct ixgbe_filter_info *filter_info = 6285 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6286 int i, idx, shift; 6287 6288 /* 6289 * look for an unused 5tuple filter index, 6290 * and insert the filter to list. 6291 */ 6292 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) { 6293 idx = i / (sizeof(uint32_t) * NBBY); 6294 shift = i % (sizeof(uint32_t) * NBBY); 6295 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) { 6296 filter_info->fivetuple_mask[idx] |= 1 << shift; 6297 filter->index = i; 6298 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list, 6299 filter, 6300 entries); 6301 break; 6302 } 6303 } 6304 if (i >= IXGBE_MAX_FTQF_FILTERS) { 6305 PMD_DRV_LOG(ERR, "5tuple filters are full."); 6306 return -ENOSYS; 6307 } 6308 6309 ixgbe_inject_5tuple_filter(dev, filter); 6310 6311 return 0; 6312 } 6313 6314 /* 6315 * remove a 5tuple filter 6316 * 6317 * @param 6318 * dev: Pointer to struct rte_eth_dev. 6319 * filter: the pointer of the filter will be removed. 6320 */ 6321 static void 6322 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 6323 struct ixgbe_5tuple_filter *filter) 6324 { 6325 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6326 struct ixgbe_filter_info *filter_info = 6327 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6328 uint16_t index = filter->index; 6329 6330 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &= 6331 ~(1 << (index % (sizeof(uint32_t) * NBBY))); 6332 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries); 6333 rte_free(filter); 6334 6335 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0); 6336 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0); 6337 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0); 6338 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0); 6339 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0); 6340 } 6341 6342 static int 6343 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 6344 { 6345 struct ixgbe_hw *hw; 6346 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD; 6347 struct rte_eth_dev_data *dev_data = dev->data; 6348 6349 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6350 6351 if (mtu < RTE_ETHER_MIN_MTU || max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN) 6352 return -EINVAL; 6353 6354 /* If device is started, refuse mtu that requires the support of 6355 * scattered packets when this feature has not been enabled before. 6356 */ 6357 if (dev_data->dev_started && !dev_data->scattered_rx && 6358 (max_frame + 2 * RTE_VLAN_HLEN > 6359 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 6360 PMD_INIT_LOG(ERR, "Stop port first."); 6361 return -EINVAL; 6362 } 6363 6364 /* 6365 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU 6366 * request of the version 2.0 of the mailbox API. 6367 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0 6368 * of the mailbox API. 6369 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers 6370 * prior to 3.11.33 which contains the following change: 6371 * "ixgbe: Enable jumbo frames support w/ SR-IOV" 6372 */ 6373 if (ixgbevf_rlpml_set_vf(hw, max_frame)) 6374 return -EINVAL; 6375 6376 return 0; 6377 } 6378 6379 static inline struct ixgbe_5tuple_filter * 6380 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list, 6381 struct ixgbe_5tuple_filter_info *key) 6382 { 6383 struct ixgbe_5tuple_filter *it; 6384 6385 TAILQ_FOREACH(it, filter_list, entries) { 6386 if (memcmp(key, &it->filter_info, 6387 sizeof(struct ixgbe_5tuple_filter_info)) == 0) { 6388 return it; 6389 } 6390 } 6391 return NULL; 6392 } 6393 6394 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/ 6395 static inline int 6396 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter, 6397 struct ixgbe_5tuple_filter_info *filter_info) 6398 { 6399 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM || 6400 filter->priority > IXGBE_5TUPLE_MAX_PRI || 6401 filter->priority < IXGBE_5TUPLE_MIN_PRI) 6402 return -EINVAL; 6403 6404 switch (filter->dst_ip_mask) { 6405 case UINT32_MAX: 6406 filter_info->dst_ip_mask = 0; 6407 filter_info->dst_ip = filter->dst_ip; 6408 break; 6409 case 0: 6410 filter_info->dst_ip_mask = 1; 6411 break; 6412 default: 6413 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 6414 return -EINVAL; 6415 } 6416 6417 switch (filter->src_ip_mask) { 6418 case UINT32_MAX: 6419 filter_info->src_ip_mask = 0; 6420 filter_info->src_ip = filter->src_ip; 6421 break; 6422 case 0: 6423 filter_info->src_ip_mask = 1; 6424 break; 6425 default: 6426 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 6427 return -EINVAL; 6428 } 6429 6430 switch (filter->dst_port_mask) { 6431 case UINT16_MAX: 6432 filter_info->dst_port_mask = 0; 6433 filter_info->dst_port = filter->dst_port; 6434 break; 6435 case 0: 6436 filter_info->dst_port_mask = 1; 6437 break; 6438 default: 6439 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 6440 return -EINVAL; 6441 } 6442 6443 switch (filter->src_port_mask) { 6444 case UINT16_MAX: 6445 filter_info->src_port_mask = 0; 6446 filter_info->src_port = filter->src_port; 6447 break; 6448 case 0: 6449 filter_info->src_port_mask = 1; 6450 break; 6451 default: 6452 PMD_DRV_LOG(ERR, "invalid src_port mask."); 6453 return -EINVAL; 6454 } 6455 6456 switch (filter->proto_mask) { 6457 case UINT8_MAX: 6458 filter_info->proto_mask = 0; 6459 filter_info->proto = 6460 convert_protocol_type(filter->proto); 6461 break; 6462 case 0: 6463 filter_info->proto_mask = 1; 6464 break; 6465 default: 6466 PMD_DRV_LOG(ERR, "invalid protocol mask."); 6467 return -EINVAL; 6468 } 6469 6470 filter_info->priority = (uint8_t)filter->priority; 6471 return 0; 6472 } 6473 6474 /* 6475 * add or delete a ntuple filter 6476 * 6477 * @param 6478 * dev: Pointer to struct rte_eth_dev. 6479 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6480 * add: if true, add filter, if false, remove filter 6481 * 6482 * @return 6483 * - On success, zero. 6484 * - On failure, a negative value. 6485 */ 6486 int 6487 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 6488 struct rte_eth_ntuple_filter *ntuple_filter, 6489 bool add) 6490 { 6491 struct ixgbe_filter_info *filter_info = 6492 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6493 struct ixgbe_5tuple_filter_info filter_5tuple; 6494 struct ixgbe_5tuple_filter *filter; 6495 int ret; 6496 6497 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6498 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6499 return -EINVAL; 6500 } 6501 6502 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6503 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6504 if (ret < 0) 6505 return ret; 6506 6507 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6508 &filter_5tuple); 6509 if (filter != NULL && add) { 6510 PMD_DRV_LOG(ERR, "filter exists."); 6511 return -EEXIST; 6512 } 6513 if (filter == NULL && !add) { 6514 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6515 return -ENOENT; 6516 } 6517 6518 if (add) { 6519 filter = rte_zmalloc("ixgbe_5tuple_filter", 6520 sizeof(struct ixgbe_5tuple_filter), 0); 6521 if (filter == NULL) 6522 return -ENOMEM; 6523 rte_memcpy(&filter->filter_info, 6524 &filter_5tuple, 6525 sizeof(struct ixgbe_5tuple_filter_info)); 6526 filter->queue = ntuple_filter->queue; 6527 ret = ixgbe_add_5tuple_filter(dev, filter); 6528 if (ret < 0) { 6529 rte_free(filter); 6530 return ret; 6531 } 6532 } else 6533 ixgbe_remove_5tuple_filter(dev, filter); 6534 6535 return 0; 6536 } 6537 6538 int 6539 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 6540 struct rte_eth_ethertype_filter *filter, 6541 bool add) 6542 { 6543 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6544 struct ixgbe_filter_info *filter_info = 6545 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6546 uint32_t etqf = 0; 6547 uint32_t etqs = 0; 6548 int ret; 6549 struct ixgbe_ethertype_filter ethertype_filter; 6550 6551 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6552 return -EINVAL; 6553 6554 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 || 6555 filter->ether_type == RTE_ETHER_TYPE_IPV6) { 6556 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in" 6557 " ethertype filter.", filter->ether_type); 6558 return -EINVAL; 6559 } 6560 6561 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) { 6562 PMD_DRV_LOG(ERR, "mac compare is unsupported."); 6563 return -EINVAL; 6564 } 6565 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) { 6566 PMD_DRV_LOG(ERR, "drop option is unsupported."); 6567 return -EINVAL; 6568 } 6569 6570 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6571 if (ret >= 0 && add) { 6572 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.", 6573 filter->ether_type); 6574 return -EEXIST; 6575 } 6576 if (ret < 0 && !add) { 6577 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6578 filter->ether_type); 6579 return -ENOENT; 6580 } 6581 6582 if (add) { 6583 etqf = IXGBE_ETQF_FILTER_EN; 6584 etqf |= (uint32_t)filter->ether_type; 6585 etqs |= (uint32_t)((filter->queue << 6586 IXGBE_ETQS_RX_QUEUE_SHIFT) & 6587 IXGBE_ETQS_RX_QUEUE); 6588 etqs |= IXGBE_ETQS_QUEUE_EN; 6589 6590 ethertype_filter.ethertype = filter->ether_type; 6591 ethertype_filter.etqf = etqf; 6592 ethertype_filter.etqs = etqs; 6593 ethertype_filter.conf = FALSE; 6594 ret = ixgbe_ethertype_filter_insert(filter_info, 6595 ðertype_filter); 6596 if (ret < 0) { 6597 PMD_DRV_LOG(ERR, "ethertype filters are full."); 6598 return -ENOSPC; 6599 } 6600 } else { 6601 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret); 6602 if (ret < 0) 6603 return -ENOSYS; 6604 } 6605 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf); 6606 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs); 6607 IXGBE_WRITE_FLUSH(hw); 6608 6609 return 0; 6610 } 6611 6612 static int 6613 ixgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev, 6614 const struct rte_flow_ops **ops) 6615 { 6616 *ops = &ixgbe_flow_ops; 6617 return 0; 6618 } 6619 6620 static u8 * 6621 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw, 6622 u8 **mc_addr_ptr, u32 *vmdq) 6623 { 6624 u8 *mc_addr; 6625 6626 *vmdq = 0; 6627 mc_addr = *mc_addr_ptr; 6628 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr)); 6629 return mc_addr; 6630 } 6631 6632 static int 6633 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 6634 struct rte_ether_addr *mc_addr_set, 6635 uint32_t nb_mc_addr) 6636 { 6637 struct ixgbe_hw *hw; 6638 u8 *mc_addr_list; 6639 6640 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6641 mc_addr_list = (u8 *)mc_addr_set; 6642 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr, 6643 ixgbe_dev_addr_list_itr, TRUE); 6644 } 6645 6646 static uint64_t 6647 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev) 6648 { 6649 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6650 uint64_t systime_cycles; 6651 6652 switch (hw->mac.type) { 6653 case ixgbe_mac_X550: 6654 case ixgbe_mac_X550EM_x: 6655 case ixgbe_mac_X550EM_a: 6656 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */ 6657 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 6658 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 6659 * NSEC_PER_SEC; 6660 break; 6661 default: 6662 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 6663 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 6664 << 32; 6665 } 6666 6667 return systime_cycles; 6668 } 6669 6670 static uint64_t 6671 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) 6672 { 6673 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6674 uint64_t rx_tstamp_cycles; 6675 6676 switch (hw->mac.type) { 6677 case ixgbe_mac_X550: 6678 case ixgbe_mac_X550EM_x: 6679 case ixgbe_mac_X550EM_a: 6680 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 6681 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 6682 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 6683 * NSEC_PER_SEC; 6684 break; 6685 default: 6686 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 6687 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 6688 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 6689 << 32; 6690 } 6691 6692 return rx_tstamp_cycles; 6693 } 6694 6695 static uint64_t 6696 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 6697 { 6698 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6699 uint64_t tx_tstamp_cycles; 6700 6701 switch (hw->mac.type) { 6702 case ixgbe_mac_X550: 6703 case ixgbe_mac_X550EM_x: 6704 case ixgbe_mac_X550EM_a: 6705 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 6706 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 6707 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 6708 * NSEC_PER_SEC; 6709 break; 6710 default: 6711 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 6712 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 6713 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 6714 << 32; 6715 } 6716 6717 return tx_tstamp_cycles; 6718 } 6719 6720 static void 6721 ixgbe_start_timecounters(struct rte_eth_dev *dev) 6722 { 6723 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6724 struct ixgbe_adapter *adapter = dev->data->dev_private; 6725 struct rte_eth_link link; 6726 uint32_t incval = 0; 6727 uint32_t shift = 0; 6728 6729 /* Get current link speed. */ 6730 ixgbe_dev_link_update(dev, 1); 6731 rte_eth_linkstatus_get(dev, &link); 6732 6733 switch (link.link_speed) { 6734 case RTE_ETH_SPEED_NUM_100M: 6735 incval = IXGBE_INCVAL_100; 6736 shift = IXGBE_INCVAL_SHIFT_100; 6737 break; 6738 case RTE_ETH_SPEED_NUM_1G: 6739 incval = IXGBE_INCVAL_1GB; 6740 shift = IXGBE_INCVAL_SHIFT_1GB; 6741 break; 6742 case RTE_ETH_SPEED_NUM_10G: 6743 default: 6744 incval = IXGBE_INCVAL_10GB; 6745 shift = IXGBE_INCVAL_SHIFT_10GB; 6746 break; 6747 } 6748 6749 switch (hw->mac.type) { 6750 case ixgbe_mac_X550: 6751 case ixgbe_mac_X550EM_x: 6752 case ixgbe_mac_X550EM_a: 6753 /* Independent of link speed. */ 6754 incval = 1; 6755 /* Cycles read will be interpreted as ns. */ 6756 shift = 0; 6757 /* Fall-through */ 6758 case ixgbe_mac_X540: 6759 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval); 6760 break; 6761 case ixgbe_mac_82599EB: 6762 incval >>= IXGBE_INCVAL_SHIFT_82599; 6763 shift -= IXGBE_INCVAL_SHIFT_82599; 6764 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 6765 (1 << IXGBE_INCPER_SHIFT_82599) | incval); 6766 break; 6767 default: 6768 /* Not supported. */ 6769 return; 6770 } 6771 6772 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 6773 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 6774 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 6775 6776 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6777 adapter->systime_tc.cc_shift = shift; 6778 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; 6779 6780 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6781 adapter->rx_tstamp_tc.cc_shift = shift; 6782 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 6783 6784 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6785 adapter->tx_tstamp_tc.cc_shift = shift; 6786 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 6787 } 6788 6789 static int 6790 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 6791 { 6792 struct ixgbe_adapter *adapter = dev->data->dev_private; 6793 6794 adapter->systime_tc.nsec += delta; 6795 adapter->rx_tstamp_tc.nsec += delta; 6796 adapter->tx_tstamp_tc.nsec += delta; 6797 6798 return 0; 6799 } 6800 6801 static int 6802 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 6803 { 6804 uint64_t ns; 6805 struct ixgbe_adapter *adapter = dev->data->dev_private; 6806 6807 ns = rte_timespec_to_ns(ts); 6808 /* Set the timecounters to a new value. */ 6809 adapter->systime_tc.nsec = ns; 6810 adapter->rx_tstamp_tc.nsec = ns; 6811 adapter->tx_tstamp_tc.nsec = ns; 6812 6813 return 0; 6814 } 6815 6816 static int 6817 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 6818 { 6819 uint64_t ns, systime_cycles; 6820 struct ixgbe_adapter *adapter = dev->data->dev_private; 6821 6822 systime_cycles = ixgbe_read_systime_cyclecounter(dev); 6823 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 6824 *ts = rte_ns_to_timespec(ns); 6825 6826 return 0; 6827 } 6828 6829 static int 6830 ixgbe_timesync_enable(struct rte_eth_dev *dev) 6831 { 6832 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6833 uint32_t tsync_ctl; 6834 uint32_t tsauxc; 6835 6836 /* Stop the timesync system time. */ 6837 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0); 6838 /* Reset the timesync system time value. */ 6839 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0); 6840 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0); 6841 6842 /* Enable system time for platforms where it isn't on by default. */ 6843 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC); 6844 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME; 6845 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc); 6846 6847 ixgbe_start_timecounters(dev); 6848 6849 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 6850 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 6851 (RTE_ETHER_TYPE_1588 | 6852 IXGBE_ETQF_FILTER_EN | 6853 IXGBE_ETQF_1588)); 6854 6855 /* Enable timestamping of received PTP packets. */ 6856 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 6857 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED; 6858 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 6859 6860 /* Enable timestamping of transmitted PTP packets. */ 6861 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 6862 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED; 6863 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 6864 6865 IXGBE_WRITE_FLUSH(hw); 6866 6867 return 0; 6868 } 6869 6870 static int 6871 ixgbe_timesync_disable(struct rte_eth_dev *dev) 6872 { 6873 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6874 uint32_t tsync_ctl; 6875 6876 /* Disable timestamping of transmitted PTP packets. */ 6877 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 6878 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED; 6879 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 6880 6881 /* Disable timestamping of received PTP packets. */ 6882 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 6883 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED; 6884 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 6885 6886 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 6887 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0); 6888 6889 /* Stop incrementing the System Time registers. */ 6890 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0); 6891 6892 return 0; 6893 } 6894 6895 static int 6896 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 6897 struct timespec *timestamp, 6898 uint32_t flags __rte_unused) 6899 { 6900 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6901 struct ixgbe_adapter *adapter = dev->data->dev_private; 6902 uint32_t tsync_rxctl; 6903 uint64_t rx_tstamp_cycles; 6904 uint64_t ns; 6905 6906 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 6907 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0) 6908 return -EINVAL; 6909 6910 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev); 6911 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 6912 *timestamp = rte_ns_to_timespec(ns); 6913 6914 return 0; 6915 } 6916 6917 static int 6918 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 6919 struct timespec *timestamp) 6920 { 6921 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6922 struct ixgbe_adapter *adapter = dev->data->dev_private; 6923 uint32_t tsync_txctl; 6924 uint64_t tx_tstamp_cycles; 6925 uint64_t ns; 6926 6927 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 6928 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0) 6929 return -EINVAL; 6930 6931 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev); 6932 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 6933 *timestamp = rte_ns_to_timespec(ns); 6934 6935 return 0; 6936 } 6937 6938 static int 6939 ixgbe_get_reg_length(struct rte_eth_dev *dev) 6940 { 6941 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6942 int count = 0; 6943 int g_ind = 0; 6944 const struct reg_info *reg_group; 6945 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 6946 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 6947 6948 while ((reg_group = reg_set[g_ind++])) 6949 count += ixgbe_regs_group_count(reg_group); 6950 6951 return count; 6952 } 6953 6954 static int 6955 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused) 6956 { 6957 int count = 0; 6958 int g_ind = 0; 6959 const struct reg_info *reg_group; 6960 6961 while ((reg_group = ixgbevf_regs[g_ind++])) 6962 count += ixgbe_regs_group_count(reg_group); 6963 6964 return count; 6965 } 6966 6967 static int 6968 ixgbe_get_regs(struct rte_eth_dev *dev, 6969 struct rte_dev_reg_info *regs) 6970 { 6971 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6972 uint32_t *data = regs->data; 6973 int g_ind = 0; 6974 int count = 0; 6975 const struct reg_info *reg_group; 6976 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 6977 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 6978 6979 if (data == NULL) { 6980 regs->length = ixgbe_get_reg_length(dev); 6981 regs->width = sizeof(uint32_t); 6982 return 0; 6983 } 6984 6985 /* Support only full register dump */ 6986 if ((regs->length == 0) || 6987 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) { 6988 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 6989 hw->device_id; 6990 while ((reg_group = reg_set[g_ind++])) 6991 count += ixgbe_read_regs_group(dev, &data[count], 6992 reg_group); 6993 return 0; 6994 } 6995 6996 return -ENOTSUP; 6997 } 6998 6999 static int 7000 ixgbevf_get_regs(struct rte_eth_dev *dev, 7001 struct rte_dev_reg_info *regs) 7002 { 7003 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7004 uint32_t *data = regs->data; 7005 int g_ind = 0; 7006 int count = 0; 7007 const struct reg_info *reg_group; 7008 7009 if (data == NULL) { 7010 regs->length = ixgbevf_get_reg_length(dev); 7011 regs->width = sizeof(uint32_t); 7012 return 0; 7013 } 7014 7015 /* Support only full register dump */ 7016 if ((regs->length == 0) || 7017 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) { 7018 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7019 hw->device_id; 7020 while ((reg_group = ixgbevf_regs[g_ind++])) 7021 count += ixgbe_read_regs_group(dev, &data[count], 7022 reg_group); 7023 return 0; 7024 } 7025 7026 return -ENOTSUP; 7027 } 7028 7029 static int 7030 ixgbe_get_eeprom_length(struct rte_eth_dev *dev) 7031 { 7032 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7033 7034 /* Return unit is byte count */ 7035 return hw->eeprom.word_size * 2; 7036 } 7037 7038 static int 7039 ixgbe_get_eeprom(struct rte_eth_dev *dev, 7040 struct rte_dev_eeprom_info *in_eeprom) 7041 { 7042 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7043 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7044 uint16_t *data = in_eeprom->data; 7045 int first, length; 7046 7047 first = in_eeprom->offset >> 1; 7048 length = in_eeprom->length >> 1; 7049 if ((first > hw->eeprom.word_size) || 7050 ((first + length) > hw->eeprom.word_size)) 7051 return -EINVAL; 7052 7053 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7054 7055 return eeprom->ops.read_buffer(hw, first, length, data); 7056 } 7057 7058 static int 7059 ixgbe_set_eeprom(struct rte_eth_dev *dev, 7060 struct rte_dev_eeprom_info *in_eeprom) 7061 { 7062 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7063 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7064 uint16_t *data = in_eeprom->data; 7065 int first, length; 7066 7067 first = in_eeprom->offset >> 1; 7068 length = in_eeprom->length >> 1; 7069 if ((first > hw->eeprom.word_size) || 7070 ((first + length) > hw->eeprom.word_size)) 7071 return -EINVAL; 7072 7073 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7074 7075 return eeprom->ops.write_buffer(hw, first, length, data); 7076 } 7077 7078 static int 7079 ixgbe_get_module_info(struct rte_eth_dev *dev, 7080 struct rte_eth_dev_module_info *modinfo) 7081 { 7082 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7083 uint32_t status; 7084 uint8_t sff8472_rev, addr_mode; 7085 bool page_swap = false; 7086 7087 /* Check whether we support SFF-8472 or not */ 7088 status = hw->phy.ops.read_i2c_eeprom(hw, 7089 IXGBE_SFF_SFF_8472_COMP, 7090 &sff8472_rev); 7091 if (status != 0) 7092 return -EIO; 7093 7094 /* addressing mode is not supported */ 7095 status = hw->phy.ops.read_i2c_eeprom(hw, 7096 IXGBE_SFF_SFF_8472_SWAP, 7097 &addr_mode); 7098 if (status != 0) 7099 return -EIO; 7100 7101 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 7102 PMD_DRV_LOG(ERR, 7103 "Address change required to access page 0xA2, " 7104 "but not supported. Please report the module " 7105 "type to the driver maintainers."); 7106 page_swap = true; 7107 } 7108 7109 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) { 7110 /* We have a SFP, but it does not support SFF-8472 */ 7111 modinfo->type = RTE_ETH_MODULE_SFF_8079; 7112 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 7113 } else { 7114 /* We have a SFP which supports a revision of SFF-8472. */ 7115 modinfo->type = RTE_ETH_MODULE_SFF_8472; 7116 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 7117 } 7118 7119 return 0; 7120 } 7121 7122 static int 7123 ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 7124 struct rte_dev_eeprom_info *info) 7125 { 7126 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7127 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 7128 uint8_t databyte = 0xFF; 7129 uint8_t *data = info->data; 7130 uint32_t i = 0; 7131 7132 for (i = info->offset; i < info->offset + info->length; i++) { 7133 if (i < RTE_ETH_MODULE_SFF_8079_LEN) 7134 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 7135 else 7136 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 7137 7138 if (status != 0) 7139 return -EIO; 7140 7141 data[i - info->offset] = databyte; 7142 } 7143 7144 return 0; 7145 } 7146 7147 uint16_t 7148 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) { 7149 switch (mac_type) { 7150 case ixgbe_mac_X550: 7151 case ixgbe_mac_X550EM_x: 7152 case ixgbe_mac_X550EM_a: 7153 return RTE_ETH_RSS_RETA_SIZE_512; 7154 case ixgbe_mac_X550_vf: 7155 case ixgbe_mac_X550EM_x_vf: 7156 case ixgbe_mac_X550EM_a_vf: 7157 return RTE_ETH_RSS_RETA_SIZE_64; 7158 case ixgbe_mac_X540_vf: 7159 case ixgbe_mac_82599_vf: 7160 return 0; 7161 default: 7162 return RTE_ETH_RSS_RETA_SIZE_128; 7163 } 7164 } 7165 7166 uint32_t 7167 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) { 7168 switch (mac_type) { 7169 case ixgbe_mac_X550: 7170 case ixgbe_mac_X550EM_x: 7171 case ixgbe_mac_X550EM_a: 7172 if (reta_idx < RTE_ETH_RSS_RETA_SIZE_128) 7173 return IXGBE_RETA(reta_idx >> 2); 7174 else 7175 return IXGBE_ERETA((reta_idx - RTE_ETH_RSS_RETA_SIZE_128) >> 2); 7176 case ixgbe_mac_X550_vf: 7177 case ixgbe_mac_X550EM_x_vf: 7178 case ixgbe_mac_X550EM_a_vf: 7179 return IXGBE_VFRETA(reta_idx >> 2); 7180 default: 7181 return IXGBE_RETA(reta_idx >> 2); 7182 } 7183 } 7184 7185 uint32_t 7186 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) { 7187 switch (mac_type) { 7188 case ixgbe_mac_X550_vf: 7189 case ixgbe_mac_X550EM_x_vf: 7190 case ixgbe_mac_X550EM_a_vf: 7191 return IXGBE_VFMRQC; 7192 default: 7193 return IXGBE_MRQC; 7194 } 7195 } 7196 7197 uint32_t 7198 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) { 7199 switch (mac_type) { 7200 case ixgbe_mac_X550_vf: 7201 case ixgbe_mac_X550EM_x_vf: 7202 case ixgbe_mac_X550EM_a_vf: 7203 return IXGBE_VFRSSRK(i); 7204 default: 7205 return IXGBE_RSSRK(i); 7206 } 7207 } 7208 7209 bool 7210 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) { 7211 switch (mac_type) { 7212 case ixgbe_mac_82599_vf: 7213 case ixgbe_mac_X540_vf: 7214 return 0; 7215 default: 7216 return 1; 7217 } 7218 } 7219 7220 static int 7221 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 7222 struct rte_eth_dcb_info *dcb_info) 7223 { 7224 struct ixgbe_dcb_config *dcb_config = 7225 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 7226 struct ixgbe_dcb_tc_config *tc; 7227 struct rte_eth_dcb_tc_queue_mapping *tc_queue; 7228 uint8_t nb_tcs; 7229 uint8_t i, j; 7230 7231 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) 7232 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs; 7233 else 7234 dcb_info->nb_tcs = 1; 7235 7236 tc_queue = &dcb_info->tc_queue; 7237 nb_tcs = dcb_info->nb_tcs; 7238 7239 if (dcb_config->vt_mode) { /* vt is enabled*/ 7240 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf = 7241 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf; 7242 for (i = 0; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++) 7243 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i]; 7244 if (RTE_ETH_DEV_SRIOV(dev).active > 0) { 7245 for (j = 0; j < nb_tcs; j++) { 7246 tc_queue->tc_rxq[0][j].base = j; 7247 tc_queue->tc_rxq[0][j].nb_queue = 1; 7248 tc_queue->tc_txq[0][j].base = j; 7249 tc_queue->tc_txq[0][j].nb_queue = 1; 7250 } 7251 } else { 7252 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) { 7253 for (j = 0; j < nb_tcs; j++) { 7254 tc_queue->tc_rxq[i][j].base = 7255 i * nb_tcs + j; 7256 tc_queue->tc_rxq[i][j].nb_queue = 1; 7257 tc_queue->tc_txq[i][j].base = 7258 i * nb_tcs + j; 7259 tc_queue->tc_txq[i][j].nb_queue = 1; 7260 } 7261 } 7262 } 7263 } else { /* vt is disabled*/ 7264 struct rte_eth_dcb_rx_conf *rx_conf = 7265 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 7266 for (i = 0; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++) 7267 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i]; 7268 if (dcb_info->nb_tcs == RTE_ETH_4_TCS) { 7269 for (i = 0; i < dcb_info->nb_tcs; i++) { 7270 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32; 7271 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7272 } 7273 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7274 dcb_info->tc_queue.tc_txq[0][1].base = 64; 7275 dcb_info->tc_queue.tc_txq[0][2].base = 96; 7276 dcb_info->tc_queue.tc_txq[0][3].base = 112; 7277 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64; 7278 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7279 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7280 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7281 } else if (dcb_info->nb_tcs == RTE_ETH_8_TCS) { 7282 for (i = 0; i < dcb_info->nb_tcs; i++) { 7283 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16; 7284 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7285 } 7286 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7287 dcb_info->tc_queue.tc_txq[0][1].base = 32; 7288 dcb_info->tc_queue.tc_txq[0][2].base = 64; 7289 dcb_info->tc_queue.tc_txq[0][3].base = 80; 7290 dcb_info->tc_queue.tc_txq[0][4].base = 96; 7291 dcb_info->tc_queue.tc_txq[0][5].base = 104; 7292 dcb_info->tc_queue.tc_txq[0][6].base = 112; 7293 dcb_info->tc_queue.tc_txq[0][7].base = 120; 7294 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32; 7295 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7296 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7297 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7298 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8; 7299 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8; 7300 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8; 7301 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8; 7302 } 7303 } 7304 for (i = 0; i < dcb_info->nb_tcs; i++) { 7305 tc = &dcb_config->tc_config[i]; 7306 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent; 7307 } 7308 return 0; 7309 } 7310 7311 /* Update e-tag ether type */ 7312 static int 7313 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw, 7314 uint16_t ether_type) 7315 { 7316 uint32_t etag_etype; 7317 7318 if (hw->mac.type != ixgbe_mac_X550 && 7319 hw->mac.type != ixgbe_mac_X550EM_x && 7320 hw->mac.type != ixgbe_mac_X550EM_a) { 7321 return -ENOTSUP; 7322 } 7323 7324 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7325 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK; 7326 etag_etype |= ether_type; 7327 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7328 IXGBE_WRITE_FLUSH(hw); 7329 7330 return 0; 7331 } 7332 7333 /* Enable e-tag tunnel */ 7334 static int 7335 ixgbe_e_tag_enable(struct ixgbe_hw *hw) 7336 { 7337 uint32_t etag_etype; 7338 7339 if (hw->mac.type != ixgbe_mac_X550 && 7340 hw->mac.type != ixgbe_mac_X550EM_x && 7341 hw->mac.type != ixgbe_mac_X550EM_a) { 7342 return -ENOTSUP; 7343 } 7344 7345 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7346 etag_etype |= IXGBE_ETAG_ETYPE_VALID; 7347 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7348 IXGBE_WRITE_FLUSH(hw); 7349 7350 return 0; 7351 } 7352 7353 static int 7354 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev, 7355 struct ixgbe_l2_tunnel_conf *l2_tunnel) 7356 { 7357 int ret = 0; 7358 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7359 uint32_t i, rar_entries; 7360 uint32_t rar_low, rar_high; 7361 7362 if (hw->mac.type != ixgbe_mac_X550 && 7363 hw->mac.type != ixgbe_mac_X550EM_x && 7364 hw->mac.type != ixgbe_mac_X550EM_a) { 7365 return -ENOTSUP; 7366 } 7367 7368 rar_entries = ixgbe_get_num_rx_addrs(hw); 7369 7370 for (i = 1; i < rar_entries; i++) { 7371 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7372 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 7373 if ((rar_high & IXGBE_RAH_AV) && 7374 (rar_high & IXGBE_RAH_ADTYPE) && 7375 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) == 7376 l2_tunnel->tunnel_id)) { 7377 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 7378 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 7379 7380 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL); 7381 7382 return ret; 7383 } 7384 } 7385 7386 return ret; 7387 } 7388 7389 static int 7390 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev, 7391 struct ixgbe_l2_tunnel_conf *l2_tunnel) 7392 { 7393 int ret = 0; 7394 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7395 uint32_t i, rar_entries; 7396 uint32_t rar_low, rar_high; 7397 7398 if (hw->mac.type != ixgbe_mac_X550 && 7399 hw->mac.type != ixgbe_mac_X550EM_x && 7400 hw->mac.type != ixgbe_mac_X550EM_a) { 7401 return -ENOTSUP; 7402 } 7403 7404 /* One entry for one tunnel. Try to remove potential existing entry. */ 7405 ixgbe_e_tag_filter_del(dev, l2_tunnel); 7406 7407 rar_entries = ixgbe_get_num_rx_addrs(hw); 7408 7409 for (i = 1; i < rar_entries; i++) { 7410 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7411 if (rar_high & IXGBE_RAH_AV) { 7412 continue; 7413 } else { 7414 ixgbe_set_vmdq(hw, i, l2_tunnel->pool); 7415 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE; 7416 rar_low = l2_tunnel->tunnel_id; 7417 7418 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low); 7419 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high); 7420 7421 return ret; 7422 } 7423 } 7424 7425 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full." 7426 " Please remove a rule before adding a new one."); 7427 return -EINVAL; 7428 } 7429 7430 static inline struct ixgbe_l2_tn_filter * 7431 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info, 7432 struct ixgbe_l2_tn_key *key) 7433 { 7434 int ret; 7435 7436 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key); 7437 if (ret < 0) 7438 return NULL; 7439 7440 return l2_tn_info->hash_map[ret]; 7441 } 7442 7443 static inline int 7444 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7445 struct ixgbe_l2_tn_filter *l2_tn_filter) 7446 { 7447 int ret; 7448 7449 ret = rte_hash_add_key(l2_tn_info->hash_handle, 7450 &l2_tn_filter->key); 7451 7452 if (ret < 0) { 7453 PMD_DRV_LOG(ERR, 7454 "Failed to insert L2 tunnel filter" 7455 " to hash table %d!", 7456 ret); 7457 return ret; 7458 } 7459 7460 l2_tn_info->hash_map[ret] = l2_tn_filter; 7461 7462 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 7463 7464 return 0; 7465 } 7466 7467 static inline int 7468 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7469 struct ixgbe_l2_tn_key *key) 7470 { 7471 int ret; 7472 struct ixgbe_l2_tn_filter *l2_tn_filter; 7473 7474 ret = rte_hash_del_key(l2_tn_info->hash_handle, key); 7475 7476 if (ret < 0) { 7477 PMD_DRV_LOG(ERR, 7478 "No such L2 tunnel filter to delete %d!", 7479 ret); 7480 return ret; 7481 } 7482 7483 l2_tn_filter = l2_tn_info->hash_map[ret]; 7484 l2_tn_info->hash_map[ret] = NULL; 7485 7486 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 7487 rte_free(l2_tn_filter); 7488 7489 return 0; 7490 } 7491 7492 /* Add l2 tunnel filter */ 7493 int 7494 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 7495 struct ixgbe_l2_tunnel_conf *l2_tunnel, 7496 bool restore) 7497 { 7498 int ret; 7499 struct ixgbe_l2_tn_info *l2_tn_info = 7500 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7501 struct ixgbe_l2_tn_key key; 7502 struct ixgbe_l2_tn_filter *node; 7503 7504 if (!restore) { 7505 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 7506 key.tn_id = l2_tunnel->tunnel_id; 7507 7508 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key); 7509 7510 if (node) { 7511 PMD_DRV_LOG(ERR, 7512 "The L2 tunnel filter already exists!"); 7513 return -EINVAL; 7514 } 7515 7516 node = rte_zmalloc("ixgbe_l2_tn", 7517 sizeof(struct ixgbe_l2_tn_filter), 7518 0); 7519 if (!node) 7520 return -ENOMEM; 7521 7522 rte_memcpy(&node->key, 7523 &key, 7524 sizeof(struct ixgbe_l2_tn_key)); 7525 node->pool = l2_tunnel->pool; 7526 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node); 7527 if (ret < 0) { 7528 rte_free(node); 7529 return ret; 7530 } 7531 } 7532 7533 switch (l2_tunnel->l2_tunnel_type) { 7534 case RTE_ETH_L2_TUNNEL_TYPE_E_TAG: 7535 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel); 7536 break; 7537 default: 7538 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7539 ret = -EINVAL; 7540 break; 7541 } 7542 7543 if ((!restore) && (ret < 0)) 7544 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 7545 7546 return ret; 7547 } 7548 7549 /* Delete l2 tunnel filter */ 7550 int 7551 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 7552 struct ixgbe_l2_tunnel_conf *l2_tunnel) 7553 { 7554 int ret; 7555 struct ixgbe_l2_tn_info *l2_tn_info = 7556 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7557 struct ixgbe_l2_tn_key key; 7558 7559 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 7560 key.tn_id = l2_tunnel->tunnel_id; 7561 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 7562 if (ret < 0) 7563 return ret; 7564 7565 switch (l2_tunnel->l2_tunnel_type) { 7566 case RTE_ETH_L2_TUNNEL_TYPE_E_TAG: 7567 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel); 7568 break; 7569 default: 7570 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7571 ret = -EINVAL; 7572 break; 7573 } 7574 7575 return ret; 7576 } 7577 7578 static int 7579 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en) 7580 { 7581 int ret = 0; 7582 uint32_t ctrl; 7583 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7584 7585 if (hw->mac.type != ixgbe_mac_X550 && 7586 hw->mac.type != ixgbe_mac_X550EM_x && 7587 hw->mac.type != ixgbe_mac_X550EM_a) { 7588 return -ENOTSUP; 7589 } 7590 7591 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 7592 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 7593 if (en) 7594 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG; 7595 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 7596 7597 return ret; 7598 } 7599 7600 static int 7601 ixgbe_update_vxlan_port(struct ixgbe_hw *hw, 7602 uint16_t port) 7603 { 7604 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port); 7605 IXGBE_WRITE_FLUSH(hw); 7606 7607 return 0; 7608 } 7609 7610 /* There's only one register for VxLAN UDP port. 7611 * So, we cannot add several ports. Will update it. 7612 */ 7613 static int 7614 ixgbe_add_vxlan_port(struct ixgbe_hw *hw, 7615 uint16_t port) 7616 { 7617 if (port == 0) { 7618 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 7619 return -EINVAL; 7620 } 7621 7622 return ixgbe_update_vxlan_port(hw, port); 7623 } 7624 7625 /* We cannot delete the VxLAN port. For there's a register for VxLAN 7626 * UDP port, it must have a value. 7627 * So, will reset it to the original value 0. 7628 */ 7629 static int 7630 ixgbe_del_vxlan_port(struct ixgbe_hw *hw, 7631 uint16_t port) 7632 { 7633 uint16_t cur_port; 7634 7635 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL); 7636 7637 if (cur_port != port) { 7638 PMD_DRV_LOG(ERR, "Port %u does not exist.", port); 7639 return -EINVAL; 7640 } 7641 7642 return ixgbe_update_vxlan_port(hw, 0); 7643 } 7644 7645 /* Add UDP tunneling port */ 7646 static int 7647 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 7648 struct rte_eth_udp_tunnel *udp_tunnel) 7649 { 7650 int ret = 0; 7651 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7652 7653 if (hw->mac.type != ixgbe_mac_X550 && 7654 hw->mac.type != ixgbe_mac_X550EM_x && 7655 hw->mac.type != ixgbe_mac_X550EM_a) { 7656 return -ENOTSUP; 7657 } 7658 7659 if (udp_tunnel == NULL) 7660 return -EINVAL; 7661 7662 switch (udp_tunnel->prot_type) { 7663 case RTE_ETH_TUNNEL_TYPE_VXLAN: 7664 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port); 7665 break; 7666 7667 case RTE_ETH_TUNNEL_TYPE_GENEVE: 7668 case RTE_ETH_TUNNEL_TYPE_TEREDO: 7669 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 7670 ret = -EINVAL; 7671 break; 7672 7673 default: 7674 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7675 ret = -EINVAL; 7676 break; 7677 } 7678 7679 return ret; 7680 } 7681 7682 /* Remove UDP tunneling port */ 7683 static int 7684 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 7685 struct rte_eth_udp_tunnel *udp_tunnel) 7686 { 7687 int ret = 0; 7688 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7689 7690 if (hw->mac.type != ixgbe_mac_X550 && 7691 hw->mac.type != ixgbe_mac_X550EM_x && 7692 hw->mac.type != ixgbe_mac_X550EM_a) { 7693 return -ENOTSUP; 7694 } 7695 7696 if (udp_tunnel == NULL) 7697 return -EINVAL; 7698 7699 switch (udp_tunnel->prot_type) { 7700 case RTE_ETH_TUNNEL_TYPE_VXLAN: 7701 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port); 7702 break; 7703 case RTE_ETH_TUNNEL_TYPE_GENEVE: 7704 case RTE_ETH_TUNNEL_TYPE_TEREDO: 7705 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 7706 ret = -EINVAL; 7707 break; 7708 default: 7709 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7710 ret = -EINVAL; 7711 break; 7712 } 7713 7714 return ret; 7715 } 7716 7717 static int 7718 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev) 7719 { 7720 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7721 int ret; 7722 7723 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) { 7724 case IXGBE_SUCCESS: 7725 ret = 0; 7726 break; 7727 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 7728 ret = -ENOTSUP; 7729 break; 7730 default: 7731 ret = -EAGAIN; 7732 break; 7733 } 7734 7735 return ret; 7736 } 7737 7738 static int 7739 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev) 7740 { 7741 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7742 int ret; 7743 7744 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) { 7745 case IXGBE_SUCCESS: 7746 ret = 0; 7747 break; 7748 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 7749 ret = -ENOTSUP; 7750 break; 7751 default: 7752 ret = -EAGAIN; 7753 break; 7754 } 7755 7756 return ret; 7757 } 7758 7759 static int 7760 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev) 7761 { 7762 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7763 int ret; 7764 int mode = IXGBEVF_XCAST_MODE_ALLMULTI; 7765 7766 switch (hw->mac.ops.update_xcast_mode(hw, mode)) { 7767 case IXGBE_SUCCESS: 7768 ret = 0; 7769 break; 7770 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 7771 ret = -ENOTSUP; 7772 break; 7773 default: 7774 ret = -EAGAIN; 7775 break; 7776 } 7777 7778 return ret; 7779 } 7780 7781 static int 7782 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev) 7783 { 7784 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7785 int ret; 7786 7787 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) { 7788 case IXGBE_SUCCESS: 7789 ret = 0; 7790 break; 7791 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 7792 ret = -ENOTSUP; 7793 break; 7794 default: 7795 ret = -EAGAIN; 7796 break; 7797 } 7798 7799 return ret; 7800 } 7801 7802 static void ixgbevf_mbx_process(struct rte_eth_dev *dev) 7803 { 7804 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7805 u32 in_msg = 0; 7806 7807 /* peek the message first */ 7808 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM); 7809 7810 /* PF reset VF event */ 7811 if (in_msg == IXGBE_PF_CONTROL_MSG) { 7812 /* dummy mbx read to ack pf */ 7813 if (ixgbe_read_mbx(hw, &in_msg, 1, 0)) 7814 return; 7815 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 7816 NULL); 7817 } 7818 } 7819 7820 static int 7821 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev) 7822 { 7823 uint32_t eicr; 7824 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7825 struct ixgbe_interrupt *intr = 7826 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 7827 ixgbevf_intr_disable(dev); 7828 7829 /* read-on-clear nic registers here */ 7830 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR); 7831 intr->flags = 0; 7832 7833 /* only one misc vector supported - mailbox */ 7834 eicr &= IXGBE_VTEICR_MASK; 7835 if (eicr == IXGBE_MISC_VEC_ID) 7836 intr->flags |= IXGBE_FLAG_MAILBOX; 7837 7838 return 0; 7839 } 7840 7841 static int 7842 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev) 7843 { 7844 struct ixgbe_interrupt *intr = 7845 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 7846 7847 if (intr->flags & IXGBE_FLAG_MAILBOX) { 7848 ixgbevf_mbx_process(dev); 7849 intr->flags &= ~IXGBE_FLAG_MAILBOX; 7850 } 7851 7852 ixgbevf_intr_enable(dev); 7853 7854 return 0; 7855 } 7856 7857 static void 7858 ixgbevf_dev_interrupt_handler(void *param) 7859 { 7860 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 7861 7862 ixgbevf_dev_interrupt_get_status(dev); 7863 ixgbevf_dev_interrupt_action(dev); 7864 } 7865 7866 /** 7867 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path 7868 * @hw: pointer to hardware structure 7869 * 7870 * Stops the transmit data path and waits for the HW to internally empty 7871 * the Tx security block 7872 **/ 7873 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw) 7874 { 7875 #define IXGBE_MAX_SECTX_POLL 40 7876 7877 int i; 7878 int sectxreg; 7879 7880 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 7881 sectxreg |= IXGBE_SECTXCTRL_TX_DIS; 7882 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 7883 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) { 7884 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT); 7885 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY) 7886 break; 7887 /* Use interrupt-safe sleep just in case */ 7888 usec_delay(1000); 7889 } 7890 7891 /* For informational purposes only */ 7892 if (i >= IXGBE_MAX_SECTX_POLL) 7893 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security " 7894 "path fully disabled. Continuing with init."); 7895 7896 return IXGBE_SUCCESS; 7897 } 7898 7899 /** 7900 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path 7901 * @hw: pointer to hardware structure 7902 * 7903 * Enables the transmit data path. 7904 **/ 7905 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw) 7906 { 7907 uint32_t sectxreg; 7908 7909 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 7910 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS; 7911 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 7912 IXGBE_WRITE_FLUSH(hw); 7913 7914 return IXGBE_SUCCESS; 7915 } 7916 7917 /* restore n-tuple filter */ 7918 static inline void 7919 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev) 7920 { 7921 struct ixgbe_filter_info *filter_info = 7922 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 7923 struct ixgbe_5tuple_filter *node; 7924 7925 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) { 7926 ixgbe_inject_5tuple_filter(dev, node); 7927 } 7928 } 7929 7930 /* restore ethernet type filter */ 7931 static inline void 7932 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev) 7933 { 7934 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7935 struct ixgbe_filter_info *filter_info = 7936 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 7937 int i; 7938 7939 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 7940 if (filter_info->ethertype_mask & (1 << i)) { 7941 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 7942 filter_info->ethertype_filters[i].etqf); 7943 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 7944 filter_info->ethertype_filters[i].etqs); 7945 IXGBE_WRITE_FLUSH(hw); 7946 } 7947 } 7948 } 7949 7950 /* restore SYN filter */ 7951 static inline void 7952 ixgbe_syn_filter_restore(struct rte_eth_dev *dev) 7953 { 7954 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7955 struct ixgbe_filter_info *filter_info = 7956 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 7957 uint32_t synqf; 7958 7959 synqf = filter_info->syn_info; 7960 7961 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 7962 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 7963 IXGBE_WRITE_FLUSH(hw); 7964 } 7965 } 7966 7967 /* restore L2 tunnel filter */ 7968 static inline void 7969 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev) 7970 { 7971 struct ixgbe_l2_tn_info *l2_tn_info = 7972 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7973 struct ixgbe_l2_tn_filter *node; 7974 struct ixgbe_l2_tunnel_conf l2_tn_conf; 7975 7976 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) { 7977 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type; 7978 l2_tn_conf.tunnel_id = node->key.tn_id; 7979 l2_tn_conf.pool = node->pool; 7980 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE); 7981 } 7982 } 7983 7984 /* restore rss filter */ 7985 static inline void 7986 ixgbe_rss_filter_restore(struct rte_eth_dev *dev) 7987 { 7988 struct ixgbe_filter_info *filter_info = 7989 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 7990 7991 if (filter_info->rss_info.conf.queue_num) 7992 ixgbe_config_rss_filter(dev, 7993 &filter_info->rss_info, TRUE); 7994 } 7995 7996 static int 7997 ixgbe_filter_restore(struct rte_eth_dev *dev) 7998 { 7999 ixgbe_ntuple_filter_restore(dev); 8000 ixgbe_ethertype_filter_restore(dev); 8001 ixgbe_syn_filter_restore(dev); 8002 ixgbe_fdir_filter_restore(dev); 8003 ixgbe_l2_tn_filter_restore(dev); 8004 ixgbe_rss_filter_restore(dev); 8005 8006 return 0; 8007 } 8008 8009 static void 8010 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev) 8011 { 8012 struct ixgbe_l2_tn_info *l2_tn_info = 8013 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8014 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8015 8016 if (l2_tn_info->e_tag_en) 8017 (void)ixgbe_e_tag_enable(hw); 8018 8019 if (l2_tn_info->e_tag_fwd_en) 8020 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1); 8021 8022 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type); 8023 } 8024 8025 /* remove all the n-tuple filters */ 8026 void 8027 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev) 8028 { 8029 struct ixgbe_filter_info *filter_info = 8030 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8031 struct ixgbe_5tuple_filter *p_5tuple; 8032 8033 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) 8034 ixgbe_remove_5tuple_filter(dev, p_5tuple); 8035 } 8036 8037 /* remove all the ether type filters */ 8038 void 8039 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev) 8040 { 8041 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8042 struct ixgbe_filter_info *filter_info = 8043 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8044 int i; 8045 8046 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8047 if (filter_info->ethertype_mask & (1 << i) && 8048 !filter_info->ethertype_filters[i].conf) { 8049 (void)ixgbe_ethertype_filter_remove(filter_info, 8050 (uint8_t)i); 8051 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0); 8052 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0); 8053 IXGBE_WRITE_FLUSH(hw); 8054 } 8055 } 8056 } 8057 8058 /* remove the SYN filter */ 8059 void 8060 ixgbe_clear_syn_filter(struct rte_eth_dev *dev) 8061 { 8062 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8063 struct ixgbe_filter_info *filter_info = 8064 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8065 8066 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) { 8067 filter_info->syn_info = 0; 8068 8069 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0); 8070 IXGBE_WRITE_FLUSH(hw); 8071 } 8072 } 8073 8074 /* remove all the L2 tunnel filters */ 8075 int 8076 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev) 8077 { 8078 struct ixgbe_l2_tn_info *l2_tn_info = 8079 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8080 struct ixgbe_l2_tn_filter *l2_tn_filter; 8081 struct ixgbe_l2_tunnel_conf l2_tn_conf; 8082 int ret = 0; 8083 8084 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 8085 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type; 8086 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id; 8087 l2_tn_conf.pool = l2_tn_filter->pool; 8088 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf); 8089 if (ret < 0) 8090 return ret; 8091 } 8092 8093 return 0; 8094 } 8095 8096 void 8097 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev, 8098 struct ixgbe_macsec_setting *macsec_setting) 8099 { 8100 struct ixgbe_macsec_setting *macsec = 8101 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 8102 8103 macsec->offload_en = macsec_setting->offload_en; 8104 macsec->encrypt_en = macsec_setting->encrypt_en; 8105 macsec->replayprotect_en = macsec_setting->replayprotect_en; 8106 } 8107 8108 void 8109 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev) 8110 { 8111 struct ixgbe_macsec_setting *macsec = 8112 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 8113 8114 macsec->offload_en = 0; 8115 macsec->encrypt_en = 0; 8116 macsec->replayprotect_en = 0; 8117 } 8118 8119 void 8120 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev, 8121 struct ixgbe_macsec_setting *macsec_setting) 8122 { 8123 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8124 uint32_t ctrl; 8125 uint8_t en = macsec_setting->encrypt_en; 8126 uint8_t rp = macsec_setting->replayprotect_en; 8127 8128 /** 8129 * Workaround: 8130 * As no ixgbe_disable_sec_rx_path equivalent is 8131 * implemented for tx in the base code, and we are 8132 * not allowed to modify the base code in DPDK, so 8133 * just call the hand-written one directly for now. 8134 * The hardware support has been checked by 8135 * ixgbe_disable_sec_rx_path(). 8136 */ 8137 ixgbe_disable_sec_tx_path_generic(hw); 8138 8139 /* Enable Ethernet CRC (required by MACsec offload) */ 8140 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0); 8141 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP; 8142 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl); 8143 8144 /* Enable the TX and RX crypto engines */ 8145 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8146 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS; 8147 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl); 8148 8149 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 8150 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS; 8151 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl); 8152 8153 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 8154 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK; 8155 ctrl |= 0x3; 8156 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl); 8157 8158 /* Enable SA lookup */ 8159 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL); 8160 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK; 8161 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT : 8162 IXGBE_LSECTXCTRL_AUTH; 8163 ctrl |= IXGBE_LSECTXCTRL_AISCI; 8164 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK; 8165 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK; 8166 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl); 8167 8168 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL); 8169 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK; 8170 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT; 8171 ctrl &= ~IXGBE_LSECRXCTRL_PLSH; 8172 if (rp) 8173 ctrl |= IXGBE_LSECRXCTRL_RP; 8174 else 8175 ctrl &= ~IXGBE_LSECRXCTRL_RP; 8176 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl); 8177 8178 /* Start the data paths */ 8179 ixgbe_enable_sec_rx_path(hw); 8180 /** 8181 * Workaround: 8182 * As no ixgbe_enable_sec_rx_path equivalent is 8183 * implemented for tx in the base code, and we are 8184 * not allowed to modify the base code in DPDK, so 8185 * just call the hand-written one directly for now. 8186 */ 8187 ixgbe_enable_sec_tx_path_generic(hw); 8188 } 8189 8190 void 8191 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev) 8192 { 8193 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8194 uint32_t ctrl; 8195 8196 /** 8197 * Workaround: 8198 * As no ixgbe_disable_sec_rx_path equivalent is 8199 * implemented for tx in the base code, and we are 8200 * not allowed to modify the base code in DPDK, so 8201 * just call the hand-written one directly for now. 8202 * The hardware support has been checked by 8203 * ixgbe_disable_sec_rx_path(). 8204 */ 8205 ixgbe_disable_sec_tx_path_generic(hw); 8206 8207 /* Disable the TX and RX crypto engines */ 8208 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8209 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS; 8210 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl); 8211 8212 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 8213 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS; 8214 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl); 8215 8216 /* Disable SA lookup */ 8217 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL); 8218 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK; 8219 ctrl |= IXGBE_LSECTXCTRL_DISABLE; 8220 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl); 8221 8222 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL); 8223 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK; 8224 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT; 8225 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl); 8226 8227 /* Start the data paths */ 8228 ixgbe_enable_sec_rx_path(hw); 8229 /** 8230 * Workaround: 8231 * As no ixgbe_enable_sec_rx_path equivalent is 8232 * implemented for tx in the base code, and we are 8233 * not allowed to modify the base code in DPDK, so 8234 * just call the hand-written one directly for now. 8235 */ 8236 ixgbe_enable_sec_tx_path_generic(hw); 8237 } 8238 8239 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd); 8240 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map); 8241 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 8242 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd); 8243 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map); 8244 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci"); 8245 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf, 8246 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>"); 8247 8248 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_init, init, NOTICE); 8249 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_driver, driver, NOTICE); 8250 8251 #ifdef RTE_ETHDEV_DEBUG_RX 8252 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_rx, rx, DEBUG); 8253 #endif 8254 #ifdef RTE_ETHDEV_DEBUG_TX 8255 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_tx, tx, DEBUG); 8256 #endif 8257