1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <inttypes.h> 13 #include <rte_string_fns.h> 14 #include <rte_byteorder.h> 15 #include <rte_common.h> 16 #include <rte_cycles.h> 17 18 #include <rte_interrupts.h> 19 #include <rte_log.h> 20 #include <rte_debug.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_branch_prediction.h> 24 #include <rte_memory.h> 25 #include <rte_kvargs.h> 26 #include <rte_eal.h> 27 #include <rte_alarm.h> 28 #include <rte_ether.h> 29 #include <ethdev_driver.h> 30 #include <ethdev_pci.h> 31 #include <rte_malloc.h> 32 #include <rte_random.h> 33 #include <rte_dev.h> 34 #include <rte_hash_crc.h> 35 #ifdef RTE_LIB_SECURITY 36 #include <rte_security_driver.h> 37 #endif 38 39 #include "ixgbe_logs.h" 40 #include "base/ixgbe_api.h" 41 #include "base/ixgbe_vf.h" 42 #include "base/ixgbe_common.h" 43 #include "ixgbe_ethdev.h" 44 #include "ixgbe_bypass.h" 45 #include "ixgbe_rxtx.h" 46 #include "base/ixgbe_type.h" 47 #include "base/ixgbe_phy.h" 48 #include "base/ixgbe_osdep.h" 49 #include "ixgbe_regs.h" 50 51 /* 52 * High threshold controlling when to start sending XOFF frames. Must be at 53 * least 8 bytes less than receive packet buffer size. This value is in units 54 * of 1024 bytes. 55 */ 56 #define IXGBE_FC_HI 0x80 57 58 /* 59 * Low threshold controlling when to start sending XON frames. This value is 60 * in units of 1024 bytes. 61 */ 62 #define IXGBE_FC_LO 0x40 63 64 /* Timer value included in XOFF frames. */ 65 #define IXGBE_FC_PAUSE 0x680 66 67 /*Default value of Max Rx Queue*/ 68 #define IXGBE_MAX_RX_QUEUE_NUM 128 69 70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */ 71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */ 72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */ 73 74 #define IXGBE_MMW_SIZE_DEFAULT 0x4 75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14 76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */ 77 78 /* 79 * Default values for RX/TX configuration 80 */ 81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32 82 #define IXGBE_DEFAULT_RX_PTHRESH 8 83 #define IXGBE_DEFAULT_RX_HTHRESH 8 84 #define IXGBE_DEFAULT_RX_WTHRESH 0 85 86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32 87 #define IXGBE_DEFAULT_TX_PTHRESH 32 88 #define IXGBE_DEFAULT_TX_HTHRESH 0 89 #define IXGBE_DEFAULT_TX_WTHRESH 0 90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32 91 92 /* Bit shift and mask */ 93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2) 94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t) 95 #define IXGBE_8_BIT_WIDTH CHAR_BIT 96 #define IXGBE_8_BIT_MASK UINT8_MAX 97 98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */ 99 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0])) 101 102 /* Additional timesync values. */ 103 #define NSEC_PER_SEC 1000000000L 104 #define IXGBE_INCVAL_10GB 0x66666666 105 #define IXGBE_INCVAL_1GB 0x40000000 106 #define IXGBE_INCVAL_100 0x50000000 107 #define IXGBE_INCVAL_SHIFT_10GB 28 108 #define IXGBE_INCVAL_SHIFT_1GB 24 109 #define IXGBE_INCVAL_SHIFT_100 21 110 #define IXGBE_INCVAL_SHIFT_82599 7 111 #define IXGBE_INCPER_SHIFT_82599 24 112 113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL 114 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000 117 #define IXGBE_ETAG_ETYPE 0x00005084 118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff 119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000 120 #define IXGBE_RAH_ADTYPE 0x40000000 121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff 122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */ 125 #define IXGBE_QDE_STRIP_TAG 0x00000004 126 #define IXGBE_VTEICR_MASK 0x07 127 128 #define IXGBE_EXVET_VET_EXT_SHIFT 16 129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000 130 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk" 132 133 static const char * const ixgbevf_valid_arguments[] = { 134 IXGBEVF_DEVARG_PFLINK_FULLCHK, 135 NULL 136 }; 137 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev); 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev); 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev); 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev); 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev); 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev); 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev); 146 static int ixgbe_dev_start(struct rte_eth_dev *dev); 147 static int ixgbe_dev_stop(struct rte_eth_dev *dev); 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev); 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev); 150 static int ixgbe_dev_close(struct rte_eth_dev *dev); 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev); 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev, 157 int wait_to_complete); 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev, 159 struct rte_eth_stats *stats); 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev, 161 struct rte_eth_xstat *xstats, unsigned n); 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, 163 struct rte_eth_xstat *xstats, unsigned n); 164 static int 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 166 uint64_t *values, unsigned int n); 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev); 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev); 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 170 struct rte_eth_xstat_name *xstats_names, 171 unsigned int size); 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev, 173 struct rte_eth_xstat_name *xstats_names, unsigned limit); 174 static int ixgbe_dev_xstats_get_names_by_id( 175 struct rte_eth_dev *dev, 176 const uint64_t *ids, 177 struct rte_eth_xstat_name *xstats_names, 178 unsigned int limit); 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 180 uint16_t queue_id, 181 uint8_t stat_idx, 182 uint8_t is_rx); 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 184 size_t fw_size); 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev, 186 struct rte_eth_dev_info *dev_info); 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev, 189 struct rte_eth_dev_info *dev_info); 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 191 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev, 193 uint16_t vlan_id, int on); 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 195 enum rte_vlan_type vlan_type, 196 uint16_t tpid_id); 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, 198 uint16_t queue, bool on); 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, 200 int on); 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, 202 int mask); 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask); 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask); 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue); 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue); 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev); 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev); 209 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev); 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev); 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, 213 struct rte_eth_fc_conf *fc_conf); 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, 215 struct rte_eth_fc_conf *fc_conf); 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 217 struct rte_eth_pfc_conf *pfc_conf); 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 219 struct rte_eth_rss_reta_entry64 *reta_conf, 220 uint16_t reta_size); 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 222 struct rte_eth_rss_reta_entry64 *reta_conf, 223 uint16_t reta_size); 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev); 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev); 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev); 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev); 230 static void ixgbe_dev_interrupt_handler(void *param); 231 static void ixgbe_dev_interrupt_delayed_handler(void *param); 232 static void *ixgbe_dev_setup_link_thread_handler(void *param); 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, 234 uint32_t timeout_ms); 235 236 static int ixgbe_add_rar(struct rte_eth_dev *dev, 237 struct rte_ether_addr *mac_addr, 238 uint32_t index, uint32_t pool); 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index); 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, 241 struct rte_ether_addr *mac_addr); 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config); 243 static bool is_device_supported(struct rte_eth_dev *dev, 244 struct rte_pci_driver *drv); 245 246 /* For Virtual Function support */ 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev); 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev); 249 static int ixgbevf_dev_configure(struct rte_eth_dev *dev); 250 static int ixgbevf_dev_start(struct rte_eth_dev *dev); 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev, 252 int wait_to_complete); 253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev); 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev); 255 static int ixgbevf_dev_reset(struct rte_eth_dev *dev); 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev); 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev); 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev, 259 struct rte_eth_stats *stats); 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev); 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, 262 uint16_t vlan_id, int on); 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, 264 uint16_t queue, int on); 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask); 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask); 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on); 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 269 uint16_t queue_id); 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 271 uint16_t queue_id); 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 273 uint8_t queue, uint8_t msix_vector); 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev); 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev); 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev); 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev); 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev); 279 280 /* For Eth VMDQ APIs support */ 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct 282 rte_ether_addr * mac_addr, uint8_t on); 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on); 284 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 285 uint16_t queue_id); 286 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 287 uint16_t queue_id); 288 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 289 uint8_t queue, uint8_t msix_vector); 290 static void ixgbe_configure_msix(struct rte_eth_dev *dev); 291 292 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev, 293 struct rte_ether_addr *mac_addr, 294 uint32_t index, uint32_t pool); 295 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index); 296 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 297 struct rte_ether_addr *mac_addr); 298 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 299 struct ixgbe_5tuple_filter *filter); 300 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 301 struct ixgbe_5tuple_filter *filter); 302 static int ixgbe_dev_flow_ops_get(struct rte_eth_dev *dev, 303 const struct rte_flow_ops **ops); 304 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 305 306 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 307 struct rte_ether_addr *mc_addr_set, 308 uint32_t nb_mc_addr); 309 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 310 struct rte_eth_dcb_info *dcb_info); 311 312 static int ixgbe_get_reg_length(struct rte_eth_dev *dev); 313 static int ixgbe_get_regs(struct rte_eth_dev *dev, 314 struct rte_dev_reg_info *regs); 315 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev); 316 static int ixgbe_get_eeprom(struct rte_eth_dev *dev, 317 struct rte_dev_eeprom_info *eeprom); 318 static int ixgbe_set_eeprom(struct rte_eth_dev *dev, 319 struct rte_dev_eeprom_info *eeprom); 320 321 static int ixgbe_get_module_info(struct rte_eth_dev *dev, 322 struct rte_eth_dev_module_info *modinfo); 323 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 324 struct rte_dev_eeprom_info *info); 325 326 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev); 327 static int ixgbevf_get_regs(struct rte_eth_dev *dev, 328 struct rte_dev_reg_info *regs); 329 330 static int ixgbe_timesync_enable(struct rte_eth_dev *dev); 331 static int ixgbe_timesync_disable(struct rte_eth_dev *dev); 332 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 333 struct timespec *timestamp, 334 uint32_t flags); 335 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 336 struct timespec *timestamp); 337 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 338 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev, 339 struct timespec *timestamp); 340 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev, 341 const struct timespec *timestamp); 342 static void ixgbevf_dev_interrupt_handler(void *param); 343 344 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 345 struct rte_eth_udp_tunnel *udp_tunnel); 346 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 347 struct rte_eth_udp_tunnel *udp_tunnel); 348 static int ixgbe_filter_restore(struct rte_eth_dev *dev); 349 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev); 350 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw); 351 352 /* 353 * Define VF Stats MACRO for Non "cleared on read" register 354 */ 355 #define UPDATE_VF_STAT(reg, last, cur) \ 356 { \ 357 uint32_t latest = IXGBE_READ_REG(hw, reg); \ 358 cur += (latest - last) & UINT_MAX; \ 359 last = latest; \ 360 } 361 362 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \ 363 { \ 364 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \ 365 u64 new_msb = IXGBE_READ_REG(hw, msb); \ 366 u64 latest = ((new_msb << 32) | new_lsb); \ 367 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \ 368 last = latest; \ 369 } 370 371 #define IXGBE_SET_HWSTRIP(h, q) do {\ 372 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 373 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 374 (h)->bitmap[idx] |= 1 << bit;\ 375 } while (0) 376 377 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\ 378 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 379 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 380 (h)->bitmap[idx] &= ~(1 << bit);\ 381 } while (0) 382 383 #define IXGBE_GET_HWSTRIP(h, q, r) do {\ 384 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 385 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 386 (r) = (h)->bitmap[idx] >> bit & 1;\ 387 } while (0) 388 389 /* 390 * The set of PCI devices this driver supports 391 */ 392 static const struct rte_pci_id pci_id_ixgbe_map[] = { 393 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) }, 394 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) }, 395 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) }, 396 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) }, 397 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) }, 398 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) }, 399 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) }, 400 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) }, 401 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) }, 402 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) }, 403 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) }, 404 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) }, 405 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) }, 406 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) }, 407 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) }, 408 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) }, 409 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) }, 410 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) }, 411 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) }, 412 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) }, 413 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) }, 414 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) }, 415 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) }, 416 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) }, 417 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) }, 418 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) }, 419 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) }, 420 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) }, 421 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) }, 422 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) }, 423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) }, 424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) }, 425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) }, 426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) }, 427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) }, 428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) }, 429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) }, 430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) }, 431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) }, 432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) }, 433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) }, 434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) }, 435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) }, 436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) }, 437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) }, 438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) }, 439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) }, 440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) }, 441 #ifdef RTE_LIBRTE_IXGBE_BYPASS 442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) }, 443 #endif 444 { .vendor_id = 0, /* sentinel */ }, 445 }; 446 447 /* 448 * The set of PCI devices this driver supports (for 82599 VF) 449 */ 450 static const struct rte_pci_id pci_id_ixgbevf_map[] = { 451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) }, 452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) }, 453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) }, 454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) }, 455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) }, 456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) }, 457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) }, 458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) }, 459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) }, 460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) }, 461 { .vendor_id = 0, /* sentinel */ }, 462 }; 463 464 static const struct rte_eth_desc_lim rx_desc_lim = { 465 .nb_max = IXGBE_MAX_RING_DESC, 466 .nb_min = IXGBE_MIN_RING_DESC, 467 .nb_align = IXGBE_RXD_ALIGN, 468 }; 469 470 static const struct rte_eth_desc_lim tx_desc_lim = { 471 .nb_max = IXGBE_MAX_RING_DESC, 472 .nb_min = IXGBE_MIN_RING_DESC, 473 .nb_align = IXGBE_TXD_ALIGN, 474 .nb_seg_max = IXGBE_TX_MAX_SEG, 475 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG, 476 }; 477 478 static const struct eth_dev_ops ixgbe_eth_dev_ops = { 479 .dev_configure = ixgbe_dev_configure, 480 .dev_start = ixgbe_dev_start, 481 .dev_stop = ixgbe_dev_stop, 482 .dev_set_link_up = ixgbe_dev_set_link_up, 483 .dev_set_link_down = ixgbe_dev_set_link_down, 484 .dev_close = ixgbe_dev_close, 485 .dev_reset = ixgbe_dev_reset, 486 .promiscuous_enable = ixgbe_dev_promiscuous_enable, 487 .promiscuous_disable = ixgbe_dev_promiscuous_disable, 488 .allmulticast_enable = ixgbe_dev_allmulticast_enable, 489 .allmulticast_disable = ixgbe_dev_allmulticast_disable, 490 .link_update = ixgbe_dev_link_update, 491 .stats_get = ixgbe_dev_stats_get, 492 .xstats_get = ixgbe_dev_xstats_get, 493 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id, 494 .stats_reset = ixgbe_dev_stats_reset, 495 .xstats_reset = ixgbe_dev_xstats_reset, 496 .xstats_get_names = ixgbe_dev_xstats_get_names, 497 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id, 498 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set, 499 .fw_version_get = ixgbe_fw_version_get, 500 .dev_infos_get = ixgbe_dev_info_get, 501 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 502 .mtu_set = ixgbe_dev_mtu_set, 503 .vlan_filter_set = ixgbe_vlan_filter_set, 504 .vlan_tpid_set = ixgbe_vlan_tpid_set, 505 .vlan_offload_set = ixgbe_vlan_offload_set, 506 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set, 507 .rx_queue_start = ixgbe_dev_rx_queue_start, 508 .rx_queue_stop = ixgbe_dev_rx_queue_stop, 509 .tx_queue_start = ixgbe_dev_tx_queue_start, 510 .tx_queue_stop = ixgbe_dev_tx_queue_stop, 511 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 512 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable, 513 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable, 514 .rx_queue_release = ixgbe_dev_rx_queue_release, 515 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 516 .tx_queue_release = ixgbe_dev_tx_queue_release, 517 .dev_led_on = ixgbe_dev_led_on, 518 .dev_led_off = ixgbe_dev_led_off, 519 .flow_ctrl_get = ixgbe_flow_ctrl_get, 520 .flow_ctrl_set = ixgbe_flow_ctrl_set, 521 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set, 522 .mac_addr_add = ixgbe_add_rar, 523 .mac_addr_remove = ixgbe_remove_rar, 524 .mac_addr_set = ixgbe_set_default_mac_addr, 525 .uc_hash_table_set = ixgbe_uc_hash_table_set, 526 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set, 527 .set_queue_rate_limit = ixgbe_set_queue_rate_limit, 528 .reta_update = ixgbe_dev_rss_reta_update, 529 .reta_query = ixgbe_dev_rss_reta_query, 530 .rss_hash_update = ixgbe_dev_rss_hash_update, 531 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 532 .flow_ops_get = ixgbe_dev_flow_ops_get, 533 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 534 .rxq_info_get = ixgbe_rxq_info_get, 535 .txq_info_get = ixgbe_txq_info_get, 536 .timesync_enable = ixgbe_timesync_enable, 537 .timesync_disable = ixgbe_timesync_disable, 538 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp, 539 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp, 540 .get_reg = ixgbe_get_regs, 541 .get_eeprom_length = ixgbe_get_eeprom_length, 542 .get_eeprom = ixgbe_get_eeprom, 543 .set_eeprom = ixgbe_set_eeprom, 544 .get_module_info = ixgbe_get_module_info, 545 .get_module_eeprom = ixgbe_get_module_eeprom, 546 .get_dcb_info = ixgbe_dev_get_dcb_info, 547 .timesync_adjust_time = ixgbe_timesync_adjust_time, 548 .timesync_read_time = ixgbe_timesync_read_time, 549 .timesync_write_time = ixgbe_timesync_write_time, 550 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add, 551 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del, 552 .tm_ops_get = ixgbe_tm_ops_get, 553 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup, 554 .get_monitor_addr = ixgbe_get_monitor_addr, 555 }; 556 557 /* 558 * dev_ops for virtual function, bare necessities for basic vf 559 * operation have been implemented 560 */ 561 static const struct eth_dev_ops ixgbevf_eth_dev_ops = { 562 .dev_configure = ixgbevf_dev_configure, 563 .dev_start = ixgbevf_dev_start, 564 .dev_stop = ixgbevf_dev_stop, 565 .link_update = ixgbevf_dev_link_update, 566 .stats_get = ixgbevf_dev_stats_get, 567 .xstats_get = ixgbevf_dev_xstats_get, 568 .stats_reset = ixgbevf_dev_stats_reset, 569 .xstats_reset = ixgbevf_dev_stats_reset, 570 .xstats_get_names = ixgbevf_dev_xstats_get_names, 571 .dev_close = ixgbevf_dev_close, 572 .dev_reset = ixgbevf_dev_reset, 573 .promiscuous_enable = ixgbevf_dev_promiscuous_enable, 574 .promiscuous_disable = ixgbevf_dev_promiscuous_disable, 575 .allmulticast_enable = ixgbevf_dev_allmulticast_enable, 576 .allmulticast_disable = ixgbevf_dev_allmulticast_disable, 577 .dev_infos_get = ixgbevf_dev_info_get, 578 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 579 .mtu_set = ixgbevf_dev_set_mtu, 580 .vlan_filter_set = ixgbevf_vlan_filter_set, 581 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set, 582 .vlan_offload_set = ixgbevf_vlan_offload_set, 583 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 584 .rx_queue_release = ixgbe_dev_rx_queue_release, 585 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 586 .tx_queue_release = ixgbe_dev_tx_queue_release, 587 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable, 588 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable, 589 .mac_addr_add = ixgbevf_add_mac_addr, 590 .mac_addr_remove = ixgbevf_remove_mac_addr, 591 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 592 .rxq_info_get = ixgbe_rxq_info_get, 593 .txq_info_get = ixgbe_txq_info_get, 594 .mac_addr_set = ixgbevf_set_default_mac_addr, 595 .get_reg = ixgbevf_get_regs, 596 .reta_update = ixgbe_dev_rss_reta_update, 597 .reta_query = ixgbe_dev_rss_reta_query, 598 .rss_hash_update = ixgbe_dev_rss_hash_update, 599 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 600 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup, 601 .get_monitor_addr = ixgbe_get_monitor_addr, 602 }; 603 604 /* store statistics names and its offset in stats structure */ 605 struct rte_ixgbe_xstats_name_off { 606 char name[RTE_ETH_XSTATS_NAME_SIZE]; 607 unsigned offset; 608 }; 609 610 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = { 611 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)}, 612 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)}, 613 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)}, 614 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)}, 615 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)}, 616 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)}, 617 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)}, 618 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)}, 619 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)}, 620 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)}, 621 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)}, 622 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)}, 623 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)}, 624 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)}, 625 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 626 prc1023)}, 627 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 628 prc1522)}, 629 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)}, 630 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)}, 631 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)}, 632 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)}, 633 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)}, 634 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)}, 635 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)}, 636 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)}, 637 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)}, 638 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)}, 639 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)}, 640 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)}, 641 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)}, 642 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)}, 643 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)}, 644 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)}, 645 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 646 ptc1023)}, 647 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 648 ptc1522)}, 649 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)}, 650 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)}, 651 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)}, 652 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)}, 653 654 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats, 655 fdirustat_add)}, 656 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats, 657 fdirustat_remove)}, 658 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats, 659 fdirfstat_fadd)}, 660 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats, 661 fdirfstat_fremove)}, 662 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats, 663 fdirmatch)}, 664 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats, 665 fdirmiss)}, 666 667 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)}, 668 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)}, 669 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, 670 fclast)}, 671 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)}, 672 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)}, 673 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)}, 674 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)}, 675 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats, 676 fcoe_noddp)}, 677 {"rx_fcoe_no_direct_data_placement_ext_buff", 678 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)}, 679 680 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 681 lxontxc)}, 682 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 683 lxonrxc)}, 684 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 685 lxofftxc)}, 686 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 687 lxoffrxc)}, 688 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)}, 689 }; 690 691 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \ 692 sizeof(rte_ixgbe_stats_strings[0])) 693 694 /* MACsec statistics */ 695 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = { 696 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 697 out_pkts_untagged)}, 698 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats, 699 out_pkts_encrypted)}, 700 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats, 701 out_pkts_protected)}, 702 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats, 703 out_octets_encrypted)}, 704 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats, 705 out_octets_protected)}, 706 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 707 in_pkts_untagged)}, 708 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats, 709 in_pkts_badtag)}, 710 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats, 711 in_pkts_nosci)}, 712 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats, 713 in_pkts_unknownsci)}, 714 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats, 715 in_octets_decrypted)}, 716 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats, 717 in_octets_validated)}, 718 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats, 719 in_pkts_unchecked)}, 720 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats, 721 in_pkts_delayed)}, 722 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats, 723 in_pkts_late)}, 724 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats, 725 in_pkts_ok)}, 726 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats, 727 in_pkts_invalid)}, 728 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats, 729 in_pkts_notvalid)}, 730 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats, 731 in_pkts_unusedsa)}, 732 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats, 733 in_pkts_notusingsa)}, 734 }; 735 736 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \ 737 sizeof(rte_ixgbe_macsec_strings[0])) 738 739 /* Per-queue statistics */ 740 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = { 741 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)}, 742 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)}, 743 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)}, 744 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)}, 745 }; 746 747 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \ 748 sizeof(rte_ixgbe_rxq_strings[0])) 749 #define IXGBE_NB_RXQ_PRIO_VALUES 8 750 751 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = { 752 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)}, 753 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)}, 754 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats, 755 pxon2offc)}, 756 }; 757 758 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \ 759 sizeof(rte_ixgbe_txq_strings[0])) 760 #define IXGBE_NB_TXQ_PRIO_VALUES 8 761 762 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = { 763 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)}, 764 }; 765 766 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \ 767 sizeof(rte_ixgbevf_stats_strings[0])) 768 769 /* 770 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h. 771 */ 772 static inline int 773 ixgbe_is_sfp(struct ixgbe_hw *hw) 774 { 775 switch (hw->phy.type) { 776 case ixgbe_phy_sfp_avago: 777 case ixgbe_phy_sfp_ftl: 778 case ixgbe_phy_sfp_intel: 779 case ixgbe_phy_sfp_unknown: 780 case ixgbe_phy_sfp_passive_tyco: 781 case ixgbe_phy_sfp_passive_unknown: 782 return 1; 783 default: 784 return 0; 785 } 786 } 787 788 static inline int32_t 789 ixgbe_pf_reset_hw(struct ixgbe_hw *hw) 790 { 791 uint32_t ctrl_ext; 792 int32_t status; 793 794 status = ixgbe_reset_hw(hw); 795 796 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 797 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 798 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 799 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 800 IXGBE_WRITE_FLUSH(hw); 801 802 if (status == IXGBE_ERR_SFP_NOT_PRESENT) 803 status = IXGBE_SUCCESS; 804 return status; 805 } 806 807 static inline void 808 ixgbe_enable_intr(struct rte_eth_dev *dev) 809 { 810 struct ixgbe_interrupt *intr = 811 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 812 struct ixgbe_hw *hw = 813 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 814 815 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask); 816 IXGBE_WRITE_FLUSH(hw); 817 } 818 819 /* 820 * This function is based on ixgbe_disable_intr() in base/ixgbe.h. 821 */ 822 static void 823 ixgbe_disable_intr(struct ixgbe_hw *hw) 824 { 825 PMD_INIT_FUNC_TRACE(); 826 827 if (hw->mac.type == ixgbe_mac_82598EB) { 828 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0); 829 } else { 830 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000); 831 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0); 832 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0); 833 } 834 IXGBE_WRITE_FLUSH(hw); 835 } 836 837 /* 838 * This function resets queue statistics mapping registers. 839 * From Niantic datasheet, Initialization of Statistics section: 840 * "...if software requires the queue counters, the RQSMR and TQSM registers 841 * must be re-programmed following a device reset. 842 */ 843 static void 844 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw) 845 { 846 uint32_t i; 847 848 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) { 849 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0); 850 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0); 851 } 852 } 853 854 855 static int 856 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 857 uint16_t queue_id, 858 uint8_t stat_idx, 859 uint8_t is_rx) 860 { 861 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8 862 #define NB_QMAP_FIELDS_PER_QSM_REG 4 863 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f 864 865 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 866 struct ixgbe_stat_mapping_registers *stat_mappings = 867 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private); 868 uint32_t qsmr_mask = 0; 869 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK; 870 uint32_t q_map; 871 uint8_t n, offset; 872 873 if ((hw->mac.type != ixgbe_mac_82599EB) && 874 (hw->mac.type != ixgbe_mac_X540) && 875 (hw->mac.type != ixgbe_mac_X550) && 876 (hw->mac.type != ixgbe_mac_X550EM_x) && 877 (hw->mac.type != ixgbe_mac_X550EM_a)) 878 return -ENOSYS; 879 880 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d", 881 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 882 queue_id, stat_idx); 883 884 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG); 885 if (n >= IXGBE_NB_STAT_MAPPING_REGS) { 886 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded"); 887 return -EIO; 888 } 889 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG); 890 891 /* Now clear any previous stat_idx set */ 892 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 893 if (!is_rx) 894 stat_mappings->tqsm[n] &= ~clearing_mask; 895 else 896 stat_mappings->rqsmr[n] &= ~clearing_mask; 897 898 q_map = (uint32_t)stat_idx; 899 q_map &= QMAP_FIELD_RESERVED_BITS_MASK; 900 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 901 if (!is_rx) 902 stat_mappings->tqsm[n] |= qsmr_mask; 903 else 904 stat_mappings->rqsmr[n] |= qsmr_mask; 905 906 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d", 907 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 908 queue_id, stat_idx); 909 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n, 910 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]); 911 912 /* Now write the mapping in the appropriate register */ 913 if (is_rx) { 914 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d", 915 stat_mappings->rqsmr[n], n); 916 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]); 917 } else { 918 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d", 919 stat_mappings->tqsm[n], n); 920 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]); 921 } 922 return 0; 923 } 924 925 static void 926 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev) 927 { 928 struct ixgbe_stat_mapping_registers *stat_mappings = 929 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private); 930 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 931 int i; 932 933 /* write whatever was in stat mapping table to the NIC */ 934 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) { 935 /* rx */ 936 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]); 937 938 /* tx */ 939 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]); 940 } 941 } 942 943 static void 944 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config) 945 { 946 uint8_t i; 947 struct ixgbe_dcb_tc_config *tc; 948 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS; 949 950 dcb_config->num_tcs.pg_tcs = dcb_max_tc; 951 dcb_config->num_tcs.pfc_tcs = dcb_max_tc; 952 for (i = 0; i < dcb_max_tc; i++) { 953 tc = &dcb_config->tc_config[i]; 954 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i; 955 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 956 (uint8_t)(100/dcb_max_tc + (i & 1)); 957 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i; 958 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 959 (uint8_t)(100/dcb_max_tc + (i & 1)); 960 tc->pfc = ixgbe_dcb_pfc_disabled; 961 } 962 963 /* Initialize default user to priority mapping, UPx->TC0 */ 964 tc = &dcb_config->tc_config[0]; 965 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 966 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 967 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) { 968 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100; 969 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100; 970 } 971 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal; 972 dcb_config->pfc_mode_enable = false; 973 dcb_config->vt_mode = true; 974 dcb_config->round_robin_enable = false; 975 /* support all DCB capabilities in 82599 */ 976 dcb_config->support.capabilities = 0xFF; 977 978 /*we only support 4 Tcs for X540, X550 */ 979 if (hw->mac.type == ixgbe_mac_X540 || 980 hw->mac.type == ixgbe_mac_X550 || 981 hw->mac.type == ixgbe_mac_X550EM_x || 982 hw->mac.type == ixgbe_mac_X550EM_a) { 983 dcb_config->num_tcs.pg_tcs = 4; 984 dcb_config->num_tcs.pfc_tcs = 4; 985 } 986 } 987 988 /* 989 * Ensure that all locks are released before first NVM or PHY access 990 */ 991 static void 992 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw) 993 { 994 uint16_t mask; 995 996 /* 997 * Phy lock should not fail in this early stage. If this is the case, 998 * it is due to an improper exit of the application. 999 * So force the release of the faulty lock. Release of common lock 1000 * is done automatically by swfw_sync function. 1001 */ 1002 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func; 1003 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1004 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func); 1005 } 1006 ixgbe_release_swfw_semaphore(hw, mask); 1007 1008 /* 1009 * These ones are more tricky since they are common to all ports; but 1010 * swfw_sync retries last long enough (1s) to be almost sure that if 1011 * lock can not be taken it is due to an improper lock of the 1012 * semaphore. 1013 */ 1014 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM; 1015 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1016 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 1017 } 1018 ixgbe_release_swfw_semaphore(hw, mask); 1019 } 1020 1021 /* 1022 * This function is based on code in ixgbe_attach() in base/ixgbe.c. 1023 * It returns 0 on success. 1024 */ 1025 static int 1026 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) 1027 { 1028 struct ixgbe_adapter *ad = eth_dev->data->dev_private; 1029 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1030 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 1031 struct ixgbe_hw *hw = 1032 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1033 struct ixgbe_vfta *shadow_vfta = 1034 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1035 struct ixgbe_hwstrip *hwstrip = 1036 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1037 struct ixgbe_dcb_config *dcb_config = 1038 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private); 1039 struct ixgbe_filter_info *filter_info = 1040 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1041 struct ixgbe_bw_conf *bw_conf = 1042 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private); 1043 uint32_t ctrl_ext; 1044 uint16_t csum; 1045 int diag, i, ret; 1046 1047 PMD_INIT_FUNC_TRACE(); 1048 1049 ixgbe_dev_macsec_setting_reset(eth_dev); 1050 1051 eth_dev->dev_ops = &ixgbe_eth_dev_ops; 1052 eth_dev->rx_queue_count = ixgbe_dev_rx_queue_count; 1053 eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status; 1054 eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status; 1055 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1056 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1057 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts; 1058 1059 /* 1060 * For secondary processes, we don't initialise any further as primary 1061 * has already done this work. Only check we don't need a different 1062 * RX and TX function. 1063 */ 1064 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1065 struct ixgbe_tx_queue *txq; 1066 /* TX queue function in primary, set by last queue initialized 1067 * Tx queue may not initialized by primary process 1068 */ 1069 if (eth_dev->data->tx_queues) { 1070 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1]; 1071 ixgbe_set_tx_function(eth_dev, txq); 1072 } else { 1073 /* Use default TX function if we get here */ 1074 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. " 1075 "Using default TX function."); 1076 } 1077 1078 ixgbe_set_rx_function(eth_dev); 1079 1080 return 0; 1081 } 1082 1083 rte_atomic32_clear(&ad->link_thread_running); 1084 rte_eth_copy_pci_info(eth_dev, pci_dev); 1085 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1086 1087 /* Vendor and Device ID need to be set before init of shared code */ 1088 hw->device_id = pci_dev->id.device_id; 1089 hw->vendor_id = pci_dev->id.vendor_id; 1090 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1091 hw->allow_unsupported_sfp = 1; 1092 1093 /* Initialize the shared code (base driver) */ 1094 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1095 diag = ixgbe_bypass_init_shared_code(hw); 1096 #else 1097 diag = ixgbe_init_shared_code(hw); 1098 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1099 1100 if (diag != IXGBE_SUCCESS) { 1101 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag); 1102 return -EIO; 1103 } 1104 1105 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 1106 PMD_INIT_LOG(ERR, "\nERROR: " 1107 "Firmware recovery mode detected. Limiting functionality.\n" 1108 "Refer to the Intel(R) Ethernet Adapters and Devices " 1109 "User Guide for details on firmware recovery mode."); 1110 return -EIO; 1111 } 1112 1113 /* pick up the PCI bus settings for reporting later */ 1114 ixgbe_get_bus_info(hw); 1115 1116 /* Unlock any pending hardware semaphore */ 1117 ixgbe_swfw_lock_reset(hw); 1118 1119 #ifdef RTE_LIB_SECURITY 1120 /* Initialize security_ctx only for primary process*/ 1121 if (ixgbe_ipsec_ctx_create(eth_dev)) 1122 return -ENOMEM; 1123 #endif 1124 1125 /* Initialize DCB configuration*/ 1126 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config)); 1127 ixgbe_dcb_init(hw, dcb_config); 1128 /* Get Hardware Flow Control setting */ 1129 hw->fc.requested_mode = ixgbe_fc_none; 1130 hw->fc.current_mode = ixgbe_fc_none; 1131 hw->fc.pause_time = IXGBE_FC_PAUSE; 1132 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 1133 hw->fc.low_water[i] = IXGBE_FC_LO; 1134 hw->fc.high_water[i] = IXGBE_FC_HI; 1135 } 1136 hw->fc.send_xon = 1; 1137 1138 /* Make sure we have a good EEPROM before we read from it */ 1139 diag = ixgbe_validate_eeprom_checksum(hw, &csum); 1140 if (diag != IXGBE_SUCCESS) { 1141 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag); 1142 return -EIO; 1143 } 1144 1145 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1146 diag = ixgbe_bypass_init_hw(hw); 1147 #else 1148 diag = ixgbe_init_hw(hw); 1149 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1150 1151 /* 1152 * Devices with copper phys will fail to initialise if ixgbe_init_hw() 1153 * is called too soon after the kernel driver unbinding/binding occurs. 1154 * The failure occurs in ixgbe_identify_phy_generic() for all devices, 1155 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is 1156 * also called. See ixgbe_identify_phy_82599(). The reason for the 1157 * failure is not known, and only occuts when virtualisation features 1158 * are disabled in the bios. A delay of 100ms was found to be enough by 1159 * trial-and-error, and is doubled to be safe. 1160 */ 1161 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) { 1162 rte_delay_ms(200); 1163 diag = ixgbe_init_hw(hw); 1164 } 1165 1166 if (diag == IXGBE_ERR_SFP_NOT_PRESENT) 1167 diag = IXGBE_SUCCESS; 1168 1169 if (diag == IXGBE_ERR_EEPROM_VERSION) { 1170 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/" 1171 "LOM. Please be aware there may be issues associated " 1172 "with your hardware."); 1173 PMD_INIT_LOG(ERR, "If you are experiencing problems " 1174 "please contact your Intel or hardware representative " 1175 "who provided you with this hardware."); 1176 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED) 1177 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module"); 1178 if (diag) { 1179 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag); 1180 return -EIO; 1181 } 1182 1183 /* Reset the hw statistics */ 1184 ixgbe_dev_stats_reset(eth_dev); 1185 1186 /* disable interrupt */ 1187 ixgbe_disable_intr(hw); 1188 1189 /* reset mappings for queue statistics hw counters*/ 1190 ixgbe_reset_qstat_mappings(hw); 1191 1192 /* Allocate memory for storing MAC addresses */ 1193 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN * 1194 hw->mac.num_rar_entries, 0); 1195 if (eth_dev->data->mac_addrs == NULL) { 1196 PMD_INIT_LOG(ERR, 1197 "Failed to allocate %u bytes needed to store " 1198 "MAC addresses", 1199 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1200 return -ENOMEM; 1201 } 1202 /* Copy the permanent MAC address */ 1203 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr, 1204 ð_dev->data->mac_addrs[0]); 1205 1206 /* Allocate memory for storing hash filter MAC addresses */ 1207 eth_dev->data->hash_mac_addrs = rte_zmalloc( 1208 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0); 1209 if (eth_dev->data->hash_mac_addrs == NULL) { 1210 PMD_INIT_LOG(ERR, 1211 "Failed to allocate %d bytes needed to store MAC addresses", 1212 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC); 1213 rte_free(eth_dev->data->mac_addrs); 1214 eth_dev->data->mac_addrs = NULL; 1215 return -ENOMEM; 1216 } 1217 1218 /* initialize the vfta */ 1219 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1220 1221 /* initialize the hw strip bitmap*/ 1222 memset(hwstrip, 0, sizeof(*hwstrip)); 1223 1224 /* initialize PF if max_vfs not zero */ 1225 ret = ixgbe_pf_host_init(eth_dev); 1226 if (ret) 1227 goto err_pf_host_init; 1228 1229 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 1230 /* let hardware know driver is loaded */ 1231 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD; 1232 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 1233 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 1234 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 1235 IXGBE_WRITE_FLUSH(hw); 1236 1237 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 1238 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d", 1239 (int) hw->mac.type, (int) hw->phy.type, 1240 (int) hw->phy.sfp_type); 1241 else 1242 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d", 1243 (int) hw->mac.type, (int) hw->phy.type); 1244 1245 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 1246 eth_dev->data->port_id, pci_dev->id.vendor_id, 1247 pci_dev->id.device_id); 1248 1249 rte_intr_callback_register(intr_handle, 1250 ixgbe_dev_interrupt_handler, eth_dev); 1251 1252 /* enable uio/vfio intr/eventfd mapping */ 1253 rte_intr_enable(intr_handle); 1254 1255 /* enable support intr */ 1256 ixgbe_enable_intr(eth_dev); 1257 1258 /* initialize filter info */ 1259 memset(filter_info, 0, 1260 sizeof(struct ixgbe_filter_info)); 1261 1262 /* initialize 5tuple filter list */ 1263 TAILQ_INIT(&filter_info->fivetuple_list); 1264 1265 /* initialize flow director filter list & hash */ 1266 ret = ixgbe_fdir_filter_init(eth_dev); 1267 if (ret) 1268 goto err_fdir_filter_init; 1269 1270 /* initialize l2 tunnel filter list & hash */ 1271 ret = ixgbe_l2_tn_filter_init(eth_dev); 1272 if (ret) 1273 goto err_l2_tn_filter_init; 1274 1275 /* initialize flow filter lists */ 1276 ixgbe_filterlist_init(); 1277 1278 /* initialize bandwidth configuration info */ 1279 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf)); 1280 1281 /* initialize Traffic Manager configuration */ 1282 ixgbe_tm_conf_init(eth_dev); 1283 1284 return 0; 1285 1286 err_l2_tn_filter_init: 1287 ixgbe_fdir_filter_uninit(eth_dev); 1288 err_fdir_filter_init: 1289 ixgbe_disable_intr(hw); 1290 rte_intr_disable(intr_handle); 1291 rte_intr_callback_unregister(intr_handle, 1292 ixgbe_dev_interrupt_handler, eth_dev); 1293 ixgbe_pf_host_uninit(eth_dev); 1294 err_pf_host_init: 1295 rte_free(eth_dev->data->mac_addrs); 1296 eth_dev->data->mac_addrs = NULL; 1297 rte_free(eth_dev->data->hash_mac_addrs); 1298 eth_dev->data->hash_mac_addrs = NULL; 1299 return ret; 1300 } 1301 1302 static int 1303 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1304 { 1305 PMD_INIT_FUNC_TRACE(); 1306 1307 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1308 return 0; 1309 1310 ixgbe_dev_close(eth_dev); 1311 1312 return 0; 1313 } 1314 1315 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev) 1316 { 1317 struct ixgbe_filter_info *filter_info = 1318 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1319 struct ixgbe_5tuple_filter *p_5tuple; 1320 1321 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) { 1322 TAILQ_REMOVE(&filter_info->fivetuple_list, 1323 p_5tuple, 1324 entries); 1325 rte_free(p_5tuple); 1326 } 1327 memset(filter_info->fivetuple_mask, 0, 1328 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE); 1329 1330 return 0; 1331 } 1332 1333 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev) 1334 { 1335 struct ixgbe_hw_fdir_info *fdir_info = 1336 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1337 struct ixgbe_fdir_filter *fdir_filter; 1338 1339 rte_free(fdir_info->hash_map); 1340 rte_hash_free(fdir_info->hash_handle); 1341 1342 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 1343 TAILQ_REMOVE(&fdir_info->fdir_list, 1344 fdir_filter, 1345 entries); 1346 rte_free(fdir_filter); 1347 } 1348 1349 return 0; 1350 } 1351 1352 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev) 1353 { 1354 struct ixgbe_l2_tn_info *l2_tn_info = 1355 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1356 struct ixgbe_l2_tn_filter *l2_tn_filter; 1357 1358 rte_free(l2_tn_info->hash_map); 1359 rte_hash_free(l2_tn_info->hash_handle); 1360 1361 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 1362 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, 1363 l2_tn_filter, 1364 entries); 1365 rte_free(l2_tn_filter); 1366 } 1367 1368 return 0; 1369 } 1370 1371 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev) 1372 { 1373 struct ixgbe_hw_fdir_info *fdir_info = 1374 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1375 char fdir_hash_name[RTE_HASH_NAMESIZE]; 1376 struct rte_hash_parameters fdir_hash_params = { 1377 .name = fdir_hash_name, 1378 .entries = IXGBE_MAX_FDIR_FILTER_NUM, 1379 .key_len = sizeof(union ixgbe_atr_input), 1380 .hash_func = rte_hash_crc, 1381 .hash_func_init_val = 0, 1382 .socket_id = rte_socket_id(), 1383 }; 1384 1385 TAILQ_INIT(&fdir_info->fdir_list); 1386 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 1387 "fdir_%s", eth_dev->device->name); 1388 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params); 1389 if (!fdir_info->hash_handle) { 1390 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 1391 return -EINVAL; 1392 } 1393 fdir_info->hash_map = rte_zmalloc("ixgbe", 1394 sizeof(struct ixgbe_fdir_filter *) * 1395 IXGBE_MAX_FDIR_FILTER_NUM, 1396 0); 1397 if (!fdir_info->hash_map) { 1398 PMD_INIT_LOG(ERR, 1399 "Failed to allocate memory for fdir hash map!"); 1400 rte_hash_free(fdir_info->hash_handle); 1401 return -ENOMEM; 1402 } 1403 fdir_info->mask_added = FALSE; 1404 1405 return 0; 1406 } 1407 1408 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) 1409 { 1410 struct ixgbe_l2_tn_info *l2_tn_info = 1411 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1412 char l2_tn_hash_name[RTE_HASH_NAMESIZE]; 1413 struct rte_hash_parameters l2_tn_hash_params = { 1414 .name = l2_tn_hash_name, 1415 .entries = IXGBE_MAX_L2_TN_FILTER_NUM, 1416 .key_len = sizeof(struct ixgbe_l2_tn_key), 1417 .hash_func = rte_hash_crc, 1418 .hash_func_init_val = 0, 1419 .socket_id = rte_socket_id(), 1420 }; 1421 1422 TAILQ_INIT(&l2_tn_info->l2_tn_list); 1423 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE, 1424 "l2_tn_%s", eth_dev->device->name); 1425 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params); 1426 if (!l2_tn_info->hash_handle) { 1427 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!"); 1428 return -EINVAL; 1429 } 1430 l2_tn_info->hash_map = rte_zmalloc("ixgbe", 1431 sizeof(struct ixgbe_l2_tn_filter *) * 1432 IXGBE_MAX_L2_TN_FILTER_NUM, 1433 0); 1434 if (!l2_tn_info->hash_map) { 1435 PMD_INIT_LOG(ERR, 1436 "Failed to allocate memory for L2 TN hash map!"); 1437 rte_hash_free(l2_tn_info->hash_handle); 1438 return -ENOMEM; 1439 } 1440 l2_tn_info->e_tag_en = FALSE; 1441 l2_tn_info->e_tag_fwd_en = FALSE; 1442 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG; 1443 1444 return 0; 1445 } 1446 /* 1447 * Negotiate mailbox API version with the PF. 1448 * After reset API version is always set to the basic one (ixgbe_mbox_api_10). 1449 * Then we try to negotiate starting with the most recent one. 1450 * If all negotiation attempts fail, then we will proceed with 1451 * the default one (ixgbe_mbox_api_10). 1452 */ 1453 static void 1454 ixgbevf_negotiate_api(struct ixgbe_hw *hw) 1455 { 1456 int32_t i; 1457 1458 /* start with highest supported, proceed down */ 1459 static const enum ixgbe_pfvf_api_rev sup_ver[] = { 1460 ixgbe_mbox_api_13, 1461 ixgbe_mbox_api_12, 1462 ixgbe_mbox_api_11, 1463 ixgbe_mbox_api_10, 1464 }; 1465 1466 for (i = 0; 1467 i != RTE_DIM(sup_ver) && 1468 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0; 1469 i++) 1470 ; 1471 } 1472 1473 static void 1474 generate_random_mac_addr(struct rte_ether_addr *mac_addr) 1475 { 1476 uint64_t random; 1477 1478 /* Set Organizationally Unique Identifier (OUI) prefix. */ 1479 mac_addr->addr_bytes[0] = 0x00; 1480 mac_addr->addr_bytes[1] = 0x09; 1481 mac_addr->addr_bytes[2] = 0xC0; 1482 /* Force indication of locally assigned MAC address. */ 1483 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR; 1484 /* Generate the last 3 bytes of the MAC address with a random number. */ 1485 random = rte_rand(); 1486 memcpy(&mac_addr->addr_bytes[3], &random, 3); 1487 } 1488 1489 static int 1490 devarg_handle_int(__rte_unused const char *key, const char *value, 1491 void *extra_args) 1492 { 1493 uint16_t *n = extra_args; 1494 1495 if (value == NULL || extra_args == NULL) 1496 return -EINVAL; 1497 1498 *n = (uint16_t)strtoul(value, NULL, 0); 1499 if (*n == USHRT_MAX && errno == ERANGE) 1500 return -1; 1501 1502 return 0; 1503 } 1504 1505 static void 1506 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter, 1507 struct rte_devargs *devargs) 1508 { 1509 struct rte_kvargs *kvlist; 1510 uint16_t pflink_fullchk; 1511 1512 if (devargs == NULL) 1513 return; 1514 1515 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments); 1516 if (kvlist == NULL) 1517 return; 1518 1519 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 && 1520 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK, 1521 devarg_handle_int, &pflink_fullchk) == 0 && 1522 pflink_fullchk == 1) 1523 adapter->pflink_fullchk = 1; 1524 1525 rte_kvargs_free(kvlist); 1526 } 1527 1528 /* 1529 * Virtual Function device init 1530 */ 1531 static int 1532 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev) 1533 { 1534 int diag; 1535 uint32_t tc, tcs; 1536 struct ixgbe_adapter *ad = eth_dev->data->dev_private; 1537 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1538 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 1539 struct ixgbe_hw *hw = 1540 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1541 struct ixgbe_vfta *shadow_vfta = 1542 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1543 struct ixgbe_hwstrip *hwstrip = 1544 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1545 struct rte_ether_addr *perm_addr = 1546 (struct rte_ether_addr *)hw->mac.perm_addr; 1547 1548 PMD_INIT_FUNC_TRACE(); 1549 1550 eth_dev->dev_ops = &ixgbevf_eth_dev_ops; 1551 eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status; 1552 eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status; 1553 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1554 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1555 1556 /* for secondary processes, we don't initialise any further as primary 1557 * has already done this work. Only check we don't need a different 1558 * RX function 1559 */ 1560 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1561 struct ixgbe_tx_queue *txq; 1562 /* TX queue function in primary, set by last queue initialized 1563 * Tx queue may not initialized by primary process 1564 */ 1565 if (eth_dev->data->tx_queues) { 1566 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1]; 1567 ixgbe_set_tx_function(eth_dev, txq); 1568 } else { 1569 /* Use default TX function if we get here */ 1570 PMD_INIT_LOG(NOTICE, 1571 "No TX queues configured yet. Using default TX function."); 1572 } 1573 1574 ixgbe_set_rx_function(eth_dev); 1575 1576 return 0; 1577 } 1578 1579 rte_atomic32_clear(&ad->link_thread_running); 1580 ixgbevf_parse_devargs(eth_dev->data->dev_private, 1581 pci_dev->device.devargs); 1582 1583 rte_eth_copy_pci_info(eth_dev, pci_dev); 1584 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1585 1586 hw->device_id = pci_dev->id.device_id; 1587 hw->vendor_id = pci_dev->id.vendor_id; 1588 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1589 1590 /* initialize the vfta */ 1591 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1592 1593 /* initialize the hw strip bitmap*/ 1594 memset(hwstrip, 0, sizeof(*hwstrip)); 1595 1596 /* Initialize the shared code (base driver) */ 1597 diag = ixgbe_init_shared_code(hw); 1598 if (diag != IXGBE_SUCCESS) { 1599 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag); 1600 return -EIO; 1601 } 1602 1603 /* init_mailbox_params */ 1604 hw->mbx.ops.init_params(hw); 1605 1606 /* Reset the hw statistics */ 1607 ixgbevf_dev_stats_reset(eth_dev); 1608 1609 /* Disable the interrupts for VF */ 1610 ixgbevf_intr_disable(eth_dev); 1611 1612 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */ 1613 diag = hw->mac.ops.reset_hw(hw); 1614 1615 /* 1616 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when 1617 * the underlying PF driver has not assigned a MAC address to the VF. 1618 * In this case, assign a random MAC address. 1619 */ 1620 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) { 1621 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1622 /* 1623 * This error code will be propagated to the app by 1624 * rte_eth_dev_reset, so use a public error code rather than 1625 * the internal-only IXGBE_ERR_RESET_FAILED 1626 */ 1627 return -EAGAIN; 1628 } 1629 1630 /* negotiate mailbox API version to use with the PF. */ 1631 ixgbevf_negotiate_api(hw); 1632 1633 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */ 1634 ixgbevf_get_queues(hw, &tcs, &tc); 1635 1636 /* Allocate memory for storing MAC addresses */ 1637 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN * 1638 hw->mac.num_rar_entries, 0); 1639 if (eth_dev->data->mac_addrs == NULL) { 1640 PMD_INIT_LOG(ERR, 1641 "Failed to allocate %u bytes needed to store " 1642 "MAC addresses", 1643 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1644 return -ENOMEM; 1645 } 1646 1647 /* Generate a random MAC address, if none was assigned by PF. */ 1648 if (rte_is_zero_ether_addr(perm_addr)) { 1649 generate_random_mac_addr(perm_addr); 1650 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1); 1651 if (diag) { 1652 rte_free(eth_dev->data->mac_addrs); 1653 eth_dev->data->mac_addrs = NULL; 1654 return diag; 1655 } 1656 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF"); 1657 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address " 1658 RTE_ETHER_ADDR_PRT_FMT, 1659 RTE_ETHER_ADDR_BYTES(perm_addr)); 1660 } 1661 1662 /* Copy the permanent MAC address */ 1663 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]); 1664 1665 /* reset the hardware with the new settings */ 1666 diag = hw->mac.ops.start_hw(hw); 1667 switch (diag) { 1668 case 0: 1669 break; 1670 1671 default: 1672 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1673 rte_free(eth_dev->data->mac_addrs); 1674 eth_dev->data->mac_addrs = NULL; 1675 return -EIO; 1676 } 1677 1678 rte_intr_callback_register(intr_handle, 1679 ixgbevf_dev_interrupt_handler, eth_dev); 1680 rte_intr_enable(intr_handle); 1681 ixgbevf_intr_enable(eth_dev); 1682 1683 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s", 1684 eth_dev->data->port_id, pci_dev->id.vendor_id, 1685 pci_dev->id.device_id, "ixgbe_mac_82599_vf"); 1686 1687 return 0; 1688 } 1689 1690 /* Virtual Function device uninit */ 1691 1692 static int 1693 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev) 1694 { 1695 PMD_INIT_FUNC_TRACE(); 1696 1697 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1698 return 0; 1699 1700 ixgbevf_dev_close(eth_dev); 1701 1702 return 0; 1703 } 1704 1705 static int 1706 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1707 struct rte_pci_device *pci_dev) 1708 { 1709 char name[RTE_ETH_NAME_MAX_LEN]; 1710 struct rte_eth_dev *pf_ethdev; 1711 struct rte_eth_devargs eth_da; 1712 int i, retval; 1713 1714 if (pci_dev->device.devargs) { 1715 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 1716 ð_da); 1717 if (retval) 1718 return retval; 1719 } else 1720 memset(ð_da, 0, sizeof(eth_da)); 1721 1722 if (eth_da.nb_representor_ports > 0 && 1723 eth_da.type != RTE_ETH_REPRESENTOR_VF) { 1724 PMD_DRV_LOG(ERR, "unsupported representor type: %s\n", 1725 pci_dev->device.devargs->args); 1726 return -ENOTSUP; 1727 } 1728 1729 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 1730 sizeof(struct ixgbe_adapter), 1731 eth_dev_pci_specific_init, pci_dev, 1732 eth_ixgbe_dev_init, NULL); 1733 1734 if (retval || eth_da.nb_representor_ports < 1) 1735 return retval; 1736 1737 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1738 if (pf_ethdev == NULL) 1739 return -ENODEV; 1740 1741 /* probe VF representor ports */ 1742 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1743 struct ixgbe_vf_info *vfinfo; 1744 struct ixgbe_vf_representor representor; 1745 1746 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA( 1747 pf_ethdev->data->dev_private); 1748 if (vfinfo == NULL) { 1749 PMD_DRV_LOG(ERR, 1750 "no virtual functions supported by PF"); 1751 break; 1752 } 1753 1754 representor.vf_id = eth_da.representor_ports[i]; 1755 representor.switch_domain_id = vfinfo->switch_domain_id; 1756 representor.pf_ethdev = pf_ethdev; 1757 1758 /* representor port net_bdf_port */ 1759 snprintf(name, sizeof(name), "net_%s_representor_%d", 1760 pci_dev->device.name, 1761 eth_da.representor_ports[i]); 1762 1763 retval = rte_eth_dev_create(&pci_dev->device, name, 1764 sizeof(struct ixgbe_vf_representor), NULL, NULL, 1765 ixgbe_vf_representor_init, &representor); 1766 1767 if (retval) 1768 PMD_DRV_LOG(ERR, "failed to create ixgbe vf " 1769 "representor %s.", name); 1770 } 1771 1772 return 0; 1773 } 1774 1775 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev) 1776 { 1777 struct rte_eth_dev *ethdev; 1778 1779 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1780 if (!ethdev) 1781 return 0; 1782 1783 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 1784 return rte_eth_dev_pci_generic_remove(pci_dev, 1785 ixgbe_vf_representor_uninit); 1786 else 1787 return rte_eth_dev_pci_generic_remove(pci_dev, 1788 eth_ixgbe_dev_uninit); 1789 } 1790 1791 static struct rte_pci_driver rte_ixgbe_pmd = { 1792 .id_table = pci_id_ixgbe_map, 1793 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1794 .probe = eth_ixgbe_pci_probe, 1795 .remove = eth_ixgbe_pci_remove, 1796 }; 1797 1798 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1799 struct rte_pci_device *pci_dev) 1800 { 1801 return rte_eth_dev_pci_generic_probe(pci_dev, 1802 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init); 1803 } 1804 1805 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev) 1806 { 1807 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit); 1808 } 1809 1810 /* 1811 * virtual function driver struct 1812 */ 1813 static struct rte_pci_driver rte_ixgbevf_pmd = { 1814 .id_table = pci_id_ixgbevf_map, 1815 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1816 .probe = eth_ixgbevf_pci_probe, 1817 .remove = eth_ixgbevf_pci_remove, 1818 }; 1819 1820 static int 1821 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1822 { 1823 struct ixgbe_hw *hw = 1824 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1825 struct ixgbe_vfta *shadow_vfta = 1826 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1827 uint32_t vfta; 1828 uint32_t vid_idx; 1829 uint32_t vid_bit; 1830 1831 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 1832 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 1833 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx)); 1834 if (on) 1835 vfta |= vid_bit; 1836 else 1837 vfta &= ~vid_bit; 1838 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta); 1839 1840 /* update local VFTA copy */ 1841 shadow_vfta->vfta[vid_idx] = vfta; 1842 1843 return 0; 1844 } 1845 1846 static void 1847 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 1848 { 1849 if (on) 1850 ixgbe_vlan_hw_strip_enable(dev, queue); 1851 else 1852 ixgbe_vlan_hw_strip_disable(dev, queue); 1853 } 1854 1855 static int 1856 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1857 enum rte_vlan_type vlan_type, 1858 uint16_t tpid) 1859 { 1860 struct ixgbe_hw *hw = 1861 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1862 int ret = 0; 1863 uint32_t reg; 1864 uint32_t qinq; 1865 1866 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1867 qinq &= IXGBE_DMATXCTL_GDV; 1868 1869 switch (vlan_type) { 1870 case RTE_ETH_VLAN_TYPE_INNER: 1871 if (qinq) { 1872 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1873 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1874 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1875 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1876 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1877 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1878 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1879 } else { 1880 ret = -ENOTSUP; 1881 PMD_DRV_LOG(ERR, "Inner type is not supported" 1882 " by single VLAN"); 1883 } 1884 break; 1885 case RTE_ETH_VLAN_TYPE_OUTER: 1886 if (qinq) { 1887 /* Only the high 16-bits is valid */ 1888 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid << 1889 IXGBE_EXVET_VET_EXT_SHIFT); 1890 } else { 1891 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1892 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1893 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1894 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1895 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1896 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1897 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1898 } 1899 1900 break; 1901 default: 1902 ret = -EINVAL; 1903 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type); 1904 break; 1905 } 1906 1907 return ret; 1908 } 1909 1910 void 1911 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev) 1912 { 1913 struct ixgbe_hw *hw = 1914 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1915 uint32_t vlnctrl; 1916 1917 PMD_INIT_FUNC_TRACE(); 1918 1919 /* Filter Table Disable */ 1920 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1921 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 1922 1923 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1924 } 1925 1926 void 1927 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1928 { 1929 struct ixgbe_hw *hw = 1930 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1931 struct ixgbe_vfta *shadow_vfta = 1932 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1933 uint32_t vlnctrl; 1934 uint16_t i; 1935 1936 PMD_INIT_FUNC_TRACE(); 1937 1938 /* Filter Table Enable */ 1939 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1940 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; 1941 vlnctrl |= IXGBE_VLNCTRL_VFE; 1942 1943 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1944 1945 /* write whatever is in local vfta copy */ 1946 for (i = 0; i < IXGBE_VFTA_SIZE; i++) 1947 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]); 1948 } 1949 1950 static void 1951 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on) 1952 { 1953 struct ixgbe_hwstrip *hwstrip = 1954 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private); 1955 struct ixgbe_rx_queue *rxq; 1956 1957 if (queue >= IXGBE_MAX_RX_QUEUE_NUM) 1958 return; 1959 1960 if (on) 1961 IXGBE_SET_HWSTRIP(hwstrip, queue); 1962 else 1963 IXGBE_CLEAR_HWSTRIP(hwstrip, queue); 1964 1965 if (queue >= dev->data->nb_rx_queues) 1966 return; 1967 1968 rxq = dev->data->rx_queues[queue]; 1969 1970 if (on) { 1971 rxq->vlan_flags = RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED; 1972 rxq->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 1973 } else { 1974 rxq->vlan_flags = RTE_MBUF_F_RX_VLAN; 1975 rxq->offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 1976 } 1977 } 1978 1979 static void 1980 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue) 1981 { 1982 struct ixgbe_hw *hw = 1983 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1984 uint32_t ctrl; 1985 1986 PMD_INIT_FUNC_TRACE(); 1987 1988 if (hw->mac.type == ixgbe_mac_82598EB) { 1989 /* No queue level support */ 1990 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 1991 return; 1992 } 1993 1994 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 1995 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 1996 ctrl &= ~IXGBE_RXDCTL_VME; 1997 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 1998 1999 /* record those setting for HW strip per queue */ 2000 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0); 2001 } 2002 2003 static void 2004 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue) 2005 { 2006 struct ixgbe_hw *hw = 2007 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2008 uint32_t ctrl; 2009 2010 PMD_INIT_FUNC_TRACE(); 2011 2012 if (hw->mac.type == ixgbe_mac_82598EB) { 2013 /* No queue level supported */ 2014 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2015 return; 2016 } 2017 2018 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2019 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2020 ctrl |= IXGBE_RXDCTL_VME; 2021 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2022 2023 /* record those setting for HW strip per queue */ 2024 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1); 2025 } 2026 2027 static void 2028 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev) 2029 { 2030 struct ixgbe_hw *hw = 2031 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2032 uint32_t ctrl; 2033 2034 PMD_INIT_FUNC_TRACE(); 2035 2036 /* DMATXCTRL: Geric Double VLAN Disable */ 2037 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2038 ctrl &= ~IXGBE_DMATXCTL_GDV; 2039 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2040 2041 /* CTRL_EXT: Global Double VLAN Disable */ 2042 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2043 ctrl &= ~IXGBE_EXTENDED_VLAN; 2044 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2045 2046 } 2047 2048 static void 2049 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) 2050 { 2051 struct ixgbe_hw *hw = 2052 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2053 uint32_t ctrl; 2054 2055 PMD_INIT_FUNC_TRACE(); 2056 2057 /* DMATXCTRL: Geric Double VLAN Enable */ 2058 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2059 ctrl |= IXGBE_DMATXCTL_GDV; 2060 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2061 2062 /* CTRL_EXT: Global Double VLAN Enable */ 2063 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2064 ctrl |= IXGBE_EXTENDED_VLAN; 2065 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2066 2067 /* Clear pooling mode of PFVTCTL. It's required by X550. */ 2068 if (hw->mac.type == ixgbe_mac_X550 || 2069 hw->mac.type == ixgbe_mac_X550EM_x || 2070 hw->mac.type == ixgbe_mac_X550EM_a) { 2071 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 2072 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 2073 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 2074 } 2075 2076 /* 2077 * VET EXT field in the EXVET register = 0x8100 by default 2078 * So no need to change. Same to VT field of DMATXCTL register 2079 */ 2080 } 2081 2082 void 2083 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev) 2084 { 2085 struct ixgbe_hw *hw = 2086 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2087 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 2088 uint32_t ctrl; 2089 uint16_t i; 2090 struct ixgbe_rx_queue *rxq; 2091 bool on; 2092 2093 PMD_INIT_FUNC_TRACE(); 2094 2095 if (hw->mac.type == ixgbe_mac_82598EB) { 2096 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) { 2097 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2098 ctrl |= IXGBE_VLNCTRL_VME; 2099 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2100 } else { 2101 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2102 ctrl &= ~IXGBE_VLNCTRL_VME; 2103 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2104 } 2105 } else { 2106 /* 2107 * Other 10G NIC, the VLAN strip can be setup 2108 * per queue in RXDCTL 2109 */ 2110 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2111 rxq = dev->data->rx_queues[i]; 2112 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx)); 2113 if (rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) { 2114 ctrl |= IXGBE_RXDCTL_VME; 2115 on = TRUE; 2116 } else { 2117 ctrl &= ~IXGBE_RXDCTL_VME; 2118 on = FALSE; 2119 } 2120 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl); 2121 2122 /* record those setting for HW strip per queue */ 2123 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on); 2124 } 2125 } 2126 } 2127 2128 static void 2129 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask) 2130 { 2131 uint16_t i; 2132 struct rte_eth_rxmode *rxmode; 2133 struct ixgbe_rx_queue *rxq; 2134 2135 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 2136 rxmode = &dev->data->dev_conf.rxmode; 2137 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 2138 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2139 rxq = dev->data->rx_queues[i]; 2140 rxq->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 2141 } 2142 else 2143 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2144 rxq = dev->data->rx_queues[i]; 2145 rxq->offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 2146 } 2147 } 2148 } 2149 2150 static int 2151 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask) 2152 { 2153 struct rte_eth_rxmode *rxmode; 2154 rxmode = &dev->data->dev_conf.rxmode; 2155 2156 if (mask & RTE_ETH_VLAN_STRIP_MASK) 2157 ixgbe_vlan_hw_strip_config(dev); 2158 2159 if (mask & RTE_ETH_VLAN_FILTER_MASK) { 2160 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) 2161 ixgbe_vlan_hw_filter_enable(dev); 2162 else 2163 ixgbe_vlan_hw_filter_disable(dev); 2164 } 2165 2166 if (mask & RTE_ETH_VLAN_EXTEND_MASK) { 2167 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) 2168 ixgbe_vlan_hw_extend_enable(dev); 2169 else 2170 ixgbe_vlan_hw_extend_disable(dev); 2171 } 2172 2173 return 0; 2174 } 2175 2176 static int 2177 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2178 { 2179 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 2180 2181 ixgbe_vlan_offload_config(dev, mask); 2182 2183 return 0; 2184 } 2185 2186 static void 2187 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev) 2188 { 2189 struct ixgbe_hw *hw = 2190 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2191 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */ 2192 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2193 2194 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */ 2195 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl); 2196 } 2197 2198 static int 2199 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q) 2200 { 2201 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2202 2203 switch (nb_rx_q) { 2204 case 1: 2205 case 2: 2206 RTE_ETH_DEV_SRIOV(dev).active = RTE_ETH_64_POOLS; 2207 break; 2208 case 4: 2209 RTE_ETH_DEV_SRIOV(dev).active = RTE_ETH_32_POOLS; 2210 break; 2211 default: 2212 return -EINVAL; 2213 } 2214 2215 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 2216 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2217 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 2218 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2219 return 0; 2220 } 2221 2222 static int 2223 ixgbe_check_mq_mode(struct rte_eth_dev *dev) 2224 { 2225 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 2226 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2227 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2228 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2229 2230 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 2231 /* check multi-queue mode */ 2232 switch (dev_conf->rxmode.mq_mode) { 2233 case RTE_ETH_MQ_RX_VMDQ_DCB: 2234 PMD_INIT_LOG(INFO, "RTE_ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV"); 2235 break; 2236 case RTE_ETH_MQ_RX_VMDQ_DCB_RSS: 2237 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */ 2238 PMD_INIT_LOG(ERR, "SRIOV active," 2239 " unsupported mq_mode rx %d.", 2240 dev_conf->rxmode.mq_mode); 2241 return -EINVAL; 2242 case RTE_ETH_MQ_RX_RSS: 2243 case RTE_ETH_MQ_RX_VMDQ_RSS: 2244 dev->data->dev_conf.rxmode.mq_mode = RTE_ETH_MQ_RX_VMDQ_RSS; 2245 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) 2246 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) { 2247 PMD_INIT_LOG(ERR, "SRIOV is active," 2248 " invalid queue number" 2249 " for VMDQ RSS, allowed" 2250 " value are 1, 2 or 4."); 2251 return -EINVAL; 2252 } 2253 break; 2254 case RTE_ETH_MQ_RX_VMDQ_ONLY: 2255 case RTE_ETH_MQ_RX_NONE: 2256 /* if nothing mq mode configure, use default scheme */ 2257 dev->data->dev_conf.rxmode.mq_mode = RTE_ETH_MQ_RX_VMDQ_ONLY; 2258 break; 2259 default: /* RTE_ETH_MQ_RX_DCB, RTE_ETH_MQ_RX_DCB_RSS or RTE_ETH_MQ_TX_DCB*/ 2260 /* SRIOV only works in VMDq enable mode */ 2261 PMD_INIT_LOG(ERR, "SRIOV is active," 2262 " wrong mq_mode rx %d.", 2263 dev_conf->rxmode.mq_mode); 2264 return -EINVAL; 2265 } 2266 2267 switch (dev_conf->txmode.mq_mode) { 2268 case RTE_ETH_MQ_TX_VMDQ_DCB: 2269 PMD_INIT_LOG(INFO, "RTE_ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV"); 2270 dev->data->dev_conf.txmode.mq_mode = RTE_ETH_MQ_TX_VMDQ_DCB; 2271 break; 2272 default: /* RTE_ETH_MQ_TX_VMDQ_ONLY or RTE_ETH_MQ_TX_NONE */ 2273 dev->data->dev_conf.txmode.mq_mode = RTE_ETH_MQ_TX_VMDQ_ONLY; 2274 break; 2275 } 2276 2277 /* check valid queue number */ 2278 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) || 2279 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) { 2280 PMD_INIT_LOG(ERR, "SRIOV is active," 2281 " nb_rx_q=%d nb_tx_q=%d queue number" 2282 " must be less than or equal to %d.", 2283 nb_rx_q, nb_tx_q, 2284 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool); 2285 return -EINVAL; 2286 } 2287 } else { 2288 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_DCB_RSS) { 2289 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is" 2290 " not supported."); 2291 return -EINVAL; 2292 } 2293 /* check configuration for vmdb+dcb mode */ 2294 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_DCB) { 2295 const struct rte_eth_vmdq_dcb_conf *conf; 2296 2297 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2298 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.", 2299 IXGBE_VMDQ_DCB_NB_QUEUES); 2300 return -EINVAL; 2301 } 2302 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf; 2303 if (!(conf->nb_queue_pools == RTE_ETH_16_POOLS || 2304 conf->nb_queue_pools == RTE_ETH_32_POOLS)) { 2305 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2306 " nb_queue_pools must be %d or %d.", 2307 RTE_ETH_16_POOLS, RTE_ETH_32_POOLS); 2308 return -EINVAL; 2309 } 2310 } 2311 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB) { 2312 const struct rte_eth_vmdq_dcb_tx_conf *conf; 2313 2314 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2315 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d", 2316 IXGBE_VMDQ_DCB_NB_QUEUES); 2317 return -EINVAL; 2318 } 2319 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf; 2320 if (!(conf->nb_queue_pools == RTE_ETH_16_POOLS || 2321 conf->nb_queue_pools == RTE_ETH_32_POOLS)) { 2322 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2323 " nb_queue_pools != %d and" 2324 " nb_queue_pools != %d.", 2325 RTE_ETH_16_POOLS, RTE_ETH_32_POOLS); 2326 return -EINVAL; 2327 } 2328 } 2329 2330 /* For DCB mode check our configuration before we go further */ 2331 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_DCB) { 2332 const struct rte_eth_dcb_rx_conf *conf; 2333 2334 conf = &dev_conf->rx_adv_conf.dcb_rx_conf; 2335 if (!(conf->nb_tcs == RTE_ETH_4_TCS || 2336 conf->nb_tcs == RTE_ETH_8_TCS)) { 2337 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2338 " and nb_tcs != %d.", 2339 RTE_ETH_4_TCS, RTE_ETH_8_TCS); 2340 return -EINVAL; 2341 } 2342 } 2343 2344 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_DCB) { 2345 const struct rte_eth_dcb_tx_conf *conf; 2346 2347 conf = &dev_conf->tx_adv_conf.dcb_tx_conf; 2348 if (!(conf->nb_tcs == RTE_ETH_4_TCS || 2349 conf->nb_tcs == RTE_ETH_8_TCS)) { 2350 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2351 " and nb_tcs != %d.", 2352 RTE_ETH_4_TCS, RTE_ETH_8_TCS); 2353 return -EINVAL; 2354 } 2355 } 2356 2357 /* 2358 * When DCB/VT is off, maximum number of queues changes, 2359 * except for 82598EB, which remains constant. 2360 */ 2361 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_NONE && 2362 hw->mac.type != ixgbe_mac_82598EB) { 2363 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) { 2364 PMD_INIT_LOG(ERR, 2365 "Neither VT nor DCB are enabled, " 2366 "nb_tx_q > %d.", 2367 IXGBE_NONE_MODE_TX_NB_QUEUES); 2368 return -EINVAL; 2369 } 2370 } 2371 } 2372 return 0; 2373 } 2374 2375 static int 2376 ixgbe_dev_configure(struct rte_eth_dev *dev) 2377 { 2378 struct ixgbe_interrupt *intr = 2379 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2380 struct ixgbe_adapter *adapter = dev->data->dev_private; 2381 int ret; 2382 2383 PMD_INIT_FUNC_TRACE(); 2384 2385 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 2386 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; 2387 2388 /* multiple queue mode checking */ 2389 ret = ixgbe_check_mq_mode(dev); 2390 if (ret != 0) { 2391 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.", 2392 ret); 2393 return ret; 2394 } 2395 2396 /* set flag to update link status after init */ 2397 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2398 2399 /* 2400 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 2401 * allocation or vector Rx preconditions we will reset it. 2402 */ 2403 adapter->rx_bulk_alloc_allowed = true; 2404 adapter->rx_vec_allowed = true; 2405 2406 return 0; 2407 } 2408 2409 static void 2410 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) 2411 { 2412 struct ixgbe_hw *hw = 2413 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2414 struct ixgbe_interrupt *intr = 2415 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2416 uint32_t gpie; 2417 2418 /* only set up it on X550EM_X */ 2419 if (hw->mac.type == ixgbe_mac_X550EM_x) { 2420 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 2421 gpie |= IXGBE_SDP0_GPIEN_X550EM_x; 2422 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 2423 if (hw->phy.type == ixgbe_phy_x550em_ext_t) 2424 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x; 2425 } 2426 } 2427 2428 int 2429 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 2430 uint16_t tx_rate, uint64_t q_msk) 2431 { 2432 struct ixgbe_hw *hw; 2433 struct ixgbe_vf_info *vfinfo; 2434 struct rte_eth_link link; 2435 uint8_t nb_q_per_pool; 2436 uint32_t queue_stride; 2437 uint32_t queue_idx, idx = 0, vf_idx; 2438 uint32_t queue_end; 2439 uint16_t total_rate = 0; 2440 struct rte_pci_device *pci_dev; 2441 int ret; 2442 2443 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2444 ret = rte_eth_link_get_nowait(dev->data->port_id, &link); 2445 if (ret < 0) 2446 return ret; 2447 2448 if (vf >= pci_dev->max_vfs) 2449 return -EINVAL; 2450 2451 if (tx_rate > link.link_speed) 2452 return -EINVAL; 2453 2454 if (q_msk == 0) 2455 return 0; 2456 2457 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2458 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 2459 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2460 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2461 queue_idx = vf * queue_stride; 2462 queue_end = queue_idx + nb_q_per_pool - 1; 2463 if (queue_end >= hw->mac.max_tx_queues) 2464 return -EINVAL; 2465 2466 if (vfinfo) { 2467 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) { 2468 if (vf_idx == vf) 2469 continue; 2470 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate); 2471 idx++) 2472 total_rate += vfinfo[vf_idx].tx_rate[idx]; 2473 } 2474 } else { 2475 return -EINVAL; 2476 } 2477 2478 /* Store tx_rate for this vf. */ 2479 for (idx = 0; idx < nb_q_per_pool; idx++) { 2480 if (((uint64_t)0x1 << idx) & q_msk) { 2481 if (vfinfo[vf].tx_rate[idx] != tx_rate) 2482 vfinfo[vf].tx_rate[idx] = tx_rate; 2483 total_rate += tx_rate; 2484 } 2485 } 2486 2487 if (total_rate > dev->data->dev_link.link_speed) { 2488 /* Reset stored TX rate of the VF if it causes exceed 2489 * link speed. 2490 */ 2491 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate)); 2492 return -EINVAL; 2493 } 2494 2495 /* Set RTTBCNRC of each queue/pool for vf X */ 2496 for (; queue_idx <= queue_end; queue_idx++) { 2497 if (0x1 & q_msk) 2498 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate); 2499 q_msk = q_msk >> 1; 2500 } 2501 2502 return 0; 2503 } 2504 2505 static int 2506 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw) 2507 { 2508 struct ixgbe_adapter *adapter = dev->data->dev_private; 2509 int err; 2510 uint32_t mflcn; 2511 2512 ixgbe_setup_fc(hw); 2513 2514 err = ixgbe_fc_enable(hw); 2515 2516 /* Not negotiated is not an error case */ 2517 if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) { 2518 /* 2519 *check if we want to forward MAC frames - driver doesn't 2520 *have native capability to do that, 2521 *so we'll write the registers ourselves 2522 */ 2523 2524 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2525 2526 /* set or clear MFLCN.PMCF bit depending on configuration */ 2527 if (adapter->mac_ctrl_frame_fwd != 0) 2528 mflcn |= IXGBE_MFLCN_PMCF; 2529 else 2530 mflcn &= ~IXGBE_MFLCN_PMCF; 2531 2532 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn); 2533 IXGBE_WRITE_FLUSH(hw); 2534 2535 return 0; 2536 } 2537 return err; 2538 } 2539 2540 /* 2541 * Configure device link speed and setup link. 2542 * It returns 0 on success. 2543 */ 2544 static int 2545 ixgbe_dev_start(struct rte_eth_dev *dev) 2546 { 2547 struct ixgbe_hw *hw = 2548 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2549 struct ixgbe_vf_info *vfinfo = 2550 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2551 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2552 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 2553 uint32_t intr_vector = 0; 2554 int err; 2555 bool link_up = false, negotiate = 0; 2556 uint32_t speed = 0; 2557 uint32_t allowed_speeds = 0; 2558 int mask = 0; 2559 int status; 2560 uint16_t vf, idx; 2561 uint32_t *link_speeds; 2562 struct ixgbe_tm_conf *tm_conf = 2563 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2564 struct ixgbe_macsec_setting *macsec_setting = 2565 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 2566 2567 PMD_INIT_FUNC_TRACE(); 2568 2569 /* Stop the link setup handler before resetting the HW. */ 2570 ixgbe_dev_wait_setup_link_complete(dev, 0); 2571 2572 /* disable uio/vfio intr/eventfd mapping */ 2573 rte_intr_disable(intr_handle); 2574 2575 /* stop adapter */ 2576 hw->adapter_stopped = 0; 2577 ixgbe_stop_adapter(hw); 2578 2579 /* reinitialize adapter 2580 * this calls reset and start 2581 */ 2582 status = ixgbe_pf_reset_hw(hw); 2583 if (status != 0) 2584 return -1; 2585 hw->mac.ops.start_hw(hw); 2586 hw->mac.get_link_status = true; 2587 2588 /* configure PF module if SRIOV enabled */ 2589 ixgbe_pf_host_configure(dev); 2590 2591 ixgbe_dev_phy_intr_setup(dev); 2592 2593 /* check and configure queue intr-vector mapping */ 2594 if ((rte_intr_cap_multiple(intr_handle) || 2595 !RTE_ETH_DEV_SRIOV(dev).active) && 2596 dev->data->dev_conf.intr_conf.rxq != 0) { 2597 intr_vector = dev->data->nb_rx_queues; 2598 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) { 2599 PMD_INIT_LOG(ERR, "At most %d intr queues supported", 2600 IXGBE_MAX_INTR_QUEUE_NUM); 2601 return -ENOTSUP; 2602 } 2603 if (rte_intr_efd_enable(intr_handle, intr_vector)) 2604 return -1; 2605 } 2606 2607 if (rte_intr_dp_is_en(intr_handle)) { 2608 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec", 2609 dev->data->nb_rx_queues)) { 2610 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 2611 " intr_vec", dev->data->nb_rx_queues); 2612 return -ENOMEM; 2613 } 2614 } 2615 2616 /* configure MSI-X for sleep until Rx interrupt */ 2617 ixgbe_configure_msix(dev); 2618 2619 /* initialize transmission unit */ 2620 ixgbe_dev_tx_init(dev); 2621 2622 /* This can fail when allocating mbufs for descriptor rings */ 2623 err = ixgbe_dev_rx_init(dev); 2624 if (err) { 2625 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 2626 goto error; 2627 } 2628 2629 mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK | 2630 RTE_ETH_VLAN_EXTEND_MASK; 2631 err = ixgbe_vlan_offload_config(dev, mask); 2632 if (err) { 2633 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 2634 goto error; 2635 } 2636 2637 if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_ONLY) { 2638 /* Enable vlan filtering for VMDq */ 2639 ixgbe_vmdq_vlan_hw_filter_enable(dev); 2640 } 2641 2642 /* Configure DCB hw */ 2643 ixgbe_configure_dcb(dev); 2644 2645 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) { 2646 err = ixgbe_fdir_configure(dev); 2647 if (err) 2648 goto error; 2649 } 2650 2651 /* Restore vf rate limit */ 2652 if (vfinfo != NULL) { 2653 for (vf = 0; vf < pci_dev->max_vfs; vf++) 2654 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++) 2655 if (vfinfo[vf].tx_rate[idx] != 0) 2656 ixgbe_set_vf_rate_limit( 2657 dev, vf, 2658 vfinfo[vf].tx_rate[idx], 2659 1 << idx); 2660 } 2661 2662 ixgbe_restore_statistics_mapping(dev); 2663 2664 err = ixgbe_flow_ctrl_enable(dev, hw); 2665 if (err < 0) { 2666 PMD_INIT_LOG(ERR, "enable flow ctrl err"); 2667 goto error; 2668 } 2669 2670 err = ixgbe_dev_rxtx_start(dev); 2671 if (err < 0) { 2672 PMD_INIT_LOG(ERR, "Unable to start rxtx queues"); 2673 goto error; 2674 } 2675 2676 /* Skip link setup if loopback mode is enabled. */ 2677 if (dev->data->dev_conf.lpbk_mode != 0) { 2678 err = ixgbe_check_supported_loopback_mode(dev); 2679 if (err < 0) { 2680 PMD_INIT_LOG(ERR, "Unsupported loopback mode"); 2681 goto error; 2682 } else { 2683 goto skip_link_setup; 2684 } 2685 } 2686 2687 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) { 2688 err = hw->mac.ops.setup_sfp(hw); 2689 if (err) 2690 goto error; 2691 } 2692 2693 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2694 /* Turn on the copper */ 2695 ixgbe_set_phy_power(hw, true); 2696 } else { 2697 /* Turn on the laser */ 2698 ixgbe_enable_tx_laser(hw); 2699 } 2700 2701 err = ixgbe_check_link(hw, &speed, &link_up, 0); 2702 if (err) 2703 goto error; 2704 dev->data->dev_link.link_status = link_up; 2705 2706 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate); 2707 if (err) 2708 goto error; 2709 2710 switch (hw->mac.type) { 2711 case ixgbe_mac_X550: 2712 case ixgbe_mac_X550EM_x: 2713 case ixgbe_mac_X550EM_a: 2714 allowed_speeds = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G | 2715 RTE_ETH_LINK_SPEED_2_5G | RTE_ETH_LINK_SPEED_5G | 2716 RTE_ETH_LINK_SPEED_10G; 2717 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 2718 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 2719 allowed_speeds = RTE_ETH_LINK_SPEED_10M | 2720 RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G; 2721 break; 2722 default: 2723 allowed_speeds = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G | 2724 RTE_ETH_LINK_SPEED_10G; 2725 } 2726 2727 link_speeds = &dev->data->dev_conf.link_speeds; 2728 2729 /* Ignore autoneg flag bit and check the validity of 2730 * link_speed 2731 */ 2732 if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) { 2733 PMD_INIT_LOG(ERR, "Invalid link setting"); 2734 goto error; 2735 } 2736 2737 speed = 0x0; 2738 if (*link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) { 2739 switch (hw->mac.type) { 2740 case ixgbe_mac_82598EB: 2741 speed = IXGBE_LINK_SPEED_82598_AUTONEG; 2742 break; 2743 case ixgbe_mac_82599EB: 2744 case ixgbe_mac_X540: 2745 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2746 break; 2747 case ixgbe_mac_X550: 2748 case ixgbe_mac_X550EM_x: 2749 case ixgbe_mac_X550EM_a: 2750 speed = IXGBE_LINK_SPEED_X550_AUTONEG; 2751 break; 2752 default: 2753 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2754 } 2755 } else { 2756 if (*link_speeds & RTE_ETH_LINK_SPEED_10G) 2757 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2758 if (*link_speeds & RTE_ETH_LINK_SPEED_5G) 2759 speed |= IXGBE_LINK_SPEED_5GB_FULL; 2760 if (*link_speeds & RTE_ETH_LINK_SPEED_2_5G) 2761 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 2762 if (*link_speeds & RTE_ETH_LINK_SPEED_1G) 2763 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2764 if (*link_speeds & RTE_ETH_LINK_SPEED_100M) 2765 speed |= IXGBE_LINK_SPEED_100_FULL; 2766 if (*link_speeds & RTE_ETH_LINK_SPEED_10M) 2767 speed |= IXGBE_LINK_SPEED_10_FULL; 2768 } 2769 2770 err = ixgbe_setup_link(hw, speed, link_up); 2771 if (err) 2772 goto error; 2773 2774 skip_link_setup: 2775 2776 if (rte_intr_allow_others(intr_handle)) { 2777 /* check if lsc interrupt is enabled */ 2778 if (dev->data->dev_conf.intr_conf.lsc != 0) 2779 ixgbe_dev_lsc_interrupt_setup(dev, TRUE); 2780 else 2781 ixgbe_dev_lsc_interrupt_setup(dev, FALSE); 2782 ixgbe_dev_macsec_interrupt_setup(dev); 2783 } else { 2784 rte_intr_callback_unregister(intr_handle, 2785 ixgbe_dev_interrupt_handler, dev); 2786 if (dev->data->dev_conf.intr_conf.lsc != 0) 2787 PMD_INIT_LOG(INFO, "lsc won't enable because of" 2788 " no intr multiplex"); 2789 } 2790 2791 /* check if rxq interrupt is enabled */ 2792 if (dev->data->dev_conf.intr_conf.rxq != 0 && 2793 rte_intr_dp_is_en(intr_handle)) 2794 ixgbe_dev_rxq_interrupt_setup(dev); 2795 2796 /* enable uio/vfio intr/eventfd mapping */ 2797 rte_intr_enable(intr_handle); 2798 2799 /* resume enabled intr since hw reset */ 2800 ixgbe_enable_intr(dev); 2801 ixgbe_l2_tunnel_conf(dev); 2802 ixgbe_filter_restore(dev); 2803 2804 if (tm_conf->root && !tm_conf->committed) 2805 PMD_DRV_LOG(WARNING, 2806 "please call hierarchy_commit() " 2807 "before starting the port"); 2808 2809 /* wait for the controller to acquire link */ 2810 err = ixgbe_wait_for_link_up(hw); 2811 if (err) 2812 goto error; 2813 2814 /* 2815 * Update link status right before return, because it may 2816 * start link configuration process in a separate thread. 2817 */ 2818 ixgbe_dev_link_update(dev, 0); 2819 2820 /* setup the macsec setting register */ 2821 if (macsec_setting->offload_en) 2822 ixgbe_dev_macsec_register_enable(dev, macsec_setting); 2823 2824 return 0; 2825 2826 error: 2827 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err); 2828 ixgbe_dev_clear_queues(dev); 2829 return -EIO; 2830 } 2831 2832 /* 2833 * Stop device: disable rx and tx functions to allow for reconfiguring. 2834 */ 2835 static int 2836 ixgbe_dev_stop(struct rte_eth_dev *dev) 2837 { 2838 struct rte_eth_link link; 2839 struct ixgbe_adapter *adapter = dev->data->dev_private; 2840 struct ixgbe_hw *hw = 2841 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2842 struct ixgbe_vf_info *vfinfo = 2843 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2844 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2845 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 2846 int vf; 2847 struct ixgbe_tm_conf *tm_conf = 2848 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2849 2850 if (hw->adapter_stopped) 2851 return 0; 2852 2853 PMD_INIT_FUNC_TRACE(); 2854 2855 ixgbe_dev_wait_setup_link_complete(dev, 0); 2856 2857 /* disable interrupts */ 2858 ixgbe_disable_intr(hw); 2859 2860 /* reset the NIC */ 2861 ixgbe_pf_reset_hw(hw); 2862 hw->adapter_stopped = 0; 2863 2864 /* stop adapter */ 2865 ixgbe_stop_adapter(hw); 2866 2867 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++) 2868 vfinfo[vf].clear_to_send = false; 2869 2870 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2871 /* Turn off the copper */ 2872 ixgbe_set_phy_power(hw, false); 2873 } else { 2874 /* Turn off the laser */ 2875 ixgbe_disable_tx_laser(hw); 2876 } 2877 2878 ixgbe_dev_clear_queues(dev); 2879 2880 /* Clear stored conf */ 2881 dev->data->scattered_rx = 0; 2882 dev->data->lro = 0; 2883 2884 /* Clear recorded link status */ 2885 memset(&link, 0, sizeof(link)); 2886 rte_eth_linkstatus_set(dev, &link); 2887 2888 if (!rte_intr_allow_others(intr_handle)) 2889 /* resume to the default handler */ 2890 rte_intr_callback_register(intr_handle, 2891 ixgbe_dev_interrupt_handler, 2892 (void *)dev); 2893 2894 /* Clean datapath event and queue/vec mapping */ 2895 rte_intr_efd_disable(intr_handle); 2896 rte_intr_vec_list_free(intr_handle); 2897 2898 /* reset hierarchy commit */ 2899 tm_conf->committed = false; 2900 2901 adapter->rss_reta_updated = 0; 2902 2903 hw->adapter_stopped = true; 2904 dev->data->dev_started = 0; 2905 2906 return 0; 2907 } 2908 2909 /* 2910 * Set device link up: enable tx. 2911 */ 2912 static int 2913 ixgbe_dev_set_link_up(struct rte_eth_dev *dev) 2914 { 2915 struct ixgbe_hw *hw = 2916 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2917 if (hw->mac.type == ixgbe_mac_82599EB) { 2918 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2919 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2920 /* Not supported in bypass mode */ 2921 PMD_INIT_LOG(ERR, "Set link up is not supported " 2922 "by device id 0x%x", hw->device_id); 2923 return -ENOTSUP; 2924 } 2925 #endif 2926 } 2927 2928 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2929 /* Turn on the copper */ 2930 ixgbe_set_phy_power(hw, true); 2931 } else { 2932 /* Turn on the laser */ 2933 ixgbe_enable_tx_laser(hw); 2934 ixgbe_dev_link_update(dev, 0); 2935 } 2936 2937 return 0; 2938 } 2939 2940 /* 2941 * Set device link down: disable tx. 2942 */ 2943 static int 2944 ixgbe_dev_set_link_down(struct rte_eth_dev *dev) 2945 { 2946 struct ixgbe_hw *hw = 2947 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2948 if (hw->mac.type == ixgbe_mac_82599EB) { 2949 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2950 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2951 /* Not supported in bypass mode */ 2952 PMD_INIT_LOG(ERR, "Set link down is not supported " 2953 "by device id 0x%x", hw->device_id); 2954 return -ENOTSUP; 2955 } 2956 #endif 2957 } 2958 2959 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2960 /* Turn off the copper */ 2961 ixgbe_set_phy_power(hw, false); 2962 } else { 2963 /* Turn off the laser */ 2964 ixgbe_disable_tx_laser(hw); 2965 ixgbe_dev_link_update(dev, 0); 2966 } 2967 2968 return 0; 2969 } 2970 2971 /* 2972 * Reset and stop device. 2973 */ 2974 static int 2975 ixgbe_dev_close(struct rte_eth_dev *dev) 2976 { 2977 struct ixgbe_hw *hw = 2978 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2979 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2980 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 2981 int retries = 0; 2982 int ret; 2983 2984 PMD_INIT_FUNC_TRACE(); 2985 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2986 return 0; 2987 2988 ixgbe_pf_reset_hw(hw); 2989 2990 ret = ixgbe_dev_stop(dev); 2991 2992 ixgbe_dev_free_queues(dev); 2993 2994 ixgbe_disable_pcie_master(hw); 2995 2996 /* reprogram the RAR[0] in case user changed it. */ 2997 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2998 2999 /* Unlock any pending hardware semaphore */ 3000 ixgbe_swfw_lock_reset(hw); 3001 3002 /* disable uio intr before callback unregister */ 3003 rte_intr_disable(intr_handle); 3004 3005 do { 3006 ret = rte_intr_callback_unregister(intr_handle, 3007 ixgbe_dev_interrupt_handler, dev); 3008 if (ret >= 0 || ret == -ENOENT) { 3009 break; 3010 } else if (ret != -EAGAIN) { 3011 PMD_INIT_LOG(ERR, 3012 "intr callback unregister failed: %d", 3013 ret); 3014 } 3015 rte_delay_ms(100); 3016 } while (retries++ < (10 + IXGBE_LINK_UP_TIME)); 3017 3018 /* cancel the delay handler before remove dev */ 3019 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev); 3020 3021 /* uninitialize PF if max_vfs not zero */ 3022 ixgbe_pf_host_uninit(dev); 3023 3024 /* remove all the fdir filters & hash */ 3025 ixgbe_fdir_filter_uninit(dev); 3026 3027 /* remove all the L2 tunnel filters & hash */ 3028 ixgbe_l2_tn_filter_uninit(dev); 3029 3030 /* Remove all ntuple filters of the device */ 3031 ixgbe_ntuple_filter_uninit(dev); 3032 3033 /* clear all the filters list */ 3034 ixgbe_filterlist_flush(); 3035 3036 /* Remove all Traffic Manager configuration */ 3037 ixgbe_tm_conf_uninit(dev); 3038 3039 #ifdef RTE_LIB_SECURITY 3040 rte_free(dev->security_ctx); 3041 #endif 3042 3043 return ret; 3044 } 3045 3046 /* 3047 * Reset PF device. 3048 */ 3049 static int 3050 ixgbe_dev_reset(struct rte_eth_dev *dev) 3051 { 3052 int ret; 3053 3054 /* When a DPDK PMD PF begin to reset PF port, it should notify all 3055 * its VF to make them align with it. The detailed notification 3056 * mechanism is PMD specific. As to ixgbe PF, it is rather complex. 3057 * To avoid unexpected behavior in VF, currently reset of PF with 3058 * SR-IOV activation is not supported. It might be supported later. 3059 */ 3060 if (dev->data->sriov.active) 3061 return -ENOTSUP; 3062 3063 ret = eth_ixgbe_dev_uninit(dev); 3064 if (ret) 3065 return ret; 3066 3067 ret = eth_ixgbe_dev_init(dev, NULL); 3068 3069 return ret; 3070 } 3071 3072 static void 3073 ixgbe_read_stats_registers(struct ixgbe_hw *hw, 3074 struct ixgbe_hw_stats *hw_stats, 3075 struct ixgbe_macsec_stats *macsec_stats, 3076 uint64_t *total_missed_rx, uint64_t *total_qbrc, 3077 uint64_t *total_qprc, uint64_t *total_qprdc) 3078 { 3079 uint32_t bprc, lxon, lxoff, total; 3080 uint32_t delta_gprc = 0; 3081 unsigned i; 3082 /* Workaround for RX byte count not including CRC bytes when CRC 3083 * strip is enabled. CRC bytes are removed from counters when crc_strip 3084 * is disabled. 3085 */ 3086 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) & 3087 IXGBE_HLREG0_RXCRCSTRP); 3088 3089 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 3090 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC); 3091 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC); 3092 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC); 3093 3094 for (i = 0; i < 8; i++) { 3095 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 3096 3097 /* global total per queue */ 3098 hw_stats->mpc[i] += mp; 3099 /* Running comprehensive total for stats display */ 3100 *total_missed_rx += hw_stats->mpc[i]; 3101 if (hw->mac.type == ixgbe_mac_82598EB) { 3102 hw_stats->rnbc[i] += 3103 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 3104 hw_stats->pxonrxc[i] += 3105 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 3106 hw_stats->pxoffrxc[i] += 3107 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 3108 } else { 3109 hw_stats->pxonrxc[i] += 3110 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 3111 hw_stats->pxoffrxc[i] += 3112 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 3113 hw_stats->pxon2offc[i] += 3114 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 3115 } 3116 hw_stats->pxontxc[i] += 3117 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 3118 hw_stats->pxofftxc[i] += 3119 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 3120 } 3121 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3122 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 3123 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 3124 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 3125 3126 delta_gprc += delta_qprc; 3127 3128 hw_stats->qprc[i] += delta_qprc; 3129 hw_stats->qptc[i] += delta_qptc; 3130 3131 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 3132 hw_stats->qbrc[i] += 3133 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32); 3134 if (crc_strip == 0) 3135 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN; 3136 3137 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 3138 hw_stats->qbtc[i] += 3139 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32); 3140 3141 hw_stats->qprdc[i] += delta_qprdc; 3142 *total_qprdc += hw_stats->qprdc[i]; 3143 3144 *total_qprc += hw_stats->qprc[i]; 3145 *total_qbrc += hw_stats->qbrc[i]; 3146 } 3147 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC); 3148 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC); 3149 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 3150 3151 /* 3152 * An errata states that gprc actually counts good + missed packets: 3153 * Workaround to set gprc to summated queue packet receives 3154 */ 3155 hw_stats->gprc = *total_qprc; 3156 3157 if (hw->mac.type != ixgbe_mac_82598EB) { 3158 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 3159 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32); 3160 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 3161 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32); 3162 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 3163 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32); 3164 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 3165 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 3166 } else { 3167 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 3168 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 3169 /* 82598 only has a counter in the high register */ 3170 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 3171 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 3172 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 3173 } 3174 uint64_t old_tpr = hw_stats->tpr; 3175 3176 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 3177 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT); 3178 3179 if (crc_strip == 0) 3180 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN; 3181 3182 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC); 3183 hw_stats->gptc += delta_gptc; 3184 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN; 3185 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN; 3186 3187 /* 3188 * Workaround: mprc hardware is incorrectly counting 3189 * broadcasts, so for now we subtract those. 3190 */ 3191 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 3192 hw_stats->bprc += bprc; 3193 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 3194 if (hw->mac.type == ixgbe_mac_82598EB) 3195 hw_stats->mprc -= bprc; 3196 3197 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 3198 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 3199 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 3200 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 3201 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 3202 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 3203 3204 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 3205 hw_stats->lxontxc += lxon; 3206 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 3207 hw_stats->lxofftxc += lxoff; 3208 total = lxon + lxoff; 3209 3210 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 3211 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 3212 hw_stats->gptc -= total; 3213 hw_stats->mptc -= total; 3214 hw_stats->ptc64 -= total; 3215 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN; 3216 3217 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 3218 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 3219 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 3220 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 3221 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC); 3222 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC); 3223 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC); 3224 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 3225 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 3226 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 3227 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 3228 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 3229 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 3230 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC); 3231 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 3232 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST); 3233 /* Only read FCOE on 82599 */ 3234 if (hw->mac.type != ixgbe_mac_82598EB) { 3235 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 3236 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 3237 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 3238 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 3239 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 3240 } 3241 3242 /* Flow Director Stats registers */ 3243 if (hw->mac.type != ixgbe_mac_82598EB) { 3244 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 3245 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 3246 hw_stats->fdirustat_add += IXGBE_READ_REG(hw, 3247 IXGBE_FDIRUSTAT) & 0xFFFF; 3248 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw, 3249 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF; 3250 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw, 3251 IXGBE_FDIRFSTAT) & 0xFFFF; 3252 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw, 3253 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF; 3254 } 3255 /* MACsec Stats registers */ 3256 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT); 3257 macsec_stats->out_pkts_encrypted += 3258 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE); 3259 macsec_stats->out_pkts_protected += 3260 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP); 3261 macsec_stats->out_octets_encrypted += 3262 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE); 3263 macsec_stats->out_octets_protected += 3264 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP); 3265 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT); 3266 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD); 3267 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI); 3268 macsec_stats->in_pkts_unknownsci += 3269 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI); 3270 macsec_stats->in_octets_decrypted += 3271 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD); 3272 macsec_stats->in_octets_validated += 3273 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV); 3274 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH); 3275 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY); 3276 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE); 3277 for (i = 0; i < 2; i++) { 3278 macsec_stats->in_pkts_ok += 3279 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i)); 3280 macsec_stats->in_pkts_invalid += 3281 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i)); 3282 macsec_stats->in_pkts_notvalid += 3283 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i)); 3284 } 3285 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA); 3286 macsec_stats->in_pkts_notusingsa += 3287 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA); 3288 } 3289 3290 /* 3291 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c 3292 */ 3293 static int 3294 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3295 { 3296 struct ixgbe_hw *hw = 3297 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3298 struct ixgbe_hw_stats *hw_stats = 3299 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3300 struct ixgbe_macsec_stats *macsec_stats = 3301 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3302 dev->data->dev_private); 3303 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3304 unsigned i; 3305 3306 total_missed_rx = 0; 3307 total_qbrc = 0; 3308 total_qprc = 0; 3309 total_qprdc = 0; 3310 3311 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3312 &total_qbrc, &total_qprc, &total_qprdc); 3313 3314 if (stats == NULL) 3315 return -EINVAL; 3316 3317 /* Fill out the rte_eth_stats statistics structure */ 3318 stats->ipackets = total_qprc; 3319 stats->ibytes = total_qbrc; 3320 stats->opackets = hw_stats->gptc; 3321 stats->obytes = hw_stats->gotc; 3322 3323 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3324 stats->q_ipackets[i] = hw_stats->qprc[i]; 3325 stats->q_opackets[i] = hw_stats->qptc[i]; 3326 stats->q_ibytes[i] = hw_stats->qbrc[i]; 3327 stats->q_obytes[i] = hw_stats->qbtc[i]; 3328 stats->q_errors[i] = hw_stats->qprdc[i]; 3329 } 3330 3331 /* Rx Errors */ 3332 stats->imissed = total_missed_rx; 3333 stats->ierrors = hw_stats->crcerrs + 3334 hw_stats->mspdc + 3335 hw_stats->rlec + 3336 hw_stats->ruc + 3337 hw_stats->roc + 3338 hw_stats->illerrc + 3339 hw_stats->errbc + 3340 hw_stats->rfc + 3341 hw_stats->fccrc + 3342 hw_stats->fclast; 3343 3344 /* 3345 * 82599 errata, UDP frames with a 0 checksum can be marked as checksum 3346 * errors. 3347 */ 3348 if (hw->mac.type != ixgbe_mac_82599EB) 3349 stats->ierrors += hw_stats->xec; 3350 3351 /* Tx Errors */ 3352 stats->oerrors = 0; 3353 return 0; 3354 } 3355 3356 static int 3357 ixgbe_dev_stats_reset(struct rte_eth_dev *dev) 3358 { 3359 struct ixgbe_hw_stats *stats = 3360 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3361 3362 /* HW registers are cleared on read */ 3363 ixgbe_dev_stats_get(dev, NULL); 3364 3365 /* Reset software totals */ 3366 memset(stats, 0, sizeof(*stats)); 3367 3368 return 0; 3369 } 3370 3371 /* This function calculates the number of xstats based on the current config */ 3372 static unsigned 3373 ixgbe_xstats_calc_num(void) { 3374 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS + 3375 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) + 3376 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES); 3377 } 3378 3379 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3380 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size) 3381 { 3382 const unsigned cnt_stats = ixgbe_xstats_calc_num(); 3383 unsigned stat, i, count; 3384 3385 if (xstats_names != NULL) { 3386 count = 0; 3387 3388 /* Note: limit >= cnt_stats checked upstream 3389 * in rte_eth_xstats_names() 3390 */ 3391 3392 /* Extended stats from ixgbe_hw_stats */ 3393 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3394 strlcpy(xstats_names[count].name, 3395 rte_ixgbe_stats_strings[i].name, 3396 sizeof(xstats_names[count].name)); 3397 count++; 3398 } 3399 3400 /* MACsec Stats */ 3401 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3402 strlcpy(xstats_names[count].name, 3403 rte_ixgbe_macsec_strings[i].name, 3404 sizeof(xstats_names[count].name)); 3405 count++; 3406 } 3407 3408 /* RX Priority Stats */ 3409 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3410 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3411 snprintf(xstats_names[count].name, 3412 sizeof(xstats_names[count].name), 3413 "rx_priority%u_%s", i, 3414 rte_ixgbe_rxq_strings[stat].name); 3415 count++; 3416 } 3417 } 3418 3419 /* TX Priority Stats */ 3420 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3421 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3422 snprintf(xstats_names[count].name, 3423 sizeof(xstats_names[count].name), 3424 "tx_priority%u_%s", i, 3425 rte_ixgbe_txq_strings[stat].name); 3426 count++; 3427 } 3428 } 3429 } 3430 return cnt_stats; 3431 } 3432 3433 static int ixgbe_dev_xstats_get_names_by_id( 3434 struct rte_eth_dev *dev, 3435 const uint64_t *ids, 3436 struct rte_eth_xstat_name *xstats_names, 3437 unsigned int limit) 3438 { 3439 if (!ids) { 3440 const unsigned int cnt_stats = ixgbe_xstats_calc_num(); 3441 unsigned int stat, i, count; 3442 3443 if (xstats_names != NULL) { 3444 count = 0; 3445 3446 /* Note: limit >= cnt_stats checked upstream 3447 * in rte_eth_xstats_names() 3448 */ 3449 3450 /* Extended stats from ixgbe_hw_stats */ 3451 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3452 strlcpy(xstats_names[count].name, 3453 rte_ixgbe_stats_strings[i].name, 3454 sizeof(xstats_names[count].name)); 3455 count++; 3456 } 3457 3458 /* MACsec Stats */ 3459 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3460 strlcpy(xstats_names[count].name, 3461 rte_ixgbe_macsec_strings[i].name, 3462 sizeof(xstats_names[count].name)); 3463 count++; 3464 } 3465 3466 /* RX Priority Stats */ 3467 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3468 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3469 snprintf(xstats_names[count].name, 3470 sizeof(xstats_names[count].name), 3471 "rx_priority%u_%s", i, 3472 rte_ixgbe_rxq_strings[stat].name); 3473 count++; 3474 } 3475 } 3476 3477 /* TX Priority Stats */ 3478 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3479 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3480 snprintf(xstats_names[count].name, 3481 sizeof(xstats_names[count].name), 3482 "tx_priority%u_%s", i, 3483 rte_ixgbe_txq_strings[stat].name); 3484 count++; 3485 } 3486 } 3487 } 3488 return cnt_stats; 3489 } 3490 3491 uint16_t i; 3492 uint16_t size = ixgbe_xstats_calc_num(); 3493 struct rte_eth_xstat_name xstats_names_copy[size]; 3494 3495 ixgbe_dev_xstats_get_names_by_id(dev, NULL, xstats_names_copy, 3496 size); 3497 3498 for (i = 0; i < limit; i++) { 3499 if (ids[i] >= size) { 3500 PMD_INIT_LOG(ERR, "id value isn't valid"); 3501 return -1; 3502 } 3503 strcpy(xstats_names[i].name, 3504 xstats_names_copy[ids[i]].name); 3505 } 3506 return limit; 3507 } 3508 3509 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3510 struct rte_eth_xstat_name *xstats_names, unsigned limit) 3511 { 3512 unsigned i; 3513 3514 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL) 3515 return -ENOMEM; 3516 3517 if (xstats_names != NULL) 3518 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) 3519 strlcpy(xstats_names[i].name, 3520 rte_ixgbevf_stats_strings[i].name, 3521 sizeof(xstats_names[i].name)); 3522 return IXGBEVF_NB_XSTATS; 3523 } 3524 3525 static int 3526 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3527 unsigned n) 3528 { 3529 struct ixgbe_hw *hw = 3530 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3531 struct ixgbe_hw_stats *hw_stats = 3532 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3533 struct ixgbe_macsec_stats *macsec_stats = 3534 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3535 dev->data->dev_private); 3536 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3537 unsigned i, stat, count = 0; 3538 3539 count = ixgbe_xstats_calc_num(); 3540 3541 if (n < count) 3542 return count; 3543 3544 total_missed_rx = 0; 3545 total_qbrc = 0; 3546 total_qprc = 0; 3547 total_qprdc = 0; 3548 3549 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3550 &total_qbrc, &total_qprc, &total_qprdc); 3551 3552 /* If this is a reset xstats is NULL, and we have cleared the 3553 * registers by reading them. 3554 */ 3555 if (!xstats) 3556 return 0; 3557 3558 /* Extended stats from ixgbe_hw_stats */ 3559 count = 0; 3560 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3561 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3562 rte_ixgbe_stats_strings[i].offset); 3563 xstats[count].id = count; 3564 count++; 3565 } 3566 3567 /* MACsec Stats */ 3568 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3569 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) + 3570 rte_ixgbe_macsec_strings[i].offset); 3571 xstats[count].id = count; 3572 count++; 3573 } 3574 3575 /* RX Priority Stats */ 3576 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3577 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3578 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3579 rte_ixgbe_rxq_strings[stat].offset + 3580 (sizeof(uint64_t) * i)); 3581 xstats[count].id = count; 3582 count++; 3583 } 3584 } 3585 3586 /* TX Priority Stats */ 3587 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3588 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3589 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3590 rte_ixgbe_txq_strings[stat].offset + 3591 (sizeof(uint64_t) * i)); 3592 xstats[count].id = count; 3593 count++; 3594 } 3595 } 3596 return count; 3597 } 3598 3599 static int 3600 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 3601 uint64_t *values, unsigned int n) 3602 { 3603 if (!ids) { 3604 struct ixgbe_hw *hw = 3605 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3606 struct ixgbe_hw_stats *hw_stats = 3607 IXGBE_DEV_PRIVATE_TO_STATS( 3608 dev->data->dev_private); 3609 struct ixgbe_macsec_stats *macsec_stats = 3610 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3611 dev->data->dev_private); 3612 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3613 unsigned int i, stat, count = 0; 3614 3615 count = ixgbe_xstats_calc_num(); 3616 3617 if (!ids && n < count) 3618 return count; 3619 3620 total_missed_rx = 0; 3621 total_qbrc = 0; 3622 total_qprc = 0; 3623 total_qprdc = 0; 3624 3625 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, 3626 &total_missed_rx, &total_qbrc, &total_qprc, 3627 &total_qprdc); 3628 3629 /* If this is a reset xstats is NULL, and we have cleared the 3630 * registers by reading them. 3631 */ 3632 if (!ids && !values) 3633 return 0; 3634 3635 /* Extended stats from ixgbe_hw_stats */ 3636 count = 0; 3637 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3638 values[count] = *(uint64_t *)(((char *)hw_stats) + 3639 rte_ixgbe_stats_strings[i].offset); 3640 count++; 3641 } 3642 3643 /* MACsec Stats */ 3644 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3645 values[count] = *(uint64_t *)(((char *)macsec_stats) + 3646 rte_ixgbe_macsec_strings[i].offset); 3647 count++; 3648 } 3649 3650 /* RX Priority Stats */ 3651 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3652 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3653 values[count] = 3654 *(uint64_t *)(((char *)hw_stats) + 3655 rte_ixgbe_rxq_strings[stat].offset + 3656 (sizeof(uint64_t) * i)); 3657 count++; 3658 } 3659 } 3660 3661 /* TX Priority Stats */ 3662 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3663 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3664 values[count] = 3665 *(uint64_t *)(((char *)hw_stats) + 3666 rte_ixgbe_txq_strings[stat].offset + 3667 (sizeof(uint64_t) * i)); 3668 count++; 3669 } 3670 } 3671 return count; 3672 } 3673 3674 uint16_t i; 3675 uint16_t size = ixgbe_xstats_calc_num(); 3676 uint64_t values_copy[size]; 3677 3678 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size); 3679 3680 for (i = 0; i < n; i++) { 3681 if (ids[i] >= size) { 3682 PMD_INIT_LOG(ERR, "id value isn't valid"); 3683 return -1; 3684 } 3685 values[i] = values_copy[ids[i]]; 3686 } 3687 return n; 3688 } 3689 3690 static int 3691 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev) 3692 { 3693 struct ixgbe_hw_stats *stats = 3694 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3695 struct ixgbe_macsec_stats *macsec_stats = 3696 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3697 dev->data->dev_private); 3698 3699 unsigned count = ixgbe_xstats_calc_num(); 3700 3701 /* HW registers are cleared on read */ 3702 ixgbe_dev_xstats_get(dev, NULL, count); 3703 3704 /* Reset software totals */ 3705 memset(stats, 0, sizeof(*stats)); 3706 memset(macsec_stats, 0, sizeof(*macsec_stats)); 3707 3708 return 0; 3709 } 3710 3711 static void 3712 ixgbevf_update_stats(struct rte_eth_dev *dev) 3713 { 3714 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3715 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3716 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3717 3718 /* Good Rx packet, include VF loopback */ 3719 UPDATE_VF_STAT(IXGBE_VFGPRC, 3720 hw_stats->last_vfgprc, hw_stats->vfgprc); 3721 3722 /* Good Rx octets, include VF loopback */ 3723 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB, 3724 hw_stats->last_vfgorc, hw_stats->vfgorc); 3725 3726 /* Good Tx packet, include VF loopback */ 3727 UPDATE_VF_STAT(IXGBE_VFGPTC, 3728 hw_stats->last_vfgptc, hw_stats->vfgptc); 3729 3730 /* Good Tx octets, include VF loopback */ 3731 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB, 3732 hw_stats->last_vfgotc, hw_stats->vfgotc); 3733 3734 /* Rx Multicst Packet */ 3735 UPDATE_VF_STAT(IXGBE_VFMPRC, 3736 hw_stats->last_vfmprc, hw_stats->vfmprc); 3737 } 3738 3739 static int 3740 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3741 unsigned n) 3742 { 3743 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3744 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3745 unsigned i; 3746 3747 if (n < IXGBEVF_NB_XSTATS) 3748 return IXGBEVF_NB_XSTATS; 3749 3750 ixgbevf_update_stats(dev); 3751 3752 if (!xstats) 3753 return 0; 3754 3755 /* Extended stats */ 3756 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) { 3757 xstats[i].id = i; 3758 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + 3759 rte_ixgbevf_stats_strings[i].offset); 3760 } 3761 3762 return IXGBEVF_NB_XSTATS; 3763 } 3764 3765 static int 3766 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3767 { 3768 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3769 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3770 3771 ixgbevf_update_stats(dev); 3772 3773 if (stats == NULL) 3774 return -EINVAL; 3775 3776 stats->ipackets = hw_stats->vfgprc; 3777 stats->ibytes = hw_stats->vfgorc; 3778 stats->opackets = hw_stats->vfgptc; 3779 stats->obytes = hw_stats->vfgotc; 3780 return 0; 3781 } 3782 3783 static int 3784 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev) 3785 { 3786 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3787 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3788 3789 /* Sync HW register to the last stats */ 3790 ixgbevf_dev_stats_get(dev, NULL); 3791 3792 /* reset HW current stats*/ 3793 hw_stats->vfgprc = 0; 3794 hw_stats->vfgorc = 0; 3795 hw_stats->vfgptc = 0; 3796 hw_stats->vfgotc = 0; 3797 hw_stats->vfmprc = 0; 3798 3799 return 0; 3800 } 3801 3802 static int 3803 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 3804 { 3805 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3806 u16 eeprom_verh, eeprom_verl; 3807 u32 etrack_id; 3808 int ret; 3809 3810 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh); 3811 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl); 3812 3813 etrack_id = (eeprom_verh << 16) | eeprom_verl; 3814 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id); 3815 if (ret < 0) 3816 return -EINVAL; 3817 3818 ret += 1; /* add the size of '\0' */ 3819 if (fw_size < (size_t)ret) 3820 return ret; 3821 else 3822 return 0; 3823 } 3824 3825 static int 3826 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3827 { 3828 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3829 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3830 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 3831 3832 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3833 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3834 if (RTE_ETH_DEV_SRIOV(dev).active == 0) { 3835 /* 3836 * When DCB/VT is off, maximum number of queues changes, 3837 * except for 82598EB, which remains constant. 3838 */ 3839 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_NONE && 3840 hw->mac.type != ixgbe_mac_82598EB) 3841 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES; 3842 } 3843 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */ 3844 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */ 3845 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3846 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3847 dev_info->max_vfs = pci_dev->max_vfs; 3848 if (hw->mac.type == ixgbe_mac_82598EB) 3849 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS; 3850 else 3851 dev_info->max_vmdq_pools = RTE_ETH_64_POOLS; 3852 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD; 3853 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 3854 dev_info->vmdq_queue_num = dev_info->max_rx_queues; 3855 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3856 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3857 dev_info->rx_queue_offload_capa); 3858 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3859 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3860 3861 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3862 .rx_thresh = { 3863 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3864 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3865 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3866 }, 3867 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3868 .rx_drop_en = 0, 3869 .offloads = 0, 3870 }; 3871 3872 dev_info->default_txconf = (struct rte_eth_txconf) { 3873 .tx_thresh = { 3874 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3875 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3876 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3877 }, 3878 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3879 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3880 .offloads = 0, 3881 }; 3882 3883 dev_info->rx_desc_lim = rx_desc_lim; 3884 dev_info->tx_desc_lim = tx_desc_lim; 3885 3886 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 3887 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 3888 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 3889 3890 dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G; 3891 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 3892 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 3893 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M | 3894 RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G; 3895 3896 if (hw->mac.type == ixgbe_mac_X540 || 3897 hw->mac.type == ixgbe_mac_X540_vf || 3898 hw->mac.type == ixgbe_mac_X550 || 3899 hw->mac.type == ixgbe_mac_X550_vf) { 3900 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_100M; 3901 } 3902 if (hw->mac.type == ixgbe_mac_X550) { 3903 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_2_5G; 3904 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_5G; 3905 } 3906 3907 /* Driver-preferred Rx/Tx parameters */ 3908 dev_info->default_rxportconf.burst_size = 32; 3909 dev_info->default_txportconf.burst_size = 32; 3910 dev_info->default_rxportconf.nb_queues = 1; 3911 dev_info->default_txportconf.nb_queues = 1; 3912 dev_info->default_rxportconf.ring_size = 256; 3913 dev_info->default_txportconf.ring_size = 256; 3914 3915 return 0; 3916 } 3917 3918 static const uint32_t * 3919 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 3920 { 3921 static const uint32_t ptypes[] = { 3922 /* For non-vec functions, 3923 * refers to ixgbe_rxd_pkt_info_to_pkt_type(); 3924 * for vec functions, 3925 * refers to _recv_raw_pkts_vec(). 3926 */ 3927 RTE_PTYPE_L2_ETHER, 3928 RTE_PTYPE_L3_IPV4, 3929 RTE_PTYPE_L3_IPV4_EXT, 3930 RTE_PTYPE_L3_IPV6, 3931 RTE_PTYPE_L3_IPV6_EXT, 3932 RTE_PTYPE_L4_SCTP, 3933 RTE_PTYPE_L4_TCP, 3934 RTE_PTYPE_L4_UDP, 3935 RTE_PTYPE_TUNNEL_IP, 3936 RTE_PTYPE_INNER_L3_IPV6, 3937 RTE_PTYPE_INNER_L3_IPV6_EXT, 3938 RTE_PTYPE_INNER_L4_TCP, 3939 RTE_PTYPE_INNER_L4_UDP, 3940 RTE_PTYPE_UNKNOWN 3941 }; 3942 3943 if (dev->rx_pkt_burst == ixgbe_recv_pkts || 3944 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc || 3945 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc || 3946 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc) 3947 return ptypes; 3948 3949 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON) 3950 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec || 3951 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec) 3952 return ptypes; 3953 #endif 3954 return NULL; 3955 } 3956 3957 static int 3958 ixgbevf_dev_info_get(struct rte_eth_dev *dev, 3959 struct rte_eth_dev_info *dev_info) 3960 { 3961 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3962 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3963 3964 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3965 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3966 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */ 3967 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */ 3968 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD; 3969 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3970 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3971 dev_info->max_vfs = pci_dev->max_vfs; 3972 if (hw->mac.type == ixgbe_mac_82598EB) 3973 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS; 3974 else 3975 dev_info->max_vmdq_pools = RTE_ETH_64_POOLS; 3976 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3977 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3978 dev_info->rx_queue_offload_capa); 3979 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3980 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3981 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 3982 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 3983 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 3984 3985 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3986 .rx_thresh = { 3987 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3988 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3989 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3990 }, 3991 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3992 .rx_drop_en = 0, 3993 .offloads = 0, 3994 }; 3995 3996 dev_info->default_txconf = (struct rte_eth_txconf) { 3997 .tx_thresh = { 3998 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3999 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 4000 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 4001 }, 4002 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 4003 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 4004 .offloads = 0, 4005 }; 4006 4007 dev_info->rx_desc_lim = rx_desc_lim; 4008 dev_info->tx_desc_lim = tx_desc_lim; 4009 4010 return 0; 4011 } 4012 4013 static int 4014 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4015 bool *link_up, int wait_to_complete) 4016 { 4017 struct ixgbe_adapter *adapter = container_of(hw, 4018 struct ixgbe_adapter, hw); 4019 struct ixgbe_mbx_info *mbx = &hw->mbx; 4020 struct ixgbe_mac_info *mac = &hw->mac; 4021 uint32_t links_reg, in_msg; 4022 int ret_val = 0; 4023 4024 /* If we were hit with a reset drop the link */ 4025 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout) 4026 mac->get_link_status = true; 4027 4028 if (!mac->get_link_status) 4029 goto out; 4030 4031 /* if link status is down no point in checking to see if pf is up */ 4032 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 4033 if (!(links_reg & IXGBE_LINKS_UP)) 4034 goto out; 4035 4036 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs 4037 * before the link status is correct 4038 */ 4039 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) { 4040 int i; 4041 4042 for (i = 0; i < 5; i++) { 4043 rte_delay_us(100); 4044 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 4045 4046 if (!(links_reg & IXGBE_LINKS_UP)) 4047 goto out; 4048 } 4049 } 4050 4051 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 4052 case IXGBE_LINKS_SPEED_10G_82599: 4053 *speed = IXGBE_LINK_SPEED_10GB_FULL; 4054 if (hw->mac.type >= ixgbe_mac_X550) { 4055 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4056 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4057 } 4058 break; 4059 case IXGBE_LINKS_SPEED_1G_82599: 4060 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4061 break; 4062 case IXGBE_LINKS_SPEED_100_82599: 4063 *speed = IXGBE_LINK_SPEED_100_FULL; 4064 if (hw->mac.type == ixgbe_mac_X550) { 4065 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4066 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4067 } 4068 break; 4069 case IXGBE_LINKS_SPEED_10_X550EM_A: 4070 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4071 /* Since Reserved in older MAC's */ 4072 if (hw->mac.type >= ixgbe_mac_X550) 4073 *speed = IXGBE_LINK_SPEED_10_FULL; 4074 break; 4075 default: 4076 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4077 } 4078 4079 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) { 4080 if (*speed == IXGBE_LINK_SPEED_UNKNOWN) 4081 mac->get_link_status = true; 4082 else 4083 mac->get_link_status = false; 4084 4085 goto out; 4086 } 4087 4088 /* if the read failed it could just be a mailbox collision, best wait 4089 * until we are called again and don't report an error 4090 */ 4091 if (mbx->ops.read(hw, &in_msg, 1, 0)) 4092 goto out; 4093 4094 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) { 4095 /* msg is not CTS and is NACK we must have lost CTS status */ 4096 if (in_msg & IXGBE_VT_MSGTYPE_NACK) 4097 mac->get_link_status = false; 4098 goto out; 4099 } 4100 4101 /* the pf is talking, if we timed out in the past we reinit */ 4102 if (!mbx->timeout) { 4103 ret_val = -1; 4104 goto out; 4105 } 4106 4107 /* if we passed all the tests above then the link is up and we no 4108 * longer need to check for link 4109 */ 4110 mac->get_link_status = false; 4111 4112 out: 4113 *link_up = !mac->get_link_status; 4114 return ret_val; 4115 } 4116 4117 /* 4118 * If @timeout_ms was 0, it means that it will not return until link complete. 4119 * It returns 1 on complete, return 0 on timeout. 4120 */ 4121 static int 4122 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms) 4123 { 4124 #define WARNING_TIMEOUT 9000 /* 9s in total */ 4125 struct ixgbe_adapter *ad = dev->data->dev_private; 4126 uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT; 4127 4128 while (rte_atomic32_read(&ad->link_thread_running)) { 4129 msec_delay(1); 4130 timeout--; 4131 4132 if (timeout_ms) { 4133 if (!timeout) 4134 return 0; 4135 } else if (!timeout) { 4136 /* It will not return until link complete */ 4137 timeout = WARNING_TIMEOUT; 4138 PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!"); 4139 } 4140 } 4141 4142 return 1; 4143 } 4144 4145 static void * 4146 ixgbe_dev_setup_link_thread_handler(void *param) 4147 { 4148 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4149 struct ixgbe_adapter *ad = dev->data->dev_private; 4150 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4151 struct ixgbe_interrupt *intr = 4152 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4153 u32 speed; 4154 bool autoneg = false; 4155 4156 pthread_detach(pthread_self()); 4157 speed = hw->phy.autoneg_advertised; 4158 if (!speed) 4159 ixgbe_get_link_capabilities(hw, &speed, &autoneg); 4160 4161 ixgbe_setup_link(hw, speed, true); 4162 4163 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 4164 rte_atomic32_clear(&ad->link_thread_running); 4165 return NULL; 4166 } 4167 4168 /* 4169 * In freebsd environment, nic_uio drivers do not support interrupts, 4170 * rte_intr_callback_register() will fail to register interrupts. 4171 * We can not make link status to change from down to up by interrupt 4172 * callback. So we need to wait for the controller to acquire link 4173 * when ports start. 4174 * It returns 0 on link up. 4175 */ 4176 static int 4177 ixgbe_wait_for_link_up(struct ixgbe_hw *hw) 4178 { 4179 #ifdef RTE_EXEC_ENV_FREEBSD 4180 int err, i; 4181 bool link_up = false; 4182 uint32_t speed = 0; 4183 const int nb_iter = 25; 4184 4185 for (i = 0; i < nb_iter; i++) { 4186 err = ixgbe_check_link(hw, &speed, &link_up, 0); 4187 if (err) 4188 return err; 4189 if (link_up) 4190 return 0; 4191 msec_delay(200); 4192 } 4193 4194 return 0; 4195 #else 4196 RTE_SET_USED(hw); 4197 return 0; 4198 #endif 4199 } 4200 4201 /* return 0 means link status changed, -1 means not changed */ 4202 int 4203 ixgbe_dev_link_update_share(struct rte_eth_dev *dev, 4204 int wait_to_complete, int vf) 4205 { 4206 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4207 struct ixgbe_adapter *ad = dev->data->dev_private; 4208 struct rte_eth_link link; 4209 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4210 struct ixgbe_interrupt *intr = 4211 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4212 bool link_up; 4213 int diag; 4214 int wait = 1; 4215 u32 esdp_reg; 4216 4217 memset(&link, 0, sizeof(link)); 4218 link.link_status = RTE_ETH_LINK_DOWN; 4219 link.link_speed = RTE_ETH_SPEED_NUM_NONE; 4220 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX; 4221 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 4222 RTE_ETH_LINK_SPEED_FIXED); 4223 4224 hw->mac.get_link_status = true; 4225 4226 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) 4227 return rte_eth_linkstatus_set(dev, &link); 4228 4229 /* check if it needs to wait to complete, if lsc interrupt is enabled */ 4230 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0) 4231 wait = 0; 4232 4233 /* BSD has no interrupt mechanism, so force NIC status synchronization. */ 4234 #ifdef RTE_EXEC_ENV_FREEBSD 4235 wait = 1; 4236 #endif 4237 4238 if (vf) 4239 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait); 4240 else 4241 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait); 4242 4243 if (diag != 0) { 4244 link.link_speed = RTE_ETH_SPEED_NUM_100M; 4245 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 4246 return rte_eth_linkstatus_set(dev, &link); 4247 } 4248 4249 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) { 4250 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 4251 if ((esdp_reg & IXGBE_ESDP_SDP3)) 4252 link_up = 0; 4253 } 4254 4255 if (link_up == 0) { 4256 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) { 4257 ixgbe_dev_wait_setup_link_complete(dev, 0); 4258 if (rte_atomic32_test_and_set(&ad->link_thread_running)) { 4259 /* To avoid race condition between threads, set 4260 * the IXGBE_FLAG_NEED_LINK_CONFIG flag only 4261 * when there is no link thread running. 4262 */ 4263 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 4264 if (rte_ctrl_thread_create(&ad->link_thread_tid, 4265 "ixgbe-link-handler", 4266 NULL, 4267 ixgbe_dev_setup_link_thread_handler, 4268 dev) < 0) { 4269 PMD_DRV_LOG(ERR, 4270 "Create link thread failed!"); 4271 rte_atomic32_clear(&ad->link_thread_running); 4272 } 4273 } else { 4274 PMD_DRV_LOG(ERR, 4275 "Other link thread is running now!"); 4276 } 4277 } 4278 return rte_eth_linkstatus_set(dev, &link); 4279 } 4280 4281 link.link_status = RTE_ETH_LINK_UP; 4282 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 4283 4284 switch (link_speed) { 4285 default: 4286 case IXGBE_LINK_SPEED_UNKNOWN: 4287 link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN; 4288 break; 4289 4290 case IXGBE_LINK_SPEED_10_FULL: 4291 link.link_speed = RTE_ETH_SPEED_NUM_10M; 4292 break; 4293 4294 case IXGBE_LINK_SPEED_100_FULL: 4295 link.link_speed = RTE_ETH_SPEED_NUM_100M; 4296 break; 4297 4298 case IXGBE_LINK_SPEED_1GB_FULL: 4299 link.link_speed = RTE_ETH_SPEED_NUM_1G; 4300 break; 4301 4302 case IXGBE_LINK_SPEED_2_5GB_FULL: 4303 link.link_speed = RTE_ETH_SPEED_NUM_2_5G; 4304 break; 4305 4306 case IXGBE_LINK_SPEED_5GB_FULL: 4307 link.link_speed = RTE_ETH_SPEED_NUM_5G; 4308 break; 4309 4310 case IXGBE_LINK_SPEED_10GB_FULL: 4311 link.link_speed = RTE_ETH_SPEED_NUM_10G; 4312 break; 4313 } 4314 4315 return rte_eth_linkstatus_set(dev, &link); 4316 } 4317 4318 static int 4319 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4320 { 4321 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0); 4322 } 4323 4324 static int 4325 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4326 { 4327 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1); 4328 } 4329 4330 static int 4331 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 4332 { 4333 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4334 uint32_t fctrl; 4335 4336 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4337 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4338 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4339 4340 return 0; 4341 } 4342 4343 static int 4344 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 4345 { 4346 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4347 uint32_t fctrl; 4348 4349 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4350 fctrl &= (~IXGBE_FCTRL_UPE); 4351 if (dev->data->all_multicast == 1) 4352 fctrl |= IXGBE_FCTRL_MPE; 4353 else 4354 fctrl &= (~IXGBE_FCTRL_MPE); 4355 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4356 4357 return 0; 4358 } 4359 4360 static int 4361 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 4362 { 4363 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4364 uint32_t fctrl; 4365 4366 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4367 fctrl |= IXGBE_FCTRL_MPE; 4368 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4369 4370 return 0; 4371 } 4372 4373 static int 4374 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 4375 { 4376 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4377 uint32_t fctrl; 4378 4379 if (dev->data->promiscuous == 1) 4380 return 0; /* must remain in all_multicast mode */ 4381 4382 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4383 fctrl &= (~IXGBE_FCTRL_MPE); 4384 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4385 4386 return 0; 4387 } 4388 4389 /** 4390 * It clears the interrupt causes and enables the interrupt. 4391 * It will be called once only during nic initialized. 4392 * 4393 * @param dev 4394 * Pointer to struct rte_eth_dev. 4395 * @param on 4396 * Enable or Disable. 4397 * 4398 * @return 4399 * - On success, zero. 4400 * - On failure, a negative value. 4401 */ 4402 static int 4403 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 4404 { 4405 struct ixgbe_interrupt *intr = 4406 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4407 4408 ixgbe_dev_link_status_print(dev); 4409 if (on) 4410 intr->mask |= IXGBE_EICR_LSC; 4411 else 4412 intr->mask &= ~IXGBE_EICR_LSC; 4413 4414 return 0; 4415 } 4416 4417 /** 4418 * It clears the interrupt causes and enables the interrupt. 4419 * It will be called once only during nic initialized. 4420 * 4421 * @param dev 4422 * Pointer to struct rte_eth_dev. 4423 * 4424 * @return 4425 * - On success, zero. 4426 * - On failure, a negative value. 4427 */ 4428 static int 4429 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev) 4430 { 4431 struct ixgbe_interrupt *intr = 4432 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4433 4434 intr->mask |= IXGBE_EICR_RTX_QUEUE; 4435 4436 return 0; 4437 } 4438 4439 /** 4440 * It clears the interrupt causes and enables the interrupt. 4441 * It will be called once only during nic initialized. 4442 * 4443 * @param dev 4444 * Pointer to struct rte_eth_dev. 4445 * 4446 * @return 4447 * - On success, zero. 4448 * - On failure, a negative value. 4449 */ 4450 static int 4451 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev) 4452 { 4453 struct ixgbe_interrupt *intr = 4454 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4455 4456 intr->mask |= IXGBE_EICR_LINKSEC; 4457 4458 return 0; 4459 } 4460 4461 /* 4462 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update. 4463 * 4464 * @param dev 4465 * Pointer to struct rte_eth_dev. 4466 * 4467 * @return 4468 * - On success, zero. 4469 * - On failure, a negative value. 4470 */ 4471 static int 4472 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev) 4473 { 4474 uint32_t eicr; 4475 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4476 struct ixgbe_interrupt *intr = 4477 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4478 4479 /* clear all cause mask */ 4480 ixgbe_disable_intr(hw); 4481 4482 /* read-on-clear nic registers here */ 4483 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4484 PMD_DRV_LOG(DEBUG, "eicr %x", eicr); 4485 4486 intr->flags = 0; 4487 4488 /* set flag for async link update */ 4489 if (eicr & IXGBE_EICR_LSC) 4490 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 4491 4492 if (eicr & IXGBE_EICR_MAILBOX) 4493 intr->flags |= IXGBE_FLAG_MAILBOX; 4494 4495 if (eicr & IXGBE_EICR_LINKSEC) 4496 intr->flags |= IXGBE_FLAG_MACSEC; 4497 4498 if (hw->mac.type == ixgbe_mac_X550EM_x && 4499 hw->phy.type == ixgbe_phy_x550em_ext_t && 4500 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x)) 4501 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT; 4502 4503 return 0; 4504 } 4505 4506 /** 4507 * It gets and then prints the link status. 4508 * 4509 * @param dev 4510 * Pointer to struct rte_eth_dev. 4511 * 4512 * @return 4513 * - On success, zero. 4514 * - On failure, a negative value. 4515 */ 4516 static void 4517 ixgbe_dev_link_status_print(struct rte_eth_dev *dev) 4518 { 4519 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4520 struct rte_eth_link link; 4521 4522 rte_eth_linkstatus_get(dev, &link); 4523 4524 if (link.link_status) { 4525 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", 4526 (int)(dev->data->port_id), 4527 (unsigned)link.link_speed, 4528 link.link_duplex == RTE_ETH_LINK_FULL_DUPLEX ? 4529 "full-duplex" : "half-duplex"); 4530 } else { 4531 PMD_INIT_LOG(INFO, " Port %d: Link Down", 4532 (int)(dev->data->port_id)); 4533 } 4534 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 4535 pci_dev->addr.domain, 4536 pci_dev->addr.bus, 4537 pci_dev->addr.devid, 4538 pci_dev->addr.function); 4539 } 4540 4541 /* 4542 * It executes link_update after knowing an interrupt occurred. 4543 * 4544 * @param dev 4545 * Pointer to struct rte_eth_dev. 4546 * 4547 * @return 4548 * - On success, zero. 4549 * - On failure, a negative value. 4550 */ 4551 static int 4552 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev) 4553 { 4554 struct ixgbe_interrupt *intr = 4555 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4556 int64_t timeout; 4557 struct ixgbe_hw *hw = 4558 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4559 4560 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags); 4561 4562 if (intr->flags & IXGBE_FLAG_MAILBOX) { 4563 ixgbe_pf_mbx_process(dev); 4564 intr->flags &= ~IXGBE_FLAG_MAILBOX; 4565 } 4566 4567 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4568 ixgbe_handle_lasi(hw); 4569 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4570 } 4571 4572 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4573 struct rte_eth_link link; 4574 4575 /* get the link status before link update, for predicting later */ 4576 rte_eth_linkstatus_get(dev, &link); 4577 4578 ixgbe_dev_link_update(dev, 0); 4579 4580 /* likely to up */ 4581 if (!link.link_status) 4582 /* handle it 1 sec later, wait it being stable */ 4583 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT; 4584 /* likely to down */ 4585 else 4586 /* handle it 4 sec later, wait it being stable */ 4587 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT; 4588 4589 ixgbe_dev_link_status_print(dev); 4590 if (rte_eal_alarm_set(timeout * 1000, 4591 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0) 4592 PMD_DRV_LOG(ERR, "Error setting alarm"); 4593 else { 4594 /* remember original mask */ 4595 intr->mask_original = intr->mask; 4596 /* only disable lsc interrupt */ 4597 intr->mask &= ~IXGBE_EIMS_LSC; 4598 } 4599 } 4600 4601 PMD_DRV_LOG(DEBUG, "enable intr immediately"); 4602 ixgbe_enable_intr(dev); 4603 4604 return 0; 4605 } 4606 4607 /** 4608 * Interrupt handler which shall be registered for alarm callback for delayed 4609 * handling specific interrupt to wait for the stable nic state. As the 4610 * NIC interrupt state is not stable for ixgbe after link is just down, 4611 * it needs to wait 4 seconds to get the stable status. 4612 * 4613 * @param handle 4614 * Pointer to interrupt handle. 4615 * @param param 4616 * The address of parameter (struct rte_eth_dev *) registered before. 4617 * 4618 * @return 4619 * void 4620 */ 4621 static void 4622 ixgbe_dev_interrupt_delayed_handler(void *param) 4623 { 4624 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4625 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4626 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 4627 struct ixgbe_interrupt *intr = 4628 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4629 struct ixgbe_hw *hw = 4630 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4631 uint32_t eicr; 4632 4633 ixgbe_disable_intr(hw); 4634 4635 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4636 if (eicr & IXGBE_EICR_MAILBOX) 4637 ixgbe_pf_mbx_process(dev); 4638 4639 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4640 ixgbe_handle_lasi(hw); 4641 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4642 } 4643 4644 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4645 ixgbe_dev_link_update(dev, 0); 4646 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 4647 ixgbe_dev_link_status_print(dev); 4648 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 4649 } 4650 4651 if (intr->flags & IXGBE_FLAG_MACSEC) { 4652 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL); 4653 intr->flags &= ~IXGBE_FLAG_MACSEC; 4654 } 4655 4656 /* restore original mask */ 4657 intr->mask = intr->mask_original; 4658 intr->mask_original = 0; 4659 4660 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr); 4661 ixgbe_enable_intr(dev); 4662 rte_intr_ack(intr_handle); 4663 } 4664 4665 /** 4666 * Interrupt handler triggered by NIC for handling 4667 * specific interrupt. 4668 * 4669 * @param handle 4670 * Pointer to interrupt handle. 4671 * @param param 4672 * The address of parameter (struct rte_eth_dev *) registered before. 4673 * 4674 * @return 4675 * void 4676 */ 4677 static void 4678 ixgbe_dev_interrupt_handler(void *param) 4679 { 4680 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4681 4682 ixgbe_dev_interrupt_get_status(dev); 4683 ixgbe_dev_interrupt_action(dev); 4684 } 4685 4686 static int 4687 ixgbe_dev_led_on(struct rte_eth_dev *dev) 4688 { 4689 struct ixgbe_hw *hw; 4690 4691 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4692 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4693 } 4694 4695 static int 4696 ixgbe_dev_led_off(struct rte_eth_dev *dev) 4697 { 4698 struct ixgbe_hw *hw; 4699 4700 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4701 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4702 } 4703 4704 static int 4705 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4706 { 4707 struct ixgbe_hw *hw; 4708 uint32_t mflcn_reg; 4709 uint32_t fccfg_reg; 4710 int rx_pause; 4711 int tx_pause; 4712 4713 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4714 4715 fc_conf->pause_time = hw->fc.pause_time; 4716 fc_conf->high_water = hw->fc.high_water[0]; 4717 fc_conf->low_water = hw->fc.low_water[0]; 4718 fc_conf->send_xon = hw->fc.send_xon; 4719 fc_conf->autoneg = !hw->fc.disable_fc_autoneg; 4720 4721 /* 4722 * Return rx_pause status according to actual setting of 4723 * MFLCN register. 4724 */ 4725 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4726 if (mflcn_reg & IXGBE_MFLCN_PMCF) 4727 fc_conf->mac_ctrl_frame_fwd = 1; 4728 else 4729 fc_conf->mac_ctrl_frame_fwd = 0; 4730 4731 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE)) 4732 rx_pause = 1; 4733 else 4734 rx_pause = 0; 4735 4736 /* 4737 * Return tx_pause status according to actual setting of 4738 * FCCFG register. 4739 */ 4740 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4741 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY)) 4742 tx_pause = 1; 4743 else 4744 tx_pause = 0; 4745 4746 if (rx_pause && tx_pause) 4747 fc_conf->mode = RTE_ETH_FC_FULL; 4748 else if (rx_pause) 4749 fc_conf->mode = RTE_ETH_FC_RX_PAUSE; 4750 else if (tx_pause) 4751 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 4752 else 4753 fc_conf->mode = RTE_ETH_FC_NONE; 4754 4755 return 0; 4756 } 4757 4758 static int 4759 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4760 { 4761 struct ixgbe_hw *hw; 4762 struct ixgbe_adapter *adapter = dev->data->dev_private; 4763 int err; 4764 uint32_t rx_buf_size; 4765 uint32_t max_high_water; 4766 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4767 ixgbe_fc_none, 4768 ixgbe_fc_rx_pause, 4769 ixgbe_fc_tx_pause, 4770 ixgbe_fc_full 4771 }; 4772 4773 PMD_INIT_FUNC_TRACE(); 4774 4775 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4776 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)); 4777 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4778 4779 /* 4780 * At least reserve one Ethernet frame for watermark 4781 * high_water/low_water in kilo bytes for ixgbe 4782 */ 4783 max_high_water = (rx_buf_size - 4784 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4785 if ((fc_conf->high_water > max_high_water) || 4786 (fc_conf->high_water < fc_conf->low_water)) { 4787 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4788 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4789 return -EINVAL; 4790 } 4791 4792 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode]; 4793 hw->fc.pause_time = fc_conf->pause_time; 4794 hw->fc.high_water[0] = fc_conf->high_water; 4795 hw->fc.low_water[0] = fc_conf->low_water; 4796 hw->fc.send_xon = fc_conf->send_xon; 4797 hw->fc.disable_fc_autoneg = !fc_conf->autoneg; 4798 adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; 4799 4800 err = ixgbe_flow_ctrl_enable(dev, hw); 4801 if (err < 0) { 4802 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err); 4803 return -EIO; 4804 } 4805 return err; 4806 } 4807 4808 /** 4809 * ixgbe_pfc_enable_generic - Enable flow control 4810 * @hw: pointer to hardware structure 4811 * @tc_num: traffic class number 4812 * Enable flow control according to the current settings. 4813 */ 4814 static int 4815 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num) 4816 { 4817 int ret_val = 0; 4818 uint32_t mflcn_reg, fccfg_reg; 4819 uint32_t reg; 4820 uint32_t fcrtl, fcrth; 4821 uint8_t i; 4822 uint8_t nb_rx_en; 4823 4824 /* Validate the water mark configuration */ 4825 if (!hw->fc.pause_time) { 4826 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4827 goto out; 4828 } 4829 4830 /* Low water mark of zero causes XOFF floods */ 4831 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 4832 /* High/Low water can not be 0 */ 4833 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) { 4834 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4835 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4836 goto out; 4837 } 4838 4839 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) { 4840 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4841 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4842 goto out; 4843 } 4844 } 4845 /* Negotiate the fc mode to use */ 4846 ixgbe_fc_autoneg(hw); 4847 4848 /* Disable any previous flow control settings */ 4849 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4850 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE); 4851 4852 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4853 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 4854 4855 switch (hw->fc.current_mode) { 4856 case ixgbe_fc_none: 4857 /* 4858 * If the count of enabled RX Priority Flow control >1, 4859 * and the TX pause can not be disabled 4860 */ 4861 nb_rx_en = 0; 4862 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4863 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4864 if (reg & IXGBE_FCRTH_FCEN) 4865 nb_rx_en++; 4866 } 4867 if (nb_rx_en > 1) 4868 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4869 break; 4870 case ixgbe_fc_rx_pause: 4871 /* 4872 * Rx Flow control is enabled and Tx Flow control is 4873 * disabled by software override. Since there really 4874 * isn't a way to advertise that we are capable of RX 4875 * Pause ONLY, we will advertise that we support both 4876 * symmetric and asymmetric Rx PAUSE. Later, we will 4877 * disable the adapter's ability to send PAUSE frames. 4878 */ 4879 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4880 /* 4881 * If the count of enabled RX Priority Flow control >1, 4882 * and the TX pause can not be disabled 4883 */ 4884 nb_rx_en = 0; 4885 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4886 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4887 if (reg & IXGBE_FCRTH_FCEN) 4888 nb_rx_en++; 4889 } 4890 if (nb_rx_en > 1) 4891 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4892 break; 4893 case ixgbe_fc_tx_pause: 4894 /* 4895 * Tx Flow control is enabled, and Rx Flow control is 4896 * disabled by software override. 4897 */ 4898 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4899 break; 4900 case ixgbe_fc_full: 4901 /* Flow control (both Rx and Tx) is enabled by SW override. */ 4902 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4903 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4904 break; 4905 default: 4906 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly"); 4907 ret_val = IXGBE_ERR_CONFIG; 4908 goto out; 4909 } 4910 4911 /* Set 802.3x based flow control settings. */ 4912 mflcn_reg |= IXGBE_MFLCN_DPF; 4913 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 4914 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 4915 4916 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 4917 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 4918 hw->fc.high_water[tc_num]) { 4919 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE; 4920 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl); 4921 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN; 4922 } else { 4923 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0); 4924 /* 4925 * In order to prevent Tx hangs when the internal Tx 4926 * switch is enabled we must set the high water mark 4927 * to the maximum FCRTH value. This allows the Tx 4928 * switch to function even under heavy Rx workloads. 4929 */ 4930 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32; 4931 } 4932 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth); 4933 4934 /* Configure pause time (2 TCs per register) */ 4935 reg = hw->fc.pause_time * 0x00010001; 4936 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 4937 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 4938 4939 /* Configure flow control refresh threshold value */ 4940 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 4941 4942 out: 4943 return ret_val; 4944 } 4945 4946 static int 4947 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num) 4948 { 4949 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4950 int32_t ret_val = IXGBE_NOT_IMPLEMENTED; 4951 4952 if (hw->mac.type != ixgbe_mac_82598EB) { 4953 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num); 4954 } 4955 return ret_val; 4956 } 4957 4958 static int 4959 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf) 4960 { 4961 int err; 4962 uint32_t rx_buf_size; 4963 uint32_t max_high_water; 4964 uint8_t tc_num; 4965 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 4966 struct ixgbe_hw *hw = 4967 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4968 struct ixgbe_dcb_config *dcb_config = 4969 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 4970 4971 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4972 ixgbe_fc_none, 4973 ixgbe_fc_rx_pause, 4974 ixgbe_fc_tx_pause, 4975 ixgbe_fc_full 4976 }; 4977 4978 PMD_INIT_FUNC_TRACE(); 4979 4980 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map); 4981 tc_num = map[pfc_conf->priority]; 4982 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)); 4983 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4984 /* 4985 * At least reserve one Ethernet frame for watermark 4986 * high_water/low_water in kilo bytes for ixgbe 4987 */ 4988 max_high_water = (rx_buf_size - 4989 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4990 if ((pfc_conf->fc.high_water > max_high_water) || 4991 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) { 4992 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4993 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4994 return -EINVAL; 4995 } 4996 4997 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode]; 4998 hw->fc.pause_time = pfc_conf->fc.pause_time; 4999 hw->fc.send_xon = pfc_conf->fc.send_xon; 5000 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water; 5001 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; 5002 5003 err = ixgbe_dcb_pfc_enable(dev, tc_num); 5004 5005 /* Not negotiated is not an error case */ 5006 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) 5007 return 0; 5008 5009 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err); 5010 return -EIO; 5011 } 5012 5013 static int 5014 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 5015 struct rte_eth_rss_reta_entry64 *reta_conf, 5016 uint16_t reta_size) 5017 { 5018 uint16_t i, sp_reta_size; 5019 uint8_t j, mask; 5020 uint32_t reta, r; 5021 uint16_t idx, shift; 5022 struct ixgbe_adapter *adapter = dev->data->dev_private; 5023 struct rte_eth_dev_data *dev_data = dev->data; 5024 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5025 uint32_t reta_reg; 5026 5027 PMD_INIT_FUNC_TRACE(); 5028 5029 if (!dev_data->dev_started) { 5030 PMD_DRV_LOG(ERR, 5031 "port %d must be started before rss reta update", 5032 dev_data->port_id); 5033 return -EIO; 5034 } 5035 5036 if (!ixgbe_rss_update_sp(hw->mac.type)) { 5037 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " 5038 "NIC."); 5039 return -ENOTSUP; 5040 } 5041 5042 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 5043 if (reta_size != sp_reta_size) { 5044 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 5045 "(%d) doesn't match the number hardware can supported " 5046 "(%d)", reta_size, sp_reta_size); 5047 return -EINVAL; 5048 } 5049 5050 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 5051 idx = i / RTE_ETH_RETA_GROUP_SIZE; 5052 shift = i % RTE_ETH_RETA_GROUP_SIZE; 5053 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 5054 IXGBE_4_BIT_MASK); 5055 if (!mask) 5056 continue; 5057 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 5058 if (mask == IXGBE_4_BIT_MASK) 5059 r = 0; 5060 else 5061 r = IXGBE_READ_REG(hw, reta_reg); 5062 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) { 5063 if (mask & (0x1 << j)) 5064 reta |= reta_conf[idx].reta[shift + j] << 5065 (CHAR_BIT * j); 5066 else 5067 reta |= r & (IXGBE_8_BIT_MASK << 5068 (CHAR_BIT * j)); 5069 } 5070 IXGBE_WRITE_REG(hw, reta_reg, reta); 5071 } 5072 adapter->rss_reta_updated = 1; 5073 5074 return 0; 5075 } 5076 5077 static int 5078 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 5079 struct rte_eth_rss_reta_entry64 *reta_conf, 5080 uint16_t reta_size) 5081 { 5082 uint16_t i, sp_reta_size; 5083 uint8_t j, mask; 5084 uint32_t reta; 5085 uint16_t idx, shift; 5086 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5087 uint32_t reta_reg; 5088 5089 PMD_INIT_FUNC_TRACE(); 5090 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 5091 if (reta_size != sp_reta_size) { 5092 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 5093 "(%d) doesn't match the number hardware can supported " 5094 "(%d)", reta_size, sp_reta_size); 5095 return -EINVAL; 5096 } 5097 5098 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 5099 idx = i / RTE_ETH_RETA_GROUP_SIZE; 5100 shift = i % RTE_ETH_RETA_GROUP_SIZE; 5101 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 5102 IXGBE_4_BIT_MASK); 5103 if (!mask) 5104 continue; 5105 5106 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 5107 reta = IXGBE_READ_REG(hw, reta_reg); 5108 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) { 5109 if (mask & (0x1 << j)) 5110 reta_conf[idx].reta[shift + j] = 5111 ((reta >> (CHAR_BIT * j)) & 5112 IXGBE_8_BIT_MASK); 5113 } 5114 } 5115 5116 return 0; 5117 } 5118 5119 static int 5120 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 5121 uint32_t index, uint32_t pool) 5122 { 5123 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5124 uint32_t enable_addr = 1; 5125 5126 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes, 5127 pool, enable_addr); 5128 } 5129 5130 static void 5131 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) 5132 { 5133 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5134 5135 ixgbe_clear_rar(hw, index); 5136 } 5137 5138 static int 5139 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 5140 { 5141 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5142 5143 ixgbe_remove_rar(dev, 0); 5144 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs); 5145 5146 return 0; 5147 } 5148 5149 static bool 5150 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 5151 { 5152 if (strcmp(dev->device->driver->name, drv->driver.name)) 5153 return false; 5154 5155 return true; 5156 } 5157 5158 bool 5159 is_ixgbe_supported(struct rte_eth_dev *dev) 5160 { 5161 return is_device_supported(dev, &rte_ixgbe_pmd); 5162 } 5163 5164 static int 5165 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 5166 { 5167 uint32_t hlreg0; 5168 uint32_t maxfrs; 5169 struct ixgbe_hw *hw; 5170 struct rte_eth_dev_info dev_info; 5171 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD; 5172 int ret; 5173 5174 ret = ixgbe_dev_info_get(dev, &dev_info); 5175 if (ret != 0) 5176 return ret; 5177 5178 /* check that mtu is within the allowed range */ 5179 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) 5180 return -EINVAL; 5181 5182 /* If device is started, refuse mtu that requires the support of 5183 * scattered packets when this feature has not been enabled before. 5184 */ 5185 if (dev->data->dev_started && !dev->data->scattered_rx && 5186 frame_size + 2 * RTE_VLAN_HLEN > 5187 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) { 5188 PMD_INIT_LOG(ERR, "Stop port first."); 5189 return -EINVAL; 5190 } 5191 5192 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5193 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 5194 5195 /* switch to jumbo mode if needed */ 5196 if (mtu > RTE_ETHER_MTU) 5197 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 5198 else 5199 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; 5200 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 5201 5202 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS); 5203 maxfrs &= 0x0000FFFF; 5204 maxfrs |= (frame_size << 16); 5205 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs); 5206 5207 return 0; 5208 } 5209 5210 /* 5211 * Virtual Function operations 5212 */ 5213 static void 5214 ixgbevf_intr_disable(struct rte_eth_dev *dev) 5215 { 5216 struct ixgbe_interrupt *intr = 5217 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5218 struct ixgbe_hw *hw = 5219 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5220 5221 PMD_INIT_FUNC_TRACE(); 5222 5223 /* Clear interrupt mask to stop from interrupts being generated */ 5224 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK); 5225 5226 IXGBE_WRITE_FLUSH(hw); 5227 5228 /* Clear mask value. */ 5229 intr->mask = 0; 5230 } 5231 5232 static void 5233 ixgbevf_intr_enable(struct rte_eth_dev *dev) 5234 { 5235 struct ixgbe_interrupt *intr = 5236 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5237 struct ixgbe_hw *hw = 5238 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5239 5240 PMD_INIT_FUNC_TRACE(); 5241 5242 /* VF enable interrupt autoclean */ 5243 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK); 5244 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK); 5245 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK); 5246 5247 IXGBE_WRITE_FLUSH(hw); 5248 5249 /* Save IXGBE_VTEIMS value to mask. */ 5250 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK; 5251 } 5252 5253 static int 5254 ixgbevf_dev_configure(struct rte_eth_dev *dev) 5255 { 5256 struct rte_eth_conf *conf = &dev->data->dev_conf; 5257 struct ixgbe_adapter *adapter = dev->data->dev_private; 5258 5259 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d", 5260 dev->data->port_id); 5261 5262 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 5263 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; 5264 5265 /* 5266 * VF has no ability to enable/disable HW CRC 5267 * Keep the persistent behavior the same as Host PF 5268 */ 5269 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC 5270 if (conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) { 5271 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip"); 5272 conf->rxmode.offloads &= ~RTE_ETH_RX_OFFLOAD_KEEP_CRC; 5273 } 5274 #else 5275 if (!(conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)) { 5276 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip"); 5277 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_KEEP_CRC; 5278 } 5279 #endif 5280 5281 /* 5282 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 5283 * allocation or vector Rx preconditions we will reset it. 5284 */ 5285 adapter->rx_bulk_alloc_allowed = true; 5286 adapter->rx_vec_allowed = true; 5287 5288 return 0; 5289 } 5290 5291 static int 5292 ixgbevf_dev_start(struct rte_eth_dev *dev) 5293 { 5294 struct ixgbe_hw *hw = 5295 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5296 uint32_t intr_vector = 0; 5297 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5298 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 5299 5300 int err, mask = 0; 5301 5302 PMD_INIT_FUNC_TRACE(); 5303 5304 /* Stop the link setup handler before resetting the HW. */ 5305 ixgbe_dev_wait_setup_link_complete(dev, 0); 5306 5307 err = hw->mac.ops.reset_hw(hw); 5308 5309 /** 5310 * In this case, reuses the MAC address assigned by VF 5311 * initialization. 5312 */ 5313 if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) { 5314 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err); 5315 return err; 5316 } 5317 5318 hw->mac.get_link_status = true; 5319 5320 /* negotiate mailbox API version to use with the PF. */ 5321 ixgbevf_negotiate_api(hw); 5322 5323 ixgbevf_dev_tx_init(dev); 5324 5325 /* This can fail when allocating mbufs for descriptor rings */ 5326 err = ixgbevf_dev_rx_init(dev); 5327 if (err) { 5328 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err); 5329 ixgbe_dev_clear_queues(dev); 5330 return err; 5331 } 5332 5333 /* Set vfta */ 5334 ixgbevf_set_vfta_all(dev, 1); 5335 5336 /* Set HW strip */ 5337 mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK | 5338 RTE_ETH_VLAN_EXTEND_MASK; 5339 err = ixgbevf_vlan_offload_config(dev, mask); 5340 if (err) { 5341 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err); 5342 ixgbe_dev_clear_queues(dev); 5343 return err; 5344 } 5345 5346 ixgbevf_dev_rxtx_start(dev); 5347 5348 /* check and configure queue intr-vector mapping */ 5349 if (rte_intr_cap_multiple(intr_handle) && 5350 dev->data->dev_conf.intr_conf.rxq) { 5351 /* According to datasheet, only vector 0/1/2 can be used, 5352 * now only one vector is used for Rx queue 5353 */ 5354 intr_vector = 1; 5355 if (rte_intr_efd_enable(intr_handle, intr_vector)) { 5356 ixgbe_dev_clear_queues(dev); 5357 return -1; 5358 } 5359 } 5360 5361 if (rte_intr_dp_is_en(intr_handle)) { 5362 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec", 5363 dev->data->nb_rx_queues)) { 5364 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 5365 " intr_vec", dev->data->nb_rx_queues); 5366 ixgbe_dev_clear_queues(dev); 5367 return -ENOMEM; 5368 } 5369 } 5370 ixgbevf_configure_msix(dev); 5371 5372 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt 5373 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ). 5374 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( ) 5375 * is not cleared, it will fail when following rte_intr_enable( ) tries 5376 * to map Rx queue interrupt to other VFIO vectors. 5377 * So clear uio/vfio intr/evevnfd first to avoid failure. 5378 */ 5379 rte_intr_disable(intr_handle); 5380 5381 rte_intr_enable(intr_handle); 5382 5383 /* Re-enable interrupt for VF */ 5384 ixgbevf_intr_enable(dev); 5385 5386 /* 5387 * Update link status right before return, because it may 5388 * start link configuration process in a separate thread. 5389 */ 5390 ixgbevf_dev_link_update(dev, 0); 5391 5392 hw->adapter_stopped = false; 5393 5394 return 0; 5395 } 5396 5397 static int 5398 ixgbevf_dev_stop(struct rte_eth_dev *dev) 5399 { 5400 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5401 struct ixgbe_adapter *adapter = dev->data->dev_private; 5402 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5403 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 5404 5405 if (hw->adapter_stopped) 5406 return 0; 5407 5408 PMD_INIT_FUNC_TRACE(); 5409 5410 ixgbe_dev_wait_setup_link_complete(dev, 0); 5411 5412 ixgbevf_intr_disable(dev); 5413 5414 dev->data->dev_started = 0; 5415 hw->adapter_stopped = 1; 5416 ixgbe_stop_adapter(hw); 5417 5418 /* 5419 * Clear what we set, but we still keep shadow_vfta to 5420 * restore after device starts 5421 */ 5422 ixgbevf_set_vfta_all(dev, 0); 5423 5424 /* Clear stored conf */ 5425 dev->data->scattered_rx = 0; 5426 5427 ixgbe_dev_clear_queues(dev); 5428 5429 /* Clean datapath event and queue/vec mapping */ 5430 rte_intr_efd_disable(intr_handle); 5431 rte_intr_vec_list_free(intr_handle); 5432 5433 adapter->rss_reta_updated = 0; 5434 5435 return 0; 5436 } 5437 5438 static int 5439 ixgbevf_dev_close(struct rte_eth_dev *dev) 5440 { 5441 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5442 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5443 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 5444 int ret; 5445 5446 PMD_INIT_FUNC_TRACE(); 5447 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5448 return 0; 5449 5450 ixgbe_reset_hw(hw); 5451 5452 ret = ixgbevf_dev_stop(dev); 5453 5454 ixgbe_dev_free_queues(dev); 5455 5456 /** 5457 * Remove the VF MAC address ro ensure 5458 * that the VF traffic goes to the PF 5459 * after stop, close and detach of the VF 5460 **/ 5461 ixgbevf_remove_mac_addr(dev, 0); 5462 5463 rte_intr_disable(intr_handle); 5464 rte_intr_callback_unregister(intr_handle, 5465 ixgbevf_dev_interrupt_handler, dev); 5466 5467 return ret; 5468 } 5469 5470 /* 5471 * Reset VF device 5472 */ 5473 static int 5474 ixgbevf_dev_reset(struct rte_eth_dev *dev) 5475 { 5476 int ret; 5477 5478 ret = eth_ixgbevf_dev_uninit(dev); 5479 if (ret) 5480 return ret; 5481 5482 ret = eth_ixgbevf_dev_init(dev); 5483 5484 return ret; 5485 } 5486 5487 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) 5488 { 5489 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5490 struct ixgbe_vfta *shadow_vfta = 5491 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5492 int i = 0, j = 0, vfta = 0, mask = 1; 5493 5494 for (i = 0; i < IXGBE_VFTA_SIZE; i++) { 5495 vfta = shadow_vfta->vfta[i]; 5496 if (vfta) { 5497 mask = 1; 5498 for (j = 0; j < 32; j++) { 5499 if (vfta & mask) 5500 ixgbe_set_vfta(hw, (i<<5)+j, 0, 5501 on, false); 5502 mask <<= 1; 5503 } 5504 } 5505 } 5506 5507 } 5508 5509 static int 5510 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 5511 { 5512 struct ixgbe_hw *hw = 5513 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5514 struct ixgbe_vfta *shadow_vfta = 5515 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5516 uint32_t vid_idx = 0; 5517 uint32_t vid_bit = 0; 5518 int ret = 0; 5519 5520 PMD_INIT_FUNC_TRACE(); 5521 5522 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */ 5523 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false); 5524 if (ret) { 5525 PMD_INIT_LOG(ERR, "Unable to set VF vlan"); 5526 return ret; 5527 } 5528 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 5529 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 5530 5531 /* Save what we set and retore it after device reset */ 5532 if (on) 5533 shadow_vfta->vfta[vid_idx] |= vid_bit; 5534 else 5535 shadow_vfta->vfta[vid_idx] &= ~vid_bit; 5536 5537 return 0; 5538 } 5539 5540 static void 5541 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 5542 { 5543 struct ixgbe_hw *hw = 5544 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5545 uint32_t ctrl; 5546 5547 PMD_INIT_FUNC_TRACE(); 5548 5549 if (queue >= hw->mac.max_rx_queues) 5550 return; 5551 5552 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 5553 if (on) 5554 ctrl |= IXGBE_RXDCTL_VME; 5555 else 5556 ctrl &= ~IXGBE_RXDCTL_VME; 5557 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 5558 5559 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on); 5560 } 5561 5562 static int 5563 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask) 5564 { 5565 struct ixgbe_rx_queue *rxq; 5566 uint16_t i; 5567 int on = 0; 5568 5569 /* VF function only support hw strip feature, others are not support */ 5570 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 5571 for (i = 0; i < dev->data->nb_rx_queues; i++) { 5572 rxq = dev->data->rx_queues[i]; 5573 on = !!(rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP); 5574 ixgbevf_vlan_strip_queue_set(dev, i, on); 5575 } 5576 } 5577 5578 return 0; 5579 } 5580 5581 static int 5582 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 5583 { 5584 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 5585 5586 ixgbevf_vlan_offload_config(dev, mask); 5587 5588 return 0; 5589 } 5590 5591 int 5592 ixgbe_vt_check(struct ixgbe_hw *hw) 5593 { 5594 uint32_t reg_val; 5595 5596 /* if Virtualization Technology is enabled */ 5597 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 5598 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) { 5599 PMD_INIT_LOG(ERR, "VT must be enabled for this setting"); 5600 return -1; 5601 } 5602 5603 return 0; 5604 } 5605 5606 static uint32_t 5607 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr) 5608 { 5609 uint32_t vector = 0; 5610 5611 switch (hw->mac.mc_filter_type) { 5612 case 0: /* use bits [47:36] of the address */ 5613 vector = ((uc_addr->addr_bytes[4] >> 4) | 5614 (((uint16_t)uc_addr->addr_bytes[5]) << 4)); 5615 break; 5616 case 1: /* use bits [46:35] of the address */ 5617 vector = ((uc_addr->addr_bytes[4] >> 3) | 5618 (((uint16_t)uc_addr->addr_bytes[5]) << 5)); 5619 break; 5620 case 2: /* use bits [45:34] of the address */ 5621 vector = ((uc_addr->addr_bytes[4] >> 2) | 5622 (((uint16_t)uc_addr->addr_bytes[5]) << 6)); 5623 break; 5624 case 3: /* use bits [43:32] of the address */ 5625 vector = ((uc_addr->addr_bytes[4]) | 5626 (((uint16_t)uc_addr->addr_bytes[5]) << 8)); 5627 break; 5628 default: /* Invalid mc_filter_type */ 5629 break; 5630 } 5631 5632 /* vector can only be 12-bits or boundary will be exceeded */ 5633 vector &= 0xFFF; 5634 return vector; 5635 } 5636 5637 static int 5638 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, 5639 struct rte_ether_addr *mac_addr, uint8_t on) 5640 { 5641 uint32_t vector; 5642 uint32_t uta_idx; 5643 uint32_t reg_val; 5644 uint32_t uta_shift; 5645 uint32_t rc; 5646 const uint32_t ixgbe_uta_idx_mask = 0x7F; 5647 const uint32_t ixgbe_uta_bit_shift = 5; 5648 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1; 5649 const uint32_t bit1 = 0x1; 5650 5651 struct ixgbe_hw *hw = 5652 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5653 struct ixgbe_uta_info *uta_info = 5654 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5655 5656 /* The UTA table only exists on 82599 hardware and newer */ 5657 if (hw->mac.type < ixgbe_mac_82599EB) 5658 return -ENOTSUP; 5659 5660 vector = ixgbe_uta_vector(hw, mac_addr); 5661 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask; 5662 uta_shift = vector & ixgbe_uta_bit_mask; 5663 5664 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0); 5665 if (rc == on) 5666 return 0; 5667 5668 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx)); 5669 if (on) { 5670 uta_info->uta_in_use++; 5671 reg_val |= (bit1 << uta_shift); 5672 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift); 5673 } else { 5674 uta_info->uta_in_use--; 5675 reg_val &= ~(bit1 << uta_shift); 5676 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift); 5677 } 5678 5679 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val); 5680 5681 if (uta_info->uta_in_use > 0) 5682 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 5683 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 5684 else 5685 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 5686 5687 return 0; 5688 } 5689 5690 static int 5691 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) 5692 { 5693 int i; 5694 struct ixgbe_hw *hw = 5695 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5696 struct ixgbe_uta_info *uta_info = 5697 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5698 5699 /* The UTA table only exists on 82599 hardware and newer */ 5700 if (hw->mac.type < ixgbe_mac_82599EB) 5701 return -ENOTSUP; 5702 5703 if (on) { 5704 for (i = 0; i < RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5705 uta_info->uta_shadow[i] = ~0; 5706 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); 5707 } 5708 } else { 5709 for (i = 0; i < RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5710 uta_info->uta_shadow[i] = 0; 5711 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 5712 } 5713 } 5714 return 0; 5715 5716 } 5717 5718 uint32_t 5719 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val) 5720 { 5721 uint32_t new_val = orig_val; 5722 5723 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_UNTAG) 5724 new_val |= IXGBE_VMOLR_AUPE; 5725 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_HASH_MC) 5726 new_val |= IXGBE_VMOLR_ROMPE; 5727 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_HASH_UC) 5728 new_val |= IXGBE_VMOLR_ROPE; 5729 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_BROADCAST) 5730 new_val |= IXGBE_VMOLR_BAM; 5731 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_MULTICAST) 5732 new_val |= IXGBE_VMOLR_MPE; 5733 5734 return new_val; 5735 } 5736 5737 static int 5738 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5739 { 5740 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5741 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 5742 struct ixgbe_interrupt *intr = 5743 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5744 struct ixgbe_hw *hw = 5745 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5746 uint32_t vec = IXGBE_MISC_VEC_ID; 5747 5748 if (rte_intr_allow_others(intr_handle)) 5749 vec = IXGBE_RX_VEC_START; 5750 intr->mask |= (1 << vec); 5751 RTE_SET_USED(queue_id); 5752 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5753 5754 rte_intr_ack(intr_handle); 5755 5756 return 0; 5757 } 5758 5759 static int 5760 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5761 { 5762 struct ixgbe_interrupt *intr = 5763 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5764 struct ixgbe_hw *hw = 5765 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5766 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5767 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 5768 uint32_t vec = IXGBE_MISC_VEC_ID; 5769 5770 if (rte_intr_allow_others(intr_handle)) 5771 vec = IXGBE_RX_VEC_START; 5772 intr->mask &= ~(1 << vec); 5773 RTE_SET_USED(queue_id); 5774 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5775 5776 return 0; 5777 } 5778 5779 static int 5780 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5781 { 5782 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5783 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 5784 uint32_t mask; 5785 struct ixgbe_hw *hw = 5786 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5787 struct ixgbe_interrupt *intr = 5788 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5789 5790 if (queue_id < 16) { 5791 ixgbe_disable_intr(hw); 5792 intr->mask |= (1 << queue_id); 5793 ixgbe_enable_intr(dev); 5794 } else if (queue_id < 32) { 5795 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5796 mask &= (1 << queue_id); 5797 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5798 } else if (queue_id < 64) { 5799 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5800 mask &= (1 << (queue_id - 32)); 5801 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5802 } 5803 rte_intr_ack(intr_handle); 5804 5805 return 0; 5806 } 5807 5808 static int 5809 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5810 { 5811 uint32_t mask; 5812 struct ixgbe_hw *hw = 5813 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5814 struct ixgbe_interrupt *intr = 5815 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5816 5817 if (queue_id < 16) { 5818 ixgbe_disable_intr(hw); 5819 intr->mask &= ~(1 << queue_id); 5820 ixgbe_enable_intr(dev); 5821 } else if (queue_id < 32) { 5822 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5823 mask &= ~(1 << queue_id); 5824 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5825 } else if (queue_id < 64) { 5826 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5827 mask &= ~(1 << (queue_id - 32)); 5828 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5829 } 5830 5831 return 0; 5832 } 5833 5834 static void 5835 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 5836 uint8_t queue, uint8_t msix_vector) 5837 { 5838 uint32_t tmp, idx; 5839 5840 if (direction == -1) { 5841 /* other causes */ 5842 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5843 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC); 5844 tmp &= ~0xFF; 5845 tmp |= msix_vector; 5846 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp); 5847 } else { 5848 /* rx or tx cause */ 5849 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5850 idx = ((16 * (queue & 1)) + (8 * direction)); 5851 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1)); 5852 tmp &= ~(0xFF << idx); 5853 tmp |= (msix_vector << idx); 5854 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp); 5855 } 5856 } 5857 5858 /** 5859 * set the IVAR registers, mapping interrupt causes to vectors 5860 * @param hw 5861 * pointer to ixgbe_hw struct 5862 * @direction 5863 * 0 for Rx, 1 for Tx, -1 for other causes 5864 * @queue 5865 * queue to map the corresponding interrupt to 5866 * @msix_vector 5867 * the vector to map to the corresponding queue 5868 */ 5869 static void 5870 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 5871 uint8_t queue, uint8_t msix_vector) 5872 { 5873 uint32_t tmp, idx; 5874 5875 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5876 if (hw->mac.type == ixgbe_mac_82598EB) { 5877 if (direction == -1) 5878 direction = 0; 5879 idx = (((direction * 64) + queue) >> 2) & 0x1F; 5880 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx)); 5881 tmp &= ~(0xFF << (8 * (queue & 0x3))); 5882 tmp |= (msix_vector << (8 * (queue & 0x3))); 5883 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp); 5884 } else if ((hw->mac.type == ixgbe_mac_82599EB) || 5885 (hw->mac.type == ixgbe_mac_X540) || 5886 (hw->mac.type == ixgbe_mac_X550) || 5887 (hw->mac.type == ixgbe_mac_X550EM_x)) { 5888 if (direction == -1) { 5889 /* other causes */ 5890 idx = ((queue & 1) * 8); 5891 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC); 5892 tmp &= ~(0xFF << idx); 5893 tmp |= (msix_vector << idx); 5894 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp); 5895 } else { 5896 /* rx or tx causes */ 5897 idx = ((16 * (queue & 1)) + (8 * direction)); 5898 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 5899 tmp &= ~(0xFF << idx); 5900 tmp |= (msix_vector << idx); 5901 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp); 5902 } 5903 } 5904 } 5905 5906 static void 5907 ixgbevf_configure_msix(struct rte_eth_dev *dev) 5908 { 5909 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5910 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 5911 struct ixgbe_hw *hw = 5912 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5913 uint32_t q_idx; 5914 uint32_t vector_idx = IXGBE_MISC_VEC_ID; 5915 uint32_t base = IXGBE_MISC_VEC_ID; 5916 5917 /* Configure VF other cause ivar */ 5918 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx); 5919 5920 /* won't configure msix register if no mapping is done 5921 * between intr vector and event fd. 5922 */ 5923 if (!rte_intr_dp_is_en(intr_handle)) 5924 return; 5925 5926 if (rte_intr_allow_others(intr_handle)) { 5927 base = IXGBE_RX_VEC_START; 5928 vector_idx = IXGBE_RX_VEC_START; 5929 } 5930 5931 /* Configure all RX queues of VF */ 5932 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) { 5933 /* Force all queue use vector 0, 5934 * as IXGBE_VF_MAXMSIVECTOR = 1 5935 */ 5936 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx); 5937 rte_intr_vec_list_index_set(intr_handle, q_idx, 5938 vector_idx); 5939 if (vector_idx < base + rte_intr_nb_efd_get(intr_handle) 5940 - 1) 5941 vector_idx++; 5942 } 5943 5944 /* As RX queue setting above show, all queues use the vector 0. 5945 * Set only the ITR value of IXGBE_MISC_VEC_ID. 5946 */ 5947 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID), 5948 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 5949 | IXGBE_EITR_CNT_WDIS); 5950 } 5951 5952 /** 5953 * Sets up the hardware to properly generate MSI-X interrupts 5954 * @hw 5955 * board private structure 5956 */ 5957 static void 5958 ixgbe_configure_msix(struct rte_eth_dev *dev) 5959 { 5960 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5961 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 5962 struct ixgbe_hw *hw = 5963 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5964 uint32_t queue_id, base = IXGBE_MISC_VEC_ID; 5965 uint32_t vec = IXGBE_MISC_VEC_ID; 5966 uint32_t mask; 5967 uint32_t gpie; 5968 5969 /* won't configure msix register if no mapping is done 5970 * between intr vector and event fd 5971 * but if misx has been enabled already, need to configure 5972 * auto clean, auto mask and throttling. 5973 */ 5974 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 5975 if (!rte_intr_dp_is_en(intr_handle) && 5976 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT))) 5977 return; 5978 5979 if (rte_intr_allow_others(intr_handle)) 5980 vec = base = IXGBE_RX_VEC_START; 5981 5982 /* setup GPIE for MSI-x mode */ 5983 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 5984 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5985 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME; 5986 /* auto clearing and auto setting corresponding bits in EIMS 5987 * when MSI-X interrupt is triggered 5988 */ 5989 if (hw->mac.type == ixgbe_mac_82598EB) { 5990 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5991 } else { 5992 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5993 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5994 } 5995 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5996 5997 /* Populate the IVAR table and set the ITR values to the 5998 * corresponding register. 5999 */ 6000 if (rte_intr_dp_is_en(intr_handle)) { 6001 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; 6002 queue_id++) { 6003 /* by default, 1:1 mapping */ 6004 ixgbe_set_ivar_map(hw, 0, queue_id, vec); 6005 rte_intr_vec_list_index_set(intr_handle, 6006 queue_id, vec); 6007 if (vec < base + rte_intr_nb_efd_get(intr_handle) 6008 - 1) 6009 vec++; 6010 } 6011 6012 switch (hw->mac.type) { 6013 case ixgbe_mac_82598EB: 6014 ixgbe_set_ivar_map(hw, -1, 6015 IXGBE_IVAR_OTHER_CAUSES_INDEX, 6016 IXGBE_MISC_VEC_ID); 6017 break; 6018 case ixgbe_mac_82599EB: 6019 case ixgbe_mac_X540: 6020 case ixgbe_mac_X550: 6021 case ixgbe_mac_X550EM_x: 6022 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID); 6023 break; 6024 default: 6025 break; 6026 } 6027 } 6028 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID), 6029 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 6030 | IXGBE_EITR_CNT_WDIS); 6031 6032 /* set up to autoclear timer, and the vectors */ 6033 mask = IXGBE_EIMS_ENABLE_MASK; 6034 mask &= ~(IXGBE_EIMS_OTHER | 6035 IXGBE_EIMS_MAILBOX | 6036 IXGBE_EIMS_LSC); 6037 6038 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask); 6039 } 6040 6041 int 6042 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, 6043 uint16_t queue_idx, uint16_t tx_rate) 6044 { 6045 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6046 uint32_t rf_dec, rf_int; 6047 uint32_t bcnrc_val; 6048 uint16_t link_speed = dev->data->dev_link.link_speed; 6049 6050 if (queue_idx >= hw->mac.max_tx_queues) 6051 return -EINVAL; 6052 6053 if (tx_rate != 0) { 6054 /* Calculate the rate factor values to set */ 6055 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate; 6056 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate; 6057 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate; 6058 6059 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA; 6060 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) & 6061 IXGBE_RTTBCNRC_RF_INT_MASK_M); 6062 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK); 6063 } else { 6064 bcnrc_val = 0; 6065 } 6066 6067 /* 6068 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 6069 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise 6070 * set as 0x4. 6071 */ 6072 if (dev->data->mtu + IXGBE_ETH_OVERHEAD >= IXGBE_MAX_JUMBO_FRAME_SIZE) 6073 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, IXGBE_MMW_SIZE_JUMBO_FRAME); 6074 else 6075 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, IXGBE_MMW_SIZE_DEFAULT); 6076 6077 /* Set RTTBCNRC of queue X */ 6078 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx); 6079 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 6080 IXGBE_WRITE_FLUSH(hw); 6081 6082 return 0; 6083 } 6084 6085 static int 6086 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 6087 __rte_unused uint32_t index, 6088 __rte_unused uint32_t pool) 6089 { 6090 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6091 int diag; 6092 6093 /* 6094 * On a 82599 VF, adding again the same MAC addr is not an idempotent 6095 * operation. Trap this case to avoid exhausting the [very limited] 6096 * set of PF resources used to store VF MAC addresses. 6097 */ 6098 if (memcmp(hw->mac.perm_addr, mac_addr, 6099 sizeof(struct rte_ether_addr)) == 0) 6100 return -1; 6101 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6102 if (diag != 0) 6103 PMD_DRV_LOG(ERR, "Unable to add MAC address " 6104 RTE_ETHER_ADDR_PRT_FMT " - diag=%d", 6105 RTE_ETHER_ADDR_BYTES(mac_addr), diag); 6106 return diag; 6107 } 6108 6109 static void 6110 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index) 6111 { 6112 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6113 struct rte_ether_addr *perm_addr = 6114 (struct rte_ether_addr *)hw->mac.perm_addr; 6115 struct rte_ether_addr *mac_addr; 6116 uint32_t i; 6117 int diag; 6118 6119 /* 6120 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does 6121 * not support the deletion of a given MAC address. 6122 * Instead, it imposes to delete all MAC addresses, then to add again 6123 * all MAC addresses with the exception of the one to be deleted. 6124 */ 6125 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL); 6126 6127 /* 6128 * Add again all MAC addresses, with the exception of the deleted one 6129 * and of the permanent MAC address. 6130 */ 6131 for (i = 0, mac_addr = dev->data->mac_addrs; 6132 i < hw->mac.num_rar_entries; i++, mac_addr++) { 6133 /* Skip the deleted MAC address */ 6134 if (i == index) 6135 continue; 6136 /* Skip NULL MAC addresses */ 6137 if (rte_is_zero_ether_addr(mac_addr)) 6138 continue; 6139 /* Skip the permanent MAC address */ 6140 if (memcmp(perm_addr, mac_addr, 6141 sizeof(struct rte_ether_addr)) == 0) 6142 continue; 6143 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6144 if (diag != 0) 6145 PMD_DRV_LOG(ERR, 6146 "Adding again MAC address " 6147 RTE_ETHER_ADDR_PRT_FMT " failed " 6148 "diag=%d", RTE_ETHER_ADDR_BYTES(mac_addr), 6149 diag); 6150 } 6151 } 6152 6153 static int 6154 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 6155 struct rte_ether_addr *addr) 6156 { 6157 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6158 6159 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0); 6160 6161 return 0; 6162 } 6163 6164 int 6165 ixgbe_syn_filter_set(struct rte_eth_dev *dev, 6166 struct rte_eth_syn_filter *filter, 6167 bool add) 6168 { 6169 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6170 struct ixgbe_filter_info *filter_info = 6171 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6172 uint32_t syn_info; 6173 uint32_t synqf; 6174 6175 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6176 return -EINVAL; 6177 6178 syn_info = filter_info->syn_info; 6179 6180 if (add) { 6181 if (syn_info & IXGBE_SYN_FILTER_ENABLE) 6182 return -EINVAL; 6183 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) & 6184 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE); 6185 6186 if (filter->hig_pri) 6187 synqf |= IXGBE_SYN_FILTER_SYNQFP; 6188 else 6189 synqf &= ~IXGBE_SYN_FILTER_SYNQFP; 6190 } else { 6191 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6192 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE)) 6193 return -ENOENT; 6194 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE); 6195 } 6196 6197 filter_info->syn_info = synqf; 6198 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 6199 IXGBE_WRITE_FLUSH(hw); 6200 return 0; 6201 } 6202 6203 6204 static inline enum ixgbe_5tuple_protocol 6205 convert_protocol_type(uint8_t protocol_value) 6206 { 6207 if (protocol_value == IPPROTO_TCP) 6208 return IXGBE_FILTER_PROTOCOL_TCP; 6209 else if (protocol_value == IPPROTO_UDP) 6210 return IXGBE_FILTER_PROTOCOL_UDP; 6211 else if (protocol_value == IPPROTO_SCTP) 6212 return IXGBE_FILTER_PROTOCOL_SCTP; 6213 else 6214 return IXGBE_FILTER_PROTOCOL_NONE; 6215 } 6216 6217 /* inject a 5-tuple filter to HW */ 6218 static inline void 6219 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev, 6220 struct ixgbe_5tuple_filter *filter) 6221 { 6222 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6223 int i; 6224 uint32_t ftqf, sdpqf; 6225 uint32_t l34timir = 0; 6226 uint8_t mask = 0xff; 6227 6228 i = filter->index; 6229 6230 sdpqf = (uint32_t)(filter->filter_info.dst_port << 6231 IXGBE_SDPQF_DSTPORT_SHIFT); 6232 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT); 6233 6234 ftqf = (uint32_t)(filter->filter_info.proto & 6235 IXGBE_FTQF_PROTOCOL_MASK); 6236 ftqf |= (uint32_t)((filter->filter_info.priority & 6237 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT); 6238 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */ 6239 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK; 6240 if (filter->filter_info.dst_ip_mask == 0) 6241 mask &= IXGBE_FTQF_DEST_ADDR_MASK; 6242 if (filter->filter_info.src_port_mask == 0) 6243 mask &= IXGBE_FTQF_SOURCE_PORT_MASK; 6244 if (filter->filter_info.dst_port_mask == 0) 6245 mask &= IXGBE_FTQF_DEST_PORT_MASK; 6246 if (filter->filter_info.proto_mask == 0) 6247 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK; 6248 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT; 6249 ftqf |= IXGBE_FTQF_POOL_MASK_EN; 6250 ftqf |= IXGBE_FTQF_QUEUE_ENABLE; 6251 6252 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip); 6253 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip); 6254 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf); 6255 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf); 6256 6257 l34timir |= IXGBE_L34T_IMIR_RESERVE; 6258 l34timir |= (uint32_t)(filter->queue << 6259 IXGBE_L34T_IMIR_QUEUE_SHIFT); 6260 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir); 6261 } 6262 6263 /* 6264 * add a 5tuple filter 6265 * 6266 * @param 6267 * dev: Pointer to struct rte_eth_dev. 6268 * index: the index the filter allocates. 6269 * filter: pointer to the filter that will be added. 6270 * rx_queue: the queue id the filter assigned to. 6271 * 6272 * @return 6273 * - On success, zero. 6274 * - On failure, a negative value. 6275 */ 6276 static int 6277 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 6278 struct ixgbe_5tuple_filter *filter) 6279 { 6280 struct ixgbe_filter_info *filter_info = 6281 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6282 int i, idx, shift; 6283 6284 /* 6285 * look for an unused 5tuple filter index, 6286 * and insert the filter to list. 6287 */ 6288 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) { 6289 idx = i / (sizeof(uint32_t) * NBBY); 6290 shift = i % (sizeof(uint32_t) * NBBY); 6291 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) { 6292 filter_info->fivetuple_mask[idx] |= 1 << shift; 6293 filter->index = i; 6294 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list, 6295 filter, 6296 entries); 6297 break; 6298 } 6299 } 6300 if (i >= IXGBE_MAX_FTQF_FILTERS) { 6301 PMD_DRV_LOG(ERR, "5tuple filters are full."); 6302 return -ENOSYS; 6303 } 6304 6305 ixgbe_inject_5tuple_filter(dev, filter); 6306 6307 return 0; 6308 } 6309 6310 /* 6311 * remove a 5tuple filter 6312 * 6313 * @param 6314 * dev: Pointer to struct rte_eth_dev. 6315 * filter: the pointer of the filter will be removed. 6316 */ 6317 static void 6318 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 6319 struct ixgbe_5tuple_filter *filter) 6320 { 6321 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6322 struct ixgbe_filter_info *filter_info = 6323 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6324 uint16_t index = filter->index; 6325 6326 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &= 6327 ~(1 << (index % (sizeof(uint32_t) * NBBY))); 6328 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries); 6329 rte_free(filter); 6330 6331 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0); 6332 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0); 6333 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0); 6334 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0); 6335 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0); 6336 } 6337 6338 static int 6339 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 6340 { 6341 struct ixgbe_hw *hw; 6342 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD; 6343 struct rte_eth_dev_data *dev_data = dev->data; 6344 6345 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6346 6347 if (mtu < RTE_ETHER_MIN_MTU || max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN) 6348 return -EINVAL; 6349 6350 /* If device is started, refuse mtu that requires the support of 6351 * scattered packets when this feature has not been enabled before. 6352 */ 6353 if (dev_data->dev_started && !dev_data->scattered_rx && 6354 (max_frame + 2 * RTE_VLAN_HLEN > 6355 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 6356 PMD_INIT_LOG(ERR, "Stop port first."); 6357 return -EINVAL; 6358 } 6359 6360 /* 6361 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU 6362 * request of the version 2.0 of the mailbox API. 6363 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0 6364 * of the mailbox API. 6365 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers 6366 * prior to 3.11.33 which contains the following change: 6367 * "ixgbe: Enable jumbo frames support w/ SR-IOV" 6368 */ 6369 if (ixgbevf_rlpml_set_vf(hw, max_frame)) 6370 return -EINVAL; 6371 6372 return 0; 6373 } 6374 6375 static inline struct ixgbe_5tuple_filter * 6376 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list, 6377 struct ixgbe_5tuple_filter_info *key) 6378 { 6379 struct ixgbe_5tuple_filter *it; 6380 6381 TAILQ_FOREACH(it, filter_list, entries) { 6382 if (memcmp(key, &it->filter_info, 6383 sizeof(struct ixgbe_5tuple_filter_info)) == 0) { 6384 return it; 6385 } 6386 } 6387 return NULL; 6388 } 6389 6390 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/ 6391 static inline int 6392 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter, 6393 struct ixgbe_5tuple_filter_info *filter_info) 6394 { 6395 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM || 6396 filter->priority > IXGBE_5TUPLE_MAX_PRI || 6397 filter->priority < IXGBE_5TUPLE_MIN_PRI) 6398 return -EINVAL; 6399 6400 switch (filter->dst_ip_mask) { 6401 case UINT32_MAX: 6402 filter_info->dst_ip_mask = 0; 6403 filter_info->dst_ip = filter->dst_ip; 6404 break; 6405 case 0: 6406 filter_info->dst_ip_mask = 1; 6407 break; 6408 default: 6409 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 6410 return -EINVAL; 6411 } 6412 6413 switch (filter->src_ip_mask) { 6414 case UINT32_MAX: 6415 filter_info->src_ip_mask = 0; 6416 filter_info->src_ip = filter->src_ip; 6417 break; 6418 case 0: 6419 filter_info->src_ip_mask = 1; 6420 break; 6421 default: 6422 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 6423 return -EINVAL; 6424 } 6425 6426 switch (filter->dst_port_mask) { 6427 case UINT16_MAX: 6428 filter_info->dst_port_mask = 0; 6429 filter_info->dst_port = filter->dst_port; 6430 break; 6431 case 0: 6432 filter_info->dst_port_mask = 1; 6433 break; 6434 default: 6435 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 6436 return -EINVAL; 6437 } 6438 6439 switch (filter->src_port_mask) { 6440 case UINT16_MAX: 6441 filter_info->src_port_mask = 0; 6442 filter_info->src_port = filter->src_port; 6443 break; 6444 case 0: 6445 filter_info->src_port_mask = 1; 6446 break; 6447 default: 6448 PMD_DRV_LOG(ERR, "invalid src_port mask."); 6449 return -EINVAL; 6450 } 6451 6452 switch (filter->proto_mask) { 6453 case UINT8_MAX: 6454 filter_info->proto_mask = 0; 6455 filter_info->proto = 6456 convert_protocol_type(filter->proto); 6457 break; 6458 case 0: 6459 filter_info->proto_mask = 1; 6460 break; 6461 default: 6462 PMD_DRV_LOG(ERR, "invalid protocol mask."); 6463 return -EINVAL; 6464 } 6465 6466 filter_info->priority = (uint8_t)filter->priority; 6467 return 0; 6468 } 6469 6470 /* 6471 * add or delete a ntuple filter 6472 * 6473 * @param 6474 * dev: Pointer to struct rte_eth_dev. 6475 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6476 * add: if true, add filter, if false, remove filter 6477 * 6478 * @return 6479 * - On success, zero. 6480 * - On failure, a negative value. 6481 */ 6482 int 6483 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 6484 struct rte_eth_ntuple_filter *ntuple_filter, 6485 bool add) 6486 { 6487 struct ixgbe_filter_info *filter_info = 6488 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6489 struct ixgbe_5tuple_filter_info filter_5tuple; 6490 struct ixgbe_5tuple_filter *filter; 6491 int ret; 6492 6493 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6494 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6495 return -EINVAL; 6496 } 6497 6498 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6499 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6500 if (ret < 0) 6501 return ret; 6502 6503 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6504 &filter_5tuple); 6505 if (filter != NULL && add) { 6506 PMD_DRV_LOG(ERR, "filter exists."); 6507 return -EEXIST; 6508 } 6509 if (filter == NULL && !add) { 6510 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6511 return -ENOENT; 6512 } 6513 6514 if (add) { 6515 filter = rte_zmalloc("ixgbe_5tuple_filter", 6516 sizeof(struct ixgbe_5tuple_filter), 0); 6517 if (filter == NULL) 6518 return -ENOMEM; 6519 rte_memcpy(&filter->filter_info, 6520 &filter_5tuple, 6521 sizeof(struct ixgbe_5tuple_filter_info)); 6522 filter->queue = ntuple_filter->queue; 6523 ret = ixgbe_add_5tuple_filter(dev, filter); 6524 if (ret < 0) { 6525 rte_free(filter); 6526 return ret; 6527 } 6528 } else 6529 ixgbe_remove_5tuple_filter(dev, filter); 6530 6531 return 0; 6532 } 6533 6534 int 6535 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 6536 struct rte_eth_ethertype_filter *filter, 6537 bool add) 6538 { 6539 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6540 struct ixgbe_filter_info *filter_info = 6541 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6542 uint32_t etqf = 0; 6543 uint32_t etqs = 0; 6544 int ret; 6545 struct ixgbe_ethertype_filter ethertype_filter; 6546 6547 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6548 return -EINVAL; 6549 6550 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 || 6551 filter->ether_type == RTE_ETHER_TYPE_IPV6) { 6552 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in" 6553 " ethertype filter.", filter->ether_type); 6554 return -EINVAL; 6555 } 6556 6557 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) { 6558 PMD_DRV_LOG(ERR, "mac compare is unsupported."); 6559 return -EINVAL; 6560 } 6561 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) { 6562 PMD_DRV_LOG(ERR, "drop option is unsupported."); 6563 return -EINVAL; 6564 } 6565 6566 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6567 if (ret >= 0 && add) { 6568 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.", 6569 filter->ether_type); 6570 return -EEXIST; 6571 } 6572 if (ret < 0 && !add) { 6573 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6574 filter->ether_type); 6575 return -ENOENT; 6576 } 6577 6578 if (add) { 6579 etqf = IXGBE_ETQF_FILTER_EN; 6580 etqf |= (uint32_t)filter->ether_type; 6581 etqs |= (uint32_t)((filter->queue << 6582 IXGBE_ETQS_RX_QUEUE_SHIFT) & 6583 IXGBE_ETQS_RX_QUEUE); 6584 etqs |= IXGBE_ETQS_QUEUE_EN; 6585 6586 ethertype_filter.ethertype = filter->ether_type; 6587 ethertype_filter.etqf = etqf; 6588 ethertype_filter.etqs = etqs; 6589 ethertype_filter.conf = FALSE; 6590 ret = ixgbe_ethertype_filter_insert(filter_info, 6591 ðertype_filter); 6592 if (ret < 0) { 6593 PMD_DRV_LOG(ERR, "ethertype filters are full."); 6594 return -ENOSPC; 6595 } 6596 } else { 6597 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret); 6598 if (ret < 0) 6599 return -ENOSYS; 6600 } 6601 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf); 6602 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs); 6603 IXGBE_WRITE_FLUSH(hw); 6604 6605 return 0; 6606 } 6607 6608 static int 6609 ixgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev, 6610 const struct rte_flow_ops **ops) 6611 { 6612 *ops = &ixgbe_flow_ops; 6613 return 0; 6614 } 6615 6616 static u8 * 6617 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw, 6618 u8 **mc_addr_ptr, u32 *vmdq) 6619 { 6620 u8 *mc_addr; 6621 6622 *vmdq = 0; 6623 mc_addr = *mc_addr_ptr; 6624 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr)); 6625 return mc_addr; 6626 } 6627 6628 static int 6629 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 6630 struct rte_ether_addr *mc_addr_set, 6631 uint32_t nb_mc_addr) 6632 { 6633 struct ixgbe_hw *hw; 6634 u8 *mc_addr_list; 6635 6636 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6637 mc_addr_list = (u8 *)mc_addr_set; 6638 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr, 6639 ixgbe_dev_addr_list_itr, TRUE); 6640 } 6641 6642 static uint64_t 6643 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev) 6644 { 6645 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6646 uint64_t systime_cycles; 6647 6648 switch (hw->mac.type) { 6649 case ixgbe_mac_X550: 6650 case ixgbe_mac_X550EM_x: 6651 case ixgbe_mac_X550EM_a: 6652 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */ 6653 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 6654 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 6655 * NSEC_PER_SEC; 6656 break; 6657 default: 6658 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 6659 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 6660 << 32; 6661 } 6662 6663 return systime_cycles; 6664 } 6665 6666 static uint64_t 6667 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) 6668 { 6669 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6670 uint64_t rx_tstamp_cycles; 6671 6672 switch (hw->mac.type) { 6673 case ixgbe_mac_X550: 6674 case ixgbe_mac_X550EM_x: 6675 case ixgbe_mac_X550EM_a: 6676 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 6677 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 6678 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 6679 * NSEC_PER_SEC; 6680 break; 6681 default: 6682 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 6683 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 6684 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 6685 << 32; 6686 } 6687 6688 return rx_tstamp_cycles; 6689 } 6690 6691 static uint64_t 6692 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 6693 { 6694 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6695 uint64_t tx_tstamp_cycles; 6696 6697 switch (hw->mac.type) { 6698 case ixgbe_mac_X550: 6699 case ixgbe_mac_X550EM_x: 6700 case ixgbe_mac_X550EM_a: 6701 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 6702 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 6703 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 6704 * NSEC_PER_SEC; 6705 break; 6706 default: 6707 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 6708 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 6709 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 6710 << 32; 6711 } 6712 6713 return tx_tstamp_cycles; 6714 } 6715 6716 static void 6717 ixgbe_start_timecounters(struct rte_eth_dev *dev) 6718 { 6719 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6720 struct ixgbe_adapter *adapter = dev->data->dev_private; 6721 struct rte_eth_link link; 6722 uint32_t incval = 0; 6723 uint32_t shift = 0; 6724 6725 /* Get current link speed. */ 6726 ixgbe_dev_link_update(dev, 1); 6727 rte_eth_linkstatus_get(dev, &link); 6728 6729 switch (link.link_speed) { 6730 case RTE_ETH_SPEED_NUM_100M: 6731 incval = IXGBE_INCVAL_100; 6732 shift = IXGBE_INCVAL_SHIFT_100; 6733 break; 6734 case RTE_ETH_SPEED_NUM_1G: 6735 incval = IXGBE_INCVAL_1GB; 6736 shift = IXGBE_INCVAL_SHIFT_1GB; 6737 break; 6738 case RTE_ETH_SPEED_NUM_10G: 6739 default: 6740 incval = IXGBE_INCVAL_10GB; 6741 shift = IXGBE_INCVAL_SHIFT_10GB; 6742 break; 6743 } 6744 6745 switch (hw->mac.type) { 6746 case ixgbe_mac_X550: 6747 case ixgbe_mac_X550EM_x: 6748 case ixgbe_mac_X550EM_a: 6749 /* Independent of link speed. */ 6750 incval = 1; 6751 /* Cycles read will be interpreted as ns. */ 6752 shift = 0; 6753 /* Fall-through */ 6754 case ixgbe_mac_X540: 6755 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval); 6756 break; 6757 case ixgbe_mac_82599EB: 6758 incval >>= IXGBE_INCVAL_SHIFT_82599; 6759 shift -= IXGBE_INCVAL_SHIFT_82599; 6760 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 6761 (1 << IXGBE_INCPER_SHIFT_82599) | incval); 6762 break; 6763 default: 6764 /* Not supported. */ 6765 return; 6766 } 6767 6768 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 6769 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 6770 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 6771 6772 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6773 adapter->systime_tc.cc_shift = shift; 6774 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; 6775 6776 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6777 adapter->rx_tstamp_tc.cc_shift = shift; 6778 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 6779 6780 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6781 adapter->tx_tstamp_tc.cc_shift = shift; 6782 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 6783 } 6784 6785 static int 6786 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 6787 { 6788 struct ixgbe_adapter *adapter = dev->data->dev_private; 6789 6790 adapter->systime_tc.nsec += delta; 6791 adapter->rx_tstamp_tc.nsec += delta; 6792 adapter->tx_tstamp_tc.nsec += delta; 6793 6794 return 0; 6795 } 6796 6797 static int 6798 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 6799 { 6800 uint64_t ns; 6801 struct ixgbe_adapter *adapter = dev->data->dev_private; 6802 6803 ns = rte_timespec_to_ns(ts); 6804 /* Set the timecounters to a new value. */ 6805 adapter->systime_tc.nsec = ns; 6806 adapter->rx_tstamp_tc.nsec = ns; 6807 adapter->tx_tstamp_tc.nsec = ns; 6808 6809 return 0; 6810 } 6811 6812 static int 6813 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 6814 { 6815 uint64_t ns, systime_cycles; 6816 struct ixgbe_adapter *adapter = dev->data->dev_private; 6817 6818 systime_cycles = ixgbe_read_systime_cyclecounter(dev); 6819 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 6820 *ts = rte_ns_to_timespec(ns); 6821 6822 return 0; 6823 } 6824 6825 static int 6826 ixgbe_timesync_enable(struct rte_eth_dev *dev) 6827 { 6828 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6829 uint32_t tsync_ctl; 6830 uint32_t tsauxc; 6831 6832 /* Stop the timesync system time. */ 6833 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0); 6834 /* Reset the timesync system time value. */ 6835 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0); 6836 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0); 6837 6838 /* Enable system time for platforms where it isn't on by default. */ 6839 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC); 6840 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME; 6841 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc); 6842 6843 ixgbe_start_timecounters(dev); 6844 6845 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 6846 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 6847 (RTE_ETHER_TYPE_1588 | 6848 IXGBE_ETQF_FILTER_EN | 6849 IXGBE_ETQF_1588)); 6850 6851 /* Enable timestamping of received PTP packets. */ 6852 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 6853 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED; 6854 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 6855 6856 /* Enable timestamping of transmitted PTP packets. */ 6857 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 6858 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED; 6859 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 6860 6861 IXGBE_WRITE_FLUSH(hw); 6862 6863 return 0; 6864 } 6865 6866 static int 6867 ixgbe_timesync_disable(struct rte_eth_dev *dev) 6868 { 6869 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6870 uint32_t tsync_ctl; 6871 6872 /* Disable timestamping of transmitted PTP packets. */ 6873 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 6874 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED; 6875 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 6876 6877 /* Disable timestamping of received PTP packets. */ 6878 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 6879 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED; 6880 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 6881 6882 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 6883 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0); 6884 6885 /* Stop incrementing the System Time registers. */ 6886 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0); 6887 6888 return 0; 6889 } 6890 6891 static int 6892 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 6893 struct timespec *timestamp, 6894 uint32_t flags __rte_unused) 6895 { 6896 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6897 struct ixgbe_adapter *adapter = dev->data->dev_private; 6898 uint32_t tsync_rxctl; 6899 uint64_t rx_tstamp_cycles; 6900 uint64_t ns; 6901 6902 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 6903 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0) 6904 return -EINVAL; 6905 6906 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev); 6907 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 6908 *timestamp = rte_ns_to_timespec(ns); 6909 6910 return 0; 6911 } 6912 6913 static int 6914 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 6915 struct timespec *timestamp) 6916 { 6917 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6918 struct ixgbe_adapter *adapter = dev->data->dev_private; 6919 uint32_t tsync_txctl; 6920 uint64_t tx_tstamp_cycles; 6921 uint64_t ns; 6922 6923 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 6924 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0) 6925 return -EINVAL; 6926 6927 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev); 6928 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 6929 *timestamp = rte_ns_to_timespec(ns); 6930 6931 return 0; 6932 } 6933 6934 static int 6935 ixgbe_get_reg_length(struct rte_eth_dev *dev) 6936 { 6937 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6938 int count = 0; 6939 int g_ind = 0; 6940 const struct reg_info *reg_group; 6941 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 6942 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 6943 6944 while ((reg_group = reg_set[g_ind++])) 6945 count += ixgbe_regs_group_count(reg_group); 6946 6947 return count; 6948 } 6949 6950 static int 6951 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused) 6952 { 6953 int count = 0; 6954 int g_ind = 0; 6955 const struct reg_info *reg_group; 6956 6957 while ((reg_group = ixgbevf_regs[g_ind++])) 6958 count += ixgbe_regs_group_count(reg_group); 6959 6960 return count; 6961 } 6962 6963 static int 6964 ixgbe_get_regs(struct rte_eth_dev *dev, 6965 struct rte_dev_reg_info *regs) 6966 { 6967 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6968 uint32_t *data = regs->data; 6969 int g_ind = 0; 6970 int count = 0; 6971 const struct reg_info *reg_group; 6972 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 6973 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 6974 6975 if (data == NULL) { 6976 regs->length = ixgbe_get_reg_length(dev); 6977 regs->width = sizeof(uint32_t); 6978 return 0; 6979 } 6980 6981 /* Support only full register dump */ 6982 if ((regs->length == 0) || 6983 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) { 6984 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 6985 hw->device_id; 6986 while ((reg_group = reg_set[g_ind++])) 6987 count += ixgbe_read_regs_group(dev, &data[count], 6988 reg_group); 6989 return 0; 6990 } 6991 6992 return -ENOTSUP; 6993 } 6994 6995 static int 6996 ixgbevf_get_regs(struct rte_eth_dev *dev, 6997 struct rte_dev_reg_info *regs) 6998 { 6999 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7000 uint32_t *data = regs->data; 7001 int g_ind = 0; 7002 int count = 0; 7003 const struct reg_info *reg_group; 7004 7005 if (data == NULL) { 7006 regs->length = ixgbevf_get_reg_length(dev); 7007 regs->width = sizeof(uint32_t); 7008 return 0; 7009 } 7010 7011 /* Support only full register dump */ 7012 if ((regs->length == 0) || 7013 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) { 7014 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7015 hw->device_id; 7016 while ((reg_group = ixgbevf_regs[g_ind++])) 7017 count += ixgbe_read_regs_group(dev, &data[count], 7018 reg_group); 7019 return 0; 7020 } 7021 7022 return -ENOTSUP; 7023 } 7024 7025 static int 7026 ixgbe_get_eeprom_length(struct rte_eth_dev *dev) 7027 { 7028 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7029 7030 /* Return unit is byte count */ 7031 return hw->eeprom.word_size * 2; 7032 } 7033 7034 static int 7035 ixgbe_get_eeprom(struct rte_eth_dev *dev, 7036 struct rte_dev_eeprom_info *in_eeprom) 7037 { 7038 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7039 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7040 uint16_t *data = in_eeprom->data; 7041 int first, length; 7042 7043 first = in_eeprom->offset >> 1; 7044 length = in_eeprom->length >> 1; 7045 if ((first > hw->eeprom.word_size) || 7046 ((first + length) > hw->eeprom.word_size)) 7047 return -EINVAL; 7048 7049 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7050 7051 return eeprom->ops.read_buffer(hw, first, length, data); 7052 } 7053 7054 static int 7055 ixgbe_set_eeprom(struct rte_eth_dev *dev, 7056 struct rte_dev_eeprom_info *in_eeprom) 7057 { 7058 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7059 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7060 uint16_t *data = in_eeprom->data; 7061 int first, length; 7062 7063 first = in_eeprom->offset >> 1; 7064 length = in_eeprom->length >> 1; 7065 if ((first > hw->eeprom.word_size) || 7066 ((first + length) > hw->eeprom.word_size)) 7067 return -EINVAL; 7068 7069 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7070 7071 return eeprom->ops.write_buffer(hw, first, length, data); 7072 } 7073 7074 static int 7075 ixgbe_get_module_info(struct rte_eth_dev *dev, 7076 struct rte_eth_dev_module_info *modinfo) 7077 { 7078 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7079 uint32_t status; 7080 uint8_t sff8472_rev, addr_mode; 7081 bool page_swap = false; 7082 7083 /* Check whether we support SFF-8472 or not */ 7084 status = hw->phy.ops.read_i2c_eeprom(hw, 7085 IXGBE_SFF_SFF_8472_COMP, 7086 &sff8472_rev); 7087 if (status != 0) 7088 return -EIO; 7089 7090 /* addressing mode is not supported */ 7091 status = hw->phy.ops.read_i2c_eeprom(hw, 7092 IXGBE_SFF_SFF_8472_SWAP, 7093 &addr_mode); 7094 if (status != 0) 7095 return -EIO; 7096 7097 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 7098 PMD_DRV_LOG(ERR, 7099 "Address change required to access page 0xA2, " 7100 "but not supported. Please report the module " 7101 "type to the driver maintainers."); 7102 page_swap = true; 7103 } 7104 7105 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) { 7106 /* We have a SFP, but it does not support SFF-8472 */ 7107 modinfo->type = RTE_ETH_MODULE_SFF_8079; 7108 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 7109 } else { 7110 /* We have a SFP which supports a revision of SFF-8472. */ 7111 modinfo->type = RTE_ETH_MODULE_SFF_8472; 7112 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 7113 } 7114 7115 return 0; 7116 } 7117 7118 static int 7119 ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 7120 struct rte_dev_eeprom_info *info) 7121 { 7122 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7123 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 7124 uint8_t databyte = 0xFF; 7125 uint8_t *data = info->data; 7126 uint32_t i = 0; 7127 7128 for (i = info->offset; i < info->offset + info->length; i++) { 7129 if (i < RTE_ETH_MODULE_SFF_8079_LEN) 7130 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 7131 else 7132 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 7133 7134 if (status != 0) 7135 return -EIO; 7136 7137 data[i - info->offset] = databyte; 7138 } 7139 7140 return 0; 7141 } 7142 7143 uint16_t 7144 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) { 7145 switch (mac_type) { 7146 case ixgbe_mac_X550: 7147 case ixgbe_mac_X550EM_x: 7148 case ixgbe_mac_X550EM_a: 7149 return RTE_ETH_RSS_RETA_SIZE_512; 7150 case ixgbe_mac_X550_vf: 7151 case ixgbe_mac_X550EM_x_vf: 7152 case ixgbe_mac_X550EM_a_vf: 7153 return RTE_ETH_RSS_RETA_SIZE_64; 7154 case ixgbe_mac_X540_vf: 7155 case ixgbe_mac_82599_vf: 7156 return 0; 7157 default: 7158 return RTE_ETH_RSS_RETA_SIZE_128; 7159 } 7160 } 7161 7162 uint32_t 7163 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) { 7164 switch (mac_type) { 7165 case ixgbe_mac_X550: 7166 case ixgbe_mac_X550EM_x: 7167 case ixgbe_mac_X550EM_a: 7168 if (reta_idx < RTE_ETH_RSS_RETA_SIZE_128) 7169 return IXGBE_RETA(reta_idx >> 2); 7170 else 7171 return IXGBE_ERETA((reta_idx - RTE_ETH_RSS_RETA_SIZE_128) >> 2); 7172 case ixgbe_mac_X550_vf: 7173 case ixgbe_mac_X550EM_x_vf: 7174 case ixgbe_mac_X550EM_a_vf: 7175 return IXGBE_VFRETA(reta_idx >> 2); 7176 default: 7177 return IXGBE_RETA(reta_idx >> 2); 7178 } 7179 } 7180 7181 uint32_t 7182 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) { 7183 switch (mac_type) { 7184 case ixgbe_mac_X550_vf: 7185 case ixgbe_mac_X550EM_x_vf: 7186 case ixgbe_mac_X550EM_a_vf: 7187 return IXGBE_VFMRQC; 7188 default: 7189 return IXGBE_MRQC; 7190 } 7191 } 7192 7193 uint32_t 7194 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) { 7195 switch (mac_type) { 7196 case ixgbe_mac_X550_vf: 7197 case ixgbe_mac_X550EM_x_vf: 7198 case ixgbe_mac_X550EM_a_vf: 7199 return IXGBE_VFRSSRK(i); 7200 default: 7201 return IXGBE_RSSRK(i); 7202 } 7203 } 7204 7205 bool 7206 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) { 7207 switch (mac_type) { 7208 case ixgbe_mac_82599_vf: 7209 case ixgbe_mac_X540_vf: 7210 return 0; 7211 default: 7212 return 1; 7213 } 7214 } 7215 7216 static int 7217 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 7218 struct rte_eth_dcb_info *dcb_info) 7219 { 7220 struct ixgbe_dcb_config *dcb_config = 7221 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 7222 struct ixgbe_dcb_tc_config *tc; 7223 struct rte_eth_dcb_tc_queue_mapping *tc_queue; 7224 uint8_t nb_tcs; 7225 uint8_t i, j; 7226 7227 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) 7228 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs; 7229 else 7230 dcb_info->nb_tcs = 1; 7231 7232 tc_queue = &dcb_info->tc_queue; 7233 nb_tcs = dcb_info->nb_tcs; 7234 7235 if (dcb_config->vt_mode) { /* vt is enabled*/ 7236 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf = 7237 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf; 7238 for (i = 0; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++) 7239 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i]; 7240 if (RTE_ETH_DEV_SRIOV(dev).active > 0) { 7241 for (j = 0; j < nb_tcs; j++) { 7242 tc_queue->tc_rxq[0][j].base = j; 7243 tc_queue->tc_rxq[0][j].nb_queue = 1; 7244 tc_queue->tc_txq[0][j].base = j; 7245 tc_queue->tc_txq[0][j].nb_queue = 1; 7246 } 7247 } else { 7248 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) { 7249 for (j = 0; j < nb_tcs; j++) { 7250 tc_queue->tc_rxq[i][j].base = 7251 i * nb_tcs + j; 7252 tc_queue->tc_rxq[i][j].nb_queue = 1; 7253 tc_queue->tc_txq[i][j].base = 7254 i * nb_tcs + j; 7255 tc_queue->tc_txq[i][j].nb_queue = 1; 7256 } 7257 } 7258 } 7259 } else { /* vt is disabled*/ 7260 struct rte_eth_dcb_rx_conf *rx_conf = 7261 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 7262 for (i = 0; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++) 7263 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i]; 7264 if (dcb_info->nb_tcs == RTE_ETH_4_TCS) { 7265 for (i = 0; i < dcb_info->nb_tcs; i++) { 7266 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32; 7267 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7268 } 7269 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7270 dcb_info->tc_queue.tc_txq[0][1].base = 64; 7271 dcb_info->tc_queue.tc_txq[0][2].base = 96; 7272 dcb_info->tc_queue.tc_txq[0][3].base = 112; 7273 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64; 7274 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7275 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7276 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7277 } else if (dcb_info->nb_tcs == RTE_ETH_8_TCS) { 7278 for (i = 0; i < dcb_info->nb_tcs; i++) { 7279 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16; 7280 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7281 } 7282 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7283 dcb_info->tc_queue.tc_txq[0][1].base = 32; 7284 dcb_info->tc_queue.tc_txq[0][2].base = 64; 7285 dcb_info->tc_queue.tc_txq[0][3].base = 80; 7286 dcb_info->tc_queue.tc_txq[0][4].base = 96; 7287 dcb_info->tc_queue.tc_txq[0][5].base = 104; 7288 dcb_info->tc_queue.tc_txq[0][6].base = 112; 7289 dcb_info->tc_queue.tc_txq[0][7].base = 120; 7290 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32; 7291 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7292 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7293 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7294 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8; 7295 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8; 7296 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8; 7297 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8; 7298 } 7299 } 7300 for (i = 0; i < dcb_info->nb_tcs; i++) { 7301 tc = &dcb_config->tc_config[i]; 7302 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent; 7303 } 7304 return 0; 7305 } 7306 7307 /* Update e-tag ether type */ 7308 static int 7309 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw, 7310 uint16_t ether_type) 7311 { 7312 uint32_t etag_etype; 7313 7314 if (hw->mac.type != ixgbe_mac_X550 && 7315 hw->mac.type != ixgbe_mac_X550EM_x && 7316 hw->mac.type != ixgbe_mac_X550EM_a) { 7317 return -ENOTSUP; 7318 } 7319 7320 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7321 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK; 7322 etag_etype |= ether_type; 7323 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7324 IXGBE_WRITE_FLUSH(hw); 7325 7326 return 0; 7327 } 7328 7329 /* Enable e-tag tunnel */ 7330 static int 7331 ixgbe_e_tag_enable(struct ixgbe_hw *hw) 7332 { 7333 uint32_t etag_etype; 7334 7335 if (hw->mac.type != ixgbe_mac_X550 && 7336 hw->mac.type != ixgbe_mac_X550EM_x && 7337 hw->mac.type != ixgbe_mac_X550EM_a) { 7338 return -ENOTSUP; 7339 } 7340 7341 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7342 etag_etype |= IXGBE_ETAG_ETYPE_VALID; 7343 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7344 IXGBE_WRITE_FLUSH(hw); 7345 7346 return 0; 7347 } 7348 7349 static int 7350 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev, 7351 struct ixgbe_l2_tunnel_conf *l2_tunnel) 7352 { 7353 int ret = 0; 7354 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7355 uint32_t i, rar_entries; 7356 uint32_t rar_low, rar_high; 7357 7358 if (hw->mac.type != ixgbe_mac_X550 && 7359 hw->mac.type != ixgbe_mac_X550EM_x && 7360 hw->mac.type != ixgbe_mac_X550EM_a) { 7361 return -ENOTSUP; 7362 } 7363 7364 rar_entries = ixgbe_get_num_rx_addrs(hw); 7365 7366 for (i = 1; i < rar_entries; i++) { 7367 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7368 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 7369 if ((rar_high & IXGBE_RAH_AV) && 7370 (rar_high & IXGBE_RAH_ADTYPE) && 7371 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) == 7372 l2_tunnel->tunnel_id)) { 7373 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 7374 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 7375 7376 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL); 7377 7378 return ret; 7379 } 7380 } 7381 7382 return ret; 7383 } 7384 7385 static int 7386 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev, 7387 struct ixgbe_l2_tunnel_conf *l2_tunnel) 7388 { 7389 int ret = 0; 7390 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7391 uint32_t i, rar_entries; 7392 uint32_t rar_low, rar_high; 7393 7394 if (hw->mac.type != ixgbe_mac_X550 && 7395 hw->mac.type != ixgbe_mac_X550EM_x && 7396 hw->mac.type != ixgbe_mac_X550EM_a) { 7397 return -ENOTSUP; 7398 } 7399 7400 /* One entry for one tunnel. Try to remove potential existing entry. */ 7401 ixgbe_e_tag_filter_del(dev, l2_tunnel); 7402 7403 rar_entries = ixgbe_get_num_rx_addrs(hw); 7404 7405 for (i = 1; i < rar_entries; i++) { 7406 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7407 if (rar_high & IXGBE_RAH_AV) { 7408 continue; 7409 } else { 7410 ixgbe_set_vmdq(hw, i, l2_tunnel->pool); 7411 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE; 7412 rar_low = l2_tunnel->tunnel_id; 7413 7414 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low); 7415 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high); 7416 7417 return ret; 7418 } 7419 } 7420 7421 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full." 7422 " Please remove a rule before adding a new one."); 7423 return -EINVAL; 7424 } 7425 7426 static inline struct ixgbe_l2_tn_filter * 7427 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info, 7428 struct ixgbe_l2_tn_key *key) 7429 { 7430 int ret; 7431 7432 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key); 7433 if (ret < 0) 7434 return NULL; 7435 7436 return l2_tn_info->hash_map[ret]; 7437 } 7438 7439 static inline int 7440 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7441 struct ixgbe_l2_tn_filter *l2_tn_filter) 7442 { 7443 int ret; 7444 7445 ret = rte_hash_add_key(l2_tn_info->hash_handle, 7446 &l2_tn_filter->key); 7447 7448 if (ret < 0) { 7449 PMD_DRV_LOG(ERR, 7450 "Failed to insert L2 tunnel filter" 7451 " to hash table %d!", 7452 ret); 7453 return ret; 7454 } 7455 7456 l2_tn_info->hash_map[ret] = l2_tn_filter; 7457 7458 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 7459 7460 return 0; 7461 } 7462 7463 static inline int 7464 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7465 struct ixgbe_l2_tn_key *key) 7466 { 7467 int ret; 7468 struct ixgbe_l2_tn_filter *l2_tn_filter; 7469 7470 ret = rte_hash_del_key(l2_tn_info->hash_handle, key); 7471 7472 if (ret < 0) { 7473 PMD_DRV_LOG(ERR, 7474 "No such L2 tunnel filter to delete %d!", 7475 ret); 7476 return ret; 7477 } 7478 7479 l2_tn_filter = l2_tn_info->hash_map[ret]; 7480 l2_tn_info->hash_map[ret] = NULL; 7481 7482 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 7483 rte_free(l2_tn_filter); 7484 7485 return 0; 7486 } 7487 7488 /* Add l2 tunnel filter */ 7489 int 7490 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 7491 struct ixgbe_l2_tunnel_conf *l2_tunnel, 7492 bool restore) 7493 { 7494 int ret; 7495 struct ixgbe_l2_tn_info *l2_tn_info = 7496 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7497 struct ixgbe_l2_tn_key key; 7498 struct ixgbe_l2_tn_filter *node; 7499 7500 if (!restore) { 7501 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 7502 key.tn_id = l2_tunnel->tunnel_id; 7503 7504 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key); 7505 7506 if (node) { 7507 PMD_DRV_LOG(ERR, 7508 "The L2 tunnel filter already exists!"); 7509 return -EINVAL; 7510 } 7511 7512 node = rte_zmalloc("ixgbe_l2_tn", 7513 sizeof(struct ixgbe_l2_tn_filter), 7514 0); 7515 if (!node) 7516 return -ENOMEM; 7517 7518 rte_memcpy(&node->key, 7519 &key, 7520 sizeof(struct ixgbe_l2_tn_key)); 7521 node->pool = l2_tunnel->pool; 7522 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node); 7523 if (ret < 0) { 7524 rte_free(node); 7525 return ret; 7526 } 7527 } 7528 7529 switch (l2_tunnel->l2_tunnel_type) { 7530 case RTE_ETH_L2_TUNNEL_TYPE_E_TAG: 7531 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel); 7532 break; 7533 default: 7534 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7535 ret = -EINVAL; 7536 break; 7537 } 7538 7539 if ((!restore) && (ret < 0)) 7540 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 7541 7542 return ret; 7543 } 7544 7545 /* Delete l2 tunnel filter */ 7546 int 7547 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 7548 struct ixgbe_l2_tunnel_conf *l2_tunnel) 7549 { 7550 int ret; 7551 struct ixgbe_l2_tn_info *l2_tn_info = 7552 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7553 struct ixgbe_l2_tn_key key; 7554 7555 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 7556 key.tn_id = l2_tunnel->tunnel_id; 7557 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 7558 if (ret < 0) 7559 return ret; 7560 7561 switch (l2_tunnel->l2_tunnel_type) { 7562 case RTE_ETH_L2_TUNNEL_TYPE_E_TAG: 7563 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel); 7564 break; 7565 default: 7566 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7567 ret = -EINVAL; 7568 break; 7569 } 7570 7571 return ret; 7572 } 7573 7574 static int 7575 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en) 7576 { 7577 int ret = 0; 7578 uint32_t ctrl; 7579 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7580 7581 if (hw->mac.type != ixgbe_mac_X550 && 7582 hw->mac.type != ixgbe_mac_X550EM_x && 7583 hw->mac.type != ixgbe_mac_X550EM_a) { 7584 return -ENOTSUP; 7585 } 7586 7587 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 7588 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 7589 if (en) 7590 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG; 7591 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 7592 7593 return ret; 7594 } 7595 7596 static int 7597 ixgbe_update_vxlan_port(struct ixgbe_hw *hw, 7598 uint16_t port) 7599 { 7600 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port); 7601 IXGBE_WRITE_FLUSH(hw); 7602 7603 return 0; 7604 } 7605 7606 /* There's only one register for VxLAN UDP port. 7607 * So, we cannot add several ports. Will update it. 7608 */ 7609 static int 7610 ixgbe_add_vxlan_port(struct ixgbe_hw *hw, 7611 uint16_t port) 7612 { 7613 if (port == 0) { 7614 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 7615 return -EINVAL; 7616 } 7617 7618 return ixgbe_update_vxlan_port(hw, port); 7619 } 7620 7621 /* We cannot delete the VxLAN port. For there's a register for VxLAN 7622 * UDP port, it must have a value. 7623 * So, will reset it to the original value 0. 7624 */ 7625 static int 7626 ixgbe_del_vxlan_port(struct ixgbe_hw *hw, 7627 uint16_t port) 7628 { 7629 uint16_t cur_port; 7630 7631 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL); 7632 7633 if (cur_port != port) { 7634 PMD_DRV_LOG(ERR, "Port %u does not exist.", port); 7635 return -EINVAL; 7636 } 7637 7638 return ixgbe_update_vxlan_port(hw, 0); 7639 } 7640 7641 /* Add UDP tunneling port */ 7642 static int 7643 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 7644 struct rte_eth_udp_tunnel *udp_tunnel) 7645 { 7646 int ret = 0; 7647 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7648 7649 if (hw->mac.type != ixgbe_mac_X550 && 7650 hw->mac.type != ixgbe_mac_X550EM_x && 7651 hw->mac.type != ixgbe_mac_X550EM_a) { 7652 return -ENOTSUP; 7653 } 7654 7655 if (udp_tunnel == NULL) 7656 return -EINVAL; 7657 7658 switch (udp_tunnel->prot_type) { 7659 case RTE_ETH_TUNNEL_TYPE_VXLAN: 7660 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port); 7661 break; 7662 7663 case RTE_ETH_TUNNEL_TYPE_GENEVE: 7664 case RTE_ETH_TUNNEL_TYPE_TEREDO: 7665 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 7666 ret = -EINVAL; 7667 break; 7668 7669 default: 7670 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7671 ret = -EINVAL; 7672 break; 7673 } 7674 7675 return ret; 7676 } 7677 7678 /* Remove UDP tunneling port */ 7679 static int 7680 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 7681 struct rte_eth_udp_tunnel *udp_tunnel) 7682 { 7683 int ret = 0; 7684 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7685 7686 if (hw->mac.type != ixgbe_mac_X550 && 7687 hw->mac.type != ixgbe_mac_X550EM_x && 7688 hw->mac.type != ixgbe_mac_X550EM_a) { 7689 return -ENOTSUP; 7690 } 7691 7692 if (udp_tunnel == NULL) 7693 return -EINVAL; 7694 7695 switch (udp_tunnel->prot_type) { 7696 case RTE_ETH_TUNNEL_TYPE_VXLAN: 7697 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port); 7698 break; 7699 case RTE_ETH_TUNNEL_TYPE_GENEVE: 7700 case RTE_ETH_TUNNEL_TYPE_TEREDO: 7701 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 7702 ret = -EINVAL; 7703 break; 7704 default: 7705 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7706 ret = -EINVAL; 7707 break; 7708 } 7709 7710 return ret; 7711 } 7712 7713 static int 7714 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev) 7715 { 7716 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7717 int ret; 7718 7719 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) { 7720 case IXGBE_SUCCESS: 7721 ret = 0; 7722 break; 7723 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 7724 ret = -ENOTSUP; 7725 break; 7726 default: 7727 ret = -EAGAIN; 7728 break; 7729 } 7730 7731 return ret; 7732 } 7733 7734 static int 7735 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev) 7736 { 7737 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7738 int ret; 7739 7740 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) { 7741 case IXGBE_SUCCESS: 7742 ret = 0; 7743 break; 7744 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 7745 ret = -ENOTSUP; 7746 break; 7747 default: 7748 ret = -EAGAIN; 7749 break; 7750 } 7751 7752 return ret; 7753 } 7754 7755 static int 7756 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev) 7757 { 7758 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7759 int ret; 7760 int mode = IXGBEVF_XCAST_MODE_ALLMULTI; 7761 7762 switch (hw->mac.ops.update_xcast_mode(hw, mode)) { 7763 case IXGBE_SUCCESS: 7764 ret = 0; 7765 break; 7766 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 7767 ret = -ENOTSUP; 7768 break; 7769 default: 7770 ret = -EAGAIN; 7771 break; 7772 } 7773 7774 return ret; 7775 } 7776 7777 static int 7778 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev) 7779 { 7780 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7781 int ret; 7782 7783 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) { 7784 case IXGBE_SUCCESS: 7785 ret = 0; 7786 break; 7787 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 7788 ret = -ENOTSUP; 7789 break; 7790 default: 7791 ret = -EAGAIN; 7792 break; 7793 } 7794 7795 return ret; 7796 } 7797 7798 static void ixgbevf_mbx_process(struct rte_eth_dev *dev) 7799 { 7800 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7801 u32 in_msg = 0; 7802 7803 /* peek the message first */ 7804 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM); 7805 7806 /* PF reset VF event */ 7807 if (in_msg == IXGBE_PF_CONTROL_MSG) { 7808 /* dummy mbx read to ack pf */ 7809 if (ixgbe_read_mbx(hw, &in_msg, 1, 0)) 7810 return; 7811 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 7812 NULL); 7813 } 7814 } 7815 7816 static int 7817 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev) 7818 { 7819 uint32_t eicr; 7820 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7821 struct ixgbe_interrupt *intr = 7822 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 7823 ixgbevf_intr_disable(dev); 7824 7825 /* read-on-clear nic registers here */ 7826 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR); 7827 intr->flags = 0; 7828 7829 /* only one misc vector supported - mailbox */ 7830 eicr &= IXGBE_VTEICR_MASK; 7831 if (eicr == IXGBE_MISC_VEC_ID) 7832 intr->flags |= IXGBE_FLAG_MAILBOX; 7833 7834 return 0; 7835 } 7836 7837 static int 7838 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev) 7839 { 7840 struct ixgbe_interrupt *intr = 7841 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 7842 7843 if (intr->flags & IXGBE_FLAG_MAILBOX) { 7844 ixgbevf_mbx_process(dev); 7845 intr->flags &= ~IXGBE_FLAG_MAILBOX; 7846 } 7847 7848 ixgbevf_intr_enable(dev); 7849 7850 return 0; 7851 } 7852 7853 static void 7854 ixgbevf_dev_interrupt_handler(void *param) 7855 { 7856 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 7857 7858 ixgbevf_dev_interrupt_get_status(dev); 7859 ixgbevf_dev_interrupt_action(dev); 7860 } 7861 7862 /** 7863 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path 7864 * @hw: pointer to hardware structure 7865 * 7866 * Stops the transmit data path and waits for the HW to internally empty 7867 * the Tx security block 7868 **/ 7869 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw) 7870 { 7871 #define IXGBE_MAX_SECTX_POLL 40 7872 7873 int i; 7874 int sectxreg; 7875 7876 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 7877 sectxreg |= IXGBE_SECTXCTRL_TX_DIS; 7878 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 7879 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) { 7880 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT); 7881 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY) 7882 break; 7883 /* Use interrupt-safe sleep just in case */ 7884 usec_delay(1000); 7885 } 7886 7887 /* For informational purposes only */ 7888 if (i >= IXGBE_MAX_SECTX_POLL) 7889 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security " 7890 "path fully disabled. Continuing with init."); 7891 7892 return IXGBE_SUCCESS; 7893 } 7894 7895 /** 7896 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path 7897 * @hw: pointer to hardware structure 7898 * 7899 * Enables the transmit data path. 7900 **/ 7901 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw) 7902 { 7903 uint32_t sectxreg; 7904 7905 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 7906 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS; 7907 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 7908 IXGBE_WRITE_FLUSH(hw); 7909 7910 return IXGBE_SUCCESS; 7911 } 7912 7913 /* restore n-tuple filter */ 7914 static inline void 7915 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev) 7916 { 7917 struct ixgbe_filter_info *filter_info = 7918 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 7919 struct ixgbe_5tuple_filter *node; 7920 7921 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) { 7922 ixgbe_inject_5tuple_filter(dev, node); 7923 } 7924 } 7925 7926 /* restore ethernet type filter */ 7927 static inline void 7928 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev) 7929 { 7930 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7931 struct ixgbe_filter_info *filter_info = 7932 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 7933 int i; 7934 7935 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 7936 if (filter_info->ethertype_mask & (1 << i)) { 7937 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 7938 filter_info->ethertype_filters[i].etqf); 7939 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 7940 filter_info->ethertype_filters[i].etqs); 7941 IXGBE_WRITE_FLUSH(hw); 7942 } 7943 } 7944 } 7945 7946 /* restore SYN filter */ 7947 static inline void 7948 ixgbe_syn_filter_restore(struct rte_eth_dev *dev) 7949 { 7950 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7951 struct ixgbe_filter_info *filter_info = 7952 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 7953 uint32_t synqf; 7954 7955 synqf = filter_info->syn_info; 7956 7957 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 7958 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 7959 IXGBE_WRITE_FLUSH(hw); 7960 } 7961 } 7962 7963 /* restore L2 tunnel filter */ 7964 static inline void 7965 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev) 7966 { 7967 struct ixgbe_l2_tn_info *l2_tn_info = 7968 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7969 struct ixgbe_l2_tn_filter *node; 7970 struct ixgbe_l2_tunnel_conf l2_tn_conf; 7971 7972 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) { 7973 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type; 7974 l2_tn_conf.tunnel_id = node->key.tn_id; 7975 l2_tn_conf.pool = node->pool; 7976 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE); 7977 } 7978 } 7979 7980 /* restore rss filter */ 7981 static inline void 7982 ixgbe_rss_filter_restore(struct rte_eth_dev *dev) 7983 { 7984 struct ixgbe_filter_info *filter_info = 7985 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 7986 7987 if (filter_info->rss_info.conf.queue_num) 7988 ixgbe_config_rss_filter(dev, 7989 &filter_info->rss_info, TRUE); 7990 } 7991 7992 static int 7993 ixgbe_filter_restore(struct rte_eth_dev *dev) 7994 { 7995 ixgbe_ntuple_filter_restore(dev); 7996 ixgbe_ethertype_filter_restore(dev); 7997 ixgbe_syn_filter_restore(dev); 7998 ixgbe_fdir_filter_restore(dev); 7999 ixgbe_l2_tn_filter_restore(dev); 8000 ixgbe_rss_filter_restore(dev); 8001 8002 return 0; 8003 } 8004 8005 static void 8006 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev) 8007 { 8008 struct ixgbe_l2_tn_info *l2_tn_info = 8009 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8010 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8011 8012 if (l2_tn_info->e_tag_en) 8013 (void)ixgbe_e_tag_enable(hw); 8014 8015 if (l2_tn_info->e_tag_fwd_en) 8016 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1); 8017 8018 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type); 8019 } 8020 8021 /* remove all the n-tuple filters */ 8022 void 8023 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev) 8024 { 8025 struct ixgbe_filter_info *filter_info = 8026 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8027 struct ixgbe_5tuple_filter *p_5tuple; 8028 8029 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) 8030 ixgbe_remove_5tuple_filter(dev, p_5tuple); 8031 } 8032 8033 /* remove all the ether type filters */ 8034 void 8035 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev) 8036 { 8037 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8038 struct ixgbe_filter_info *filter_info = 8039 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8040 int i; 8041 8042 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8043 if (filter_info->ethertype_mask & (1 << i) && 8044 !filter_info->ethertype_filters[i].conf) { 8045 (void)ixgbe_ethertype_filter_remove(filter_info, 8046 (uint8_t)i); 8047 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0); 8048 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0); 8049 IXGBE_WRITE_FLUSH(hw); 8050 } 8051 } 8052 } 8053 8054 /* remove the SYN filter */ 8055 void 8056 ixgbe_clear_syn_filter(struct rte_eth_dev *dev) 8057 { 8058 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8059 struct ixgbe_filter_info *filter_info = 8060 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8061 8062 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) { 8063 filter_info->syn_info = 0; 8064 8065 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0); 8066 IXGBE_WRITE_FLUSH(hw); 8067 } 8068 } 8069 8070 /* remove all the L2 tunnel filters */ 8071 int 8072 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev) 8073 { 8074 struct ixgbe_l2_tn_info *l2_tn_info = 8075 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8076 struct ixgbe_l2_tn_filter *l2_tn_filter; 8077 struct ixgbe_l2_tunnel_conf l2_tn_conf; 8078 int ret = 0; 8079 8080 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 8081 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type; 8082 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id; 8083 l2_tn_conf.pool = l2_tn_filter->pool; 8084 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf); 8085 if (ret < 0) 8086 return ret; 8087 } 8088 8089 return 0; 8090 } 8091 8092 void 8093 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev, 8094 struct ixgbe_macsec_setting *macsec_setting) 8095 { 8096 struct ixgbe_macsec_setting *macsec = 8097 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 8098 8099 macsec->offload_en = macsec_setting->offload_en; 8100 macsec->encrypt_en = macsec_setting->encrypt_en; 8101 macsec->replayprotect_en = macsec_setting->replayprotect_en; 8102 } 8103 8104 void 8105 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev) 8106 { 8107 struct ixgbe_macsec_setting *macsec = 8108 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 8109 8110 macsec->offload_en = 0; 8111 macsec->encrypt_en = 0; 8112 macsec->replayprotect_en = 0; 8113 } 8114 8115 void 8116 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev, 8117 struct ixgbe_macsec_setting *macsec_setting) 8118 { 8119 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8120 uint32_t ctrl; 8121 uint8_t en = macsec_setting->encrypt_en; 8122 uint8_t rp = macsec_setting->replayprotect_en; 8123 8124 /** 8125 * Workaround: 8126 * As no ixgbe_disable_sec_rx_path equivalent is 8127 * implemented for tx in the base code, and we are 8128 * not allowed to modify the base code in DPDK, so 8129 * just call the hand-written one directly for now. 8130 * The hardware support has been checked by 8131 * ixgbe_disable_sec_rx_path(). 8132 */ 8133 ixgbe_disable_sec_tx_path_generic(hw); 8134 8135 /* Enable Ethernet CRC (required by MACsec offload) */ 8136 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0); 8137 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP; 8138 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl); 8139 8140 /* Enable the TX and RX crypto engines */ 8141 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8142 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS; 8143 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl); 8144 8145 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 8146 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS; 8147 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl); 8148 8149 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 8150 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK; 8151 ctrl |= 0x3; 8152 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl); 8153 8154 /* Enable SA lookup */ 8155 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL); 8156 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK; 8157 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT : 8158 IXGBE_LSECTXCTRL_AUTH; 8159 ctrl |= IXGBE_LSECTXCTRL_AISCI; 8160 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK; 8161 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK; 8162 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl); 8163 8164 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL); 8165 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK; 8166 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT; 8167 ctrl &= ~IXGBE_LSECRXCTRL_PLSH; 8168 if (rp) 8169 ctrl |= IXGBE_LSECRXCTRL_RP; 8170 else 8171 ctrl &= ~IXGBE_LSECRXCTRL_RP; 8172 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl); 8173 8174 /* Start the data paths */ 8175 ixgbe_enable_sec_rx_path(hw); 8176 /** 8177 * Workaround: 8178 * As no ixgbe_enable_sec_rx_path equivalent is 8179 * implemented for tx in the base code, and we are 8180 * not allowed to modify the base code in DPDK, so 8181 * just call the hand-written one directly for now. 8182 */ 8183 ixgbe_enable_sec_tx_path_generic(hw); 8184 } 8185 8186 void 8187 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev) 8188 { 8189 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8190 uint32_t ctrl; 8191 8192 /** 8193 * Workaround: 8194 * As no ixgbe_disable_sec_rx_path equivalent is 8195 * implemented for tx in the base code, and we are 8196 * not allowed to modify the base code in DPDK, so 8197 * just call the hand-written one directly for now. 8198 * The hardware support has been checked by 8199 * ixgbe_disable_sec_rx_path(). 8200 */ 8201 ixgbe_disable_sec_tx_path_generic(hw); 8202 8203 /* Disable the TX and RX crypto engines */ 8204 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8205 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS; 8206 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl); 8207 8208 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 8209 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS; 8210 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl); 8211 8212 /* Disable SA lookup */ 8213 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL); 8214 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK; 8215 ctrl |= IXGBE_LSECTXCTRL_DISABLE; 8216 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl); 8217 8218 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL); 8219 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK; 8220 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT; 8221 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl); 8222 8223 /* Start the data paths */ 8224 ixgbe_enable_sec_rx_path(hw); 8225 /** 8226 * Workaround: 8227 * As no ixgbe_enable_sec_rx_path equivalent is 8228 * implemented for tx in the base code, and we are 8229 * not allowed to modify the base code in DPDK, so 8230 * just call the hand-written one directly for now. 8231 */ 8232 ixgbe_enable_sec_tx_path_generic(hw); 8233 } 8234 8235 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd); 8236 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map); 8237 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 8238 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd); 8239 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map); 8240 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci"); 8241 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf, 8242 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>"); 8243 8244 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_init, init, NOTICE); 8245 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_driver, driver, NOTICE); 8246 8247 #ifdef RTE_ETHDEV_DEBUG_RX 8248 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_rx, rx, DEBUG); 8249 #endif 8250 #ifdef RTE_ETHDEV_DEBUG_TX 8251 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_tx, tx, DEBUG); 8252 #endif 8253