1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <inttypes.h> 13 #include <netinet/in.h> 14 #include <rte_string_fns.h> 15 #include <rte_byteorder.h> 16 #include <rte_common.h> 17 #include <rte_cycles.h> 18 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_bus_pci.h> 24 #include <rte_branch_prediction.h> 25 #include <rte_memory.h> 26 #include <rte_kvargs.h> 27 #include <rte_eal.h> 28 #include <rte_alarm.h> 29 #include <rte_ether.h> 30 #include <rte_ethdev_driver.h> 31 #include <rte_ethdev_pci.h> 32 #include <rte_malloc.h> 33 #include <rte_random.h> 34 #include <rte_dev.h> 35 #include <rte_hash_crc.h> 36 #ifdef RTE_LIBRTE_SECURITY 37 #include <rte_security_driver.h> 38 #endif 39 40 #include "ixgbe_logs.h" 41 #include "base/ixgbe_api.h" 42 #include "base/ixgbe_vf.h" 43 #include "base/ixgbe_common.h" 44 #include "ixgbe_ethdev.h" 45 #include "ixgbe_bypass.h" 46 #include "ixgbe_rxtx.h" 47 #include "base/ixgbe_type.h" 48 #include "base/ixgbe_phy.h" 49 #include "ixgbe_regs.h" 50 51 /* 52 * High threshold controlling when to start sending XOFF frames. Must be at 53 * least 8 bytes less than receive packet buffer size. This value is in units 54 * of 1024 bytes. 55 */ 56 #define IXGBE_FC_HI 0x80 57 58 /* 59 * Low threshold controlling when to start sending XON frames. This value is 60 * in units of 1024 bytes. 61 */ 62 #define IXGBE_FC_LO 0x40 63 64 /* Timer value included in XOFF frames. */ 65 #define IXGBE_FC_PAUSE 0x680 66 67 /*Default value of Max Rx Queue*/ 68 #define IXGBE_MAX_RX_QUEUE_NUM 128 69 70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */ 71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */ 72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */ 73 74 #define IXGBE_MMW_SIZE_DEFAULT 0x4 75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14 76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */ 77 78 /* 79 * Default values for RX/TX configuration 80 */ 81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32 82 #define IXGBE_DEFAULT_RX_PTHRESH 8 83 #define IXGBE_DEFAULT_RX_HTHRESH 8 84 #define IXGBE_DEFAULT_RX_WTHRESH 0 85 86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32 87 #define IXGBE_DEFAULT_TX_PTHRESH 32 88 #define IXGBE_DEFAULT_TX_HTHRESH 0 89 #define IXGBE_DEFAULT_TX_WTHRESH 0 90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32 91 92 /* Bit shift and mask */ 93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2) 94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t) 95 #define IXGBE_8_BIT_WIDTH CHAR_BIT 96 #define IXGBE_8_BIT_MASK UINT8_MAX 97 98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */ 99 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0])) 101 102 /* Additional timesync values. */ 103 #define NSEC_PER_SEC 1000000000L 104 #define IXGBE_INCVAL_10GB 0x66666666 105 #define IXGBE_INCVAL_1GB 0x40000000 106 #define IXGBE_INCVAL_100 0x50000000 107 #define IXGBE_INCVAL_SHIFT_10GB 28 108 #define IXGBE_INCVAL_SHIFT_1GB 24 109 #define IXGBE_INCVAL_SHIFT_100 21 110 #define IXGBE_INCVAL_SHIFT_82599 7 111 #define IXGBE_INCPER_SHIFT_82599 24 112 113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL 114 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000 117 #define IXGBE_ETAG_ETYPE 0x00005084 118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff 119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000 120 #define IXGBE_RAH_ADTYPE 0x40000000 121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff 122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */ 125 #define IXGBE_QDE_STRIP_TAG 0x00000004 126 #define IXGBE_VTEICR_MASK 0x07 127 128 #define IXGBE_EXVET_VET_EXT_SHIFT 16 129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000 130 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk" 132 133 static const char * const ixgbevf_valid_arguments[] = { 134 IXGBEVF_DEVARG_PFLINK_FULLCHK, 135 NULL 136 }; 137 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev); 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev); 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev); 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev); 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev); 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev); 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev); 146 static int ixgbe_dev_start(struct rte_eth_dev *dev); 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev); 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev); 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev); 150 static void ixgbe_dev_close(struct rte_eth_dev *dev); 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev); 152 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 153 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 154 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 155 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev, 157 int wait_to_complete); 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev, 159 struct rte_eth_stats *stats); 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev, 161 struct rte_eth_xstat *xstats, unsigned n); 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, 163 struct rte_eth_xstat *xstats, unsigned n); 164 static int 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 166 uint64_t *values, unsigned int n); 167 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev); 168 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev); 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 170 struct rte_eth_xstat_name *xstats_names, 171 unsigned int size); 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev, 173 struct rte_eth_xstat_name *xstats_names, unsigned limit); 174 static int ixgbe_dev_xstats_get_names_by_id( 175 struct rte_eth_dev *dev, 176 struct rte_eth_xstat_name *xstats_names, 177 const uint64_t *ids, 178 unsigned int limit); 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 180 uint16_t queue_id, 181 uint8_t stat_idx, 182 uint8_t is_rx); 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 184 size_t fw_size); 185 static void ixgbe_dev_info_get(struct rte_eth_dev *dev, 186 struct rte_eth_dev_info *dev_info); 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); 188 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev, 189 struct rte_eth_dev_info *dev_info); 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 191 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev, 193 uint16_t vlan_id, int on); 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 195 enum rte_vlan_type vlan_type, 196 uint16_t tpid_id); 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, 198 uint16_t queue, bool on); 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, 200 int on); 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, 202 int mask); 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask); 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask); 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue); 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue); 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev); 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev); 209 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev); 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev); 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, 213 struct rte_eth_fc_conf *fc_conf); 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, 215 struct rte_eth_fc_conf *fc_conf); 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 217 struct rte_eth_pfc_conf *pfc_conf); 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 219 struct rte_eth_rss_reta_entry64 *reta_conf, 220 uint16_t reta_size); 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 222 struct rte_eth_rss_reta_entry64 *reta_conf, 223 uint16_t reta_size); 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev); 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev); 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev); 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev); 230 static void ixgbe_dev_interrupt_handler(void *param); 231 static void ixgbe_dev_interrupt_delayed_handler(void *param); 232 static void ixgbe_dev_setup_link_alarm_handler(void *param); 233 234 static int ixgbe_add_rar(struct rte_eth_dev *dev, 235 struct rte_ether_addr *mac_addr, 236 uint32_t index, uint32_t pool); 237 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index); 238 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, 239 struct rte_ether_addr *mac_addr); 240 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config); 241 static bool is_device_supported(struct rte_eth_dev *dev, 242 struct rte_pci_driver *drv); 243 244 /* For Virtual Function support */ 245 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev); 246 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev); 247 static int ixgbevf_dev_configure(struct rte_eth_dev *dev); 248 static int ixgbevf_dev_start(struct rte_eth_dev *dev); 249 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev, 250 int wait_to_complete); 251 static void ixgbevf_dev_stop(struct rte_eth_dev *dev); 252 static void ixgbevf_dev_close(struct rte_eth_dev *dev); 253 static int ixgbevf_dev_reset(struct rte_eth_dev *dev); 254 static void ixgbevf_intr_disable(struct rte_eth_dev *dev); 255 static void ixgbevf_intr_enable(struct rte_eth_dev *dev); 256 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev, 257 struct rte_eth_stats *stats); 258 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev); 259 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, 260 uint16_t vlan_id, int on); 261 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, 262 uint16_t queue, int on); 263 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask); 264 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask); 265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on); 266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 267 uint16_t queue_id); 268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 269 uint16_t queue_id); 270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 271 uint8_t queue, uint8_t msix_vector); 272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev); 273 static void ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev); 274 static void ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev); 275 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev); 276 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev); 277 278 /* For Eth VMDQ APIs support */ 279 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct 280 rte_ether_addr * mac_addr, uint8_t on); 281 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on); 282 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 283 struct rte_eth_mirror_conf *mirror_conf, 284 uint8_t rule_id, uint8_t on); 285 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, 286 uint8_t rule_id); 287 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 288 uint16_t queue_id); 289 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 290 uint16_t queue_id); 291 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 292 uint8_t queue, uint8_t msix_vector); 293 static void ixgbe_configure_msix(struct rte_eth_dev *dev); 294 295 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev, 296 struct rte_ether_addr *mac_addr, 297 uint32_t index, uint32_t pool); 298 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index); 299 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 300 struct rte_ether_addr *mac_addr); 301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev, 302 struct rte_eth_syn_filter *filter); 303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev, 304 enum rte_filter_op filter_op, 305 void *arg); 306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 307 struct ixgbe_5tuple_filter *filter); 308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 309 struct ixgbe_5tuple_filter *filter); 310 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev, 311 enum rte_filter_op filter_op, 312 void *arg); 313 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev, 314 struct rte_eth_ntuple_filter *filter); 315 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev, 316 enum rte_filter_op filter_op, 317 void *arg); 318 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, 319 struct rte_eth_ethertype_filter *filter); 320 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 321 enum rte_filter_type filter_type, 322 enum rte_filter_op filter_op, 323 void *arg); 324 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 325 326 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 327 struct rte_ether_addr *mc_addr_set, 328 uint32_t nb_mc_addr); 329 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 330 struct rte_eth_dcb_info *dcb_info); 331 332 static int ixgbe_get_reg_length(struct rte_eth_dev *dev); 333 static int ixgbe_get_regs(struct rte_eth_dev *dev, 334 struct rte_dev_reg_info *regs); 335 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev); 336 static int ixgbe_get_eeprom(struct rte_eth_dev *dev, 337 struct rte_dev_eeprom_info *eeprom); 338 static int ixgbe_set_eeprom(struct rte_eth_dev *dev, 339 struct rte_dev_eeprom_info *eeprom); 340 341 static int ixgbe_get_module_info(struct rte_eth_dev *dev, 342 struct rte_eth_dev_module_info *modinfo); 343 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 344 struct rte_dev_eeprom_info *info); 345 346 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev); 347 static int ixgbevf_get_regs(struct rte_eth_dev *dev, 348 struct rte_dev_reg_info *regs); 349 350 static int ixgbe_timesync_enable(struct rte_eth_dev *dev); 351 static int ixgbe_timesync_disable(struct rte_eth_dev *dev); 352 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 353 struct timespec *timestamp, 354 uint32_t flags); 355 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 356 struct timespec *timestamp); 357 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 358 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev, 359 struct timespec *timestamp); 360 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev, 361 const struct timespec *timestamp); 362 static void ixgbevf_dev_interrupt_handler(void *param); 363 364 static int ixgbe_dev_l2_tunnel_eth_type_conf 365 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel); 366 static int ixgbe_dev_l2_tunnel_offload_set 367 (struct rte_eth_dev *dev, 368 struct rte_eth_l2_tunnel_conf *l2_tunnel, 369 uint32_t mask, 370 uint8_t en); 371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev, 372 enum rte_filter_op filter_op, 373 void *arg); 374 375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 376 struct rte_eth_udp_tunnel *udp_tunnel); 377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 378 struct rte_eth_udp_tunnel *udp_tunnel); 379 static int ixgbe_filter_restore(struct rte_eth_dev *dev); 380 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev); 381 382 /* 383 * Define VF Stats MACRO for Non "cleared on read" register 384 */ 385 #define UPDATE_VF_STAT(reg, last, cur) \ 386 { \ 387 uint32_t latest = IXGBE_READ_REG(hw, reg); \ 388 cur += (latest - last) & UINT_MAX; \ 389 last = latest; \ 390 } 391 392 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \ 393 { \ 394 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \ 395 u64 new_msb = IXGBE_READ_REG(hw, msb); \ 396 u64 latest = ((new_msb << 32) | new_lsb); \ 397 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \ 398 last = latest; \ 399 } 400 401 #define IXGBE_SET_HWSTRIP(h, q) do {\ 402 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 403 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 404 (h)->bitmap[idx] |= 1 << bit;\ 405 } while (0) 406 407 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\ 408 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 409 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 410 (h)->bitmap[idx] &= ~(1 << bit);\ 411 } while (0) 412 413 #define IXGBE_GET_HWSTRIP(h, q, r) do {\ 414 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 415 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 416 (r) = (h)->bitmap[idx] >> bit & 1;\ 417 } while (0) 418 419 int ixgbe_logtype_init; 420 int ixgbe_logtype_driver; 421 422 /* 423 * The set of PCI devices this driver supports 424 */ 425 static const struct rte_pci_id pci_id_ixgbe_map[] = { 426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) }, 427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) }, 428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) }, 429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) }, 430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) }, 431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) }, 432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) }, 433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) }, 434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) }, 435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) }, 436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) }, 437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) }, 438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) }, 439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) }, 440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) }, 441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) }, 442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) }, 443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) }, 444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) }, 445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) }, 446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) }, 447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) }, 448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) }, 449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) }, 450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) }, 451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) }, 452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) }, 453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) }, 454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) }, 455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) }, 456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) }, 457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) }, 458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) }, 459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) }, 460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) }, 461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) }, 462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) }, 463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) }, 464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) }, 465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) }, 466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) }, 467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) }, 468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) }, 469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) }, 470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) }, 471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) }, 472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) }, 473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) }, 474 #ifdef RTE_LIBRTE_IXGBE_BYPASS 475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) }, 476 #endif 477 { .vendor_id = 0, /* sentinel */ }, 478 }; 479 480 /* 481 * The set of PCI devices this driver supports (for 82599 VF) 482 */ 483 static const struct rte_pci_id pci_id_ixgbevf_map[] = { 484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) }, 485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) }, 486 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) }, 487 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) }, 488 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) }, 489 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) }, 490 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) }, 491 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) }, 492 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) }, 493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) }, 494 { .vendor_id = 0, /* sentinel */ }, 495 }; 496 497 static const struct rte_eth_desc_lim rx_desc_lim = { 498 .nb_max = IXGBE_MAX_RING_DESC, 499 .nb_min = IXGBE_MIN_RING_DESC, 500 .nb_align = IXGBE_RXD_ALIGN, 501 }; 502 503 static const struct rte_eth_desc_lim tx_desc_lim = { 504 .nb_max = IXGBE_MAX_RING_DESC, 505 .nb_min = IXGBE_MIN_RING_DESC, 506 .nb_align = IXGBE_TXD_ALIGN, 507 .nb_seg_max = IXGBE_TX_MAX_SEG, 508 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG, 509 }; 510 511 static const struct eth_dev_ops ixgbe_eth_dev_ops = { 512 .dev_configure = ixgbe_dev_configure, 513 .dev_start = ixgbe_dev_start, 514 .dev_stop = ixgbe_dev_stop, 515 .dev_set_link_up = ixgbe_dev_set_link_up, 516 .dev_set_link_down = ixgbe_dev_set_link_down, 517 .dev_close = ixgbe_dev_close, 518 .dev_reset = ixgbe_dev_reset, 519 .promiscuous_enable = ixgbe_dev_promiscuous_enable, 520 .promiscuous_disable = ixgbe_dev_promiscuous_disable, 521 .allmulticast_enable = ixgbe_dev_allmulticast_enable, 522 .allmulticast_disable = ixgbe_dev_allmulticast_disable, 523 .link_update = ixgbe_dev_link_update, 524 .stats_get = ixgbe_dev_stats_get, 525 .xstats_get = ixgbe_dev_xstats_get, 526 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id, 527 .stats_reset = ixgbe_dev_stats_reset, 528 .xstats_reset = ixgbe_dev_xstats_reset, 529 .xstats_get_names = ixgbe_dev_xstats_get_names, 530 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id, 531 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set, 532 .fw_version_get = ixgbe_fw_version_get, 533 .dev_infos_get = ixgbe_dev_info_get, 534 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 535 .mtu_set = ixgbe_dev_mtu_set, 536 .vlan_filter_set = ixgbe_vlan_filter_set, 537 .vlan_tpid_set = ixgbe_vlan_tpid_set, 538 .vlan_offload_set = ixgbe_vlan_offload_set, 539 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set, 540 .rx_queue_start = ixgbe_dev_rx_queue_start, 541 .rx_queue_stop = ixgbe_dev_rx_queue_stop, 542 .tx_queue_start = ixgbe_dev_tx_queue_start, 543 .tx_queue_stop = ixgbe_dev_tx_queue_stop, 544 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 545 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable, 546 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable, 547 .rx_queue_release = ixgbe_dev_rx_queue_release, 548 .rx_queue_count = ixgbe_dev_rx_queue_count, 549 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done, 550 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status, 551 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status, 552 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 553 .tx_queue_release = ixgbe_dev_tx_queue_release, 554 .dev_led_on = ixgbe_dev_led_on, 555 .dev_led_off = ixgbe_dev_led_off, 556 .flow_ctrl_get = ixgbe_flow_ctrl_get, 557 .flow_ctrl_set = ixgbe_flow_ctrl_set, 558 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set, 559 .mac_addr_add = ixgbe_add_rar, 560 .mac_addr_remove = ixgbe_remove_rar, 561 .mac_addr_set = ixgbe_set_default_mac_addr, 562 .uc_hash_table_set = ixgbe_uc_hash_table_set, 563 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set, 564 .mirror_rule_set = ixgbe_mirror_rule_set, 565 .mirror_rule_reset = ixgbe_mirror_rule_reset, 566 .set_queue_rate_limit = ixgbe_set_queue_rate_limit, 567 .reta_update = ixgbe_dev_rss_reta_update, 568 .reta_query = ixgbe_dev_rss_reta_query, 569 .rss_hash_update = ixgbe_dev_rss_hash_update, 570 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 571 .filter_ctrl = ixgbe_dev_filter_ctrl, 572 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 573 .rxq_info_get = ixgbe_rxq_info_get, 574 .txq_info_get = ixgbe_txq_info_get, 575 .timesync_enable = ixgbe_timesync_enable, 576 .timesync_disable = ixgbe_timesync_disable, 577 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp, 578 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp, 579 .get_reg = ixgbe_get_regs, 580 .get_eeprom_length = ixgbe_get_eeprom_length, 581 .get_eeprom = ixgbe_get_eeprom, 582 .set_eeprom = ixgbe_set_eeprom, 583 .get_module_info = ixgbe_get_module_info, 584 .get_module_eeprom = ixgbe_get_module_eeprom, 585 .get_dcb_info = ixgbe_dev_get_dcb_info, 586 .timesync_adjust_time = ixgbe_timesync_adjust_time, 587 .timesync_read_time = ixgbe_timesync_read_time, 588 .timesync_write_time = ixgbe_timesync_write_time, 589 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf, 590 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set, 591 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add, 592 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del, 593 .tm_ops_get = ixgbe_tm_ops_get, 594 }; 595 596 /* 597 * dev_ops for virtual function, bare necessities for basic vf 598 * operation have been implemented 599 */ 600 static const struct eth_dev_ops ixgbevf_eth_dev_ops = { 601 .dev_configure = ixgbevf_dev_configure, 602 .dev_start = ixgbevf_dev_start, 603 .dev_stop = ixgbevf_dev_stop, 604 .link_update = ixgbevf_dev_link_update, 605 .stats_get = ixgbevf_dev_stats_get, 606 .xstats_get = ixgbevf_dev_xstats_get, 607 .stats_reset = ixgbevf_dev_stats_reset, 608 .xstats_reset = ixgbevf_dev_stats_reset, 609 .xstats_get_names = ixgbevf_dev_xstats_get_names, 610 .dev_close = ixgbevf_dev_close, 611 .dev_reset = ixgbevf_dev_reset, 612 .promiscuous_enable = ixgbevf_dev_promiscuous_enable, 613 .promiscuous_disable = ixgbevf_dev_promiscuous_disable, 614 .allmulticast_enable = ixgbevf_dev_allmulticast_enable, 615 .allmulticast_disable = ixgbevf_dev_allmulticast_disable, 616 .dev_infos_get = ixgbevf_dev_info_get, 617 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 618 .mtu_set = ixgbevf_dev_set_mtu, 619 .vlan_filter_set = ixgbevf_vlan_filter_set, 620 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set, 621 .vlan_offload_set = ixgbevf_vlan_offload_set, 622 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 623 .rx_queue_release = ixgbe_dev_rx_queue_release, 624 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done, 625 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status, 626 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status, 627 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 628 .tx_queue_release = ixgbe_dev_tx_queue_release, 629 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable, 630 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable, 631 .mac_addr_add = ixgbevf_add_mac_addr, 632 .mac_addr_remove = ixgbevf_remove_mac_addr, 633 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 634 .rxq_info_get = ixgbe_rxq_info_get, 635 .txq_info_get = ixgbe_txq_info_get, 636 .mac_addr_set = ixgbevf_set_default_mac_addr, 637 .get_reg = ixgbevf_get_regs, 638 .reta_update = ixgbe_dev_rss_reta_update, 639 .reta_query = ixgbe_dev_rss_reta_query, 640 .rss_hash_update = ixgbe_dev_rss_hash_update, 641 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 642 }; 643 644 /* store statistics names and its offset in stats structure */ 645 struct rte_ixgbe_xstats_name_off { 646 char name[RTE_ETH_XSTATS_NAME_SIZE]; 647 unsigned offset; 648 }; 649 650 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = { 651 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)}, 652 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)}, 653 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)}, 654 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)}, 655 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)}, 656 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)}, 657 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)}, 658 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)}, 659 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)}, 660 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)}, 661 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)}, 662 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)}, 663 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)}, 664 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)}, 665 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 666 prc1023)}, 667 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 668 prc1522)}, 669 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)}, 670 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)}, 671 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)}, 672 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)}, 673 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)}, 674 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)}, 675 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)}, 676 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)}, 677 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)}, 678 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)}, 679 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)}, 680 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)}, 681 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)}, 682 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)}, 683 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)}, 684 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)}, 685 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 686 ptc1023)}, 687 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 688 ptc1522)}, 689 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)}, 690 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)}, 691 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)}, 692 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)}, 693 694 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats, 695 fdirustat_add)}, 696 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats, 697 fdirustat_remove)}, 698 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats, 699 fdirfstat_fadd)}, 700 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats, 701 fdirfstat_fremove)}, 702 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats, 703 fdirmatch)}, 704 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats, 705 fdirmiss)}, 706 707 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)}, 708 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)}, 709 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, 710 fclast)}, 711 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)}, 712 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)}, 713 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)}, 714 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)}, 715 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats, 716 fcoe_noddp)}, 717 {"rx_fcoe_no_direct_data_placement_ext_buff", 718 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)}, 719 720 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 721 lxontxc)}, 722 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 723 lxonrxc)}, 724 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 725 lxofftxc)}, 726 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 727 lxoffrxc)}, 728 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)}, 729 }; 730 731 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \ 732 sizeof(rte_ixgbe_stats_strings[0])) 733 734 /* MACsec statistics */ 735 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = { 736 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 737 out_pkts_untagged)}, 738 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats, 739 out_pkts_encrypted)}, 740 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats, 741 out_pkts_protected)}, 742 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats, 743 out_octets_encrypted)}, 744 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats, 745 out_octets_protected)}, 746 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 747 in_pkts_untagged)}, 748 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats, 749 in_pkts_badtag)}, 750 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats, 751 in_pkts_nosci)}, 752 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats, 753 in_pkts_unknownsci)}, 754 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats, 755 in_octets_decrypted)}, 756 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats, 757 in_octets_validated)}, 758 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats, 759 in_pkts_unchecked)}, 760 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats, 761 in_pkts_delayed)}, 762 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats, 763 in_pkts_late)}, 764 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats, 765 in_pkts_ok)}, 766 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats, 767 in_pkts_invalid)}, 768 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats, 769 in_pkts_notvalid)}, 770 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats, 771 in_pkts_unusedsa)}, 772 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats, 773 in_pkts_notusingsa)}, 774 }; 775 776 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \ 777 sizeof(rte_ixgbe_macsec_strings[0])) 778 779 /* Per-queue statistics */ 780 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = { 781 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)}, 782 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)}, 783 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)}, 784 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)}, 785 }; 786 787 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \ 788 sizeof(rte_ixgbe_rxq_strings[0])) 789 #define IXGBE_NB_RXQ_PRIO_VALUES 8 790 791 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = { 792 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)}, 793 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)}, 794 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats, 795 pxon2offc)}, 796 }; 797 798 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \ 799 sizeof(rte_ixgbe_txq_strings[0])) 800 #define IXGBE_NB_TXQ_PRIO_VALUES 8 801 802 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = { 803 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)}, 804 }; 805 806 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \ 807 sizeof(rte_ixgbevf_stats_strings[0])) 808 809 /* 810 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h. 811 */ 812 static inline int 813 ixgbe_is_sfp(struct ixgbe_hw *hw) 814 { 815 switch (hw->phy.type) { 816 case ixgbe_phy_sfp_avago: 817 case ixgbe_phy_sfp_ftl: 818 case ixgbe_phy_sfp_intel: 819 case ixgbe_phy_sfp_unknown: 820 case ixgbe_phy_sfp_passive_tyco: 821 case ixgbe_phy_sfp_passive_unknown: 822 return 1; 823 default: 824 return 0; 825 } 826 } 827 828 static inline int32_t 829 ixgbe_pf_reset_hw(struct ixgbe_hw *hw) 830 { 831 uint32_t ctrl_ext; 832 int32_t status; 833 834 status = ixgbe_reset_hw(hw); 835 836 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 837 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 838 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 839 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 840 IXGBE_WRITE_FLUSH(hw); 841 842 if (status == IXGBE_ERR_SFP_NOT_PRESENT) 843 status = IXGBE_SUCCESS; 844 return status; 845 } 846 847 static inline void 848 ixgbe_enable_intr(struct rte_eth_dev *dev) 849 { 850 struct ixgbe_interrupt *intr = 851 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 852 struct ixgbe_hw *hw = 853 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 854 855 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask); 856 IXGBE_WRITE_FLUSH(hw); 857 } 858 859 /* 860 * This function is based on ixgbe_disable_intr() in base/ixgbe.h. 861 */ 862 static void 863 ixgbe_disable_intr(struct ixgbe_hw *hw) 864 { 865 PMD_INIT_FUNC_TRACE(); 866 867 if (hw->mac.type == ixgbe_mac_82598EB) { 868 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0); 869 } else { 870 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000); 871 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0); 872 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0); 873 } 874 IXGBE_WRITE_FLUSH(hw); 875 } 876 877 /* 878 * This function resets queue statistics mapping registers. 879 * From Niantic datasheet, Initialization of Statistics section: 880 * "...if software requires the queue counters, the RQSMR and TQSM registers 881 * must be re-programmed following a device reset. 882 */ 883 static void 884 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw) 885 { 886 uint32_t i; 887 888 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) { 889 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0); 890 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0); 891 } 892 } 893 894 895 static int 896 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 897 uint16_t queue_id, 898 uint8_t stat_idx, 899 uint8_t is_rx) 900 { 901 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8 902 #define NB_QMAP_FIELDS_PER_QSM_REG 4 903 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f 904 905 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 906 struct ixgbe_stat_mapping_registers *stat_mappings = 907 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private); 908 uint32_t qsmr_mask = 0; 909 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK; 910 uint32_t q_map; 911 uint8_t n, offset; 912 913 if ((hw->mac.type != ixgbe_mac_82599EB) && 914 (hw->mac.type != ixgbe_mac_X540) && 915 (hw->mac.type != ixgbe_mac_X550) && 916 (hw->mac.type != ixgbe_mac_X550EM_x) && 917 (hw->mac.type != ixgbe_mac_X550EM_a)) 918 return -ENOSYS; 919 920 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d", 921 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 922 queue_id, stat_idx); 923 924 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG); 925 if (n >= IXGBE_NB_STAT_MAPPING_REGS) { 926 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded"); 927 return -EIO; 928 } 929 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG); 930 931 /* Now clear any previous stat_idx set */ 932 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 933 if (!is_rx) 934 stat_mappings->tqsm[n] &= ~clearing_mask; 935 else 936 stat_mappings->rqsmr[n] &= ~clearing_mask; 937 938 q_map = (uint32_t)stat_idx; 939 q_map &= QMAP_FIELD_RESERVED_BITS_MASK; 940 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 941 if (!is_rx) 942 stat_mappings->tqsm[n] |= qsmr_mask; 943 else 944 stat_mappings->rqsmr[n] |= qsmr_mask; 945 946 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d", 947 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 948 queue_id, stat_idx); 949 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n, 950 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]); 951 952 /* Now write the mapping in the appropriate register */ 953 if (is_rx) { 954 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d", 955 stat_mappings->rqsmr[n], n); 956 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]); 957 } else { 958 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d", 959 stat_mappings->tqsm[n], n); 960 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]); 961 } 962 return 0; 963 } 964 965 static void 966 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev) 967 { 968 struct ixgbe_stat_mapping_registers *stat_mappings = 969 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private); 970 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 971 int i; 972 973 /* write whatever was in stat mapping table to the NIC */ 974 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) { 975 /* rx */ 976 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]); 977 978 /* tx */ 979 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]); 980 } 981 } 982 983 static void 984 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config) 985 { 986 uint8_t i; 987 struct ixgbe_dcb_tc_config *tc; 988 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS; 989 990 dcb_config->num_tcs.pg_tcs = dcb_max_tc; 991 dcb_config->num_tcs.pfc_tcs = dcb_max_tc; 992 for (i = 0; i < dcb_max_tc; i++) { 993 tc = &dcb_config->tc_config[i]; 994 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i; 995 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 996 (uint8_t)(100/dcb_max_tc + (i & 1)); 997 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i; 998 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 999 (uint8_t)(100/dcb_max_tc + (i & 1)); 1000 tc->pfc = ixgbe_dcb_pfc_disabled; 1001 } 1002 1003 /* Initialize default user to priority mapping, UPx->TC0 */ 1004 tc = &dcb_config->tc_config[0]; 1005 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 1006 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 1007 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) { 1008 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100; 1009 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100; 1010 } 1011 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal; 1012 dcb_config->pfc_mode_enable = false; 1013 dcb_config->vt_mode = true; 1014 dcb_config->round_robin_enable = false; 1015 /* support all DCB capabilities in 82599 */ 1016 dcb_config->support.capabilities = 0xFF; 1017 1018 /*we only support 4 Tcs for X540, X550 */ 1019 if (hw->mac.type == ixgbe_mac_X540 || 1020 hw->mac.type == ixgbe_mac_X550 || 1021 hw->mac.type == ixgbe_mac_X550EM_x || 1022 hw->mac.type == ixgbe_mac_X550EM_a) { 1023 dcb_config->num_tcs.pg_tcs = 4; 1024 dcb_config->num_tcs.pfc_tcs = 4; 1025 } 1026 } 1027 1028 /* 1029 * Ensure that all locks are released before first NVM or PHY access 1030 */ 1031 static void 1032 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw) 1033 { 1034 uint16_t mask; 1035 1036 /* 1037 * Phy lock should not fail in this early stage. If this is the case, 1038 * it is due to an improper exit of the application. 1039 * So force the release of the faulty lock. Release of common lock 1040 * is done automatically by swfw_sync function. 1041 */ 1042 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func; 1043 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1044 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func); 1045 } 1046 ixgbe_release_swfw_semaphore(hw, mask); 1047 1048 /* 1049 * These ones are more tricky since they are common to all ports; but 1050 * swfw_sync retries last long enough (1s) to be almost sure that if 1051 * lock can not be taken it is due to an improper lock of the 1052 * semaphore. 1053 */ 1054 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM; 1055 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1056 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 1057 } 1058 ixgbe_release_swfw_semaphore(hw, mask); 1059 } 1060 1061 /* 1062 * This function is based on code in ixgbe_attach() in base/ixgbe.c. 1063 * It returns 0 on success. 1064 */ 1065 static int 1066 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) 1067 { 1068 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1069 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1070 struct ixgbe_hw *hw = 1071 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1072 struct ixgbe_vfta *shadow_vfta = 1073 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1074 struct ixgbe_hwstrip *hwstrip = 1075 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1076 struct ixgbe_dcb_config *dcb_config = 1077 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private); 1078 struct ixgbe_filter_info *filter_info = 1079 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1080 struct ixgbe_bw_conf *bw_conf = 1081 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private); 1082 uint32_t ctrl_ext; 1083 uint16_t csum; 1084 int diag, i; 1085 1086 PMD_INIT_FUNC_TRACE(); 1087 1088 eth_dev->dev_ops = &ixgbe_eth_dev_ops; 1089 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1090 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1091 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts; 1092 1093 /* 1094 * For secondary processes, we don't initialise any further as primary 1095 * has already done this work. Only check we don't need a different 1096 * RX and TX function. 1097 */ 1098 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1099 struct ixgbe_tx_queue *txq; 1100 /* TX queue function in primary, set by last queue initialized 1101 * Tx queue may not initialized by primary process 1102 */ 1103 if (eth_dev->data->tx_queues) { 1104 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1]; 1105 ixgbe_set_tx_function(eth_dev, txq); 1106 } else { 1107 /* Use default TX function if we get here */ 1108 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. " 1109 "Using default TX function."); 1110 } 1111 1112 ixgbe_set_rx_function(eth_dev); 1113 1114 return 0; 1115 } 1116 1117 rte_eth_copy_pci_info(eth_dev, pci_dev); 1118 1119 /* Vendor and Device ID need to be set before init of shared code */ 1120 hw->device_id = pci_dev->id.device_id; 1121 hw->vendor_id = pci_dev->id.vendor_id; 1122 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1123 hw->allow_unsupported_sfp = 1; 1124 1125 /* Initialize the shared code (base driver) */ 1126 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1127 diag = ixgbe_bypass_init_shared_code(hw); 1128 #else 1129 diag = ixgbe_init_shared_code(hw); 1130 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1131 1132 if (diag != IXGBE_SUCCESS) { 1133 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag); 1134 return -EIO; 1135 } 1136 1137 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 1138 PMD_INIT_LOG(ERR, "\nERROR: " 1139 "Firmware recovery mode detected. Limiting functionality.\n" 1140 "Refer to the Intel(R) Ethernet Adapters and Devices " 1141 "User Guide for details on firmware recovery mode."); 1142 return -EIO; 1143 } 1144 1145 /* pick up the PCI bus settings for reporting later */ 1146 ixgbe_get_bus_info(hw); 1147 1148 /* Unlock any pending hardware semaphore */ 1149 ixgbe_swfw_lock_reset(hw); 1150 1151 #ifdef RTE_LIBRTE_SECURITY 1152 /* Initialize security_ctx only for primary process*/ 1153 if (ixgbe_ipsec_ctx_create(eth_dev)) 1154 return -ENOMEM; 1155 #endif 1156 1157 /* Initialize DCB configuration*/ 1158 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config)); 1159 ixgbe_dcb_init(hw, dcb_config); 1160 /* Get Hardware Flow Control setting */ 1161 hw->fc.requested_mode = ixgbe_fc_full; 1162 hw->fc.current_mode = ixgbe_fc_full; 1163 hw->fc.pause_time = IXGBE_FC_PAUSE; 1164 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 1165 hw->fc.low_water[i] = IXGBE_FC_LO; 1166 hw->fc.high_water[i] = IXGBE_FC_HI; 1167 } 1168 hw->fc.send_xon = 1; 1169 1170 /* Make sure we have a good EEPROM before we read from it */ 1171 diag = ixgbe_validate_eeprom_checksum(hw, &csum); 1172 if (diag != IXGBE_SUCCESS) { 1173 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag); 1174 return -EIO; 1175 } 1176 1177 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1178 diag = ixgbe_bypass_init_hw(hw); 1179 #else 1180 diag = ixgbe_init_hw(hw); 1181 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1182 1183 /* 1184 * Devices with copper phys will fail to initialise if ixgbe_init_hw() 1185 * is called too soon after the kernel driver unbinding/binding occurs. 1186 * The failure occurs in ixgbe_identify_phy_generic() for all devices, 1187 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is 1188 * also called. See ixgbe_identify_phy_82599(). The reason for the 1189 * failure is not known, and only occuts when virtualisation features 1190 * are disabled in the bios. A delay of 100ms was found to be enough by 1191 * trial-and-error, and is doubled to be safe. 1192 */ 1193 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) { 1194 rte_delay_ms(200); 1195 diag = ixgbe_init_hw(hw); 1196 } 1197 1198 if (diag == IXGBE_ERR_SFP_NOT_PRESENT) 1199 diag = IXGBE_SUCCESS; 1200 1201 if (diag == IXGBE_ERR_EEPROM_VERSION) { 1202 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/" 1203 "LOM. Please be aware there may be issues associated " 1204 "with your hardware."); 1205 PMD_INIT_LOG(ERR, "If you are experiencing problems " 1206 "please contact your Intel or hardware representative " 1207 "who provided you with this hardware."); 1208 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED) 1209 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module"); 1210 if (diag) { 1211 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag); 1212 return -EIO; 1213 } 1214 1215 /* Reset the hw statistics */ 1216 ixgbe_dev_stats_reset(eth_dev); 1217 1218 /* disable interrupt */ 1219 ixgbe_disable_intr(hw); 1220 1221 /* reset mappings for queue statistics hw counters*/ 1222 ixgbe_reset_qstat_mappings(hw); 1223 1224 /* Allocate memory for storing MAC addresses */ 1225 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN * 1226 hw->mac.num_rar_entries, 0); 1227 if (eth_dev->data->mac_addrs == NULL) { 1228 PMD_INIT_LOG(ERR, 1229 "Failed to allocate %u bytes needed to store " 1230 "MAC addresses", 1231 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1232 return -ENOMEM; 1233 } 1234 /* Copy the permanent MAC address */ 1235 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr, 1236 ð_dev->data->mac_addrs[0]); 1237 1238 /* Allocate memory for storing hash filter MAC addresses */ 1239 eth_dev->data->hash_mac_addrs = rte_zmalloc( 1240 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0); 1241 if (eth_dev->data->hash_mac_addrs == NULL) { 1242 PMD_INIT_LOG(ERR, 1243 "Failed to allocate %d bytes needed to store MAC addresses", 1244 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC); 1245 return -ENOMEM; 1246 } 1247 1248 /* initialize the vfta */ 1249 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1250 1251 /* initialize the hw strip bitmap*/ 1252 memset(hwstrip, 0, sizeof(*hwstrip)); 1253 1254 /* initialize PF if max_vfs not zero */ 1255 ixgbe_pf_host_init(eth_dev); 1256 1257 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 1258 /* let hardware know driver is loaded */ 1259 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD; 1260 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 1261 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 1262 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 1263 IXGBE_WRITE_FLUSH(hw); 1264 1265 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 1266 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d", 1267 (int) hw->mac.type, (int) hw->phy.type, 1268 (int) hw->phy.sfp_type); 1269 else 1270 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d", 1271 (int) hw->mac.type, (int) hw->phy.type); 1272 1273 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 1274 eth_dev->data->port_id, pci_dev->id.vendor_id, 1275 pci_dev->id.device_id); 1276 1277 rte_intr_callback_register(intr_handle, 1278 ixgbe_dev_interrupt_handler, eth_dev); 1279 1280 /* enable uio/vfio intr/eventfd mapping */ 1281 rte_intr_enable(intr_handle); 1282 1283 /* enable support intr */ 1284 ixgbe_enable_intr(eth_dev); 1285 1286 /* initialize filter info */ 1287 memset(filter_info, 0, 1288 sizeof(struct ixgbe_filter_info)); 1289 1290 /* initialize 5tuple filter list */ 1291 TAILQ_INIT(&filter_info->fivetuple_list); 1292 1293 /* initialize flow director filter list & hash */ 1294 ixgbe_fdir_filter_init(eth_dev); 1295 1296 /* initialize l2 tunnel filter list & hash */ 1297 ixgbe_l2_tn_filter_init(eth_dev); 1298 1299 /* initialize flow filter lists */ 1300 ixgbe_filterlist_init(); 1301 1302 /* initialize bandwidth configuration info */ 1303 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf)); 1304 1305 /* initialize Traffic Manager configuration */ 1306 ixgbe_tm_conf_init(eth_dev); 1307 1308 return 0; 1309 } 1310 1311 static int 1312 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1313 { 1314 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1315 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1316 struct ixgbe_hw *hw; 1317 int retries = 0; 1318 int ret; 1319 1320 PMD_INIT_FUNC_TRACE(); 1321 1322 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1323 return 0; 1324 1325 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1326 1327 if (hw->adapter_stopped == 0) 1328 ixgbe_dev_close(eth_dev); 1329 1330 eth_dev->dev_ops = NULL; 1331 eth_dev->rx_pkt_burst = NULL; 1332 eth_dev->tx_pkt_burst = NULL; 1333 1334 /* Unlock any pending hardware semaphore */ 1335 ixgbe_swfw_lock_reset(hw); 1336 1337 /* disable uio intr before callback unregister */ 1338 rte_intr_disable(intr_handle); 1339 1340 do { 1341 ret = rte_intr_callback_unregister(intr_handle, 1342 ixgbe_dev_interrupt_handler, eth_dev); 1343 if (ret >= 0) { 1344 break; 1345 } else if (ret != -EAGAIN) { 1346 PMD_INIT_LOG(ERR, 1347 "intr callback unregister failed: %d", 1348 ret); 1349 return ret; 1350 } 1351 rte_delay_ms(100); 1352 } while (retries++ < (10 + IXGBE_LINK_UP_TIME)); 1353 1354 /* cancel the delay handler before remove dev */ 1355 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, eth_dev); 1356 1357 /* cancel the link handler before remove dev */ 1358 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, eth_dev); 1359 1360 /* uninitialize PF if max_vfs not zero */ 1361 ixgbe_pf_host_uninit(eth_dev); 1362 1363 /* remove all the fdir filters & hash */ 1364 ixgbe_fdir_filter_uninit(eth_dev); 1365 1366 /* remove all the L2 tunnel filters & hash */ 1367 ixgbe_l2_tn_filter_uninit(eth_dev); 1368 1369 /* Remove all ntuple filters of the device */ 1370 ixgbe_ntuple_filter_uninit(eth_dev); 1371 1372 /* clear all the filters list */ 1373 ixgbe_filterlist_flush(); 1374 1375 /* Remove all Traffic Manager configuration */ 1376 ixgbe_tm_conf_uninit(eth_dev); 1377 1378 #ifdef RTE_LIBRTE_SECURITY 1379 rte_free(eth_dev->security_ctx); 1380 #endif 1381 1382 return 0; 1383 } 1384 1385 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev) 1386 { 1387 struct ixgbe_filter_info *filter_info = 1388 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1389 struct ixgbe_5tuple_filter *p_5tuple; 1390 1391 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) { 1392 TAILQ_REMOVE(&filter_info->fivetuple_list, 1393 p_5tuple, 1394 entries); 1395 rte_free(p_5tuple); 1396 } 1397 memset(filter_info->fivetuple_mask, 0, 1398 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE); 1399 1400 return 0; 1401 } 1402 1403 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev) 1404 { 1405 struct ixgbe_hw_fdir_info *fdir_info = 1406 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1407 struct ixgbe_fdir_filter *fdir_filter; 1408 1409 if (fdir_info->hash_map) 1410 rte_free(fdir_info->hash_map); 1411 if (fdir_info->hash_handle) 1412 rte_hash_free(fdir_info->hash_handle); 1413 1414 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 1415 TAILQ_REMOVE(&fdir_info->fdir_list, 1416 fdir_filter, 1417 entries); 1418 rte_free(fdir_filter); 1419 } 1420 1421 return 0; 1422 } 1423 1424 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev) 1425 { 1426 struct ixgbe_l2_tn_info *l2_tn_info = 1427 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1428 struct ixgbe_l2_tn_filter *l2_tn_filter; 1429 1430 if (l2_tn_info->hash_map) 1431 rte_free(l2_tn_info->hash_map); 1432 if (l2_tn_info->hash_handle) 1433 rte_hash_free(l2_tn_info->hash_handle); 1434 1435 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 1436 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, 1437 l2_tn_filter, 1438 entries); 1439 rte_free(l2_tn_filter); 1440 } 1441 1442 return 0; 1443 } 1444 1445 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev) 1446 { 1447 struct ixgbe_hw_fdir_info *fdir_info = 1448 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1449 char fdir_hash_name[RTE_HASH_NAMESIZE]; 1450 struct rte_hash_parameters fdir_hash_params = { 1451 .name = fdir_hash_name, 1452 .entries = IXGBE_MAX_FDIR_FILTER_NUM, 1453 .key_len = sizeof(union ixgbe_atr_input), 1454 .hash_func = rte_hash_crc, 1455 .hash_func_init_val = 0, 1456 .socket_id = rte_socket_id(), 1457 }; 1458 1459 TAILQ_INIT(&fdir_info->fdir_list); 1460 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 1461 "fdir_%s", eth_dev->device->name); 1462 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params); 1463 if (!fdir_info->hash_handle) { 1464 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 1465 return -EINVAL; 1466 } 1467 fdir_info->hash_map = rte_zmalloc("ixgbe", 1468 sizeof(struct ixgbe_fdir_filter *) * 1469 IXGBE_MAX_FDIR_FILTER_NUM, 1470 0); 1471 if (!fdir_info->hash_map) { 1472 PMD_INIT_LOG(ERR, 1473 "Failed to allocate memory for fdir hash map!"); 1474 return -ENOMEM; 1475 } 1476 fdir_info->mask_added = FALSE; 1477 1478 return 0; 1479 } 1480 1481 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) 1482 { 1483 struct ixgbe_l2_tn_info *l2_tn_info = 1484 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1485 char l2_tn_hash_name[RTE_HASH_NAMESIZE]; 1486 struct rte_hash_parameters l2_tn_hash_params = { 1487 .name = l2_tn_hash_name, 1488 .entries = IXGBE_MAX_L2_TN_FILTER_NUM, 1489 .key_len = sizeof(struct ixgbe_l2_tn_key), 1490 .hash_func = rte_hash_crc, 1491 .hash_func_init_val = 0, 1492 .socket_id = rte_socket_id(), 1493 }; 1494 1495 TAILQ_INIT(&l2_tn_info->l2_tn_list); 1496 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE, 1497 "l2_tn_%s", eth_dev->device->name); 1498 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params); 1499 if (!l2_tn_info->hash_handle) { 1500 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!"); 1501 return -EINVAL; 1502 } 1503 l2_tn_info->hash_map = rte_zmalloc("ixgbe", 1504 sizeof(struct ixgbe_l2_tn_filter *) * 1505 IXGBE_MAX_L2_TN_FILTER_NUM, 1506 0); 1507 if (!l2_tn_info->hash_map) { 1508 PMD_INIT_LOG(ERR, 1509 "Failed to allocate memory for L2 TN hash map!"); 1510 return -ENOMEM; 1511 } 1512 l2_tn_info->e_tag_en = FALSE; 1513 l2_tn_info->e_tag_fwd_en = FALSE; 1514 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG; 1515 1516 return 0; 1517 } 1518 /* 1519 * Negotiate mailbox API version with the PF. 1520 * After reset API version is always set to the basic one (ixgbe_mbox_api_10). 1521 * Then we try to negotiate starting with the most recent one. 1522 * If all negotiation attempts fail, then we will proceed with 1523 * the default one (ixgbe_mbox_api_10). 1524 */ 1525 static void 1526 ixgbevf_negotiate_api(struct ixgbe_hw *hw) 1527 { 1528 int32_t i; 1529 1530 /* start with highest supported, proceed down */ 1531 static const enum ixgbe_pfvf_api_rev sup_ver[] = { 1532 ixgbe_mbox_api_13, 1533 ixgbe_mbox_api_12, 1534 ixgbe_mbox_api_11, 1535 ixgbe_mbox_api_10, 1536 }; 1537 1538 for (i = 0; 1539 i != RTE_DIM(sup_ver) && 1540 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0; 1541 i++) 1542 ; 1543 } 1544 1545 static void 1546 generate_random_mac_addr(struct rte_ether_addr *mac_addr) 1547 { 1548 uint64_t random; 1549 1550 /* Set Organizationally Unique Identifier (OUI) prefix. */ 1551 mac_addr->addr_bytes[0] = 0x00; 1552 mac_addr->addr_bytes[1] = 0x09; 1553 mac_addr->addr_bytes[2] = 0xC0; 1554 /* Force indication of locally assigned MAC address. */ 1555 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR; 1556 /* Generate the last 3 bytes of the MAC address with a random number. */ 1557 random = rte_rand(); 1558 memcpy(&mac_addr->addr_bytes[3], &random, 3); 1559 } 1560 1561 static int 1562 devarg_handle_int(__rte_unused const char *key, const char *value, 1563 void *extra_args) 1564 { 1565 uint16_t *n = extra_args; 1566 1567 if (value == NULL || extra_args == NULL) 1568 return -EINVAL; 1569 1570 *n = (uint16_t)strtoul(value, NULL, 0); 1571 if (*n == USHRT_MAX && errno == ERANGE) 1572 return -1; 1573 1574 return 0; 1575 } 1576 1577 static void 1578 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter, 1579 struct rte_devargs *devargs) 1580 { 1581 struct rte_kvargs *kvlist; 1582 uint16_t pflink_fullchk; 1583 1584 if (devargs == NULL) 1585 return; 1586 1587 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments); 1588 if (kvlist == NULL) 1589 return; 1590 1591 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 && 1592 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK, 1593 devarg_handle_int, &pflink_fullchk) == 0 && 1594 pflink_fullchk == 1) 1595 adapter->pflink_fullchk = 1; 1596 1597 rte_kvargs_free(kvlist); 1598 } 1599 1600 /* 1601 * Virtual Function device init 1602 */ 1603 static int 1604 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev) 1605 { 1606 int diag; 1607 uint32_t tc, tcs; 1608 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1609 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1610 struct ixgbe_hw *hw = 1611 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1612 struct ixgbe_vfta *shadow_vfta = 1613 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1614 struct ixgbe_hwstrip *hwstrip = 1615 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1616 struct rte_ether_addr *perm_addr = 1617 (struct rte_ether_addr *)hw->mac.perm_addr; 1618 1619 PMD_INIT_FUNC_TRACE(); 1620 1621 eth_dev->dev_ops = &ixgbevf_eth_dev_ops; 1622 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1623 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1624 1625 /* for secondary processes, we don't initialise any further as primary 1626 * has already done this work. Only check we don't need a different 1627 * RX function 1628 */ 1629 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1630 struct ixgbe_tx_queue *txq; 1631 /* TX queue function in primary, set by last queue initialized 1632 * Tx queue may not initialized by primary process 1633 */ 1634 if (eth_dev->data->tx_queues) { 1635 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1]; 1636 ixgbe_set_tx_function(eth_dev, txq); 1637 } else { 1638 /* Use default TX function if we get here */ 1639 PMD_INIT_LOG(NOTICE, 1640 "No TX queues configured yet. Using default TX function."); 1641 } 1642 1643 ixgbe_set_rx_function(eth_dev); 1644 1645 return 0; 1646 } 1647 1648 ixgbevf_parse_devargs(eth_dev->data->dev_private, 1649 pci_dev->device.devargs); 1650 1651 rte_eth_copy_pci_info(eth_dev, pci_dev); 1652 1653 hw->device_id = pci_dev->id.device_id; 1654 hw->vendor_id = pci_dev->id.vendor_id; 1655 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1656 1657 /* initialize the vfta */ 1658 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1659 1660 /* initialize the hw strip bitmap*/ 1661 memset(hwstrip, 0, sizeof(*hwstrip)); 1662 1663 /* Initialize the shared code (base driver) */ 1664 diag = ixgbe_init_shared_code(hw); 1665 if (diag != IXGBE_SUCCESS) { 1666 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag); 1667 return -EIO; 1668 } 1669 1670 /* init_mailbox_params */ 1671 hw->mbx.ops.init_params(hw); 1672 1673 /* Reset the hw statistics */ 1674 ixgbevf_dev_stats_reset(eth_dev); 1675 1676 /* Disable the interrupts for VF */ 1677 ixgbevf_intr_disable(eth_dev); 1678 1679 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */ 1680 diag = hw->mac.ops.reset_hw(hw); 1681 1682 /* 1683 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when 1684 * the underlying PF driver has not assigned a MAC address to the VF. 1685 * In this case, assign a random MAC address. 1686 */ 1687 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) { 1688 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1689 /* 1690 * This error code will be propagated to the app by 1691 * rte_eth_dev_reset, so use a public error code rather than 1692 * the internal-only IXGBE_ERR_RESET_FAILED 1693 */ 1694 return -EAGAIN; 1695 } 1696 1697 /* negotiate mailbox API version to use with the PF. */ 1698 ixgbevf_negotiate_api(hw); 1699 1700 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */ 1701 ixgbevf_get_queues(hw, &tcs, &tc); 1702 1703 /* Allocate memory for storing MAC addresses */ 1704 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN * 1705 hw->mac.num_rar_entries, 0); 1706 if (eth_dev->data->mac_addrs == NULL) { 1707 PMD_INIT_LOG(ERR, 1708 "Failed to allocate %u bytes needed to store " 1709 "MAC addresses", 1710 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1711 return -ENOMEM; 1712 } 1713 1714 /* Generate a random MAC address, if none was assigned by PF. */ 1715 if (rte_is_zero_ether_addr(perm_addr)) { 1716 generate_random_mac_addr(perm_addr); 1717 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1); 1718 if (diag) { 1719 rte_free(eth_dev->data->mac_addrs); 1720 eth_dev->data->mac_addrs = NULL; 1721 return diag; 1722 } 1723 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF"); 1724 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address " 1725 "%02x:%02x:%02x:%02x:%02x:%02x", 1726 perm_addr->addr_bytes[0], 1727 perm_addr->addr_bytes[1], 1728 perm_addr->addr_bytes[2], 1729 perm_addr->addr_bytes[3], 1730 perm_addr->addr_bytes[4], 1731 perm_addr->addr_bytes[5]); 1732 } 1733 1734 /* Copy the permanent MAC address */ 1735 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]); 1736 1737 /* reset the hardware with the new settings */ 1738 diag = hw->mac.ops.start_hw(hw); 1739 switch (diag) { 1740 case 0: 1741 break; 1742 1743 default: 1744 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1745 return -EIO; 1746 } 1747 1748 rte_intr_callback_register(intr_handle, 1749 ixgbevf_dev_interrupt_handler, eth_dev); 1750 rte_intr_enable(intr_handle); 1751 ixgbevf_intr_enable(eth_dev); 1752 1753 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s", 1754 eth_dev->data->port_id, pci_dev->id.vendor_id, 1755 pci_dev->id.device_id, "ixgbe_mac_82599_vf"); 1756 1757 return 0; 1758 } 1759 1760 /* Virtual Function device uninit */ 1761 1762 static int 1763 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev) 1764 { 1765 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1766 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1767 struct ixgbe_hw *hw; 1768 1769 PMD_INIT_FUNC_TRACE(); 1770 1771 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1772 return 0; 1773 1774 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1775 1776 if (hw->adapter_stopped == 0) 1777 ixgbevf_dev_close(eth_dev); 1778 1779 eth_dev->dev_ops = NULL; 1780 eth_dev->rx_pkt_burst = NULL; 1781 eth_dev->tx_pkt_burst = NULL; 1782 1783 /* Disable the interrupts for VF */ 1784 ixgbevf_intr_disable(eth_dev); 1785 1786 rte_intr_disable(intr_handle); 1787 rte_intr_callback_unregister(intr_handle, 1788 ixgbevf_dev_interrupt_handler, eth_dev); 1789 1790 return 0; 1791 } 1792 1793 static int 1794 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1795 struct rte_pci_device *pci_dev) 1796 { 1797 char name[RTE_ETH_NAME_MAX_LEN]; 1798 struct rte_eth_dev *pf_ethdev; 1799 struct rte_eth_devargs eth_da; 1800 int i, retval; 1801 1802 if (pci_dev->device.devargs) { 1803 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 1804 ð_da); 1805 if (retval) 1806 return retval; 1807 } else 1808 memset(ð_da, 0, sizeof(eth_da)); 1809 1810 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 1811 sizeof(struct ixgbe_adapter), 1812 eth_dev_pci_specific_init, pci_dev, 1813 eth_ixgbe_dev_init, NULL); 1814 1815 if (retval || eth_da.nb_representor_ports < 1) 1816 return retval; 1817 1818 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1819 if (pf_ethdev == NULL) 1820 return -ENODEV; 1821 1822 /* probe VF representor ports */ 1823 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1824 struct ixgbe_vf_info *vfinfo; 1825 struct ixgbe_vf_representor representor; 1826 1827 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA( 1828 pf_ethdev->data->dev_private); 1829 if (vfinfo == NULL) { 1830 PMD_DRV_LOG(ERR, 1831 "no virtual functions supported by PF"); 1832 break; 1833 } 1834 1835 representor.vf_id = eth_da.representor_ports[i]; 1836 representor.switch_domain_id = vfinfo->switch_domain_id; 1837 representor.pf_ethdev = pf_ethdev; 1838 1839 /* representor port net_bdf_port */ 1840 snprintf(name, sizeof(name), "net_%s_representor_%d", 1841 pci_dev->device.name, 1842 eth_da.representor_ports[i]); 1843 1844 retval = rte_eth_dev_create(&pci_dev->device, name, 1845 sizeof(struct ixgbe_vf_representor), NULL, NULL, 1846 ixgbe_vf_representor_init, &representor); 1847 1848 if (retval) 1849 PMD_DRV_LOG(ERR, "failed to create ixgbe vf " 1850 "representor %s.", name); 1851 } 1852 1853 return 0; 1854 } 1855 1856 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev) 1857 { 1858 struct rte_eth_dev *ethdev; 1859 1860 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1861 if (!ethdev) 1862 return -ENODEV; 1863 1864 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 1865 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit); 1866 else 1867 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit); 1868 } 1869 1870 static struct rte_pci_driver rte_ixgbe_pmd = { 1871 .id_table = pci_id_ixgbe_map, 1872 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 1873 RTE_PCI_DRV_IOVA_AS_VA, 1874 .probe = eth_ixgbe_pci_probe, 1875 .remove = eth_ixgbe_pci_remove, 1876 }; 1877 1878 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1879 struct rte_pci_device *pci_dev) 1880 { 1881 return rte_eth_dev_pci_generic_probe(pci_dev, 1882 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init); 1883 } 1884 1885 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev) 1886 { 1887 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit); 1888 } 1889 1890 /* 1891 * virtual function driver struct 1892 */ 1893 static struct rte_pci_driver rte_ixgbevf_pmd = { 1894 .id_table = pci_id_ixgbevf_map, 1895 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA, 1896 .probe = eth_ixgbevf_pci_probe, 1897 .remove = eth_ixgbevf_pci_remove, 1898 }; 1899 1900 static int 1901 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1902 { 1903 struct ixgbe_hw *hw = 1904 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1905 struct ixgbe_vfta *shadow_vfta = 1906 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1907 uint32_t vfta; 1908 uint32_t vid_idx; 1909 uint32_t vid_bit; 1910 1911 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 1912 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 1913 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx)); 1914 if (on) 1915 vfta |= vid_bit; 1916 else 1917 vfta &= ~vid_bit; 1918 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta); 1919 1920 /* update local VFTA copy */ 1921 shadow_vfta->vfta[vid_idx] = vfta; 1922 1923 return 0; 1924 } 1925 1926 static void 1927 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 1928 { 1929 if (on) 1930 ixgbe_vlan_hw_strip_enable(dev, queue); 1931 else 1932 ixgbe_vlan_hw_strip_disable(dev, queue); 1933 } 1934 1935 static int 1936 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1937 enum rte_vlan_type vlan_type, 1938 uint16_t tpid) 1939 { 1940 struct ixgbe_hw *hw = 1941 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1942 int ret = 0; 1943 uint32_t reg; 1944 uint32_t qinq; 1945 1946 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1947 qinq &= IXGBE_DMATXCTL_GDV; 1948 1949 switch (vlan_type) { 1950 case ETH_VLAN_TYPE_INNER: 1951 if (qinq) { 1952 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1953 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1954 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1955 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1956 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1957 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1958 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1959 } else { 1960 ret = -ENOTSUP; 1961 PMD_DRV_LOG(ERR, "Inner type is not supported" 1962 " by single VLAN"); 1963 } 1964 break; 1965 case ETH_VLAN_TYPE_OUTER: 1966 if (qinq) { 1967 /* Only the high 16-bits is valid */ 1968 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid << 1969 IXGBE_EXVET_VET_EXT_SHIFT); 1970 } else { 1971 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1972 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1973 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1974 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1975 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1976 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1977 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1978 } 1979 1980 break; 1981 default: 1982 ret = -EINVAL; 1983 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type); 1984 break; 1985 } 1986 1987 return ret; 1988 } 1989 1990 void 1991 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev) 1992 { 1993 struct ixgbe_hw *hw = 1994 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1995 uint32_t vlnctrl; 1996 1997 PMD_INIT_FUNC_TRACE(); 1998 1999 /* Filter Table Disable */ 2000 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2001 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 2002 2003 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 2004 } 2005 2006 void 2007 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev) 2008 { 2009 struct ixgbe_hw *hw = 2010 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2011 struct ixgbe_vfta *shadow_vfta = 2012 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 2013 uint32_t vlnctrl; 2014 uint16_t i; 2015 2016 PMD_INIT_FUNC_TRACE(); 2017 2018 /* Filter Table Enable */ 2019 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2020 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; 2021 vlnctrl |= IXGBE_VLNCTRL_VFE; 2022 2023 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 2024 2025 /* write whatever is in local vfta copy */ 2026 for (i = 0; i < IXGBE_VFTA_SIZE; i++) 2027 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]); 2028 } 2029 2030 static void 2031 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on) 2032 { 2033 struct ixgbe_hwstrip *hwstrip = 2034 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private); 2035 struct ixgbe_rx_queue *rxq; 2036 2037 if (queue >= IXGBE_MAX_RX_QUEUE_NUM) 2038 return; 2039 2040 if (on) 2041 IXGBE_SET_HWSTRIP(hwstrip, queue); 2042 else 2043 IXGBE_CLEAR_HWSTRIP(hwstrip, queue); 2044 2045 if (queue >= dev->data->nb_rx_queues) 2046 return; 2047 2048 rxq = dev->data->rx_queues[queue]; 2049 2050 if (on) { 2051 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; 2052 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 2053 } else { 2054 rxq->vlan_flags = PKT_RX_VLAN; 2055 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 2056 } 2057 } 2058 2059 static void 2060 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue) 2061 { 2062 struct ixgbe_hw *hw = 2063 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2064 uint32_t ctrl; 2065 2066 PMD_INIT_FUNC_TRACE(); 2067 2068 if (hw->mac.type == ixgbe_mac_82598EB) { 2069 /* No queue level support */ 2070 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2071 return; 2072 } 2073 2074 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2075 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2076 ctrl &= ~IXGBE_RXDCTL_VME; 2077 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2078 2079 /* record those setting for HW strip per queue */ 2080 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0); 2081 } 2082 2083 static void 2084 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue) 2085 { 2086 struct ixgbe_hw *hw = 2087 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2088 uint32_t ctrl; 2089 2090 PMD_INIT_FUNC_TRACE(); 2091 2092 if (hw->mac.type == ixgbe_mac_82598EB) { 2093 /* No queue level supported */ 2094 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2095 return; 2096 } 2097 2098 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2099 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2100 ctrl |= IXGBE_RXDCTL_VME; 2101 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2102 2103 /* record those setting for HW strip per queue */ 2104 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1); 2105 } 2106 2107 static void 2108 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev) 2109 { 2110 struct ixgbe_hw *hw = 2111 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2112 uint32_t ctrl; 2113 2114 PMD_INIT_FUNC_TRACE(); 2115 2116 /* DMATXCTRL: Geric Double VLAN Disable */ 2117 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2118 ctrl &= ~IXGBE_DMATXCTL_GDV; 2119 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2120 2121 /* CTRL_EXT: Global Double VLAN Disable */ 2122 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2123 ctrl &= ~IXGBE_EXTENDED_VLAN; 2124 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2125 2126 } 2127 2128 static void 2129 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) 2130 { 2131 struct ixgbe_hw *hw = 2132 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2133 uint32_t ctrl; 2134 2135 PMD_INIT_FUNC_TRACE(); 2136 2137 /* DMATXCTRL: Geric Double VLAN Enable */ 2138 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2139 ctrl |= IXGBE_DMATXCTL_GDV; 2140 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2141 2142 /* CTRL_EXT: Global Double VLAN Enable */ 2143 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2144 ctrl |= IXGBE_EXTENDED_VLAN; 2145 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2146 2147 /* Clear pooling mode of PFVTCTL. It's required by X550. */ 2148 if (hw->mac.type == ixgbe_mac_X550 || 2149 hw->mac.type == ixgbe_mac_X550EM_x || 2150 hw->mac.type == ixgbe_mac_X550EM_a) { 2151 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 2152 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 2153 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 2154 } 2155 2156 /* 2157 * VET EXT field in the EXVET register = 0x8100 by default 2158 * So no need to change. Same to VT field of DMATXCTL register 2159 */ 2160 } 2161 2162 void 2163 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev) 2164 { 2165 struct ixgbe_hw *hw = 2166 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2167 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 2168 uint32_t ctrl; 2169 uint16_t i; 2170 struct ixgbe_rx_queue *rxq; 2171 bool on; 2172 2173 PMD_INIT_FUNC_TRACE(); 2174 2175 if (hw->mac.type == ixgbe_mac_82598EB) { 2176 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2177 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2178 ctrl |= IXGBE_VLNCTRL_VME; 2179 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2180 } else { 2181 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2182 ctrl &= ~IXGBE_VLNCTRL_VME; 2183 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2184 } 2185 } else { 2186 /* 2187 * Other 10G NIC, the VLAN strip can be setup 2188 * per queue in RXDCTL 2189 */ 2190 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2191 rxq = dev->data->rx_queues[i]; 2192 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx)); 2193 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2194 ctrl |= IXGBE_RXDCTL_VME; 2195 on = TRUE; 2196 } else { 2197 ctrl &= ~IXGBE_RXDCTL_VME; 2198 on = FALSE; 2199 } 2200 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl); 2201 2202 /* record those setting for HW strip per queue */ 2203 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on); 2204 } 2205 } 2206 } 2207 2208 static void 2209 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask) 2210 { 2211 uint16_t i; 2212 struct rte_eth_rxmode *rxmode; 2213 struct ixgbe_rx_queue *rxq; 2214 2215 if (mask & ETH_VLAN_STRIP_MASK) { 2216 rxmode = &dev->data->dev_conf.rxmode; 2217 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 2218 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2219 rxq = dev->data->rx_queues[i]; 2220 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 2221 } 2222 else 2223 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2224 rxq = dev->data->rx_queues[i]; 2225 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 2226 } 2227 } 2228 } 2229 2230 static int 2231 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask) 2232 { 2233 struct rte_eth_rxmode *rxmode; 2234 rxmode = &dev->data->dev_conf.rxmode; 2235 2236 if (mask & ETH_VLAN_STRIP_MASK) { 2237 ixgbe_vlan_hw_strip_config(dev); 2238 } 2239 2240 if (mask & ETH_VLAN_FILTER_MASK) { 2241 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 2242 ixgbe_vlan_hw_filter_enable(dev); 2243 else 2244 ixgbe_vlan_hw_filter_disable(dev); 2245 } 2246 2247 if (mask & ETH_VLAN_EXTEND_MASK) { 2248 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2249 ixgbe_vlan_hw_extend_enable(dev); 2250 else 2251 ixgbe_vlan_hw_extend_disable(dev); 2252 } 2253 2254 return 0; 2255 } 2256 2257 static int 2258 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2259 { 2260 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 2261 2262 ixgbe_vlan_offload_config(dev, mask); 2263 2264 return 0; 2265 } 2266 2267 static void 2268 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev) 2269 { 2270 struct ixgbe_hw *hw = 2271 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2272 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */ 2273 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2274 2275 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */ 2276 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl); 2277 } 2278 2279 static int 2280 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q) 2281 { 2282 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2283 2284 switch (nb_rx_q) { 2285 case 1: 2286 case 2: 2287 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS; 2288 break; 2289 case 4: 2290 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS; 2291 break; 2292 default: 2293 return -EINVAL; 2294 } 2295 2296 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 2297 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2298 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 2299 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2300 return 0; 2301 } 2302 2303 static int 2304 ixgbe_check_mq_mode(struct rte_eth_dev *dev) 2305 { 2306 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 2307 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2308 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2309 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2310 2311 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 2312 /* check multi-queue mode */ 2313 switch (dev_conf->rxmode.mq_mode) { 2314 case ETH_MQ_RX_VMDQ_DCB: 2315 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV"); 2316 break; 2317 case ETH_MQ_RX_VMDQ_DCB_RSS: 2318 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */ 2319 PMD_INIT_LOG(ERR, "SRIOV active," 2320 " unsupported mq_mode rx %d.", 2321 dev_conf->rxmode.mq_mode); 2322 return -EINVAL; 2323 case ETH_MQ_RX_RSS: 2324 case ETH_MQ_RX_VMDQ_RSS: 2325 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS; 2326 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) 2327 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) { 2328 PMD_INIT_LOG(ERR, "SRIOV is active," 2329 " invalid queue number" 2330 " for VMDQ RSS, allowed" 2331 " value are 1, 2 or 4."); 2332 return -EINVAL; 2333 } 2334 break; 2335 case ETH_MQ_RX_VMDQ_ONLY: 2336 case ETH_MQ_RX_NONE: 2337 /* if nothing mq mode configure, use default scheme */ 2338 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY; 2339 break; 2340 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/ 2341 /* SRIOV only works in VMDq enable mode */ 2342 PMD_INIT_LOG(ERR, "SRIOV is active," 2343 " wrong mq_mode rx %d.", 2344 dev_conf->rxmode.mq_mode); 2345 return -EINVAL; 2346 } 2347 2348 switch (dev_conf->txmode.mq_mode) { 2349 case ETH_MQ_TX_VMDQ_DCB: 2350 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV"); 2351 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB; 2352 break; 2353 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */ 2354 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY; 2355 break; 2356 } 2357 2358 /* check valid queue number */ 2359 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) || 2360 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) { 2361 PMD_INIT_LOG(ERR, "SRIOV is active," 2362 " nb_rx_q=%d nb_tx_q=%d queue number" 2363 " must be less than or equal to %d.", 2364 nb_rx_q, nb_tx_q, 2365 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool); 2366 return -EINVAL; 2367 } 2368 } else { 2369 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) { 2370 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is" 2371 " not supported."); 2372 return -EINVAL; 2373 } 2374 /* check configuration for vmdb+dcb mode */ 2375 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) { 2376 const struct rte_eth_vmdq_dcb_conf *conf; 2377 2378 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2379 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.", 2380 IXGBE_VMDQ_DCB_NB_QUEUES); 2381 return -EINVAL; 2382 } 2383 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf; 2384 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2385 conf->nb_queue_pools == ETH_32_POOLS)) { 2386 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2387 " nb_queue_pools must be %d or %d.", 2388 ETH_16_POOLS, ETH_32_POOLS); 2389 return -EINVAL; 2390 } 2391 } 2392 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) { 2393 const struct rte_eth_vmdq_dcb_tx_conf *conf; 2394 2395 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2396 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d", 2397 IXGBE_VMDQ_DCB_NB_QUEUES); 2398 return -EINVAL; 2399 } 2400 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf; 2401 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2402 conf->nb_queue_pools == ETH_32_POOLS)) { 2403 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2404 " nb_queue_pools != %d and" 2405 " nb_queue_pools != %d.", 2406 ETH_16_POOLS, ETH_32_POOLS); 2407 return -EINVAL; 2408 } 2409 } 2410 2411 /* For DCB mode check our configuration before we go further */ 2412 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) { 2413 const struct rte_eth_dcb_rx_conf *conf; 2414 2415 conf = &dev_conf->rx_adv_conf.dcb_rx_conf; 2416 if (!(conf->nb_tcs == ETH_4_TCS || 2417 conf->nb_tcs == ETH_8_TCS)) { 2418 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2419 " and nb_tcs != %d.", 2420 ETH_4_TCS, ETH_8_TCS); 2421 return -EINVAL; 2422 } 2423 } 2424 2425 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) { 2426 const struct rte_eth_dcb_tx_conf *conf; 2427 2428 conf = &dev_conf->tx_adv_conf.dcb_tx_conf; 2429 if (!(conf->nb_tcs == ETH_4_TCS || 2430 conf->nb_tcs == ETH_8_TCS)) { 2431 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2432 " and nb_tcs != %d.", 2433 ETH_4_TCS, ETH_8_TCS); 2434 return -EINVAL; 2435 } 2436 } 2437 2438 /* 2439 * When DCB/VT is off, maximum number of queues changes, 2440 * except for 82598EB, which remains constant. 2441 */ 2442 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 2443 hw->mac.type != ixgbe_mac_82598EB) { 2444 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) { 2445 PMD_INIT_LOG(ERR, 2446 "Neither VT nor DCB are enabled, " 2447 "nb_tx_q > %d.", 2448 IXGBE_NONE_MODE_TX_NB_QUEUES); 2449 return -EINVAL; 2450 } 2451 } 2452 } 2453 return 0; 2454 } 2455 2456 static int 2457 ixgbe_dev_configure(struct rte_eth_dev *dev) 2458 { 2459 struct ixgbe_interrupt *intr = 2460 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2461 struct ixgbe_adapter *adapter = dev->data->dev_private; 2462 int ret; 2463 2464 PMD_INIT_FUNC_TRACE(); 2465 /* multipe queue mode checking */ 2466 ret = ixgbe_check_mq_mode(dev); 2467 if (ret != 0) { 2468 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.", 2469 ret); 2470 return ret; 2471 } 2472 2473 /* set flag to update link status after init */ 2474 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2475 2476 /* 2477 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 2478 * allocation or vector Rx preconditions we will reset it. 2479 */ 2480 adapter->rx_bulk_alloc_allowed = true; 2481 adapter->rx_vec_allowed = true; 2482 2483 return 0; 2484 } 2485 2486 static void 2487 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) 2488 { 2489 struct ixgbe_hw *hw = 2490 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2491 struct ixgbe_interrupt *intr = 2492 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2493 uint32_t gpie; 2494 2495 /* only set up it on X550EM_X */ 2496 if (hw->mac.type == ixgbe_mac_X550EM_x) { 2497 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 2498 gpie |= IXGBE_SDP0_GPIEN_X550EM_x; 2499 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 2500 if (hw->phy.type == ixgbe_phy_x550em_ext_t) 2501 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x; 2502 } 2503 } 2504 2505 int 2506 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 2507 uint16_t tx_rate, uint64_t q_msk) 2508 { 2509 struct ixgbe_hw *hw; 2510 struct ixgbe_vf_info *vfinfo; 2511 struct rte_eth_link link; 2512 uint8_t nb_q_per_pool; 2513 uint32_t queue_stride; 2514 uint32_t queue_idx, idx = 0, vf_idx; 2515 uint32_t queue_end; 2516 uint16_t total_rate = 0; 2517 struct rte_pci_device *pci_dev; 2518 2519 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2520 rte_eth_link_get_nowait(dev->data->port_id, &link); 2521 2522 if (vf >= pci_dev->max_vfs) 2523 return -EINVAL; 2524 2525 if (tx_rate > link.link_speed) 2526 return -EINVAL; 2527 2528 if (q_msk == 0) 2529 return 0; 2530 2531 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2532 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 2533 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2534 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2535 queue_idx = vf * queue_stride; 2536 queue_end = queue_idx + nb_q_per_pool - 1; 2537 if (queue_end >= hw->mac.max_tx_queues) 2538 return -EINVAL; 2539 2540 if (vfinfo) { 2541 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) { 2542 if (vf_idx == vf) 2543 continue; 2544 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate); 2545 idx++) 2546 total_rate += vfinfo[vf_idx].tx_rate[idx]; 2547 } 2548 } else { 2549 return -EINVAL; 2550 } 2551 2552 /* Store tx_rate for this vf. */ 2553 for (idx = 0; idx < nb_q_per_pool; idx++) { 2554 if (((uint64_t)0x1 << idx) & q_msk) { 2555 if (vfinfo[vf].tx_rate[idx] != tx_rate) 2556 vfinfo[vf].tx_rate[idx] = tx_rate; 2557 total_rate += tx_rate; 2558 } 2559 } 2560 2561 if (total_rate > dev->data->dev_link.link_speed) { 2562 /* Reset stored TX rate of the VF if it causes exceed 2563 * link speed. 2564 */ 2565 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate)); 2566 return -EINVAL; 2567 } 2568 2569 /* Set RTTBCNRC of each queue/pool for vf X */ 2570 for (; queue_idx <= queue_end; queue_idx++) { 2571 if (0x1 & q_msk) 2572 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate); 2573 q_msk = q_msk >> 1; 2574 } 2575 2576 return 0; 2577 } 2578 2579 /* 2580 * Configure device link speed and setup link. 2581 * It returns 0 on success. 2582 */ 2583 static int 2584 ixgbe_dev_start(struct rte_eth_dev *dev) 2585 { 2586 struct ixgbe_hw *hw = 2587 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2588 struct ixgbe_vf_info *vfinfo = 2589 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2590 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2591 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2592 uint32_t intr_vector = 0; 2593 int err, link_up = 0, negotiate = 0; 2594 uint32_t speed = 0; 2595 uint32_t allowed_speeds = 0; 2596 int mask = 0; 2597 int status; 2598 uint16_t vf, idx; 2599 uint32_t *link_speeds; 2600 struct ixgbe_tm_conf *tm_conf = 2601 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2602 2603 PMD_INIT_FUNC_TRACE(); 2604 2605 /* IXGBE devices don't support: 2606 * - half duplex (checked afterwards for valid speeds) 2607 * - fixed speed: TODO implement 2608 */ 2609 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) { 2610 PMD_INIT_LOG(ERR, 2611 "Invalid link_speeds for port %u, fix speed not supported", 2612 dev->data->port_id); 2613 return -EINVAL; 2614 } 2615 2616 /* Stop the link setup handler before resetting the HW. */ 2617 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 2618 2619 /* disable uio/vfio intr/eventfd mapping */ 2620 rte_intr_disable(intr_handle); 2621 2622 /* stop adapter */ 2623 hw->adapter_stopped = 0; 2624 ixgbe_stop_adapter(hw); 2625 2626 /* reinitialize adapter 2627 * this calls reset and start 2628 */ 2629 status = ixgbe_pf_reset_hw(hw); 2630 if (status != 0) 2631 return -1; 2632 hw->mac.ops.start_hw(hw); 2633 hw->mac.get_link_status = true; 2634 2635 /* configure PF module if SRIOV enabled */ 2636 ixgbe_pf_host_configure(dev); 2637 2638 ixgbe_dev_phy_intr_setup(dev); 2639 2640 /* check and configure queue intr-vector mapping */ 2641 if ((rte_intr_cap_multiple(intr_handle) || 2642 !RTE_ETH_DEV_SRIOV(dev).active) && 2643 dev->data->dev_conf.intr_conf.rxq != 0) { 2644 intr_vector = dev->data->nb_rx_queues; 2645 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) { 2646 PMD_INIT_LOG(ERR, "At most %d intr queues supported", 2647 IXGBE_MAX_INTR_QUEUE_NUM); 2648 return -ENOTSUP; 2649 } 2650 if (rte_intr_efd_enable(intr_handle, intr_vector)) 2651 return -1; 2652 } 2653 2654 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 2655 intr_handle->intr_vec = 2656 rte_zmalloc("intr_vec", 2657 dev->data->nb_rx_queues * sizeof(int), 0); 2658 if (intr_handle->intr_vec == NULL) { 2659 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 2660 " intr_vec", dev->data->nb_rx_queues); 2661 return -ENOMEM; 2662 } 2663 } 2664 2665 /* confiugre msix for sleep until rx interrupt */ 2666 ixgbe_configure_msix(dev); 2667 2668 /* initialize transmission unit */ 2669 ixgbe_dev_tx_init(dev); 2670 2671 /* This can fail when allocating mbufs for descriptor rings */ 2672 err = ixgbe_dev_rx_init(dev); 2673 if (err) { 2674 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 2675 goto error; 2676 } 2677 2678 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 2679 ETH_VLAN_EXTEND_MASK; 2680 err = ixgbe_vlan_offload_config(dev, mask); 2681 if (err) { 2682 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 2683 goto error; 2684 } 2685 2686 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) { 2687 /* Enable vlan filtering for VMDq */ 2688 ixgbe_vmdq_vlan_hw_filter_enable(dev); 2689 } 2690 2691 /* Configure DCB hw */ 2692 ixgbe_configure_dcb(dev); 2693 2694 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) { 2695 err = ixgbe_fdir_configure(dev); 2696 if (err) 2697 goto error; 2698 } 2699 2700 /* Restore vf rate limit */ 2701 if (vfinfo != NULL) { 2702 for (vf = 0; vf < pci_dev->max_vfs; vf++) 2703 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++) 2704 if (vfinfo[vf].tx_rate[idx] != 0) 2705 ixgbe_set_vf_rate_limit( 2706 dev, vf, 2707 vfinfo[vf].tx_rate[idx], 2708 1 << idx); 2709 } 2710 2711 ixgbe_restore_statistics_mapping(dev); 2712 2713 err = ixgbe_dev_rxtx_start(dev); 2714 if (err < 0) { 2715 PMD_INIT_LOG(ERR, "Unable to start rxtx queues"); 2716 goto error; 2717 } 2718 2719 /* Skip link setup if loopback mode is enabled. */ 2720 if (dev->data->dev_conf.lpbk_mode != 0) { 2721 err = ixgbe_check_supported_loopback_mode(dev); 2722 if (err < 0) { 2723 PMD_INIT_LOG(ERR, "Unsupported loopback mode"); 2724 goto error; 2725 } else { 2726 goto skip_link_setup; 2727 } 2728 } 2729 2730 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) { 2731 err = hw->mac.ops.setup_sfp(hw); 2732 if (err) 2733 goto error; 2734 } 2735 2736 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2737 /* Turn on the copper */ 2738 ixgbe_set_phy_power(hw, true); 2739 } else { 2740 /* Turn on the laser */ 2741 ixgbe_enable_tx_laser(hw); 2742 } 2743 2744 err = ixgbe_check_link(hw, &speed, &link_up, 0); 2745 if (err) 2746 goto error; 2747 dev->data->dev_link.link_status = link_up; 2748 2749 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate); 2750 if (err) 2751 goto error; 2752 2753 switch (hw->mac.type) { 2754 case ixgbe_mac_X550: 2755 case ixgbe_mac_X550EM_x: 2756 case ixgbe_mac_X550EM_a: 2757 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2758 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G | 2759 ETH_LINK_SPEED_10G; 2760 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 2761 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 2762 allowed_speeds = ETH_LINK_SPEED_10M | 2763 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G; 2764 break; 2765 default: 2766 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2767 ETH_LINK_SPEED_10G; 2768 } 2769 2770 link_speeds = &dev->data->dev_conf.link_speeds; 2771 if (*link_speeds & ~allowed_speeds) { 2772 PMD_INIT_LOG(ERR, "Invalid link setting"); 2773 goto error; 2774 } 2775 2776 speed = 0x0; 2777 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) { 2778 switch (hw->mac.type) { 2779 case ixgbe_mac_82598EB: 2780 speed = IXGBE_LINK_SPEED_82598_AUTONEG; 2781 break; 2782 case ixgbe_mac_82599EB: 2783 case ixgbe_mac_X540: 2784 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2785 break; 2786 case ixgbe_mac_X550: 2787 case ixgbe_mac_X550EM_x: 2788 case ixgbe_mac_X550EM_a: 2789 speed = IXGBE_LINK_SPEED_X550_AUTONEG; 2790 break; 2791 default: 2792 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2793 } 2794 } else { 2795 if (*link_speeds & ETH_LINK_SPEED_10G) 2796 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2797 if (*link_speeds & ETH_LINK_SPEED_5G) 2798 speed |= IXGBE_LINK_SPEED_5GB_FULL; 2799 if (*link_speeds & ETH_LINK_SPEED_2_5G) 2800 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 2801 if (*link_speeds & ETH_LINK_SPEED_1G) 2802 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2803 if (*link_speeds & ETH_LINK_SPEED_100M) 2804 speed |= IXGBE_LINK_SPEED_100_FULL; 2805 if (*link_speeds & ETH_LINK_SPEED_10M) 2806 speed |= IXGBE_LINK_SPEED_10_FULL; 2807 } 2808 2809 err = ixgbe_setup_link(hw, speed, link_up); 2810 if (err) 2811 goto error; 2812 2813 skip_link_setup: 2814 2815 if (rte_intr_allow_others(intr_handle)) { 2816 /* check if lsc interrupt is enabled */ 2817 if (dev->data->dev_conf.intr_conf.lsc != 0) 2818 ixgbe_dev_lsc_interrupt_setup(dev, TRUE); 2819 else 2820 ixgbe_dev_lsc_interrupt_setup(dev, FALSE); 2821 ixgbe_dev_macsec_interrupt_setup(dev); 2822 } else { 2823 rte_intr_callback_unregister(intr_handle, 2824 ixgbe_dev_interrupt_handler, dev); 2825 if (dev->data->dev_conf.intr_conf.lsc != 0) 2826 PMD_INIT_LOG(INFO, "lsc won't enable because of" 2827 " no intr multiplex"); 2828 } 2829 2830 /* check if rxq interrupt is enabled */ 2831 if (dev->data->dev_conf.intr_conf.rxq != 0 && 2832 rte_intr_dp_is_en(intr_handle)) 2833 ixgbe_dev_rxq_interrupt_setup(dev); 2834 2835 /* enable uio/vfio intr/eventfd mapping */ 2836 rte_intr_enable(intr_handle); 2837 2838 /* resume enabled intr since hw reset */ 2839 ixgbe_enable_intr(dev); 2840 ixgbe_l2_tunnel_conf(dev); 2841 ixgbe_filter_restore(dev); 2842 2843 if (tm_conf->root && !tm_conf->committed) 2844 PMD_DRV_LOG(WARNING, 2845 "please call hierarchy_commit() " 2846 "before starting the port"); 2847 2848 /* 2849 * Update link status right before return, because it may 2850 * start link configuration process in a separate thread. 2851 */ 2852 ixgbe_dev_link_update(dev, 0); 2853 2854 return 0; 2855 2856 error: 2857 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err); 2858 ixgbe_dev_clear_queues(dev); 2859 return -EIO; 2860 } 2861 2862 /* 2863 * Stop device: disable rx and tx functions to allow for reconfiguring. 2864 */ 2865 static void 2866 ixgbe_dev_stop(struct rte_eth_dev *dev) 2867 { 2868 struct rte_eth_link link; 2869 struct ixgbe_adapter *adapter = dev->data->dev_private; 2870 struct ixgbe_hw *hw = 2871 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2872 struct ixgbe_vf_info *vfinfo = 2873 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2874 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2875 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2876 int vf; 2877 struct ixgbe_tm_conf *tm_conf = 2878 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2879 2880 PMD_INIT_FUNC_TRACE(); 2881 2882 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 2883 2884 /* disable interrupts */ 2885 ixgbe_disable_intr(hw); 2886 2887 /* reset the NIC */ 2888 ixgbe_pf_reset_hw(hw); 2889 hw->adapter_stopped = 0; 2890 2891 /* stop adapter */ 2892 ixgbe_stop_adapter(hw); 2893 2894 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++) 2895 vfinfo[vf].clear_to_send = false; 2896 2897 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2898 /* Turn off the copper */ 2899 ixgbe_set_phy_power(hw, false); 2900 } else { 2901 /* Turn off the laser */ 2902 ixgbe_disable_tx_laser(hw); 2903 } 2904 2905 ixgbe_dev_clear_queues(dev); 2906 2907 /* Clear stored conf */ 2908 dev->data->scattered_rx = 0; 2909 dev->data->lro = 0; 2910 2911 /* Clear recorded link status */ 2912 memset(&link, 0, sizeof(link)); 2913 rte_eth_linkstatus_set(dev, &link); 2914 2915 if (!rte_intr_allow_others(intr_handle)) 2916 /* resume to the default handler */ 2917 rte_intr_callback_register(intr_handle, 2918 ixgbe_dev_interrupt_handler, 2919 (void *)dev); 2920 2921 /* Clean datapath event and queue/vec mapping */ 2922 rte_intr_efd_disable(intr_handle); 2923 if (intr_handle->intr_vec != NULL) { 2924 rte_free(intr_handle->intr_vec); 2925 intr_handle->intr_vec = NULL; 2926 } 2927 2928 /* reset hierarchy commit */ 2929 tm_conf->committed = false; 2930 2931 adapter->rss_reta_updated = 0; 2932 } 2933 2934 /* 2935 * Set device link up: enable tx. 2936 */ 2937 static int 2938 ixgbe_dev_set_link_up(struct rte_eth_dev *dev) 2939 { 2940 struct ixgbe_hw *hw = 2941 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2942 if (hw->mac.type == ixgbe_mac_82599EB) { 2943 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2944 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2945 /* Not suported in bypass mode */ 2946 PMD_INIT_LOG(ERR, "Set link up is not supported " 2947 "by device id 0x%x", hw->device_id); 2948 return -ENOTSUP; 2949 } 2950 #endif 2951 } 2952 2953 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2954 /* Turn on the copper */ 2955 ixgbe_set_phy_power(hw, true); 2956 } else { 2957 /* Turn on the laser */ 2958 ixgbe_enable_tx_laser(hw); 2959 } 2960 2961 return 0; 2962 } 2963 2964 /* 2965 * Set device link down: disable tx. 2966 */ 2967 static int 2968 ixgbe_dev_set_link_down(struct rte_eth_dev *dev) 2969 { 2970 struct ixgbe_hw *hw = 2971 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2972 if (hw->mac.type == ixgbe_mac_82599EB) { 2973 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2974 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2975 /* Not suported in bypass mode */ 2976 PMD_INIT_LOG(ERR, "Set link down is not supported " 2977 "by device id 0x%x", hw->device_id); 2978 return -ENOTSUP; 2979 } 2980 #endif 2981 } 2982 2983 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2984 /* Turn off the copper */ 2985 ixgbe_set_phy_power(hw, false); 2986 } else { 2987 /* Turn off the laser */ 2988 ixgbe_disable_tx_laser(hw); 2989 } 2990 2991 return 0; 2992 } 2993 2994 /* 2995 * Reset and stop device. 2996 */ 2997 static void 2998 ixgbe_dev_close(struct rte_eth_dev *dev) 2999 { 3000 struct ixgbe_hw *hw = 3001 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3002 3003 PMD_INIT_FUNC_TRACE(); 3004 3005 ixgbe_pf_reset_hw(hw); 3006 3007 ixgbe_dev_stop(dev); 3008 hw->adapter_stopped = 1; 3009 3010 ixgbe_dev_free_queues(dev); 3011 3012 ixgbe_disable_pcie_master(hw); 3013 3014 /* reprogram the RAR[0] in case user changed it. */ 3015 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 3016 } 3017 3018 /* 3019 * Reset PF device. 3020 */ 3021 static int 3022 ixgbe_dev_reset(struct rte_eth_dev *dev) 3023 { 3024 int ret; 3025 3026 /* When a DPDK PMD PF begin to reset PF port, it should notify all 3027 * its VF to make them align with it. The detailed notification 3028 * mechanism is PMD specific. As to ixgbe PF, it is rather complex. 3029 * To avoid unexpected behavior in VF, currently reset of PF with 3030 * SR-IOV activation is not supported. It might be supported later. 3031 */ 3032 if (dev->data->sriov.active) 3033 return -ENOTSUP; 3034 3035 ret = eth_ixgbe_dev_uninit(dev); 3036 if (ret) 3037 return ret; 3038 3039 ret = eth_ixgbe_dev_init(dev, NULL); 3040 3041 return ret; 3042 } 3043 3044 static void 3045 ixgbe_read_stats_registers(struct ixgbe_hw *hw, 3046 struct ixgbe_hw_stats *hw_stats, 3047 struct ixgbe_macsec_stats *macsec_stats, 3048 uint64_t *total_missed_rx, uint64_t *total_qbrc, 3049 uint64_t *total_qprc, uint64_t *total_qprdc) 3050 { 3051 uint32_t bprc, lxon, lxoff, total; 3052 uint32_t delta_gprc = 0; 3053 unsigned i; 3054 /* Workaround for RX byte count not including CRC bytes when CRC 3055 * strip is enabled. CRC bytes are removed from counters when crc_strip 3056 * is disabled. 3057 */ 3058 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) & 3059 IXGBE_HLREG0_RXCRCSTRP); 3060 3061 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 3062 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC); 3063 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC); 3064 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC); 3065 3066 for (i = 0; i < 8; i++) { 3067 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 3068 3069 /* global total per queue */ 3070 hw_stats->mpc[i] += mp; 3071 /* Running comprehensive total for stats display */ 3072 *total_missed_rx += hw_stats->mpc[i]; 3073 if (hw->mac.type == ixgbe_mac_82598EB) { 3074 hw_stats->rnbc[i] += 3075 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 3076 hw_stats->pxonrxc[i] += 3077 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 3078 hw_stats->pxoffrxc[i] += 3079 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 3080 } else { 3081 hw_stats->pxonrxc[i] += 3082 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 3083 hw_stats->pxoffrxc[i] += 3084 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 3085 hw_stats->pxon2offc[i] += 3086 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 3087 } 3088 hw_stats->pxontxc[i] += 3089 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 3090 hw_stats->pxofftxc[i] += 3091 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 3092 } 3093 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3094 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 3095 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 3096 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 3097 3098 delta_gprc += delta_qprc; 3099 3100 hw_stats->qprc[i] += delta_qprc; 3101 hw_stats->qptc[i] += delta_qptc; 3102 3103 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 3104 hw_stats->qbrc[i] += 3105 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32); 3106 if (crc_strip == 0) 3107 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN; 3108 3109 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 3110 hw_stats->qbtc[i] += 3111 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32); 3112 3113 hw_stats->qprdc[i] += delta_qprdc; 3114 *total_qprdc += hw_stats->qprdc[i]; 3115 3116 *total_qprc += hw_stats->qprc[i]; 3117 *total_qbrc += hw_stats->qbrc[i]; 3118 } 3119 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC); 3120 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC); 3121 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 3122 3123 /* 3124 * An errata states that gprc actually counts good + missed packets: 3125 * Workaround to set gprc to summated queue packet receives 3126 */ 3127 hw_stats->gprc = *total_qprc; 3128 3129 if (hw->mac.type != ixgbe_mac_82598EB) { 3130 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 3131 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32); 3132 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 3133 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32); 3134 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 3135 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32); 3136 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 3137 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 3138 } else { 3139 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 3140 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 3141 /* 82598 only has a counter in the high register */ 3142 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 3143 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 3144 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 3145 } 3146 uint64_t old_tpr = hw_stats->tpr; 3147 3148 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 3149 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT); 3150 3151 if (crc_strip == 0) 3152 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN; 3153 3154 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC); 3155 hw_stats->gptc += delta_gptc; 3156 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN; 3157 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN; 3158 3159 /* 3160 * Workaround: mprc hardware is incorrectly counting 3161 * broadcasts, so for now we subtract those. 3162 */ 3163 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 3164 hw_stats->bprc += bprc; 3165 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 3166 if (hw->mac.type == ixgbe_mac_82598EB) 3167 hw_stats->mprc -= bprc; 3168 3169 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 3170 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 3171 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 3172 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 3173 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 3174 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 3175 3176 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 3177 hw_stats->lxontxc += lxon; 3178 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 3179 hw_stats->lxofftxc += lxoff; 3180 total = lxon + lxoff; 3181 3182 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 3183 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 3184 hw_stats->gptc -= total; 3185 hw_stats->mptc -= total; 3186 hw_stats->ptc64 -= total; 3187 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN; 3188 3189 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 3190 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 3191 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 3192 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 3193 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC); 3194 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC); 3195 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC); 3196 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 3197 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 3198 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 3199 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 3200 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 3201 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 3202 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC); 3203 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 3204 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST); 3205 /* Only read FCOE on 82599 */ 3206 if (hw->mac.type != ixgbe_mac_82598EB) { 3207 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 3208 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 3209 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 3210 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 3211 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 3212 } 3213 3214 /* Flow Director Stats registers */ 3215 if (hw->mac.type != ixgbe_mac_82598EB) { 3216 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 3217 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 3218 hw_stats->fdirustat_add += IXGBE_READ_REG(hw, 3219 IXGBE_FDIRUSTAT) & 0xFFFF; 3220 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw, 3221 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF; 3222 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw, 3223 IXGBE_FDIRFSTAT) & 0xFFFF; 3224 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw, 3225 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF; 3226 } 3227 /* MACsec Stats registers */ 3228 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT); 3229 macsec_stats->out_pkts_encrypted += 3230 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE); 3231 macsec_stats->out_pkts_protected += 3232 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP); 3233 macsec_stats->out_octets_encrypted += 3234 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE); 3235 macsec_stats->out_octets_protected += 3236 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP); 3237 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT); 3238 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD); 3239 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI); 3240 macsec_stats->in_pkts_unknownsci += 3241 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI); 3242 macsec_stats->in_octets_decrypted += 3243 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD); 3244 macsec_stats->in_octets_validated += 3245 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV); 3246 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH); 3247 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY); 3248 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE); 3249 for (i = 0; i < 2; i++) { 3250 macsec_stats->in_pkts_ok += 3251 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i)); 3252 macsec_stats->in_pkts_invalid += 3253 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i)); 3254 macsec_stats->in_pkts_notvalid += 3255 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i)); 3256 } 3257 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA); 3258 macsec_stats->in_pkts_notusingsa += 3259 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA); 3260 } 3261 3262 /* 3263 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c 3264 */ 3265 static int 3266 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3267 { 3268 struct ixgbe_hw *hw = 3269 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3270 struct ixgbe_hw_stats *hw_stats = 3271 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3272 struct ixgbe_macsec_stats *macsec_stats = 3273 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3274 dev->data->dev_private); 3275 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3276 unsigned i; 3277 3278 total_missed_rx = 0; 3279 total_qbrc = 0; 3280 total_qprc = 0; 3281 total_qprdc = 0; 3282 3283 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3284 &total_qbrc, &total_qprc, &total_qprdc); 3285 3286 if (stats == NULL) 3287 return -EINVAL; 3288 3289 /* Fill out the rte_eth_stats statistics structure */ 3290 stats->ipackets = total_qprc; 3291 stats->ibytes = total_qbrc; 3292 stats->opackets = hw_stats->gptc; 3293 stats->obytes = hw_stats->gotc; 3294 3295 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3296 stats->q_ipackets[i] = hw_stats->qprc[i]; 3297 stats->q_opackets[i] = hw_stats->qptc[i]; 3298 stats->q_ibytes[i] = hw_stats->qbrc[i]; 3299 stats->q_obytes[i] = hw_stats->qbtc[i]; 3300 stats->q_errors[i] = hw_stats->qprdc[i]; 3301 } 3302 3303 /* Rx Errors */ 3304 stats->imissed = total_missed_rx; 3305 stats->ierrors = hw_stats->crcerrs + 3306 hw_stats->mspdc + 3307 hw_stats->rlec + 3308 hw_stats->ruc + 3309 hw_stats->roc + 3310 hw_stats->illerrc + 3311 hw_stats->errbc + 3312 hw_stats->rfc + 3313 hw_stats->fccrc + 3314 hw_stats->fclast; 3315 3316 /* Tx Errors */ 3317 stats->oerrors = 0; 3318 return 0; 3319 } 3320 3321 static void 3322 ixgbe_dev_stats_reset(struct rte_eth_dev *dev) 3323 { 3324 struct ixgbe_hw_stats *stats = 3325 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3326 3327 /* HW registers are cleared on read */ 3328 ixgbe_dev_stats_get(dev, NULL); 3329 3330 /* Reset software totals */ 3331 memset(stats, 0, sizeof(*stats)); 3332 } 3333 3334 /* This function calculates the number of xstats based on the current config */ 3335 static unsigned 3336 ixgbe_xstats_calc_num(void) { 3337 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS + 3338 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) + 3339 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES); 3340 } 3341 3342 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3343 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size) 3344 { 3345 const unsigned cnt_stats = ixgbe_xstats_calc_num(); 3346 unsigned stat, i, count; 3347 3348 if (xstats_names != NULL) { 3349 count = 0; 3350 3351 /* Note: limit >= cnt_stats checked upstream 3352 * in rte_eth_xstats_names() 3353 */ 3354 3355 /* Extended stats from ixgbe_hw_stats */ 3356 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3357 strlcpy(xstats_names[count].name, 3358 rte_ixgbe_stats_strings[i].name, 3359 sizeof(xstats_names[count].name)); 3360 count++; 3361 } 3362 3363 /* MACsec Stats */ 3364 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3365 strlcpy(xstats_names[count].name, 3366 rte_ixgbe_macsec_strings[i].name, 3367 sizeof(xstats_names[count].name)); 3368 count++; 3369 } 3370 3371 /* RX Priority Stats */ 3372 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3373 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3374 snprintf(xstats_names[count].name, 3375 sizeof(xstats_names[count].name), 3376 "rx_priority%u_%s", i, 3377 rte_ixgbe_rxq_strings[stat].name); 3378 count++; 3379 } 3380 } 3381 3382 /* TX Priority Stats */ 3383 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3384 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3385 snprintf(xstats_names[count].name, 3386 sizeof(xstats_names[count].name), 3387 "tx_priority%u_%s", i, 3388 rte_ixgbe_txq_strings[stat].name); 3389 count++; 3390 } 3391 } 3392 } 3393 return cnt_stats; 3394 } 3395 3396 static int ixgbe_dev_xstats_get_names_by_id( 3397 struct rte_eth_dev *dev, 3398 struct rte_eth_xstat_name *xstats_names, 3399 const uint64_t *ids, 3400 unsigned int limit) 3401 { 3402 if (!ids) { 3403 const unsigned int cnt_stats = ixgbe_xstats_calc_num(); 3404 unsigned int stat, i, count; 3405 3406 if (xstats_names != NULL) { 3407 count = 0; 3408 3409 /* Note: limit >= cnt_stats checked upstream 3410 * in rte_eth_xstats_names() 3411 */ 3412 3413 /* Extended stats from ixgbe_hw_stats */ 3414 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3415 strlcpy(xstats_names[count].name, 3416 rte_ixgbe_stats_strings[i].name, 3417 sizeof(xstats_names[count].name)); 3418 count++; 3419 } 3420 3421 /* MACsec Stats */ 3422 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3423 strlcpy(xstats_names[count].name, 3424 rte_ixgbe_macsec_strings[i].name, 3425 sizeof(xstats_names[count].name)); 3426 count++; 3427 } 3428 3429 /* RX Priority Stats */ 3430 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3431 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3432 snprintf(xstats_names[count].name, 3433 sizeof(xstats_names[count].name), 3434 "rx_priority%u_%s", i, 3435 rte_ixgbe_rxq_strings[stat].name); 3436 count++; 3437 } 3438 } 3439 3440 /* TX Priority Stats */ 3441 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3442 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3443 snprintf(xstats_names[count].name, 3444 sizeof(xstats_names[count].name), 3445 "tx_priority%u_%s", i, 3446 rte_ixgbe_txq_strings[stat].name); 3447 count++; 3448 } 3449 } 3450 } 3451 return cnt_stats; 3452 } 3453 3454 uint16_t i; 3455 uint16_t size = ixgbe_xstats_calc_num(); 3456 struct rte_eth_xstat_name xstats_names_copy[size]; 3457 3458 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL, 3459 size); 3460 3461 for (i = 0; i < limit; i++) { 3462 if (ids[i] >= size) { 3463 PMD_INIT_LOG(ERR, "id value isn't valid"); 3464 return -1; 3465 } 3466 strcpy(xstats_names[i].name, 3467 xstats_names_copy[ids[i]].name); 3468 } 3469 return limit; 3470 } 3471 3472 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3473 struct rte_eth_xstat_name *xstats_names, unsigned limit) 3474 { 3475 unsigned i; 3476 3477 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL) 3478 return -ENOMEM; 3479 3480 if (xstats_names != NULL) 3481 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) 3482 strlcpy(xstats_names[i].name, 3483 rte_ixgbevf_stats_strings[i].name, 3484 sizeof(xstats_names[i].name)); 3485 return IXGBEVF_NB_XSTATS; 3486 } 3487 3488 static int 3489 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3490 unsigned n) 3491 { 3492 struct ixgbe_hw *hw = 3493 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3494 struct ixgbe_hw_stats *hw_stats = 3495 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3496 struct ixgbe_macsec_stats *macsec_stats = 3497 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3498 dev->data->dev_private); 3499 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3500 unsigned i, stat, count = 0; 3501 3502 count = ixgbe_xstats_calc_num(); 3503 3504 if (n < count) 3505 return count; 3506 3507 total_missed_rx = 0; 3508 total_qbrc = 0; 3509 total_qprc = 0; 3510 total_qprdc = 0; 3511 3512 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3513 &total_qbrc, &total_qprc, &total_qprdc); 3514 3515 /* If this is a reset xstats is NULL, and we have cleared the 3516 * registers by reading them. 3517 */ 3518 if (!xstats) 3519 return 0; 3520 3521 /* Extended stats from ixgbe_hw_stats */ 3522 count = 0; 3523 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3524 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3525 rte_ixgbe_stats_strings[i].offset); 3526 xstats[count].id = count; 3527 count++; 3528 } 3529 3530 /* MACsec Stats */ 3531 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3532 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) + 3533 rte_ixgbe_macsec_strings[i].offset); 3534 xstats[count].id = count; 3535 count++; 3536 } 3537 3538 /* RX Priority Stats */ 3539 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3540 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3541 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3542 rte_ixgbe_rxq_strings[stat].offset + 3543 (sizeof(uint64_t) * i)); 3544 xstats[count].id = count; 3545 count++; 3546 } 3547 } 3548 3549 /* TX Priority Stats */ 3550 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3551 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3552 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3553 rte_ixgbe_txq_strings[stat].offset + 3554 (sizeof(uint64_t) * i)); 3555 xstats[count].id = count; 3556 count++; 3557 } 3558 } 3559 return count; 3560 } 3561 3562 static int 3563 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 3564 uint64_t *values, unsigned int n) 3565 { 3566 if (!ids) { 3567 struct ixgbe_hw *hw = 3568 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3569 struct ixgbe_hw_stats *hw_stats = 3570 IXGBE_DEV_PRIVATE_TO_STATS( 3571 dev->data->dev_private); 3572 struct ixgbe_macsec_stats *macsec_stats = 3573 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3574 dev->data->dev_private); 3575 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3576 unsigned int i, stat, count = 0; 3577 3578 count = ixgbe_xstats_calc_num(); 3579 3580 if (!ids && n < count) 3581 return count; 3582 3583 total_missed_rx = 0; 3584 total_qbrc = 0; 3585 total_qprc = 0; 3586 total_qprdc = 0; 3587 3588 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, 3589 &total_missed_rx, &total_qbrc, &total_qprc, 3590 &total_qprdc); 3591 3592 /* If this is a reset xstats is NULL, and we have cleared the 3593 * registers by reading them. 3594 */ 3595 if (!ids && !values) 3596 return 0; 3597 3598 /* Extended stats from ixgbe_hw_stats */ 3599 count = 0; 3600 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3601 values[count] = *(uint64_t *)(((char *)hw_stats) + 3602 rte_ixgbe_stats_strings[i].offset); 3603 count++; 3604 } 3605 3606 /* MACsec Stats */ 3607 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3608 values[count] = *(uint64_t *)(((char *)macsec_stats) + 3609 rte_ixgbe_macsec_strings[i].offset); 3610 count++; 3611 } 3612 3613 /* RX Priority Stats */ 3614 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3615 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3616 values[count] = 3617 *(uint64_t *)(((char *)hw_stats) + 3618 rte_ixgbe_rxq_strings[stat].offset + 3619 (sizeof(uint64_t) * i)); 3620 count++; 3621 } 3622 } 3623 3624 /* TX Priority Stats */ 3625 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3626 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3627 values[count] = 3628 *(uint64_t *)(((char *)hw_stats) + 3629 rte_ixgbe_txq_strings[stat].offset + 3630 (sizeof(uint64_t) * i)); 3631 count++; 3632 } 3633 } 3634 return count; 3635 } 3636 3637 uint16_t i; 3638 uint16_t size = ixgbe_xstats_calc_num(); 3639 uint64_t values_copy[size]; 3640 3641 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size); 3642 3643 for (i = 0; i < n; i++) { 3644 if (ids[i] >= size) { 3645 PMD_INIT_LOG(ERR, "id value isn't valid"); 3646 return -1; 3647 } 3648 values[i] = values_copy[ids[i]]; 3649 } 3650 return n; 3651 } 3652 3653 static void 3654 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev) 3655 { 3656 struct ixgbe_hw_stats *stats = 3657 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3658 struct ixgbe_macsec_stats *macsec_stats = 3659 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3660 dev->data->dev_private); 3661 3662 unsigned count = ixgbe_xstats_calc_num(); 3663 3664 /* HW registers are cleared on read */ 3665 ixgbe_dev_xstats_get(dev, NULL, count); 3666 3667 /* Reset software totals */ 3668 memset(stats, 0, sizeof(*stats)); 3669 memset(macsec_stats, 0, sizeof(*macsec_stats)); 3670 } 3671 3672 static void 3673 ixgbevf_update_stats(struct rte_eth_dev *dev) 3674 { 3675 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3676 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3677 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3678 3679 /* Good Rx packet, include VF loopback */ 3680 UPDATE_VF_STAT(IXGBE_VFGPRC, 3681 hw_stats->last_vfgprc, hw_stats->vfgprc); 3682 3683 /* Good Rx octets, include VF loopback */ 3684 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB, 3685 hw_stats->last_vfgorc, hw_stats->vfgorc); 3686 3687 /* Good Tx packet, include VF loopback */ 3688 UPDATE_VF_STAT(IXGBE_VFGPTC, 3689 hw_stats->last_vfgptc, hw_stats->vfgptc); 3690 3691 /* Good Tx octets, include VF loopback */ 3692 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB, 3693 hw_stats->last_vfgotc, hw_stats->vfgotc); 3694 3695 /* Rx Multicst Packet */ 3696 UPDATE_VF_STAT(IXGBE_VFMPRC, 3697 hw_stats->last_vfmprc, hw_stats->vfmprc); 3698 } 3699 3700 static int 3701 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3702 unsigned n) 3703 { 3704 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3705 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3706 unsigned i; 3707 3708 if (n < IXGBEVF_NB_XSTATS) 3709 return IXGBEVF_NB_XSTATS; 3710 3711 ixgbevf_update_stats(dev); 3712 3713 if (!xstats) 3714 return 0; 3715 3716 /* Extended stats */ 3717 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) { 3718 xstats[i].id = i; 3719 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + 3720 rte_ixgbevf_stats_strings[i].offset); 3721 } 3722 3723 return IXGBEVF_NB_XSTATS; 3724 } 3725 3726 static int 3727 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3728 { 3729 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3730 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3731 3732 ixgbevf_update_stats(dev); 3733 3734 if (stats == NULL) 3735 return -EINVAL; 3736 3737 stats->ipackets = hw_stats->vfgprc; 3738 stats->ibytes = hw_stats->vfgorc; 3739 stats->opackets = hw_stats->vfgptc; 3740 stats->obytes = hw_stats->vfgotc; 3741 return 0; 3742 } 3743 3744 static void 3745 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev) 3746 { 3747 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3748 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3749 3750 /* Sync HW register to the last stats */ 3751 ixgbevf_dev_stats_get(dev, NULL); 3752 3753 /* reset HW current stats*/ 3754 hw_stats->vfgprc = 0; 3755 hw_stats->vfgorc = 0; 3756 hw_stats->vfgptc = 0; 3757 hw_stats->vfgotc = 0; 3758 } 3759 3760 static int 3761 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 3762 { 3763 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3764 u16 eeprom_verh, eeprom_verl; 3765 u32 etrack_id; 3766 int ret; 3767 3768 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh); 3769 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl); 3770 3771 etrack_id = (eeprom_verh << 16) | eeprom_verl; 3772 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id); 3773 3774 ret += 1; /* add the size of '\0' */ 3775 if (fw_size < (u32)ret) 3776 return ret; 3777 else 3778 return 0; 3779 } 3780 3781 static void 3782 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3783 { 3784 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3785 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3786 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 3787 3788 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3789 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3790 if (RTE_ETH_DEV_SRIOV(dev).active == 0) { 3791 /* 3792 * When DCB/VT is off, maximum number of queues changes, 3793 * except for 82598EB, which remains constant. 3794 */ 3795 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 3796 hw->mac.type != ixgbe_mac_82598EB) 3797 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES; 3798 } 3799 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */ 3800 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */ 3801 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3802 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3803 dev_info->max_vfs = pci_dev->max_vfs; 3804 if (hw->mac.type == ixgbe_mac_82598EB) 3805 dev_info->max_vmdq_pools = ETH_16_POOLS; 3806 else 3807 dev_info->max_vmdq_pools = ETH_64_POOLS; 3808 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD; 3809 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 3810 dev_info->vmdq_queue_num = dev_info->max_rx_queues; 3811 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3812 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3813 dev_info->rx_queue_offload_capa); 3814 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3815 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3816 3817 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3818 .rx_thresh = { 3819 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3820 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3821 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3822 }, 3823 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3824 .rx_drop_en = 0, 3825 .offloads = 0, 3826 }; 3827 3828 dev_info->default_txconf = (struct rte_eth_txconf) { 3829 .tx_thresh = { 3830 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3831 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3832 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3833 }, 3834 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3835 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3836 .offloads = 0, 3837 }; 3838 3839 dev_info->rx_desc_lim = rx_desc_lim; 3840 dev_info->tx_desc_lim = tx_desc_lim; 3841 3842 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 3843 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 3844 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 3845 3846 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 3847 if (hw->mac.type == ixgbe_mac_X540 || 3848 hw->mac.type == ixgbe_mac_X540_vf || 3849 hw->mac.type == ixgbe_mac_X550 || 3850 hw->mac.type == ixgbe_mac_X550_vf) { 3851 dev_info->speed_capa |= ETH_LINK_SPEED_100M; 3852 } 3853 if (hw->mac.type == ixgbe_mac_X550) { 3854 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G; 3855 dev_info->speed_capa |= ETH_LINK_SPEED_5G; 3856 } 3857 3858 /* Driver-preferred Rx/Tx parameters */ 3859 dev_info->default_rxportconf.burst_size = 32; 3860 dev_info->default_txportconf.burst_size = 32; 3861 dev_info->default_rxportconf.nb_queues = 1; 3862 dev_info->default_txportconf.nb_queues = 1; 3863 dev_info->default_rxportconf.ring_size = 256; 3864 dev_info->default_txportconf.ring_size = 256; 3865 } 3866 3867 static const uint32_t * 3868 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 3869 { 3870 static const uint32_t ptypes[] = { 3871 /* For non-vec functions, 3872 * refers to ixgbe_rxd_pkt_info_to_pkt_type(); 3873 * for vec functions, 3874 * refers to _recv_raw_pkts_vec(). 3875 */ 3876 RTE_PTYPE_L2_ETHER, 3877 RTE_PTYPE_L3_IPV4, 3878 RTE_PTYPE_L3_IPV4_EXT, 3879 RTE_PTYPE_L3_IPV6, 3880 RTE_PTYPE_L3_IPV6_EXT, 3881 RTE_PTYPE_L4_SCTP, 3882 RTE_PTYPE_L4_TCP, 3883 RTE_PTYPE_L4_UDP, 3884 RTE_PTYPE_TUNNEL_IP, 3885 RTE_PTYPE_INNER_L3_IPV6, 3886 RTE_PTYPE_INNER_L3_IPV6_EXT, 3887 RTE_PTYPE_INNER_L4_TCP, 3888 RTE_PTYPE_INNER_L4_UDP, 3889 RTE_PTYPE_UNKNOWN 3890 }; 3891 3892 if (dev->rx_pkt_burst == ixgbe_recv_pkts || 3893 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc || 3894 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc || 3895 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc) 3896 return ptypes; 3897 3898 #if defined(RTE_ARCH_X86) 3899 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec || 3900 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec) 3901 return ptypes; 3902 #endif 3903 return NULL; 3904 } 3905 3906 static void 3907 ixgbevf_dev_info_get(struct rte_eth_dev *dev, 3908 struct rte_eth_dev_info *dev_info) 3909 { 3910 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3911 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3912 3913 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3914 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3915 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */ 3916 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */ 3917 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD; 3918 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3919 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3920 dev_info->max_vfs = pci_dev->max_vfs; 3921 if (hw->mac.type == ixgbe_mac_82598EB) 3922 dev_info->max_vmdq_pools = ETH_16_POOLS; 3923 else 3924 dev_info->max_vmdq_pools = ETH_64_POOLS; 3925 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3926 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3927 dev_info->rx_queue_offload_capa); 3928 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3929 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3930 3931 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3932 .rx_thresh = { 3933 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3934 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3935 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3936 }, 3937 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3938 .rx_drop_en = 0, 3939 .offloads = 0, 3940 }; 3941 3942 dev_info->default_txconf = (struct rte_eth_txconf) { 3943 .tx_thresh = { 3944 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3945 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3946 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3947 }, 3948 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3949 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3950 .offloads = 0, 3951 }; 3952 3953 dev_info->rx_desc_lim = rx_desc_lim; 3954 dev_info->tx_desc_lim = tx_desc_lim; 3955 } 3956 3957 static int 3958 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3959 int *link_up, int wait_to_complete) 3960 { 3961 struct ixgbe_adapter *adapter = container_of(hw, 3962 struct ixgbe_adapter, hw); 3963 struct ixgbe_mbx_info *mbx = &hw->mbx; 3964 struct ixgbe_mac_info *mac = &hw->mac; 3965 uint32_t links_reg, in_msg; 3966 int ret_val = 0; 3967 3968 /* If we were hit with a reset drop the link */ 3969 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout) 3970 mac->get_link_status = true; 3971 3972 if (!mac->get_link_status) 3973 goto out; 3974 3975 /* if link status is down no point in checking to see if pf is up */ 3976 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 3977 if (!(links_reg & IXGBE_LINKS_UP)) 3978 goto out; 3979 3980 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs 3981 * before the link status is correct 3982 */ 3983 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) { 3984 int i; 3985 3986 for (i = 0; i < 5; i++) { 3987 rte_delay_us(100); 3988 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 3989 3990 if (!(links_reg & IXGBE_LINKS_UP)) 3991 goto out; 3992 } 3993 } 3994 3995 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 3996 case IXGBE_LINKS_SPEED_10G_82599: 3997 *speed = IXGBE_LINK_SPEED_10GB_FULL; 3998 if (hw->mac.type >= ixgbe_mac_X550) { 3999 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4000 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4001 } 4002 break; 4003 case IXGBE_LINKS_SPEED_1G_82599: 4004 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4005 break; 4006 case IXGBE_LINKS_SPEED_100_82599: 4007 *speed = IXGBE_LINK_SPEED_100_FULL; 4008 if (hw->mac.type == ixgbe_mac_X550) { 4009 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4010 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4011 } 4012 break; 4013 case IXGBE_LINKS_SPEED_10_X550EM_A: 4014 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4015 /* Since Reserved in older MAC's */ 4016 if (hw->mac.type >= ixgbe_mac_X550) 4017 *speed = IXGBE_LINK_SPEED_10_FULL; 4018 break; 4019 default: 4020 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4021 } 4022 4023 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) { 4024 if (*speed == IXGBE_LINK_SPEED_UNKNOWN) 4025 mac->get_link_status = true; 4026 else 4027 mac->get_link_status = false; 4028 4029 goto out; 4030 } 4031 4032 /* if the read failed it could just be a mailbox collision, best wait 4033 * until we are called again and don't report an error 4034 */ 4035 if (mbx->ops.read(hw, &in_msg, 1, 0)) 4036 goto out; 4037 4038 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) { 4039 /* msg is not CTS and is NACK we must have lost CTS status */ 4040 if (in_msg & IXGBE_VT_MSGTYPE_NACK) 4041 mac->get_link_status = false; 4042 goto out; 4043 } 4044 4045 /* the pf is talking, if we timed out in the past we reinit */ 4046 if (!mbx->timeout) { 4047 ret_val = -1; 4048 goto out; 4049 } 4050 4051 /* if we passed all the tests above then the link is up and we no 4052 * longer need to check for link 4053 */ 4054 mac->get_link_status = false; 4055 4056 out: 4057 *link_up = !mac->get_link_status; 4058 return ret_val; 4059 } 4060 4061 static void 4062 ixgbe_dev_setup_link_alarm_handler(void *param) 4063 { 4064 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4065 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4066 struct ixgbe_interrupt *intr = 4067 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4068 u32 speed; 4069 bool autoneg = false; 4070 4071 speed = hw->phy.autoneg_advertised; 4072 if (!speed) 4073 ixgbe_get_link_capabilities(hw, &speed, &autoneg); 4074 4075 ixgbe_setup_link(hw, speed, true); 4076 4077 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 4078 } 4079 4080 /* return 0 means link status changed, -1 means not changed */ 4081 int 4082 ixgbe_dev_link_update_share(struct rte_eth_dev *dev, 4083 int wait_to_complete, int vf) 4084 { 4085 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4086 struct rte_eth_link link; 4087 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4088 struct ixgbe_interrupt *intr = 4089 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4090 int link_up; 4091 int diag; 4092 int wait = 1; 4093 4094 memset(&link, 0, sizeof(link)); 4095 link.link_status = ETH_LINK_DOWN; 4096 link.link_speed = ETH_SPEED_NUM_NONE; 4097 link.link_duplex = ETH_LINK_HALF_DUPLEX; 4098 link.link_autoneg = ETH_LINK_AUTONEG; 4099 4100 hw->mac.get_link_status = true; 4101 4102 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) 4103 return rte_eth_linkstatus_set(dev, &link); 4104 4105 /* check if it needs to wait to complete, if lsc interrupt is enabled */ 4106 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0) 4107 wait = 0; 4108 4109 if (vf) 4110 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait); 4111 else 4112 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait); 4113 4114 if (diag != 0) { 4115 link.link_speed = ETH_SPEED_NUM_100M; 4116 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4117 return rte_eth_linkstatus_set(dev, &link); 4118 } 4119 4120 if (link_up == 0) { 4121 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) { 4122 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 4123 rte_eal_alarm_set(10, 4124 ixgbe_dev_setup_link_alarm_handler, dev); 4125 } 4126 return rte_eth_linkstatus_set(dev, &link); 4127 } 4128 4129 link.link_status = ETH_LINK_UP; 4130 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4131 4132 switch (link_speed) { 4133 default: 4134 case IXGBE_LINK_SPEED_UNKNOWN: 4135 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 4136 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 4137 link.link_speed = ETH_SPEED_NUM_10M; 4138 else 4139 link.link_speed = ETH_SPEED_NUM_100M; 4140 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4141 break; 4142 4143 case IXGBE_LINK_SPEED_100_FULL: 4144 link.link_speed = ETH_SPEED_NUM_100M; 4145 break; 4146 4147 case IXGBE_LINK_SPEED_1GB_FULL: 4148 link.link_speed = ETH_SPEED_NUM_1G; 4149 break; 4150 4151 case IXGBE_LINK_SPEED_2_5GB_FULL: 4152 link.link_speed = ETH_SPEED_NUM_2_5G; 4153 break; 4154 4155 case IXGBE_LINK_SPEED_5GB_FULL: 4156 link.link_speed = ETH_SPEED_NUM_5G; 4157 break; 4158 4159 case IXGBE_LINK_SPEED_10GB_FULL: 4160 link.link_speed = ETH_SPEED_NUM_10G; 4161 break; 4162 } 4163 4164 return rte_eth_linkstatus_set(dev, &link); 4165 } 4166 4167 static int 4168 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4169 { 4170 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0); 4171 } 4172 4173 static int 4174 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4175 { 4176 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1); 4177 } 4178 4179 static void 4180 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 4181 { 4182 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4183 uint32_t fctrl; 4184 4185 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4186 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4187 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4188 } 4189 4190 static void 4191 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 4192 { 4193 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4194 uint32_t fctrl; 4195 4196 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4197 fctrl &= (~IXGBE_FCTRL_UPE); 4198 if (dev->data->all_multicast == 1) 4199 fctrl |= IXGBE_FCTRL_MPE; 4200 else 4201 fctrl &= (~IXGBE_FCTRL_MPE); 4202 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4203 } 4204 4205 static void 4206 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 4207 { 4208 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4209 uint32_t fctrl; 4210 4211 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4212 fctrl |= IXGBE_FCTRL_MPE; 4213 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4214 } 4215 4216 static void 4217 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 4218 { 4219 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4220 uint32_t fctrl; 4221 4222 if (dev->data->promiscuous == 1) 4223 return; /* must remain in all_multicast mode */ 4224 4225 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4226 fctrl &= (~IXGBE_FCTRL_MPE); 4227 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4228 } 4229 4230 /** 4231 * It clears the interrupt causes and enables the interrupt. 4232 * It will be called once only during nic initialized. 4233 * 4234 * @param dev 4235 * Pointer to struct rte_eth_dev. 4236 * @param on 4237 * Enable or Disable. 4238 * 4239 * @return 4240 * - On success, zero. 4241 * - On failure, a negative value. 4242 */ 4243 static int 4244 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 4245 { 4246 struct ixgbe_interrupt *intr = 4247 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4248 4249 ixgbe_dev_link_status_print(dev); 4250 if (on) 4251 intr->mask |= IXGBE_EICR_LSC; 4252 else 4253 intr->mask &= ~IXGBE_EICR_LSC; 4254 4255 return 0; 4256 } 4257 4258 /** 4259 * It clears the interrupt causes and enables the interrupt. 4260 * It will be called once only during nic initialized. 4261 * 4262 * @param dev 4263 * Pointer to struct rte_eth_dev. 4264 * 4265 * @return 4266 * - On success, zero. 4267 * - On failure, a negative value. 4268 */ 4269 static int 4270 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev) 4271 { 4272 struct ixgbe_interrupt *intr = 4273 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4274 4275 intr->mask |= IXGBE_EICR_RTX_QUEUE; 4276 4277 return 0; 4278 } 4279 4280 /** 4281 * It clears the interrupt causes and enables the interrupt. 4282 * It will be called once only during nic initialized. 4283 * 4284 * @param dev 4285 * Pointer to struct rte_eth_dev. 4286 * 4287 * @return 4288 * - On success, zero. 4289 * - On failure, a negative value. 4290 */ 4291 static int 4292 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev) 4293 { 4294 struct ixgbe_interrupt *intr = 4295 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4296 4297 intr->mask |= IXGBE_EICR_LINKSEC; 4298 4299 return 0; 4300 } 4301 4302 /* 4303 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update. 4304 * 4305 * @param dev 4306 * Pointer to struct rte_eth_dev. 4307 * 4308 * @return 4309 * - On success, zero. 4310 * - On failure, a negative value. 4311 */ 4312 static int 4313 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev) 4314 { 4315 uint32_t eicr; 4316 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4317 struct ixgbe_interrupt *intr = 4318 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4319 4320 /* clear all cause mask */ 4321 ixgbe_disable_intr(hw); 4322 4323 /* read-on-clear nic registers here */ 4324 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4325 PMD_DRV_LOG(DEBUG, "eicr %x", eicr); 4326 4327 intr->flags = 0; 4328 4329 /* set flag for async link update */ 4330 if (eicr & IXGBE_EICR_LSC) 4331 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 4332 4333 if (eicr & IXGBE_EICR_MAILBOX) 4334 intr->flags |= IXGBE_FLAG_MAILBOX; 4335 4336 if (eicr & IXGBE_EICR_LINKSEC) 4337 intr->flags |= IXGBE_FLAG_MACSEC; 4338 4339 if (hw->mac.type == ixgbe_mac_X550EM_x && 4340 hw->phy.type == ixgbe_phy_x550em_ext_t && 4341 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x)) 4342 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT; 4343 4344 return 0; 4345 } 4346 4347 /** 4348 * It gets and then prints the link status. 4349 * 4350 * @param dev 4351 * Pointer to struct rte_eth_dev. 4352 * 4353 * @return 4354 * - On success, zero. 4355 * - On failure, a negative value. 4356 */ 4357 static void 4358 ixgbe_dev_link_status_print(struct rte_eth_dev *dev) 4359 { 4360 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4361 struct rte_eth_link link; 4362 4363 rte_eth_linkstatus_get(dev, &link); 4364 4365 if (link.link_status) { 4366 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", 4367 (int)(dev->data->port_id), 4368 (unsigned)link.link_speed, 4369 link.link_duplex == ETH_LINK_FULL_DUPLEX ? 4370 "full-duplex" : "half-duplex"); 4371 } else { 4372 PMD_INIT_LOG(INFO, " Port %d: Link Down", 4373 (int)(dev->data->port_id)); 4374 } 4375 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 4376 pci_dev->addr.domain, 4377 pci_dev->addr.bus, 4378 pci_dev->addr.devid, 4379 pci_dev->addr.function); 4380 } 4381 4382 /* 4383 * It executes link_update after knowing an interrupt occurred. 4384 * 4385 * @param dev 4386 * Pointer to struct rte_eth_dev. 4387 * 4388 * @return 4389 * - On success, zero. 4390 * - On failure, a negative value. 4391 */ 4392 static int 4393 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev) 4394 { 4395 struct ixgbe_interrupt *intr = 4396 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4397 int64_t timeout; 4398 struct ixgbe_hw *hw = 4399 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4400 4401 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags); 4402 4403 if (intr->flags & IXGBE_FLAG_MAILBOX) { 4404 ixgbe_pf_mbx_process(dev); 4405 intr->flags &= ~IXGBE_FLAG_MAILBOX; 4406 } 4407 4408 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4409 ixgbe_handle_lasi(hw); 4410 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4411 } 4412 4413 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4414 struct rte_eth_link link; 4415 4416 /* get the link status before link update, for predicting later */ 4417 rte_eth_linkstatus_get(dev, &link); 4418 4419 ixgbe_dev_link_update(dev, 0); 4420 4421 /* likely to up */ 4422 if (!link.link_status) 4423 /* handle it 1 sec later, wait it being stable */ 4424 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT; 4425 /* likely to down */ 4426 else 4427 /* handle it 4 sec later, wait it being stable */ 4428 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT; 4429 4430 ixgbe_dev_link_status_print(dev); 4431 if (rte_eal_alarm_set(timeout * 1000, 4432 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0) 4433 PMD_DRV_LOG(ERR, "Error setting alarm"); 4434 else { 4435 /* remember original mask */ 4436 intr->mask_original = intr->mask; 4437 /* only disable lsc interrupt */ 4438 intr->mask &= ~IXGBE_EIMS_LSC; 4439 } 4440 } 4441 4442 PMD_DRV_LOG(DEBUG, "enable intr immediately"); 4443 ixgbe_enable_intr(dev); 4444 4445 return 0; 4446 } 4447 4448 /** 4449 * Interrupt handler which shall be registered for alarm callback for delayed 4450 * handling specific interrupt to wait for the stable nic state. As the 4451 * NIC interrupt state is not stable for ixgbe after link is just down, 4452 * it needs to wait 4 seconds to get the stable status. 4453 * 4454 * @param handle 4455 * Pointer to interrupt handle. 4456 * @param param 4457 * The address of parameter (struct rte_eth_dev *) regsitered before. 4458 * 4459 * @return 4460 * void 4461 */ 4462 static void 4463 ixgbe_dev_interrupt_delayed_handler(void *param) 4464 { 4465 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4466 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4467 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4468 struct ixgbe_interrupt *intr = 4469 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4470 struct ixgbe_hw *hw = 4471 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4472 uint32_t eicr; 4473 4474 ixgbe_disable_intr(hw); 4475 4476 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4477 if (eicr & IXGBE_EICR_MAILBOX) 4478 ixgbe_pf_mbx_process(dev); 4479 4480 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4481 ixgbe_handle_lasi(hw); 4482 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4483 } 4484 4485 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4486 ixgbe_dev_link_update(dev, 0); 4487 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 4488 ixgbe_dev_link_status_print(dev); 4489 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, 4490 NULL); 4491 } 4492 4493 if (intr->flags & IXGBE_FLAG_MACSEC) { 4494 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, 4495 NULL); 4496 intr->flags &= ~IXGBE_FLAG_MACSEC; 4497 } 4498 4499 /* restore original mask */ 4500 intr->mask = intr->mask_original; 4501 intr->mask_original = 0; 4502 4503 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr); 4504 ixgbe_enable_intr(dev); 4505 rte_intr_enable(intr_handle); 4506 } 4507 4508 /** 4509 * Interrupt handler triggered by NIC for handling 4510 * specific interrupt. 4511 * 4512 * @param handle 4513 * Pointer to interrupt handle. 4514 * @param param 4515 * The address of parameter (struct rte_eth_dev *) regsitered before. 4516 * 4517 * @return 4518 * void 4519 */ 4520 static void 4521 ixgbe_dev_interrupt_handler(void *param) 4522 { 4523 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4524 4525 ixgbe_dev_interrupt_get_status(dev); 4526 ixgbe_dev_interrupt_action(dev); 4527 } 4528 4529 static int 4530 ixgbe_dev_led_on(struct rte_eth_dev *dev) 4531 { 4532 struct ixgbe_hw *hw; 4533 4534 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4535 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4536 } 4537 4538 static int 4539 ixgbe_dev_led_off(struct rte_eth_dev *dev) 4540 { 4541 struct ixgbe_hw *hw; 4542 4543 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4544 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4545 } 4546 4547 static int 4548 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4549 { 4550 struct ixgbe_hw *hw; 4551 uint32_t mflcn_reg; 4552 uint32_t fccfg_reg; 4553 int rx_pause; 4554 int tx_pause; 4555 4556 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4557 4558 fc_conf->pause_time = hw->fc.pause_time; 4559 fc_conf->high_water = hw->fc.high_water[0]; 4560 fc_conf->low_water = hw->fc.low_water[0]; 4561 fc_conf->send_xon = hw->fc.send_xon; 4562 fc_conf->autoneg = !hw->fc.disable_fc_autoneg; 4563 4564 /* 4565 * Return rx_pause status according to actual setting of 4566 * MFLCN register. 4567 */ 4568 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4569 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE)) 4570 rx_pause = 1; 4571 else 4572 rx_pause = 0; 4573 4574 /* 4575 * Return tx_pause status according to actual setting of 4576 * FCCFG register. 4577 */ 4578 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4579 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY)) 4580 tx_pause = 1; 4581 else 4582 tx_pause = 0; 4583 4584 if (rx_pause && tx_pause) 4585 fc_conf->mode = RTE_FC_FULL; 4586 else if (rx_pause) 4587 fc_conf->mode = RTE_FC_RX_PAUSE; 4588 else if (tx_pause) 4589 fc_conf->mode = RTE_FC_TX_PAUSE; 4590 else 4591 fc_conf->mode = RTE_FC_NONE; 4592 4593 return 0; 4594 } 4595 4596 static int 4597 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4598 { 4599 struct ixgbe_hw *hw; 4600 int err; 4601 uint32_t rx_buf_size; 4602 uint32_t max_high_water; 4603 uint32_t mflcn; 4604 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4605 ixgbe_fc_none, 4606 ixgbe_fc_rx_pause, 4607 ixgbe_fc_tx_pause, 4608 ixgbe_fc_full 4609 }; 4610 4611 PMD_INIT_FUNC_TRACE(); 4612 4613 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4614 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)); 4615 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4616 4617 /* 4618 * At least reserve one Ethernet frame for watermark 4619 * high_water/low_water in kilo bytes for ixgbe 4620 */ 4621 max_high_water = (rx_buf_size - 4622 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4623 if ((fc_conf->high_water > max_high_water) || 4624 (fc_conf->high_water < fc_conf->low_water)) { 4625 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4626 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4627 return -EINVAL; 4628 } 4629 4630 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode]; 4631 hw->fc.pause_time = fc_conf->pause_time; 4632 hw->fc.high_water[0] = fc_conf->high_water; 4633 hw->fc.low_water[0] = fc_conf->low_water; 4634 hw->fc.send_xon = fc_conf->send_xon; 4635 hw->fc.disable_fc_autoneg = !fc_conf->autoneg; 4636 4637 err = ixgbe_fc_enable(hw); 4638 4639 /* Not negotiated is not an error case */ 4640 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) { 4641 4642 /* check if we want to forward MAC frames - driver doesn't have native 4643 * capability to do that, so we'll write the registers ourselves */ 4644 4645 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4646 4647 /* set or clear MFLCN.PMCF bit depending on configuration */ 4648 if (fc_conf->mac_ctrl_frame_fwd != 0) 4649 mflcn |= IXGBE_MFLCN_PMCF; 4650 else 4651 mflcn &= ~IXGBE_MFLCN_PMCF; 4652 4653 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn); 4654 IXGBE_WRITE_FLUSH(hw); 4655 4656 return 0; 4657 } 4658 4659 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err); 4660 return -EIO; 4661 } 4662 4663 /** 4664 * ixgbe_pfc_enable_generic - Enable flow control 4665 * @hw: pointer to hardware structure 4666 * @tc_num: traffic class number 4667 * Enable flow control according to the current settings. 4668 */ 4669 static int 4670 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num) 4671 { 4672 int ret_val = 0; 4673 uint32_t mflcn_reg, fccfg_reg; 4674 uint32_t reg; 4675 uint32_t fcrtl, fcrth; 4676 uint8_t i; 4677 uint8_t nb_rx_en; 4678 4679 /* Validate the water mark configuration */ 4680 if (!hw->fc.pause_time) { 4681 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4682 goto out; 4683 } 4684 4685 /* Low water mark of zero causes XOFF floods */ 4686 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 4687 /* High/Low water can not be 0 */ 4688 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) { 4689 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4690 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4691 goto out; 4692 } 4693 4694 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) { 4695 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4696 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4697 goto out; 4698 } 4699 } 4700 /* Negotiate the fc mode to use */ 4701 ixgbe_fc_autoneg(hw); 4702 4703 /* Disable any previous flow control settings */ 4704 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4705 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE); 4706 4707 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4708 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 4709 4710 switch (hw->fc.current_mode) { 4711 case ixgbe_fc_none: 4712 /* 4713 * If the count of enabled RX Priority Flow control >1, 4714 * and the TX pause can not be disabled 4715 */ 4716 nb_rx_en = 0; 4717 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4718 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4719 if (reg & IXGBE_FCRTH_FCEN) 4720 nb_rx_en++; 4721 } 4722 if (nb_rx_en > 1) 4723 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4724 break; 4725 case ixgbe_fc_rx_pause: 4726 /* 4727 * Rx Flow control is enabled and Tx Flow control is 4728 * disabled by software override. Since there really 4729 * isn't a way to advertise that we are capable of RX 4730 * Pause ONLY, we will advertise that we support both 4731 * symmetric and asymmetric Rx PAUSE. Later, we will 4732 * disable the adapter's ability to send PAUSE frames. 4733 */ 4734 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4735 /* 4736 * If the count of enabled RX Priority Flow control >1, 4737 * and the TX pause can not be disabled 4738 */ 4739 nb_rx_en = 0; 4740 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4741 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4742 if (reg & IXGBE_FCRTH_FCEN) 4743 nb_rx_en++; 4744 } 4745 if (nb_rx_en > 1) 4746 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4747 break; 4748 case ixgbe_fc_tx_pause: 4749 /* 4750 * Tx Flow control is enabled, and Rx Flow control is 4751 * disabled by software override. 4752 */ 4753 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4754 break; 4755 case ixgbe_fc_full: 4756 /* Flow control (both Rx and Tx) is enabled by SW override. */ 4757 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4758 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4759 break; 4760 default: 4761 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly"); 4762 ret_val = IXGBE_ERR_CONFIG; 4763 goto out; 4764 } 4765 4766 /* Set 802.3x based flow control settings. */ 4767 mflcn_reg |= IXGBE_MFLCN_DPF; 4768 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 4769 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 4770 4771 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 4772 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 4773 hw->fc.high_water[tc_num]) { 4774 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE; 4775 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl); 4776 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN; 4777 } else { 4778 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0); 4779 /* 4780 * In order to prevent Tx hangs when the internal Tx 4781 * switch is enabled we must set the high water mark 4782 * to the maximum FCRTH value. This allows the Tx 4783 * switch to function even under heavy Rx workloads. 4784 */ 4785 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32; 4786 } 4787 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth); 4788 4789 /* Configure pause time (2 TCs per register) */ 4790 reg = hw->fc.pause_time * 0x00010001; 4791 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 4792 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 4793 4794 /* Configure flow control refresh threshold value */ 4795 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 4796 4797 out: 4798 return ret_val; 4799 } 4800 4801 static int 4802 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num) 4803 { 4804 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4805 int32_t ret_val = IXGBE_NOT_IMPLEMENTED; 4806 4807 if (hw->mac.type != ixgbe_mac_82598EB) { 4808 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num); 4809 } 4810 return ret_val; 4811 } 4812 4813 static int 4814 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf) 4815 { 4816 int err; 4817 uint32_t rx_buf_size; 4818 uint32_t max_high_water; 4819 uint8_t tc_num; 4820 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 4821 struct ixgbe_hw *hw = 4822 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4823 struct ixgbe_dcb_config *dcb_config = 4824 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 4825 4826 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4827 ixgbe_fc_none, 4828 ixgbe_fc_rx_pause, 4829 ixgbe_fc_tx_pause, 4830 ixgbe_fc_full 4831 }; 4832 4833 PMD_INIT_FUNC_TRACE(); 4834 4835 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map); 4836 tc_num = map[pfc_conf->priority]; 4837 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)); 4838 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4839 /* 4840 * At least reserve one Ethernet frame for watermark 4841 * high_water/low_water in kilo bytes for ixgbe 4842 */ 4843 max_high_water = (rx_buf_size - 4844 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4845 if ((pfc_conf->fc.high_water > max_high_water) || 4846 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) { 4847 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4848 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4849 return -EINVAL; 4850 } 4851 4852 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode]; 4853 hw->fc.pause_time = pfc_conf->fc.pause_time; 4854 hw->fc.send_xon = pfc_conf->fc.send_xon; 4855 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water; 4856 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; 4857 4858 err = ixgbe_dcb_pfc_enable(dev, tc_num); 4859 4860 /* Not negotiated is not an error case */ 4861 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) 4862 return 0; 4863 4864 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err); 4865 return -EIO; 4866 } 4867 4868 static int 4869 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 4870 struct rte_eth_rss_reta_entry64 *reta_conf, 4871 uint16_t reta_size) 4872 { 4873 uint16_t i, sp_reta_size; 4874 uint8_t j, mask; 4875 uint32_t reta, r; 4876 uint16_t idx, shift; 4877 struct ixgbe_adapter *adapter = dev->data->dev_private; 4878 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4879 uint32_t reta_reg; 4880 4881 PMD_INIT_FUNC_TRACE(); 4882 4883 if (!ixgbe_rss_update_sp(hw->mac.type)) { 4884 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " 4885 "NIC."); 4886 return -ENOTSUP; 4887 } 4888 4889 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 4890 if (reta_size != sp_reta_size) { 4891 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 4892 "(%d) doesn't match the number hardware can supported " 4893 "(%d)", reta_size, sp_reta_size); 4894 return -EINVAL; 4895 } 4896 4897 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 4898 idx = i / RTE_RETA_GROUP_SIZE; 4899 shift = i % RTE_RETA_GROUP_SIZE; 4900 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 4901 IXGBE_4_BIT_MASK); 4902 if (!mask) 4903 continue; 4904 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 4905 if (mask == IXGBE_4_BIT_MASK) 4906 r = 0; 4907 else 4908 r = IXGBE_READ_REG(hw, reta_reg); 4909 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) { 4910 if (mask & (0x1 << j)) 4911 reta |= reta_conf[idx].reta[shift + j] << 4912 (CHAR_BIT * j); 4913 else 4914 reta |= r & (IXGBE_8_BIT_MASK << 4915 (CHAR_BIT * j)); 4916 } 4917 IXGBE_WRITE_REG(hw, reta_reg, reta); 4918 } 4919 adapter->rss_reta_updated = 1; 4920 4921 return 0; 4922 } 4923 4924 static int 4925 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 4926 struct rte_eth_rss_reta_entry64 *reta_conf, 4927 uint16_t reta_size) 4928 { 4929 uint16_t i, sp_reta_size; 4930 uint8_t j, mask; 4931 uint32_t reta; 4932 uint16_t idx, shift; 4933 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4934 uint32_t reta_reg; 4935 4936 PMD_INIT_FUNC_TRACE(); 4937 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 4938 if (reta_size != sp_reta_size) { 4939 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 4940 "(%d) doesn't match the number hardware can supported " 4941 "(%d)", reta_size, sp_reta_size); 4942 return -EINVAL; 4943 } 4944 4945 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 4946 idx = i / RTE_RETA_GROUP_SIZE; 4947 shift = i % RTE_RETA_GROUP_SIZE; 4948 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 4949 IXGBE_4_BIT_MASK); 4950 if (!mask) 4951 continue; 4952 4953 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 4954 reta = IXGBE_READ_REG(hw, reta_reg); 4955 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) { 4956 if (mask & (0x1 << j)) 4957 reta_conf[idx].reta[shift + j] = 4958 ((reta >> (CHAR_BIT * j)) & 4959 IXGBE_8_BIT_MASK); 4960 } 4961 } 4962 4963 return 0; 4964 } 4965 4966 static int 4967 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 4968 uint32_t index, uint32_t pool) 4969 { 4970 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4971 uint32_t enable_addr = 1; 4972 4973 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes, 4974 pool, enable_addr); 4975 } 4976 4977 static void 4978 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) 4979 { 4980 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4981 4982 ixgbe_clear_rar(hw, index); 4983 } 4984 4985 static int 4986 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 4987 { 4988 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4989 4990 ixgbe_remove_rar(dev, 0); 4991 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs); 4992 4993 return 0; 4994 } 4995 4996 static bool 4997 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 4998 { 4999 if (strcmp(dev->device->driver->name, drv->driver.name)) 5000 return false; 5001 5002 return true; 5003 } 5004 5005 bool 5006 is_ixgbe_supported(struct rte_eth_dev *dev) 5007 { 5008 return is_device_supported(dev, &rte_ixgbe_pmd); 5009 } 5010 5011 static int 5012 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 5013 { 5014 uint32_t hlreg0; 5015 uint32_t maxfrs; 5016 struct ixgbe_hw *hw; 5017 struct rte_eth_dev_info dev_info; 5018 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD; 5019 struct rte_eth_dev_data *dev_data = dev->data; 5020 5021 ixgbe_dev_info_get(dev, &dev_info); 5022 5023 /* check that mtu is within the allowed range */ 5024 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) 5025 return -EINVAL; 5026 5027 /* If device is started, refuse mtu that requires the support of 5028 * scattered packets when this feature has not been enabled before. 5029 */ 5030 if (dev_data->dev_started && !dev_data->scattered_rx && 5031 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE > 5032 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 5033 PMD_INIT_LOG(ERR, "Stop port first."); 5034 return -EINVAL; 5035 } 5036 5037 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5038 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 5039 5040 /* switch to jumbo mode if needed */ 5041 if (frame_size > RTE_ETHER_MAX_LEN) { 5042 dev->data->dev_conf.rxmode.offloads |= 5043 DEV_RX_OFFLOAD_JUMBO_FRAME; 5044 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 5045 } else { 5046 dev->data->dev_conf.rxmode.offloads &= 5047 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 5048 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; 5049 } 5050 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 5051 5052 /* update max frame size */ 5053 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 5054 5055 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS); 5056 maxfrs &= 0x0000FFFF; 5057 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16); 5058 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs); 5059 5060 return 0; 5061 } 5062 5063 /* 5064 * Virtual Function operations 5065 */ 5066 static void 5067 ixgbevf_intr_disable(struct rte_eth_dev *dev) 5068 { 5069 struct ixgbe_interrupt *intr = 5070 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5071 struct ixgbe_hw *hw = 5072 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5073 5074 PMD_INIT_FUNC_TRACE(); 5075 5076 /* Clear interrupt mask to stop from interrupts being generated */ 5077 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK); 5078 5079 IXGBE_WRITE_FLUSH(hw); 5080 5081 /* Clear mask value. */ 5082 intr->mask = 0; 5083 } 5084 5085 static void 5086 ixgbevf_intr_enable(struct rte_eth_dev *dev) 5087 { 5088 struct ixgbe_interrupt *intr = 5089 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5090 struct ixgbe_hw *hw = 5091 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5092 5093 PMD_INIT_FUNC_TRACE(); 5094 5095 /* VF enable interrupt autoclean */ 5096 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK); 5097 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK); 5098 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK); 5099 5100 IXGBE_WRITE_FLUSH(hw); 5101 5102 /* Save IXGBE_VTEIMS value to mask. */ 5103 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK; 5104 } 5105 5106 static int 5107 ixgbevf_dev_configure(struct rte_eth_dev *dev) 5108 { 5109 struct rte_eth_conf *conf = &dev->data->dev_conf; 5110 struct ixgbe_adapter *adapter = dev->data->dev_private; 5111 5112 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d", 5113 dev->data->port_id); 5114 5115 /* 5116 * VF has no ability to enable/disable HW CRC 5117 * Keep the persistent behavior the same as Host PF 5118 */ 5119 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC 5120 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) { 5121 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip"); 5122 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC; 5123 } 5124 #else 5125 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) { 5126 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip"); 5127 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC; 5128 } 5129 #endif 5130 5131 /* 5132 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 5133 * allocation or vector Rx preconditions we will reset it. 5134 */ 5135 adapter->rx_bulk_alloc_allowed = true; 5136 adapter->rx_vec_allowed = true; 5137 5138 return 0; 5139 } 5140 5141 static int 5142 ixgbevf_dev_start(struct rte_eth_dev *dev) 5143 { 5144 struct ixgbe_hw *hw = 5145 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5146 uint32_t intr_vector = 0; 5147 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5148 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5149 5150 int err, mask = 0; 5151 5152 PMD_INIT_FUNC_TRACE(); 5153 5154 /* Stop the link setup handler before resetting the HW. */ 5155 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 5156 5157 err = hw->mac.ops.reset_hw(hw); 5158 if (err) { 5159 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err); 5160 return err; 5161 } 5162 hw->mac.get_link_status = true; 5163 5164 /* negotiate mailbox API version to use with the PF. */ 5165 ixgbevf_negotiate_api(hw); 5166 5167 ixgbevf_dev_tx_init(dev); 5168 5169 /* This can fail when allocating mbufs for descriptor rings */ 5170 err = ixgbevf_dev_rx_init(dev); 5171 if (err) { 5172 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err); 5173 ixgbe_dev_clear_queues(dev); 5174 return err; 5175 } 5176 5177 /* Set vfta */ 5178 ixgbevf_set_vfta_all(dev, 1); 5179 5180 /* Set HW strip */ 5181 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 5182 ETH_VLAN_EXTEND_MASK; 5183 err = ixgbevf_vlan_offload_config(dev, mask); 5184 if (err) { 5185 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err); 5186 ixgbe_dev_clear_queues(dev); 5187 return err; 5188 } 5189 5190 ixgbevf_dev_rxtx_start(dev); 5191 5192 /* check and configure queue intr-vector mapping */ 5193 if (rte_intr_cap_multiple(intr_handle) && 5194 dev->data->dev_conf.intr_conf.rxq) { 5195 /* According to datasheet, only vector 0/1/2 can be used, 5196 * now only one vector is used for Rx queue 5197 */ 5198 intr_vector = 1; 5199 if (rte_intr_efd_enable(intr_handle, intr_vector)) 5200 return -1; 5201 } 5202 5203 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 5204 intr_handle->intr_vec = 5205 rte_zmalloc("intr_vec", 5206 dev->data->nb_rx_queues * sizeof(int), 0); 5207 if (intr_handle->intr_vec == NULL) { 5208 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 5209 " intr_vec", dev->data->nb_rx_queues); 5210 return -ENOMEM; 5211 } 5212 } 5213 ixgbevf_configure_msix(dev); 5214 5215 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt 5216 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ). 5217 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( ) 5218 * is not cleared, it will fail when following rte_intr_enable( ) tries 5219 * to map Rx queue interrupt to other VFIO vectors. 5220 * So clear uio/vfio intr/evevnfd first to avoid failure. 5221 */ 5222 rte_intr_disable(intr_handle); 5223 5224 rte_intr_enable(intr_handle); 5225 5226 /* Re-enable interrupt for VF */ 5227 ixgbevf_intr_enable(dev); 5228 5229 /* 5230 * Update link status right before return, because it may 5231 * start link configuration process in a separate thread. 5232 */ 5233 ixgbevf_dev_link_update(dev, 0); 5234 5235 return 0; 5236 } 5237 5238 static void 5239 ixgbevf_dev_stop(struct rte_eth_dev *dev) 5240 { 5241 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5242 struct ixgbe_adapter *adapter = dev->data->dev_private; 5243 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5244 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5245 5246 PMD_INIT_FUNC_TRACE(); 5247 5248 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 5249 5250 ixgbevf_intr_disable(dev); 5251 5252 hw->adapter_stopped = 1; 5253 ixgbe_stop_adapter(hw); 5254 5255 /* 5256 * Clear what we set, but we still keep shadow_vfta to 5257 * restore after device starts 5258 */ 5259 ixgbevf_set_vfta_all(dev, 0); 5260 5261 /* Clear stored conf */ 5262 dev->data->scattered_rx = 0; 5263 5264 ixgbe_dev_clear_queues(dev); 5265 5266 /* Clean datapath event and queue/vec mapping */ 5267 rte_intr_efd_disable(intr_handle); 5268 if (intr_handle->intr_vec != NULL) { 5269 rte_free(intr_handle->intr_vec); 5270 intr_handle->intr_vec = NULL; 5271 } 5272 5273 adapter->rss_reta_updated = 0; 5274 } 5275 5276 static void 5277 ixgbevf_dev_close(struct rte_eth_dev *dev) 5278 { 5279 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5280 5281 PMD_INIT_FUNC_TRACE(); 5282 5283 ixgbe_reset_hw(hw); 5284 5285 ixgbevf_dev_stop(dev); 5286 5287 ixgbe_dev_free_queues(dev); 5288 5289 /** 5290 * Remove the VF MAC address ro ensure 5291 * that the VF traffic goes to the PF 5292 * after stop, close and detach of the VF 5293 **/ 5294 ixgbevf_remove_mac_addr(dev, 0); 5295 } 5296 5297 /* 5298 * Reset VF device 5299 */ 5300 static int 5301 ixgbevf_dev_reset(struct rte_eth_dev *dev) 5302 { 5303 int ret; 5304 5305 ret = eth_ixgbevf_dev_uninit(dev); 5306 if (ret) 5307 return ret; 5308 5309 ret = eth_ixgbevf_dev_init(dev); 5310 5311 return ret; 5312 } 5313 5314 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) 5315 { 5316 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5317 struct ixgbe_vfta *shadow_vfta = 5318 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5319 int i = 0, j = 0, vfta = 0, mask = 1; 5320 5321 for (i = 0; i < IXGBE_VFTA_SIZE; i++) { 5322 vfta = shadow_vfta->vfta[i]; 5323 if (vfta) { 5324 mask = 1; 5325 for (j = 0; j < 32; j++) { 5326 if (vfta & mask) 5327 ixgbe_set_vfta(hw, (i<<5)+j, 0, 5328 on, false); 5329 mask <<= 1; 5330 } 5331 } 5332 } 5333 5334 } 5335 5336 static int 5337 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 5338 { 5339 struct ixgbe_hw *hw = 5340 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5341 struct ixgbe_vfta *shadow_vfta = 5342 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5343 uint32_t vid_idx = 0; 5344 uint32_t vid_bit = 0; 5345 int ret = 0; 5346 5347 PMD_INIT_FUNC_TRACE(); 5348 5349 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */ 5350 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false); 5351 if (ret) { 5352 PMD_INIT_LOG(ERR, "Unable to set VF vlan"); 5353 return ret; 5354 } 5355 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 5356 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 5357 5358 /* Save what we set and retore it after device reset */ 5359 if (on) 5360 shadow_vfta->vfta[vid_idx] |= vid_bit; 5361 else 5362 shadow_vfta->vfta[vid_idx] &= ~vid_bit; 5363 5364 return 0; 5365 } 5366 5367 static void 5368 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 5369 { 5370 struct ixgbe_hw *hw = 5371 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5372 uint32_t ctrl; 5373 5374 PMD_INIT_FUNC_TRACE(); 5375 5376 if (queue >= hw->mac.max_rx_queues) 5377 return; 5378 5379 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 5380 if (on) 5381 ctrl |= IXGBE_RXDCTL_VME; 5382 else 5383 ctrl &= ~IXGBE_RXDCTL_VME; 5384 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 5385 5386 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on); 5387 } 5388 5389 static int 5390 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask) 5391 { 5392 struct ixgbe_rx_queue *rxq; 5393 uint16_t i; 5394 int on = 0; 5395 5396 /* VF function only support hw strip feature, others are not support */ 5397 if (mask & ETH_VLAN_STRIP_MASK) { 5398 for (i = 0; i < dev->data->nb_rx_queues; i++) { 5399 rxq = dev->data->rx_queues[i]; 5400 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP); 5401 ixgbevf_vlan_strip_queue_set(dev, i, on); 5402 } 5403 } 5404 5405 return 0; 5406 } 5407 5408 static int 5409 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 5410 { 5411 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 5412 5413 ixgbevf_vlan_offload_config(dev, mask); 5414 5415 return 0; 5416 } 5417 5418 int 5419 ixgbe_vt_check(struct ixgbe_hw *hw) 5420 { 5421 uint32_t reg_val; 5422 5423 /* if Virtualization Technology is enabled */ 5424 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 5425 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) { 5426 PMD_INIT_LOG(ERR, "VT must be enabled for this setting"); 5427 return -1; 5428 } 5429 5430 return 0; 5431 } 5432 5433 static uint32_t 5434 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr) 5435 { 5436 uint32_t vector = 0; 5437 5438 switch (hw->mac.mc_filter_type) { 5439 case 0: /* use bits [47:36] of the address */ 5440 vector = ((uc_addr->addr_bytes[4] >> 4) | 5441 (((uint16_t)uc_addr->addr_bytes[5]) << 4)); 5442 break; 5443 case 1: /* use bits [46:35] of the address */ 5444 vector = ((uc_addr->addr_bytes[4] >> 3) | 5445 (((uint16_t)uc_addr->addr_bytes[5]) << 5)); 5446 break; 5447 case 2: /* use bits [45:34] of the address */ 5448 vector = ((uc_addr->addr_bytes[4] >> 2) | 5449 (((uint16_t)uc_addr->addr_bytes[5]) << 6)); 5450 break; 5451 case 3: /* use bits [43:32] of the address */ 5452 vector = ((uc_addr->addr_bytes[4]) | 5453 (((uint16_t)uc_addr->addr_bytes[5]) << 8)); 5454 break; 5455 default: /* Invalid mc_filter_type */ 5456 break; 5457 } 5458 5459 /* vector can only be 12-bits or boundary will be exceeded */ 5460 vector &= 0xFFF; 5461 return vector; 5462 } 5463 5464 static int 5465 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, 5466 struct rte_ether_addr *mac_addr, uint8_t on) 5467 { 5468 uint32_t vector; 5469 uint32_t uta_idx; 5470 uint32_t reg_val; 5471 uint32_t uta_shift; 5472 uint32_t rc; 5473 const uint32_t ixgbe_uta_idx_mask = 0x7F; 5474 const uint32_t ixgbe_uta_bit_shift = 5; 5475 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1; 5476 const uint32_t bit1 = 0x1; 5477 5478 struct ixgbe_hw *hw = 5479 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5480 struct ixgbe_uta_info *uta_info = 5481 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5482 5483 /* The UTA table only exists on 82599 hardware and newer */ 5484 if (hw->mac.type < ixgbe_mac_82599EB) 5485 return -ENOTSUP; 5486 5487 vector = ixgbe_uta_vector(hw, mac_addr); 5488 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask; 5489 uta_shift = vector & ixgbe_uta_bit_mask; 5490 5491 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0); 5492 if (rc == on) 5493 return 0; 5494 5495 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx)); 5496 if (on) { 5497 uta_info->uta_in_use++; 5498 reg_val |= (bit1 << uta_shift); 5499 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift); 5500 } else { 5501 uta_info->uta_in_use--; 5502 reg_val &= ~(bit1 << uta_shift); 5503 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift); 5504 } 5505 5506 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val); 5507 5508 if (uta_info->uta_in_use > 0) 5509 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 5510 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 5511 else 5512 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 5513 5514 return 0; 5515 } 5516 5517 static int 5518 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) 5519 { 5520 int i; 5521 struct ixgbe_hw *hw = 5522 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5523 struct ixgbe_uta_info *uta_info = 5524 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5525 5526 /* The UTA table only exists on 82599 hardware and newer */ 5527 if (hw->mac.type < ixgbe_mac_82599EB) 5528 return -ENOTSUP; 5529 5530 if (on) { 5531 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5532 uta_info->uta_shadow[i] = ~0; 5533 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); 5534 } 5535 } else { 5536 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5537 uta_info->uta_shadow[i] = 0; 5538 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 5539 } 5540 } 5541 return 0; 5542 5543 } 5544 5545 uint32_t 5546 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val) 5547 { 5548 uint32_t new_val = orig_val; 5549 5550 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG) 5551 new_val |= IXGBE_VMOLR_AUPE; 5552 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC) 5553 new_val |= IXGBE_VMOLR_ROMPE; 5554 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC) 5555 new_val |= IXGBE_VMOLR_ROPE; 5556 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST) 5557 new_val |= IXGBE_VMOLR_BAM; 5558 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST) 5559 new_val |= IXGBE_VMOLR_MPE; 5560 5561 return new_val; 5562 } 5563 5564 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */ 5565 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */ 5566 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */ 5567 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */ 5568 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \ 5569 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \ 5570 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN)) 5571 5572 static int 5573 ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 5574 struct rte_eth_mirror_conf *mirror_conf, 5575 uint8_t rule_id, uint8_t on) 5576 { 5577 uint32_t mr_ctl, vlvf; 5578 uint32_t mp_lsb = 0; 5579 uint32_t mv_msb = 0; 5580 uint32_t mv_lsb = 0; 5581 uint32_t mp_msb = 0; 5582 uint8_t i = 0; 5583 int reg_index = 0; 5584 uint64_t vlan_mask = 0; 5585 5586 const uint8_t pool_mask_offset = 32; 5587 const uint8_t vlan_mask_offset = 32; 5588 const uint8_t dst_pool_offset = 8; 5589 const uint8_t rule_mr_offset = 4; 5590 const uint8_t mirror_rule_mask = 0x0F; 5591 5592 struct ixgbe_mirror_info *mr_info = 5593 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5594 struct ixgbe_hw *hw = 5595 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5596 uint8_t mirror_type = 0; 5597 5598 if (ixgbe_vt_check(hw) < 0) 5599 return -ENOTSUP; 5600 5601 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5602 return -EINVAL; 5603 5604 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) { 5605 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.", 5606 mirror_conf->rule_type); 5607 return -EINVAL; 5608 } 5609 5610 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5611 mirror_type |= IXGBE_MRCTL_VLME; 5612 /* Check if vlan id is valid and find conresponding VLAN ID 5613 * index in VLVF 5614 */ 5615 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) { 5616 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) { 5617 /* search vlan id related pool vlan filter 5618 * index 5619 */ 5620 reg_index = ixgbe_find_vlvf_slot( 5621 hw, 5622 mirror_conf->vlan.vlan_id[i], 5623 false); 5624 if (reg_index < 0) 5625 return -EINVAL; 5626 vlvf = IXGBE_READ_REG(hw, 5627 IXGBE_VLVF(reg_index)); 5628 if ((vlvf & IXGBE_VLVF_VIEN) && 5629 ((vlvf & IXGBE_VLVF_VLANID_MASK) == 5630 mirror_conf->vlan.vlan_id[i])) 5631 vlan_mask |= (1ULL << reg_index); 5632 else 5633 return -EINVAL; 5634 } 5635 } 5636 5637 if (on) { 5638 mv_lsb = vlan_mask & 0xFFFFFFFF; 5639 mv_msb = vlan_mask >> vlan_mask_offset; 5640 5641 mr_info->mr_conf[rule_id].vlan.vlan_mask = 5642 mirror_conf->vlan.vlan_mask; 5643 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) { 5644 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) 5645 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 5646 mirror_conf->vlan.vlan_id[i]; 5647 } 5648 } else { 5649 mv_lsb = 0; 5650 mv_msb = 0; 5651 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0; 5652 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) 5653 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0; 5654 } 5655 } 5656 5657 /** 5658 * if enable pool mirror, write related pool mask register,if disable 5659 * pool mirror, clear PFMRVM register 5660 */ 5661 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5662 mirror_type |= IXGBE_MRCTL_VPME; 5663 if (on) { 5664 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF; 5665 mp_msb = mirror_conf->pool_mask >> pool_mask_offset; 5666 mr_info->mr_conf[rule_id].pool_mask = 5667 mirror_conf->pool_mask; 5668 5669 } else { 5670 mp_lsb = 0; 5671 mp_msb = 0; 5672 mr_info->mr_conf[rule_id].pool_mask = 0; 5673 } 5674 } 5675 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT) 5676 mirror_type |= IXGBE_MRCTL_UPME; 5677 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT) 5678 mirror_type |= IXGBE_MRCTL_DPME; 5679 5680 /* read mirror control register and recalculate it */ 5681 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id)); 5682 5683 if (on) { 5684 mr_ctl |= mirror_type; 5685 mr_ctl &= mirror_rule_mask; 5686 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset; 5687 } else { 5688 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask); 5689 } 5690 5691 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type; 5692 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool; 5693 5694 /* write mirrror control register */ 5695 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5696 5697 /* write pool mirrror control register */ 5698 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5699 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb); 5700 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), 5701 mp_msb); 5702 } 5703 /* write VLAN mirrror control register */ 5704 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5705 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb); 5706 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), 5707 mv_msb); 5708 } 5709 5710 return 0; 5711 } 5712 5713 static int 5714 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id) 5715 { 5716 int mr_ctl = 0; 5717 uint32_t lsb_val = 0; 5718 uint32_t msb_val = 0; 5719 const uint8_t rule_mr_offset = 4; 5720 5721 struct ixgbe_hw *hw = 5722 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5723 struct ixgbe_mirror_info *mr_info = 5724 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5725 5726 if (ixgbe_vt_check(hw) < 0) 5727 return -ENOTSUP; 5728 5729 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5730 return -EINVAL; 5731 5732 memset(&mr_info->mr_conf[rule_id], 0, 5733 sizeof(struct rte_eth_mirror_conf)); 5734 5735 /* clear PFVMCTL register */ 5736 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5737 5738 /* clear pool mask register */ 5739 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val); 5740 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val); 5741 5742 /* clear vlan mask register */ 5743 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val); 5744 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val); 5745 5746 return 0; 5747 } 5748 5749 static int 5750 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5751 { 5752 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5753 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5754 struct ixgbe_interrupt *intr = 5755 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5756 struct ixgbe_hw *hw = 5757 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5758 uint32_t vec = IXGBE_MISC_VEC_ID; 5759 5760 if (rte_intr_allow_others(intr_handle)) 5761 vec = IXGBE_RX_VEC_START; 5762 intr->mask |= (1 << vec); 5763 RTE_SET_USED(queue_id); 5764 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5765 5766 rte_intr_enable(intr_handle); 5767 5768 return 0; 5769 } 5770 5771 static int 5772 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5773 { 5774 struct ixgbe_interrupt *intr = 5775 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5776 struct ixgbe_hw *hw = 5777 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5778 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5779 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5780 uint32_t vec = IXGBE_MISC_VEC_ID; 5781 5782 if (rte_intr_allow_others(intr_handle)) 5783 vec = IXGBE_RX_VEC_START; 5784 intr->mask &= ~(1 << vec); 5785 RTE_SET_USED(queue_id); 5786 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5787 5788 return 0; 5789 } 5790 5791 static int 5792 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5793 { 5794 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5795 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5796 uint32_t mask; 5797 struct ixgbe_hw *hw = 5798 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5799 struct ixgbe_interrupt *intr = 5800 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5801 5802 if (queue_id < 16) { 5803 ixgbe_disable_intr(hw); 5804 intr->mask |= (1 << queue_id); 5805 ixgbe_enable_intr(dev); 5806 } else if (queue_id < 32) { 5807 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5808 mask &= (1 << queue_id); 5809 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5810 } else if (queue_id < 64) { 5811 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5812 mask &= (1 << (queue_id - 32)); 5813 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5814 } 5815 rte_intr_enable(intr_handle); 5816 5817 return 0; 5818 } 5819 5820 static int 5821 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5822 { 5823 uint32_t mask; 5824 struct ixgbe_hw *hw = 5825 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5826 struct ixgbe_interrupt *intr = 5827 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5828 5829 if (queue_id < 16) { 5830 ixgbe_disable_intr(hw); 5831 intr->mask &= ~(1 << queue_id); 5832 ixgbe_enable_intr(dev); 5833 } else if (queue_id < 32) { 5834 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5835 mask &= ~(1 << queue_id); 5836 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5837 } else if (queue_id < 64) { 5838 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5839 mask &= ~(1 << (queue_id - 32)); 5840 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5841 } 5842 5843 return 0; 5844 } 5845 5846 static void 5847 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 5848 uint8_t queue, uint8_t msix_vector) 5849 { 5850 uint32_t tmp, idx; 5851 5852 if (direction == -1) { 5853 /* other causes */ 5854 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5855 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC); 5856 tmp &= ~0xFF; 5857 tmp |= msix_vector; 5858 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp); 5859 } else { 5860 /* rx or tx cause */ 5861 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5862 idx = ((16 * (queue & 1)) + (8 * direction)); 5863 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1)); 5864 tmp &= ~(0xFF << idx); 5865 tmp |= (msix_vector << idx); 5866 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp); 5867 } 5868 } 5869 5870 /** 5871 * set the IVAR registers, mapping interrupt causes to vectors 5872 * @param hw 5873 * pointer to ixgbe_hw struct 5874 * @direction 5875 * 0 for Rx, 1 for Tx, -1 for other causes 5876 * @queue 5877 * queue to map the corresponding interrupt to 5878 * @msix_vector 5879 * the vector to map to the corresponding queue 5880 */ 5881 static void 5882 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 5883 uint8_t queue, uint8_t msix_vector) 5884 { 5885 uint32_t tmp, idx; 5886 5887 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5888 if (hw->mac.type == ixgbe_mac_82598EB) { 5889 if (direction == -1) 5890 direction = 0; 5891 idx = (((direction * 64) + queue) >> 2) & 0x1F; 5892 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx)); 5893 tmp &= ~(0xFF << (8 * (queue & 0x3))); 5894 tmp |= (msix_vector << (8 * (queue & 0x3))); 5895 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp); 5896 } else if ((hw->mac.type == ixgbe_mac_82599EB) || 5897 (hw->mac.type == ixgbe_mac_X540) || 5898 (hw->mac.type == ixgbe_mac_X550)) { 5899 if (direction == -1) { 5900 /* other causes */ 5901 idx = ((queue & 1) * 8); 5902 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC); 5903 tmp &= ~(0xFF << idx); 5904 tmp |= (msix_vector << idx); 5905 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp); 5906 } else { 5907 /* rx or tx causes */ 5908 idx = ((16 * (queue & 1)) + (8 * direction)); 5909 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 5910 tmp &= ~(0xFF << idx); 5911 tmp |= (msix_vector << idx); 5912 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp); 5913 } 5914 } 5915 } 5916 5917 static void 5918 ixgbevf_configure_msix(struct rte_eth_dev *dev) 5919 { 5920 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5921 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5922 struct ixgbe_hw *hw = 5923 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5924 uint32_t q_idx; 5925 uint32_t vector_idx = IXGBE_MISC_VEC_ID; 5926 uint32_t base = IXGBE_MISC_VEC_ID; 5927 5928 /* Configure VF other cause ivar */ 5929 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx); 5930 5931 /* won't configure msix register if no mapping is done 5932 * between intr vector and event fd. 5933 */ 5934 if (!rte_intr_dp_is_en(intr_handle)) 5935 return; 5936 5937 if (rte_intr_allow_others(intr_handle)) { 5938 base = IXGBE_RX_VEC_START; 5939 vector_idx = IXGBE_RX_VEC_START; 5940 } 5941 5942 /* Configure all RX queues of VF */ 5943 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) { 5944 /* Force all queue use vector 0, 5945 * as IXGBE_VF_MAXMSIVECOTR = 1 5946 */ 5947 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx); 5948 intr_handle->intr_vec[q_idx] = vector_idx; 5949 if (vector_idx < base + intr_handle->nb_efd - 1) 5950 vector_idx++; 5951 } 5952 5953 /* As RX queue setting above show, all queues use the vector 0. 5954 * Set only the ITR value of IXGBE_MISC_VEC_ID. 5955 */ 5956 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID), 5957 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 5958 | IXGBE_EITR_CNT_WDIS); 5959 } 5960 5961 /** 5962 * Sets up the hardware to properly generate MSI-X interrupts 5963 * @hw 5964 * board private structure 5965 */ 5966 static void 5967 ixgbe_configure_msix(struct rte_eth_dev *dev) 5968 { 5969 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5970 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5971 struct ixgbe_hw *hw = 5972 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5973 uint32_t queue_id, base = IXGBE_MISC_VEC_ID; 5974 uint32_t vec = IXGBE_MISC_VEC_ID; 5975 uint32_t mask; 5976 uint32_t gpie; 5977 5978 /* won't configure msix register if no mapping is done 5979 * between intr vector and event fd 5980 * but if misx has been enabled already, need to configure 5981 * auto clean, auto mask and throttling. 5982 */ 5983 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 5984 if (!rte_intr_dp_is_en(intr_handle) && 5985 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT))) 5986 return; 5987 5988 if (rte_intr_allow_others(intr_handle)) 5989 vec = base = IXGBE_RX_VEC_START; 5990 5991 /* setup GPIE for MSI-x mode */ 5992 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 5993 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5994 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME; 5995 /* auto clearing and auto setting corresponding bits in EIMS 5996 * when MSI-X interrupt is triggered 5997 */ 5998 if (hw->mac.type == ixgbe_mac_82598EB) { 5999 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 6000 } else { 6001 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 6002 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 6003 } 6004 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 6005 6006 /* Populate the IVAR table and set the ITR values to the 6007 * corresponding register. 6008 */ 6009 if (rte_intr_dp_is_en(intr_handle)) { 6010 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; 6011 queue_id++) { 6012 /* by default, 1:1 mapping */ 6013 ixgbe_set_ivar_map(hw, 0, queue_id, vec); 6014 intr_handle->intr_vec[queue_id] = vec; 6015 if (vec < base + intr_handle->nb_efd - 1) 6016 vec++; 6017 } 6018 6019 switch (hw->mac.type) { 6020 case ixgbe_mac_82598EB: 6021 ixgbe_set_ivar_map(hw, -1, 6022 IXGBE_IVAR_OTHER_CAUSES_INDEX, 6023 IXGBE_MISC_VEC_ID); 6024 break; 6025 case ixgbe_mac_82599EB: 6026 case ixgbe_mac_X540: 6027 case ixgbe_mac_X550: 6028 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID); 6029 break; 6030 default: 6031 break; 6032 } 6033 } 6034 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID), 6035 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 6036 | IXGBE_EITR_CNT_WDIS); 6037 6038 /* set up to autoclear timer, and the vectors */ 6039 mask = IXGBE_EIMS_ENABLE_MASK; 6040 mask &= ~(IXGBE_EIMS_OTHER | 6041 IXGBE_EIMS_MAILBOX | 6042 IXGBE_EIMS_LSC); 6043 6044 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask); 6045 } 6046 6047 int 6048 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, 6049 uint16_t queue_idx, uint16_t tx_rate) 6050 { 6051 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6052 struct rte_eth_rxmode *rxmode; 6053 uint32_t rf_dec, rf_int; 6054 uint32_t bcnrc_val; 6055 uint16_t link_speed = dev->data->dev_link.link_speed; 6056 6057 if (queue_idx >= hw->mac.max_tx_queues) 6058 return -EINVAL; 6059 6060 if (tx_rate != 0) { 6061 /* Calculate the rate factor values to set */ 6062 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate; 6063 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate; 6064 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate; 6065 6066 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA; 6067 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) & 6068 IXGBE_RTTBCNRC_RF_INT_MASK_M); 6069 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK); 6070 } else { 6071 bcnrc_val = 0; 6072 } 6073 6074 rxmode = &dev->data->dev_conf.rxmode; 6075 /* 6076 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 6077 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise 6078 * set as 0x4. 6079 */ 6080 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) && 6081 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE)) 6082 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 6083 IXGBE_MMW_SIZE_JUMBO_FRAME); 6084 else 6085 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 6086 IXGBE_MMW_SIZE_DEFAULT); 6087 6088 /* Set RTTBCNRC of queue X */ 6089 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx); 6090 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 6091 IXGBE_WRITE_FLUSH(hw); 6092 6093 return 0; 6094 } 6095 6096 static int 6097 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 6098 __attribute__((unused)) uint32_t index, 6099 __attribute__((unused)) uint32_t pool) 6100 { 6101 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6102 int diag; 6103 6104 /* 6105 * On a 82599 VF, adding again the same MAC addr is not an idempotent 6106 * operation. Trap this case to avoid exhausting the [very limited] 6107 * set of PF resources used to store VF MAC addresses. 6108 */ 6109 if (memcmp(hw->mac.perm_addr, mac_addr, 6110 sizeof(struct rte_ether_addr)) == 0) 6111 return -1; 6112 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6113 if (diag != 0) 6114 PMD_DRV_LOG(ERR, "Unable to add MAC address " 6115 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d", 6116 mac_addr->addr_bytes[0], 6117 mac_addr->addr_bytes[1], 6118 mac_addr->addr_bytes[2], 6119 mac_addr->addr_bytes[3], 6120 mac_addr->addr_bytes[4], 6121 mac_addr->addr_bytes[5], 6122 diag); 6123 return diag; 6124 } 6125 6126 static void 6127 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index) 6128 { 6129 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6130 struct rte_ether_addr *perm_addr = 6131 (struct rte_ether_addr *)hw->mac.perm_addr; 6132 struct rte_ether_addr *mac_addr; 6133 uint32_t i; 6134 int diag; 6135 6136 /* 6137 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does 6138 * not support the deletion of a given MAC address. 6139 * Instead, it imposes to delete all MAC addresses, then to add again 6140 * all MAC addresses with the exception of the one to be deleted. 6141 */ 6142 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL); 6143 6144 /* 6145 * Add again all MAC addresses, with the exception of the deleted one 6146 * and of the permanent MAC address. 6147 */ 6148 for (i = 0, mac_addr = dev->data->mac_addrs; 6149 i < hw->mac.num_rar_entries; i++, mac_addr++) { 6150 /* Skip the deleted MAC address */ 6151 if (i == index) 6152 continue; 6153 /* Skip NULL MAC addresses */ 6154 if (rte_is_zero_ether_addr(mac_addr)) 6155 continue; 6156 /* Skip the permanent MAC address */ 6157 if (memcmp(perm_addr, mac_addr, 6158 sizeof(struct rte_ether_addr)) == 0) 6159 continue; 6160 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6161 if (diag != 0) 6162 PMD_DRV_LOG(ERR, 6163 "Adding again MAC address " 6164 "%02x:%02x:%02x:%02x:%02x:%02x failed " 6165 "diag=%d", 6166 mac_addr->addr_bytes[0], 6167 mac_addr->addr_bytes[1], 6168 mac_addr->addr_bytes[2], 6169 mac_addr->addr_bytes[3], 6170 mac_addr->addr_bytes[4], 6171 mac_addr->addr_bytes[5], 6172 diag); 6173 } 6174 } 6175 6176 static int 6177 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 6178 struct rte_ether_addr *addr) 6179 { 6180 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6181 6182 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0); 6183 6184 return 0; 6185 } 6186 6187 int 6188 ixgbe_syn_filter_set(struct rte_eth_dev *dev, 6189 struct rte_eth_syn_filter *filter, 6190 bool add) 6191 { 6192 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6193 struct ixgbe_filter_info *filter_info = 6194 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6195 uint32_t syn_info; 6196 uint32_t synqf; 6197 6198 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6199 return -EINVAL; 6200 6201 syn_info = filter_info->syn_info; 6202 6203 if (add) { 6204 if (syn_info & IXGBE_SYN_FILTER_ENABLE) 6205 return -EINVAL; 6206 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) & 6207 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE); 6208 6209 if (filter->hig_pri) 6210 synqf |= IXGBE_SYN_FILTER_SYNQFP; 6211 else 6212 synqf &= ~IXGBE_SYN_FILTER_SYNQFP; 6213 } else { 6214 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6215 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE)) 6216 return -ENOENT; 6217 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE); 6218 } 6219 6220 filter_info->syn_info = synqf; 6221 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 6222 IXGBE_WRITE_FLUSH(hw); 6223 return 0; 6224 } 6225 6226 static int 6227 ixgbe_syn_filter_get(struct rte_eth_dev *dev, 6228 struct rte_eth_syn_filter *filter) 6229 { 6230 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6231 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6232 6233 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 6234 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0; 6235 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1); 6236 return 0; 6237 } 6238 return -ENOENT; 6239 } 6240 6241 static int 6242 ixgbe_syn_filter_handle(struct rte_eth_dev *dev, 6243 enum rte_filter_op filter_op, 6244 void *arg) 6245 { 6246 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6247 int ret; 6248 6249 MAC_TYPE_FILTER_SUP(hw->mac.type); 6250 6251 if (filter_op == RTE_ETH_FILTER_NOP) 6252 return 0; 6253 6254 if (arg == NULL) { 6255 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u", 6256 filter_op); 6257 return -EINVAL; 6258 } 6259 6260 switch (filter_op) { 6261 case RTE_ETH_FILTER_ADD: 6262 ret = ixgbe_syn_filter_set(dev, 6263 (struct rte_eth_syn_filter *)arg, 6264 TRUE); 6265 break; 6266 case RTE_ETH_FILTER_DELETE: 6267 ret = ixgbe_syn_filter_set(dev, 6268 (struct rte_eth_syn_filter *)arg, 6269 FALSE); 6270 break; 6271 case RTE_ETH_FILTER_GET: 6272 ret = ixgbe_syn_filter_get(dev, 6273 (struct rte_eth_syn_filter *)arg); 6274 break; 6275 default: 6276 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op); 6277 ret = -EINVAL; 6278 break; 6279 } 6280 6281 return ret; 6282 } 6283 6284 6285 static inline enum ixgbe_5tuple_protocol 6286 convert_protocol_type(uint8_t protocol_value) 6287 { 6288 if (protocol_value == IPPROTO_TCP) 6289 return IXGBE_FILTER_PROTOCOL_TCP; 6290 else if (protocol_value == IPPROTO_UDP) 6291 return IXGBE_FILTER_PROTOCOL_UDP; 6292 else if (protocol_value == IPPROTO_SCTP) 6293 return IXGBE_FILTER_PROTOCOL_SCTP; 6294 else 6295 return IXGBE_FILTER_PROTOCOL_NONE; 6296 } 6297 6298 /* inject a 5-tuple filter to HW */ 6299 static inline void 6300 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev, 6301 struct ixgbe_5tuple_filter *filter) 6302 { 6303 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6304 int i; 6305 uint32_t ftqf, sdpqf; 6306 uint32_t l34timir = 0; 6307 uint8_t mask = 0xff; 6308 6309 i = filter->index; 6310 6311 sdpqf = (uint32_t)(filter->filter_info.dst_port << 6312 IXGBE_SDPQF_DSTPORT_SHIFT); 6313 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT); 6314 6315 ftqf = (uint32_t)(filter->filter_info.proto & 6316 IXGBE_FTQF_PROTOCOL_MASK); 6317 ftqf |= (uint32_t)((filter->filter_info.priority & 6318 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT); 6319 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */ 6320 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK; 6321 if (filter->filter_info.dst_ip_mask == 0) 6322 mask &= IXGBE_FTQF_DEST_ADDR_MASK; 6323 if (filter->filter_info.src_port_mask == 0) 6324 mask &= IXGBE_FTQF_SOURCE_PORT_MASK; 6325 if (filter->filter_info.dst_port_mask == 0) 6326 mask &= IXGBE_FTQF_DEST_PORT_MASK; 6327 if (filter->filter_info.proto_mask == 0) 6328 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK; 6329 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT; 6330 ftqf |= IXGBE_FTQF_POOL_MASK_EN; 6331 ftqf |= IXGBE_FTQF_QUEUE_ENABLE; 6332 6333 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip); 6334 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip); 6335 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf); 6336 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf); 6337 6338 l34timir |= IXGBE_L34T_IMIR_RESERVE; 6339 l34timir |= (uint32_t)(filter->queue << 6340 IXGBE_L34T_IMIR_QUEUE_SHIFT); 6341 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir); 6342 } 6343 6344 /* 6345 * add a 5tuple filter 6346 * 6347 * @param 6348 * dev: Pointer to struct rte_eth_dev. 6349 * index: the index the filter allocates. 6350 * filter: ponter to the filter that will be added. 6351 * rx_queue: the queue id the filter assigned to. 6352 * 6353 * @return 6354 * - On success, zero. 6355 * - On failure, a negative value. 6356 */ 6357 static int 6358 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 6359 struct ixgbe_5tuple_filter *filter) 6360 { 6361 struct ixgbe_filter_info *filter_info = 6362 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6363 int i, idx, shift; 6364 6365 /* 6366 * look for an unused 5tuple filter index, 6367 * and insert the filter to list. 6368 */ 6369 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) { 6370 idx = i / (sizeof(uint32_t) * NBBY); 6371 shift = i % (sizeof(uint32_t) * NBBY); 6372 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) { 6373 filter_info->fivetuple_mask[idx] |= 1 << shift; 6374 filter->index = i; 6375 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list, 6376 filter, 6377 entries); 6378 break; 6379 } 6380 } 6381 if (i >= IXGBE_MAX_FTQF_FILTERS) { 6382 PMD_DRV_LOG(ERR, "5tuple filters are full."); 6383 return -ENOSYS; 6384 } 6385 6386 ixgbe_inject_5tuple_filter(dev, filter); 6387 6388 return 0; 6389 } 6390 6391 /* 6392 * remove a 5tuple filter 6393 * 6394 * @param 6395 * dev: Pointer to struct rte_eth_dev. 6396 * filter: the pointer of the filter will be removed. 6397 */ 6398 static void 6399 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 6400 struct ixgbe_5tuple_filter *filter) 6401 { 6402 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6403 struct ixgbe_filter_info *filter_info = 6404 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6405 uint16_t index = filter->index; 6406 6407 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &= 6408 ~(1 << (index % (sizeof(uint32_t) * NBBY))); 6409 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries); 6410 rte_free(filter); 6411 6412 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0); 6413 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0); 6414 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0); 6415 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0); 6416 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0); 6417 } 6418 6419 static int 6420 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 6421 { 6422 struct ixgbe_hw *hw; 6423 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD; 6424 struct rte_eth_dev_data *dev_data = dev->data; 6425 6426 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6427 6428 if (mtu < RTE_ETHER_MIN_MTU || 6429 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN) 6430 return -EINVAL; 6431 6432 /* If device is started, refuse mtu that requires the support of 6433 * scattered packets when this feature has not been enabled before. 6434 */ 6435 if (dev_data->dev_started && !dev_data->scattered_rx && 6436 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE > 6437 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 6438 PMD_INIT_LOG(ERR, "Stop port first."); 6439 return -EINVAL; 6440 } 6441 6442 /* 6443 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU 6444 * request of the version 2.0 of the mailbox API. 6445 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0 6446 * of the mailbox API. 6447 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers 6448 * prior to 3.11.33 which contains the following change: 6449 * "ixgbe: Enable jumbo frames support w/ SR-IOV" 6450 */ 6451 ixgbevf_rlpml_set_vf(hw, max_frame); 6452 6453 /* update max frame size */ 6454 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame; 6455 return 0; 6456 } 6457 6458 static inline struct ixgbe_5tuple_filter * 6459 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list, 6460 struct ixgbe_5tuple_filter_info *key) 6461 { 6462 struct ixgbe_5tuple_filter *it; 6463 6464 TAILQ_FOREACH(it, filter_list, entries) { 6465 if (memcmp(key, &it->filter_info, 6466 sizeof(struct ixgbe_5tuple_filter_info)) == 0) { 6467 return it; 6468 } 6469 } 6470 return NULL; 6471 } 6472 6473 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/ 6474 static inline int 6475 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter, 6476 struct ixgbe_5tuple_filter_info *filter_info) 6477 { 6478 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM || 6479 filter->priority > IXGBE_5TUPLE_MAX_PRI || 6480 filter->priority < IXGBE_5TUPLE_MIN_PRI) 6481 return -EINVAL; 6482 6483 switch (filter->dst_ip_mask) { 6484 case UINT32_MAX: 6485 filter_info->dst_ip_mask = 0; 6486 filter_info->dst_ip = filter->dst_ip; 6487 break; 6488 case 0: 6489 filter_info->dst_ip_mask = 1; 6490 break; 6491 default: 6492 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 6493 return -EINVAL; 6494 } 6495 6496 switch (filter->src_ip_mask) { 6497 case UINT32_MAX: 6498 filter_info->src_ip_mask = 0; 6499 filter_info->src_ip = filter->src_ip; 6500 break; 6501 case 0: 6502 filter_info->src_ip_mask = 1; 6503 break; 6504 default: 6505 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 6506 return -EINVAL; 6507 } 6508 6509 switch (filter->dst_port_mask) { 6510 case UINT16_MAX: 6511 filter_info->dst_port_mask = 0; 6512 filter_info->dst_port = filter->dst_port; 6513 break; 6514 case 0: 6515 filter_info->dst_port_mask = 1; 6516 break; 6517 default: 6518 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 6519 return -EINVAL; 6520 } 6521 6522 switch (filter->src_port_mask) { 6523 case UINT16_MAX: 6524 filter_info->src_port_mask = 0; 6525 filter_info->src_port = filter->src_port; 6526 break; 6527 case 0: 6528 filter_info->src_port_mask = 1; 6529 break; 6530 default: 6531 PMD_DRV_LOG(ERR, "invalid src_port mask."); 6532 return -EINVAL; 6533 } 6534 6535 switch (filter->proto_mask) { 6536 case UINT8_MAX: 6537 filter_info->proto_mask = 0; 6538 filter_info->proto = 6539 convert_protocol_type(filter->proto); 6540 break; 6541 case 0: 6542 filter_info->proto_mask = 1; 6543 break; 6544 default: 6545 PMD_DRV_LOG(ERR, "invalid protocol mask."); 6546 return -EINVAL; 6547 } 6548 6549 filter_info->priority = (uint8_t)filter->priority; 6550 return 0; 6551 } 6552 6553 /* 6554 * add or delete a ntuple filter 6555 * 6556 * @param 6557 * dev: Pointer to struct rte_eth_dev. 6558 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6559 * add: if true, add filter, if false, remove filter 6560 * 6561 * @return 6562 * - On success, zero. 6563 * - On failure, a negative value. 6564 */ 6565 int 6566 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 6567 struct rte_eth_ntuple_filter *ntuple_filter, 6568 bool add) 6569 { 6570 struct ixgbe_filter_info *filter_info = 6571 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6572 struct ixgbe_5tuple_filter_info filter_5tuple; 6573 struct ixgbe_5tuple_filter *filter; 6574 int ret; 6575 6576 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6577 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6578 return -EINVAL; 6579 } 6580 6581 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6582 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6583 if (ret < 0) 6584 return ret; 6585 6586 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6587 &filter_5tuple); 6588 if (filter != NULL && add) { 6589 PMD_DRV_LOG(ERR, "filter exists."); 6590 return -EEXIST; 6591 } 6592 if (filter == NULL && !add) { 6593 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6594 return -ENOENT; 6595 } 6596 6597 if (add) { 6598 filter = rte_zmalloc("ixgbe_5tuple_filter", 6599 sizeof(struct ixgbe_5tuple_filter), 0); 6600 if (filter == NULL) 6601 return -ENOMEM; 6602 rte_memcpy(&filter->filter_info, 6603 &filter_5tuple, 6604 sizeof(struct ixgbe_5tuple_filter_info)); 6605 filter->queue = ntuple_filter->queue; 6606 ret = ixgbe_add_5tuple_filter(dev, filter); 6607 if (ret < 0) { 6608 rte_free(filter); 6609 return ret; 6610 } 6611 } else 6612 ixgbe_remove_5tuple_filter(dev, filter); 6613 6614 return 0; 6615 } 6616 6617 /* 6618 * get a ntuple filter 6619 * 6620 * @param 6621 * dev: Pointer to struct rte_eth_dev. 6622 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6623 * 6624 * @return 6625 * - On success, zero. 6626 * - On failure, a negative value. 6627 */ 6628 static int 6629 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev, 6630 struct rte_eth_ntuple_filter *ntuple_filter) 6631 { 6632 struct ixgbe_filter_info *filter_info = 6633 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6634 struct ixgbe_5tuple_filter_info filter_5tuple; 6635 struct ixgbe_5tuple_filter *filter; 6636 int ret; 6637 6638 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6639 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6640 return -EINVAL; 6641 } 6642 6643 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6644 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6645 if (ret < 0) 6646 return ret; 6647 6648 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6649 &filter_5tuple); 6650 if (filter == NULL) { 6651 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6652 return -ENOENT; 6653 } 6654 ntuple_filter->queue = filter->queue; 6655 return 0; 6656 } 6657 6658 /* 6659 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter. 6660 * @dev: pointer to rte_eth_dev structure 6661 * @filter_op:operation will be taken. 6662 * @arg: a pointer to specific structure corresponding to the filter_op 6663 * 6664 * @return 6665 * - On success, zero. 6666 * - On failure, a negative value. 6667 */ 6668 static int 6669 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev, 6670 enum rte_filter_op filter_op, 6671 void *arg) 6672 { 6673 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6674 int ret; 6675 6676 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type); 6677 6678 if (filter_op == RTE_ETH_FILTER_NOP) 6679 return 0; 6680 6681 if (arg == NULL) { 6682 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 6683 filter_op); 6684 return -EINVAL; 6685 } 6686 6687 switch (filter_op) { 6688 case RTE_ETH_FILTER_ADD: 6689 ret = ixgbe_add_del_ntuple_filter(dev, 6690 (struct rte_eth_ntuple_filter *)arg, 6691 TRUE); 6692 break; 6693 case RTE_ETH_FILTER_DELETE: 6694 ret = ixgbe_add_del_ntuple_filter(dev, 6695 (struct rte_eth_ntuple_filter *)arg, 6696 FALSE); 6697 break; 6698 case RTE_ETH_FILTER_GET: 6699 ret = ixgbe_get_ntuple_filter(dev, 6700 (struct rte_eth_ntuple_filter *)arg); 6701 break; 6702 default: 6703 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 6704 ret = -EINVAL; 6705 break; 6706 } 6707 return ret; 6708 } 6709 6710 int 6711 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 6712 struct rte_eth_ethertype_filter *filter, 6713 bool add) 6714 { 6715 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6716 struct ixgbe_filter_info *filter_info = 6717 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6718 uint32_t etqf = 0; 6719 uint32_t etqs = 0; 6720 int ret; 6721 struct ixgbe_ethertype_filter ethertype_filter; 6722 6723 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6724 return -EINVAL; 6725 6726 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 || 6727 filter->ether_type == RTE_ETHER_TYPE_IPV6) { 6728 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in" 6729 " ethertype filter.", filter->ether_type); 6730 return -EINVAL; 6731 } 6732 6733 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) { 6734 PMD_DRV_LOG(ERR, "mac compare is unsupported."); 6735 return -EINVAL; 6736 } 6737 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) { 6738 PMD_DRV_LOG(ERR, "drop option is unsupported."); 6739 return -EINVAL; 6740 } 6741 6742 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6743 if (ret >= 0 && add) { 6744 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.", 6745 filter->ether_type); 6746 return -EEXIST; 6747 } 6748 if (ret < 0 && !add) { 6749 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6750 filter->ether_type); 6751 return -ENOENT; 6752 } 6753 6754 if (add) { 6755 etqf = IXGBE_ETQF_FILTER_EN; 6756 etqf |= (uint32_t)filter->ether_type; 6757 etqs |= (uint32_t)((filter->queue << 6758 IXGBE_ETQS_RX_QUEUE_SHIFT) & 6759 IXGBE_ETQS_RX_QUEUE); 6760 etqs |= IXGBE_ETQS_QUEUE_EN; 6761 6762 ethertype_filter.ethertype = filter->ether_type; 6763 ethertype_filter.etqf = etqf; 6764 ethertype_filter.etqs = etqs; 6765 ethertype_filter.conf = FALSE; 6766 ret = ixgbe_ethertype_filter_insert(filter_info, 6767 ðertype_filter); 6768 if (ret < 0) { 6769 PMD_DRV_LOG(ERR, "ethertype filters are full."); 6770 return -ENOSPC; 6771 } 6772 } else { 6773 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret); 6774 if (ret < 0) 6775 return -ENOSYS; 6776 } 6777 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf); 6778 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs); 6779 IXGBE_WRITE_FLUSH(hw); 6780 6781 return 0; 6782 } 6783 6784 static int 6785 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, 6786 struct rte_eth_ethertype_filter *filter) 6787 { 6788 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6789 struct ixgbe_filter_info *filter_info = 6790 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6791 uint32_t etqf, etqs; 6792 int ret; 6793 6794 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6795 if (ret < 0) { 6796 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6797 filter->ether_type); 6798 return -ENOENT; 6799 } 6800 6801 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret)); 6802 if (etqf & IXGBE_ETQF_FILTER_EN) { 6803 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret)); 6804 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE; 6805 filter->flags = 0; 6806 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> 6807 IXGBE_ETQS_RX_QUEUE_SHIFT; 6808 return 0; 6809 } 6810 return -ENOENT; 6811 } 6812 6813 /* 6814 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter. 6815 * @dev: pointer to rte_eth_dev structure 6816 * @filter_op:operation will be taken. 6817 * @arg: a pointer to specific structure corresponding to the filter_op 6818 */ 6819 static int 6820 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev, 6821 enum rte_filter_op filter_op, 6822 void *arg) 6823 { 6824 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6825 int ret; 6826 6827 MAC_TYPE_FILTER_SUP(hw->mac.type); 6828 6829 if (filter_op == RTE_ETH_FILTER_NOP) 6830 return 0; 6831 6832 if (arg == NULL) { 6833 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 6834 filter_op); 6835 return -EINVAL; 6836 } 6837 6838 switch (filter_op) { 6839 case RTE_ETH_FILTER_ADD: 6840 ret = ixgbe_add_del_ethertype_filter(dev, 6841 (struct rte_eth_ethertype_filter *)arg, 6842 TRUE); 6843 break; 6844 case RTE_ETH_FILTER_DELETE: 6845 ret = ixgbe_add_del_ethertype_filter(dev, 6846 (struct rte_eth_ethertype_filter *)arg, 6847 FALSE); 6848 break; 6849 case RTE_ETH_FILTER_GET: 6850 ret = ixgbe_get_ethertype_filter(dev, 6851 (struct rte_eth_ethertype_filter *)arg); 6852 break; 6853 default: 6854 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 6855 ret = -EINVAL; 6856 break; 6857 } 6858 return ret; 6859 } 6860 6861 static int 6862 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 6863 enum rte_filter_type filter_type, 6864 enum rte_filter_op filter_op, 6865 void *arg) 6866 { 6867 int ret = 0; 6868 6869 switch (filter_type) { 6870 case RTE_ETH_FILTER_NTUPLE: 6871 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg); 6872 break; 6873 case RTE_ETH_FILTER_ETHERTYPE: 6874 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg); 6875 break; 6876 case RTE_ETH_FILTER_SYN: 6877 ret = ixgbe_syn_filter_handle(dev, filter_op, arg); 6878 break; 6879 case RTE_ETH_FILTER_FDIR: 6880 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg); 6881 break; 6882 case RTE_ETH_FILTER_L2_TUNNEL: 6883 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg); 6884 break; 6885 case RTE_ETH_FILTER_GENERIC: 6886 if (filter_op != RTE_ETH_FILTER_GET) 6887 return -EINVAL; 6888 *(const void **)arg = &ixgbe_flow_ops; 6889 break; 6890 default: 6891 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 6892 filter_type); 6893 ret = -EINVAL; 6894 break; 6895 } 6896 6897 return ret; 6898 } 6899 6900 static u8 * 6901 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw, 6902 u8 **mc_addr_ptr, u32 *vmdq) 6903 { 6904 u8 *mc_addr; 6905 6906 *vmdq = 0; 6907 mc_addr = *mc_addr_ptr; 6908 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr)); 6909 return mc_addr; 6910 } 6911 6912 static int 6913 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 6914 struct rte_ether_addr *mc_addr_set, 6915 uint32_t nb_mc_addr) 6916 { 6917 struct ixgbe_hw *hw; 6918 u8 *mc_addr_list; 6919 6920 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6921 mc_addr_list = (u8 *)mc_addr_set; 6922 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr, 6923 ixgbe_dev_addr_list_itr, TRUE); 6924 } 6925 6926 static uint64_t 6927 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev) 6928 { 6929 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6930 uint64_t systime_cycles; 6931 6932 switch (hw->mac.type) { 6933 case ixgbe_mac_X550: 6934 case ixgbe_mac_X550EM_x: 6935 case ixgbe_mac_X550EM_a: 6936 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */ 6937 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 6938 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 6939 * NSEC_PER_SEC; 6940 break; 6941 default: 6942 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 6943 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 6944 << 32; 6945 } 6946 6947 return systime_cycles; 6948 } 6949 6950 static uint64_t 6951 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) 6952 { 6953 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6954 uint64_t rx_tstamp_cycles; 6955 6956 switch (hw->mac.type) { 6957 case ixgbe_mac_X550: 6958 case ixgbe_mac_X550EM_x: 6959 case ixgbe_mac_X550EM_a: 6960 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 6961 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 6962 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 6963 * NSEC_PER_SEC; 6964 break; 6965 default: 6966 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 6967 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 6968 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 6969 << 32; 6970 } 6971 6972 return rx_tstamp_cycles; 6973 } 6974 6975 static uint64_t 6976 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 6977 { 6978 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6979 uint64_t tx_tstamp_cycles; 6980 6981 switch (hw->mac.type) { 6982 case ixgbe_mac_X550: 6983 case ixgbe_mac_X550EM_x: 6984 case ixgbe_mac_X550EM_a: 6985 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 6986 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 6987 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 6988 * NSEC_PER_SEC; 6989 break; 6990 default: 6991 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 6992 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 6993 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 6994 << 32; 6995 } 6996 6997 return tx_tstamp_cycles; 6998 } 6999 7000 static void 7001 ixgbe_start_timecounters(struct rte_eth_dev *dev) 7002 { 7003 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7004 struct ixgbe_adapter *adapter = dev->data->dev_private; 7005 struct rte_eth_link link; 7006 uint32_t incval = 0; 7007 uint32_t shift = 0; 7008 7009 /* Get current link speed. */ 7010 ixgbe_dev_link_update(dev, 1); 7011 rte_eth_linkstatus_get(dev, &link); 7012 7013 switch (link.link_speed) { 7014 case ETH_SPEED_NUM_100M: 7015 incval = IXGBE_INCVAL_100; 7016 shift = IXGBE_INCVAL_SHIFT_100; 7017 break; 7018 case ETH_SPEED_NUM_1G: 7019 incval = IXGBE_INCVAL_1GB; 7020 shift = IXGBE_INCVAL_SHIFT_1GB; 7021 break; 7022 case ETH_SPEED_NUM_10G: 7023 default: 7024 incval = IXGBE_INCVAL_10GB; 7025 shift = IXGBE_INCVAL_SHIFT_10GB; 7026 break; 7027 } 7028 7029 switch (hw->mac.type) { 7030 case ixgbe_mac_X550: 7031 case ixgbe_mac_X550EM_x: 7032 case ixgbe_mac_X550EM_a: 7033 /* Independent of link speed. */ 7034 incval = 1; 7035 /* Cycles read will be interpreted as ns. */ 7036 shift = 0; 7037 /* Fall-through */ 7038 case ixgbe_mac_X540: 7039 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval); 7040 break; 7041 case ixgbe_mac_82599EB: 7042 incval >>= IXGBE_INCVAL_SHIFT_82599; 7043 shift -= IXGBE_INCVAL_SHIFT_82599; 7044 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 7045 (1 << IXGBE_INCPER_SHIFT_82599) | incval); 7046 break; 7047 default: 7048 /* Not supported. */ 7049 return; 7050 } 7051 7052 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 7053 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 7054 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 7055 7056 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 7057 adapter->systime_tc.cc_shift = shift; 7058 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; 7059 7060 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 7061 adapter->rx_tstamp_tc.cc_shift = shift; 7062 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 7063 7064 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 7065 adapter->tx_tstamp_tc.cc_shift = shift; 7066 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 7067 } 7068 7069 static int 7070 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 7071 { 7072 struct ixgbe_adapter *adapter = dev->data->dev_private; 7073 7074 adapter->systime_tc.nsec += delta; 7075 adapter->rx_tstamp_tc.nsec += delta; 7076 adapter->tx_tstamp_tc.nsec += delta; 7077 7078 return 0; 7079 } 7080 7081 static int 7082 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 7083 { 7084 uint64_t ns; 7085 struct ixgbe_adapter *adapter = dev->data->dev_private; 7086 7087 ns = rte_timespec_to_ns(ts); 7088 /* Set the timecounters to a new value. */ 7089 adapter->systime_tc.nsec = ns; 7090 adapter->rx_tstamp_tc.nsec = ns; 7091 adapter->tx_tstamp_tc.nsec = ns; 7092 7093 return 0; 7094 } 7095 7096 static int 7097 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 7098 { 7099 uint64_t ns, systime_cycles; 7100 struct ixgbe_adapter *adapter = dev->data->dev_private; 7101 7102 systime_cycles = ixgbe_read_systime_cyclecounter(dev); 7103 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 7104 *ts = rte_ns_to_timespec(ns); 7105 7106 return 0; 7107 } 7108 7109 static int 7110 ixgbe_timesync_enable(struct rte_eth_dev *dev) 7111 { 7112 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7113 uint32_t tsync_ctl; 7114 uint32_t tsauxc; 7115 7116 /* Stop the timesync system time. */ 7117 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0); 7118 /* Reset the timesync system time value. */ 7119 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0); 7120 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0); 7121 7122 /* Enable system time for platforms where it isn't on by default. */ 7123 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC); 7124 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME; 7125 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc); 7126 7127 ixgbe_start_timecounters(dev); 7128 7129 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7130 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 7131 (RTE_ETHER_TYPE_1588 | 7132 IXGBE_ETQF_FILTER_EN | 7133 IXGBE_ETQF_1588)); 7134 7135 /* Enable timestamping of received PTP packets. */ 7136 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7137 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED; 7138 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7139 7140 /* Enable timestamping of transmitted PTP packets. */ 7141 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7142 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED; 7143 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7144 7145 IXGBE_WRITE_FLUSH(hw); 7146 7147 return 0; 7148 } 7149 7150 static int 7151 ixgbe_timesync_disable(struct rte_eth_dev *dev) 7152 { 7153 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7154 uint32_t tsync_ctl; 7155 7156 /* Disable timestamping of transmitted PTP packets. */ 7157 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7158 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED; 7159 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7160 7161 /* Disable timestamping of received PTP packets. */ 7162 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7163 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED; 7164 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7165 7166 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7167 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0); 7168 7169 /* Stop incrementating the System Time registers. */ 7170 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0); 7171 7172 return 0; 7173 } 7174 7175 static int 7176 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 7177 struct timespec *timestamp, 7178 uint32_t flags __rte_unused) 7179 { 7180 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7181 struct ixgbe_adapter *adapter = dev->data->dev_private; 7182 uint32_t tsync_rxctl; 7183 uint64_t rx_tstamp_cycles; 7184 uint64_t ns; 7185 7186 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7187 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0) 7188 return -EINVAL; 7189 7190 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev); 7191 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 7192 *timestamp = rte_ns_to_timespec(ns); 7193 7194 return 0; 7195 } 7196 7197 static int 7198 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 7199 struct timespec *timestamp) 7200 { 7201 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7202 struct ixgbe_adapter *adapter = dev->data->dev_private; 7203 uint32_t tsync_txctl; 7204 uint64_t tx_tstamp_cycles; 7205 uint64_t ns; 7206 7207 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7208 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0) 7209 return -EINVAL; 7210 7211 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev); 7212 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 7213 *timestamp = rte_ns_to_timespec(ns); 7214 7215 return 0; 7216 } 7217 7218 static int 7219 ixgbe_get_reg_length(struct rte_eth_dev *dev) 7220 { 7221 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7222 int count = 0; 7223 int g_ind = 0; 7224 const struct reg_info *reg_group; 7225 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7226 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7227 7228 while ((reg_group = reg_set[g_ind++])) 7229 count += ixgbe_regs_group_count(reg_group); 7230 7231 return count; 7232 } 7233 7234 static int 7235 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused) 7236 { 7237 int count = 0; 7238 int g_ind = 0; 7239 const struct reg_info *reg_group; 7240 7241 while ((reg_group = ixgbevf_regs[g_ind++])) 7242 count += ixgbe_regs_group_count(reg_group); 7243 7244 return count; 7245 } 7246 7247 static int 7248 ixgbe_get_regs(struct rte_eth_dev *dev, 7249 struct rte_dev_reg_info *regs) 7250 { 7251 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7252 uint32_t *data = regs->data; 7253 int g_ind = 0; 7254 int count = 0; 7255 const struct reg_info *reg_group; 7256 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7257 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7258 7259 if (data == NULL) { 7260 regs->length = ixgbe_get_reg_length(dev); 7261 regs->width = sizeof(uint32_t); 7262 return 0; 7263 } 7264 7265 /* Support only full register dump */ 7266 if ((regs->length == 0) || 7267 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) { 7268 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7269 hw->device_id; 7270 while ((reg_group = reg_set[g_ind++])) 7271 count += ixgbe_read_regs_group(dev, &data[count], 7272 reg_group); 7273 return 0; 7274 } 7275 7276 return -ENOTSUP; 7277 } 7278 7279 static int 7280 ixgbevf_get_regs(struct rte_eth_dev *dev, 7281 struct rte_dev_reg_info *regs) 7282 { 7283 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7284 uint32_t *data = regs->data; 7285 int g_ind = 0; 7286 int count = 0; 7287 const struct reg_info *reg_group; 7288 7289 if (data == NULL) { 7290 regs->length = ixgbevf_get_reg_length(dev); 7291 regs->width = sizeof(uint32_t); 7292 return 0; 7293 } 7294 7295 /* Support only full register dump */ 7296 if ((regs->length == 0) || 7297 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) { 7298 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7299 hw->device_id; 7300 while ((reg_group = ixgbevf_regs[g_ind++])) 7301 count += ixgbe_read_regs_group(dev, &data[count], 7302 reg_group); 7303 return 0; 7304 } 7305 7306 return -ENOTSUP; 7307 } 7308 7309 static int 7310 ixgbe_get_eeprom_length(struct rte_eth_dev *dev) 7311 { 7312 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7313 7314 /* Return unit is byte count */ 7315 return hw->eeprom.word_size * 2; 7316 } 7317 7318 static int 7319 ixgbe_get_eeprom(struct rte_eth_dev *dev, 7320 struct rte_dev_eeprom_info *in_eeprom) 7321 { 7322 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7323 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7324 uint16_t *data = in_eeprom->data; 7325 int first, length; 7326 7327 first = in_eeprom->offset >> 1; 7328 length = in_eeprom->length >> 1; 7329 if ((first > hw->eeprom.word_size) || 7330 ((first + length) > hw->eeprom.word_size)) 7331 return -EINVAL; 7332 7333 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7334 7335 return eeprom->ops.read_buffer(hw, first, length, data); 7336 } 7337 7338 static int 7339 ixgbe_set_eeprom(struct rte_eth_dev *dev, 7340 struct rte_dev_eeprom_info *in_eeprom) 7341 { 7342 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7343 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7344 uint16_t *data = in_eeprom->data; 7345 int first, length; 7346 7347 first = in_eeprom->offset >> 1; 7348 length = in_eeprom->length >> 1; 7349 if ((first > hw->eeprom.word_size) || 7350 ((first + length) > hw->eeprom.word_size)) 7351 return -EINVAL; 7352 7353 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7354 7355 return eeprom->ops.write_buffer(hw, first, length, data); 7356 } 7357 7358 static int 7359 ixgbe_get_module_info(struct rte_eth_dev *dev, 7360 struct rte_eth_dev_module_info *modinfo) 7361 { 7362 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7363 uint32_t status; 7364 uint8_t sff8472_rev, addr_mode; 7365 bool page_swap = false; 7366 7367 /* Check whether we support SFF-8472 or not */ 7368 status = hw->phy.ops.read_i2c_eeprom(hw, 7369 IXGBE_SFF_SFF_8472_COMP, 7370 &sff8472_rev); 7371 if (status != 0) 7372 return -EIO; 7373 7374 /* addressing mode is not supported */ 7375 status = hw->phy.ops.read_i2c_eeprom(hw, 7376 IXGBE_SFF_SFF_8472_SWAP, 7377 &addr_mode); 7378 if (status != 0) 7379 return -EIO; 7380 7381 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 7382 PMD_DRV_LOG(ERR, 7383 "Address change required to access page 0xA2, " 7384 "but not supported. Please report the module " 7385 "type to the driver maintainers."); 7386 page_swap = true; 7387 } 7388 7389 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) { 7390 /* We have a SFP, but it does not support SFF-8472 */ 7391 modinfo->type = RTE_ETH_MODULE_SFF_8079; 7392 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 7393 } else { 7394 /* We have a SFP which supports a revision of SFF-8472. */ 7395 modinfo->type = RTE_ETH_MODULE_SFF_8472; 7396 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 7397 } 7398 7399 return 0; 7400 } 7401 7402 static int 7403 ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 7404 struct rte_dev_eeprom_info *info) 7405 { 7406 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7407 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 7408 uint8_t databyte = 0xFF; 7409 uint8_t *data = info->data; 7410 uint32_t i = 0; 7411 7412 if (info->length == 0) 7413 return -EINVAL; 7414 7415 for (i = info->offset; i < info->offset + info->length; i++) { 7416 if (i < RTE_ETH_MODULE_SFF_8079_LEN) 7417 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 7418 else 7419 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 7420 7421 if (status != 0) 7422 return -EIO; 7423 7424 data[i - info->offset] = databyte; 7425 } 7426 7427 return 0; 7428 } 7429 7430 uint16_t 7431 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) { 7432 switch (mac_type) { 7433 case ixgbe_mac_X550: 7434 case ixgbe_mac_X550EM_x: 7435 case ixgbe_mac_X550EM_a: 7436 return ETH_RSS_RETA_SIZE_512; 7437 case ixgbe_mac_X550_vf: 7438 case ixgbe_mac_X550EM_x_vf: 7439 case ixgbe_mac_X550EM_a_vf: 7440 return ETH_RSS_RETA_SIZE_64; 7441 default: 7442 return ETH_RSS_RETA_SIZE_128; 7443 } 7444 } 7445 7446 uint32_t 7447 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) { 7448 switch (mac_type) { 7449 case ixgbe_mac_X550: 7450 case ixgbe_mac_X550EM_x: 7451 case ixgbe_mac_X550EM_a: 7452 if (reta_idx < ETH_RSS_RETA_SIZE_128) 7453 return IXGBE_RETA(reta_idx >> 2); 7454 else 7455 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2); 7456 case ixgbe_mac_X550_vf: 7457 case ixgbe_mac_X550EM_x_vf: 7458 case ixgbe_mac_X550EM_a_vf: 7459 return IXGBE_VFRETA(reta_idx >> 2); 7460 default: 7461 return IXGBE_RETA(reta_idx >> 2); 7462 } 7463 } 7464 7465 uint32_t 7466 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) { 7467 switch (mac_type) { 7468 case ixgbe_mac_X550_vf: 7469 case ixgbe_mac_X550EM_x_vf: 7470 case ixgbe_mac_X550EM_a_vf: 7471 return IXGBE_VFMRQC; 7472 default: 7473 return IXGBE_MRQC; 7474 } 7475 } 7476 7477 uint32_t 7478 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) { 7479 switch (mac_type) { 7480 case ixgbe_mac_X550_vf: 7481 case ixgbe_mac_X550EM_x_vf: 7482 case ixgbe_mac_X550EM_a_vf: 7483 return IXGBE_VFRSSRK(i); 7484 default: 7485 return IXGBE_RSSRK(i); 7486 } 7487 } 7488 7489 bool 7490 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) { 7491 switch (mac_type) { 7492 case ixgbe_mac_82599_vf: 7493 case ixgbe_mac_X540_vf: 7494 return 0; 7495 default: 7496 return 1; 7497 } 7498 } 7499 7500 static int 7501 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 7502 struct rte_eth_dcb_info *dcb_info) 7503 { 7504 struct ixgbe_dcb_config *dcb_config = 7505 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 7506 struct ixgbe_dcb_tc_config *tc; 7507 struct rte_eth_dcb_tc_queue_mapping *tc_queue; 7508 uint8_t nb_tcs; 7509 uint8_t i, j; 7510 7511 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG) 7512 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs; 7513 else 7514 dcb_info->nb_tcs = 1; 7515 7516 tc_queue = &dcb_info->tc_queue; 7517 nb_tcs = dcb_info->nb_tcs; 7518 7519 if (dcb_config->vt_mode) { /* vt is enabled*/ 7520 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf = 7521 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf; 7522 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7523 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i]; 7524 if (RTE_ETH_DEV_SRIOV(dev).active > 0) { 7525 for (j = 0; j < nb_tcs; j++) { 7526 tc_queue->tc_rxq[0][j].base = j; 7527 tc_queue->tc_rxq[0][j].nb_queue = 1; 7528 tc_queue->tc_txq[0][j].base = j; 7529 tc_queue->tc_txq[0][j].nb_queue = 1; 7530 } 7531 } else { 7532 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) { 7533 for (j = 0; j < nb_tcs; j++) { 7534 tc_queue->tc_rxq[i][j].base = 7535 i * nb_tcs + j; 7536 tc_queue->tc_rxq[i][j].nb_queue = 1; 7537 tc_queue->tc_txq[i][j].base = 7538 i * nb_tcs + j; 7539 tc_queue->tc_txq[i][j].nb_queue = 1; 7540 } 7541 } 7542 } 7543 } else { /* vt is disabled*/ 7544 struct rte_eth_dcb_rx_conf *rx_conf = 7545 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 7546 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7547 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i]; 7548 if (dcb_info->nb_tcs == ETH_4_TCS) { 7549 for (i = 0; i < dcb_info->nb_tcs; i++) { 7550 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32; 7551 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7552 } 7553 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7554 dcb_info->tc_queue.tc_txq[0][1].base = 64; 7555 dcb_info->tc_queue.tc_txq[0][2].base = 96; 7556 dcb_info->tc_queue.tc_txq[0][3].base = 112; 7557 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64; 7558 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7559 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7560 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7561 } else if (dcb_info->nb_tcs == ETH_8_TCS) { 7562 for (i = 0; i < dcb_info->nb_tcs; i++) { 7563 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16; 7564 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7565 } 7566 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7567 dcb_info->tc_queue.tc_txq[0][1].base = 32; 7568 dcb_info->tc_queue.tc_txq[0][2].base = 64; 7569 dcb_info->tc_queue.tc_txq[0][3].base = 80; 7570 dcb_info->tc_queue.tc_txq[0][4].base = 96; 7571 dcb_info->tc_queue.tc_txq[0][5].base = 104; 7572 dcb_info->tc_queue.tc_txq[0][6].base = 112; 7573 dcb_info->tc_queue.tc_txq[0][7].base = 120; 7574 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32; 7575 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7576 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7577 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7578 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8; 7579 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8; 7580 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8; 7581 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8; 7582 } 7583 } 7584 for (i = 0; i < dcb_info->nb_tcs; i++) { 7585 tc = &dcb_config->tc_config[i]; 7586 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent; 7587 } 7588 return 0; 7589 } 7590 7591 /* Update e-tag ether type */ 7592 static int 7593 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw, 7594 uint16_t ether_type) 7595 { 7596 uint32_t etag_etype; 7597 7598 if (hw->mac.type != ixgbe_mac_X550 && 7599 hw->mac.type != ixgbe_mac_X550EM_x && 7600 hw->mac.type != ixgbe_mac_X550EM_a) { 7601 return -ENOTSUP; 7602 } 7603 7604 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7605 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK; 7606 etag_etype |= ether_type; 7607 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7608 IXGBE_WRITE_FLUSH(hw); 7609 7610 return 0; 7611 } 7612 7613 /* Config l2 tunnel ether type */ 7614 static int 7615 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev, 7616 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7617 { 7618 int ret = 0; 7619 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7620 struct ixgbe_l2_tn_info *l2_tn_info = 7621 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7622 7623 if (l2_tunnel == NULL) 7624 return -EINVAL; 7625 7626 switch (l2_tunnel->l2_tunnel_type) { 7627 case RTE_L2_TUNNEL_TYPE_E_TAG: 7628 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type; 7629 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type); 7630 break; 7631 default: 7632 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7633 ret = -EINVAL; 7634 break; 7635 } 7636 7637 return ret; 7638 } 7639 7640 /* Enable e-tag tunnel */ 7641 static int 7642 ixgbe_e_tag_enable(struct ixgbe_hw *hw) 7643 { 7644 uint32_t etag_etype; 7645 7646 if (hw->mac.type != ixgbe_mac_X550 && 7647 hw->mac.type != ixgbe_mac_X550EM_x && 7648 hw->mac.type != ixgbe_mac_X550EM_a) { 7649 return -ENOTSUP; 7650 } 7651 7652 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7653 etag_etype |= IXGBE_ETAG_ETYPE_VALID; 7654 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7655 IXGBE_WRITE_FLUSH(hw); 7656 7657 return 0; 7658 } 7659 7660 /* Enable l2 tunnel */ 7661 static int 7662 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev, 7663 enum rte_eth_tunnel_type l2_tunnel_type) 7664 { 7665 int ret = 0; 7666 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7667 struct ixgbe_l2_tn_info *l2_tn_info = 7668 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7669 7670 switch (l2_tunnel_type) { 7671 case RTE_L2_TUNNEL_TYPE_E_TAG: 7672 l2_tn_info->e_tag_en = TRUE; 7673 ret = ixgbe_e_tag_enable(hw); 7674 break; 7675 default: 7676 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7677 ret = -EINVAL; 7678 break; 7679 } 7680 7681 return ret; 7682 } 7683 7684 /* Disable e-tag tunnel */ 7685 static int 7686 ixgbe_e_tag_disable(struct ixgbe_hw *hw) 7687 { 7688 uint32_t etag_etype; 7689 7690 if (hw->mac.type != ixgbe_mac_X550 && 7691 hw->mac.type != ixgbe_mac_X550EM_x && 7692 hw->mac.type != ixgbe_mac_X550EM_a) { 7693 return -ENOTSUP; 7694 } 7695 7696 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7697 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID; 7698 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7699 IXGBE_WRITE_FLUSH(hw); 7700 7701 return 0; 7702 } 7703 7704 /* Disable l2 tunnel */ 7705 static int 7706 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev, 7707 enum rte_eth_tunnel_type l2_tunnel_type) 7708 { 7709 int ret = 0; 7710 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7711 struct ixgbe_l2_tn_info *l2_tn_info = 7712 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7713 7714 switch (l2_tunnel_type) { 7715 case RTE_L2_TUNNEL_TYPE_E_TAG: 7716 l2_tn_info->e_tag_en = FALSE; 7717 ret = ixgbe_e_tag_disable(hw); 7718 break; 7719 default: 7720 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7721 ret = -EINVAL; 7722 break; 7723 } 7724 7725 return ret; 7726 } 7727 7728 static int 7729 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev, 7730 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7731 { 7732 int ret = 0; 7733 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7734 uint32_t i, rar_entries; 7735 uint32_t rar_low, rar_high; 7736 7737 if (hw->mac.type != ixgbe_mac_X550 && 7738 hw->mac.type != ixgbe_mac_X550EM_x && 7739 hw->mac.type != ixgbe_mac_X550EM_a) { 7740 return -ENOTSUP; 7741 } 7742 7743 rar_entries = ixgbe_get_num_rx_addrs(hw); 7744 7745 for (i = 1; i < rar_entries; i++) { 7746 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7747 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 7748 if ((rar_high & IXGBE_RAH_AV) && 7749 (rar_high & IXGBE_RAH_ADTYPE) && 7750 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) == 7751 l2_tunnel->tunnel_id)) { 7752 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 7753 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 7754 7755 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL); 7756 7757 return ret; 7758 } 7759 } 7760 7761 return ret; 7762 } 7763 7764 static int 7765 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev, 7766 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7767 { 7768 int ret = 0; 7769 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7770 uint32_t i, rar_entries; 7771 uint32_t rar_low, rar_high; 7772 7773 if (hw->mac.type != ixgbe_mac_X550 && 7774 hw->mac.type != ixgbe_mac_X550EM_x && 7775 hw->mac.type != ixgbe_mac_X550EM_a) { 7776 return -ENOTSUP; 7777 } 7778 7779 /* One entry for one tunnel. Try to remove potential existing entry. */ 7780 ixgbe_e_tag_filter_del(dev, l2_tunnel); 7781 7782 rar_entries = ixgbe_get_num_rx_addrs(hw); 7783 7784 for (i = 1; i < rar_entries; i++) { 7785 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7786 if (rar_high & IXGBE_RAH_AV) { 7787 continue; 7788 } else { 7789 ixgbe_set_vmdq(hw, i, l2_tunnel->pool); 7790 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE; 7791 rar_low = l2_tunnel->tunnel_id; 7792 7793 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low); 7794 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high); 7795 7796 return ret; 7797 } 7798 } 7799 7800 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full." 7801 " Please remove a rule before adding a new one."); 7802 return -EINVAL; 7803 } 7804 7805 static inline struct ixgbe_l2_tn_filter * 7806 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info, 7807 struct ixgbe_l2_tn_key *key) 7808 { 7809 int ret; 7810 7811 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key); 7812 if (ret < 0) 7813 return NULL; 7814 7815 return l2_tn_info->hash_map[ret]; 7816 } 7817 7818 static inline int 7819 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7820 struct ixgbe_l2_tn_filter *l2_tn_filter) 7821 { 7822 int ret; 7823 7824 ret = rte_hash_add_key(l2_tn_info->hash_handle, 7825 &l2_tn_filter->key); 7826 7827 if (ret < 0) { 7828 PMD_DRV_LOG(ERR, 7829 "Failed to insert L2 tunnel filter" 7830 " to hash table %d!", 7831 ret); 7832 return ret; 7833 } 7834 7835 l2_tn_info->hash_map[ret] = l2_tn_filter; 7836 7837 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 7838 7839 return 0; 7840 } 7841 7842 static inline int 7843 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7844 struct ixgbe_l2_tn_key *key) 7845 { 7846 int ret; 7847 struct ixgbe_l2_tn_filter *l2_tn_filter; 7848 7849 ret = rte_hash_del_key(l2_tn_info->hash_handle, key); 7850 7851 if (ret < 0) { 7852 PMD_DRV_LOG(ERR, 7853 "No such L2 tunnel filter to delete %d!", 7854 ret); 7855 return ret; 7856 } 7857 7858 l2_tn_filter = l2_tn_info->hash_map[ret]; 7859 l2_tn_info->hash_map[ret] = NULL; 7860 7861 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 7862 rte_free(l2_tn_filter); 7863 7864 return 0; 7865 } 7866 7867 /* Add l2 tunnel filter */ 7868 int 7869 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 7870 struct rte_eth_l2_tunnel_conf *l2_tunnel, 7871 bool restore) 7872 { 7873 int ret; 7874 struct ixgbe_l2_tn_info *l2_tn_info = 7875 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7876 struct ixgbe_l2_tn_key key; 7877 struct ixgbe_l2_tn_filter *node; 7878 7879 if (!restore) { 7880 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 7881 key.tn_id = l2_tunnel->tunnel_id; 7882 7883 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key); 7884 7885 if (node) { 7886 PMD_DRV_LOG(ERR, 7887 "The L2 tunnel filter already exists!"); 7888 return -EINVAL; 7889 } 7890 7891 node = rte_zmalloc("ixgbe_l2_tn", 7892 sizeof(struct ixgbe_l2_tn_filter), 7893 0); 7894 if (!node) 7895 return -ENOMEM; 7896 7897 rte_memcpy(&node->key, 7898 &key, 7899 sizeof(struct ixgbe_l2_tn_key)); 7900 node->pool = l2_tunnel->pool; 7901 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node); 7902 if (ret < 0) { 7903 rte_free(node); 7904 return ret; 7905 } 7906 } 7907 7908 switch (l2_tunnel->l2_tunnel_type) { 7909 case RTE_L2_TUNNEL_TYPE_E_TAG: 7910 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel); 7911 break; 7912 default: 7913 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7914 ret = -EINVAL; 7915 break; 7916 } 7917 7918 if ((!restore) && (ret < 0)) 7919 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 7920 7921 return ret; 7922 } 7923 7924 /* Delete l2 tunnel filter */ 7925 int 7926 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 7927 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7928 { 7929 int ret; 7930 struct ixgbe_l2_tn_info *l2_tn_info = 7931 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7932 struct ixgbe_l2_tn_key key; 7933 7934 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 7935 key.tn_id = l2_tunnel->tunnel_id; 7936 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 7937 if (ret < 0) 7938 return ret; 7939 7940 switch (l2_tunnel->l2_tunnel_type) { 7941 case RTE_L2_TUNNEL_TYPE_E_TAG: 7942 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel); 7943 break; 7944 default: 7945 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7946 ret = -EINVAL; 7947 break; 7948 } 7949 7950 return ret; 7951 } 7952 7953 /** 7954 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter. 7955 * @dev: pointer to rte_eth_dev structure 7956 * @filter_op:operation will be taken. 7957 * @arg: a pointer to specific structure corresponding to the filter_op 7958 */ 7959 static int 7960 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev, 7961 enum rte_filter_op filter_op, 7962 void *arg) 7963 { 7964 int ret; 7965 7966 if (filter_op == RTE_ETH_FILTER_NOP) 7967 return 0; 7968 7969 if (arg == NULL) { 7970 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 7971 filter_op); 7972 return -EINVAL; 7973 } 7974 7975 switch (filter_op) { 7976 case RTE_ETH_FILTER_ADD: 7977 ret = ixgbe_dev_l2_tunnel_filter_add 7978 (dev, 7979 (struct rte_eth_l2_tunnel_conf *)arg, 7980 FALSE); 7981 break; 7982 case RTE_ETH_FILTER_DELETE: 7983 ret = ixgbe_dev_l2_tunnel_filter_del 7984 (dev, 7985 (struct rte_eth_l2_tunnel_conf *)arg); 7986 break; 7987 default: 7988 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 7989 ret = -EINVAL; 7990 break; 7991 } 7992 return ret; 7993 } 7994 7995 static int 7996 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en) 7997 { 7998 int ret = 0; 7999 uint32_t ctrl; 8000 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8001 8002 if (hw->mac.type != ixgbe_mac_X550 && 8003 hw->mac.type != ixgbe_mac_X550EM_x && 8004 hw->mac.type != ixgbe_mac_X550EM_a) { 8005 return -ENOTSUP; 8006 } 8007 8008 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 8009 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 8010 if (en) 8011 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG; 8012 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 8013 8014 return ret; 8015 } 8016 8017 /* Enable l2 tunnel forwarding */ 8018 static int 8019 ixgbe_dev_l2_tunnel_forwarding_enable 8020 (struct rte_eth_dev *dev, 8021 enum rte_eth_tunnel_type l2_tunnel_type) 8022 { 8023 struct ixgbe_l2_tn_info *l2_tn_info = 8024 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8025 int ret = 0; 8026 8027 switch (l2_tunnel_type) { 8028 case RTE_L2_TUNNEL_TYPE_E_TAG: 8029 l2_tn_info->e_tag_fwd_en = TRUE; 8030 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1); 8031 break; 8032 default: 8033 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8034 ret = -EINVAL; 8035 break; 8036 } 8037 8038 return ret; 8039 } 8040 8041 /* Disable l2 tunnel forwarding */ 8042 static int 8043 ixgbe_dev_l2_tunnel_forwarding_disable 8044 (struct rte_eth_dev *dev, 8045 enum rte_eth_tunnel_type l2_tunnel_type) 8046 { 8047 struct ixgbe_l2_tn_info *l2_tn_info = 8048 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8049 int ret = 0; 8050 8051 switch (l2_tunnel_type) { 8052 case RTE_L2_TUNNEL_TYPE_E_TAG: 8053 l2_tn_info->e_tag_fwd_en = FALSE; 8054 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0); 8055 break; 8056 default: 8057 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8058 ret = -EINVAL; 8059 break; 8060 } 8061 8062 return ret; 8063 } 8064 8065 static int 8066 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev, 8067 struct rte_eth_l2_tunnel_conf *l2_tunnel, 8068 bool en) 8069 { 8070 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 8071 int ret = 0; 8072 uint32_t vmtir, vmvir; 8073 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8074 8075 if (l2_tunnel->vf_id >= pci_dev->max_vfs) { 8076 PMD_DRV_LOG(ERR, 8077 "VF id %u should be less than %u", 8078 l2_tunnel->vf_id, 8079 pci_dev->max_vfs); 8080 return -EINVAL; 8081 } 8082 8083 if (hw->mac.type != ixgbe_mac_X550 && 8084 hw->mac.type != ixgbe_mac_X550EM_x && 8085 hw->mac.type != ixgbe_mac_X550EM_a) { 8086 return -ENOTSUP; 8087 } 8088 8089 if (en) 8090 vmtir = l2_tunnel->tunnel_id; 8091 else 8092 vmtir = 0; 8093 8094 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir); 8095 8096 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id)); 8097 vmvir &= ~IXGBE_VMVIR_TAGA_MASK; 8098 if (en) 8099 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT; 8100 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir); 8101 8102 return ret; 8103 } 8104 8105 /* Enable l2 tunnel tag insertion */ 8106 static int 8107 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev, 8108 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8109 { 8110 int ret = 0; 8111 8112 switch (l2_tunnel->l2_tunnel_type) { 8113 case RTE_L2_TUNNEL_TYPE_E_TAG: 8114 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1); 8115 break; 8116 default: 8117 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8118 ret = -EINVAL; 8119 break; 8120 } 8121 8122 return ret; 8123 } 8124 8125 /* Disable l2 tunnel tag insertion */ 8126 static int 8127 ixgbe_dev_l2_tunnel_insertion_disable 8128 (struct rte_eth_dev *dev, 8129 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8130 { 8131 int ret = 0; 8132 8133 switch (l2_tunnel->l2_tunnel_type) { 8134 case RTE_L2_TUNNEL_TYPE_E_TAG: 8135 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0); 8136 break; 8137 default: 8138 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8139 ret = -EINVAL; 8140 break; 8141 } 8142 8143 return ret; 8144 } 8145 8146 static int 8147 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev, 8148 bool en) 8149 { 8150 int ret = 0; 8151 uint32_t qde; 8152 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8153 8154 if (hw->mac.type != ixgbe_mac_X550 && 8155 hw->mac.type != ixgbe_mac_X550EM_x && 8156 hw->mac.type != ixgbe_mac_X550EM_a) { 8157 return -ENOTSUP; 8158 } 8159 8160 qde = IXGBE_READ_REG(hw, IXGBE_QDE); 8161 if (en) 8162 qde |= IXGBE_QDE_STRIP_TAG; 8163 else 8164 qde &= ~IXGBE_QDE_STRIP_TAG; 8165 qde &= ~IXGBE_QDE_READ; 8166 qde |= IXGBE_QDE_WRITE; 8167 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde); 8168 8169 return ret; 8170 } 8171 8172 /* Enable l2 tunnel tag stripping */ 8173 static int 8174 ixgbe_dev_l2_tunnel_stripping_enable 8175 (struct rte_eth_dev *dev, 8176 enum rte_eth_tunnel_type l2_tunnel_type) 8177 { 8178 int ret = 0; 8179 8180 switch (l2_tunnel_type) { 8181 case RTE_L2_TUNNEL_TYPE_E_TAG: 8182 ret = ixgbe_e_tag_stripping_en_dis(dev, 1); 8183 break; 8184 default: 8185 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8186 ret = -EINVAL; 8187 break; 8188 } 8189 8190 return ret; 8191 } 8192 8193 /* Disable l2 tunnel tag stripping */ 8194 static int 8195 ixgbe_dev_l2_tunnel_stripping_disable 8196 (struct rte_eth_dev *dev, 8197 enum rte_eth_tunnel_type l2_tunnel_type) 8198 { 8199 int ret = 0; 8200 8201 switch (l2_tunnel_type) { 8202 case RTE_L2_TUNNEL_TYPE_E_TAG: 8203 ret = ixgbe_e_tag_stripping_en_dis(dev, 0); 8204 break; 8205 default: 8206 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8207 ret = -EINVAL; 8208 break; 8209 } 8210 8211 return ret; 8212 } 8213 8214 /* Enable/disable l2 tunnel offload functions */ 8215 static int 8216 ixgbe_dev_l2_tunnel_offload_set 8217 (struct rte_eth_dev *dev, 8218 struct rte_eth_l2_tunnel_conf *l2_tunnel, 8219 uint32_t mask, 8220 uint8_t en) 8221 { 8222 int ret = 0; 8223 8224 if (l2_tunnel == NULL) 8225 return -EINVAL; 8226 8227 ret = -EINVAL; 8228 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) { 8229 if (en) 8230 ret = ixgbe_dev_l2_tunnel_enable( 8231 dev, 8232 l2_tunnel->l2_tunnel_type); 8233 else 8234 ret = ixgbe_dev_l2_tunnel_disable( 8235 dev, 8236 l2_tunnel->l2_tunnel_type); 8237 } 8238 8239 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) { 8240 if (en) 8241 ret = ixgbe_dev_l2_tunnel_insertion_enable( 8242 dev, 8243 l2_tunnel); 8244 else 8245 ret = ixgbe_dev_l2_tunnel_insertion_disable( 8246 dev, 8247 l2_tunnel); 8248 } 8249 8250 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) { 8251 if (en) 8252 ret = ixgbe_dev_l2_tunnel_stripping_enable( 8253 dev, 8254 l2_tunnel->l2_tunnel_type); 8255 else 8256 ret = ixgbe_dev_l2_tunnel_stripping_disable( 8257 dev, 8258 l2_tunnel->l2_tunnel_type); 8259 } 8260 8261 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) { 8262 if (en) 8263 ret = ixgbe_dev_l2_tunnel_forwarding_enable( 8264 dev, 8265 l2_tunnel->l2_tunnel_type); 8266 else 8267 ret = ixgbe_dev_l2_tunnel_forwarding_disable( 8268 dev, 8269 l2_tunnel->l2_tunnel_type); 8270 } 8271 8272 return ret; 8273 } 8274 8275 static int 8276 ixgbe_update_vxlan_port(struct ixgbe_hw *hw, 8277 uint16_t port) 8278 { 8279 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port); 8280 IXGBE_WRITE_FLUSH(hw); 8281 8282 return 0; 8283 } 8284 8285 /* There's only one register for VxLAN UDP port. 8286 * So, we cannot add several ports. Will update it. 8287 */ 8288 static int 8289 ixgbe_add_vxlan_port(struct ixgbe_hw *hw, 8290 uint16_t port) 8291 { 8292 if (port == 0) { 8293 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 8294 return -EINVAL; 8295 } 8296 8297 return ixgbe_update_vxlan_port(hw, port); 8298 } 8299 8300 /* We cannot delete the VxLAN port. For there's a register for VxLAN 8301 * UDP port, it must have a value. 8302 * So, will reset it to the original value 0. 8303 */ 8304 static int 8305 ixgbe_del_vxlan_port(struct ixgbe_hw *hw, 8306 uint16_t port) 8307 { 8308 uint16_t cur_port; 8309 8310 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL); 8311 8312 if (cur_port != port) { 8313 PMD_DRV_LOG(ERR, "Port %u does not exist.", port); 8314 return -EINVAL; 8315 } 8316 8317 return ixgbe_update_vxlan_port(hw, 0); 8318 } 8319 8320 /* Add UDP tunneling port */ 8321 static int 8322 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 8323 struct rte_eth_udp_tunnel *udp_tunnel) 8324 { 8325 int ret = 0; 8326 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8327 8328 if (hw->mac.type != ixgbe_mac_X550 && 8329 hw->mac.type != ixgbe_mac_X550EM_x && 8330 hw->mac.type != ixgbe_mac_X550EM_a) { 8331 return -ENOTSUP; 8332 } 8333 8334 if (udp_tunnel == NULL) 8335 return -EINVAL; 8336 8337 switch (udp_tunnel->prot_type) { 8338 case RTE_TUNNEL_TYPE_VXLAN: 8339 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port); 8340 break; 8341 8342 case RTE_TUNNEL_TYPE_GENEVE: 8343 case RTE_TUNNEL_TYPE_TEREDO: 8344 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8345 ret = -EINVAL; 8346 break; 8347 8348 default: 8349 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8350 ret = -EINVAL; 8351 break; 8352 } 8353 8354 return ret; 8355 } 8356 8357 /* Remove UDP tunneling port */ 8358 static int 8359 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 8360 struct rte_eth_udp_tunnel *udp_tunnel) 8361 { 8362 int ret = 0; 8363 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8364 8365 if (hw->mac.type != ixgbe_mac_X550 && 8366 hw->mac.type != ixgbe_mac_X550EM_x && 8367 hw->mac.type != ixgbe_mac_X550EM_a) { 8368 return -ENOTSUP; 8369 } 8370 8371 if (udp_tunnel == NULL) 8372 return -EINVAL; 8373 8374 switch (udp_tunnel->prot_type) { 8375 case RTE_TUNNEL_TYPE_VXLAN: 8376 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port); 8377 break; 8378 case RTE_TUNNEL_TYPE_GENEVE: 8379 case RTE_TUNNEL_TYPE_TEREDO: 8380 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8381 ret = -EINVAL; 8382 break; 8383 default: 8384 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8385 ret = -EINVAL; 8386 break; 8387 } 8388 8389 return ret; 8390 } 8391 8392 static void 8393 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev) 8394 { 8395 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8396 8397 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC); 8398 } 8399 8400 static void 8401 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev) 8402 { 8403 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8404 8405 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE); 8406 } 8407 8408 static void 8409 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev) 8410 { 8411 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8412 8413 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI); 8414 } 8415 8416 static void 8417 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev) 8418 { 8419 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8420 8421 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI); 8422 } 8423 8424 static void ixgbevf_mbx_process(struct rte_eth_dev *dev) 8425 { 8426 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8427 u32 in_msg = 0; 8428 8429 /* peek the message first */ 8430 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM); 8431 8432 /* PF reset VF event */ 8433 if (in_msg == IXGBE_PF_CONTROL_MSG) { 8434 /* dummy mbx read to ack pf */ 8435 if (ixgbe_read_mbx(hw, &in_msg, 1, 0)) 8436 return; 8437 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 8438 NULL); 8439 } 8440 } 8441 8442 static int 8443 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev) 8444 { 8445 uint32_t eicr; 8446 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8447 struct ixgbe_interrupt *intr = 8448 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8449 ixgbevf_intr_disable(dev); 8450 8451 /* read-on-clear nic registers here */ 8452 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR); 8453 intr->flags = 0; 8454 8455 /* only one misc vector supported - mailbox */ 8456 eicr &= IXGBE_VTEICR_MASK; 8457 if (eicr == IXGBE_MISC_VEC_ID) 8458 intr->flags |= IXGBE_FLAG_MAILBOX; 8459 8460 return 0; 8461 } 8462 8463 static int 8464 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev) 8465 { 8466 struct ixgbe_interrupt *intr = 8467 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8468 8469 if (intr->flags & IXGBE_FLAG_MAILBOX) { 8470 ixgbevf_mbx_process(dev); 8471 intr->flags &= ~IXGBE_FLAG_MAILBOX; 8472 } 8473 8474 ixgbevf_intr_enable(dev); 8475 8476 return 0; 8477 } 8478 8479 static void 8480 ixgbevf_dev_interrupt_handler(void *param) 8481 { 8482 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 8483 8484 ixgbevf_dev_interrupt_get_status(dev); 8485 ixgbevf_dev_interrupt_action(dev); 8486 } 8487 8488 /** 8489 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path 8490 * @hw: pointer to hardware structure 8491 * 8492 * Stops the transmit data path and waits for the HW to internally empty 8493 * the Tx security block 8494 **/ 8495 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw) 8496 { 8497 #define IXGBE_MAX_SECTX_POLL 40 8498 8499 int i; 8500 int sectxreg; 8501 8502 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8503 sectxreg |= IXGBE_SECTXCTRL_TX_DIS; 8504 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8505 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) { 8506 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT); 8507 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY) 8508 break; 8509 /* Use interrupt-safe sleep just in case */ 8510 usec_delay(1000); 8511 } 8512 8513 /* For informational purposes only */ 8514 if (i >= IXGBE_MAX_SECTX_POLL) 8515 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security " 8516 "path fully disabled. Continuing with init."); 8517 8518 return IXGBE_SUCCESS; 8519 } 8520 8521 /** 8522 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path 8523 * @hw: pointer to hardware structure 8524 * 8525 * Enables the transmit data path. 8526 **/ 8527 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw) 8528 { 8529 uint32_t sectxreg; 8530 8531 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8532 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS; 8533 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8534 IXGBE_WRITE_FLUSH(hw); 8535 8536 return IXGBE_SUCCESS; 8537 } 8538 8539 /* restore n-tuple filter */ 8540 static inline void 8541 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev) 8542 { 8543 struct ixgbe_filter_info *filter_info = 8544 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8545 struct ixgbe_5tuple_filter *node; 8546 8547 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) { 8548 ixgbe_inject_5tuple_filter(dev, node); 8549 } 8550 } 8551 8552 /* restore ethernet type filter */ 8553 static inline void 8554 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev) 8555 { 8556 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8557 struct ixgbe_filter_info *filter_info = 8558 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8559 int i; 8560 8561 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8562 if (filter_info->ethertype_mask & (1 << i)) { 8563 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 8564 filter_info->ethertype_filters[i].etqf); 8565 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 8566 filter_info->ethertype_filters[i].etqs); 8567 IXGBE_WRITE_FLUSH(hw); 8568 } 8569 } 8570 } 8571 8572 /* restore SYN filter */ 8573 static inline void 8574 ixgbe_syn_filter_restore(struct rte_eth_dev *dev) 8575 { 8576 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8577 struct ixgbe_filter_info *filter_info = 8578 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8579 uint32_t synqf; 8580 8581 synqf = filter_info->syn_info; 8582 8583 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 8584 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 8585 IXGBE_WRITE_FLUSH(hw); 8586 } 8587 } 8588 8589 /* restore L2 tunnel filter */ 8590 static inline void 8591 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev) 8592 { 8593 struct ixgbe_l2_tn_info *l2_tn_info = 8594 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8595 struct ixgbe_l2_tn_filter *node; 8596 struct rte_eth_l2_tunnel_conf l2_tn_conf; 8597 8598 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) { 8599 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type; 8600 l2_tn_conf.tunnel_id = node->key.tn_id; 8601 l2_tn_conf.pool = node->pool; 8602 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE); 8603 } 8604 } 8605 8606 /* restore rss filter */ 8607 static inline void 8608 ixgbe_rss_filter_restore(struct rte_eth_dev *dev) 8609 { 8610 struct ixgbe_filter_info *filter_info = 8611 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8612 8613 if (filter_info->rss_info.conf.queue_num) 8614 ixgbe_config_rss_filter(dev, 8615 &filter_info->rss_info, TRUE); 8616 } 8617 8618 static int 8619 ixgbe_filter_restore(struct rte_eth_dev *dev) 8620 { 8621 ixgbe_ntuple_filter_restore(dev); 8622 ixgbe_ethertype_filter_restore(dev); 8623 ixgbe_syn_filter_restore(dev); 8624 ixgbe_fdir_filter_restore(dev); 8625 ixgbe_l2_tn_filter_restore(dev); 8626 ixgbe_rss_filter_restore(dev); 8627 8628 return 0; 8629 } 8630 8631 static void 8632 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev) 8633 { 8634 struct ixgbe_l2_tn_info *l2_tn_info = 8635 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8636 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8637 8638 if (l2_tn_info->e_tag_en) 8639 (void)ixgbe_e_tag_enable(hw); 8640 8641 if (l2_tn_info->e_tag_fwd_en) 8642 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1); 8643 8644 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type); 8645 } 8646 8647 /* remove all the n-tuple filters */ 8648 void 8649 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev) 8650 { 8651 struct ixgbe_filter_info *filter_info = 8652 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8653 struct ixgbe_5tuple_filter *p_5tuple; 8654 8655 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) 8656 ixgbe_remove_5tuple_filter(dev, p_5tuple); 8657 } 8658 8659 /* remove all the ether type filters */ 8660 void 8661 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev) 8662 { 8663 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8664 struct ixgbe_filter_info *filter_info = 8665 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8666 int i; 8667 8668 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8669 if (filter_info->ethertype_mask & (1 << i) && 8670 !filter_info->ethertype_filters[i].conf) { 8671 (void)ixgbe_ethertype_filter_remove(filter_info, 8672 (uint8_t)i); 8673 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0); 8674 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0); 8675 IXGBE_WRITE_FLUSH(hw); 8676 } 8677 } 8678 } 8679 8680 /* remove the SYN filter */ 8681 void 8682 ixgbe_clear_syn_filter(struct rte_eth_dev *dev) 8683 { 8684 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8685 struct ixgbe_filter_info *filter_info = 8686 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8687 8688 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) { 8689 filter_info->syn_info = 0; 8690 8691 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0); 8692 IXGBE_WRITE_FLUSH(hw); 8693 } 8694 } 8695 8696 /* remove all the L2 tunnel filters */ 8697 int 8698 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev) 8699 { 8700 struct ixgbe_l2_tn_info *l2_tn_info = 8701 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8702 struct ixgbe_l2_tn_filter *l2_tn_filter; 8703 struct rte_eth_l2_tunnel_conf l2_tn_conf; 8704 int ret = 0; 8705 8706 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 8707 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type; 8708 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id; 8709 l2_tn_conf.pool = l2_tn_filter->pool; 8710 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf); 8711 if (ret < 0) 8712 return ret; 8713 } 8714 8715 return 0; 8716 } 8717 8718 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd); 8719 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map); 8720 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 8721 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd); 8722 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map); 8723 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci"); 8724 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf, 8725 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>"); 8726 8727 RTE_INIT(ixgbe_init_log) 8728 { 8729 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init"); 8730 if (ixgbe_logtype_init >= 0) 8731 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE); 8732 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver"); 8733 if (ixgbe_logtype_driver >= 0) 8734 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE); 8735 } 8736