1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <inttypes.h> 13 #include <netinet/in.h> 14 #include <rte_string_fns.h> 15 #include <rte_byteorder.h> 16 #include <rte_common.h> 17 #include <rte_cycles.h> 18 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_bus_pci.h> 24 #include <rte_branch_prediction.h> 25 #include <rte_memory.h> 26 #include <rte_kvargs.h> 27 #include <rte_eal.h> 28 #include <rte_alarm.h> 29 #include <rte_ether.h> 30 #include <rte_ethdev_driver.h> 31 #include <rte_ethdev_pci.h> 32 #include <rte_malloc.h> 33 #include <rte_random.h> 34 #include <rte_dev.h> 35 #include <rte_hash_crc.h> 36 #ifdef RTE_LIBRTE_SECURITY 37 #include <rte_security_driver.h> 38 #endif 39 40 #include "ixgbe_logs.h" 41 #include "base/ixgbe_api.h" 42 #include "base/ixgbe_vf.h" 43 #include "base/ixgbe_common.h" 44 #include "ixgbe_ethdev.h" 45 #include "ixgbe_bypass.h" 46 #include "ixgbe_rxtx.h" 47 #include "base/ixgbe_type.h" 48 #include "base/ixgbe_phy.h" 49 #include "ixgbe_regs.h" 50 51 /* 52 * High threshold controlling when to start sending XOFF frames. Must be at 53 * least 8 bytes less than receive packet buffer size. This value is in units 54 * of 1024 bytes. 55 */ 56 #define IXGBE_FC_HI 0x80 57 58 /* 59 * Low threshold controlling when to start sending XON frames. This value is 60 * in units of 1024 bytes. 61 */ 62 #define IXGBE_FC_LO 0x40 63 64 /* Timer value included in XOFF frames. */ 65 #define IXGBE_FC_PAUSE 0x680 66 67 /*Default value of Max Rx Queue*/ 68 #define IXGBE_MAX_RX_QUEUE_NUM 128 69 70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */ 71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */ 72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */ 73 74 #define IXGBE_MMW_SIZE_DEFAULT 0x4 75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14 76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */ 77 78 /* 79 * Default values for RX/TX configuration 80 */ 81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32 82 #define IXGBE_DEFAULT_RX_PTHRESH 8 83 #define IXGBE_DEFAULT_RX_HTHRESH 8 84 #define IXGBE_DEFAULT_RX_WTHRESH 0 85 86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32 87 #define IXGBE_DEFAULT_TX_PTHRESH 32 88 #define IXGBE_DEFAULT_TX_HTHRESH 0 89 #define IXGBE_DEFAULT_TX_WTHRESH 0 90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32 91 92 /* Bit shift and mask */ 93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2) 94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t) 95 #define IXGBE_8_BIT_WIDTH CHAR_BIT 96 #define IXGBE_8_BIT_MASK UINT8_MAX 97 98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */ 99 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0])) 101 102 /* Additional timesync values. */ 103 #define NSEC_PER_SEC 1000000000L 104 #define IXGBE_INCVAL_10GB 0x66666666 105 #define IXGBE_INCVAL_1GB 0x40000000 106 #define IXGBE_INCVAL_100 0x50000000 107 #define IXGBE_INCVAL_SHIFT_10GB 28 108 #define IXGBE_INCVAL_SHIFT_1GB 24 109 #define IXGBE_INCVAL_SHIFT_100 21 110 #define IXGBE_INCVAL_SHIFT_82599 7 111 #define IXGBE_INCPER_SHIFT_82599 24 112 113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL 114 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000 117 #define IXGBE_ETAG_ETYPE 0x00005084 118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff 119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000 120 #define IXGBE_RAH_ADTYPE 0x40000000 121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff 122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */ 125 #define IXGBE_QDE_STRIP_TAG 0x00000004 126 #define IXGBE_VTEICR_MASK 0x07 127 128 #define IXGBE_EXVET_VET_EXT_SHIFT 16 129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000 130 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk" 132 133 static const char * const ixgbevf_valid_arguments[] = { 134 IXGBEVF_DEVARG_PFLINK_FULLCHK, 135 NULL 136 }; 137 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev); 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev); 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev); 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev); 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev); 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev); 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev); 146 static int ixgbe_dev_start(struct rte_eth_dev *dev); 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev); 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev); 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev); 150 static void ixgbe_dev_close(struct rte_eth_dev *dev); 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev); 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev, 157 int wait_to_complete); 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev, 159 struct rte_eth_stats *stats); 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev, 161 struct rte_eth_xstat *xstats, unsigned n); 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, 163 struct rte_eth_xstat *xstats, unsigned n); 164 static int 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 166 uint64_t *values, unsigned int n); 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev); 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev); 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 170 struct rte_eth_xstat_name *xstats_names, 171 unsigned int size); 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev, 173 struct rte_eth_xstat_name *xstats_names, unsigned limit); 174 static int ixgbe_dev_xstats_get_names_by_id( 175 struct rte_eth_dev *dev, 176 struct rte_eth_xstat_name *xstats_names, 177 const uint64_t *ids, 178 unsigned int limit); 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 180 uint16_t queue_id, 181 uint8_t stat_idx, 182 uint8_t is_rx); 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 184 size_t fw_size); 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev, 186 struct rte_eth_dev_info *dev_info); 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev, 189 struct rte_eth_dev_info *dev_info); 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 191 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev, 193 uint16_t vlan_id, int on); 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 195 enum rte_vlan_type vlan_type, 196 uint16_t tpid_id); 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, 198 uint16_t queue, bool on); 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, 200 int on); 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, 202 int mask); 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask); 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask); 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue); 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue); 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev); 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev); 209 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev); 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev); 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, 213 struct rte_eth_fc_conf *fc_conf); 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, 215 struct rte_eth_fc_conf *fc_conf); 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 217 struct rte_eth_pfc_conf *pfc_conf); 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 219 struct rte_eth_rss_reta_entry64 *reta_conf, 220 uint16_t reta_size); 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 222 struct rte_eth_rss_reta_entry64 *reta_conf, 223 uint16_t reta_size); 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev); 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev); 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev); 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev); 230 static void ixgbe_dev_interrupt_handler(void *param); 231 static void ixgbe_dev_interrupt_delayed_handler(void *param); 232 static void *ixgbe_dev_setup_link_thread_handler(void *param); 233 static void ixgbe_dev_cancel_link_thread(struct rte_eth_dev *dev); 234 235 static int ixgbe_add_rar(struct rte_eth_dev *dev, 236 struct rte_ether_addr *mac_addr, 237 uint32_t index, uint32_t pool); 238 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index); 239 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, 240 struct rte_ether_addr *mac_addr); 241 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config); 242 static bool is_device_supported(struct rte_eth_dev *dev, 243 struct rte_pci_driver *drv); 244 245 /* For Virtual Function support */ 246 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev); 247 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev); 248 static int ixgbevf_dev_configure(struct rte_eth_dev *dev); 249 static int ixgbevf_dev_start(struct rte_eth_dev *dev); 250 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev, 251 int wait_to_complete); 252 static void ixgbevf_dev_stop(struct rte_eth_dev *dev); 253 static void ixgbevf_dev_close(struct rte_eth_dev *dev); 254 static int ixgbevf_dev_reset(struct rte_eth_dev *dev); 255 static void ixgbevf_intr_disable(struct rte_eth_dev *dev); 256 static void ixgbevf_intr_enable(struct rte_eth_dev *dev); 257 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev, 258 struct rte_eth_stats *stats); 259 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev); 260 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, 261 uint16_t vlan_id, int on); 262 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, 263 uint16_t queue, int on); 264 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask); 265 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask); 266 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on); 267 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 268 uint16_t queue_id); 269 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 270 uint16_t queue_id); 271 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 272 uint8_t queue, uint8_t msix_vector); 273 static void ixgbevf_configure_msix(struct rte_eth_dev *dev); 274 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev); 275 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev); 276 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev); 277 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev); 278 279 /* For Eth VMDQ APIs support */ 280 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct 281 rte_ether_addr * mac_addr, uint8_t on); 282 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on); 283 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 284 struct rte_eth_mirror_conf *mirror_conf, 285 uint8_t rule_id, uint8_t on); 286 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, 287 uint8_t rule_id); 288 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 289 uint16_t queue_id); 290 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 291 uint16_t queue_id); 292 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 293 uint8_t queue, uint8_t msix_vector); 294 static void ixgbe_configure_msix(struct rte_eth_dev *dev); 295 296 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev, 297 struct rte_ether_addr *mac_addr, 298 uint32_t index, uint32_t pool); 299 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index); 300 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 301 struct rte_ether_addr *mac_addr); 302 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev, 303 struct rte_eth_syn_filter *filter); 304 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev, 305 enum rte_filter_op filter_op, 306 void *arg); 307 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 308 struct ixgbe_5tuple_filter *filter); 309 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 310 struct ixgbe_5tuple_filter *filter); 311 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev, 312 enum rte_filter_op filter_op, 313 void *arg); 314 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev, 315 struct rte_eth_ntuple_filter *filter); 316 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev, 317 enum rte_filter_op filter_op, 318 void *arg); 319 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, 320 struct rte_eth_ethertype_filter *filter); 321 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 322 enum rte_filter_type filter_type, 323 enum rte_filter_op filter_op, 324 void *arg); 325 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 326 327 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 328 struct rte_ether_addr *mc_addr_set, 329 uint32_t nb_mc_addr); 330 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 331 struct rte_eth_dcb_info *dcb_info); 332 333 static int ixgbe_get_reg_length(struct rte_eth_dev *dev); 334 static int ixgbe_get_regs(struct rte_eth_dev *dev, 335 struct rte_dev_reg_info *regs); 336 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev); 337 static int ixgbe_get_eeprom(struct rte_eth_dev *dev, 338 struct rte_dev_eeprom_info *eeprom); 339 static int ixgbe_set_eeprom(struct rte_eth_dev *dev, 340 struct rte_dev_eeprom_info *eeprom); 341 342 static int ixgbe_get_module_info(struct rte_eth_dev *dev, 343 struct rte_eth_dev_module_info *modinfo); 344 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 345 struct rte_dev_eeprom_info *info); 346 347 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev); 348 static int ixgbevf_get_regs(struct rte_eth_dev *dev, 349 struct rte_dev_reg_info *regs); 350 351 static int ixgbe_timesync_enable(struct rte_eth_dev *dev); 352 static int ixgbe_timesync_disable(struct rte_eth_dev *dev); 353 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 354 struct timespec *timestamp, 355 uint32_t flags); 356 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 357 struct timespec *timestamp); 358 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 359 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev, 360 struct timespec *timestamp); 361 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev, 362 const struct timespec *timestamp); 363 static void ixgbevf_dev_interrupt_handler(void *param); 364 365 static int ixgbe_dev_l2_tunnel_eth_type_conf 366 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel); 367 static int ixgbe_dev_l2_tunnel_offload_set 368 (struct rte_eth_dev *dev, 369 struct rte_eth_l2_tunnel_conf *l2_tunnel, 370 uint32_t mask, 371 uint8_t en); 372 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev, 373 enum rte_filter_op filter_op, 374 void *arg); 375 376 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 377 struct rte_eth_udp_tunnel *udp_tunnel); 378 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 379 struct rte_eth_udp_tunnel *udp_tunnel); 380 static int ixgbe_filter_restore(struct rte_eth_dev *dev); 381 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev); 382 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw); 383 384 /* 385 * Define VF Stats MACRO for Non "cleared on read" register 386 */ 387 #define UPDATE_VF_STAT(reg, last, cur) \ 388 { \ 389 uint32_t latest = IXGBE_READ_REG(hw, reg); \ 390 cur += (latest - last) & UINT_MAX; \ 391 last = latest; \ 392 } 393 394 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \ 395 { \ 396 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \ 397 u64 new_msb = IXGBE_READ_REG(hw, msb); \ 398 u64 latest = ((new_msb << 32) | new_lsb); \ 399 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \ 400 last = latest; \ 401 } 402 403 #define IXGBE_SET_HWSTRIP(h, q) do {\ 404 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 405 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 406 (h)->bitmap[idx] |= 1 << bit;\ 407 } while (0) 408 409 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\ 410 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 411 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 412 (h)->bitmap[idx] &= ~(1 << bit);\ 413 } while (0) 414 415 #define IXGBE_GET_HWSTRIP(h, q, r) do {\ 416 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 417 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 418 (r) = (h)->bitmap[idx] >> bit & 1;\ 419 } while (0) 420 421 int ixgbe_logtype_init; 422 int ixgbe_logtype_driver; 423 424 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX 425 int ixgbe_logtype_rx; 426 #endif 427 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX 428 int ixgbe_logtype_tx; 429 #endif 430 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE 431 int ixgbe_logtype_tx_free; 432 #endif 433 434 /* 435 * The set of PCI devices this driver supports 436 */ 437 static const struct rte_pci_id pci_id_ixgbe_map[] = { 438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) }, 439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) }, 440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) }, 441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) }, 442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) }, 443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) }, 444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) }, 445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) }, 446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) }, 447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) }, 448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) }, 449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) }, 450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) }, 451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) }, 452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) }, 453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) }, 454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) }, 455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) }, 456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) }, 457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) }, 458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) }, 459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) }, 460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) }, 461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) }, 462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) }, 463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) }, 464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) }, 465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) }, 466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) }, 467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) }, 468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) }, 469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) }, 470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) }, 471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) }, 472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) }, 473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) }, 474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) }, 475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) }, 476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) }, 477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) }, 478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) }, 479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) }, 480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) }, 481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) }, 482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) }, 483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) }, 484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) }, 485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) }, 486 #ifdef RTE_LIBRTE_IXGBE_BYPASS 487 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) }, 488 #endif 489 { .vendor_id = 0, /* sentinel */ }, 490 }; 491 492 /* 493 * The set of PCI devices this driver supports (for 82599 VF) 494 */ 495 static const struct rte_pci_id pci_id_ixgbevf_map[] = { 496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) }, 497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) }, 498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) }, 499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) }, 500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) }, 501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) }, 502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) }, 503 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) }, 504 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) }, 505 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) }, 506 { .vendor_id = 0, /* sentinel */ }, 507 }; 508 509 static const struct rte_eth_desc_lim rx_desc_lim = { 510 .nb_max = IXGBE_MAX_RING_DESC, 511 .nb_min = IXGBE_MIN_RING_DESC, 512 .nb_align = IXGBE_RXD_ALIGN, 513 }; 514 515 static const struct rte_eth_desc_lim tx_desc_lim = { 516 .nb_max = IXGBE_MAX_RING_DESC, 517 .nb_min = IXGBE_MIN_RING_DESC, 518 .nb_align = IXGBE_TXD_ALIGN, 519 .nb_seg_max = IXGBE_TX_MAX_SEG, 520 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG, 521 }; 522 523 static const struct eth_dev_ops ixgbe_eth_dev_ops = { 524 .dev_configure = ixgbe_dev_configure, 525 .dev_start = ixgbe_dev_start, 526 .dev_stop = ixgbe_dev_stop, 527 .dev_set_link_up = ixgbe_dev_set_link_up, 528 .dev_set_link_down = ixgbe_dev_set_link_down, 529 .dev_close = ixgbe_dev_close, 530 .dev_reset = ixgbe_dev_reset, 531 .promiscuous_enable = ixgbe_dev_promiscuous_enable, 532 .promiscuous_disable = ixgbe_dev_promiscuous_disable, 533 .allmulticast_enable = ixgbe_dev_allmulticast_enable, 534 .allmulticast_disable = ixgbe_dev_allmulticast_disable, 535 .link_update = ixgbe_dev_link_update, 536 .stats_get = ixgbe_dev_stats_get, 537 .xstats_get = ixgbe_dev_xstats_get, 538 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id, 539 .stats_reset = ixgbe_dev_stats_reset, 540 .xstats_reset = ixgbe_dev_xstats_reset, 541 .xstats_get_names = ixgbe_dev_xstats_get_names, 542 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id, 543 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set, 544 .fw_version_get = ixgbe_fw_version_get, 545 .dev_infos_get = ixgbe_dev_info_get, 546 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 547 .mtu_set = ixgbe_dev_mtu_set, 548 .vlan_filter_set = ixgbe_vlan_filter_set, 549 .vlan_tpid_set = ixgbe_vlan_tpid_set, 550 .vlan_offload_set = ixgbe_vlan_offload_set, 551 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set, 552 .rx_queue_start = ixgbe_dev_rx_queue_start, 553 .rx_queue_stop = ixgbe_dev_rx_queue_stop, 554 .tx_queue_start = ixgbe_dev_tx_queue_start, 555 .tx_queue_stop = ixgbe_dev_tx_queue_stop, 556 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 557 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable, 558 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable, 559 .rx_queue_release = ixgbe_dev_rx_queue_release, 560 .rx_queue_count = ixgbe_dev_rx_queue_count, 561 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done, 562 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status, 563 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status, 564 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 565 .tx_queue_release = ixgbe_dev_tx_queue_release, 566 .dev_led_on = ixgbe_dev_led_on, 567 .dev_led_off = ixgbe_dev_led_off, 568 .flow_ctrl_get = ixgbe_flow_ctrl_get, 569 .flow_ctrl_set = ixgbe_flow_ctrl_set, 570 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set, 571 .mac_addr_add = ixgbe_add_rar, 572 .mac_addr_remove = ixgbe_remove_rar, 573 .mac_addr_set = ixgbe_set_default_mac_addr, 574 .uc_hash_table_set = ixgbe_uc_hash_table_set, 575 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set, 576 .mirror_rule_set = ixgbe_mirror_rule_set, 577 .mirror_rule_reset = ixgbe_mirror_rule_reset, 578 .set_queue_rate_limit = ixgbe_set_queue_rate_limit, 579 .reta_update = ixgbe_dev_rss_reta_update, 580 .reta_query = ixgbe_dev_rss_reta_query, 581 .rss_hash_update = ixgbe_dev_rss_hash_update, 582 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 583 .filter_ctrl = ixgbe_dev_filter_ctrl, 584 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 585 .rxq_info_get = ixgbe_rxq_info_get, 586 .txq_info_get = ixgbe_txq_info_get, 587 .timesync_enable = ixgbe_timesync_enable, 588 .timesync_disable = ixgbe_timesync_disable, 589 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp, 590 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp, 591 .get_reg = ixgbe_get_regs, 592 .get_eeprom_length = ixgbe_get_eeprom_length, 593 .get_eeprom = ixgbe_get_eeprom, 594 .set_eeprom = ixgbe_set_eeprom, 595 .get_module_info = ixgbe_get_module_info, 596 .get_module_eeprom = ixgbe_get_module_eeprom, 597 .get_dcb_info = ixgbe_dev_get_dcb_info, 598 .timesync_adjust_time = ixgbe_timesync_adjust_time, 599 .timesync_read_time = ixgbe_timesync_read_time, 600 .timesync_write_time = ixgbe_timesync_write_time, 601 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf, 602 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set, 603 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add, 604 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del, 605 .tm_ops_get = ixgbe_tm_ops_get, 606 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup, 607 }; 608 609 /* 610 * dev_ops for virtual function, bare necessities for basic vf 611 * operation have been implemented 612 */ 613 static const struct eth_dev_ops ixgbevf_eth_dev_ops = { 614 .dev_configure = ixgbevf_dev_configure, 615 .dev_start = ixgbevf_dev_start, 616 .dev_stop = ixgbevf_dev_stop, 617 .link_update = ixgbevf_dev_link_update, 618 .stats_get = ixgbevf_dev_stats_get, 619 .xstats_get = ixgbevf_dev_xstats_get, 620 .stats_reset = ixgbevf_dev_stats_reset, 621 .xstats_reset = ixgbevf_dev_stats_reset, 622 .xstats_get_names = ixgbevf_dev_xstats_get_names, 623 .dev_close = ixgbevf_dev_close, 624 .dev_reset = ixgbevf_dev_reset, 625 .promiscuous_enable = ixgbevf_dev_promiscuous_enable, 626 .promiscuous_disable = ixgbevf_dev_promiscuous_disable, 627 .allmulticast_enable = ixgbevf_dev_allmulticast_enable, 628 .allmulticast_disable = ixgbevf_dev_allmulticast_disable, 629 .dev_infos_get = ixgbevf_dev_info_get, 630 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 631 .mtu_set = ixgbevf_dev_set_mtu, 632 .vlan_filter_set = ixgbevf_vlan_filter_set, 633 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set, 634 .vlan_offload_set = ixgbevf_vlan_offload_set, 635 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 636 .rx_queue_release = ixgbe_dev_rx_queue_release, 637 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done, 638 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status, 639 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status, 640 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 641 .tx_queue_release = ixgbe_dev_tx_queue_release, 642 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable, 643 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable, 644 .mac_addr_add = ixgbevf_add_mac_addr, 645 .mac_addr_remove = ixgbevf_remove_mac_addr, 646 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 647 .rxq_info_get = ixgbe_rxq_info_get, 648 .txq_info_get = ixgbe_txq_info_get, 649 .mac_addr_set = ixgbevf_set_default_mac_addr, 650 .get_reg = ixgbevf_get_regs, 651 .reta_update = ixgbe_dev_rss_reta_update, 652 .reta_query = ixgbe_dev_rss_reta_query, 653 .rss_hash_update = ixgbe_dev_rss_hash_update, 654 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 655 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup, 656 }; 657 658 /* store statistics names and its offset in stats structure */ 659 struct rte_ixgbe_xstats_name_off { 660 char name[RTE_ETH_XSTATS_NAME_SIZE]; 661 unsigned offset; 662 }; 663 664 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = { 665 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)}, 666 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)}, 667 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)}, 668 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)}, 669 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)}, 670 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)}, 671 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)}, 672 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)}, 673 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)}, 674 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)}, 675 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)}, 676 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)}, 677 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)}, 678 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)}, 679 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 680 prc1023)}, 681 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 682 prc1522)}, 683 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)}, 684 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)}, 685 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)}, 686 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)}, 687 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)}, 688 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)}, 689 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)}, 690 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)}, 691 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)}, 692 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)}, 693 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)}, 694 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)}, 695 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)}, 696 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)}, 697 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)}, 698 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)}, 699 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 700 ptc1023)}, 701 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 702 ptc1522)}, 703 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)}, 704 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)}, 705 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)}, 706 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)}, 707 708 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats, 709 fdirustat_add)}, 710 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats, 711 fdirustat_remove)}, 712 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats, 713 fdirfstat_fadd)}, 714 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats, 715 fdirfstat_fremove)}, 716 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats, 717 fdirmatch)}, 718 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats, 719 fdirmiss)}, 720 721 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)}, 722 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)}, 723 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, 724 fclast)}, 725 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)}, 726 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)}, 727 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)}, 728 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)}, 729 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats, 730 fcoe_noddp)}, 731 {"rx_fcoe_no_direct_data_placement_ext_buff", 732 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)}, 733 734 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 735 lxontxc)}, 736 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 737 lxonrxc)}, 738 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 739 lxofftxc)}, 740 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 741 lxoffrxc)}, 742 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)}, 743 }; 744 745 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \ 746 sizeof(rte_ixgbe_stats_strings[0])) 747 748 /* MACsec statistics */ 749 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = { 750 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 751 out_pkts_untagged)}, 752 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats, 753 out_pkts_encrypted)}, 754 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats, 755 out_pkts_protected)}, 756 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats, 757 out_octets_encrypted)}, 758 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats, 759 out_octets_protected)}, 760 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 761 in_pkts_untagged)}, 762 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats, 763 in_pkts_badtag)}, 764 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats, 765 in_pkts_nosci)}, 766 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats, 767 in_pkts_unknownsci)}, 768 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats, 769 in_octets_decrypted)}, 770 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats, 771 in_octets_validated)}, 772 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats, 773 in_pkts_unchecked)}, 774 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats, 775 in_pkts_delayed)}, 776 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats, 777 in_pkts_late)}, 778 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats, 779 in_pkts_ok)}, 780 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats, 781 in_pkts_invalid)}, 782 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats, 783 in_pkts_notvalid)}, 784 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats, 785 in_pkts_unusedsa)}, 786 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats, 787 in_pkts_notusingsa)}, 788 }; 789 790 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \ 791 sizeof(rte_ixgbe_macsec_strings[0])) 792 793 /* Per-queue statistics */ 794 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = { 795 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)}, 796 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)}, 797 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)}, 798 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)}, 799 }; 800 801 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \ 802 sizeof(rte_ixgbe_rxq_strings[0])) 803 #define IXGBE_NB_RXQ_PRIO_VALUES 8 804 805 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = { 806 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)}, 807 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)}, 808 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats, 809 pxon2offc)}, 810 }; 811 812 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \ 813 sizeof(rte_ixgbe_txq_strings[0])) 814 #define IXGBE_NB_TXQ_PRIO_VALUES 8 815 816 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = { 817 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)}, 818 }; 819 820 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \ 821 sizeof(rte_ixgbevf_stats_strings[0])) 822 823 /* 824 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h. 825 */ 826 static inline int 827 ixgbe_is_sfp(struct ixgbe_hw *hw) 828 { 829 switch (hw->phy.type) { 830 case ixgbe_phy_sfp_avago: 831 case ixgbe_phy_sfp_ftl: 832 case ixgbe_phy_sfp_intel: 833 case ixgbe_phy_sfp_unknown: 834 case ixgbe_phy_sfp_passive_tyco: 835 case ixgbe_phy_sfp_passive_unknown: 836 return 1; 837 default: 838 return 0; 839 } 840 } 841 842 static inline int32_t 843 ixgbe_pf_reset_hw(struct ixgbe_hw *hw) 844 { 845 uint32_t ctrl_ext; 846 int32_t status; 847 848 status = ixgbe_reset_hw(hw); 849 850 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 851 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 852 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 853 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 854 IXGBE_WRITE_FLUSH(hw); 855 856 if (status == IXGBE_ERR_SFP_NOT_PRESENT) 857 status = IXGBE_SUCCESS; 858 return status; 859 } 860 861 static inline void 862 ixgbe_enable_intr(struct rte_eth_dev *dev) 863 { 864 struct ixgbe_interrupt *intr = 865 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 866 struct ixgbe_hw *hw = 867 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 868 869 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask); 870 IXGBE_WRITE_FLUSH(hw); 871 } 872 873 /* 874 * This function is based on ixgbe_disable_intr() in base/ixgbe.h. 875 */ 876 static void 877 ixgbe_disable_intr(struct ixgbe_hw *hw) 878 { 879 PMD_INIT_FUNC_TRACE(); 880 881 if (hw->mac.type == ixgbe_mac_82598EB) { 882 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0); 883 } else { 884 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000); 885 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0); 886 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0); 887 } 888 IXGBE_WRITE_FLUSH(hw); 889 } 890 891 /* 892 * This function resets queue statistics mapping registers. 893 * From Niantic datasheet, Initialization of Statistics section: 894 * "...if software requires the queue counters, the RQSMR and TQSM registers 895 * must be re-programmed following a device reset. 896 */ 897 static void 898 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw) 899 { 900 uint32_t i; 901 902 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) { 903 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0); 904 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0); 905 } 906 } 907 908 909 static int 910 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 911 uint16_t queue_id, 912 uint8_t stat_idx, 913 uint8_t is_rx) 914 { 915 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8 916 #define NB_QMAP_FIELDS_PER_QSM_REG 4 917 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f 918 919 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 920 struct ixgbe_stat_mapping_registers *stat_mappings = 921 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private); 922 uint32_t qsmr_mask = 0; 923 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK; 924 uint32_t q_map; 925 uint8_t n, offset; 926 927 if ((hw->mac.type != ixgbe_mac_82599EB) && 928 (hw->mac.type != ixgbe_mac_X540) && 929 (hw->mac.type != ixgbe_mac_X550) && 930 (hw->mac.type != ixgbe_mac_X550EM_x) && 931 (hw->mac.type != ixgbe_mac_X550EM_a)) 932 return -ENOSYS; 933 934 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d", 935 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 936 queue_id, stat_idx); 937 938 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG); 939 if (n >= IXGBE_NB_STAT_MAPPING_REGS) { 940 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded"); 941 return -EIO; 942 } 943 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG); 944 945 /* Now clear any previous stat_idx set */ 946 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 947 if (!is_rx) 948 stat_mappings->tqsm[n] &= ~clearing_mask; 949 else 950 stat_mappings->rqsmr[n] &= ~clearing_mask; 951 952 q_map = (uint32_t)stat_idx; 953 q_map &= QMAP_FIELD_RESERVED_BITS_MASK; 954 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 955 if (!is_rx) 956 stat_mappings->tqsm[n] |= qsmr_mask; 957 else 958 stat_mappings->rqsmr[n] |= qsmr_mask; 959 960 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d", 961 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 962 queue_id, stat_idx); 963 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n, 964 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]); 965 966 /* Now write the mapping in the appropriate register */ 967 if (is_rx) { 968 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d", 969 stat_mappings->rqsmr[n], n); 970 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]); 971 } else { 972 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d", 973 stat_mappings->tqsm[n], n); 974 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]); 975 } 976 return 0; 977 } 978 979 static void 980 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev) 981 { 982 struct ixgbe_stat_mapping_registers *stat_mappings = 983 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private); 984 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 985 int i; 986 987 /* write whatever was in stat mapping table to the NIC */ 988 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) { 989 /* rx */ 990 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]); 991 992 /* tx */ 993 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]); 994 } 995 } 996 997 static void 998 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config) 999 { 1000 uint8_t i; 1001 struct ixgbe_dcb_tc_config *tc; 1002 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS; 1003 1004 dcb_config->num_tcs.pg_tcs = dcb_max_tc; 1005 dcb_config->num_tcs.pfc_tcs = dcb_max_tc; 1006 for (i = 0; i < dcb_max_tc; i++) { 1007 tc = &dcb_config->tc_config[i]; 1008 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i; 1009 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 1010 (uint8_t)(100/dcb_max_tc + (i & 1)); 1011 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i; 1012 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 1013 (uint8_t)(100/dcb_max_tc + (i & 1)); 1014 tc->pfc = ixgbe_dcb_pfc_disabled; 1015 } 1016 1017 /* Initialize default user to priority mapping, UPx->TC0 */ 1018 tc = &dcb_config->tc_config[0]; 1019 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 1020 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 1021 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) { 1022 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100; 1023 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100; 1024 } 1025 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal; 1026 dcb_config->pfc_mode_enable = false; 1027 dcb_config->vt_mode = true; 1028 dcb_config->round_robin_enable = false; 1029 /* support all DCB capabilities in 82599 */ 1030 dcb_config->support.capabilities = 0xFF; 1031 1032 /*we only support 4 Tcs for X540, X550 */ 1033 if (hw->mac.type == ixgbe_mac_X540 || 1034 hw->mac.type == ixgbe_mac_X550 || 1035 hw->mac.type == ixgbe_mac_X550EM_x || 1036 hw->mac.type == ixgbe_mac_X550EM_a) { 1037 dcb_config->num_tcs.pg_tcs = 4; 1038 dcb_config->num_tcs.pfc_tcs = 4; 1039 } 1040 } 1041 1042 /* 1043 * Ensure that all locks are released before first NVM or PHY access 1044 */ 1045 static void 1046 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw) 1047 { 1048 uint16_t mask; 1049 1050 /* 1051 * Phy lock should not fail in this early stage. If this is the case, 1052 * it is due to an improper exit of the application. 1053 * So force the release of the faulty lock. Release of common lock 1054 * is done automatically by swfw_sync function. 1055 */ 1056 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func; 1057 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1058 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func); 1059 } 1060 ixgbe_release_swfw_semaphore(hw, mask); 1061 1062 /* 1063 * These ones are more tricky since they are common to all ports; but 1064 * swfw_sync retries last long enough (1s) to be almost sure that if 1065 * lock can not be taken it is due to an improper lock of the 1066 * semaphore. 1067 */ 1068 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM; 1069 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1070 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 1071 } 1072 ixgbe_release_swfw_semaphore(hw, mask); 1073 } 1074 1075 /* 1076 * This function is based on code in ixgbe_attach() in base/ixgbe.c. 1077 * It returns 0 on success. 1078 */ 1079 static int 1080 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) 1081 { 1082 struct ixgbe_adapter *ad = eth_dev->data->dev_private; 1083 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1084 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1085 struct ixgbe_hw *hw = 1086 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1087 struct ixgbe_vfta *shadow_vfta = 1088 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1089 struct ixgbe_hwstrip *hwstrip = 1090 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1091 struct ixgbe_dcb_config *dcb_config = 1092 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private); 1093 struct ixgbe_filter_info *filter_info = 1094 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1095 struct ixgbe_bw_conf *bw_conf = 1096 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private); 1097 uint32_t ctrl_ext; 1098 uint16_t csum; 1099 int diag, i; 1100 1101 PMD_INIT_FUNC_TRACE(); 1102 1103 ixgbe_dev_macsec_setting_reset(eth_dev); 1104 1105 eth_dev->dev_ops = &ixgbe_eth_dev_ops; 1106 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1107 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1108 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts; 1109 1110 /* 1111 * For secondary processes, we don't initialise any further as primary 1112 * has already done this work. Only check we don't need a different 1113 * RX and TX function. 1114 */ 1115 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1116 struct ixgbe_tx_queue *txq; 1117 /* TX queue function in primary, set by last queue initialized 1118 * Tx queue may not initialized by primary process 1119 */ 1120 if (eth_dev->data->tx_queues) { 1121 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1]; 1122 ixgbe_set_tx_function(eth_dev, txq); 1123 } else { 1124 /* Use default TX function if we get here */ 1125 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. " 1126 "Using default TX function."); 1127 } 1128 1129 ixgbe_set_rx_function(eth_dev); 1130 1131 return 0; 1132 } 1133 1134 rte_atomic32_clear(&ad->link_thread_running); 1135 rte_eth_copy_pci_info(eth_dev, pci_dev); 1136 1137 /* Vendor and Device ID need to be set before init of shared code */ 1138 hw->device_id = pci_dev->id.device_id; 1139 hw->vendor_id = pci_dev->id.vendor_id; 1140 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1141 hw->allow_unsupported_sfp = 1; 1142 1143 /* Initialize the shared code (base driver) */ 1144 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1145 diag = ixgbe_bypass_init_shared_code(hw); 1146 #else 1147 diag = ixgbe_init_shared_code(hw); 1148 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1149 1150 if (diag != IXGBE_SUCCESS) { 1151 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag); 1152 return -EIO; 1153 } 1154 1155 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 1156 PMD_INIT_LOG(ERR, "\nERROR: " 1157 "Firmware recovery mode detected. Limiting functionality.\n" 1158 "Refer to the Intel(R) Ethernet Adapters and Devices " 1159 "User Guide for details on firmware recovery mode."); 1160 return -EIO; 1161 } 1162 1163 /* pick up the PCI bus settings for reporting later */ 1164 ixgbe_get_bus_info(hw); 1165 1166 /* Unlock any pending hardware semaphore */ 1167 ixgbe_swfw_lock_reset(hw); 1168 1169 #ifdef RTE_LIBRTE_SECURITY 1170 /* Initialize security_ctx only for primary process*/ 1171 if (ixgbe_ipsec_ctx_create(eth_dev)) 1172 return -ENOMEM; 1173 #endif 1174 1175 /* Initialize DCB configuration*/ 1176 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config)); 1177 ixgbe_dcb_init(hw, dcb_config); 1178 /* Get Hardware Flow Control setting */ 1179 hw->fc.requested_mode = ixgbe_fc_none; 1180 hw->fc.current_mode = ixgbe_fc_none; 1181 hw->fc.pause_time = IXGBE_FC_PAUSE; 1182 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 1183 hw->fc.low_water[i] = IXGBE_FC_LO; 1184 hw->fc.high_water[i] = IXGBE_FC_HI; 1185 } 1186 hw->fc.send_xon = 1; 1187 1188 /* Make sure we have a good EEPROM before we read from it */ 1189 diag = ixgbe_validate_eeprom_checksum(hw, &csum); 1190 if (diag != IXGBE_SUCCESS) { 1191 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag); 1192 return -EIO; 1193 } 1194 1195 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1196 diag = ixgbe_bypass_init_hw(hw); 1197 #else 1198 diag = ixgbe_init_hw(hw); 1199 hw->mac.autotry_restart = false; 1200 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1201 1202 /* 1203 * Devices with copper phys will fail to initialise if ixgbe_init_hw() 1204 * is called too soon after the kernel driver unbinding/binding occurs. 1205 * The failure occurs in ixgbe_identify_phy_generic() for all devices, 1206 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is 1207 * also called. See ixgbe_identify_phy_82599(). The reason for the 1208 * failure is not known, and only occuts when virtualisation features 1209 * are disabled in the bios. A delay of 100ms was found to be enough by 1210 * trial-and-error, and is doubled to be safe. 1211 */ 1212 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) { 1213 rte_delay_ms(200); 1214 diag = ixgbe_init_hw(hw); 1215 } 1216 1217 if (diag == IXGBE_ERR_SFP_NOT_PRESENT) 1218 diag = IXGBE_SUCCESS; 1219 1220 if (diag == IXGBE_ERR_EEPROM_VERSION) { 1221 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/" 1222 "LOM. Please be aware there may be issues associated " 1223 "with your hardware."); 1224 PMD_INIT_LOG(ERR, "If you are experiencing problems " 1225 "please contact your Intel or hardware representative " 1226 "who provided you with this hardware."); 1227 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED) 1228 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module"); 1229 if (diag) { 1230 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag); 1231 return -EIO; 1232 } 1233 1234 /* Reset the hw statistics */ 1235 ixgbe_dev_stats_reset(eth_dev); 1236 1237 /* disable interrupt */ 1238 ixgbe_disable_intr(hw); 1239 1240 /* reset mappings for queue statistics hw counters*/ 1241 ixgbe_reset_qstat_mappings(hw); 1242 1243 /* Allocate memory for storing MAC addresses */ 1244 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN * 1245 hw->mac.num_rar_entries, 0); 1246 if (eth_dev->data->mac_addrs == NULL) { 1247 PMD_INIT_LOG(ERR, 1248 "Failed to allocate %u bytes needed to store " 1249 "MAC addresses", 1250 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1251 return -ENOMEM; 1252 } 1253 /* Copy the permanent MAC address */ 1254 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr, 1255 ð_dev->data->mac_addrs[0]); 1256 1257 /* Allocate memory for storing hash filter MAC addresses */ 1258 eth_dev->data->hash_mac_addrs = rte_zmalloc( 1259 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0); 1260 if (eth_dev->data->hash_mac_addrs == NULL) { 1261 PMD_INIT_LOG(ERR, 1262 "Failed to allocate %d bytes needed to store MAC addresses", 1263 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC); 1264 return -ENOMEM; 1265 } 1266 1267 /* Pass the information to the rte_eth_dev_close() that it should also 1268 * release the private port resources. 1269 */ 1270 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1271 1272 /* initialize the vfta */ 1273 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1274 1275 /* initialize the hw strip bitmap*/ 1276 memset(hwstrip, 0, sizeof(*hwstrip)); 1277 1278 /* initialize PF if max_vfs not zero */ 1279 ixgbe_pf_host_init(eth_dev); 1280 1281 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 1282 /* let hardware know driver is loaded */ 1283 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD; 1284 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 1285 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 1286 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 1287 IXGBE_WRITE_FLUSH(hw); 1288 1289 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 1290 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d", 1291 (int) hw->mac.type, (int) hw->phy.type, 1292 (int) hw->phy.sfp_type); 1293 else 1294 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d", 1295 (int) hw->mac.type, (int) hw->phy.type); 1296 1297 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 1298 eth_dev->data->port_id, pci_dev->id.vendor_id, 1299 pci_dev->id.device_id); 1300 1301 rte_intr_callback_register(intr_handle, 1302 ixgbe_dev_interrupt_handler, eth_dev); 1303 1304 /* enable uio/vfio intr/eventfd mapping */ 1305 rte_intr_enable(intr_handle); 1306 1307 /* enable support intr */ 1308 ixgbe_enable_intr(eth_dev); 1309 1310 ixgbe_dev_set_link_down(eth_dev); 1311 1312 /* initialize filter info */ 1313 memset(filter_info, 0, 1314 sizeof(struct ixgbe_filter_info)); 1315 1316 /* initialize 5tuple filter list */ 1317 TAILQ_INIT(&filter_info->fivetuple_list); 1318 1319 /* initialize flow director filter list & hash */ 1320 ixgbe_fdir_filter_init(eth_dev); 1321 1322 /* initialize l2 tunnel filter list & hash */ 1323 ixgbe_l2_tn_filter_init(eth_dev); 1324 1325 /* initialize flow filter lists */ 1326 ixgbe_filterlist_init(); 1327 1328 /* initialize bandwidth configuration info */ 1329 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf)); 1330 1331 /* initialize Traffic Manager configuration */ 1332 ixgbe_tm_conf_init(eth_dev); 1333 1334 return 0; 1335 } 1336 1337 static int 1338 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1339 { 1340 PMD_INIT_FUNC_TRACE(); 1341 1342 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1343 return 0; 1344 1345 ixgbe_dev_close(eth_dev); 1346 1347 return 0; 1348 } 1349 1350 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev) 1351 { 1352 struct ixgbe_filter_info *filter_info = 1353 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1354 struct ixgbe_5tuple_filter *p_5tuple; 1355 1356 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) { 1357 TAILQ_REMOVE(&filter_info->fivetuple_list, 1358 p_5tuple, 1359 entries); 1360 rte_free(p_5tuple); 1361 } 1362 memset(filter_info->fivetuple_mask, 0, 1363 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE); 1364 1365 return 0; 1366 } 1367 1368 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev) 1369 { 1370 struct ixgbe_hw_fdir_info *fdir_info = 1371 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1372 struct ixgbe_fdir_filter *fdir_filter; 1373 1374 if (fdir_info->hash_map) 1375 rte_free(fdir_info->hash_map); 1376 if (fdir_info->hash_handle) 1377 rte_hash_free(fdir_info->hash_handle); 1378 1379 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 1380 TAILQ_REMOVE(&fdir_info->fdir_list, 1381 fdir_filter, 1382 entries); 1383 rte_free(fdir_filter); 1384 } 1385 1386 return 0; 1387 } 1388 1389 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev) 1390 { 1391 struct ixgbe_l2_tn_info *l2_tn_info = 1392 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1393 struct ixgbe_l2_tn_filter *l2_tn_filter; 1394 1395 if (l2_tn_info->hash_map) 1396 rte_free(l2_tn_info->hash_map); 1397 if (l2_tn_info->hash_handle) 1398 rte_hash_free(l2_tn_info->hash_handle); 1399 1400 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 1401 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, 1402 l2_tn_filter, 1403 entries); 1404 rte_free(l2_tn_filter); 1405 } 1406 1407 return 0; 1408 } 1409 1410 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev) 1411 { 1412 struct ixgbe_hw_fdir_info *fdir_info = 1413 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1414 char fdir_hash_name[RTE_HASH_NAMESIZE]; 1415 struct rte_hash_parameters fdir_hash_params = { 1416 .name = fdir_hash_name, 1417 .entries = IXGBE_MAX_FDIR_FILTER_NUM, 1418 .key_len = sizeof(union ixgbe_atr_input), 1419 .hash_func = rte_hash_crc, 1420 .hash_func_init_val = 0, 1421 .socket_id = rte_socket_id(), 1422 }; 1423 1424 TAILQ_INIT(&fdir_info->fdir_list); 1425 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 1426 "fdir_%s", eth_dev->device->name); 1427 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params); 1428 if (!fdir_info->hash_handle) { 1429 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 1430 return -EINVAL; 1431 } 1432 fdir_info->hash_map = rte_zmalloc("ixgbe", 1433 sizeof(struct ixgbe_fdir_filter *) * 1434 IXGBE_MAX_FDIR_FILTER_NUM, 1435 0); 1436 if (!fdir_info->hash_map) { 1437 PMD_INIT_LOG(ERR, 1438 "Failed to allocate memory for fdir hash map!"); 1439 return -ENOMEM; 1440 } 1441 fdir_info->mask_added = FALSE; 1442 1443 return 0; 1444 } 1445 1446 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) 1447 { 1448 struct ixgbe_l2_tn_info *l2_tn_info = 1449 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1450 char l2_tn_hash_name[RTE_HASH_NAMESIZE]; 1451 struct rte_hash_parameters l2_tn_hash_params = { 1452 .name = l2_tn_hash_name, 1453 .entries = IXGBE_MAX_L2_TN_FILTER_NUM, 1454 .key_len = sizeof(struct ixgbe_l2_tn_key), 1455 .hash_func = rte_hash_crc, 1456 .hash_func_init_val = 0, 1457 .socket_id = rte_socket_id(), 1458 }; 1459 1460 TAILQ_INIT(&l2_tn_info->l2_tn_list); 1461 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE, 1462 "l2_tn_%s", eth_dev->device->name); 1463 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params); 1464 if (!l2_tn_info->hash_handle) { 1465 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!"); 1466 return -EINVAL; 1467 } 1468 l2_tn_info->hash_map = rte_zmalloc("ixgbe", 1469 sizeof(struct ixgbe_l2_tn_filter *) * 1470 IXGBE_MAX_L2_TN_FILTER_NUM, 1471 0); 1472 if (!l2_tn_info->hash_map) { 1473 PMD_INIT_LOG(ERR, 1474 "Failed to allocate memory for L2 TN hash map!"); 1475 return -ENOMEM; 1476 } 1477 l2_tn_info->e_tag_en = FALSE; 1478 l2_tn_info->e_tag_fwd_en = FALSE; 1479 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG; 1480 1481 return 0; 1482 } 1483 /* 1484 * Negotiate mailbox API version with the PF. 1485 * After reset API version is always set to the basic one (ixgbe_mbox_api_10). 1486 * Then we try to negotiate starting with the most recent one. 1487 * If all negotiation attempts fail, then we will proceed with 1488 * the default one (ixgbe_mbox_api_10). 1489 */ 1490 static void 1491 ixgbevf_negotiate_api(struct ixgbe_hw *hw) 1492 { 1493 int32_t i; 1494 1495 /* start with highest supported, proceed down */ 1496 static const enum ixgbe_pfvf_api_rev sup_ver[] = { 1497 ixgbe_mbox_api_13, 1498 ixgbe_mbox_api_12, 1499 ixgbe_mbox_api_11, 1500 ixgbe_mbox_api_10, 1501 }; 1502 1503 for (i = 0; 1504 i != RTE_DIM(sup_ver) && 1505 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0; 1506 i++) 1507 ; 1508 } 1509 1510 static void 1511 generate_random_mac_addr(struct rte_ether_addr *mac_addr) 1512 { 1513 uint64_t random; 1514 1515 /* Set Organizationally Unique Identifier (OUI) prefix. */ 1516 mac_addr->addr_bytes[0] = 0x00; 1517 mac_addr->addr_bytes[1] = 0x09; 1518 mac_addr->addr_bytes[2] = 0xC0; 1519 /* Force indication of locally assigned MAC address. */ 1520 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR; 1521 /* Generate the last 3 bytes of the MAC address with a random number. */ 1522 random = rte_rand(); 1523 memcpy(&mac_addr->addr_bytes[3], &random, 3); 1524 } 1525 1526 static int 1527 devarg_handle_int(__rte_unused const char *key, const char *value, 1528 void *extra_args) 1529 { 1530 uint16_t *n = extra_args; 1531 1532 if (value == NULL || extra_args == NULL) 1533 return -EINVAL; 1534 1535 *n = (uint16_t)strtoul(value, NULL, 0); 1536 if (*n == USHRT_MAX && errno == ERANGE) 1537 return -1; 1538 1539 return 0; 1540 } 1541 1542 static void 1543 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter, 1544 struct rte_devargs *devargs) 1545 { 1546 struct rte_kvargs *kvlist; 1547 uint16_t pflink_fullchk; 1548 1549 if (devargs == NULL) 1550 return; 1551 1552 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments); 1553 if (kvlist == NULL) 1554 return; 1555 1556 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 && 1557 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK, 1558 devarg_handle_int, &pflink_fullchk) == 0 && 1559 pflink_fullchk == 1) 1560 adapter->pflink_fullchk = 1; 1561 1562 rte_kvargs_free(kvlist); 1563 } 1564 1565 /* 1566 * Virtual Function device init 1567 */ 1568 static int 1569 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev) 1570 { 1571 int diag; 1572 uint32_t tc, tcs; 1573 struct ixgbe_adapter *ad = eth_dev->data->dev_private; 1574 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1575 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1576 struct ixgbe_hw *hw = 1577 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1578 struct ixgbe_vfta *shadow_vfta = 1579 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1580 struct ixgbe_hwstrip *hwstrip = 1581 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1582 struct rte_ether_addr *perm_addr = 1583 (struct rte_ether_addr *)hw->mac.perm_addr; 1584 1585 PMD_INIT_FUNC_TRACE(); 1586 1587 eth_dev->dev_ops = &ixgbevf_eth_dev_ops; 1588 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1589 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1590 1591 /* for secondary processes, we don't initialise any further as primary 1592 * has already done this work. Only check we don't need a different 1593 * RX function 1594 */ 1595 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1596 struct ixgbe_tx_queue *txq; 1597 /* TX queue function in primary, set by last queue initialized 1598 * Tx queue may not initialized by primary process 1599 */ 1600 if (eth_dev->data->tx_queues) { 1601 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1]; 1602 ixgbe_set_tx_function(eth_dev, txq); 1603 } else { 1604 /* Use default TX function if we get here */ 1605 PMD_INIT_LOG(NOTICE, 1606 "No TX queues configured yet. Using default TX function."); 1607 } 1608 1609 ixgbe_set_rx_function(eth_dev); 1610 1611 return 0; 1612 } 1613 1614 rte_atomic32_clear(&ad->link_thread_running); 1615 ixgbevf_parse_devargs(eth_dev->data->dev_private, 1616 pci_dev->device.devargs); 1617 1618 rte_eth_copy_pci_info(eth_dev, pci_dev); 1619 1620 hw->device_id = pci_dev->id.device_id; 1621 hw->vendor_id = pci_dev->id.vendor_id; 1622 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1623 1624 /* initialize the vfta */ 1625 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1626 1627 /* initialize the hw strip bitmap*/ 1628 memset(hwstrip, 0, sizeof(*hwstrip)); 1629 1630 /* Initialize the shared code (base driver) */ 1631 diag = ixgbe_init_shared_code(hw); 1632 if (diag != IXGBE_SUCCESS) { 1633 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag); 1634 return -EIO; 1635 } 1636 1637 /* init_mailbox_params */ 1638 hw->mbx.ops.init_params(hw); 1639 1640 /* Reset the hw statistics */ 1641 ixgbevf_dev_stats_reset(eth_dev); 1642 1643 /* Disable the interrupts for VF */ 1644 ixgbevf_intr_disable(eth_dev); 1645 1646 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */ 1647 diag = hw->mac.ops.reset_hw(hw); 1648 1649 /* 1650 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when 1651 * the underlying PF driver has not assigned a MAC address to the VF. 1652 * In this case, assign a random MAC address. 1653 */ 1654 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) { 1655 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1656 /* 1657 * This error code will be propagated to the app by 1658 * rte_eth_dev_reset, so use a public error code rather than 1659 * the internal-only IXGBE_ERR_RESET_FAILED 1660 */ 1661 return -EAGAIN; 1662 } 1663 1664 /* negotiate mailbox API version to use with the PF. */ 1665 ixgbevf_negotiate_api(hw); 1666 1667 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */ 1668 ixgbevf_get_queues(hw, &tcs, &tc); 1669 1670 /* Allocate memory for storing MAC addresses */ 1671 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN * 1672 hw->mac.num_rar_entries, 0); 1673 if (eth_dev->data->mac_addrs == NULL) { 1674 PMD_INIT_LOG(ERR, 1675 "Failed to allocate %u bytes needed to store " 1676 "MAC addresses", 1677 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1678 return -ENOMEM; 1679 } 1680 1681 /* Pass the information to the rte_eth_dev_close() that it should also 1682 * release the private port resources. 1683 */ 1684 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1685 1686 /* Generate a random MAC address, if none was assigned by PF. */ 1687 if (rte_is_zero_ether_addr(perm_addr)) { 1688 generate_random_mac_addr(perm_addr); 1689 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1); 1690 if (diag) { 1691 rte_free(eth_dev->data->mac_addrs); 1692 eth_dev->data->mac_addrs = NULL; 1693 return diag; 1694 } 1695 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF"); 1696 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address " 1697 "%02x:%02x:%02x:%02x:%02x:%02x", 1698 perm_addr->addr_bytes[0], 1699 perm_addr->addr_bytes[1], 1700 perm_addr->addr_bytes[2], 1701 perm_addr->addr_bytes[3], 1702 perm_addr->addr_bytes[4], 1703 perm_addr->addr_bytes[5]); 1704 } 1705 1706 /* Copy the permanent MAC address */ 1707 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]); 1708 1709 /* reset the hardware with the new settings */ 1710 diag = hw->mac.ops.start_hw(hw); 1711 switch (diag) { 1712 case 0: 1713 break; 1714 1715 default: 1716 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1717 return -EIO; 1718 } 1719 1720 rte_intr_callback_register(intr_handle, 1721 ixgbevf_dev_interrupt_handler, eth_dev); 1722 rte_intr_enable(intr_handle); 1723 ixgbevf_intr_enable(eth_dev); 1724 1725 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s", 1726 eth_dev->data->port_id, pci_dev->id.vendor_id, 1727 pci_dev->id.device_id, "ixgbe_mac_82599_vf"); 1728 1729 return 0; 1730 } 1731 1732 /* Virtual Function device uninit */ 1733 1734 static int 1735 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev) 1736 { 1737 PMD_INIT_FUNC_TRACE(); 1738 1739 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1740 return 0; 1741 1742 ixgbevf_dev_close(eth_dev); 1743 1744 return 0; 1745 } 1746 1747 static int 1748 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1749 struct rte_pci_device *pci_dev) 1750 { 1751 char name[RTE_ETH_NAME_MAX_LEN]; 1752 struct rte_eth_dev *pf_ethdev; 1753 struct rte_eth_devargs eth_da; 1754 int i, retval; 1755 1756 if (pci_dev->device.devargs) { 1757 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 1758 ð_da); 1759 if (retval) 1760 return retval; 1761 } else 1762 memset(ð_da, 0, sizeof(eth_da)); 1763 1764 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 1765 sizeof(struct ixgbe_adapter), 1766 eth_dev_pci_specific_init, pci_dev, 1767 eth_ixgbe_dev_init, NULL); 1768 1769 if (retval || eth_da.nb_representor_ports < 1) 1770 return retval; 1771 1772 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1773 if (pf_ethdev == NULL) 1774 return -ENODEV; 1775 1776 /* probe VF representor ports */ 1777 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1778 struct ixgbe_vf_info *vfinfo; 1779 struct ixgbe_vf_representor representor; 1780 1781 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA( 1782 pf_ethdev->data->dev_private); 1783 if (vfinfo == NULL) { 1784 PMD_DRV_LOG(ERR, 1785 "no virtual functions supported by PF"); 1786 break; 1787 } 1788 1789 representor.vf_id = eth_da.representor_ports[i]; 1790 representor.switch_domain_id = vfinfo->switch_domain_id; 1791 representor.pf_ethdev = pf_ethdev; 1792 1793 /* representor port net_bdf_port */ 1794 snprintf(name, sizeof(name), "net_%s_representor_%d", 1795 pci_dev->device.name, 1796 eth_da.representor_ports[i]); 1797 1798 retval = rte_eth_dev_create(&pci_dev->device, name, 1799 sizeof(struct ixgbe_vf_representor), NULL, NULL, 1800 ixgbe_vf_representor_init, &representor); 1801 1802 if (retval) 1803 PMD_DRV_LOG(ERR, "failed to create ixgbe vf " 1804 "representor %s.", name); 1805 } 1806 1807 return 0; 1808 } 1809 1810 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev) 1811 { 1812 struct rte_eth_dev *ethdev; 1813 1814 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1815 if (!ethdev) 1816 return 0; 1817 1818 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 1819 return rte_eth_dev_pci_generic_remove(pci_dev, 1820 ixgbe_vf_representor_uninit); 1821 else 1822 return rte_eth_dev_pci_generic_remove(pci_dev, 1823 eth_ixgbe_dev_uninit); 1824 } 1825 1826 static struct rte_pci_driver rte_ixgbe_pmd = { 1827 .id_table = pci_id_ixgbe_map, 1828 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1829 .probe = eth_ixgbe_pci_probe, 1830 .remove = eth_ixgbe_pci_remove, 1831 }; 1832 1833 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1834 struct rte_pci_device *pci_dev) 1835 { 1836 return rte_eth_dev_pci_generic_probe(pci_dev, 1837 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init); 1838 } 1839 1840 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev) 1841 { 1842 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit); 1843 } 1844 1845 /* 1846 * virtual function driver struct 1847 */ 1848 static struct rte_pci_driver rte_ixgbevf_pmd = { 1849 .id_table = pci_id_ixgbevf_map, 1850 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1851 .probe = eth_ixgbevf_pci_probe, 1852 .remove = eth_ixgbevf_pci_remove, 1853 }; 1854 1855 static int 1856 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1857 { 1858 struct ixgbe_hw *hw = 1859 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1860 struct ixgbe_vfta *shadow_vfta = 1861 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1862 uint32_t vfta; 1863 uint32_t vid_idx; 1864 uint32_t vid_bit; 1865 1866 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 1867 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 1868 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx)); 1869 if (on) 1870 vfta |= vid_bit; 1871 else 1872 vfta &= ~vid_bit; 1873 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta); 1874 1875 /* update local VFTA copy */ 1876 shadow_vfta->vfta[vid_idx] = vfta; 1877 1878 return 0; 1879 } 1880 1881 static void 1882 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 1883 { 1884 if (on) 1885 ixgbe_vlan_hw_strip_enable(dev, queue); 1886 else 1887 ixgbe_vlan_hw_strip_disable(dev, queue); 1888 } 1889 1890 static int 1891 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1892 enum rte_vlan_type vlan_type, 1893 uint16_t tpid) 1894 { 1895 struct ixgbe_hw *hw = 1896 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1897 int ret = 0; 1898 uint32_t reg; 1899 uint32_t qinq; 1900 1901 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1902 qinq &= IXGBE_DMATXCTL_GDV; 1903 1904 switch (vlan_type) { 1905 case ETH_VLAN_TYPE_INNER: 1906 if (qinq) { 1907 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1908 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1909 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1910 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1911 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1912 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1913 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1914 } else { 1915 ret = -ENOTSUP; 1916 PMD_DRV_LOG(ERR, "Inner type is not supported" 1917 " by single VLAN"); 1918 } 1919 break; 1920 case ETH_VLAN_TYPE_OUTER: 1921 if (qinq) { 1922 /* Only the high 16-bits is valid */ 1923 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid << 1924 IXGBE_EXVET_VET_EXT_SHIFT); 1925 } else { 1926 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1927 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1928 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1929 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1930 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1931 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1932 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1933 } 1934 1935 break; 1936 default: 1937 ret = -EINVAL; 1938 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type); 1939 break; 1940 } 1941 1942 return ret; 1943 } 1944 1945 void 1946 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev) 1947 { 1948 struct ixgbe_hw *hw = 1949 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1950 uint32_t vlnctrl; 1951 1952 PMD_INIT_FUNC_TRACE(); 1953 1954 /* Filter Table Disable */ 1955 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1956 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 1957 1958 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1959 } 1960 1961 void 1962 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1963 { 1964 struct ixgbe_hw *hw = 1965 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1966 struct ixgbe_vfta *shadow_vfta = 1967 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1968 uint32_t vlnctrl; 1969 uint16_t i; 1970 1971 PMD_INIT_FUNC_TRACE(); 1972 1973 /* Filter Table Enable */ 1974 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1975 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; 1976 vlnctrl |= IXGBE_VLNCTRL_VFE; 1977 1978 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1979 1980 /* write whatever is in local vfta copy */ 1981 for (i = 0; i < IXGBE_VFTA_SIZE; i++) 1982 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]); 1983 } 1984 1985 static void 1986 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on) 1987 { 1988 struct ixgbe_hwstrip *hwstrip = 1989 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private); 1990 struct ixgbe_rx_queue *rxq; 1991 1992 if (queue >= IXGBE_MAX_RX_QUEUE_NUM) 1993 return; 1994 1995 if (on) 1996 IXGBE_SET_HWSTRIP(hwstrip, queue); 1997 else 1998 IXGBE_CLEAR_HWSTRIP(hwstrip, queue); 1999 2000 if (queue >= dev->data->nb_rx_queues) 2001 return; 2002 2003 rxq = dev->data->rx_queues[queue]; 2004 2005 if (on) { 2006 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; 2007 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 2008 } else { 2009 rxq->vlan_flags = PKT_RX_VLAN; 2010 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 2011 } 2012 } 2013 2014 static void 2015 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue) 2016 { 2017 struct ixgbe_hw *hw = 2018 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2019 uint32_t ctrl; 2020 2021 PMD_INIT_FUNC_TRACE(); 2022 2023 if (hw->mac.type == ixgbe_mac_82598EB) { 2024 /* No queue level support */ 2025 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2026 return; 2027 } 2028 2029 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2030 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2031 ctrl &= ~IXGBE_RXDCTL_VME; 2032 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2033 2034 /* record those setting for HW strip per queue */ 2035 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0); 2036 } 2037 2038 static void 2039 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue) 2040 { 2041 struct ixgbe_hw *hw = 2042 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2043 uint32_t ctrl; 2044 2045 PMD_INIT_FUNC_TRACE(); 2046 2047 if (hw->mac.type == ixgbe_mac_82598EB) { 2048 /* No queue level supported */ 2049 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2050 return; 2051 } 2052 2053 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2054 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2055 ctrl |= IXGBE_RXDCTL_VME; 2056 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2057 2058 /* record those setting for HW strip per queue */ 2059 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1); 2060 } 2061 2062 static void 2063 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev) 2064 { 2065 struct ixgbe_hw *hw = 2066 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2067 uint32_t ctrl; 2068 2069 PMD_INIT_FUNC_TRACE(); 2070 2071 /* DMATXCTRL: Geric Double VLAN Disable */ 2072 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2073 ctrl &= ~IXGBE_DMATXCTL_GDV; 2074 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2075 2076 /* CTRL_EXT: Global Double VLAN Disable */ 2077 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2078 ctrl &= ~IXGBE_EXTENDED_VLAN; 2079 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2080 2081 } 2082 2083 static void 2084 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) 2085 { 2086 struct ixgbe_hw *hw = 2087 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2088 uint32_t ctrl; 2089 2090 PMD_INIT_FUNC_TRACE(); 2091 2092 /* DMATXCTRL: Geric Double VLAN Enable */ 2093 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2094 ctrl |= IXGBE_DMATXCTL_GDV; 2095 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2096 2097 /* CTRL_EXT: Global Double VLAN Enable */ 2098 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2099 ctrl |= IXGBE_EXTENDED_VLAN; 2100 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2101 2102 /* Clear pooling mode of PFVTCTL. It's required by X550. */ 2103 if (hw->mac.type == ixgbe_mac_X550 || 2104 hw->mac.type == ixgbe_mac_X550EM_x || 2105 hw->mac.type == ixgbe_mac_X550EM_a) { 2106 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 2107 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 2108 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 2109 } 2110 2111 /* 2112 * VET EXT field in the EXVET register = 0x8100 by default 2113 * So no need to change. Same to VT field of DMATXCTL register 2114 */ 2115 } 2116 2117 void 2118 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev) 2119 { 2120 struct ixgbe_hw *hw = 2121 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2122 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 2123 uint32_t ctrl; 2124 uint16_t i; 2125 struct ixgbe_rx_queue *rxq; 2126 bool on; 2127 2128 PMD_INIT_FUNC_TRACE(); 2129 2130 if (hw->mac.type == ixgbe_mac_82598EB) { 2131 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2132 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2133 ctrl |= IXGBE_VLNCTRL_VME; 2134 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2135 } else { 2136 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2137 ctrl &= ~IXGBE_VLNCTRL_VME; 2138 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2139 } 2140 } else { 2141 /* 2142 * Other 10G NIC, the VLAN strip can be setup 2143 * per queue in RXDCTL 2144 */ 2145 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2146 rxq = dev->data->rx_queues[i]; 2147 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx)); 2148 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2149 ctrl |= IXGBE_RXDCTL_VME; 2150 on = TRUE; 2151 } else { 2152 ctrl &= ~IXGBE_RXDCTL_VME; 2153 on = FALSE; 2154 } 2155 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl); 2156 2157 /* record those setting for HW strip per queue */ 2158 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on); 2159 } 2160 } 2161 } 2162 2163 static void 2164 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask) 2165 { 2166 uint16_t i; 2167 struct rte_eth_rxmode *rxmode; 2168 struct ixgbe_rx_queue *rxq; 2169 2170 if (mask & ETH_VLAN_STRIP_MASK) { 2171 rxmode = &dev->data->dev_conf.rxmode; 2172 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 2173 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2174 rxq = dev->data->rx_queues[i]; 2175 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 2176 } 2177 else 2178 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2179 rxq = dev->data->rx_queues[i]; 2180 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 2181 } 2182 } 2183 } 2184 2185 static int 2186 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask) 2187 { 2188 struct rte_eth_rxmode *rxmode; 2189 rxmode = &dev->data->dev_conf.rxmode; 2190 2191 if (mask & ETH_VLAN_STRIP_MASK) { 2192 ixgbe_vlan_hw_strip_config(dev); 2193 } 2194 2195 if (mask & ETH_VLAN_FILTER_MASK) { 2196 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 2197 ixgbe_vlan_hw_filter_enable(dev); 2198 else 2199 ixgbe_vlan_hw_filter_disable(dev); 2200 } 2201 2202 if (mask & ETH_VLAN_EXTEND_MASK) { 2203 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2204 ixgbe_vlan_hw_extend_enable(dev); 2205 else 2206 ixgbe_vlan_hw_extend_disable(dev); 2207 } 2208 2209 return 0; 2210 } 2211 2212 static int 2213 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2214 { 2215 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 2216 2217 ixgbe_vlan_offload_config(dev, mask); 2218 2219 return 0; 2220 } 2221 2222 static void 2223 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev) 2224 { 2225 struct ixgbe_hw *hw = 2226 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2227 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */ 2228 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2229 2230 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */ 2231 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl); 2232 } 2233 2234 static int 2235 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q) 2236 { 2237 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2238 2239 switch (nb_rx_q) { 2240 case 1: 2241 case 2: 2242 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS; 2243 break; 2244 case 4: 2245 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS; 2246 break; 2247 default: 2248 return -EINVAL; 2249 } 2250 2251 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 2252 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2253 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 2254 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2255 return 0; 2256 } 2257 2258 static int 2259 ixgbe_check_mq_mode(struct rte_eth_dev *dev) 2260 { 2261 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 2262 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2263 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2264 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2265 2266 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 2267 /* check multi-queue mode */ 2268 switch (dev_conf->rxmode.mq_mode) { 2269 case ETH_MQ_RX_VMDQ_DCB: 2270 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV"); 2271 break; 2272 case ETH_MQ_RX_VMDQ_DCB_RSS: 2273 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */ 2274 PMD_INIT_LOG(ERR, "SRIOV active," 2275 " unsupported mq_mode rx %d.", 2276 dev_conf->rxmode.mq_mode); 2277 return -EINVAL; 2278 case ETH_MQ_RX_RSS: 2279 case ETH_MQ_RX_VMDQ_RSS: 2280 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS; 2281 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) 2282 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) { 2283 PMD_INIT_LOG(ERR, "SRIOV is active," 2284 " invalid queue number" 2285 " for VMDQ RSS, allowed" 2286 " value are 1, 2 or 4."); 2287 return -EINVAL; 2288 } 2289 break; 2290 case ETH_MQ_RX_VMDQ_ONLY: 2291 case ETH_MQ_RX_NONE: 2292 /* if nothing mq mode configure, use default scheme */ 2293 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY; 2294 break; 2295 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/ 2296 /* SRIOV only works in VMDq enable mode */ 2297 PMD_INIT_LOG(ERR, "SRIOV is active," 2298 " wrong mq_mode rx %d.", 2299 dev_conf->rxmode.mq_mode); 2300 return -EINVAL; 2301 } 2302 2303 switch (dev_conf->txmode.mq_mode) { 2304 case ETH_MQ_TX_VMDQ_DCB: 2305 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV"); 2306 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB; 2307 break; 2308 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */ 2309 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY; 2310 break; 2311 } 2312 2313 /* check valid queue number */ 2314 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) || 2315 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) { 2316 PMD_INIT_LOG(ERR, "SRIOV is active," 2317 " nb_rx_q=%d nb_tx_q=%d queue number" 2318 " must be less than or equal to %d.", 2319 nb_rx_q, nb_tx_q, 2320 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool); 2321 return -EINVAL; 2322 } 2323 } else { 2324 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) { 2325 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is" 2326 " not supported."); 2327 return -EINVAL; 2328 } 2329 /* check configuration for vmdb+dcb mode */ 2330 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) { 2331 const struct rte_eth_vmdq_dcb_conf *conf; 2332 2333 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2334 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.", 2335 IXGBE_VMDQ_DCB_NB_QUEUES); 2336 return -EINVAL; 2337 } 2338 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf; 2339 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2340 conf->nb_queue_pools == ETH_32_POOLS)) { 2341 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2342 " nb_queue_pools must be %d or %d.", 2343 ETH_16_POOLS, ETH_32_POOLS); 2344 return -EINVAL; 2345 } 2346 } 2347 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) { 2348 const struct rte_eth_vmdq_dcb_tx_conf *conf; 2349 2350 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2351 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d", 2352 IXGBE_VMDQ_DCB_NB_QUEUES); 2353 return -EINVAL; 2354 } 2355 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf; 2356 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2357 conf->nb_queue_pools == ETH_32_POOLS)) { 2358 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2359 " nb_queue_pools != %d and" 2360 " nb_queue_pools != %d.", 2361 ETH_16_POOLS, ETH_32_POOLS); 2362 return -EINVAL; 2363 } 2364 } 2365 2366 /* For DCB mode check our configuration before we go further */ 2367 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) { 2368 const struct rte_eth_dcb_rx_conf *conf; 2369 2370 conf = &dev_conf->rx_adv_conf.dcb_rx_conf; 2371 if (!(conf->nb_tcs == ETH_4_TCS || 2372 conf->nb_tcs == ETH_8_TCS)) { 2373 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2374 " and nb_tcs != %d.", 2375 ETH_4_TCS, ETH_8_TCS); 2376 return -EINVAL; 2377 } 2378 } 2379 2380 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) { 2381 const struct rte_eth_dcb_tx_conf *conf; 2382 2383 conf = &dev_conf->tx_adv_conf.dcb_tx_conf; 2384 if (!(conf->nb_tcs == ETH_4_TCS || 2385 conf->nb_tcs == ETH_8_TCS)) { 2386 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2387 " and nb_tcs != %d.", 2388 ETH_4_TCS, ETH_8_TCS); 2389 return -EINVAL; 2390 } 2391 } 2392 2393 /* 2394 * When DCB/VT is off, maximum number of queues changes, 2395 * except for 82598EB, which remains constant. 2396 */ 2397 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 2398 hw->mac.type != ixgbe_mac_82598EB) { 2399 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) { 2400 PMD_INIT_LOG(ERR, 2401 "Neither VT nor DCB are enabled, " 2402 "nb_tx_q > %d.", 2403 IXGBE_NONE_MODE_TX_NB_QUEUES); 2404 return -EINVAL; 2405 } 2406 } 2407 } 2408 return 0; 2409 } 2410 2411 static int 2412 ixgbe_dev_configure(struct rte_eth_dev *dev) 2413 { 2414 struct ixgbe_interrupt *intr = 2415 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2416 struct ixgbe_adapter *adapter = dev->data->dev_private; 2417 int ret; 2418 2419 PMD_INIT_FUNC_TRACE(); 2420 2421 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 2422 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 2423 2424 /* multipe queue mode checking */ 2425 ret = ixgbe_check_mq_mode(dev); 2426 if (ret != 0) { 2427 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.", 2428 ret); 2429 return ret; 2430 } 2431 2432 /* set flag to update link status after init */ 2433 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2434 2435 /* 2436 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 2437 * allocation or vector Rx preconditions we will reset it. 2438 */ 2439 adapter->rx_bulk_alloc_allowed = true; 2440 adapter->rx_vec_allowed = true; 2441 2442 return 0; 2443 } 2444 2445 static void 2446 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) 2447 { 2448 struct ixgbe_hw *hw = 2449 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2450 struct ixgbe_interrupt *intr = 2451 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2452 uint32_t gpie; 2453 2454 /* only set up it on X550EM_X */ 2455 if (hw->mac.type == ixgbe_mac_X550EM_x) { 2456 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 2457 gpie |= IXGBE_SDP0_GPIEN_X550EM_x; 2458 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 2459 if (hw->phy.type == ixgbe_phy_x550em_ext_t) 2460 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x; 2461 } 2462 } 2463 2464 int 2465 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 2466 uint16_t tx_rate, uint64_t q_msk) 2467 { 2468 struct ixgbe_hw *hw; 2469 struct ixgbe_vf_info *vfinfo; 2470 struct rte_eth_link link; 2471 uint8_t nb_q_per_pool; 2472 uint32_t queue_stride; 2473 uint32_t queue_idx, idx = 0, vf_idx; 2474 uint32_t queue_end; 2475 uint16_t total_rate = 0; 2476 struct rte_pci_device *pci_dev; 2477 int ret; 2478 2479 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2480 ret = rte_eth_link_get_nowait(dev->data->port_id, &link); 2481 if (ret < 0) 2482 return ret; 2483 2484 if (vf >= pci_dev->max_vfs) 2485 return -EINVAL; 2486 2487 if (tx_rate > link.link_speed) 2488 return -EINVAL; 2489 2490 if (q_msk == 0) 2491 return 0; 2492 2493 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2494 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 2495 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2496 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2497 queue_idx = vf * queue_stride; 2498 queue_end = queue_idx + nb_q_per_pool - 1; 2499 if (queue_end >= hw->mac.max_tx_queues) 2500 return -EINVAL; 2501 2502 if (vfinfo) { 2503 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) { 2504 if (vf_idx == vf) 2505 continue; 2506 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate); 2507 idx++) 2508 total_rate += vfinfo[vf_idx].tx_rate[idx]; 2509 } 2510 } else { 2511 return -EINVAL; 2512 } 2513 2514 /* Store tx_rate for this vf. */ 2515 for (idx = 0; idx < nb_q_per_pool; idx++) { 2516 if (((uint64_t)0x1 << idx) & q_msk) { 2517 if (vfinfo[vf].tx_rate[idx] != tx_rate) 2518 vfinfo[vf].tx_rate[idx] = tx_rate; 2519 total_rate += tx_rate; 2520 } 2521 } 2522 2523 if (total_rate > dev->data->dev_link.link_speed) { 2524 /* Reset stored TX rate of the VF if it causes exceed 2525 * link speed. 2526 */ 2527 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate)); 2528 return -EINVAL; 2529 } 2530 2531 /* Set RTTBCNRC of each queue/pool for vf X */ 2532 for (; queue_idx <= queue_end; queue_idx++) { 2533 if (0x1 & q_msk) 2534 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate); 2535 q_msk = q_msk >> 1; 2536 } 2537 2538 return 0; 2539 } 2540 2541 static int 2542 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw) 2543 { 2544 struct ixgbe_adapter *adapter = dev->data->dev_private; 2545 int err; 2546 uint32_t mflcn; 2547 2548 err = ixgbe_fc_enable(hw); 2549 2550 /* Not negotiated is not an error case */ 2551 if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) { 2552 /* 2553 *check if we want to forward MAC frames - driver doesn't 2554 *have native capability to do that, 2555 *so we'll write the registers ourselves 2556 */ 2557 2558 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2559 2560 /* set or clear MFLCN.PMCF bit depending on configuration */ 2561 if (adapter->mac_ctrl_frame_fwd != 0) 2562 mflcn |= IXGBE_MFLCN_PMCF; 2563 else 2564 mflcn &= ~IXGBE_MFLCN_PMCF; 2565 2566 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn); 2567 IXGBE_WRITE_FLUSH(hw); 2568 2569 return 0; 2570 } 2571 return err; 2572 } 2573 2574 /* 2575 * Configure device link speed and setup link. 2576 * It returns 0 on success. 2577 */ 2578 static int 2579 ixgbe_dev_start(struct rte_eth_dev *dev) 2580 { 2581 struct ixgbe_hw *hw = 2582 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2583 struct ixgbe_vf_info *vfinfo = 2584 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2585 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2586 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2587 uint32_t intr_vector = 0; 2588 int err; 2589 bool link_up = false, negotiate = 0; 2590 uint32_t speed = 0; 2591 uint32_t allowed_speeds = 0; 2592 int mask = 0; 2593 int status; 2594 uint16_t vf, idx; 2595 uint32_t *link_speeds; 2596 struct ixgbe_tm_conf *tm_conf = 2597 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2598 struct ixgbe_macsec_setting *macsec_setting = 2599 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 2600 2601 PMD_INIT_FUNC_TRACE(); 2602 2603 /* Stop the link setup handler before resetting the HW. */ 2604 ixgbe_dev_cancel_link_thread(dev); 2605 2606 /* disable uio/vfio intr/eventfd mapping */ 2607 rte_intr_disable(intr_handle); 2608 2609 /* stop adapter */ 2610 hw->adapter_stopped = 0; 2611 ixgbe_stop_adapter(hw); 2612 2613 /* reinitialize adapter 2614 * this calls reset and start 2615 */ 2616 status = ixgbe_pf_reset_hw(hw); 2617 if (status != 0) 2618 return -1; 2619 hw->mac.ops.start_hw(hw); 2620 hw->mac.get_link_status = true; 2621 2622 /* configure PF module if SRIOV enabled */ 2623 ixgbe_pf_host_configure(dev); 2624 2625 ixgbe_dev_phy_intr_setup(dev); 2626 2627 /* check and configure queue intr-vector mapping */ 2628 if ((rte_intr_cap_multiple(intr_handle) || 2629 !RTE_ETH_DEV_SRIOV(dev).active) && 2630 dev->data->dev_conf.intr_conf.rxq != 0) { 2631 intr_vector = dev->data->nb_rx_queues; 2632 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) { 2633 PMD_INIT_LOG(ERR, "At most %d intr queues supported", 2634 IXGBE_MAX_INTR_QUEUE_NUM); 2635 return -ENOTSUP; 2636 } 2637 if (rte_intr_efd_enable(intr_handle, intr_vector)) 2638 return -1; 2639 } 2640 2641 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 2642 intr_handle->intr_vec = 2643 rte_zmalloc("intr_vec", 2644 dev->data->nb_rx_queues * sizeof(int), 0); 2645 if (intr_handle->intr_vec == NULL) { 2646 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 2647 " intr_vec", dev->data->nb_rx_queues); 2648 return -ENOMEM; 2649 } 2650 } 2651 2652 /* confiugre msix for sleep until rx interrupt */ 2653 ixgbe_configure_msix(dev); 2654 2655 /* initialize transmission unit */ 2656 ixgbe_dev_tx_init(dev); 2657 2658 /* This can fail when allocating mbufs for descriptor rings */ 2659 err = ixgbe_dev_rx_init(dev); 2660 if (err) { 2661 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 2662 goto error; 2663 } 2664 2665 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 2666 ETH_VLAN_EXTEND_MASK; 2667 err = ixgbe_vlan_offload_config(dev, mask); 2668 if (err) { 2669 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 2670 goto error; 2671 } 2672 2673 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) { 2674 /* Enable vlan filtering for VMDq */ 2675 ixgbe_vmdq_vlan_hw_filter_enable(dev); 2676 } 2677 2678 /* Configure DCB hw */ 2679 ixgbe_configure_dcb(dev); 2680 2681 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) { 2682 err = ixgbe_fdir_configure(dev); 2683 if (err) 2684 goto error; 2685 } 2686 2687 /* Restore vf rate limit */ 2688 if (vfinfo != NULL) { 2689 for (vf = 0; vf < pci_dev->max_vfs; vf++) 2690 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++) 2691 if (vfinfo[vf].tx_rate[idx] != 0) 2692 ixgbe_set_vf_rate_limit( 2693 dev, vf, 2694 vfinfo[vf].tx_rate[idx], 2695 1 << idx); 2696 } 2697 2698 ixgbe_restore_statistics_mapping(dev); 2699 2700 err = ixgbe_flow_ctrl_enable(dev, hw); 2701 if (err < 0) { 2702 PMD_INIT_LOG(ERR, "enable flow ctrl err"); 2703 goto error; 2704 } 2705 2706 err = ixgbe_dev_rxtx_start(dev); 2707 if (err < 0) { 2708 PMD_INIT_LOG(ERR, "Unable to start rxtx queues"); 2709 goto error; 2710 } 2711 2712 /* Skip link setup if loopback mode is enabled. */ 2713 if (dev->data->dev_conf.lpbk_mode != 0) { 2714 err = ixgbe_check_supported_loopback_mode(dev); 2715 if (err < 0) { 2716 PMD_INIT_LOG(ERR, "Unsupported loopback mode"); 2717 goto error; 2718 } else { 2719 goto skip_link_setup; 2720 } 2721 } 2722 2723 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) { 2724 err = hw->mac.ops.setup_sfp(hw); 2725 if (err) 2726 goto error; 2727 } 2728 2729 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2730 /* Turn on the copper */ 2731 ixgbe_set_phy_power(hw, true); 2732 } else { 2733 /* Turn on the laser */ 2734 ixgbe_enable_tx_laser(hw); 2735 } 2736 2737 err = ixgbe_check_link(hw, &speed, &link_up, 0); 2738 if (err) 2739 goto error; 2740 dev->data->dev_link.link_status = link_up; 2741 2742 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate); 2743 if (err) 2744 goto error; 2745 2746 switch (hw->mac.type) { 2747 case ixgbe_mac_X550: 2748 case ixgbe_mac_X550EM_x: 2749 case ixgbe_mac_X550EM_a: 2750 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2751 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G | 2752 ETH_LINK_SPEED_10G; 2753 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 2754 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 2755 allowed_speeds = ETH_LINK_SPEED_10M | 2756 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G; 2757 break; 2758 default: 2759 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2760 ETH_LINK_SPEED_10G; 2761 } 2762 2763 link_speeds = &dev->data->dev_conf.link_speeds; 2764 2765 /* Ignore autoneg flag bit and check the validity of 2766 * link_speed 2767 */ 2768 if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) { 2769 PMD_INIT_LOG(ERR, "Invalid link setting"); 2770 goto error; 2771 } 2772 2773 speed = 0x0; 2774 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) { 2775 switch (hw->mac.type) { 2776 case ixgbe_mac_82598EB: 2777 speed = IXGBE_LINK_SPEED_82598_AUTONEG; 2778 break; 2779 case ixgbe_mac_82599EB: 2780 case ixgbe_mac_X540: 2781 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2782 break; 2783 case ixgbe_mac_X550: 2784 case ixgbe_mac_X550EM_x: 2785 case ixgbe_mac_X550EM_a: 2786 speed = IXGBE_LINK_SPEED_X550_AUTONEG; 2787 break; 2788 default: 2789 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2790 } 2791 } else { 2792 if (*link_speeds & ETH_LINK_SPEED_10G) 2793 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2794 if (*link_speeds & ETH_LINK_SPEED_5G) 2795 speed |= IXGBE_LINK_SPEED_5GB_FULL; 2796 if (*link_speeds & ETH_LINK_SPEED_2_5G) 2797 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 2798 if (*link_speeds & ETH_LINK_SPEED_1G) 2799 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2800 if (*link_speeds & ETH_LINK_SPEED_100M) 2801 speed |= IXGBE_LINK_SPEED_100_FULL; 2802 if (*link_speeds & ETH_LINK_SPEED_10M) 2803 speed |= IXGBE_LINK_SPEED_10_FULL; 2804 } 2805 2806 err = ixgbe_setup_link(hw, speed, link_up); 2807 if (err) 2808 goto error; 2809 2810 skip_link_setup: 2811 2812 if (rte_intr_allow_others(intr_handle)) { 2813 /* check if lsc interrupt is enabled */ 2814 if (dev->data->dev_conf.intr_conf.lsc != 0) 2815 ixgbe_dev_lsc_interrupt_setup(dev, TRUE); 2816 else 2817 ixgbe_dev_lsc_interrupt_setup(dev, FALSE); 2818 ixgbe_dev_macsec_interrupt_setup(dev); 2819 } else { 2820 rte_intr_callback_unregister(intr_handle, 2821 ixgbe_dev_interrupt_handler, dev); 2822 if (dev->data->dev_conf.intr_conf.lsc != 0) 2823 PMD_INIT_LOG(INFO, "lsc won't enable because of" 2824 " no intr multiplex"); 2825 } 2826 2827 /* check if rxq interrupt is enabled */ 2828 if (dev->data->dev_conf.intr_conf.rxq != 0 && 2829 rte_intr_dp_is_en(intr_handle)) 2830 ixgbe_dev_rxq_interrupt_setup(dev); 2831 2832 /* enable uio/vfio intr/eventfd mapping */ 2833 rte_intr_enable(intr_handle); 2834 2835 /* resume enabled intr since hw reset */ 2836 ixgbe_enable_intr(dev); 2837 ixgbe_l2_tunnel_conf(dev); 2838 ixgbe_filter_restore(dev); 2839 2840 if (tm_conf->root && !tm_conf->committed) 2841 PMD_DRV_LOG(WARNING, 2842 "please call hierarchy_commit() " 2843 "before starting the port"); 2844 2845 /* wait for the controller to acquire link */ 2846 err = ixgbe_wait_for_link_up(hw); 2847 if (err) 2848 goto error; 2849 2850 /* 2851 * Update link status right before return, because it may 2852 * start link configuration process in a separate thread. 2853 */ 2854 ixgbe_dev_link_update(dev, 0); 2855 2856 /* setup the macsec setting register */ 2857 if (macsec_setting->offload_en) 2858 ixgbe_dev_macsec_register_enable(dev, macsec_setting); 2859 2860 return 0; 2861 2862 error: 2863 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err); 2864 ixgbe_dev_clear_queues(dev); 2865 return -EIO; 2866 } 2867 2868 /* 2869 * Stop device: disable rx and tx functions to allow for reconfiguring. 2870 */ 2871 static void 2872 ixgbe_dev_stop(struct rte_eth_dev *dev) 2873 { 2874 struct rte_eth_link link; 2875 struct ixgbe_adapter *adapter = dev->data->dev_private; 2876 struct ixgbe_hw *hw = 2877 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2878 struct ixgbe_vf_info *vfinfo = 2879 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2880 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2881 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2882 int vf; 2883 struct ixgbe_tm_conf *tm_conf = 2884 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2885 2886 if (hw->adapter_stopped) 2887 return; 2888 2889 PMD_INIT_FUNC_TRACE(); 2890 2891 ixgbe_dev_cancel_link_thread(dev); 2892 2893 /* disable interrupts */ 2894 ixgbe_disable_intr(hw); 2895 2896 /* reset the NIC */ 2897 ixgbe_pf_reset_hw(hw); 2898 hw->adapter_stopped = 0; 2899 2900 /* stop adapter */ 2901 ixgbe_stop_adapter(hw); 2902 2903 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++) 2904 vfinfo[vf].clear_to_send = false; 2905 2906 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2907 /* Turn off the copper */ 2908 ixgbe_set_phy_power(hw, false); 2909 } else { 2910 /* Turn off the laser */ 2911 ixgbe_disable_tx_laser(hw); 2912 } 2913 2914 ixgbe_dev_clear_queues(dev); 2915 2916 /* Clear stored conf */ 2917 dev->data->scattered_rx = 0; 2918 dev->data->lro = 0; 2919 2920 /* Clear recorded link status */ 2921 memset(&link, 0, sizeof(link)); 2922 rte_eth_linkstatus_set(dev, &link); 2923 2924 if (!rte_intr_allow_others(intr_handle)) 2925 /* resume to the default handler */ 2926 rte_intr_callback_register(intr_handle, 2927 ixgbe_dev_interrupt_handler, 2928 (void *)dev); 2929 2930 /* Clean datapath event and queue/vec mapping */ 2931 rte_intr_efd_disable(intr_handle); 2932 if (intr_handle->intr_vec != NULL) { 2933 rte_free(intr_handle->intr_vec); 2934 intr_handle->intr_vec = NULL; 2935 } 2936 2937 /* reset hierarchy commit */ 2938 tm_conf->committed = false; 2939 2940 adapter->rss_reta_updated = 0; 2941 2942 adapter->mac_ctrl_frame_fwd = 0; 2943 2944 hw->adapter_stopped = true; 2945 } 2946 2947 /* 2948 * Set device link up: enable tx. 2949 */ 2950 static int 2951 ixgbe_dev_set_link_up(struct rte_eth_dev *dev) 2952 { 2953 struct ixgbe_hw *hw = 2954 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2955 if (hw->mac.type == ixgbe_mac_82599EB) { 2956 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2957 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2958 /* Not suported in bypass mode */ 2959 PMD_INIT_LOG(ERR, "Set link up is not supported " 2960 "by device id 0x%x", hw->device_id); 2961 return -ENOTSUP; 2962 } 2963 #endif 2964 } 2965 2966 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2967 /* Turn on the copper */ 2968 ixgbe_set_phy_power(hw, true); 2969 } else { 2970 /* Turn on the laser */ 2971 ixgbe_enable_tx_laser(hw); 2972 ixgbe_dev_link_update(dev, 0); 2973 } 2974 2975 return 0; 2976 } 2977 2978 /* 2979 * Set device link down: disable tx. 2980 */ 2981 static int 2982 ixgbe_dev_set_link_down(struct rte_eth_dev *dev) 2983 { 2984 struct ixgbe_hw *hw = 2985 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2986 if (hw->mac.type == ixgbe_mac_82599EB) { 2987 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2988 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2989 /* Not suported in bypass mode */ 2990 PMD_INIT_LOG(ERR, "Set link down is not supported " 2991 "by device id 0x%x", hw->device_id); 2992 return -ENOTSUP; 2993 } 2994 #endif 2995 } 2996 2997 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2998 /* Turn off the copper */ 2999 ixgbe_set_phy_power(hw, false); 3000 } else { 3001 /* Turn off the laser */ 3002 ixgbe_disable_tx_laser(hw); 3003 ixgbe_dev_link_update(dev, 0); 3004 } 3005 3006 return 0; 3007 } 3008 3009 /* 3010 * Reset and stop device. 3011 */ 3012 static void 3013 ixgbe_dev_close(struct rte_eth_dev *dev) 3014 { 3015 struct ixgbe_hw *hw = 3016 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3017 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3018 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3019 int retries = 0; 3020 int ret; 3021 3022 PMD_INIT_FUNC_TRACE(); 3023 3024 ixgbe_pf_reset_hw(hw); 3025 3026 ixgbe_dev_stop(dev); 3027 3028 ixgbe_dev_free_queues(dev); 3029 3030 ixgbe_disable_pcie_master(hw); 3031 3032 /* reprogram the RAR[0] in case user changed it. */ 3033 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 3034 3035 dev->dev_ops = NULL; 3036 dev->rx_pkt_burst = NULL; 3037 dev->tx_pkt_burst = NULL; 3038 3039 /* Unlock any pending hardware semaphore */ 3040 ixgbe_swfw_lock_reset(hw); 3041 3042 /* disable uio intr before callback unregister */ 3043 rte_intr_disable(intr_handle); 3044 3045 do { 3046 ret = rte_intr_callback_unregister(intr_handle, 3047 ixgbe_dev_interrupt_handler, dev); 3048 if (ret >= 0 || ret == -ENOENT) { 3049 break; 3050 } else if (ret != -EAGAIN) { 3051 PMD_INIT_LOG(ERR, 3052 "intr callback unregister failed: %d", 3053 ret); 3054 } 3055 rte_delay_ms(100); 3056 } while (retries++ < (10 + IXGBE_LINK_UP_TIME)); 3057 3058 /* cancel the delay handler before remove dev */ 3059 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev); 3060 3061 /* uninitialize PF if max_vfs not zero */ 3062 ixgbe_pf_host_uninit(dev); 3063 3064 /* remove all the fdir filters & hash */ 3065 ixgbe_fdir_filter_uninit(dev); 3066 3067 /* remove all the L2 tunnel filters & hash */ 3068 ixgbe_l2_tn_filter_uninit(dev); 3069 3070 /* Remove all ntuple filters of the device */ 3071 ixgbe_ntuple_filter_uninit(dev); 3072 3073 /* clear all the filters list */ 3074 ixgbe_filterlist_flush(); 3075 3076 /* Remove all Traffic Manager configuration */ 3077 ixgbe_tm_conf_uninit(dev); 3078 3079 #ifdef RTE_LIBRTE_SECURITY 3080 rte_free(dev->security_ctx); 3081 #endif 3082 3083 } 3084 3085 /* 3086 * Reset PF device. 3087 */ 3088 static int 3089 ixgbe_dev_reset(struct rte_eth_dev *dev) 3090 { 3091 int ret; 3092 3093 /* When a DPDK PMD PF begin to reset PF port, it should notify all 3094 * its VF to make them align with it. The detailed notification 3095 * mechanism is PMD specific. As to ixgbe PF, it is rather complex. 3096 * To avoid unexpected behavior in VF, currently reset of PF with 3097 * SR-IOV activation is not supported. It might be supported later. 3098 */ 3099 if (dev->data->sriov.active) 3100 return -ENOTSUP; 3101 3102 ret = eth_ixgbe_dev_uninit(dev); 3103 if (ret) 3104 return ret; 3105 3106 ret = eth_ixgbe_dev_init(dev, NULL); 3107 3108 return ret; 3109 } 3110 3111 static void 3112 ixgbe_read_stats_registers(struct ixgbe_hw *hw, 3113 struct ixgbe_hw_stats *hw_stats, 3114 struct ixgbe_macsec_stats *macsec_stats, 3115 uint64_t *total_missed_rx, uint64_t *total_qbrc, 3116 uint64_t *total_qprc, uint64_t *total_qprdc) 3117 { 3118 uint32_t bprc, lxon, lxoff, total; 3119 uint32_t delta_gprc = 0; 3120 unsigned i; 3121 /* Workaround for RX byte count not including CRC bytes when CRC 3122 * strip is enabled. CRC bytes are removed from counters when crc_strip 3123 * is disabled. 3124 */ 3125 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) & 3126 IXGBE_HLREG0_RXCRCSTRP); 3127 3128 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 3129 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC); 3130 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC); 3131 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC); 3132 3133 for (i = 0; i < 8; i++) { 3134 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 3135 3136 /* global total per queue */ 3137 hw_stats->mpc[i] += mp; 3138 /* Running comprehensive total for stats display */ 3139 *total_missed_rx += hw_stats->mpc[i]; 3140 if (hw->mac.type == ixgbe_mac_82598EB) { 3141 hw_stats->rnbc[i] += 3142 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 3143 hw_stats->pxonrxc[i] += 3144 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 3145 hw_stats->pxoffrxc[i] += 3146 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 3147 } else { 3148 hw_stats->pxonrxc[i] += 3149 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 3150 hw_stats->pxoffrxc[i] += 3151 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 3152 hw_stats->pxon2offc[i] += 3153 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 3154 } 3155 hw_stats->pxontxc[i] += 3156 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 3157 hw_stats->pxofftxc[i] += 3158 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 3159 } 3160 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3161 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 3162 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 3163 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 3164 3165 delta_gprc += delta_qprc; 3166 3167 hw_stats->qprc[i] += delta_qprc; 3168 hw_stats->qptc[i] += delta_qptc; 3169 3170 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 3171 hw_stats->qbrc[i] += 3172 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32); 3173 if (crc_strip == 0) 3174 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN; 3175 3176 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 3177 hw_stats->qbtc[i] += 3178 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32); 3179 3180 hw_stats->qprdc[i] += delta_qprdc; 3181 *total_qprdc += hw_stats->qprdc[i]; 3182 3183 *total_qprc += hw_stats->qprc[i]; 3184 *total_qbrc += hw_stats->qbrc[i]; 3185 } 3186 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC); 3187 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC); 3188 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 3189 3190 /* 3191 * An errata states that gprc actually counts good + missed packets: 3192 * Workaround to set gprc to summated queue packet receives 3193 */ 3194 hw_stats->gprc = *total_qprc; 3195 3196 if (hw->mac.type != ixgbe_mac_82598EB) { 3197 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 3198 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32); 3199 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 3200 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32); 3201 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 3202 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32); 3203 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 3204 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 3205 } else { 3206 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 3207 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 3208 /* 82598 only has a counter in the high register */ 3209 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 3210 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 3211 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 3212 } 3213 uint64_t old_tpr = hw_stats->tpr; 3214 3215 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 3216 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT); 3217 3218 if (crc_strip == 0) 3219 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN; 3220 3221 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC); 3222 hw_stats->gptc += delta_gptc; 3223 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN; 3224 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN; 3225 3226 /* 3227 * Workaround: mprc hardware is incorrectly counting 3228 * broadcasts, so for now we subtract those. 3229 */ 3230 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 3231 hw_stats->bprc += bprc; 3232 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 3233 if (hw->mac.type == ixgbe_mac_82598EB) 3234 hw_stats->mprc -= bprc; 3235 3236 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 3237 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 3238 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 3239 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 3240 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 3241 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 3242 3243 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 3244 hw_stats->lxontxc += lxon; 3245 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 3246 hw_stats->lxofftxc += lxoff; 3247 total = lxon + lxoff; 3248 3249 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 3250 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 3251 hw_stats->gptc -= total; 3252 hw_stats->mptc -= total; 3253 hw_stats->ptc64 -= total; 3254 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN; 3255 3256 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 3257 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 3258 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 3259 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 3260 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC); 3261 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC); 3262 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC); 3263 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 3264 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 3265 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 3266 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 3267 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 3268 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 3269 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC); 3270 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 3271 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST); 3272 /* Only read FCOE on 82599 */ 3273 if (hw->mac.type != ixgbe_mac_82598EB) { 3274 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 3275 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 3276 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 3277 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 3278 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 3279 } 3280 3281 /* Flow Director Stats registers */ 3282 if (hw->mac.type != ixgbe_mac_82598EB) { 3283 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 3284 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 3285 hw_stats->fdirustat_add += IXGBE_READ_REG(hw, 3286 IXGBE_FDIRUSTAT) & 0xFFFF; 3287 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw, 3288 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF; 3289 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw, 3290 IXGBE_FDIRFSTAT) & 0xFFFF; 3291 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw, 3292 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF; 3293 } 3294 /* MACsec Stats registers */ 3295 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT); 3296 macsec_stats->out_pkts_encrypted += 3297 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE); 3298 macsec_stats->out_pkts_protected += 3299 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP); 3300 macsec_stats->out_octets_encrypted += 3301 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE); 3302 macsec_stats->out_octets_protected += 3303 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP); 3304 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT); 3305 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD); 3306 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI); 3307 macsec_stats->in_pkts_unknownsci += 3308 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI); 3309 macsec_stats->in_octets_decrypted += 3310 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD); 3311 macsec_stats->in_octets_validated += 3312 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV); 3313 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH); 3314 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY); 3315 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE); 3316 for (i = 0; i < 2; i++) { 3317 macsec_stats->in_pkts_ok += 3318 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i)); 3319 macsec_stats->in_pkts_invalid += 3320 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i)); 3321 macsec_stats->in_pkts_notvalid += 3322 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i)); 3323 } 3324 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA); 3325 macsec_stats->in_pkts_notusingsa += 3326 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA); 3327 } 3328 3329 /* 3330 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c 3331 */ 3332 static int 3333 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3334 { 3335 struct ixgbe_hw *hw = 3336 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3337 struct ixgbe_hw_stats *hw_stats = 3338 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3339 struct ixgbe_macsec_stats *macsec_stats = 3340 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3341 dev->data->dev_private); 3342 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3343 unsigned i; 3344 3345 total_missed_rx = 0; 3346 total_qbrc = 0; 3347 total_qprc = 0; 3348 total_qprdc = 0; 3349 3350 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3351 &total_qbrc, &total_qprc, &total_qprdc); 3352 3353 if (stats == NULL) 3354 return -EINVAL; 3355 3356 /* Fill out the rte_eth_stats statistics structure */ 3357 stats->ipackets = total_qprc; 3358 stats->ibytes = total_qbrc; 3359 stats->opackets = hw_stats->gptc; 3360 stats->obytes = hw_stats->gotc; 3361 3362 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3363 stats->q_ipackets[i] = hw_stats->qprc[i]; 3364 stats->q_opackets[i] = hw_stats->qptc[i]; 3365 stats->q_ibytes[i] = hw_stats->qbrc[i]; 3366 stats->q_obytes[i] = hw_stats->qbtc[i]; 3367 stats->q_errors[i] = hw_stats->qprdc[i]; 3368 } 3369 3370 /* Rx Errors */ 3371 stats->imissed = total_missed_rx; 3372 stats->ierrors = hw_stats->crcerrs + 3373 hw_stats->mspdc + 3374 hw_stats->rlec + 3375 hw_stats->ruc + 3376 hw_stats->roc + 3377 hw_stats->illerrc + 3378 hw_stats->errbc + 3379 hw_stats->rfc + 3380 hw_stats->fccrc + 3381 hw_stats->fclast; 3382 3383 /* Tx Errors */ 3384 stats->oerrors = 0; 3385 return 0; 3386 } 3387 3388 static int 3389 ixgbe_dev_stats_reset(struct rte_eth_dev *dev) 3390 { 3391 struct ixgbe_hw_stats *stats = 3392 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3393 3394 /* HW registers are cleared on read */ 3395 ixgbe_dev_stats_get(dev, NULL); 3396 3397 /* Reset software totals */ 3398 memset(stats, 0, sizeof(*stats)); 3399 3400 return 0; 3401 } 3402 3403 /* This function calculates the number of xstats based on the current config */ 3404 static unsigned 3405 ixgbe_xstats_calc_num(void) { 3406 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS + 3407 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) + 3408 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES); 3409 } 3410 3411 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3412 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size) 3413 { 3414 const unsigned cnt_stats = ixgbe_xstats_calc_num(); 3415 unsigned stat, i, count; 3416 3417 if (xstats_names != NULL) { 3418 count = 0; 3419 3420 /* Note: limit >= cnt_stats checked upstream 3421 * in rte_eth_xstats_names() 3422 */ 3423 3424 /* Extended stats from ixgbe_hw_stats */ 3425 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3426 strlcpy(xstats_names[count].name, 3427 rte_ixgbe_stats_strings[i].name, 3428 sizeof(xstats_names[count].name)); 3429 count++; 3430 } 3431 3432 /* MACsec Stats */ 3433 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3434 strlcpy(xstats_names[count].name, 3435 rte_ixgbe_macsec_strings[i].name, 3436 sizeof(xstats_names[count].name)); 3437 count++; 3438 } 3439 3440 /* RX Priority Stats */ 3441 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3442 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3443 snprintf(xstats_names[count].name, 3444 sizeof(xstats_names[count].name), 3445 "rx_priority%u_%s", i, 3446 rte_ixgbe_rxq_strings[stat].name); 3447 count++; 3448 } 3449 } 3450 3451 /* TX Priority Stats */ 3452 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3453 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3454 snprintf(xstats_names[count].name, 3455 sizeof(xstats_names[count].name), 3456 "tx_priority%u_%s", i, 3457 rte_ixgbe_txq_strings[stat].name); 3458 count++; 3459 } 3460 } 3461 } 3462 return cnt_stats; 3463 } 3464 3465 static int ixgbe_dev_xstats_get_names_by_id( 3466 struct rte_eth_dev *dev, 3467 struct rte_eth_xstat_name *xstats_names, 3468 const uint64_t *ids, 3469 unsigned int limit) 3470 { 3471 if (!ids) { 3472 const unsigned int cnt_stats = ixgbe_xstats_calc_num(); 3473 unsigned int stat, i, count; 3474 3475 if (xstats_names != NULL) { 3476 count = 0; 3477 3478 /* Note: limit >= cnt_stats checked upstream 3479 * in rte_eth_xstats_names() 3480 */ 3481 3482 /* Extended stats from ixgbe_hw_stats */ 3483 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3484 strlcpy(xstats_names[count].name, 3485 rte_ixgbe_stats_strings[i].name, 3486 sizeof(xstats_names[count].name)); 3487 count++; 3488 } 3489 3490 /* MACsec Stats */ 3491 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3492 strlcpy(xstats_names[count].name, 3493 rte_ixgbe_macsec_strings[i].name, 3494 sizeof(xstats_names[count].name)); 3495 count++; 3496 } 3497 3498 /* RX Priority Stats */ 3499 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3500 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3501 snprintf(xstats_names[count].name, 3502 sizeof(xstats_names[count].name), 3503 "rx_priority%u_%s", i, 3504 rte_ixgbe_rxq_strings[stat].name); 3505 count++; 3506 } 3507 } 3508 3509 /* TX Priority Stats */ 3510 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3511 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3512 snprintf(xstats_names[count].name, 3513 sizeof(xstats_names[count].name), 3514 "tx_priority%u_%s", i, 3515 rte_ixgbe_txq_strings[stat].name); 3516 count++; 3517 } 3518 } 3519 } 3520 return cnt_stats; 3521 } 3522 3523 uint16_t i; 3524 uint16_t size = ixgbe_xstats_calc_num(); 3525 struct rte_eth_xstat_name xstats_names_copy[size]; 3526 3527 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL, 3528 size); 3529 3530 for (i = 0; i < limit; i++) { 3531 if (ids[i] >= size) { 3532 PMD_INIT_LOG(ERR, "id value isn't valid"); 3533 return -1; 3534 } 3535 strcpy(xstats_names[i].name, 3536 xstats_names_copy[ids[i]].name); 3537 } 3538 return limit; 3539 } 3540 3541 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3542 struct rte_eth_xstat_name *xstats_names, unsigned limit) 3543 { 3544 unsigned i; 3545 3546 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL) 3547 return -ENOMEM; 3548 3549 if (xstats_names != NULL) 3550 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) 3551 strlcpy(xstats_names[i].name, 3552 rte_ixgbevf_stats_strings[i].name, 3553 sizeof(xstats_names[i].name)); 3554 return IXGBEVF_NB_XSTATS; 3555 } 3556 3557 static int 3558 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3559 unsigned n) 3560 { 3561 struct ixgbe_hw *hw = 3562 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3563 struct ixgbe_hw_stats *hw_stats = 3564 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3565 struct ixgbe_macsec_stats *macsec_stats = 3566 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3567 dev->data->dev_private); 3568 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3569 unsigned i, stat, count = 0; 3570 3571 count = ixgbe_xstats_calc_num(); 3572 3573 if (n < count) 3574 return count; 3575 3576 total_missed_rx = 0; 3577 total_qbrc = 0; 3578 total_qprc = 0; 3579 total_qprdc = 0; 3580 3581 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3582 &total_qbrc, &total_qprc, &total_qprdc); 3583 3584 /* If this is a reset xstats is NULL, and we have cleared the 3585 * registers by reading them. 3586 */ 3587 if (!xstats) 3588 return 0; 3589 3590 /* Extended stats from ixgbe_hw_stats */ 3591 count = 0; 3592 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3593 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3594 rte_ixgbe_stats_strings[i].offset); 3595 xstats[count].id = count; 3596 count++; 3597 } 3598 3599 /* MACsec Stats */ 3600 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3601 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) + 3602 rte_ixgbe_macsec_strings[i].offset); 3603 xstats[count].id = count; 3604 count++; 3605 } 3606 3607 /* RX Priority Stats */ 3608 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3609 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3610 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3611 rte_ixgbe_rxq_strings[stat].offset + 3612 (sizeof(uint64_t) * i)); 3613 xstats[count].id = count; 3614 count++; 3615 } 3616 } 3617 3618 /* TX Priority Stats */ 3619 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3620 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3621 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3622 rte_ixgbe_txq_strings[stat].offset + 3623 (sizeof(uint64_t) * i)); 3624 xstats[count].id = count; 3625 count++; 3626 } 3627 } 3628 return count; 3629 } 3630 3631 static int 3632 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 3633 uint64_t *values, unsigned int n) 3634 { 3635 if (!ids) { 3636 struct ixgbe_hw *hw = 3637 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3638 struct ixgbe_hw_stats *hw_stats = 3639 IXGBE_DEV_PRIVATE_TO_STATS( 3640 dev->data->dev_private); 3641 struct ixgbe_macsec_stats *macsec_stats = 3642 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3643 dev->data->dev_private); 3644 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3645 unsigned int i, stat, count = 0; 3646 3647 count = ixgbe_xstats_calc_num(); 3648 3649 if (!ids && n < count) 3650 return count; 3651 3652 total_missed_rx = 0; 3653 total_qbrc = 0; 3654 total_qprc = 0; 3655 total_qprdc = 0; 3656 3657 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, 3658 &total_missed_rx, &total_qbrc, &total_qprc, 3659 &total_qprdc); 3660 3661 /* If this is a reset xstats is NULL, and we have cleared the 3662 * registers by reading them. 3663 */ 3664 if (!ids && !values) 3665 return 0; 3666 3667 /* Extended stats from ixgbe_hw_stats */ 3668 count = 0; 3669 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3670 values[count] = *(uint64_t *)(((char *)hw_stats) + 3671 rte_ixgbe_stats_strings[i].offset); 3672 count++; 3673 } 3674 3675 /* MACsec Stats */ 3676 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3677 values[count] = *(uint64_t *)(((char *)macsec_stats) + 3678 rte_ixgbe_macsec_strings[i].offset); 3679 count++; 3680 } 3681 3682 /* RX Priority Stats */ 3683 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3684 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3685 values[count] = 3686 *(uint64_t *)(((char *)hw_stats) + 3687 rte_ixgbe_rxq_strings[stat].offset + 3688 (sizeof(uint64_t) * i)); 3689 count++; 3690 } 3691 } 3692 3693 /* TX Priority Stats */ 3694 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3695 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3696 values[count] = 3697 *(uint64_t *)(((char *)hw_stats) + 3698 rte_ixgbe_txq_strings[stat].offset + 3699 (sizeof(uint64_t) * i)); 3700 count++; 3701 } 3702 } 3703 return count; 3704 } 3705 3706 uint16_t i; 3707 uint16_t size = ixgbe_xstats_calc_num(); 3708 uint64_t values_copy[size]; 3709 3710 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size); 3711 3712 for (i = 0; i < n; i++) { 3713 if (ids[i] >= size) { 3714 PMD_INIT_LOG(ERR, "id value isn't valid"); 3715 return -1; 3716 } 3717 values[i] = values_copy[ids[i]]; 3718 } 3719 return n; 3720 } 3721 3722 static int 3723 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev) 3724 { 3725 struct ixgbe_hw_stats *stats = 3726 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3727 struct ixgbe_macsec_stats *macsec_stats = 3728 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3729 dev->data->dev_private); 3730 3731 unsigned count = ixgbe_xstats_calc_num(); 3732 3733 /* HW registers are cleared on read */ 3734 ixgbe_dev_xstats_get(dev, NULL, count); 3735 3736 /* Reset software totals */ 3737 memset(stats, 0, sizeof(*stats)); 3738 memset(macsec_stats, 0, sizeof(*macsec_stats)); 3739 3740 return 0; 3741 } 3742 3743 static void 3744 ixgbevf_update_stats(struct rte_eth_dev *dev) 3745 { 3746 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3747 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3748 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3749 3750 /* Good Rx packet, include VF loopback */ 3751 UPDATE_VF_STAT(IXGBE_VFGPRC, 3752 hw_stats->last_vfgprc, hw_stats->vfgprc); 3753 3754 /* Good Rx octets, include VF loopback */ 3755 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB, 3756 hw_stats->last_vfgorc, hw_stats->vfgorc); 3757 3758 /* Good Tx packet, include VF loopback */ 3759 UPDATE_VF_STAT(IXGBE_VFGPTC, 3760 hw_stats->last_vfgptc, hw_stats->vfgptc); 3761 3762 /* Good Tx octets, include VF loopback */ 3763 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB, 3764 hw_stats->last_vfgotc, hw_stats->vfgotc); 3765 3766 /* Rx Multicst Packet */ 3767 UPDATE_VF_STAT(IXGBE_VFMPRC, 3768 hw_stats->last_vfmprc, hw_stats->vfmprc); 3769 } 3770 3771 static int 3772 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3773 unsigned n) 3774 { 3775 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3776 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3777 unsigned i; 3778 3779 if (n < IXGBEVF_NB_XSTATS) 3780 return IXGBEVF_NB_XSTATS; 3781 3782 ixgbevf_update_stats(dev); 3783 3784 if (!xstats) 3785 return 0; 3786 3787 /* Extended stats */ 3788 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) { 3789 xstats[i].id = i; 3790 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + 3791 rte_ixgbevf_stats_strings[i].offset); 3792 } 3793 3794 return IXGBEVF_NB_XSTATS; 3795 } 3796 3797 static int 3798 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3799 { 3800 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3801 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3802 3803 ixgbevf_update_stats(dev); 3804 3805 if (stats == NULL) 3806 return -EINVAL; 3807 3808 stats->ipackets = hw_stats->vfgprc; 3809 stats->ibytes = hw_stats->vfgorc; 3810 stats->opackets = hw_stats->vfgptc; 3811 stats->obytes = hw_stats->vfgotc; 3812 return 0; 3813 } 3814 3815 static int 3816 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev) 3817 { 3818 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3819 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3820 3821 /* Sync HW register to the last stats */ 3822 ixgbevf_dev_stats_get(dev, NULL); 3823 3824 /* reset HW current stats*/ 3825 hw_stats->vfgprc = 0; 3826 hw_stats->vfgorc = 0; 3827 hw_stats->vfgptc = 0; 3828 hw_stats->vfgotc = 0; 3829 3830 return 0; 3831 } 3832 3833 static int 3834 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 3835 { 3836 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3837 u16 eeprom_verh, eeprom_verl; 3838 u32 etrack_id; 3839 int ret; 3840 3841 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh); 3842 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl); 3843 3844 etrack_id = (eeprom_verh << 16) | eeprom_verl; 3845 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id); 3846 3847 ret += 1; /* add the size of '\0' */ 3848 if (fw_size < (u32)ret) 3849 return ret; 3850 else 3851 return 0; 3852 } 3853 3854 static int 3855 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3856 { 3857 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3858 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3859 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 3860 3861 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3862 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3863 if (RTE_ETH_DEV_SRIOV(dev).active == 0) { 3864 /* 3865 * When DCB/VT is off, maximum number of queues changes, 3866 * except for 82598EB, which remains constant. 3867 */ 3868 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 3869 hw->mac.type != ixgbe_mac_82598EB) 3870 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES; 3871 } 3872 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */ 3873 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */ 3874 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3875 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3876 dev_info->max_vfs = pci_dev->max_vfs; 3877 if (hw->mac.type == ixgbe_mac_82598EB) 3878 dev_info->max_vmdq_pools = ETH_16_POOLS; 3879 else 3880 dev_info->max_vmdq_pools = ETH_64_POOLS; 3881 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD; 3882 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 3883 dev_info->vmdq_queue_num = dev_info->max_rx_queues; 3884 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3885 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3886 dev_info->rx_queue_offload_capa); 3887 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3888 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3889 3890 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3891 .rx_thresh = { 3892 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3893 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3894 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3895 }, 3896 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3897 .rx_drop_en = 0, 3898 .offloads = 0, 3899 }; 3900 3901 dev_info->default_txconf = (struct rte_eth_txconf) { 3902 .tx_thresh = { 3903 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3904 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3905 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3906 }, 3907 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3908 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3909 .offloads = 0, 3910 }; 3911 3912 dev_info->rx_desc_lim = rx_desc_lim; 3913 dev_info->tx_desc_lim = tx_desc_lim; 3914 3915 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 3916 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 3917 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 3918 3919 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 3920 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 3921 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 3922 dev_info->speed_capa = ETH_LINK_SPEED_10M | 3923 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G; 3924 3925 if (hw->mac.type == ixgbe_mac_X540 || 3926 hw->mac.type == ixgbe_mac_X540_vf || 3927 hw->mac.type == ixgbe_mac_X550 || 3928 hw->mac.type == ixgbe_mac_X550_vf) { 3929 dev_info->speed_capa |= ETH_LINK_SPEED_100M; 3930 } 3931 if (hw->mac.type == ixgbe_mac_X550) { 3932 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G; 3933 dev_info->speed_capa |= ETH_LINK_SPEED_5G; 3934 } 3935 3936 /* Driver-preferred Rx/Tx parameters */ 3937 dev_info->default_rxportconf.burst_size = 32; 3938 dev_info->default_txportconf.burst_size = 32; 3939 dev_info->default_rxportconf.nb_queues = 1; 3940 dev_info->default_txportconf.nb_queues = 1; 3941 dev_info->default_rxportconf.ring_size = 256; 3942 dev_info->default_txportconf.ring_size = 256; 3943 3944 return 0; 3945 } 3946 3947 static const uint32_t * 3948 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 3949 { 3950 static const uint32_t ptypes[] = { 3951 /* For non-vec functions, 3952 * refers to ixgbe_rxd_pkt_info_to_pkt_type(); 3953 * for vec functions, 3954 * refers to _recv_raw_pkts_vec(). 3955 */ 3956 RTE_PTYPE_L2_ETHER, 3957 RTE_PTYPE_L3_IPV4, 3958 RTE_PTYPE_L3_IPV4_EXT, 3959 RTE_PTYPE_L3_IPV6, 3960 RTE_PTYPE_L3_IPV6_EXT, 3961 RTE_PTYPE_L4_SCTP, 3962 RTE_PTYPE_L4_TCP, 3963 RTE_PTYPE_L4_UDP, 3964 RTE_PTYPE_TUNNEL_IP, 3965 RTE_PTYPE_INNER_L3_IPV6, 3966 RTE_PTYPE_INNER_L3_IPV6_EXT, 3967 RTE_PTYPE_INNER_L4_TCP, 3968 RTE_PTYPE_INNER_L4_UDP, 3969 RTE_PTYPE_UNKNOWN 3970 }; 3971 3972 if (dev->rx_pkt_burst == ixgbe_recv_pkts || 3973 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc || 3974 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc || 3975 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc) 3976 return ptypes; 3977 3978 #if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_NEON) 3979 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec || 3980 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec) 3981 return ptypes; 3982 #endif 3983 return NULL; 3984 } 3985 3986 static int 3987 ixgbevf_dev_info_get(struct rte_eth_dev *dev, 3988 struct rte_eth_dev_info *dev_info) 3989 { 3990 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3991 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3992 3993 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3994 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3995 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */ 3996 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */ 3997 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD; 3998 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3999 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 4000 dev_info->max_vfs = pci_dev->max_vfs; 4001 if (hw->mac.type == ixgbe_mac_82598EB) 4002 dev_info->max_vmdq_pools = ETH_16_POOLS; 4003 else 4004 dev_info->max_vmdq_pools = ETH_64_POOLS; 4005 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 4006 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 4007 dev_info->rx_queue_offload_capa); 4008 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 4009 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 4010 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 4011 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 4012 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 4013 4014 dev_info->default_rxconf = (struct rte_eth_rxconf) { 4015 .rx_thresh = { 4016 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 4017 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 4018 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 4019 }, 4020 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 4021 .rx_drop_en = 0, 4022 .offloads = 0, 4023 }; 4024 4025 dev_info->default_txconf = (struct rte_eth_txconf) { 4026 .tx_thresh = { 4027 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 4028 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 4029 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 4030 }, 4031 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 4032 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 4033 .offloads = 0, 4034 }; 4035 4036 dev_info->rx_desc_lim = rx_desc_lim; 4037 dev_info->tx_desc_lim = tx_desc_lim; 4038 4039 return 0; 4040 } 4041 4042 static int 4043 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4044 bool *link_up, int wait_to_complete) 4045 { 4046 struct ixgbe_adapter *adapter = container_of(hw, 4047 struct ixgbe_adapter, hw); 4048 struct ixgbe_mbx_info *mbx = &hw->mbx; 4049 struct ixgbe_mac_info *mac = &hw->mac; 4050 uint32_t links_reg, in_msg; 4051 int ret_val = 0; 4052 4053 /* If we were hit with a reset drop the link */ 4054 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout) 4055 mac->get_link_status = true; 4056 4057 if (!mac->get_link_status) 4058 goto out; 4059 4060 /* if link status is down no point in checking to see if pf is up */ 4061 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 4062 if (!(links_reg & IXGBE_LINKS_UP)) 4063 goto out; 4064 4065 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs 4066 * before the link status is correct 4067 */ 4068 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) { 4069 int i; 4070 4071 for (i = 0; i < 5; i++) { 4072 rte_delay_us(100); 4073 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 4074 4075 if (!(links_reg & IXGBE_LINKS_UP)) 4076 goto out; 4077 } 4078 } 4079 4080 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 4081 case IXGBE_LINKS_SPEED_10G_82599: 4082 *speed = IXGBE_LINK_SPEED_10GB_FULL; 4083 if (hw->mac.type >= ixgbe_mac_X550) { 4084 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4085 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4086 } 4087 break; 4088 case IXGBE_LINKS_SPEED_1G_82599: 4089 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4090 break; 4091 case IXGBE_LINKS_SPEED_100_82599: 4092 *speed = IXGBE_LINK_SPEED_100_FULL; 4093 if (hw->mac.type == ixgbe_mac_X550) { 4094 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4095 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4096 } 4097 break; 4098 case IXGBE_LINKS_SPEED_10_X550EM_A: 4099 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4100 /* Since Reserved in older MAC's */ 4101 if (hw->mac.type >= ixgbe_mac_X550) 4102 *speed = IXGBE_LINK_SPEED_10_FULL; 4103 break; 4104 default: 4105 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4106 } 4107 4108 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) { 4109 if (*speed == IXGBE_LINK_SPEED_UNKNOWN) 4110 mac->get_link_status = true; 4111 else 4112 mac->get_link_status = false; 4113 4114 goto out; 4115 } 4116 4117 /* if the read failed it could just be a mailbox collision, best wait 4118 * until we are called again and don't report an error 4119 */ 4120 if (mbx->ops.read(hw, &in_msg, 1, 0)) 4121 goto out; 4122 4123 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) { 4124 /* msg is not CTS and is NACK we must have lost CTS status */ 4125 if (in_msg & IXGBE_VT_MSGTYPE_NACK) 4126 mac->get_link_status = false; 4127 goto out; 4128 } 4129 4130 /* the pf is talking, if we timed out in the past we reinit */ 4131 if (!mbx->timeout) { 4132 ret_val = -1; 4133 goto out; 4134 } 4135 4136 /* if we passed all the tests above then the link is up and we no 4137 * longer need to check for link 4138 */ 4139 mac->get_link_status = false; 4140 4141 out: 4142 *link_up = !mac->get_link_status; 4143 return ret_val; 4144 } 4145 4146 static void 4147 ixgbe_dev_cancel_link_thread(struct rte_eth_dev *dev) 4148 { 4149 struct ixgbe_adapter *ad = dev->data->dev_private; 4150 void *retval; 4151 4152 if (rte_atomic32_read(&ad->link_thread_running)) { 4153 pthread_cancel(ad->link_thread_tid); 4154 pthread_join(ad->link_thread_tid, &retval); 4155 rte_atomic32_clear(&ad->link_thread_running); 4156 } 4157 } 4158 4159 static void * 4160 ixgbe_dev_setup_link_thread_handler(void *param) 4161 { 4162 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4163 struct ixgbe_adapter *ad = dev->data->dev_private; 4164 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4165 struct ixgbe_interrupt *intr = 4166 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4167 u32 speed; 4168 bool autoneg = false; 4169 4170 speed = hw->phy.autoneg_advertised; 4171 if (!speed) 4172 ixgbe_get_link_capabilities(hw, &speed, &autoneg); 4173 4174 ixgbe_setup_link(hw, speed, true); 4175 4176 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 4177 rte_atomic32_clear(&ad->link_thread_running); 4178 return NULL; 4179 } 4180 4181 /* 4182 * In freebsd environment, nic_uio drivers do not support interrupts, 4183 * rte_intr_callback_register() will fail to register interrupts. 4184 * We can not make link status to change from down to up by interrupt 4185 * callback. So we need to wait for the controller to acquire link 4186 * when ports start. 4187 * It returns 0 on link up. 4188 */ 4189 static int 4190 ixgbe_wait_for_link_up(struct ixgbe_hw *hw) 4191 { 4192 #ifdef RTE_EXEC_ENV_FREEBSD 4193 int err, i; 4194 bool link_up = false; 4195 uint32_t speed = 0; 4196 const int nb_iter = 25; 4197 4198 for (i = 0; i < nb_iter; i++) { 4199 err = ixgbe_check_link(hw, &speed, &link_up, 0); 4200 if (err) 4201 return err; 4202 if (link_up) 4203 return 0; 4204 msec_delay(200); 4205 } 4206 4207 return 0; 4208 #else 4209 RTE_SET_USED(hw); 4210 return 0; 4211 #endif 4212 } 4213 4214 /* return 0 means link status changed, -1 means not changed */ 4215 int 4216 ixgbe_dev_link_update_share(struct rte_eth_dev *dev, 4217 int wait_to_complete, int vf) 4218 { 4219 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4220 struct ixgbe_adapter *ad = dev->data->dev_private; 4221 struct rte_eth_link link; 4222 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4223 struct ixgbe_interrupt *intr = 4224 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4225 bool link_up; 4226 int diag; 4227 int wait = 1; 4228 u32 esdp_reg; 4229 4230 memset(&link, 0, sizeof(link)); 4231 link.link_status = ETH_LINK_DOWN; 4232 link.link_speed = ETH_SPEED_NUM_NONE; 4233 link.link_duplex = ETH_LINK_HALF_DUPLEX; 4234 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 4235 ETH_LINK_SPEED_FIXED); 4236 4237 hw->mac.get_link_status = true; 4238 4239 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) 4240 return rte_eth_linkstatus_set(dev, &link); 4241 4242 /* check if it needs to wait to complete, if lsc interrupt is enabled */ 4243 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0) 4244 wait = 0; 4245 4246 if (vf) 4247 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait); 4248 else 4249 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait); 4250 4251 if (diag != 0) { 4252 link.link_speed = ETH_SPEED_NUM_100M; 4253 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4254 return rte_eth_linkstatus_set(dev, &link); 4255 } 4256 4257 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) { 4258 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 4259 if ((esdp_reg & IXGBE_ESDP_SDP3)) 4260 link_up = 0; 4261 } 4262 4263 if (link_up == 0) { 4264 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) { 4265 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 4266 if (rte_atomic32_test_and_set(&ad->link_thread_running)) { 4267 if (rte_ctrl_thread_create(&ad->link_thread_tid, 4268 "ixgbe-link-handler", 4269 NULL, 4270 ixgbe_dev_setup_link_thread_handler, 4271 dev) < 0) { 4272 PMD_DRV_LOG(ERR, 4273 "Create link thread failed!"); 4274 rte_atomic32_clear(&ad->link_thread_running); 4275 } 4276 } else { 4277 PMD_DRV_LOG(ERR, 4278 "Other link thread is running now!"); 4279 } 4280 } 4281 return rte_eth_linkstatus_set(dev, &link); 4282 } 4283 4284 link.link_status = ETH_LINK_UP; 4285 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4286 4287 switch (link_speed) { 4288 default: 4289 case IXGBE_LINK_SPEED_UNKNOWN: 4290 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 4291 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 4292 link.link_speed = ETH_SPEED_NUM_10M; 4293 else 4294 link.link_speed = ETH_SPEED_NUM_100M; 4295 break; 4296 4297 case IXGBE_LINK_SPEED_100_FULL: 4298 link.link_speed = ETH_SPEED_NUM_100M; 4299 break; 4300 4301 case IXGBE_LINK_SPEED_1GB_FULL: 4302 link.link_speed = ETH_SPEED_NUM_1G; 4303 break; 4304 4305 case IXGBE_LINK_SPEED_2_5GB_FULL: 4306 link.link_speed = ETH_SPEED_NUM_2_5G; 4307 break; 4308 4309 case IXGBE_LINK_SPEED_5GB_FULL: 4310 link.link_speed = ETH_SPEED_NUM_5G; 4311 break; 4312 4313 case IXGBE_LINK_SPEED_10GB_FULL: 4314 link.link_speed = ETH_SPEED_NUM_10G; 4315 break; 4316 } 4317 4318 return rte_eth_linkstatus_set(dev, &link); 4319 } 4320 4321 static int 4322 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4323 { 4324 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0); 4325 } 4326 4327 static int 4328 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4329 { 4330 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1); 4331 } 4332 4333 static int 4334 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 4335 { 4336 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4337 uint32_t fctrl; 4338 4339 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4340 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4341 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4342 4343 return 0; 4344 } 4345 4346 static int 4347 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 4348 { 4349 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4350 uint32_t fctrl; 4351 4352 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4353 fctrl &= (~IXGBE_FCTRL_UPE); 4354 if (dev->data->all_multicast == 1) 4355 fctrl |= IXGBE_FCTRL_MPE; 4356 else 4357 fctrl &= (~IXGBE_FCTRL_MPE); 4358 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4359 4360 return 0; 4361 } 4362 4363 static int 4364 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 4365 { 4366 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4367 uint32_t fctrl; 4368 4369 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4370 fctrl |= IXGBE_FCTRL_MPE; 4371 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4372 4373 return 0; 4374 } 4375 4376 static int 4377 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 4378 { 4379 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4380 uint32_t fctrl; 4381 4382 if (dev->data->promiscuous == 1) 4383 return 0; /* must remain in all_multicast mode */ 4384 4385 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4386 fctrl &= (~IXGBE_FCTRL_MPE); 4387 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4388 4389 return 0; 4390 } 4391 4392 /** 4393 * It clears the interrupt causes and enables the interrupt. 4394 * It will be called once only during nic initialized. 4395 * 4396 * @param dev 4397 * Pointer to struct rte_eth_dev. 4398 * @param on 4399 * Enable or Disable. 4400 * 4401 * @return 4402 * - On success, zero. 4403 * - On failure, a negative value. 4404 */ 4405 static int 4406 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 4407 { 4408 struct ixgbe_interrupt *intr = 4409 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4410 4411 ixgbe_dev_link_status_print(dev); 4412 if (on) 4413 intr->mask |= IXGBE_EICR_LSC; 4414 else 4415 intr->mask &= ~IXGBE_EICR_LSC; 4416 4417 return 0; 4418 } 4419 4420 /** 4421 * It clears the interrupt causes and enables the interrupt. 4422 * It will be called once only during nic initialized. 4423 * 4424 * @param dev 4425 * Pointer to struct rte_eth_dev. 4426 * 4427 * @return 4428 * - On success, zero. 4429 * - On failure, a negative value. 4430 */ 4431 static int 4432 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev) 4433 { 4434 struct ixgbe_interrupt *intr = 4435 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4436 4437 intr->mask |= IXGBE_EICR_RTX_QUEUE; 4438 4439 return 0; 4440 } 4441 4442 /** 4443 * It clears the interrupt causes and enables the interrupt. 4444 * It will be called once only during nic initialized. 4445 * 4446 * @param dev 4447 * Pointer to struct rte_eth_dev. 4448 * 4449 * @return 4450 * - On success, zero. 4451 * - On failure, a negative value. 4452 */ 4453 static int 4454 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev) 4455 { 4456 struct ixgbe_interrupt *intr = 4457 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4458 4459 intr->mask |= IXGBE_EICR_LINKSEC; 4460 4461 return 0; 4462 } 4463 4464 /* 4465 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update. 4466 * 4467 * @param dev 4468 * Pointer to struct rte_eth_dev. 4469 * 4470 * @return 4471 * - On success, zero. 4472 * - On failure, a negative value. 4473 */ 4474 static int 4475 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev) 4476 { 4477 uint32_t eicr; 4478 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4479 struct ixgbe_interrupt *intr = 4480 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4481 4482 /* clear all cause mask */ 4483 ixgbe_disable_intr(hw); 4484 4485 /* read-on-clear nic registers here */ 4486 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4487 PMD_DRV_LOG(DEBUG, "eicr %x", eicr); 4488 4489 intr->flags = 0; 4490 4491 /* set flag for async link update */ 4492 if (eicr & IXGBE_EICR_LSC) 4493 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 4494 4495 if (eicr & IXGBE_EICR_MAILBOX) 4496 intr->flags |= IXGBE_FLAG_MAILBOX; 4497 4498 if (eicr & IXGBE_EICR_LINKSEC) 4499 intr->flags |= IXGBE_FLAG_MACSEC; 4500 4501 if (hw->mac.type == ixgbe_mac_X550EM_x && 4502 hw->phy.type == ixgbe_phy_x550em_ext_t && 4503 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x)) 4504 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT; 4505 4506 return 0; 4507 } 4508 4509 /** 4510 * It gets and then prints the link status. 4511 * 4512 * @param dev 4513 * Pointer to struct rte_eth_dev. 4514 * 4515 * @return 4516 * - On success, zero. 4517 * - On failure, a negative value. 4518 */ 4519 static void 4520 ixgbe_dev_link_status_print(struct rte_eth_dev *dev) 4521 { 4522 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4523 struct rte_eth_link link; 4524 4525 rte_eth_linkstatus_get(dev, &link); 4526 4527 if (link.link_status) { 4528 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", 4529 (int)(dev->data->port_id), 4530 (unsigned)link.link_speed, 4531 link.link_duplex == ETH_LINK_FULL_DUPLEX ? 4532 "full-duplex" : "half-duplex"); 4533 } else { 4534 PMD_INIT_LOG(INFO, " Port %d: Link Down", 4535 (int)(dev->data->port_id)); 4536 } 4537 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 4538 pci_dev->addr.domain, 4539 pci_dev->addr.bus, 4540 pci_dev->addr.devid, 4541 pci_dev->addr.function); 4542 } 4543 4544 /* 4545 * It executes link_update after knowing an interrupt occurred. 4546 * 4547 * @param dev 4548 * Pointer to struct rte_eth_dev. 4549 * 4550 * @return 4551 * - On success, zero. 4552 * - On failure, a negative value. 4553 */ 4554 static int 4555 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev) 4556 { 4557 struct ixgbe_interrupt *intr = 4558 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4559 int64_t timeout; 4560 struct ixgbe_hw *hw = 4561 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4562 4563 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags); 4564 4565 if (intr->flags & IXGBE_FLAG_MAILBOX) { 4566 ixgbe_pf_mbx_process(dev); 4567 intr->flags &= ~IXGBE_FLAG_MAILBOX; 4568 } 4569 4570 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4571 ixgbe_handle_lasi(hw); 4572 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4573 } 4574 4575 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4576 struct rte_eth_link link; 4577 4578 /* get the link status before link update, for predicting later */ 4579 rte_eth_linkstatus_get(dev, &link); 4580 4581 ixgbe_dev_link_update(dev, 0); 4582 4583 /* likely to up */ 4584 if (!link.link_status) 4585 /* handle it 1 sec later, wait it being stable */ 4586 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT; 4587 /* likely to down */ 4588 else 4589 /* handle it 4 sec later, wait it being stable */ 4590 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT; 4591 4592 ixgbe_dev_link_status_print(dev); 4593 if (rte_eal_alarm_set(timeout * 1000, 4594 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0) 4595 PMD_DRV_LOG(ERR, "Error setting alarm"); 4596 else { 4597 /* remember original mask */ 4598 intr->mask_original = intr->mask; 4599 /* only disable lsc interrupt */ 4600 intr->mask &= ~IXGBE_EIMS_LSC; 4601 } 4602 } 4603 4604 PMD_DRV_LOG(DEBUG, "enable intr immediately"); 4605 ixgbe_enable_intr(dev); 4606 4607 return 0; 4608 } 4609 4610 /** 4611 * Interrupt handler which shall be registered for alarm callback for delayed 4612 * handling specific interrupt to wait for the stable nic state. As the 4613 * NIC interrupt state is not stable for ixgbe after link is just down, 4614 * it needs to wait 4 seconds to get the stable status. 4615 * 4616 * @param handle 4617 * Pointer to interrupt handle. 4618 * @param param 4619 * The address of parameter (struct rte_eth_dev *) regsitered before. 4620 * 4621 * @return 4622 * void 4623 */ 4624 static void 4625 ixgbe_dev_interrupt_delayed_handler(void *param) 4626 { 4627 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4628 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4629 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4630 struct ixgbe_interrupt *intr = 4631 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4632 struct ixgbe_hw *hw = 4633 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4634 uint32_t eicr; 4635 4636 ixgbe_disable_intr(hw); 4637 4638 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4639 if (eicr & IXGBE_EICR_MAILBOX) 4640 ixgbe_pf_mbx_process(dev); 4641 4642 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4643 ixgbe_handle_lasi(hw); 4644 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4645 } 4646 4647 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4648 ixgbe_dev_link_update(dev, 0); 4649 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 4650 ixgbe_dev_link_status_print(dev); 4651 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, 4652 NULL); 4653 } 4654 4655 if (intr->flags & IXGBE_FLAG_MACSEC) { 4656 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, 4657 NULL); 4658 intr->flags &= ~IXGBE_FLAG_MACSEC; 4659 } 4660 4661 /* restore original mask */ 4662 intr->mask = intr->mask_original; 4663 intr->mask_original = 0; 4664 4665 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr); 4666 ixgbe_enable_intr(dev); 4667 rte_intr_ack(intr_handle); 4668 } 4669 4670 /** 4671 * Interrupt handler triggered by NIC for handling 4672 * specific interrupt. 4673 * 4674 * @param handle 4675 * Pointer to interrupt handle. 4676 * @param param 4677 * The address of parameter (struct rte_eth_dev *) regsitered before. 4678 * 4679 * @return 4680 * void 4681 */ 4682 static void 4683 ixgbe_dev_interrupt_handler(void *param) 4684 { 4685 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4686 4687 ixgbe_dev_interrupt_get_status(dev); 4688 ixgbe_dev_interrupt_action(dev); 4689 } 4690 4691 static int 4692 ixgbe_dev_led_on(struct rte_eth_dev *dev) 4693 { 4694 struct ixgbe_hw *hw; 4695 4696 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4697 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4698 } 4699 4700 static int 4701 ixgbe_dev_led_off(struct rte_eth_dev *dev) 4702 { 4703 struct ixgbe_hw *hw; 4704 4705 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4706 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4707 } 4708 4709 static int 4710 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4711 { 4712 struct ixgbe_hw *hw; 4713 uint32_t mflcn_reg; 4714 uint32_t fccfg_reg; 4715 int rx_pause; 4716 int tx_pause; 4717 4718 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4719 4720 fc_conf->pause_time = hw->fc.pause_time; 4721 fc_conf->high_water = hw->fc.high_water[0]; 4722 fc_conf->low_water = hw->fc.low_water[0]; 4723 fc_conf->send_xon = hw->fc.send_xon; 4724 fc_conf->autoneg = !hw->fc.disable_fc_autoneg; 4725 4726 /* 4727 * Return rx_pause status according to actual setting of 4728 * MFLCN register. 4729 */ 4730 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4731 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE)) 4732 rx_pause = 1; 4733 else 4734 rx_pause = 0; 4735 4736 /* 4737 * Return tx_pause status according to actual setting of 4738 * FCCFG register. 4739 */ 4740 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4741 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY)) 4742 tx_pause = 1; 4743 else 4744 tx_pause = 0; 4745 4746 if (rx_pause && tx_pause) 4747 fc_conf->mode = RTE_FC_FULL; 4748 else if (rx_pause) 4749 fc_conf->mode = RTE_FC_RX_PAUSE; 4750 else if (tx_pause) 4751 fc_conf->mode = RTE_FC_TX_PAUSE; 4752 else 4753 fc_conf->mode = RTE_FC_NONE; 4754 4755 return 0; 4756 } 4757 4758 static int 4759 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4760 { 4761 struct ixgbe_hw *hw; 4762 struct ixgbe_adapter *adapter = dev->data->dev_private; 4763 int err; 4764 uint32_t rx_buf_size; 4765 uint32_t max_high_water; 4766 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4767 ixgbe_fc_none, 4768 ixgbe_fc_rx_pause, 4769 ixgbe_fc_tx_pause, 4770 ixgbe_fc_full 4771 }; 4772 4773 PMD_INIT_FUNC_TRACE(); 4774 4775 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4776 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)); 4777 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4778 4779 /* 4780 * At least reserve one Ethernet frame for watermark 4781 * high_water/low_water in kilo bytes for ixgbe 4782 */ 4783 max_high_water = (rx_buf_size - 4784 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4785 if ((fc_conf->high_water > max_high_water) || 4786 (fc_conf->high_water < fc_conf->low_water)) { 4787 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4788 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4789 return -EINVAL; 4790 } 4791 4792 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode]; 4793 hw->fc.pause_time = fc_conf->pause_time; 4794 hw->fc.high_water[0] = fc_conf->high_water; 4795 hw->fc.low_water[0] = fc_conf->low_water; 4796 hw->fc.send_xon = fc_conf->send_xon; 4797 hw->fc.disable_fc_autoneg = !fc_conf->autoneg; 4798 adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; 4799 4800 err = ixgbe_flow_ctrl_enable(dev, hw); 4801 if (err < 0) { 4802 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err); 4803 return -EIO; 4804 } 4805 return err; 4806 } 4807 4808 /** 4809 * ixgbe_pfc_enable_generic - Enable flow control 4810 * @hw: pointer to hardware structure 4811 * @tc_num: traffic class number 4812 * Enable flow control according to the current settings. 4813 */ 4814 static int 4815 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num) 4816 { 4817 int ret_val = 0; 4818 uint32_t mflcn_reg, fccfg_reg; 4819 uint32_t reg; 4820 uint32_t fcrtl, fcrth; 4821 uint8_t i; 4822 uint8_t nb_rx_en; 4823 4824 /* Validate the water mark configuration */ 4825 if (!hw->fc.pause_time) { 4826 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4827 goto out; 4828 } 4829 4830 /* Low water mark of zero causes XOFF floods */ 4831 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 4832 /* High/Low water can not be 0 */ 4833 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) { 4834 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4835 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4836 goto out; 4837 } 4838 4839 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) { 4840 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4841 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4842 goto out; 4843 } 4844 } 4845 /* Negotiate the fc mode to use */ 4846 ixgbe_fc_autoneg(hw); 4847 4848 /* Disable any previous flow control settings */ 4849 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4850 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE); 4851 4852 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4853 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 4854 4855 switch (hw->fc.current_mode) { 4856 case ixgbe_fc_none: 4857 /* 4858 * If the count of enabled RX Priority Flow control >1, 4859 * and the TX pause can not be disabled 4860 */ 4861 nb_rx_en = 0; 4862 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4863 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4864 if (reg & IXGBE_FCRTH_FCEN) 4865 nb_rx_en++; 4866 } 4867 if (nb_rx_en > 1) 4868 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4869 break; 4870 case ixgbe_fc_rx_pause: 4871 /* 4872 * Rx Flow control is enabled and Tx Flow control is 4873 * disabled by software override. Since there really 4874 * isn't a way to advertise that we are capable of RX 4875 * Pause ONLY, we will advertise that we support both 4876 * symmetric and asymmetric Rx PAUSE. Later, we will 4877 * disable the adapter's ability to send PAUSE frames. 4878 */ 4879 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4880 /* 4881 * If the count of enabled RX Priority Flow control >1, 4882 * and the TX pause can not be disabled 4883 */ 4884 nb_rx_en = 0; 4885 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4886 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4887 if (reg & IXGBE_FCRTH_FCEN) 4888 nb_rx_en++; 4889 } 4890 if (nb_rx_en > 1) 4891 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4892 break; 4893 case ixgbe_fc_tx_pause: 4894 /* 4895 * Tx Flow control is enabled, and Rx Flow control is 4896 * disabled by software override. 4897 */ 4898 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4899 break; 4900 case ixgbe_fc_full: 4901 /* Flow control (both Rx and Tx) is enabled by SW override. */ 4902 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4903 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4904 break; 4905 default: 4906 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly"); 4907 ret_val = IXGBE_ERR_CONFIG; 4908 goto out; 4909 } 4910 4911 /* Set 802.3x based flow control settings. */ 4912 mflcn_reg |= IXGBE_MFLCN_DPF; 4913 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 4914 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 4915 4916 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 4917 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 4918 hw->fc.high_water[tc_num]) { 4919 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE; 4920 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl); 4921 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN; 4922 } else { 4923 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0); 4924 /* 4925 * In order to prevent Tx hangs when the internal Tx 4926 * switch is enabled we must set the high water mark 4927 * to the maximum FCRTH value. This allows the Tx 4928 * switch to function even under heavy Rx workloads. 4929 */ 4930 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32; 4931 } 4932 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth); 4933 4934 /* Configure pause time (2 TCs per register) */ 4935 reg = hw->fc.pause_time * 0x00010001; 4936 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 4937 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 4938 4939 /* Configure flow control refresh threshold value */ 4940 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 4941 4942 out: 4943 return ret_val; 4944 } 4945 4946 static int 4947 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num) 4948 { 4949 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4950 int32_t ret_val = IXGBE_NOT_IMPLEMENTED; 4951 4952 if (hw->mac.type != ixgbe_mac_82598EB) { 4953 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num); 4954 } 4955 return ret_val; 4956 } 4957 4958 static int 4959 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf) 4960 { 4961 int err; 4962 uint32_t rx_buf_size; 4963 uint32_t max_high_water; 4964 uint8_t tc_num; 4965 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 4966 struct ixgbe_hw *hw = 4967 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4968 struct ixgbe_dcb_config *dcb_config = 4969 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 4970 4971 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4972 ixgbe_fc_none, 4973 ixgbe_fc_rx_pause, 4974 ixgbe_fc_tx_pause, 4975 ixgbe_fc_full 4976 }; 4977 4978 PMD_INIT_FUNC_TRACE(); 4979 4980 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map); 4981 tc_num = map[pfc_conf->priority]; 4982 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)); 4983 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4984 /* 4985 * At least reserve one Ethernet frame for watermark 4986 * high_water/low_water in kilo bytes for ixgbe 4987 */ 4988 max_high_water = (rx_buf_size - 4989 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4990 if ((pfc_conf->fc.high_water > max_high_water) || 4991 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) { 4992 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4993 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4994 return -EINVAL; 4995 } 4996 4997 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode]; 4998 hw->fc.pause_time = pfc_conf->fc.pause_time; 4999 hw->fc.send_xon = pfc_conf->fc.send_xon; 5000 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water; 5001 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; 5002 5003 err = ixgbe_dcb_pfc_enable(dev, tc_num); 5004 5005 /* Not negotiated is not an error case */ 5006 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) 5007 return 0; 5008 5009 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err); 5010 return -EIO; 5011 } 5012 5013 static int 5014 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 5015 struct rte_eth_rss_reta_entry64 *reta_conf, 5016 uint16_t reta_size) 5017 { 5018 uint16_t i, sp_reta_size; 5019 uint8_t j, mask; 5020 uint32_t reta, r; 5021 uint16_t idx, shift; 5022 struct ixgbe_adapter *adapter = dev->data->dev_private; 5023 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5024 uint32_t reta_reg; 5025 5026 PMD_INIT_FUNC_TRACE(); 5027 5028 if (!ixgbe_rss_update_sp(hw->mac.type)) { 5029 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " 5030 "NIC."); 5031 return -ENOTSUP; 5032 } 5033 5034 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 5035 if (reta_size != sp_reta_size) { 5036 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 5037 "(%d) doesn't match the number hardware can supported " 5038 "(%d)", reta_size, sp_reta_size); 5039 return -EINVAL; 5040 } 5041 5042 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 5043 idx = i / RTE_RETA_GROUP_SIZE; 5044 shift = i % RTE_RETA_GROUP_SIZE; 5045 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 5046 IXGBE_4_BIT_MASK); 5047 if (!mask) 5048 continue; 5049 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 5050 if (mask == IXGBE_4_BIT_MASK) 5051 r = 0; 5052 else 5053 r = IXGBE_READ_REG(hw, reta_reg); 5054 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) { 5055 if (mask & (0x1 << j)) 5056 reta |= reta_conf[idx].reta[shift + j] << 5057 (CHAR_BIT * j); 5058 else 5059 reta |= r & (IXGBE_8_BIT_MASK << 5060 (CHAR_BIT * j)); 5061 } 5062 IXGBE_WRITE_REG(hw, reta_reg, reta); 5063 } 5064 adapter->rss_reta_updated = 1; 5065 5066 return 0; 5067 } 5068 5069 static int 5070 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 5071 struct rte_eth_rss_reta_entry64 *reta_conf, 5072 uint16_t reta_size) 5073 { 5074 uint16_t i, sp_reta_size; 5075 uint8_t j, mask; 5076 uint32_t reta; 5077 uint16_t idx, shift; 5078 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5079 uint32_t reta_reg; 5080 5081 PMD_INIT_FUNC_TRACE(); 5082 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 5083 if (reta_size != sp_reta_size) { 5084 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 5085 "(%d) doesn't match the number hardware can supported " 5086 "(%d)", reta_size, sp_reta_size); 5087 return -EINVAL; 5088 } 5089 5090 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 5091 idx = i / RTE_RETA_GROUP_SIZE; 5092 shift = i % RTE_RETA_GROUP_SIZE; 5093 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 5094 IXGBE_4_BIT_MASK); 5095 if (!mask) 5096 continue; 5097 5098 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 5099 reta = IXGBE_READ_REG(hw, reta_reg); 5100 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) { 5101 if (mask & (0x1 << j)) 5102 reta_conf[idx].reta[shift + j] = 5103 ((reta >> (CHAR_BIT * j)) & 5104 IXGBE_8_BIT_MASK); 5105 } 5106 } 5107 5108 return 0; 5109 } 5110 5111 static int 5112 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 5113 uint32_t index, uint32_t pool) 5114 { 5115 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5116 uint32_t enable_addr = 1; 5117 5118 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes, 5119 pool, enable_addr); 5120 } 5121 5122 static void 5123 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) 5124 { 5125 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5126 5127 ixgbe_clear_rar(hw, index); 5128 } 5129 5130 static int 5131 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 5132 { 5133 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5134 5135 ixgbe_remove_rar(dev, 0); 5136 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs); 5137 5138 return 0; 5139 } 5140 5141 static bool 5142 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 5143 { 5144 if (strcmp(dev->device->driver->name, drv->driver.name)) 5145 return false; 5146 5147 return true; 5148 } 5149 5150 bool 5151 is_ixgbe_supported(struct rte_eth_dev *dev) 5152 { 5153 return is_device_supported(dev, &rte_ixgbe_pmd); 5154 } 5155 5156 static int 5157 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 5158 { 5159 uint32_t hlreg0; 5160 uint32_t maxfrs; 5161 struct ixgbe_hw *hw; 5162 struct rte_eth_dev_info dev_info; 5163 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD; 5164 struct rte_eth_dev_data *dev_data = dev->data; 5165 int ret; 5166 5167 ret = ixgbe_dev_info_get(dev, &dev_info); 5168 if (ret != 0) 5169 return ret; 5170 5171 /* check that mtu is within the allowed range */ 5172 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) 5173 return -EINVAL; 5174 5175 /* If device is started, refuse mtu that requires the support of 5176 * scattered packets when this feature has not been enabled before. 5177 */ 5178 if (dev_data->dev_started && !dev_data->scattered_rx && 5179 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE > 5180 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 5181 PMD_INIT_LOG(ERR, "Stop port first."); 5182 return -EINVAL; 5183 } 5184 5185 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5186 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 5187 5188 /* switch to jumbo mode if needed */ 5189 if (frame_size > RTE_ETHER_MAX_LEN) { 5190 dev->data->dev_conf.rxmode.offloads |= 5191 DEV_RX_OFFLOAD_JUMBO_FRAME; 5192 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 5193 } else { 5194 dev->data->dev_conf.rxmode.offloads &= 5195 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 5196 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; 5197 } 5198 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 5199 5200 /* update max frame size */ 5201 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 5202 5203 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS); 5204 maxfrs &= 0x0000FFFF; 5205 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16); 5206 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs); 5207 5208 return 0; 5209 } 5210 5211 /* 5212 * Virtual Function operations 5213 */ 5214 static void 5215 ixgbevf_intr_disable(struct rte_eth_dev *dev) 5216 { 5217 struct ixgbe_interrupt *intr = 5218 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5219 struct ixgbe_hw *hw = 5220 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5221 5222 PMD_INIT_FUNC_TRACE(); 5223 5224 /* Clear interrupt mask to stop from interrupts being generated */ 5225 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK); 5226 5227 IXGBE_WRITE_FLUSH(hw); 5228 5229 /* Clear mask value. */ 5230 intr->mask = 0; 5231 } 5232 5233 static void 5234 ixgbevf_intr_enable(struct rte_eth_dev *dev) 5235 { 5236 struct ixgbe_interrupt *intr = 5237 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5238 struct ixgbe_hw *hw = 5239 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5240 5241 PMD_INIT_FUNC_TRACE(); 5242 5243 /* VF enable interrupt autoclean */ 5244 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK); 5245 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK); 5246 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK); 5247 5248 IXGBE_WRITE_FLUSH(hw); 5249 5250 /* Save IXGBE_VTEIMS value to mask. */ 5251 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK; 5252 } 5253 5254 static int 5255 ixgbevf_dev_configure(struct rte_eth_dev *dev) 5256 { 5257 struct rte_eth_conf *conf = &dev->data->dev_conf; 5258 struct ixgbe_adapter *adapter = dev->data->dev_private; 5259 5260 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d", 5261 dev->data->port_id); 5262 5263 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 5264 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 5265 5266 /* 5267 * VF has no ability to enable/disable HW CRC 5268 * Keep the persistent behavior the same as Host PF 5269 */ 5270 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC 5271 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) { 5272 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip"); 5273 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC; 5274 } 5275 #else 5276 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) { 5277 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip"); 5278 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC; 5279 } 5280 #endif 5281 5282 /* 5283 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 5284 * allocation or vector Rx preconditions we will reset it. 5285 */ 5286 adapter->rx_bulk_alloc_allowed = true; 5287 adapter->rx_vec_allowed = true; 5288 5289 return 0; 5290 } 5291 5292 static int 5293 ixgbevf_dev_start(struct rte_eth_dev *dev) 5294 { 5295 struct ixgbe_hw *hw = 5296 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5297 uint32_t intr_vector = 0; 5298 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5299 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5300 5301 int err, mask = 0; 5302 5303 PMD_INIT_FUNC_TRACE(); 5304 5305 /* Stop the link setup handler before resetting the HW. */ 5306 ixgbe_dev_cancel_link_thread(dev); 5307 5308 err = hw->mac.ops.reset_hw(hw); 5309 if (err) { 5310 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err); 5311 return err; 5312 } 5313 hw->mac.get_link_status = true; 5314 5315 /* negotiate mailbox API version to use with the PF. */ 5316 ixgbevf_negotiate_api(hw); 5317 5318 ixgbevf_dev_tx_init(dev); 5319 5320 /* This can fail when allocating mbufs for descriptor rings */ 5321 err = ixgbevf_dev_rx_init(dev); 5322 if (err) { 5323 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err); 5324 ixgbe_dev_clear_queues(dev); 5325 return err; 5326 } 5327 5328 /* Set vfta */ 5329 ixgbevf_set_vfta_all(dev, 1); 5330 5331 /* Set HW strip */ 5332 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 5333 ETH_VLAN_EXTEND_MASK; 5334 err = ixgbevf_vlan_offload_config(dev, mask); 5335 if (err) { 5336 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err); 5337 ixgbe_dev_clear_queues(dev); 5338 return err; 5339 } 5340 5341 ixgbevf_dev_rxtx_start(dev); 5342 5343 /* check and configure queue intr-vector mapping */ 5344 if (rte_intr_cap_multiple(intr_handle) && 5345 dev->data->dev_conf.intr_conf.rxq) { 5346 /* According to datasheet, only vector 0/1/2 can be used, 5347 * now only one vector is used for Rx queue 5348 */ 5349 intr_vector = 1; 5350 if (rte_intr_efd_enable(intr_handle, intr_vector)) 5351 return -1; 5352 } 5353 5354 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 5355 intr_handle->intr_vec = 5356 rte_zmalloc("intr_vec", 5357 dev->data->nb_rx_queues * sizeof(int), 0); 5358 if (intr_handle->intr_vec == NULL) { 5359 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 5360 " intr_vec", dev->data->nb_rx_queues); 5361 return -ENOMEM; 5362 } 5363 } 5364 ixgbevf_configure_msix(dev); 5365 5366 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt 5367 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ). 5368 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( ) 5369 * is not cleared, it will fail when following rte_intr_enable( ) tries 5370 * to map Rx queue interrupt to other VFIO vectors. 5371 * So clear uio/vfio intr/evevnfd first to avoid failure. 5372 */ 5373 rte_intr_disable(intr_handle); 5374 5375 rte_intr_enable(intr_handle); 5376 5377 /* Re-enable interrupt for VF */ 5378 ixgbevf_intr_enable(dev); 5379 5380 /* 5381 * Update link status right before return, because it may 5382 * start link configuration process in a separate thread. 5383 */ 5384 ixgbevf_dev_link_update(dev, 0); 5385 5386 hw->adapter_stopped = false; 5387 5388 return 0; 5389 } 5390 5391 static void 5392 ixgbevf_dev_stop(struct rte_eth_dev *dev) 5393 { 5394 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5395 struct ixgbe_adapter *adapter = dev->data->dev_private; 5396 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5397 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5398 5399 if (hw->adapter_stopped) 5400 return; 5401 5402 PMD_INIT_FUNC_TRACE(); 5403 5404 ixgbe_dev_cancel_link_thread(dev); 5405 5406 ixgbevf_intr_disable(dev); 5407 5408 hw->adapter_stopped = 1; 5409 ixgbe_stop_adapter(hw); 5410 5411 /* 5412 * Clear what we set, but we still keep shadow_vfta to 5413 * restore after device starts 5414 */ 5415 ixgbevf_set_vfta_all(dev, 0); 5416 5417 /* Clear stored conf */ 5418 dev->data->scattered_rx = 0; 5419 5420 ixgbe_dev_clear_queues(dev); 5421 5422 /* Clean datapath event and queue/vec mapping */ 5423 rte_intr_efd_disable(intr_handle); 5424 if (intr_handle->intr_vec != NULL) { 5425 rte_free(intr_handle->intr_vec); 5426 intr_handle->intr_vec = NULL; 5427 } 5428 5429 adapter->rss_reta_updated = 0; 5430 } 5431 5432 static void 5433 ixgbevf_dev_close(struct rte_eth_dev *dev) 5434 { 5435 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5436 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5437 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5438 5439 PMD_INIT_FUNC_TRACE(); 5440 5441 ixgbe_reset_hw(hw); 5442 5443 ixgbevf_dev_stop(dev); 5444 5445 ixgbe_dev_free_queues(dev); 5446 5447 /** 5448 * Remove the VF MAC address ro ensure 5449 * that the VF traffic goes to the PF 5450 * after stop, close and detach of the VF 5451 **/ 5452 ixgbevf_remove_mac_addr(dev, 0); 5453 5454 dev->dev_ops = NULL; 5455 dev->rx_pkt_burst = NULL; 5456 dev->tx_pkt_burst = NULL; 5457 5458 rte_intr_disable(intr_handle); 5459 rte_intr_callback_unregister(intr_handle, 5460 ixgbevf_dev_interrupt_handler, dev); 5461 } 5462 5463 /* 5464 * Reset VF device 5465 */ 5466 static int 5467 ixgbevf_dev_reset(struct rte_eth_dev *dev) 5468 { 5469 int ret; 5470 5471 ret = eth_ixgbevf_dev_uninit(dev); 5472 if (ret) 5473 return ret; 5474 5475 ret = eth_ixgbevf_dev_init(dev); 5476 5477 return ret; 5478 } 5479 5480 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) 5481 { 5482 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5483 struct ixgbe_vfta *shadow_vfta = 5484 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5485 int i = 0, j = 0, vfta = 0, mask = 1; 5486 5487 for (i = 0; i < IXGBE_VFTA_SIZE; i++) { 5488 vfta = shadow_vfta->vfta[i]; 5489 if (vfta) { 5490 mask = 1; 5491 for (j = 0; j < 32; j++) { 5492 if (vfta & mask) 5493 ixgbe_set_vfta(hw, (i<<5)+j, 0, 5494 on, false); 5495 mask <<= 1; 5496 } 5497 } 5498 } 5499 5500 } 5501 5502 static int 5503 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 5504 { 5505 struct ixgbe_hw *hw = 5506 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5507 struct ixgbe_vfta *shadow_vfta = 5508 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5509 uint32_t vid_idx = 0; 5510 uint32_t vid_bit = 0; 5511 int ret = 0; 5512 5513 PMD_INIT_FUNC_TRACE(); 5514 5515 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */ 5516 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false); 5517 if (ret) { 5518 PMD_INIT_LOG(ERR, "Unable to set VF vlan"); 5519 return ret; 5520 } 5521 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 5522 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 5523 5524 /* Save what we set and retore it after device reset */ 5525 if (on) 5526 shadow_vfta->vfta[vid_idx] |= vid_bit; 5527 else 5528 shadow_vfta->vfta[vid_idx] &= ~vid_bit; 5529 5530 return 0; 5531 } 5532 5533 static void 5534 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 5535 { 5536 struct ixgbe_hw *hw = 5537 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5538 uint32_t ctrl; 5539 5540 PMD_INIT_FUNC_TRACE(); 5541 5542 if (queue >= hw->mac.max_rx_queues) 5543 return; 5544 5545 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 5546 if (on) 5547 ctrl |= IXGBE_RXDCTL_VME; 5548 else 5549 ctrl &= ~IXGBE_RXDCTL_VME; 5550 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 5551 5552 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on); 5553 } 5554 5555 static int 5556 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask) 5557 { 5558 struct ixgbe_rx_queue *rxq; 5559 uint16_t i; 5560 int on = 0; 5561 5562 /* VF function only support hw strip feature, others are not support */ 5563 if (mask & ETH_VLAN_STRIP_MASK) { 5564 for (i = 0; i < dev->data->nb_rx_queues; i++) { 5565 rxq = dev->data->rx_queues[i]; 5566 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP); 5567 ixgbevf_vlan_strip_queue_set(dev, i, on); 5568 } 5569 } 5570 5571 return 0; 5572 } 5573 5574 static int 5575 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 5576 { 5577 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 5578 5579 ixgbevf_vlan_offload_config(dev, mask); 5580 5581 return 0; 5582 } 5583 5584 int 5585 ixgbe_vt_check(struct ixgbe_hw *hw) 5586 { 5587 uint32_t reg_val; 5588 5589 /* if Virtualization Technology is enabled */ 5590 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 5591 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) { 5592 PMD_INIT_LOG(ERR, "VT must be enabled for this setting"); 5593 return -1; 5594 } 5595 5596 return 0; 5597 } 5598 5599 static uint32_t 5600 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr) 5601 { 5602 uint32_t vector = 0; 5603 5604 switch (hw->mac.mc_filter_type) { 5605 case 0: /* use bits [47:36] of the address */ 5606 vector = ((uc_addr->addr_bytes[4] >> 4) | 5607 (((uint16_t)uc_addr->addr_bytes[5]) << 4)); 5608 break; 5609 case 1: /* use bits [46:35] of the address */ 5610 vector = ((uc_addr->addr_bytes[4] >> 3) | 5611 (((uint16_t)uc_addr->addr_bytes[5]) << 5)); 5612 break; 5613 case 2: /* use bits [45:34] of the address */ 5614 vector = ((uc_addr->addr_bytes[4] >> 2) | 5615 (((uint16_t)uc_addr->addr_bytes[5]) << 6)); 5616 break; 5617 case 3: /* use bits [43:32] of the address */ 5618 vector = ((uc_addr->addr_bytes[4]) | 5619 (((uint16_t)uc_addr->addr_bytes[5]) << 8)); 5620 break; 5621 default: /* Invalid mc_filter_type */ 5622 break; 5623 } 5624 5625 /* vector can only be 12-bits or boundary will be exceeded */ 5626 vector &= 0xFFF; 5627 return vector; 5628 } 5629 5630 static int 5631 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, 5632 struct rte_ether_addr *mac_addr, uint8_t on) 5633 { 5634 uint32_t vector; 5635 uint32_t uta_idx; 5636 uint32_t reg_val; 5637 uint32_t uta_shift; 5638 uint32_t rc; 5639 const uint32_t ixgbe_uta_idx_mask = 0x7F; 5640 const uint32_t ixgbe_uta_bit_shift = 5; 5641 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1; 5642 const uint32_t bit1 = 0x1; 5643 5644 struct ixgbe_hw *hw = 5645 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5646 struct ixgbe_uta_info *uta_info = 5647 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5648 5649 /* The UTA table only exists on 82599 hardware and newer */ 5650 if (hw->mac.type < ixgbe_mac_82599EB) 5651 return -ENOTSUP; 5652 5653 vector = ixgbe_uta_vector(hw, mac_addr); 5654 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask; 5655 uta_shift = vector & ixgbe_uta_bit_mask; 5656 5657 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0); 5658 if (rc == on) 5659 return 0; 5660 5661 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx)); 5662 if (on) { 5663 uta_info->uta_in_use++; 5664 reg_val |= (bit1 << uta_shift); 5665 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift); 5666 } else { 5667 uta_info->uta_in_use--; 5668 reg_val &= ~(bit1 << uta_shift); 5669 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift); 5670 } 5671 5672 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val); 5673 5674 if (uta_info->uta_in_use > 0) 5675 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 5676 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 5677 else 5678 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 5679 5680 return 0; 5681 } 5682 5683 static int 5684 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) 5685 { 5686 int i; 5687 struct ixgbe_hw *hw = 5688 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5689 struct ixgbe_uta_info *uta_info = 5690 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5691 5692 /* The UTA table only exists on 82599 hardware and newer */ 5693 if (hw->mac.type < ixgbe_mac_82599EB) 5694 return -ENOTSUP; 5695 5696 if (on) { 5697 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5698 uta_info->uta_shadow[i] = ~0; 5699 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); 5700 } 5701 } else { 5702 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5703 uta_info->uta_shadow[i] = 0; 5704 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 5705 } 5706 } 5707 return 0; 5708 5709 } 5710 5711 uint32_t 5712 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val) 5713 { 5714 uint32_t new_val = orig_val; 5715 5716 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG) 5717 new_val |= IXGBE_VMOLR_AUPE; 5718 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC) 5719 new_val |= IXGBE_VMOLR_ROMPE; 5720 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC) 5721 new_val |= IXGBE_VMOLR_ROPE; 5722 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST) 5723 new_val |= IXGBE_VMOLR_BAM; 5724 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST) 5725 new_val |= IXGBE_VMOLR_MPE; 5726 5727 return new_val; 5728 } 5729 5730 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */ 5731 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */ 5732 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */ 5733 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */ 5734 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \ 5735 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \ 5736 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN)) 5737 5738 static int 5739 ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 5740 struct rte_eth_mirror_conf *mirror_conf, 5741 uint8_t rule_id, uint8_t on) 5742 { 5743 uint32_t mr_ctl, vlvf; 5744 uint32_t mp_lsb = 0; 5745 uint32_t mv_msb = 0; 5746 uint32_t mv_lsb = 0; 5747 uint32_t mp_msb = 0; 5748 uint8_t i = 0; 5749 int reg_index = 0; 5750 uint64_t vlan_mask = 0; 5751 5752 const uint8_t pool_mask_offset = 32; 5753 const uint8_t vlan_mask_offset = 32; 5754 const uint8_t dst_pool_offset = 8; 5755 const uint8_t rule_mr_offset = 4; 5756 const uint8_t mirror_rule_mask = 0x0F; 5757 5758 struct ixgbe_mirror_info *mr_info = 5759 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5760 struct ixgbe_hw *hw = 5761 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5762 uint8_t mirror_type = 0; 5763 5764 if (ixgbe_vt_check(hw) < 0) 5765 return -ENOTSUP; 5766 5767 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5768 return -EINVAL; 5769 5770 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) { 5771 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.", 5772 mirror_conf->rule_type); 5773 return -EINVAL; 5774 } 5775 5776 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5777 mirror_type |= IXGBE_MRCTL_VLME; 5778 /* Check if vlan id is valid and find conresponding VLAN ID 5779 * index in VLVF 5780 */ 5781 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) { 5782 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) { 5783 /* search vlan id related pool vlan filter 5784 * index 5785 */ 5786 reg_index = ixgbe_find_vlvf_slot( 5787 hw, 5788 mirror_conf->vlan.vlan_id[i], 5789 false); 5790 if (reg_index < 0) 5791 return -EINVAL; 5792 vlvf = IXGBE_READ_REG(hw, 5793 IXGBE_VLVF(reg_index)); 5794 if ((vlvf & IXGBE_VLVF_VIEN) && 5795 ((vlvf & IXGBE_VLVF_VLANID_MASK) == 5796 mirror_conf->vlan.vlan_id[i])) 5797 vlan_mask |= (1ULL << reg_index); 5798 else 5799 return -EINVAL; 5800 } 5801 } 5802 5803 if (on) { 5804 mv_lsb = vlan_mask & 0xFFFFFFFF; 5805 mv_msb = vlan_mask >> vlan_mask_offset; 5806 5807 mr_info->mr_conf[rule_id].vlan.vlan_mask = 5808 mirror_conf->vlan.vlan_mask; 5809 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) { 5810 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) 5811 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 5812 mirror_conf->vlan.vlan_id[i]; 5813 } 5814 } else { 5815 mv_lsb = 0; 5816 mv_msb = 0; 5817 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0; 5818 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) 5819 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0; 5820 } 5821 } 5822 5823 /** 5824 * if enable pool mirror, write related pool mask register,if disable 5825 * pool mirror, clear PFMRVM register 5826 */ 5827 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5828 mirror_type |= IXGBE_MRCTL_VPME; 5829 if (on) { 5830 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF; 5831 mp_msb = mirror_conf->pool_mask >> pool_mask_offset; 5832 mr_info->mr_conf[rule_id].pool_mask = 5833 mirror_conf->pool_mask; 5834 5835 } else { 5836 mp_lsb = 0; 5837 mp_msb = 0; 5838 mr_info->mr_conf[rule_id].pool_mask = 0; 5839 } 5840 } 5841 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT) 5842 mirror_type |= IXGBE_MRCTL_UPME; 5843 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT) 5844 mirror_type |= IXGBE_MRCTL_DPME; 5845 5846 /* read mirror control register and recalculate it */ 5847 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id)); 5848 5849 if (on) { 5850 mr_ctl |= mirror_type; 5851 mr_ctl &= mirror_rule_mask; 5852 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset; 5853 } else { 5854 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask); 5855 } 5856 5857 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type; 5858 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool; 5859 5860 /* write mirrror control register */ 5861 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5862 5863 /* write pool mirrror control register */ 5864 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5865 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb); 5866 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), 5867 mp_msb); 5868 } 5869 /* write VLAN mirrror control register */ 5870 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5871 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb); 5872 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), 5873 mv_msb); 5874 } 5875 5876 return 0; 5877 } 5878 5879 static int 5880 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id) 5881 { 5882 int mr_ctl = 0; 5883 uint32_t lsb_val = 0; 5884 uint32_t msb_val = 0; 5885 const uint8_t rule_mr_offset = 4; 5886 5887 struct ixgbe_hw *hw = 5888 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5889 struct ixgbe_mirror_info *mr_info = 5890 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5891 5892 if (ixgbe_vt_check(hw) < 0) 5893 return -ENOTSUP; 5894 5895 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5896 return -EINVAL; 5897 5898 memset(&mr_info->mr_conf[rule_id], 0, 5899 sizeof(struct rte_eth_mirror_conf)); 5900 5901 /* clear PFVMCTL register */ 5902 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5903 5904 /* clear pool mask register */ 5905 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val); 5906 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val); 5907 5908 /* clear vlan mask register */ 5909 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val); 5910 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val); 5911 5912 return 0; 5913 } 5914 5915 static int 5916 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5917 { 5918 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5919 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5920 struct ixgbe_interrupt *intr = 5921 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5922 struct ixgbe_hw *hw = 5923 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5924 uint32_t vec = IXGBE_MISC_VEC_ID; 5925 5926 if (rte_intr_allow_others(intr_handle)) 5927 vec = IXGBE_RX_VEC_START; 5928 intr->mask |= (1 << vec); 5929 RTE_SET_USED(queue_id); 5930 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5931 5932 rte_intr_ack(intr_handle); 5933 5934 return 0; 5935 } 5936 5937 static int 5938 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5939 { 5940 struct ixgbe_interrupt *intr = 5941 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5942 struct ixgbe_hw *hw = 5943 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5944 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5945 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5946 uint32_t vec = IXGBE_MISC_VEC_ID; 5947 5948 if (rte_intr_allow_others(intr_handle)) 5949 vec = IXGBE_RX_VEC_START; 5950 intr->mask &= ~(1 << vec); 5951 RTE_SET_USED(queue_id); 5952 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5953 5954 return 0; 5955 } 5956 5957 static int 5958 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5959 { 5960 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5961 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5962 uint32_t mask; 5963 struct ixgbe_hw *hw = 5964 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5965 struct ixgbe_interrupt *intr = 5966 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5967 5968 if (queue_id < 16) { 5969 ixgbe_disable_intr(hw); 5970 intr->mask |= (1 << queue_id); 5971 ixgbe_enable_intr(dev); 5972 } else if (queue_id < 32) { 5973 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5974 mask &= (1 << queue_id); 5975 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5976 } else if (queue_id < 64) { 5977 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5978 mask &= (1 << (queue_id - 32)); 5979 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5980 } 5981 rte_intr_ack(intr_handle); 5982 5983 return 0; 5984 } 5985 5986 static int 5987 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5988 { 5989 uint32_t mask; 5990 struct ixgbe_hw *hw = 5991 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5992 struct ixgbe_interrupt *intr = 5993 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5994 5995 if (queue_id < 16) { 5996 ixgbe_disable_intr(hw); 5997 intr->mask &= ~(1 << queue_id); 5998 ixgbe_enable_intr(dev); 5999 } else if (queue_id < 32) { 6000 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 6001 mask &= ~(1 << queue_id); 6002 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 6003 } else if (queue_id < 64) { 6004 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 6005 mask &= ~(1 << (queue_id - 32)); 6006 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 6007 } 6008 6009 return 0; 6010 } 6011 6012 static void 6013 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 6014 uint8_t queue, uint8_t msix_vector) 6015 { 6016 uint32_t tmp, idx; 6017 6018 if (direction == -1) { 6019 /* other causes */ 6020 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 6021 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC); 6022 tmp &= ~0xFF; 6023 tmp |= msix_vector; 6024 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp); 6025 } else { 6026 /* rx or tx cause */ 6027 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 6028 idx = ((16 * (queue & 1)) + (8 * direction)); 6029 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1)); 6030 tmp &= ~(0xFF << idx); 6031 tmp |= (msix_vector << idx); 6032 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp); 6033 } 6034 } 6035 6036 /** 6037 * set the IVAR registers, mapping interrupt causes to vectors 6038 * @param hw 6039 * pointer to ixgbe_hw struct 6040 * @direction 6041 * 0 for Rx, 1 for Tx, -1 for other causes 6042 * @queue 6043 * queue to map the corresponding interrupt to 6044 * @msix_vector 6045 * the vector to map to the corresponding queue 6046 */ 6047 static void 6048 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 6049 uint8_t queue, uint8_t msix_vector) 6050 { 6051 uint32_t tmp, idx; 6052 6053 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 6054 if (hw->mac.type == ixgbe_mac_82598EB) { 6055 if (direction == -1) 6056 direction = 0; 6057 idx = (((direction * 64) + queue) >> 2) & 0x1F; 6058 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx)); 6059 tmp &= ~(0xFF << (8 * (queue & 0x3))); 6060 tmp |= (msix_vector << (8 * (queue & 0x3))); 6061 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp); 6062 } else if ((hw->mac.type == ixgbe_mac_82599EB) || 6063 (hw->mac.type == ixgbe_mac_X540) || 6064 (hw->mac.type == ixgbe_mac_X550) || 6065 (hw->mac.type == ixgbe_mac_X550EM_x)) { 6066 if (direction == -1) { 6067 /* other causes */ 6068 idx = ((queue & 1) * 8); 6069 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC); 6070 tmp &= ~(0xFF << idx); 6071 tmp |= (msix_vector << idx); 6072 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp); 6073 } else { 6074 /* rx or tx causes */ 6075 idx = ((16 * (queue & 1)) + (8 * direction)); 6076 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 6077 tmp &= ~(0xFF << idx); 6078 tmp |= (msix_vector << idx); 6079 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp); 6080 } 6081 } 6082 } 6083 6084 static void 6085 ixgbevf_configure_msix(struct rte_eth_dev *dev) 6086 { 6087 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 6088 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 6089 struct ixgbe_hw *hw = 6090 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6091 uint32_t q_idx; 6092 uint32_t vector_idx = IXGBE_MISC_VEC_ID; 6093 uint32_t base = IXGBE_MISC_VEC_ID; 6094 6095 /* Configure VF other cause ivar */ 6096 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx); 6097 6098 /* won't configure msix register if no mapping is done 6099 * between intr vector and event fd. 6100 */ 6101 if (!rte_intr_dp_is_en(intr_handle)) 6102 return; 6103 6104 if (rte_intr_allow_others(intr_handle)) { 6105 base = IXGBE_RX_VEC_START; 6106 vector_idx = IXGBE_RX_VEC_START; 6107 } 6108 6109 /* Configure all RX queues of VF */ 6110 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) { 6111 /* Force all queue use vector 0, 6112 * as IXGBE_VF_MAXMSIVECOTR = 1 6113 */ 6114 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx); 6115 intr_handle->intr_vec[q_idx] = vector_idx; 6116 if (vector_idx < base + intr_handle->nb_efd - 1) 6117 vector_idx++; 6118 } 6119 6120 /* As RX queue setting above show, all queues use the vector 0. 6121 * Set only the ITR value of IXGBE_MISC_VEC_ID. 6122 */ 6123 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID), 6124 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 6125 | IXGBE_EITR_CNT_WDIS); 6126 } 6127 6128 /** 6129 * Sets up the hardware to properly generate MSI-X interrupts 6130 * @hw 6131 * board private structure 6132 */ 6133 static void 6134 ixgbe_configure_msix(struct rte_eth_dev *dev) 6135 { 6136 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 6137 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 6138 struct ixgbe_hw *hw = 6139 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6140 uint32_t queue_id, base = IXGBE_MISC_VEC_ID; 6141 uint32_t vec = IXGBE_MISC_VEC_ID; 6142 uint32_t mask; 6143 uint32_t gpie; 6144 6145 /* won't configure msix register if no mapping is done 6146 * between intr vector and event fd 6147 * but if misx has been enabled already, need to configure 6148 * auto clean, auto mask and throttling. 6149 */ 6150 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 6151 if (!rte_intr_dp_is_en(intr_handle) && 6152 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT))) 6153 return; 6154 6155 if (rte_intr_allow_others(intr_handle)) 6156 vec = base = IXGBE_RX_VEC_START; 6157 6158 /* setup GPIE for MSI-x mode */ 6159 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 6160 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 6161 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME; 6162 /* auto clearing and auto setting corresponding bits in EIMS 6163 * when MSI-X interrupt is triggered 6164 */ 6165 if (hw->mac.type == ixgbe_mac_82598EB) { 6166 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 6167 } else { 6168 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 6169 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 6170 } 6171 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 6172 6173 /* Populate the IVAR table and set the ITR values to the 6174 * corresponding register. 6175 */ 6176 if (rte_intr_dp_is_en(intr_handle)) { 6177 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; 6178 queue_id++) { 6179 /* by default, 1:1 mapping */ 6180 ixgbe_set_ivar_map(hw, 0, queue_id, vec); 6181 intr_handle->intr_vec[queue_id] = vec; 6182 if (vec < base + intr_handle->nb_efd - 1) 6183 vec++; 6184 } 6185 6186 switch (hw->mac.type) { 6187 case ixgbe_mac_82598EB: 6188 ixgbe_set_ivar_map(hw, -1, 6189 IXGBE_IVAR_OTHER_CAUSES_INDEX, 6190 IXGBE_MISC_VEC_ID); 6191 break; 6192 case ixgbe_mac_82599EB: 6193 case ixgbe_mac_X540: 6194 case ixgbe_mac_X550: 6195 case ixgbe_mac_X550EM_x: 6196 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID); 6197 break; 6198 default: 6199 break; 6200 } 6201 } 6202 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID), 6203 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 6204 | IXGBE_EITR_CNT_WDIS); 6205 6206 /* set up to autoclear timer, and the vectors */ 6207 mask = IXGBE_EIMS_ENABLE_MASK; 6208 mask &= ~(IXGBE_EIMS_OTHER | 6209 IXGBE_EIMS_MAILBOX | 6210 IXGBE_EIMS_LSC); 6211 6212 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask); 6213 } 6214 6215 int 6216 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, 6217 uint16_t queue_idx, uint16_t tx_rate) 6218 { 6219 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6220 struct rte_eth_rxmode *rxmode; 6221 uint32_t rf_dec, rf_int; 6222 uint32_t bcnrc_val; 6223 uint16_t link_speed = dev->data->dev_link.link_speed; 6224 6225 if (queue_idx >= hw->mac.max_tx_queues) 6226 return -EINVAL; 6227 6228 if (tx_rate != 0) { 6229 /* Calculate the rate factor values to set */ 6230 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate; 6231 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate; 6232 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate; 6233 6234 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA; 6235 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) & 6236 IXGBE_RTTBCNRC_RF_INT_MASK_M); 6237 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK); 6238 } else { 6239 bcnrc_val = 0; 6240 } 6241 6242 rxmode = &dev->data->dev_conf.rxmode; 6243 /* 6244 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 6245 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise 6246 * set as 0x4. 6247 */ 6248 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) && 6249 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE)) 6250 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 6251 IXGBE_MMW_SIZE_JUMBO_FRAME); 6252 else 6253 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 6254 IXGBE_MMW_SIZE_DEFAULT); 6255 6256 /* Set RTTBCNRC of queue X */ 6257 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx); 6258 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 6259 IXGBE_WRITE_FLUSH(hw); 6260 6261 return 0; 6262 } 6263 6264 static int 6265 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 6266 __rte_unused uint32_t index, 6267 __rte_unused uint32_t pool) 6268 { 6269 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6270 int diag; 6271 6272 /* 6273 * On a 82599 VF, adding again the same MAC addr is not an idempotent 6274 * operation. Trap this case to avoid exhausting the [very limited] 6275 * set of PF resources used to store VF MAC addresses. 6276 */ 6277 if (memcmp(hw->mac.perm_addr, mac_addr, 6278 sizeof(struct rte_ether_addr)) == 0) 6279 return -1; 6280 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6281 if (diag != 0) 6282 PMD_DRV_LOG(ERR, "Unable to add MAC address " 6283 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d", 6284 mac_addr->addr_bytes[0], 6285 mac_addr->addr_bytes[1], 6286 mac_addr->addr_bytes[2], 6287 mac_addr->addr_bytes[3], 6288 mac_addr->addr_bytes[4], 6289 mac_addr->addr_bytes[5], 6290 diag); 6291 return diag; 6292 } 6293 6294 static void 6295 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index) 6296 { 6297 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6298 struct rte_ether_addr *perm_addr = 6299 (struct rte_ether_addr *)hw->mac.perm_addr; 6300 struct rte_ether_addr *mac_addr; 6301 uint32_t i; 6302 int diag; 6303 6304 /* 6305 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does 6306 * not support the deletion of a given MAC address. 6307 * Instead, it imposes to delete all MAC addresses, then to add again 6308 * all MAC addresses with the exception of the one to be deleted. 6309 */ 6310 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL); 6311 6312 /* 6313 * Add again all MAC addresses, with the exception of the deleted one 6314 * and of the permanent MAC address. 6315 */ 6316 for (i = 0, mac_addr = dev->data->mac_addrs; 6317 i < hw->mac.num_rar_entries; i++, mac_addr++) { 6318 /* Skip the deleted MAC address */ 6319 if (i == index) 6320 continue; 6321 /* Skip NULL MAC addresses */ 6322 if (rte_is_zero_ether_addr(mac_addr)) 6323 continue; 6324 /* Skip the permanent MAC address */ 6325 if (memcmp(perm_addr, mac_addr, 6326 sizeof(struct rte_ether_addr)) == 0) 6327 continue; 6328 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6329 if (diag != 0) 6330 PMD_DRV_LOG(ERR, 6331 "Adding again MAC address " 6332 "%02x:%02x:%02x:%02x:%02x:%02x failed " 6333 "diag=%d", 6334 mac_addr->addr_bytes[0], 6335 mac_addr->addr_bytes[1], 6336 mac_addr->addr_bytes[2], 6337 mac_addr->addr_bytes[3], 6338 mac_addr->addr_bytes[4], 6339 mac_addr->addr_bytes[5], 6340 diag); 6341 } 6342 } 6343 6344 static int 6345 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 6346 struct rte_ether_addr *addr) 6347 { 6348 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6349 6350 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0); 6351 6352 return 0; 6353 } 6354 6355 int 6356 ixgbe_syn_filter_set(struct rte_eth_dev *dev, 6357 struct rte_eth_syn_filter *filter, 6358 bool add) 6359 { 6360 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6361 struct ixgbe_filter_info *filter_info = 6362 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6363 uint32_t syn_info; 6364 uint32_t synqf; 6365 6366 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6367 return -EINVAL; 6368 6369 syn_info = filter_info->syn_info; 6370 6371 if (add) { 6372 if (syn_info & IXGBE_SYN_FILTER_ENABLE) 6373 return -EINVAL; 6374 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) & 6375 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE); 6376 6377 if (filter->hig_pri) 6378 synqf |= IXGBE_SYN_FILTER_SYNQFP; 6379 else 6380 synqf &= ~IXGBE_SYN_FILTER_SYNQFP; 6381 } else { 6382 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6383 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE)) 6384 return -ENOENT; 6385 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE); 6386 } 6387 6388 filter_info->syn_info = synqf; 6389 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 6390 IXGBE_WRITE_FLUSH(hw); 6391 return 0; 6392 } 6393 6394 static int 6395 ixgbe_syn_filter_get(struct rte_eth_dev *dev, 6396 struct rte_eth_syn_filter *filter) 6397 { 6398 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6399 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6400 6401 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 6402 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0; 6403 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1); 6404 return 0; 6405 } 6406 return -ENOENT; 6407 } 6408 6409 static int 6410 ixgbe_syn_filter_handle(struct rte_eth_dev *dev, 6411 enum rte_filter_op filter_op, 6412 void *arg) 6413 { 6414 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6415 int ret; 6416 6417 MAC_TYPE_FILTER_SUP(hw->mac.type); 6418 6419 if (filter_op == RTE_ETH_FILTER_NOP) 6420 return 0; 6421 6422 if (arg == NULL) { 6423 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u", 6424 filter_op); 6425 return -EINVAL; 6426 } 6427 6428 switch (filter_op) { 6429 case RTE_ETH_FILTER_ADD: 6430 ret = ixgbe_syn_filter_set(dev, 6431 (struct rte_eth_syn_filter *)arg, 6432 TRUE); 6433 break; 6434 case RTE_ETH_FILTER_DELETE: 6435 ret = ixgbe_syn_filter_set(dev, 6436 (struct rte_eth_syn_filter *)arg, 6437 FALSE); 6438 break; 6439 case RTE_ETH_FILTER_GET: 6440 ret = ixgbe_syn_filter_get(dev, 6441 (struct rte_eth_syn_filter *)arg); 6442 break; 6443 default: 6444 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op); 6445 ret = -EINVAL; 6446 break; 6447 } 6448 6449 return ret; 6450 } 6451 6452 6453 static inline enum ixgbe_5tuple_protocol 6454 convert_protocol_type(uint8_t protocol_value) 6455 { 6456 if (protocol_value == IPPROTO_TCP) 6457 return IXGBE_FILTER_PROTOCOL_TCP; 6458 else if (protocol_value == IPPROTO_UDP) 6459 return IXGBE_FILTER_PROTOCOL_UDP; 6460 else if (protocol_value == IPPROTO_SCTP) 6461 return IXGBE_FILTER_PROTOCOL_SCTP; 6462 else 6463 return IXGBE_FILTER_PROTOCOL_NONE; 6464 } 6465 6466 /* inject a 5-tuple filter to HW */ 6467 static inline void 6468 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev, 6469 struct ixgbe_5tuple_filter *filter) 6470 { 6471 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6472 int i; 6473 uint32_t ftqf, sdpqf; 6474 uint32_t l34timir = 0; 6475 uint8_t mask = 0xff; 6476 6477 i = filter->index; 6478 6479 sdpqf = (uint32_t)(filter->filter_info.dst_port << 6480 IXGBE_SDPQF_DSTPORT_SHIFT); 6481 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT); 6482 6483 ftqf = (uint32_t)(filter->filter_info.proto & 6484 IXGBE_FTQF_PROTOCOL_MASK); 6485 ftqf |= (uint32_t)((filter->filter_info.priority & 6486 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT); 6487 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */ 6488 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK; 6489 if (filter->filter_info.dst_ip_mask == 0) 6490 mask &= IXGBE_FTQF_DEST_ADDR_MASK; 6491 if (filter->filter_info.src_port_mask == 0) 6492 mask &= IXGBE_FTQF_SOURCE_PORT_MASK; 6493 if (filter->filter_info.dst_port_mask == 0) 6494 mask &= IXGBE_FTQF_DEST_PORT_MASK; 6495 if (filter->filter_info.proto_mask == 0) 6496 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK; 6497 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT; 6498 ftqf |= IXGBE_FTQF_POOL_MASK_EN; 6499 ftqf |= IXGBE_FTQF_QUEUE_ENABLE; 6500 6501 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip); 6502 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip); 6503 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf); 6504 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf); 6505 6506 l34timir |= IXGBE_L34T_IMIR_RESERVE; 6507 l34timir |= (uint32_t)(filter->queue << 6508 IXGBE_L34T_IMIR_QUEUE_SHIFT); 6509 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir); 6510 } 6511 6512 /* 6513 * add a 5tuple filter 6514 * 6515 * @param 6516 * dev: Pointer to struct rte_eth_dev. 6517 * index: the index the filter allocates. 6518 * filter: ponter to the filter that will be added. 6519 * rx_queue: the queue id the filter assigned to. 6520 * 6521 * @return 6522 * - On success, zero. 6523 * - On failure, a negative value. 6524 */ 6525 static int 6526 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 6527 struct ixgbe_5tuple_filter *filter) 6528 { 6529 struct ixgbe_filter_info *filter_info = 6530 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6531 int i, idx, shift; 6532 6533 /* 6534 * look for an unused 5tuple filter index, 6535 * and insert the filter to list. 6536 */ 6537 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) { 6538 idx = i / (sizeof(uint32_t) * NBBY); 6539 shift = i % (sizeof(uint32_t) * NBBY); 6540 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) { 6541 filter_info->fivetuple_mask[idx] |= 1 << shift; 6542 filter->index = i; 6543 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list, 6544 filter, 6545 entries); 6546 break; 6547 } 6548 } 6549 if (i >= IXGBE_MAX_FTQF_FILTERS) { 6550 PMD_DRV_LOG(ERR, "5tuple filters are full."); 6551 return -ENOSYS; 6552 } 6553 6554 ixgbe_inject_5tuple_filter(dev, filter); 6555 6556 return 0; 6557 } 6558 6559 /* 6560 * remove a 5tuple filter 6561 * 6562 * @param 6563 * dev: Pointer to struct rte_eth_dev. 6564 * filter: the pointer of the filter will be removed. 6565 */ 6566 static void 6567 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 6568 struct ixgbe_5tuple_filter *filter) 6569 { 6570 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6571 struct ixgbe_filter_info *filter_info = 6572 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6573 uint16_t index = filter->index; 6574 6575 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &= 6576 ~(1 << (index % (sizeof(uint32_t) * NBBY))); 6577 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries); 6578 rte_free(filter); 6579 6580 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0); 6581 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0); 6582 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0); 6583 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0); 6584 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0); 6585 } 6586 6587 static int 6588 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 6589 { 6590 struct ixgbe_hw *hw; 6591 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD; 6592 struct rte_eth_dev_data *dev_data = dev->data; 6593 6594 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6595 6596 if (mtu < RTE_ETHER_MIN_MTU || 6597 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN) 6598 return -EINVAL; 6599 6600 /* If device is started, refuse mtu that requires the support of 6601 * scattered packets when this feature has not been enabled before. 6602 */ 6603 if (dev_data->dev_started && !dev_data->scattered_rx && 6604 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE > 6605 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 6606 PMD_INIT_LOG(ERR, "Stop port first."); 6607 return -EINVAL; 6608 } 6609 6610 /* 6611 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU 6612 * request of the version 2.0 of the mailbox API. 6613 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0 6614 * of the mailbox API. 6615 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers 6616 * prior to 3.11.33 which contains the following change: 6617 * "ixgbe: Enable jumbo frames support w/ SR-IOV" 6618 */ 6619 ixgbevf_rlpml_set_vf(hw, max_frame); 6620 6621 /* update max frame size */ 6622 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame; 6623 return 0; 6624 } 6625 6626 static inline struct ixgbe_5tuple_filter * 6627 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list, 6628 struct ixgbe_5tuple_filter_info *key) 6629 { 6630 struct ixgbe_5tuple_filter *it; 6631 6632 TAILQ_FOREACH(it, filter_list, entries) { 6633 if (memcmp(key, &it->filter_info, 6634 sizeof(struct ixgbe_5tuple_filter_info)) == 0) { 6635 return it; 6636 } 6637 } 6638 return NULL; 6639 } 6640 6641 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/ 6642 static inline int 6643 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter, 6644 struct ixgbe_5tuple_filter_info *filter_info) 6645 { 6646 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM || 6647 filter->priority > IXGBE_5TUPLE_MAX_PRI || 6648 filter->priority < IXGBE_5TUPLE_MIN_PRI) 6649 return -EINVAL; 6650 6651 switch (filter->dst_ip_mask) { 6652 case UINT32_MAX: 6653 filter_info->dst_ip_mask = 0; 6654 filter_info->dst_ip = filter->dst_ip; 6655 break; 6656 case 0: 6657 filter_info->dst_ip_mask = 1; 6658 break; 6659 default: 6660 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 6661 return -EINVAL; 6662 } 6663 6664 switch (filter->src_ip_mask) { 6665 case UINT32_MAX: 6666 filter_info->src_ip_mask = 0; 6667 filter_info->src_ip = filter->src_ip; 6668 break; 6669 case 0: 6670 filter_info->src_ip_mask = 1; 6671 break; 6672 default: 6673 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 6674 return -EINVAL; 6675 } 6676 6677 switch (filter->dst_port_mask) { 6678 case UINT16_MAX: 6679 filter_info->dst_port_mask = 0; 6680 filter_info->dst_port = filter->dst_port; 6681 break; 6682 case 0: 6683 filter_info->dst_port_mask = 1; 6684 break; 6685 default: 6686 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 6687 return -EINVAL; 6688 } 6689 6690 switch (filter->src_port_mask) { 6691 case UINT16_MAX: 6692 filter_info->src_port_mask = 0; 6693 filter_info->src_port = filter->src_port; 6694 break; 6695 case 0: 6696 filter_info->src_port_mask = 1; 6697 break; 6698 default: 6699 PMD_DRV_LOG(ERR, "invalid src_port mask."); 6700 return -EINVAL; 6701 } 6702 6703 switch (filter->proto_mask) { 6704 case UINT8_MAX: 6705 filter_info->proto_mask = 0; 6706 filter_info->proto = 6707 convert_protocol_type(filter->proto); 6708 break; 6709 case 0: 6710 filter_info->proto_mask = 1; 6711 break; 6712 default: 6713 PMD_DRV_LOG(ERR, "invalid protocol mask."); 6714 return -EINVAL; 6715 } 6716 6717 filter_info->priority = (uint8_t)filter->priority; 6718 return 0; 6719 } 6720 6721 /* 6722 * add or delete a ntuple filter 6723 * 6724 * @param 6725 * dev: Pointer to struct rte_eth_dev. 6726 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6727 * add: if true, add filter, if false, remove filter 6728 * 6729 * @return 6730 * - On success, zero. 6731 * - On failure, a negative value. 6732 */ 6733 int 6734 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 6735 struct rte_eth_ntuple_filter *ntuple_filter, 6736 bool add) 6737 { 6738 struct ixgbe_filter_info *filter_info = 6739 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6740 struct ixgbe_5tuple_filter_info filter_5tuple; 6741 struct ixgbe_5tuple_filter *filter; 6742 int ret; 6743 6744 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6745 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6746 return -EINVAL; 6747 } 6748 6749 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6750 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6751 if (ret < 0) 6752 return ret; 6753 6754 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6755 &filter_5tuple); 6756 if (filter != NULL && add) { 6757 PMD_DRV_LOG(ERR, "filter exists."); 6758 return -EEXIST; 6759 } 6760 if (filter == NULL && !add) { 6761 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6762 return -ENOENT; 6763 } 6764 6765 if (add) { 6766 filter = rte_zmalloc("ixgbe_5tuple_filter", 6767 sizeof(struct ixgbe_5tuple_filter), 0); 6768 if (filter == NULL) 6769 return -ENOMEM; 6770 rte_memcpy(&filter->filter_info, 6771 &filter_5tuple, 6772 sizeof(struct ixgbe_5tuple_filter_info)); 6773 filter->queue = ntuple_filter->queue; 6774 ret = ixgbe_add_5tuple_filter(dev, filter); 6775 if (ret < 0) { 6776 rte_free(filter); 6777 return ret; 6778 } 6779 } else 6780 ixgbe_remove_5tuple_filter(dev, filter); 6781 6782 return 0; 6783 } 6784 6785 /* 6786 * get a ntuple filter 6787 * 6788 * @param 6789 * dev: Pointer to struct rte_eth_dev. 6790 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6791 * 6792 * @return 6793 * - On success, zero. 6794 * - On failure, a negative value. 6795 */ 6796 static int 6797 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev, 6798 struct rte_eth_ntuple_filter *ntuple_filter) 6799 { 6800 struct ixgbe_filter_info *filter_info = 6801 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6802 struct ixgbe_5tuple_filter_info filter_5tuple; 6803 struct ixgbe_5tuple_filter *filter; 6804 int ret; 6805 6806 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6807 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6808 return -EINVAL; 6809 } 6810 6811 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6812 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6813 if (ret < 0) 6814 return ret; 6815 6816 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6817 &filter_5tuple); 6818 if (filter == NULL) { 6819 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6820 return -ENOENT; 6821 } 6822 ntuple_filter->queue = filter->queue; 6823 return 0; 6824 } 6825 6826 /* 6827 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter. 6828 * @dev: pointer to rte_eth_dev structure 6829 * @filter_op:operation will be taken. 6830 * @arg: a pointer to specific structure corresponding to the filter_op 6831 * 6832 * @return 6833 * - On success, zero. 6834 * - On failure, a negative value. 6835 */ 6836 static int 6837 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev, 6838 enum rte_filter_op filter_op, 6839 void *arg) 6840 { 6841 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6842 int ret; 6843 6844 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type); 6845 6846 if (filter_op == RTE_ETH_FILTER_NOP) 6847 return 0; 6848 6849 if (arg == NULL) { 6850 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 6851 filter_op); 6852 return -EINVAL; 6853 } 6854 6855 switch (filter_op) { 6856 case RTE_ETH_FILTER_ADD: 6857 ret = ixgbe_add_del_ntuple_filter(dev, 6858 (struct rte_eth_ntuple_filter *)arg, 6859 TRUE); 6860 break; 6861 case RTE_ETH_FILTER_DELETE: 6862 ret = ixgbe_add_del_ntuple_filter(dev, 6863 (struct rte_eth_ntuple_filter *)arg, 6864 FALSE); 6865 break; 6866 case RTE_ETH_FILTER_GET: 6867 ret = ixgbe_get_ntuple_filter(dev, 6868 (struct rte_eth_ntuple_filter *)arg); 6869 break; 6870 default: 6871 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 6872 ret = -EINVAL; 6873 break; 6874 } 6875 return ret; 6876 } 6877 6878 int 6879 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 6880 struct rte_eth_ethertype_filter *filter, 6881 bool add) 6882 { 6883 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6884 struct ixgbe_filter_info *filter_info = 6885 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6886 uint32_t etqf = 0; 6887 uint32_t etqs = 0; 6888 int ret; 6889 struct ixgbe_ethertype_filter ethertype_filter; 6890 6891 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6892 return -EINVAL; 6893 6894 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 || 6895 filter->ether_type == RTE_ETHER_TYPE_IPV6) { 6896 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in" 6897 " ethertype filter.", filter->ether_type); 6898 return -EINVAL; 6899 } 6900 6901 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) { 6902 PMD_DRV_LOG(ERR, "mac compare is unsupported."); 6903 return -EINVAL; 6904 } 6905 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) { 6906 PMD_DRV_LOG(ERR, "drop option is unsupported."); 6907 return -EINVAL; 6908 } 6909 6910 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6911 if (ret >= 0 && add) { 6912 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.", 6913 filter->ether_type); 6914 return -EEXIST; 6915 } 6916 if (ret < 0 && !add) { 6917 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6918 filter->ether_type); 6919 return -ENOENT; 6920 } 6921 6922 if (add) { 6923 etqf = IXGBE_ETQF_FILTER_EN; 6924 etqf |= (uint32_t)filter->ether_type; 6925 etqs |= (uint32_t)((filter->queue << 6926 IXGBE_ETQS_RX_QUEUE_SHIFT) & 6927 IXGBE_ETQS_RX_QUEUE); 6928 etqs |= IXGBE_ETQS_QUEUE_EN; 6929 6930 ethertype_filter.ethertype = filter->ether_type; 6931 ethertype_filter.etqf = etqf; 6932 ethertype_filter.etqs = etqs; 6933 ethertype_filter.conf = FALSE; 6934 ret = ixgbe_ethertype_filter_insert(filter_info, 6935 ðertype_filter); 6936 if (ret < 0) { 6937 PMD_DRV_LOG(ERR, "ethertype filters are full."); 6938 return -ENOSPC; 6939 } 6940 } else { 6941 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret); 6942 if (ret < 0) 6943 return -ENOSYS; 6944 } 6945 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf); 6946 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs); 6947 IXGBE_WRITE_FLUSH(hw); 6948 6949 return 0; 6950 } 6951 6952 static int 6953 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, 6954 struct rte_eth_ethertype_filter *filter) 6955 { 6956 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6957 struct ixgbe_filter_info *filter_info = 6958 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6959 uint32_t etqf, etqs; 6960 int ret; 6961 6962 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6963 if (ret < 0) { 6964 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6965 filter->ether_type); 6966 return -ENOENT; 6967 } 6968 6969 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret)); 6970 if (etqf & IXGBE_ETQF_FILTER_EN) { 6971 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret)); 6972 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE; 6973 filter->flags = 0; 6974 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> 6975 IXGBE_ETQS_RX_QUEUE_SHIFT; 6976 return 0; 6977 } 6978 return -ENOENT; 6979 } 6980 6981 /* 6982 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter. 6983 * @dev: pointer to rte_eth_dev structure 6984 * @filter_op:operation will be taken. 6985 * @arg: a pointer to specific structure corresponding to the filter_op 6986 */ 6987 static int 6988 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev, 6989 enum rte_filter_op filter_op, 6990 void *arg) 6991 { 6992 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6993 int ret; 6994 6995 MAC_TYPE_FILTER_SUP(hw->mac.type); 6996 6997 if (filter_op == RTE_ETH_FILTER_NOP) 6998 return 0; 6999 7000 if (arg == NULL) { 7001 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 7002 filter_op); 7003 return -EINVAL; 7004 } 7005 7006 switch (filter_op) { 7007 case RTE_ETH_FILTER_ADD: 7008 ret = ixgbe_add_del_ethertype_filter(dev, 7009 (struct rte_eth_ethertype_filter *)arg, 7010 TRUE); 7011 break; 7012 case RTE_ETH_FILTER_DELETE: 7013 ret = ixgbe_add_del_ethertype_filter(dev, 7014 (struct rte_eth_ethertype_filter *)arg, 7015 FALSE); 7016 break; 7017 case RTE_ETH_FILTER_GET: 7018 ret = ixgbe_get_ethertype_filter(dev, 7019 (struct rte_eth_ethertype_filter *)arg); 7020 break; 7021 default: 7022 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 7023 ret = -EINVAL; 7024 break; 7025 } 7026 return ret; 7027 } 7028 7029 static int 7030 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 7031 enum rte_filter_type filter_type, 7032 enum rte_filter_op filter_op, 7033 void *arg) 7034 { 7035 int ret = 0; 7036 7037 switch (filter_type) { 7038 case RTE_ETH_FILTER_NTUPLE: 7039 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg); 7040 break; 7041 case RTE_ETH_FILTER_ETHERTYPE: 7042 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg); 7043 break; 7044 case RTE_ETH_FILTER_SYN: 7045 ret = ixgbe_syn_filter_handle(dev, filter_op, arg); 7046 break; 7047 case RTE_ETH_FILTER_FDIR: 7048 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg); 7049 break; 7050 case RTE_ETH_FILTER_L2_TUNNEL: 7051 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg); 7052 break; 7053 case RTE_ETH_FILTER_GENERIC: 7054 if (filter_op != RTE_ETH_FILTER_GET) 7055 return -EINVAL; 7056 *(const void **)arg = &ixgbe_flow_ops; 7057 break; 7058 default: 7059 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 7060 filter_type); 7061 ret = -EINVAL; 7062 break; 7063 } 7064 7065 return ret; 7066 } 7067 7068 static u8 * 7069 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw, 7070 u8 **mc_addr_ptr, u32 *vmdq) 7071 { 7072 u8 *mc_addr; 7073 7074 *vmdq = 0; 7075 mc_addr = *mc_addr_ptr; 7076 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr)); 7077 return mc_addr; 7078 } 7079 7080 static int 7081 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 7082 struct rte_ether_addr *mc_addr_set, 7083 uint32_t nb_mc_addr) 7084 { 7085 struct ixgbe_hw *hw; 7086 u8 *mc_addr_list; 7087 7088 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7089 mc_addr_list = (u8 *)mc_addr_set; 7090 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr, 7091 ixgbe_dev_addr_list_itr, TRUE); 7092 } 7093 7094 static uint64_t 7095 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev) 7096 { 7097 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7098 uint64_t systime_cycles; 7099 7100 switch (hw->mac.type) { 7101 case ixgbe_mac_X550: 7102 case ixgbe_mac_X550EM_x: 7103 case ixgbe_mac_X550EM_a: 7104 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */ 7105 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 7106 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 7107 * NSEC_PER_SEC; 7108 break; 7109 default: 7110 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 7111 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 7112 << 32; 7113 } 7114 7115 return systime_cycles; 7116 } 7117 7118 static uint64_t 7119 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) 7120 { 7121 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7122 uint64_t rx_tstamp_cycles; 7123 7124 switch (hw->mac.type) { 7125 case ixgbe_mac_X550: 7126 case ixgbe_mac_X550EM_x: 7127 case ixgbe_mac_X550EM_a: 7128 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 7129 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 7130 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 7131 * NSEC_PER_SEC; 7132 break; 7133 default: 7134 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 7135 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 7136 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 7137 << 32; 7138 } 7139 7140 return rx_tstamp_cycles; 7141 } 7142 7143 static uint64_t 7144 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 7145 { 7146 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7147 uint64_t tx_tstamp_cycles; 7148 7149 switch (hw->mac.type) { 7150 case ixgbe_mac_X550: 7151 case ixgbe_mac_X550EM_x: 7152 case ixgbe_mac_X550EM_a: 7153 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 7154 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 7155 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 7156 * NSEC_PER_SEC; 7157 break; 7158 default: 7159 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 7160 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 7161 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 7162 << 32; 7163 } 7164 7165 return tx_tstamp_cycles; 7166 } 7167 7168 static void 7169 ixgbe_start_timecounters(struct rte_eth_dev *dev) 7170 { 7171 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7172 struct ixgbe_adapter *adapter = dev->data->dev_private; 7173 struct rte_eth_link link; 7174 uint32_t incval = 0; 7175 uint32_t shift = 0; 7176 7177 /* Get current link speed. */ 7178 ixgbe_dev_link_update(dev, 1); 7179 rte_eth_linkstatus_get(dev, &link); 7180 7181 switch (link.link_speed) { 7182 case ETH_SPEED_NUM_100M: 7183 incval = IXGBE_INCVAL_100; 7184 shift = IXGBE_INCVAL_SHIFT_100; 7185 break; 7186 case ETH_SPEED_NUM_1G: 7187 incval = IXGBE_INCVAL_1GB; 7188 shift = IXGBE_INCVAL_SHIFT_1GB; 7189 break; 7190 case ETH_SPEED_NUM_10G: 7191 default: 7192 incval = IXGBE_INCVAL_10GB; 7193 shift = IXGBE_INCVAL_SHIFT_10GB; 7194 break; 7195 } 7196 7197 switch (hw->mac.type) { 7198 case ixgbe_mac_X550: 7199 case ixgbe_mac_X550EM_x: 7200 case ixgbe_mac_X550EM_a: 7201 /* Independent of link speed. */ 7202 incval = 1; 7203 /* Cycles read will be interpreted as ns. */ 7204 shift = 0; 7205 /* Fall-through */ 7206 case ixgbe_mac_X540: 7207 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval); 7208 break; 7209 case ixgbe_mac_82599EB: 7210 incval >>= IXGBE_INCVAL_SHIFT_82599; 7211 shift -= IXGBE_INCVAL_SHIFT_82599; 7212 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 7213 (1 << IXGBE_INCPER_SHIFT_82599) | incval); 7214 break; 7215 default: 7216 /* Not supported. */ 7217 return; 7218 } 7219 7220 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 7221 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 7222 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 7223 7224 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 7225 adapter->systime_tc.cc_shift = shift; 7226 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; 7227 7228 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 7229 adapter->rx_tstamp_tc.cc_shift = shift; 7230 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 7231 7232 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 7233 adapter->tx_tstamp_tc.cc_shift = shift; 7234 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 7235 } 7236 7237 static int 7238 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 7239 { 7240 struct ixgbe_adapter *adapter = dev->data->dev_private; 7241 7242 adapter->systime_tc.nsec += delta; 7243 adapter->rx_tstamp_tc.nsec += delta; 7244 adapter->tx_tstamp_tc.nsec += delta; 7245 7246 return 0; 7247 } 7248 7249 static int 7250 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 7251 { 7252 uint64_t ns; 7253 struct ixgbe_adapter *adapter = dev->data->dev_private; 7254 7255 ns = rte_timespec_to_ns(ts); 7256 /* Set the timecounters to a new value. */ 7257 adapter->systime_tc.nsec = ns; 7258 adapter->rx_tstamp_tc.nsec = ns; 7259 adapter->tx_tstamp_tc.nsec = ns; 7260 7261 return 0; 7262 } 7263 7264 static int 7265 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 7266 { 7267 uint64_t ns, systime_cycles; 7268 struct ixgbe_adapter *adapter = dev->data->dev_private; 7269 7270 systime_cycles = ixgbe_read_systime_cyclecounter(dev); 7271 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 7272 *ts = rte_ns_to_timespec(ns); 7273 7274 return 0; 7275 } 7276 7277 static int 7278 ixgbe_timesync_enable(struct rte_eth_dev *dev) 7279 { 7280 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7281 uint32_t tsync_ctl; 7282 uint32_t tsauxc; 7283 7284 /* Stop the timesync system time. */ 7285 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0); 7286 /* Reset the timesync system time value. */ 7287 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0); 7288 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0); 7289 7290 /* Enable system time for platforms where it isn't on by default. */ 7291 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC); 7292 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME; 7293 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc); 7294 7295 ixgbe_start_timecounters(dev); 7296 7297 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7298 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 7299 (RTE_ETHER_TYPE_1588 | 7300 IXGBE_ETQF_FILTER_EN | 7301 IXGBE_ETQF_1588)); 7302 7303 /* Enable timestamping of received PTP packets. */ 7304 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7305 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED; 7306 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7307 7308 /* Enable timestamping of transmitted PTP packets. */ 7309 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7310 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED; 7311 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7312 7313 IXGBE_WRITE_FLUSH(hw); 7314 7315 return 0; 7316 } 7317 7318 static int 7319 ixgbe_timesync_disable(struct rte_eth_dev *dev) 7320 { 7321 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7322 uint32_t tsync_ctl; 7323 7324 /* Disable timestamping of transmitted PTP packets. */ 7325 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7326 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED; 7327 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7328 7329 /* Disable timestamping of received PTP packets. */ 7330 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7331 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED; 7332 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7333 7334 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7335 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0); 7336 7337 /* Stop incrementating the System Time registers. */ 7338 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0); 7339 7340 return 0; 7341 } 7342 7343 static int 7344 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 7345 struct timespec *timestamp, 7346 uint32_t flags __rte_unused) 7347 { 7348 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7349 struct ixgbe_adapter *adapter = dev->data->dev_private; 7350 uint32_t tsync_rxctl; 7351 uint64_t rx_tstamp_cycles; 7352 uint64_t ns; 7353 7354 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7355 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0) 7356 return -EINVAL; 7357 7358 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev); 7359 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 7360 *timestamp = rte_ns_to_timespec(ns); 7361 7362 return 0; 7363 } 7364 7365 static int 7366 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 7367 struct timespec *timestamp) 7368 { 7369 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7370 struct ixgbe_adapter *adapter = dev->data->dev_private; 7371 uint32_t tsync_txctl; 7372 uint64_t tx_tstamp_cycles; 7373 uint64_t ns; 7374 7375 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7376 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0) 7377 return -EINVAL; 7378 7379 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev); 7380 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 7381 *timestamp = rte_ns_to_timespec(ns); 7382 7383 return 0; 7384 } 7385 7386 static int 7387 ixgbe_get_reg_length(struct rte_eth_dev *dev) 7388 { 7389 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7390 int count = 0; 7391 int g_ind = 0; 7392 const struct reg_info *reg_group; 7393 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7394 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7395 7396 while ((reg_group = reg_set[g_ind++])) 7397 count += ixgbe_regs_group_count(reg_group); 7398 7399 return count; 7400 } 7401 7402 static int 7403 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused) 7404 { 7405 int count = 0; 7406 int g_ind = 0; 7407 const struct reg_info *reg_group; 7408 7409 while ((reg_group = ixgbevf_regs[g_ind++])) 7410 count += ixgbe_regs_group_count(reg_group); 7411 7412 return count; 7413 } 7414 7415 static int 7416 ixgbe_get_regs(struct rte_eth_dev *dev, 7417 struct rte_dev_reg_info *regs) 7418 { 7419 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7420 uint32_t *data = regs->data; 7421 int g_ind = 0; 7422 int count = 0; 7423 const struct reg_info *reg_group; 7424 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7425 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7426 7427 if (data == NULL) { 7428 regs->length = ixgbe_get_reg_length(dev); 7429 regs->width = sizeof(uint32_t); 7430 return 0; 7431 } 7432 7433 /* Support only full register dump */ 7434 if ((regs->length == 0) || 7435 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) { 7436 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7437 hw->device_id; 7438 while ((reg_group = reg_set[g_ind++])) 7439 count += ixgbe_read_regs_group(dev, &data[count], 7440 reg_group); 7441 return 0; 7442 } 7443 7444 return -ENOTSUP; 7445 } 7446 7447 static int 7448 ixgbevf_get_regs(struct rte_eth_dev *dev, 7449 struct rte_dev_reg_info *regs) 7450 { 7451 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7452 uint32_t *data = regs->data; 7453 int g_ind = 0; 7454 int count = 0; 7455 const struct reg_info *reg_group; 7456 7457 if (data == NULL) { 7458 regs->length = ixgbevf_get_reg_length(dev); 7459 regs->width = sizeof(uint32_t); 7460 return 0; 7461 } 7462 7463 /* Support only full register dump */ 7464 if ((regs->length == 0) || 7465 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) { 7466 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7467 hw->device_id; 7468 while ((reg_group = ixgbevf_regs[g_ind++])) 7469 count += ixgbe_read_regs_group(dev, &data[count], 7470 reg_group); 7471 return 0; 7472 } 7473 7474 return -ENOTSUP; 7475 } 7476 7477 static int 7478 ixgbe_get_eeprom_length(struct rte_eth_dev *dev) 7479 { 7480 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7481 7482 /* Return unit is byte count */ 7483 return hw->eeprom.word_size * 2; 7484 } 7485 7486 static int 7487 ixgbe_get_eeprom(struct rte_eth_dev *dev, 7488 struct rte_dev_eeprom_info *in_eeprom) 7489 { 7490 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7491 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7492 uint16_t *data = in_eeprom->data; 7493 int first, length; 7494 7495 first = in_eeprom->offset >> 1; 7496 length = in_eeprom->length >> 1; 7497 if ((first > hw->eeprom.word_size) || 7498 ((first + length) > hw->eeprom.word_size)) 7499 return -EINVAL; 7500 7501 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7502 7503 return eeprom->ops.read_buffer(hw, first, length, data); 7504 } 7505 7506 static int 7507 ixgbe_set_eeprom(struct rte_eth_dev *dev, 7508 struct rte_dev_eeprom_info *in_eeprom) 7509 { 7510 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7511 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7512 uint16_t *data = in_eeprom->data; 7513 int first, length; 7514 7515 first = in_eeprom->offset >> 1; 7516 length = in_eeprom->length >> 1; 7517 if ((first > hw->eeprom.word_size) || 7518 ((first + length) > hw->eeprom.word_size)) 7519 return -EINVAL; 7520 7521 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7522 7523 return eeprom->ops.write_buffer(hw, first, length, data); 7524 } 7525 7526 static int 7527 ixgbe_get_module_info(struct rte_eth_dev *dev, 7528 struct rte_eth_dev_module_info *modinfo) 7529 { 7530 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7531 uint32_t status; 7532 uint8_t sff8472_rev, addr_mode; 7533 bool page_swap = false; 7534 7535 /* Check whether we support SFF-8472 or not */ 7536 status = hw->phy.ops.read_i2c_eeprom(hw, 7537 IXGBE_SFF_SFF_8472_COMP, 7538 &sff8472_rev); 7539 if (status != 0) 7540 return -EIO; 7541 7542 /* addressing mode is not supported */ 7543 status = hw->phy.ops.read_i2c_eeprom(hw, 7544 IXGBE_SFF_SFF_8472_SWAP, 7545 &addr_mode); 7546 if (status != 0) 7547 return -EIO; 7548 7549 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 7550 PMD_DRV_LOG(ERR, 7551 "Address change required to access page 0xA2, " 7552 "but not supported. Please report the module " 7553 "type to the driver maintainers."); 7554 page_swap = true; 7555 } 7556 7557 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) { 7558 /* We have a SFP, but it does not support SFF-8472 */ 7559 modinfo->type = RTE_ETH_MODULE_SFF_8079; 7560 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 7561 } else { 7562 /* We have a SFP which supports a revision of SFF-8472. */ 7563 modinfo->type = RTE_ETH_MODULE_SFF_8472; 7564 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 7565 } 7566 7567 return 0; 7568 } 7569 7570 static int 7571 ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 7572 struct rte_dev_eeprom_info *info) 7573 { 7574 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7575 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 7576 uint8_t databyte = 0xFF; 7577 uint8_t *data = info->data; 7578 uint32_t i = 0; 7579 7580 if (info->length == 0) 7581 return -EINVAL; 7582 7583 for (i = info->offset; i < info->offset + info->length; i++) { 7584 if (i < RTE_ETH_MODULE_SFF_8079_LEN) 7585 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 7586 else 7587 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 7588 7589 if (status != 0) 7590 return -EIO; 7591 7592 data[i - info->offset] = databyte; 7593 } 7594 7595 return 0; 7596 } 7597 7598 uint16_t 7599 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) { 7600 switch (mac_type) { 7601 case ixgbe_mac_X550: 7602 case ixgbe_mac_X550EM_x: 7603 case ixgbe_mac_X550EM_a: 7604 return ETH_RSS_RETA_SIZE_512; 7605 case ixgbe_mac_X550_vf: 7606 case ixgbe_mac_X550EM_x_vf: 7607 case ixgbe_mac_X550EM_a_vf: 7608 return ETH_RSS_RETA_SIZE_64; 7609 case ixgbe_mac_X540_vf: 7610 case ixgbe_mac_82599_vf: 7611 return 0; 7612 default: 7613 return ETH_RSS_RETA_SIZE_128; 7614 } 7615 } 7616 7617 uint32_t 7618 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) { 7619 switch (mac_type) { 7620 case ixgbe_mac_X550: 7621 case ixgbe_mac_X550EM_x: 7622 case ixgbe_mac_X550EM_a: 7623 if (reta_idx < ETH_RSS_RETA_SIZE_128) 7624 return IXGBE_RETA(reta_idx >> 2); 7625 else 7626 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2); 7627 case ixgbe_mac_X550_vf: 7628 case ixgbe_mac_X550EM_x_vf: 7629 case ixgbe_mac_X550EM_a_vf: 7630 return IXGBE_VFRETA(reta_idx >> 2); 7631 default: 7632 return IXGBE_RETA(reta_idx >> 2); 7633 } 7634 } 7635 7636 uint32_t 7637 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) { 7638 switch (mac_type) { 7639 case ixgbe_mac_X550_vf: 7640 case ixgbe_mac_X550EM_x_vf: 7641 case ixgbe_mac_X550EM_a_vf: 7642 return IXGBE_VFMRQC; 7643 default: 7644 return IXGBE_MRQC; 7645 } 7646 } 7647 7648 uint32_t 7649 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) { 7650 switch (mac_type) { 7651 case ixgbe_mac_X550_vf: 7652 case ixgbe_mac_X550EM_x_vf: 7653 case ixgbe_mac_X550EM_a_vf: 7654 return IXGBE_VFRSSRK(i); 7655 default: 7656 return IXGBE_RSSRK(i); 7657 } 7658 } 7659 7660 bool 7661 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) { 7662 switch (mac_type) { 7663 case ixgbe_mac_82599_vf: 7664 case ixgbe_mac_X540_vf: 7665 return 0; 7666 default: 7667 return 1; 7668 } 7669 } 7670 7671 static int 7672 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 7673 struct rte_eth_dcb_info *dcb_info) 7674 { 7675 struct ixgbe_dcb_config *dcb_config = 7676 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 7677 struct ixgbe_dcb_tc_config *tc; 7678 struct rte_eth_dcb_tc_queue_mapping *tc_queue; 7679 uint8_t nb_tcs; 7680 uint8_t i, j; 7681 7682 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG) 7683 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs; 7684 else 7685 dcb_info->nb_tcs = 1; 7686 7687 tc_queue = &dcb_info->tc_queue; 7688 nb_tcs = dcb_info->nb_tcs; 7689 7690 if (dcb_config->vt_mode) { /* vt is enabled*/ 7691 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf = 7692 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf; 7693 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7694 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i]; 7695 if (RTE_ETH_DEV_SRIOV(dev).active > 0) { 7696 for (j = 0; j < nb_tcs; j++) { 7697 tc_queue->tc_rxq[0][j].base = j; 7698 tc_queue->tc_rxq[0][j].nb_queue = 1; 7699 tc_queue->tc_txq[0][j].base = j; 7700 tc_queue->tc_txq[0][j].nb_queue = 1; 7701 } 7702 } else { 7703 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) { 7704 for (j = 0; j < nb_tcs; j++) { 7705 tc_queue->tc_rxq[i][j].base = 7706 i * nb_tcs + j; 7707 tc_queue->tc_rxq[i][j].nb_queue = 1; 7708 tc_queue->tc_txq[i][j].base = 7709 i * nb_tcs + j; 7710 tc_queue->tc_txq[i][j].nb_queue = 1; 7711 } 7712 } 7713 } 7714 } else { /* vt is disabled*/ 7715 struct rte_eth_dcb_rx_conf *rx_conf = 7716 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 7717 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7718 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i]; 7719 if (dcb_info->nb_tcs == ETH_4_TCS) { 7720 for (i = 0; i < dcb_info->nb_tcs; i++) { 7721 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32; 7722 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7723 } 7724 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7725 dcb_info->tc_queue.tc_txq[0][1].base = 64; 7726 dcb_info->tc_queue.tc_txq[0][2].base = 96; 7727 dcb_info->tc_queue.tc_txq[0][3].base = 112; 7728 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64; 7729 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7730 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7731 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7732 } else if (dcb_info->nb_tcs == ETH_8_TCS) { 7733 for (i = 0; i < dcb_info->nb_tcs; i++) { 7734 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16; 7735 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7736 } 7737 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7738 dcb_info->tc_queue.tc_txq[0][1].base = 32; 7739 dcb_info->tc_queue.tc_txq[0][2].base = 64; 7740 dcb_info->tc_queue.tc_txq[0][3].base = 80; 7741 dcb_info->tc_queue.tc_txq[0][4].base = 96; 7742 dcb_info->tc_queue.tc_txq[0][5].base = 104; 7743 dcb_info->tc_queue.tc_txq[0][6].base = 112; 7744 dcb_info->tc_queue.tc_txq[0][7].base = 120; 7745 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32; 7746 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7747 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7748 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7749 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8; 7750 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8; 7751 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8; 7752 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8; 7753 } 7754 } 7755 for (i = 0; i < dcb_info->nb_tcs; i++) { 7756 tc = &dcb_config->tc_config[i]; 7757 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent; 7758 } 7759 return 0; 7760 } 7761 7762 /* Update e-tag ether type */ 7763 static int 7764 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw, 7765 uint16_t ether_type) 7766 { 7767 uint32_t etag_etype; 7768 7769 if (hw->mac.type != ixgbe_mac_X550 && 7770 hw->mac.type != ixgbe_mac_X550EM_x && 7771 hw->mac.type != ixgbe_mac_X550EM_a) { 7772 return -ENOTSUP; 7773 } 7774 7775 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7776 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK; 7777 etag_etype |= ether_type; 7778 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7779 IXGBE_WRITE_FLUSH(hw); 7780 7781 return 0; 7782 } 7783 7784 /* Config l2 tunnel ether type */ 7785 static int 7786 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev, 7787 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7788 { 7789 int ret = 0; 7790 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7791 struct ixgbe_l2_tn_info *l2_tn_info = 7792 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7793 7794 if (l2_tunnel == NULL) 7795 return -EINVAL; 7796 7797 switch (l2_tunnel->l2_tunnel_type) { 7798 case RTE_L2_TUNNEL_TYPE_E_TAG: 7799 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type; 7800 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type); 7801 break; 7802 default: 7803 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7804 ret = -EINVAL; 7805 break; 7806 } 7807 7808 return ret; 7809 } 7810 7811 /* Enable e-tag tunnel */ 7812 static int 7813 ixgbe_e_tag_enable(struct ixgbe_hw *hw) 7814 { 7815 uint32_t etag_etype; 7816 7817 if (hw->mac.type != ixgbe_mac_X550 && 7818 hw->mac.type != ixgbe_mac_X550EM_x && 7819 hw->mac.type != ixgbe_mac_X550EM_a) { 7820 return -ENOTSUP; 7821 } 7822 7823 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7824 etag_etype |= IXGBE_ETAG_ETYPE_VALID; 7825 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7826 IXGBE_WRITE_FLUSH(hw); 7827 7828 return 0; 7829 } 7830 7831 /* Enable l2 tunnel */ 7832 static int 7833 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev, 7834 enum rte_eth_tunnel_type l2_tunnel_type) 7835 { 7836 int ret = 0; 7837 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7838 struct ixgbe_l2_tn_info *l2_tn_info = 7839 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7840 7841 switch (l2_tunnel_type) { 7842 case RTE_L2_TUNNEL_TYPE_E_TAG: 7843 l2_tn_info->e_tag_en = TRUE; 7844 ret = ixgbe_e_tag_enable(hw); 7845 break; 7846 default: 7847 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7848 ret = -EINVAL; 7849 break; 7850 } 7851 7852 return ret; 7853 } 7854 7855 /* Disable e-tag tunnel */ 7856 static int 7857 ixgbe_e_tag_disable(struct ixgbe_hw *hw) 7858 { 7859 uint32_t etag_etype; 7860 7861 if (hw->mac.type != ixgbe_mac_X550 && 7862 hw->mac.type != ixgbe_mac_X550EM_x && 7863 hw->mac.type != ixgbe_mac_X550EM_a) { 7864 return -ENOTSUP; 7865 } 7866 7867 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7868 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID; 7869 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7870 IXGBE_WRITE_FLUSH(hw); 7871 7872 return 0; 7873 } 7874 7875 /* Disable l2 tunnel */ 7876 static int 7877 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev, 7878 enum rte_eth_tunnel_type l2_tunnel_type) 7879 { 7880 int ret = 0; 7881 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7882 struct ixgbe_l2_tn_info *l2_tn_info = 7883 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7884 7885 switch (l2_tunnel_type) { 7886 case RTE_L2_TUNNEL_TYPE_E_TAG: 7887 l2_tn_info->e_tag_en = FALSE; 7888 ret = ixgbe_e_tag_disable(hw); 7889 break; 7890 default: 7891 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7892 ret = -EINVAL; 7893 break; 7894 } 7895 7896 return ret; 7897 } 7898 7899 static int 7900 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev, 7901 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7902 { 7903 int ret = 0; 7904 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7905 uint32_t i, rar_entries; 7906 uint32_t rar_low, rar_high; 7907 7908 if (hw->mac.type != ixgbe_mac_X550 && 7909 hw->mac.type != ixgbe_mac_X550EM_x && 7910 hw->mac.type != ixgbe_mac_X550EM_a) { 7911 return -ENOTSUP; 7912 } 7913 7914 rar_entries = ixgbe_get_num_rx_addrs(hw); 7915 7916 for (i = 1; i < rar_entries; i++) { 7917 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7918 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 7919 if ((rar_high & IXGBE_RAH_AV) && 7920 (rar_high & IXGBE_RAH_ADTYPE) && 7921 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) == 7922 l2_tunnel->tunnel_id)) { 7923 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 7924 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 7925 7926 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL); 7927 7928 return ret; 7929 } 7930 } 7931 7932 return ret; 7933 } 7934 7935 static int 7936 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev, 7937 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7938 { 7939 int ret = 0; 7940 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7941 uint32_t i, rar_entries; 7942 uint32_t rar_low, rar_high; 7943 7944 if (hw->mac.type != ixgbe_mac_X550 && 7945 hw->mac.type != ixgbe_mac_X550EM_x && 7946 hw->mac.type != ixgbe_mac_X550EM_a) { 7947 return -ENOTSUP; 7948 } 7949 7950 /* One entry for one tunnel. Try to remove potential existing entry. */ 7951 ixgbe_e_tag_filter_del(dev, l2_tunnel); 7952 7953 rar_entries = ixgbe_get_num_rx_addrs(hw); 7954 7955 for (i = 1; i < rar_entries; i++) { 7956 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7957 if (rar_high & IXGBE_RAH_AV) { 7958 continue; 7959 } else { 7960 ixgbe_set_vmdq(hw, i, l2_tunnel->pool); 7961 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE; 7962 rar_low = l2_tunnel->tunnel_id; 7963 7964 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low); 7965 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high); 7966 7967 return ret; 7968 } 7969 } 7970 7971 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full." 7972 " Please remove a rule before adding a new one."); 7973 return -EINVAL; 7974 } 7975 7976 static inline struct ixgbe_l2_tn_filter * 7977 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info, 7978 struct ixgbe_l2_tn_key *key) 7979 { 7980 int ret; 7981 7982 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key); 7983 if (ret < 0) 7984 return NULL; 7985 7986 return l2_tn_info->hash_map[ret]; 7987 } 7988 7989 static inline int 7990 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7991 struct ixgbe_l2_tn_filter *l2_tn_filter) 7992 { 7993 int ret; 7994 7995 ret = rte_hash_add_key(l2_tn_info->hash_handle, 7996 &l2_tn_filter->key); 7997 7998 if (ret < 0) { 7999 PMD_DRV_LOG(ERR, 8000 "Failed to insert L2 tunnel filter" 8001 " to hash table %d!", 8002 ret); 8003 return ret; 8004 } 8005 8006 l2_tn_info->hash_map[ret] = l2_tn_filter; 8007 8008 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 8009 8010 return 0; 8011 } 8012 8013 static inline int 8014 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 8015 struct ixgbe_l2_tn_key *key) 8016 { 8017 int ret; 8018 struct ixgbe_l2_tn_filter *l2_tn_filter; 8019 8020 ret = rte_hash_del_key(l2_tn_info->hash_handle, key); 8021 8022 if (ret < 0) { 8023 PMD_DRV_LOG(ERR, 8024 "No such L2 tunnel filter to delete %d!", 8025 ret); 8026 return ret; 8027 } 8028 8029 l2_tn_filter = l2_tn_info->hash_map[ret]; 8030 l2_tn_info->hash_map[ret] = NULL; 8031 8032 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 8033 rte_free(l2_tn_filter); 8034 8035 return 0; 8036 } 8037 8038 /* Add l2 tunnel filter */ 8039 int 8040 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 8041 struct rte_eth_l2_tunnel_conf *l2_tunnel, 8042 bool restore) 8043 { 8044 int ret; 8045 struct ixgbe_l2_tn_info *l2_tn_info = 8046 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8047 struct ixgbe_l2_tn_key key; 8048 struct ixgbe_l2_tn_filter *node; 8049 8050 if (!restore) { 8051 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 8052 key.tn_id = l2_tunnel->tunnel_id; 8053 8054 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key); 8055 8056 if (node) { 8057 PMD_DRV_LOG(ERR, 8058 "The L2 tunnel filter already exists!"); 8059 return -EINVAL; 8060 } 8061 8062 node = rte_zmalloc("ixgbe_l2_tn", 8063 sizeof(struct ixgbe_l2_tn_filter), 8064 0); 8065 if (!node) 8066 return -ENOMEM; 8067 8068 rte_memcpy(&node->key, 8069 &key, 8070 sizeof(struct ixgbe_l2_tn_key)); 8071 node->pool = l2_tunnel->pool; 8072 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node); 8073 if (ret < 0) { 8074 rte_free(node); 8075 return ret; 8076 } 8077 } 8078 8079 switch (l2_tunnel->l2_tunnel_type) { 8080 case RTE_L2_TUNNEL_TYPE_E_TAG: 8081 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel); 8082 break; 8083 default: 8084 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8085 ret = -EINVAL; 8086 break; 8087 } 8088 8089 if ((!restore) && (ret < 0)) 8090 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 8091 8092 return ret; 8093 } 8094 8095 /* Delete l2 tunnel filter */ 8096 int 8097 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 8098 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8099 { 8100 int ret; 8101 struct ixgbe_l2_tn_info *l2_tn_info = 8102 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8103 struct ixgbe_l2_tn_key key; 8104 8105 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 8106 key.tn_id = l2_tunnel->tunnel_id; 8107 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 8108 if (ret < 0) 8109 return ret; 8110 8111 switch (l2_tunnel->l2_tunnel_type) { 8112 case RTE_L2_TUNNEL_TYPE_E_TAG: 8113 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel); 8114 break; 8115 default: 8116 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8117 ret = -EINVAL; 8118 break; 8119 } 8120 8121 return ret; 8122 } 8123 8124 /** 8125 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter. 8126 * @dev: pointer to rte_eth_dev structure 8127 * @filter_op:operation will be taken. 8128 * @arg: a pointer to specific structure corresponding to the filter_op 8129 */ 8130 static int 8131 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev, 8132 enum rte_filter_op filter_op, 8133 void *arg) 8134 { 8135 int ret; 8136 8137 if (filter_op == RTE_ETH_FILTER_NOP) 8138 return 0; 8139 8140 if (arg == NULL) { 8141 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 8142 filter_op); 8143 return -EINVAL; 8144 } 8145 8146 switch (filter_op) { 8147 case RTE_ETH_FILTER_ADD: 8148 ret = ixgbe_dev_l2_tunnel_filter_add 8149 (dev, 8150 (struct rte_eth_l2_tunnel_conf *)arg, 8151 FALSE); 8152 break; 8153 case RTE_ETH_FILTER_DELETE: 8154 ret = ixgbe_dev_l2_tunnel_filter_del 8155 (dev, 8156 (struct rte_eth_l2_tunnel_conf *)arg); 8157 break; 8158 default: 8159 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 8160 ret = -EINVAL; 8161 break; 8162 } 8163 return ret; 8164 } 8165 8166 static int 8167 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en) 8168 { 8169 int ret = 0; 8170 uint32_t ctrl; 8171 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8172 8173 if (hw->mac.type != ixgbe_mac_X550 && 8174 hw->mac.type != ixgbe_mac_X550EM_x && 8175 hw->mac.type != ixgbe_mac_X550EM_a) { 8176 return -ENOTSUP; 8177 } 8178 8179 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 8180 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 8181 if (en) 8182 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG; 8183 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 8184 8185 return ret; 8186 } 8187 8188 /* Enable l2 tunnel forwarding */ 8189 static int 8190 ixgbe_dev_l2_tunnel_forwarding_enable 8191 (struct rte_eth_dev *dev, 8192 enum rte_eth_tunnel_type l2_tunnel_type) 8193 { 8194 struct ixgbe_l2_tn_info *l2_tn_info = 8195 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8196 int ret = 0; 8197 8198 switch (l2_tunnel_type) { 8199 case RTE_L2_TUNNEL_TYPE_E_TAG: 8200 l2_tn_info->e_tag_fwd_en = TRUE; 8201 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1); 8202 break; 8203 default: 8204 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8205 ret = -EINVAL; 8206 break; 8207 } 8208 8209 return ret; 8210 } 8211 8212 /* Disable l2 tunnel forwarding */ 8213 static int 8214 ixgbe_dev_l2_tunnel_forwarding_disable 8215 (struct rte_eth_dev *dev, 8216 enum rte_eth_tunnel_type l2_tunnel_type) 8217 { 8218 struct ixgbe_l2_tn_info *l2_tn_info = 8219 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8220 int ret = 0; 8221 8222 switch (l2_tunnel_type) { 8223 case RTE_L2_TUNNEL_TYPE_E_TAG: 8224 l2_tn_info->e_tag_fwd_en = FALSE; 8225 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0); 8226 break; 8227 default: 8228 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8229 ret = -EINVAL; 8230 break; 8231 } 8232 8233 return ret; 8234 } 8235 8236 static int 8237 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev, 8238 struct rte_eth_l2_tunnel_conf *l2_tunnel, 8239 bool en) 8240 { 8241 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 8242 int ret = 0; 8243 uint32_t vmtir, vmvir; 8244 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8245 8246 if (l2_tunnel->vf_id >= pci_dev->max_vfs) { 8247 PMD_DRV_LOG(ERR, 8248 "VF id %u should be less than %u", 8249 l2_tunnel->vf_id, 8250 pci_dev->max_vfs); 8251 return -EINVAL; 8252 } 8253 8254 if (hw->mac.type != ixgbe_mac_X550 && 8255 hw->mac.type != ixgbe_mac_X550EM_x && 8256 hw->mac.type != ixgbe_mac_X550EM_a) { 8257 return -ENOTSUP; 8258 } 8259 8260 if (en) 8261 vmtir = l2_tunnel->tunnel_id; 8262 else 8263 vmtir = 0; 8264 8265 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir); 8266 8267 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id)); 8268 vmvir &= ~IXGBE_VMVIR_TAGA_MASK; 8269 if (en) 8270 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT; 8271 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir); 8272 8273 return ret; 8274 } 8275 8276 /* Enable l2 tunnel tag insertion */ 8277 static int 8278 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev, 8279 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8280 { 8281 int ret = 0; 8282 8283 switch (l2_tunnel->l2_tunnel_type) { 8284 case RTE_L2_TUNNEL_TYPE_E_TAG: 8285 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1); 8286 break; 8287 default: 8288 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8289 ret = -EINVAL; 8290 break; 8291 } 8292 8293 return ret; 8294 } 8295 8296 /* Disable l2 tunnel tag insertion */ 8297 static int 8298 ixgbe_dev_l2_tunnel_insertion_disable 8299 (struct rte_eth_dev *dev, 8300 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8301 { 8302 int ret = 0; 8303 8304 switch (l2_tunnel->l2_tunnel_type) { 8305 case RTE_L2_TUNNEL_TYPE_E_TAG: 8306 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0); 8307 break; 8308 default: 8309 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8310 ret = -EINVAL; 8311 break; 8312 } 8313 8314 return ret; 8315 } 8316 8317 static int 8318 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev, 8319 bool en) 8320 { 8321 int ret = 0; 8322 uint32_t qde; 8323 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8324 8325 if (hw->mac.type != ixgbe_mac_X550 && 8326 hw->mac.type != ixgbe_mac_X550EM_x && 8327 hw->mac.type != ixgbe_mac_X550EM_a) { 8328 return -ENOTSUP; 8329 } 8330 8331 qde = IXGBE_READ_REG(hw, IXGBE_QDE); 8332 if (en) 8333 qde |= IXGBE_QDE_STRIP_TAG; 8334 else 8335 qde &= ~IXGBE_QDE_STRIP_TAG; 8336 qde &= ~IXGBE_QDE_READ; 8337 qde |= IXGBE_QDE_WRITE; 8338 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde); 8339 8340 return ret; 8341 } 8342 8343 /* Enable l2 tunnel tag stripping */ 8344 static int 8345 ixgbe_dev_l2_tunnel_stripping_enable 8346 (struct rte_eth_dev *dev, 8347 enum rte_eth_tunnel_type l2_tunnel_type) 8348 { 8349 int ret = 0; 8350 8351 switch (l2_tunnel_type) { 8352 case RTE_L2_TUNNEL_TYPE_E_TAG: 8353 ret = ixgbe_e_tag_stripping_en_dis(dev, 1); 8354 break; 8355 default: 8356 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8357 ret = -EINVAL; 8358 break; 8359 } 8360 8361 return ret; 8362 } 8363 8364 /* Disable l2 tunnel tag stripping */ 8365 static int 8366 ixgbe_dev_l2_tunnel_stripping_disable 8367 (struct rte_eth_dev *dev, 8368 enum rte_eth_tunnel_type l2_tunnel_type) 8369 { 8370 int ret = 0; 8371 8372 switch (l2_tunnel_type) { 8373 case RTE_L2_TUNNEL_TYPE_E_TAG: 8374 ret = ixgbe_e_tag_stripping_en_dis(dev, 0); 8375 break; 8376 default: 8377 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8378 ret = -EINVAL; 8379 break; 8380 } 8381 8382 return ret; 8383 } 8384 8385 /* Enable/disable l2 tunnel offload functions */ 8386 static int 8387 ixgbe_dev_l2_tunnel_offload_set 8388 (struct rte_eth_dev *dev, 8389 struct rte_eth_l2_tunnel_conf *l2_tunnel, 8390 uint32_t mask, 8391 uint8_t en) 8392 { 8393 int ret = 0; 8394 8395 if (l2_tunnel == NULL) 8396 return -EINVAL; 8397 8398 ret = -EINVAL; 8399 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) { 8400 if (en) 8401 ret = ixgbe_dev_l2_tunnel_enable( 8402 dev, 8403 l2_tunnel->l2_tunnel_type); 8404 else 8405 ret = ixgbe_dev_l2_tunnel_disable( 8406 dev, 8407 l2_tunnel->l2_tunnel_type); 8408 } 8409 8410 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) { 8411 if (en) 8412 ret = ixgbe_dev_l2_tunnel_insertion_enable( 8413 dev, 8414 l2_tunnel); 8415 else 8416 ret = ixgbe_dev_l2_tunnel_insertion_disable( 8417 dev, 8418 l2_tunnel); 8419 } 8420 8421 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) { 8422 if (en) 8423 ret = ixgbe_dev_l2_tunnel_stripping_enable( 8424 dev, 8425 l2_tunnel->l2_tunnel_type); 8426 else 8427 ret = ixgbe_dev_l2_tunnel_stripping_disable( 8428 dev, 8429 l2_tunnel->l2_tunnel_type); 8430 } 8431 8432 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) { 8433 if (en) 8434 ret = ixgbe_dev_l2_tunnel_forwarding_enable( 8435 dev, 8436 l2_tunnel->l2_tunnel_type); 8437 else 8438 ret = ixgbe_dev_l2_tunnel_forwarding_disable( 8439 dev, 8440 l2_tunnel->l2_tunnel_type); 8441 } 8442 8443 return ret; 8444 } 8445 8446 static int 8447 ixgbe_update_vxlan_port(struct ixgbe_hw *hw, 8448 uint16_t port) 8449 { 8450 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port); 8451 IXGBE_WRITE_FLUSH(hw); 8452 8453 return 0; 8454 } 8455 8456 /* There's only one register for VxLAN UDP port. 8457 * So, we cannot add several ports. Will update it. 8458 */ 8459 static int 8460 ixgbe_add_vxlan_port(struct ixgbe_hw *hw, 8461 uint16_t port) 8462 { 8463 if (port == 0) { 8464 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 8465 return -EINVAL; 8466 } 8467 8468 return ixgbe_update_vxlan_port(hw, port); 8469 } 8470 8471 /* We cannot delete the VxLAN port. For there's a register for VxLAN 8472 * UDP port, it must have a value. 8473 * So, will reset it to the original value 0. 8474 */ 8475 static int 8476 ixgbe_del_vxlan_port(struct ixgbe_hw *hw, 8477 uint16_t port) 8478 { 8479 uint16_t cur_port; 8480 8481 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL); 8482 8483 if (cur_port != port) { 8484 PMD_DRV_LOG(ERR, "Port %u does not exist.", port); 8485 return -EINVAL; 8486 } 8487 8488 return ixgbe_update_vxlan_port(hw, 0); 8489 } 8490 8491 /* Add UDP tunneling port */ 8492 static int 8493 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 8494 struct rte_eth_udp_tunnel *udp_tunnel) 8495 { 8496 int ret = 0; 8497 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8498 8499 if (hw->mac.type != ixgbe_mac_X550 && 8500 hw->mac.type != ixgbe_mac_X550EM_x && 8501 hw->mac.type != ixgbe_mac_X550EM_a) { 8502 return -ENOTSUP; 8503 } 8504 8505 if (udp_tunnel == NULL) 8506 return -EINVAL; 8507 8508 switch (udp_tunnel->prot_type) { 8509 case RTE_TUNNEL_TYPE_VXLAN: 8510 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port); 8511 break; 8512 8513 case RTE_TUNNEL_TYPE_GENEVE: 8514 case RTE_TUNNEL_TYPE_TEREDO: 8515 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8516 ret = -EINVAL; 8517 break; 8518 8519 default: 8520 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8521 ret = -EINVAL; 8522 break; 8523 } 8524 8525 return ret; 8526 } 8527 8528 /* Remove UDP tunneling port */ 8529 static int 8530 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 8531 struct rte_eth_udp_tunnel *udp_tunnel) 8532 { 8533 int ret = 0; 8534 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8535 8536 if (hw->mac.type != ixgbe_mac_X550 && 8537 hw->mac.type != ixgbe_mac_X550EM_x && 8538 hw->mac.type != ixgbe_mac_X550EM_a) { 8539 return -ENOTSUP; 8540 } 8541 8542 if (udp_tunnel == NULL) 8543 return -EINVAL; 8544 8545 switch (udp_tunnel->prot_type) { 8546 case RTE_TUNNEL_TYPE_VXLAN: 8547 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port); 8548 break; 8549 case RTE_TUNNEL_TYPE_GENEVE: 8550 case RTE_TUNNEL_TYPE_TEREDO: 8551 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8552 ret = -EINVAL; 8553 break; 8554 default: 8555 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8556 ret = -EINVAL; 8557 break; 8558 } 8559 8560 return ret; 8561 } 8562 8563 static int 8564 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev) 8565 { 8566 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8567 int ret; 8568 8569 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) { 8570 case IXGBE_SUCCESS: 8571 ret = 0; 8572 break; 8573 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 8574 ret = -ENOTSUP; 8575 break; 8576 default: 8577 ret = -EAGAIN; 8578 break; 8579 } 8580 8581 return ret; 8582 } 8583 8584 static int 8585 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev) 8586 { 8587 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8588 int ret; 8589 8590 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) { 8591 case IXGBE_SUCCESS: 8592 ret = 0; 8593 break; 8594 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 8595 ret = -ENOTSUP; 8596 break; 8597 default: 8598 ret = -EAGAIN; 8599 break; 8600 } 8601 8602 return ret; 8603 } 8604 8605 static int 8606 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev) 8607 { 8608 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8609 int ret; 8610 int mode = IXGBEVF_XCAST_MODE_ALLMULTI; 8611 8612 switch (hw->mac.ops.update_xcast_mode(hw, mode)) { 8613 case IXGBE_SUCCESS: 8614 ret = 0; 8615 break; 8616 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 8617 ret = -ENOTSUP; 8618 break; 8619 default: 8620 ret = -EAGAIN; 8621 break; 8622 } 8623 8624 return ret; 8625 } 8626 8627 static int 8628 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev) 8629 { 8630 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8631 int ret; 8632 8633 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) { 8634 case IXGBE_SUCCESS: 8635 ret = 0; 8636 break; 8637 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 8638 ret = -ENOTSUP; 8639 break; 8640 default: 8641 ret = -EAGAIN; 8642 break; 8643 } 8644 8645 return ret; 8646 } 8647 8648 static void ixgbevf_mbx_process(struct rte_eth_dev *dev) 8649 { 8650 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8651 u32 in_msg = 0; 8652 8653 /* peek the message first */ 8654 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM); 8655 8656 /* PF reset VF event */ 8657 if (in_msg == IXGBE_PF_CONTROL_MSG) { 8658 /* dummy mbx read to ack pf */ 8659 if (ixgbe_read_mbx(hw, &in_msg, 1, 0)) 8660 return; 8661 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 8662 NULL); 8663 } 8664 } 8665 8666 static int 8667 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev) 8668 { 8669 uint32_t eicr; 8670 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8671 struct ixgbe_interrupt *intr = 8672 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8673 ixgbevf_intr_disable(dev); 8674 8675 /* read-on-clear nic registers here */ 8676 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR); 8677 intr->flags = 0; 8678 8679 /* only one misc vector supported - mailbox */ 8680 eicr &= IXGBE_VTEICR_MASK; 8681 if (eicr == IXGBE_MISC_VEC_ID) 8682 intr->flags |= IXGBE_FLAG_MAILBOX; 8683 8684 return 0; 8685 } 8686 8687 static int 8688 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev) 8689 { 8690 struct ixgbe_interrupt *intr = 8691 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8692 8693 if (intr->flags & IXGBE_FLAG_MAILBOX) { 8694 ixgbevf_mbx_process(dev); 8695 intr->flags &= ~IXGBE_FLAG_MAILBOX; 8696 } 8697 8698 ixgbevf_intr_enable(dev); 8699 8700 return 0; 8701 } 8702 8703 static void 8704 ixgbevf_dev_interrupt_handler(void *param) 8705 { 8706 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 8707 8708 ixgbevf_dev_interrupt_get_status(dev); 8709 ixgbevf_dev_interrupt_action(dev); 8710 } 8711 8712 /** 8713 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path 8714 * @hw: pointer to hardware structure 8715 * 8716 * Stops the transmit data path and waits for the HW to internally empty 8717 * the Tx security block 8718 **/ 8719 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw) 8720 { 8721 #define IXGBE_MAX_SECTX_POLL 40 8722 8723 int i; 8724 int sectxreg; 8725 8726 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8727 sectxreg |= IXGBE_SECTXCTRL_TX_DIS; 8728 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8729 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) { 8730 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT); 8731 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY) 8732 break; 8733 /* Use interrupt-safe sleep just in case */ 8734 usec_delay(1000); 8735 } 8736 8737 /* For informational purposes only */ 8738 if (i >= IXGBE_MAX_SECTX_POLL) 8739 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security " 8740 "path fully disabled. Continuing with init."); 8741 8742 return IXGBE_SUCCESS; 8743 } 8744 8745 /** 8746 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path 8747 * @hw: pointer to hardware structure 8748 * 8749 * Enables the transmit data path. 8750 **/ 8751 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw) 8752 { 8753 uint32_t sectxreg; 8754 8755 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8756 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS; 8757 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8758 IXGBE_WRITE_FLUSH(hw); 8759 8760 return IXGBE_SUCCESS; 8761 } 8762 8763 /* restore n-tuple filter */ 8764 static inline void 8765 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev) 8766 { 8767 struct ixgbe_filter_info *filter_info = 8768 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8769 struct ixgbe_5tuple_filter *node; 8770 8771 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) { 8772 ixgbe_inject_5tuple_filter(dev, node); 8773 } 8774 } 8775 8776 /* restore ethernet type filter */ 8777 static inline void 8778 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev) 8779 { 8780 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8781 struct ixgbe_filter_info *filter_info = 8782 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8783 int i; 8784 8785 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8786 if (filter_info->ethertype_mask & (1 << i)) { 8787 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 8788 filter_info->ethertype_filters[i].etqf); 8789 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 8790 filter_info->ethertype_filters[i].etqs); 8791 IXGBE_WRITE_FLUSH(hw); 8792 } 8793 } 8794 } 8795 8796 /* restore SYN filter */ 8797 static inline void 8798 ixgbe_syn_filter_restore(struct rte_eth_dev *dev) 8799 { 8800 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8801 struct ixgbe_filter_info *filter_info = 8802 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8803 uint32_t synqf; 8804 8805 synqf = filter_info->syn_info; 8806 8807 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 8808 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 8809 IXGBE_WRITE_FLUSH(hw); 8810 } 8811 } 8812 8813 /* restore L2 tunnel filter */ 8814 static inline void 8815 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev) 8816 { 8817 struct ixgbe_l2_tn_info *l2_tn_info = 8818 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8819 struct ixgbe_l2_tn_filter *node; 8820 struct rte_eth_l2_tunnel_conf l2_tn_conf; 8821 8822 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) { 8823 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type; 8824 l2_tn_conf.tunnel_id = node->key.tn_id; 8825 l2_tn_conf.pool = node->pool; 8826 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE); 8827 } 8828 } 8829 8830 /* restore rss filter */ 8831 static inline void 8832 ixgbe_rss_filter_restore(struct rte_eth_dev *dev) 8833 { 8834 struct ixgbe_filter_info *filter_info = 8835 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8836 8837 if (filter_info->rss_info.conf.queue_num) 8838 ixgbe_config_rss_filter(dev, 8839 &filter_info->rss_info, TRUE); 8840 } 8841 8842 static int 8843 ixgbe_filter_restore(struct rte_eth_dev *dev) 8844 { 8845 ixgbe_ntuple_filter_restore(dev); 8846 ixgbe_ethertype_filter_restore(dev); 8847 ixgbe_syn_filter_restore(dev); 8848 ixgbe_fdir_filter_restore(dev); 8849 ixgbe_l2_tn_filter_restore(dev); 8850 ixgbe_rss_filter_restore(dev); 8851 8852 return 0; 8853 } 8854 8855 static void 8856 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev) 8857 { 8858 struct ixgbe_l2_tn_info *l2_tn_info = 8859 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8860 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8861 8862 if (l2_tn_info->e_tag_en) 8863 (void)ixgbe_e_tag_enable(hw); 8864 8865 if (l2_tn_info->e_tag_fwd_en) 8866 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1); 8867 8868 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type); 8869 } 8870 8871 /* remove all the n-tuple filters */ 8872 void 8873 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev) 8874 { 8875 struct ixgbe_filter_info *filter_info = 8876 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8877 struct ixgbe_5tuple_filter *p_5tuple; 8878 8879 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) 8880 ixgbe_remove_5tuple_filter(dev, p_5tuple); 8881 } 8882 8883 /* remove all the ether type filters */ 8884 void 8885 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev) 8886 { 8887 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8888 struct ixgbe_filter_info *filter_info = 8889 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8890 int i; 8891 8892 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8893 if (filter_info->ethertype_mask & (1 << i) && 8894 !filter_info->ethertype_filters[i].conf) { 8895 (void)ixgbe_ethertype_filter_remove(filter_info, 8896 (uint8_t)i); 8897 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0); 8898 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0); 8899 IXGBE_WRITE_FLUSH(hw); 8900 } 8901 } 8902 } 8903 8904 /* remove the SYN filter */ 8905 void 8906 ixgbe_clear_syn_filter(struct rte_eth_dev *dev) 8907 { 8908 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8909 struct ixgbe_filter_info *filter_info = 8910 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8911 8912 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) { 8913 filter_info->syn_info = 0; 8914 8915 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0); 8916 IXGBE_WRITE_FLUSH(hw); 8917 } 8918 } 8919 8920 /* remove all the L2 tunnel filters */ 8921 int 8922 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev) 8923 { 8924 struct ixgbe_l2_tn_info *l2_tn_info = 8925 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8926 struct ixgbe_l2_tn_filter *l2_tn_filter; 8927 struct rte_eth_l2_tunnel_conf l2_tn_conf; 8928 int ret = 0; 8929 8930 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 8931 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type; 8932 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id; 8933 l2_tn_conf.pool = l2_tn_filter->pool; 8934 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf); 8935 if (ret < 0) 8936 return ret; 8937 } 8938 8939 return 0; 8940 } 8941 8942 void 8943 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev, 8944 struct ixgbe_macsec_setting *macsec_setting) 8945 { 8946 struct ixgbe_macsec_setting *macsec = 8947 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 8948 8949 macsec->offload_en = macsec_setting->offload_en; 8950 macsec->encrypt_en = macsec_setting->encrypt_en; 8951 macsec->replayprotect_en = macsec_setting->replayprotect_en; 8952 } 8953 8954 void 8955 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev) 8956 { 8957 struct ixgbe_macsec_setting *macsec = 8958 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 8959 8960 macsec->offload_en = 0; 8961 macsec->encrypt_en = 0; 8962 macsec->replayprotect_en = 0; 8963 } 8964 8965 void 8966 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev, 8967 struct ixgbe_macsec_setting *macsec_setting) 8968 { 8969 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8970 uint32_t ctrl; 8971 uint8_t en = macsec_setting->encrypt_en; 8972 uint8_t rp = macsec_setting->replayprotect_en; 8973 8974 /** 8975 * Workaround: 8976 * As no ixgbe_disable_sec_rx_path equivalent is 8977 * implemented for tx in the base code, and we are 8978 * not allowed to modify the base code in DPDK, so 8979 * just call the hand-written one directly for now. 8980 * The hardware support has been checked by 8981 * ixgbe_disable_sec_rx_path(). 8982 */ 8983 ixgbe_disable_sec_tx_path_generic(hw); 8984 8985 /* Enable Ethernet CRC (required by MACsec offload) */ 8986 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0); 8987 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP; 8988 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl); 8989 8990 /* Enable the TX and RX crypto engines */ 8991 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8992 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS; 8993 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl); 8994 8995 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 8996 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS; 8997 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl); 8998 8999 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 9000 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK; 9001 ctrl |= 0x3; 9002 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl); 9003 9004 /* Enable SA lookup */ 9005 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL); 9006 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK; 9007 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT : 9008 IXGBE_LSECTXCTRL_AUTH; 9009 ctrl |= IXGBE_LSECTXCTRL_AISCI; 9010 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK; 9011 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK; 9012 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl); 9013 9014 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL); 9015 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK; 9016 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT; 9017 ctrl &= ~IXGBE_LSECRXCTRL_PLSH; 9018 if (rp) 9019 ctrl |= IXGBE_LSECRXCTRL_RP; 9020 else 9021 ctrl &= ~IXGBE_LSECRXCTRL_RP; 9022 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl); 9023 9024 /* Start the data paths */ 9025 ixgbe_enable_sec_rx_path(hw); 9026 /** 9027 * Workaround: 9028 * As no ixgbe_enable_sec_rx_path equivalent is 9029 * implemented for tx in the base code, and we are 9030 * not allowed to modify the base code in DPDK, so 9031 * just call the hand-written one directly for now. 9032 */ 9033 ixgbe_enable_sec_tx_path_generic(hw); 9034 } 9035 9036 void 9037 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev) 9038 { 9039 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 9040 uint32_t ctrl; 9041 9042 /** 9043 * Workaround: 9044 * As no ixgbe_disable_sec_rx_path equivalent is 9045 * implemented for tx in the base code, and we are 9046 * not allowed to modify the base code in DPDK, so 9047 * just call the hand-written one directly for now. 9048 * The hardware support has been checked by 9049 * ixgbe_disable_sec_rx_path(). 9050 */ 9051 ixgbe_disable_sec_tx_path_generic(hw); 9052 9053 /* Disable the TX and RX crypto engines */ 9054 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 9055 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS; 9056 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl); 9057 9058 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 9059 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS; 9060 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl); 9061 9062 /* Disable SA lookup */ 9063 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL); 9064 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK; 9065 ctrl |= IXGBE_LSECTXCTRL_DISABLE; 9066 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl); 9067 9068 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL); 9069 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK; 9070 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT; 9071 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl); 9072 9073 /* Start the data paths */ 9074 ixgbe_enable_sec_rx_path(hw); 9075 /** 9076 * Workaround: 9077 * As no ixgbe_enable_sec_rx_path equivalent is 9078 * implemented for tx in the base code, and we are 9079 * not allowed to modify the base code in DPDK, so 9080 * just call the hand-written one directly for now. 9081 */ 9082 ixgbe_enable_sec_tx_path_generic(hw); 9083 } 9084 9085 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd); 9086 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map); 9087 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 9088 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd); 9089 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map); 9090 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci"); 9091 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf, 9092 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>"); 9093 9094 RTE_INIT(ixgbe_init_log) 9095 { 9096 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init"); 9097 if (ixgbe_logtype_init >= 0) 9098 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE); 9099 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver"); 9100 if (ixgbe_logtype_driver >= 0) 9101 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE); 9102 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX 9103 ixgbe_logtype_rx = rte_log_register("pmd.net.ixgbe.rx"); 9104 if (ixgbe_logtype_rx >= 0) 9105 rte_log_set_level(ixgbe_logtype_rx, RTE_LOG_DEBUG); 9106 #endif 9107 9108 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX 9109 ixgbe_logtype_tx = rte_log_register("pmd.net.ixgbe.tx"); 9110 if (ixgbe_logtype_tx >= 0) 9111 rte_log_set_level(ixgbe_logtype_tx, RTE_LOG_DEBUG); 9112 #endif 9113 9114 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE 9115 ixgbe_logtype_tx_free = rte_log_register("pmd.net.ixgbe.tx_free"); 9116 if (ixgbe_logtype_tx_free >= 0) 9117 rte_log_set_level(ixgbe_logtype_tx_free, RTE_LOG_DEBUG); 9118 #endif 9119 } 9120