1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <inttypes.h> 13 #include <netinet/in.h> 14 #include <rte_byteorder.h> 15 #include <rte_common.h> 16 #include <rte_cycles.h> 17 18 #include <rte_interrupts.h> 19 #include <rte_log.h> 20 #include <rte_debug.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_branch_prediction.h> 24 #include <rte_memory.h> 25 #include <rte_eal.h> 26 #include <rte_alarm.h> 27 #include <rte_ether.h> 28 #include <rte_ethdev_driver.h> 29 #include <rte_ethdev_pci.h> 30 #include <rte_malloc.h> 31 #include <rte_random.h> 32 #include <rte_dev.h> 33 #include <rte_hash_crc.h> 34 #ifdef RTE_LIBRTE_SECURITY 35 #include <rte_security_driver.h> 36 #endif 37 38 #include "ixgbe_logs.h" 39 #include "base/ixgbe_api.h" 40 #include "base/ixgbe_vf.h" 41 #include "base/ixgbe_common.h" 42 #include "ixgbe_ethdev.h" 43 #include "ixgbe_bypass.h" 44 #include "ixgbe_rxtx.h" 45 #include "base/ixgbe_type.h" 46 #include "base/ixgbe_phy.h" 47 #include "ixgbe_regs.h" 48 49 /* 50 * High threshold controlling when to start sending XOFF frames. Must be at 51 * least 8 bytes less than receive packet buffer size. This value is in units 52 * of 1024 bytes. 53 */ 54 #define IXGBE_FC_HI 0x80 55 56 /* 57 * Low threshold controlling when to start sending XON frames. This value is 58 * in units of 1024 bytes. 59 */ 60 #define IXGBE_FC_LO 0x40 61 62 /* Timer value included in XOFF frames. */ 63 #define IXGBE_FC_PAUSE 0x680 64 65 /*Default value of Max Rx Queue*/ 66 #define IXGBE_MAX_RX_QUEUE_NUM 128 67 68 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */ 69 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */ 70 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */ 71 72 #define IXGBE_MMW_SIZE_DEFAULT 0x4 73 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14 74 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */ 75 76 /* 77 * Default values for RX/TX configuration 78 */ 79 #define IXGBE_DEFAULT_RX_FREE_THRESH 32 80 #define IXGBE_DEFAULT_RX_PTHRESH 8 81 #define IXGBE_DEFAULT_RX_HTHRESH 8 82 #define IXGBE_DEFAULT_RX_WTHRESH 0 83 84 #define IXGBE_DEFAULT_TX_FREE_THRESH 32 85 #define IXGBE_DEFAULT_TX_PTHRESH 32 86 #define IXGBE_DEFAULT_TX_HTHRESH 0 87 #define IXGBE_DEFAULT_TX_WTHRESH 0 88 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32 89 90 /* Bit shift and mask */ 91 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2) 92 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t) 93 #define IXGBE_8_BIT_WIDTH CHAR_BIT 94 #define IXGBE_8_BIT_MASK UINT8_MAX 95 96 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */ 97 98 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0])) 99 100 /* Additional timesync values. */ 101 #define NSEC_PER_SEC 1000000000L 102 #define IXGBE_INCVAL_10GB 0x66666666 103 #define IXGBE_INCVAL_1GB 0x40000000 104 #define IXGBE_INCVAL_100 0x50000000 105 #define IXGBE_INCVAL_SHIFT_10GB 28 106 #define IXGBE_INCVAL_SHIFT_1GB 24 107 #define IXGBE_INCVAL_SHIFT_100 21 108 #define IXGBE_INCVAL_SHIFT_82599 7 109 #define IXGBE_INCPER_SHIFT_82599 24 110 111 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL 112 113 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000 114 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000 115 #define IXGBE_ETAG_ETYPE 0x00005084 116 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff 117 #define IXGBE_ETAG_ETYPE_VALID 0x80000000 118 #define IXGBE_RAH_ADTYPE 0x40000000 119 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff 120 #define IXGBE_VMVIR_TAGA_MASK 0x18000000 121 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000 122 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */ 123 #define IXGBE_QDE_STRIP_TAG 0x00000004 124 #define IXGBE_VTEICR_MASK 0x07 125 126 #define IXGBE_EXVET_VET_EXT_SHIFT 16 127 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000 128 129 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 130 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev); 131 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev); 132 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev); 133 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev); 134 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev); 135 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev); 136 static int ixgbe_dev_configure(struct rte_eth_dev *dev); 137 static int ixgbe_dev_start(struct rte_eth_dev *dev); 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev); 139 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev); 140 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev); 141 static void ixgbe_dev_close(struct rte_eth_dev *dev); 142 static int ixgbe_dev_reset(struct rte_eth_dev *dev); 143 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 144 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 145 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 146 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 147 static int ixgbe_dev_link_update(struct rte_eth_dev *dev, 148 int wait_to_complete); 149 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev, 150 struct rte_eth_stats *stats); 151 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev, 152 struct rte_eth_xstat *xstats, unsigned n); 153 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, 154 struct rte_eth_xstat *xstats, unsigned n); 155 static int 156 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 157 uint64_t *values, unsigned int n); 158 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev); 159 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev); 160 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 161 struct rte_eth_xstat_name *xstats_names, 162 unsigned int size); 163 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev, 164 struct rte_eth_xstat_name *xstats_names, unsigned limit); 165 static int ixgbe_dev_xstats_get_names_by_id( 166 struct rte_eth_dev *dev, 167 struct rte_eth_xstat_name *xstats_names, 168 const uint64_t *ids, 169 unsigned int limit); 170 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 171 uint16_t queue_id, 172 uint8_t stat_idx, 173 uint8_t is_rx); 174 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 175 size_t fw_size); 176 static void ixgbe_dev_info_get(struct rte_eth_dev *dev, 177 struct rte_eth_dev_info *dev_info); 178 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); 179 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev, 180 struct rte_eth_dev_info *dev_info); 181 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 182 183 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev, 184 uint16_t vlan_id, int on); 185 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 186 enum rte_vlan_type vlan_type, 187 uint16_t tpid_id); 188 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, 189 uint16_t queue, bool on); 190 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, 191 int on); 192 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, 193 int mask); 194 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask); 195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask); 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue); 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue); 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev); 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev); 200 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev); 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev); 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, 204 struct rte_eth_fc_conf *fc_conf); 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, 206 struct rte_eth_fc_conf *fc_conf); 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 208 struct rte_eth_pfc_conf *pfc_conf); 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 210 struct rte_eth_rss_reta_entry64 *reta_conf, 211 uint16_t reta_size); 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 213 struct rte_eth_rss_reta_entry64 *reta_conf, 214 uint16_t reta_size); 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev); 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); 217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev); 218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); 219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev); 220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev); 221 static void ixgbe_dev_interrupt_handler(void *param); 222 static void ixgbe_dev_interrupt_delayed_handler(void *param); 223 static void ixgbe_dev_setup_link_alarm_handler(void *param); 224 225 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr, 226 uint32_t index, uint32_t pool); 227 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index); 228 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, 229 struct ether_addr *mac_addr); 230 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config); 231 static bool is_device_supported(struct rte_eth_dev *dev, 232 struct rte_pci_driver *drv); 233 234 /* For Virtual Function support */ 235 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev); 236 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev); 237 static int ixgbevf_dev_configure(struct rte_eth_dev *dev); 238 static int ixgbevf_dev_start(struct rte_eth_dev *dev); 239 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev, 240 int wait_to_complete); 241 static void ixgbevf_dev_stop(struct rte_eth_dev *dev); 242 static void ixgbevf_dev_close(struct rte_eth_dev *dev); 243 static int ixgbevf_dev_reset(struct rte_eth_dev *dev); 244 static void ixgbevf_intr_disable(struct rte_eth_dev *dev); 245 static void ixgbevf_intr_enable(struct rte_eth_dev *dev); 246 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev, 247 struct rte_eth_stats *stats); 248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev); 249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, 250 uint16_t vlan_id, int on); 251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, 252 uint16_t queue, int on); 253 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask); 254 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask); 255 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on); 256 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 257 uint16_t queue_id); 258 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 259 uint16_t queue_id); 260 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 261 uint8_t queue, uint8_t msix_vector); 262 static void ixgbevf_configure_msix(struct rte_eth_dev *dev); 263 static void ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev); 264 static void ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev); 265 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev); 266 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev); 267 268 /* For Eth VMDQ APIs support */ 269 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct 270 ether_addr * mac_addr, uint8_t on); 271 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on); 272 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 273 struct rte_eth_mirror_conf *mirror_conf, 274 uint8_t rule_id, uint8_t on); 275 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, 276 uint8_t rule_id); 277 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 278 uint16_t queue_id); 279 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 280 uint16_t queue_id); 281 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 282 uint8_t queue, uint8_t msix_vector); 283 static void ixgbe_configure_msix(struct rte_eth_dev *dev); 284 285 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev, 286 struct ether_addr *mac_addr, 287 uint32_t index, uint32_t pool); 288 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index); 289 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 290 struct ether_addr *mac_addr); 291 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev, 292 struct rte_eth_syn_filter *filter); 293 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev, 294 enum rte_filter_op filter_op, 295 void *arg); 296 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 297 struct ixgbe_5tuple_filter *filter); 298 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 299 struct ixgbe_5tuple_filter *filter); 300 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev, 301 enum rte_filter_op filter_op, 302 void *arg); 303 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev, 304 struct rte_eth_ntuple_filter *filter); 305 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev, 306 enum rte_filter_op filter_op, 307 void *arg); 308 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, 309 struct rte_eth_ethertype_filter *filter); 310 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 311 enum rte_filter_type filter_type, 312 enum rte_filter_op filter_op, 313 void *arg); 314 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 315 316 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 317 struct ether_addr *mc_addr_set, 318 uint32_t nb_mc_addr); 319 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 320 struct rte_eth_dcb_info *dcb_info); 321 322 static int ixgbe_get_reg_length(struct rte_eth_dev *dev); 323 static int ixgbe_get_regs(struct rte_eth_dev *dev, 324 struct rte_dev_reg_info *regs); 325 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev); 326 static int ixgbe_get_eeprom(struct rte_eth_dev *dev, 327 struct rte_dev_eeprom_info *eeprom); 328 static int ixgbe_set_eeprom(struct rte_eth_dev *dev, 329 struct rte_dev_eeprom_info *eeprom); 330 331 static int ixgbe_get_module_info(struct rte_eth_dev *dev, 332 struct rte_eth_dev_module_info *modinfo); 333 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 334 struct rte_dev_eeprom_info *info); 335 336 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev); 337 static int ixgbevf_get_regs(struct rte_eth_dev *dev, 338 struct rte_dev_reg_info *regs); 339 340 static int ixgbe_timesync_enable(struct rte_eth_dev *dev); 341 static int ixgbe_timesync_disable(struct rte_eth_dev *dev); 342 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 343 struct timespec *timestamp, 344 uint32_t flags); 345 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 346 struct timespec *timestamp); 347 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 348 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev, 349 struct timespec *timestamp); 350 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev, 351 const struct timespec *timestamp); 352 static void ixgbevf_dev_interrupt_handler(void *param); 353 354 static int ixgbe_dev_l2_tunnel_eth_type_conf 355 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel); 356 static int ixgbe_dev_l2_tunnel_offload_set 357 (struct rte_eth_dev *dev, 358 struct rte_eth_l2_tunnel_conf *l2_tunnel, 359 uint32_t mask, 360 uint8_t en); 361 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev, 362 enum rte_filter_op filter_op, 363 void *arg); 364 365 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 366 struct rte_eth_udp_tunnel *udp_tunnel); 367 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 368 struct rte_eth_udp_tunnel *udp_tunnel); 369 static int ixgbe_filter_restore(struct rte_eth_dev *dev); 370 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev); 371 372 /* 373 * Define VF Stats MACRO for Non "cleared on read" register 374 */ 375 #define UPDATE_VF_STAT(reg, last, cur) \ 376 { \ 377 uint32_t latest = IXGBE_READ_REG(hw, reg); \ 378 cur += (latest - last) & UINT_MAX; \ 379 last = latest; \ 380 } 381 382 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \ 383 { \ 384 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \ 385 u64 new_msb = IXGBE_READ_REG(hw, msb); \ 386 u64 latest = ((new_msb << 32) | new_lsb); \ 387 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \ 388 last = latest; \ 389 } 390 391 #define IXGBE_SET_HWSTRIP(h, q) do {\ 392 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 393 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 394 (h)->bitmap[idx] |= 1 << bit;\ 395 } while (0) 396 397 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\ 398 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 399 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 400 (h)->bitmap[idx] &= ~(1 << bit);\ 401 } while (0) 402 403 #define IXGBE_GET_HWSTRIP(h, q, r) do {\ 404 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 405 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 406 (r) = (h)->bitmap[idx] >> bit & 1;\ 407 } while (0) 408 409 int ixgbe_logtype_init; 410 int ixgbe_logtype_driver; 411 412 /* 413 * The set of PCI devices this driver supports 414 */ 415 static const struct rte_pci_id pci_id_ixgbe_map[] = { 416 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) }, 417 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) }, 418 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) }, 419 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) }, 420 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) }, 421 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) }, 422 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) }, 423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) }, 424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) }, 425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) }, 426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) }, 427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) }, 428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) }, 429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) }, 430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) }, 431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) }, 432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) }, 433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) }, 434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) }, 435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) }, 436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) }, 437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) }, 438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) }, 439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) }, 440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) }, 441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) }, 442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) }, 443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) }, 444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) }, 445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) }, 446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) }, 447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) }, 448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) }, 449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) }, 450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) }, 451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) }, 452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) }, 453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) }, 454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) }, 455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) }, 456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) }, 457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) }, 458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) }, 459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) }, 460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) }, 461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) }, 462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) }, 463 #ifdef RTE_LIBRTE_IXGBE_BYPASS 464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) }, 465 #endif 466 { .vendor_id = 0, /* sentinel */ }, 467 }; 468 469 /* 470 * The set of PCI devices this driver supports (for 82599 VF) 471 */ 472 static const struct rte_pci_id pci_id_ixgbevf_map[] = { 473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) }, 474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) }, 475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) }, 476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) }, 477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) }, 478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) }, 479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) }, 480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) }, 481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) }, 482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) }, 483 { .vendor_id = 0, /* sentinel */ }, 484 }; 485 486 static const struct rte_eth_desc_lim rx_desc_lim = { 487 .nb_max = IXGBE_MAX_RING_DESC, 488 .nb_min = IXGBE_MIN_RING_DESC, 489 .nb_align = IXGBE_RXD_ALIGN, 490 }; 491 492 static const struct rte_eth_desc_lim tx_desc_lim = { 493 .nb_max = IXGBE_MAX_RING_DESC, 494 .nb_min = IXGBE_MIN_RING_DESC, 495 .nb_align = IXGBE_TXD_ALIGN, 496 .nb_seg_max = IXGBE_TX_MAX_SEG, 497 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG, 498 }; 499 500 static const struct eth_dev_ops ixgbe_eth_dev_ops = { 501 .dev_configure = ixgbe_dev_configure, 502 .dev_start = ixgbe_dev_start, 503 .dev_stop = ixgbe_dev_stop, 504 .dev_set_link_up = ixgbe_dev_set_link_up, 505 .dev_set_link_down = ixgbe_dev_set_link_down, 506 .dev_close = ixgbe_dev_close, 507 .dev_reset = ixgbe_dev_reset, 508 .promiscuous_enable = ixgbe_dev_promiscuous_enable, 509 .promiscuous_disable = ixgbe_dev_promiscuous_disable, 510 .allmulticast_enable = ixgbe_dev_allmulticast_enable, 511 .allmulticast_disable = ixgbe_dev_allmulticast_disable, 512 .link_update = ixgbe_dev_link_update, 513 .stats_get = ixgbe_dev_stats_get, 514 .xstats_get = ixgbe_dev_xstats_get, 515 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id, 516 .stats_reset = ixgbe_dev_stats_reset, 517 .xstats_reset = ixgbe_dev_xstats_reset, 518 .xstats_get_names = ixgbe_dev_xstats_get_names, 519 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id, 520 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set, 521 .fw_version_get = ixgbe_fw_version_get, 522 .dev_infos_get = ixgbe_dev_info_get, 523 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 524 .mtu_set = ixgbe_dev_mtu_set, 525 .vlan_filter_set = ixgbe_vlan_filter_set, 526 .vlan_tpid_set = ixgbe_vlan_tpid_set, 527 .vlan_offload_set = ixgbe_vlan_offload_set, 528 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set, 529 .rx_queue_start = ixgbe_dev_rx_queue_start, 530 .rx_queue_stop = ixgbe_dev_rx_queue_stop, 531 .tx_queue_start = ixgbe_dev_tx_queue_start, 532 .tx_queue_stop = ixgbe_dev_tx_queue_stop, 533 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 534 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable, 535 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable, 536 .rx_queue_release = ixgbe_dev_rx_queue_release, 537 .rx_queue_count = ixgbe_dev_rx_queue_count, 538 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done, 539 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status, 540 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status, 541 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 542 .tx_queue_release = ixgbe_dev_tx_queue_release, 543 .dev_led_on = ixgbe_dev_led_on, 544 .dev_led_off = ixgbe_dev_led_off, 545 .flow_ctrl_get = ixgbe_flow_ctrl_get, 546 .flow_ctrl_set = ixgbe_flow_ctrl_set, 547 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set, 548 .mac_addr_add = ixgbe_add_rar, 549 .mac_addr_remove = ixgbe_remove_rar, 550 .mac_addr_set = ixgbe_set_default_mac_addr, 551 .uc_hash_table_set = ixgbe_uc_hash_table_set, 552 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set, 553 .mirror_rule_set = ixgbe_mirror_rule_set, 554 .mirror_rule_reset = ixgbe_mirror_rule_reset, 555 .set_queue_rate_limit = ixgbe_set_queue_rate_limit, 556 .reta_update = ixgbe_dev_rss_reta_update, 557 .reta_query = ixgbe_dev_rss_reta_query, 558 .rss_hash_update = ixgbe_dev_rss_hash_update, 559 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 560 .filter_ctrl = ixgbe_dev_filter_ctrl, 561 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 562 .rxq_info_get = ixgbe_rxq_info_get, 563 .txq_info_get = ixgbe_txq_info_get, 564 .timesync_enable = ixgbe_timesync_enable, 565 .timesync_disable = ixgbe_timesync_disable, 566 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp, 567 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp, 568 .get_reg = ixgbe_get_regs, 569 .get_eeprom_length = ixgbe_get_eeprom_length, 570 .get_eeprom = ixgbe_get_eeprom, 571 .set_eeprom = ixgbe_set_eeprom, 572 .get_module_info = ixgbe_get_module_info, 573 .get_module_eeprom = ixgbe_get_module_eeprom, 574 .get_dcb_info = ixgbe_dev_get_dcb_info, 575 .timesync_adjust_time = ixgbe_timesync_adjust_time, 576 .timesync_read_time = ixgbe_timesync_read_time, 577 .timesync_write_time = ixgbe_timesync_write_time, 578 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf, 579 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set, 580 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add, 581 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del, 582 .tm_ops_get = ixgbe_tm_ops_get, 583 }; 584 585 /* 586 * dev_ops for virtual function, bare necessities for basic vf 587 * operation have been implemented 588 */ 589 static const struct eth_dev_ops ixgbevf_eth_dev_ops = { 590 .dev_configure = ixgbevf_dev_configure, 591 .dev_start = ixgbevf_dev_start, 592 .dev_stop = ixgbevf_dev_stop, 593 .link_update = ixgbevf_dev_link_update, 594 .stats_get = ixgbevf_dev_stats_get, 595 .xstats_get = ixgbevf_dev_xstats_get, 596 .stats_reset = ixgbevf_dev_stats_reset, 597 .xstats_reset = ixgbevf_dev_stats_reset, 598 .xstats_get_names = ixgbevf_dev_xstats_get_names, 599 .dev_close = ixgbevf_dev_close, 600 .dev_reset = ixgbevf_dev_reset, 601 .promiscuous_enable = ixgbevf_dev_promiscuous_enable, 602 .promiscuous_disable = ixgbevf_dev_promiscuous_disable, 603 .allmulticast_enable = ixgbevf_dev_allmulticast_enable, 604 .allmulticast_disable = ixgbevf_dev_allmulticast_disable, 605 .dev_infos_get = ixgbevf_dev_info_get, 606 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 607 .mtu_set = ixgbevf_dev_set_mtu, 608 .vlan_filter_set = ixgbevf_vlan_filter_set, 609 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set, 610 .vlan_offload_set = ixgbevf_vlan_offload_set, 611 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 612 .rx_queue_release = ixgbe_dev_rx_queue_release, 613 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done, 614 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status, 615 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status, 616 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 617 .tx_queue_release = ixgbe_dev_tx_queue_release, 618 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable, 619 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable, 620 .mac_addr_add = ixgbevf_add_mac_addr, 621 .mac_addr_remove = ixgbevf_remove_mac_addr, 622 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 623 .rxq_info_get = ixgbe_rxq_info_get, 624 .txq_info_get = ixgbe_txq_info_get, 625 .mac_addr_set = ixgbevf_set_default_mac_addr, 626 .get_reg = ixgbevf_get_regs, 627 .reta_update = ixgbe_dev_rss_reta_update, 628 .reta_query = ixgbe_dev_rss_reta_query, 629 .rss_hash_update = ixgbe_dev_rss_hash_update, 630 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 631 }; 632 633 /* store statistics names and its offset in stats structure */ 634 struct rte_ixgbe_xstats_name_off { 635 char name[RTE_ETH_XSTATS_NAME_SIZE]; 636 unsigned offset; 637 }; 638 639 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = { 640 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)}, 641 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)}, 642 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)}, 643 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)}, 644 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)}, 645 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)}, 646 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)}, 647 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)}, 648 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)}, 649 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)}, 650 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)}, 651 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)}, 652 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)}, 653 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)}, 654 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 655 prc1023)}, 656 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 657 prc1522)}, 658 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)}, 659 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)}, 660 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)}, 661 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)}, 662 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)}, 663 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)}, 664 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)}, 665 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)}, 666 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)}, 667 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)}, 668 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)}, 669 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)}, 670 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)}, 671 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)}, 672 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)}, 673 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)}, 674 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 675 ptc1023)}, 676 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 677 ptc1522)}, 678 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)}, 679 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)}, 680 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)}, 681 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)}, 682 683 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats, 684 fdirustat_add)}, 685 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats, 686 fdirustat_remove)}, 687 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats, 688 fdirfstat_fadd)}, 689 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats, 690 fdirfstat_fremove)}, 691 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats, 692 fdirmatch)}, 693 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats, 694 fdirmiss)}, 695 696 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)}, 697 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)}, 698 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, 699 fclast)}, 700 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)}, 701 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)}, 702 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)}, 703 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)}, 704 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats, 705 fcoe_noddp)}, 706 {"rx_fcoe_no_direct_data_placement_ext_buff", 707 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)}, 708 709 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 710 lxontxc)}, 711 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 712 lxonrxc)}, 713 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 714 lxofftxc)}, 715 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 716 lxoffrxc)}, 717 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)}, 718 }; 719 720 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \ 721 sizeof(rte_ixgbe_stats_strings[0])) 722 723 /* MACsec statistics */ 724 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = { 725 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 726 out_pkts_untagged)}, 727 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats, 728 out_pkts_encrypted)}, 729 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats, 730 out_pkts_protected)}, 731 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats, 732 out_octets_encrypted)}, 733 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats, 734 out_octets_protected)}, 735 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 736 in_pkts_untagged)}, 737 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats, 738 in_pkts_badtag)}, 739 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats, 740 in_pkts_nosci)}, 741 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats, 742 in_pkts_unknownsci)}, 743 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats, 744 in_octets_decrypted)}, 745 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats, 746 in_octets_validated)}, 747 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats, 748 in_pkts_unchecked)}, 749 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats, 750 in_pkts_delayed)}, 751 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats, 752 in_pkts_late)}, 753 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats, 754 in_pkts_ok)}, 755 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats, 756 in_pkts_invalid)}, 757 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats, 758 in_pkts_notvalid)}, 759 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats, 760 in_pkts_unusedsa)}, 761 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats, 762 in_pkts_notusingsa)}, 763 }; 764 765 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \ 766 sizeof(rte_ixgbe_macsec_strings[0])) 767 768 /* Per-queue statistics */ 769 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = { 770 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)}, 771 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)}, 772 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)}, 773 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)}, 774 }; 775 776 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \ 777 sizeof(rte_ixgbe_rxq_strings[0])) 778 #define IXGBE_NB_RXQ_PRIO_VALUES 8 779 780 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = { 781 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)}, 782 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)}, 783 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats, 784 pxon2offc)}, 785 }; 786 787 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \ 788 sizeof(rte_ixgbe_txq_strings[0])) 789 #define IXGBE_NB_TXQ_PRIO_VALUES 8 790 791 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = { 792 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)}, 793 }; 794 795 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \ 796 sizeof(rte_ixgbevf_stats_strings[0])) 797 798 /* 799 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h. 800 */ 801 static inline int 802 ixgbe_is_sfp(struct ixgbe_hw *hw) 803 { 804 switch (hw->phy.type) { 805 case ixgbe_phy_sfp_avago: 806 case ixgbe_phy_sfp_ftl: 807 case ixgbe_phy_sfp_intel: 808 case ixgbe_phy_sfp_unknown: 809 case ixgbe_phy_sfp_passive_tyco: 810 case ixgbe_phy_sfp_passive_unknown: 811 return 1; 812 default: 813 return 0; 814 } 815 } 816 817 static inline int32_t 818 ixgbe_pf_reset_hw(struct ixgbe_hw *hw) 819 { 820 uint32_t ctrl_ext; 821 int32_t status; 822 823 status = ixgbe_reset_hw(hw); 824 825 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 826 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 827 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 828 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 829 IXGBE_WRITE_FLUSH(hw); 830 831 if (status == IXGBE_ERR_SFP_NOT_PRESENT) 832 status = IXGBE_SUCCESS; 833 return status; 834 } 835 836 static inline void 837 ixgbe_enable_intr(struct rte_eth_dev *dev) 838 { 839 struct ixgbe_interrupt *intr = 840 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 841 struct ixgbe_hw *hw = 842 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 843 844 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask); 845 IXGBE_WRITE_FLUSH(hw); 846 } 847 848 /* 849 * This function is based on ixgbe_disable_intr() in base/ixgbe.h. 850 */ 851 static void 852 ixgbe_disable_intr(struct ixgbe_hw *hw) 853 { 854 PMD_INIT_FUNC_TRACE(); 855 856 if (hw->mac.type == ixgbe_mac_82598EB) { 857 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0); 858 } else { 859 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000); 860 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0); 861 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0); 862 } 863 IXGBE_WRITE_FLUSH(hw); 864 } 865 866 /* 867 * This function resets queue statistics mapping registers. 868 * From Niantic datasheet, Initialization of Statistics section: 869 * "...if software requires the queue counters, the RQSMR and TQSM registers 870 * must be re-programmed following a device reset. 871 */ 872 static void 873 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw) 874 { 875 uint32_t i; 876 877 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) { 878 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0); 879 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0); 880 } 881 } 882 883 884 static int 885 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 886 uint16_t queue_id, 887 uint8_t stat_idx, 888 uint8_t is_rx) 889 { 890 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8 891 #define NB_QMAP_FIELDS_PER_QSM_REG 4 892 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f 893 894 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 895 struct ixgbe_stat_mapping_registers *stat_mappings = 896 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private); 897 uint32_t qsmr_mask = 0; 898 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK; 899 uint32_t q_map; 900 uint8_t n, offset; 901 902 if ((hw->mac.type != ixgbe_mac_82599EB) && 903 (hw->mac.type != ixgbe_mac_X540) && 904 (hw->mac.type != ixgbe_mac_X550) && 905 (hw->mac.type != ixgbe_mac_X550EM_x) && 906 (hw->mac.type != ixgbe_mac_X550EM_a)) 907 return -ENOSYS; 908 909 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d", 910 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 911 queue_id, stat_idx); 912 913 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG); 914 if (n >= IXGBE_NB_STAT_MAPPING_REGS) { 915 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded"); 916 return -EIO; 917 } 918 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG); 919 920 /* Now clear any previous stat_idx set */ 921 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 922 if (!is_rx) 923 stat_mappings->tqsm[n] &= ~clearing_mask; 924 else 925 stat_mappings->rqsmr[n] &= ~clearing_mask; 926 927 q_map = (uint32_t)stat_idx; 928 q_map &= QMAP_FIELD_RESERVED_BITS_MASK; 929 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 930 if (!is_rx) 931 stat_mappings->tqsm[n] |= qsmr_mask; 932 else 933 stat_mappings->rqsmr[n] |= qsmr_mask; 934 935 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d", 936 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 937 queue_id, stat_idx); 938 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n, 939 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]); 940 941 /* Now write the mapping in the appropriate register */ 942 if (is_rx) { 943 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d", 944 stat_mappings->rqsmr[n], n); 945 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]); 946 } else { 947 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d", 948 stat_mappings->tqsm[n], n); 949 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]); 950 } 951 return 0; 952 } 953 954 static void 955 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev) 956 { 957 struct ixgbe_stat_mapping_registers *stat_mappings = 958 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private); 959 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 960 int i; 961 962 /* write whatever was in stat mapping table to the NIC */ 963 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) { 964 /* rx */ 965 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]); 966 967 /* tx */ 968 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]); 969 } 970 } 971 972 static void 973 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config) 974 { 975 uint8_t i; 976 struct ixgbe_dcb_tc_config *tc; 977 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS; 978 979 dcb_config->num_tcs.pg_tcs = dcb_max_tc; 980 dcb_config->num_tcs.pfc_tcs = dcb_max_tc; 981 for (i = 0; i < dcb_max_tc; i++) { 982 tc = &dcb_config->tc_config[i]; 983 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i; 984 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 985 (uint8_t)(100/dcb_max_tc + (i & 1)); 986 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i; 987 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 988 (uint8_t)(100/dcb_max_tc + (i & 1)); 989 tc->pfc = ixgbe_dcb_pfc_disabled; 990 } 991 992 /* Initialize default user to priority mapping, UPx->TC0 */ 993 tc = &dcb_config->tc_config[0]; 994 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 995 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 996 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) { 997 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100; 998 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100; 999 } 1000 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal; 1001 dcb_config->pfc_mode_enable = false; 1002 dcb_config->vt_mode = true; 1003 dcb_config->round_robin_enable = false; 1004 /* support all DCB capabilities in 82599 */ 1005 dcb_config->support.capabilities = 0xFF; 1006 1007 /*we only support 4 Tcs for X540, X550 */ 1008 if (hw->mac.type == ixgbe_mac_X540 || 1009 hw->mac.type == ixgbe_mac_X550 || 1010 hw->mac.type == ixgbe_mac_X550EM_x || 1011 hw->mac.type == ixgbe_mac_X550EM_a) { 1012 dcb_config->num_tcs.pg_tcs = 4; 1013 dcb_config->num_tcs.pfc_tcs = 4; 1014 } 1015 } 1016 1017 /* 1018 * Ensure that all locks are released before first NVM or PHY access 1019 */ 1020 static void 1021 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw) 1022 { 1023 uint16_t mask; 1024 1025 /* 1026 * Phy lock should not fail in this early stage. If this is the case, 1027 * it is due to an improper exit of the application. 1028 * So force the release of the faulty lock. Release of common lock 1029 * is done automatically by swfw_sync function. 1030 */ 1031 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func; 1032 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1033 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func); 1034 } 1035 ixgbe_release_swfw_semaphore(hw, mask); 1036 1037 /* 1038 * These ones are more tricky since they are common to all ports; but 1039 * swfw_sync retries last long enough (1s) to be almost sure that if 1040 * lock can not be taken it is due to an improper lock of the 1041 * semaphore. 1042 */ 1043 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM; 1044 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1045 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 1046 } 1047 ixgbe_release_swfw_semaphore(hw, mask); 1048 } 1049 1050 /* 1051 * This function is based on code in ixgbe_attach() in base/ixgbe.c. 1052 * It returns 0 on success. 1053 */ 1054 static int 1055 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) 1056 { 1057 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1058 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1059 struct ixgbe_hw *hw = 1060 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1061 struct ixgbe_vfta *shadow_vfta = 1062 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1063 struct ixgbe_hwstrip *hwstrip = 1064 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1065 struct ixgbe_dcb_config *dcb_config = 1066 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private); 1067 struct ixgbe_filter_info *filter_info = 1068 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1069 struct ixgbe_bw_conf *bw_conf = 1070 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private); 1071 uint32_t ctrl_ext; 1072 uint16_t csum; 1073 int diag, i; 1074 1075 PMD_INIT_FUNC_TRACE(); 1076 1077 eth_dev->dev_ops = &ixgbe_eth_dev_ops; 1078 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1079 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1080 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts; 1081 1082 /* 1083 * For secondary processes, we don't initialise any further as primary 1084 * has already done this work. Only check we don't need a different 1085 * RX and TX function. 1086 */ 1087 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1088 struct ixgbe_tx_queue *txq; 1089 /* TX queue function in primary, set by last queue initialized 1090 * Tx queue may not initialized by primary process 1091 */ 1092 if (eth_dev->data->tx_queues) { 1093 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1]; 1094 ixgbe_set_tx_function(eth_dev, txq); 1095 } else { 1096 /* Use default TX function if we get here */ 1097 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. " 1098 "Using default TX function."); 1099 } 1100 1101 ixgbe_set_rx_function(eth_dev); 1102 1103 return 0; 1104 } 1105 1106 rte_eth_copy_pci_info(eth_dev, pci_dev); 1107 1108 /* Vendor and Device ID need to be set before init of shared code */ 1109 hw->device_id = pci_dev->id.device_id; 1110 hw->vendor_id = pci_dev->id.vendor_id; 1111 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1112 hw->allow_unsupported_sfp = 1; 1113 1114 /* Initialize the shared code (base driver) */ 1115 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1116 diag = ixgbe_bypass_init_shared_code(hw); 1117 #else 1118 diag = ixgbe_init_shared_code(hw); 1119 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1120 1121 if (diag != IXGBE_SUCCESS) { 1122 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag); 1123 return -EIO; 1124 } 1125 1126 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 1127 PMD_INIT_LOG(ERR, "\nERROR: " 1128 "Firmware recovery mode detected. Limiting functionality.\n" 1129 "Refer to the Intel(R) Ethernet Adapters and Devices " 1130 "User Guide for details on firmware recovery mode."); 1131 return -EIO; 1132 } 1133 1134 /* pick up the PCI bus settings for reporting later */ 1135 ixgbe_get_bus_info(hw); 1136 1137 /* Unlock any pending hardware semaphore */ 1138 ixgbe_swfw_lock_reset(hw); 1139 1140 #ifdef RTE_LIBRTE_SECURITY 1141 /* Initialize security_ctx only for primary process*/ 1142 if (ixgbe_ipsec_ctx_create(eth_dev)) 1143 return -ENOMEM; 1144 #endif 1145 1146 /* Initialize DCB configuration*/ 1147 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config)); 1148 ixgbe_dcb_init(hw, dcb_config); 1149 /* Get Hardware Flow Control setting */ 1150 hw->fc.requested_mode = ixgbe_fc_full; 1151 hw->fc.current_mode = ixgbe_fc_full; 1152 hw->fc.pause_time = IXGBE_FC_PAUSE; 1153 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 1154 hw->fc.low_water[i] = IXGBE_FC_LO; 1155 hw->fc.high_water[i] = IXGBE_FC_HI; 1156 } 1157 hw->fc.send_xon = 1; 1158 1159 /* Make sure we have a good EEPROM before we read from it */ 1160 diag = ixgbe_validate_eeprom_checksum(hw, &csum); 1161 if (diag != IXGBE_SUCCESS) { 1162 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag); 1163 return -EIO; 1164 } 1165 1166 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1167 diag = ixgbe_bypass_init_hw(hw); 1168 #else 1169 diag = ixgbe_init_hw(hw); 1170 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1171 1172 /* 1173 * Devices with copper phys will fail to initialise if ixgbe_init_hw() 1174 * is called too soon after the kernel driver unbinding/binding occurs. 1175 * The failure occurs in ixgbe_identify_phy_generic() for all devices, 1176 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is 1177 * also called. See ixgbe_identify_phy_82599(). The reason for the 1178 * failure is not known, and only occuts when virtualisation features 1179 * are disabled in the bios. A delay of 100ms was found to be enough by 1180 * trial-and-error, and is doubled to be safe. 1181 */ 1182 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) { 1183 rte_delay_ms(200); 1184 diag = ixgbe_init_hw(hw); 1185 } 1186 1187 if (diag == IXGBE_ERR_SFP_NOT_PRESENT) 1188 diag = IXGBE_SUCCESS; 1189 1190 if (diag == IXGBE_ERR_EEPROM_VERSION) { 1191 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/" 1192 "LOM. Please be aware there may be issues associated " 1193 "with your hardware."); 1194 PMD_INIT_LOG(ERR, "If you are experiencing problems " 1195 "please contact your Intel or hardware representative " 1196 "who provided you with this hardware."); 1197 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED) 1198 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module"); 1199 if (diag) { 1200 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag); 1201 return -EIO; 1202 } 1203 1204 /* Reset the hw statistics */ 1205 ixgbe_dev_stats_reset(eth_dev); 1206 1207 /* disable interrupt */ 1208 ixgbe_disable_intr(hw); 1209 1210 /* reset mappings for queue statistics hw counters*/ 1211 ixgbe_reset_qstat_mappings(hw); 1212 1213 /* Allocate memory for storing MAC addresses */ 1214 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN * 1215 hw->mac.num_rar_entries, 0); 1216 if (eth_dev->data->mac_addrs == NULL) { 1217 PMD_INIT_LOG(ERR, 1218 "Failed to allocate %u bytes needed to store " 1219 "MAC addresses", 1220 ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1221 return -ENOMEM; 1222 } 1223 /* Copy the permanent MAC address */ 1224 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr, 1225 ð_dev->data->mac_addrs[0]); 1226 1227 /* Allocate memory for storing hash filter MAC addresses */ 1228 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN * 1229 IXGBE_VMDQ_NUM_UC_MAC, 0); 1230 if (eth_dev->data->hash_mac_addrs == NULL) { 1231 PMD_INIT_LOG(ERR, 1232 "Failed to allocate %d bytes needed to store MAC addresses", 1233 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC); 1234 return -ENOMEM; 1235 } 1236 1237 /* initialize the vfta */ 1238 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1239 1240 /* initialize the hw strip bitmap*/ 1241 memset(hwstrip, 0, sizeof(*hwstrip)); 1242 1243 /* initialize PF if max_vfs not zero */ 1244 ixgbe_pf_host_init(eth_dev); 1245 1246 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 1247 /* let hardware know driver is loaded */ 1248 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD; 1249 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 1250 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 1251 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 1252 IXGBE_WRITE_FLUSH(hw); 1253 1254 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 1255 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d", 1256 (int) hw->mac.type, (int) hw->phy.type, 1257 (int) hw->phy.sfp_type); 1258 else 1259 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d", 1260 (int) hw->mac.type, (int) hw->phy.type); 1261 1262 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 1263 eth_dev->data->port_id, pci_dev->id.vendor_id, 1264 pci_dev->id.device_id); 1265 1266 rte_intr_callback_register(intr_handle, 1267 ixgbe_dev_interrupt_handler, eth_dev); 1268 1269 /* enable uio/vfio intr/eventfd mapping */ 1270 rte_intr_enable(intr_handle); 1271 1272 /* enable support intr */ 1273 ixgbe_enable_intr(eth_dev); 1274 1275 /* initialize filter info */ 1276 memset(filter_info, 0, 1277 sizeof(struct ixgbe_filter_info)); 1278 1279 /* initialize 5tuple filter list */ 1280 TAILQ_INIT(&filter_info->fivetuple_list); 1281 1282 /* initialize flow director filter list & hash */ 1283 ixgbe_fdir_filter_init(eth_dev); 1284 1285 /* initialize l2 tunnel filter list & hash */ 1286 ixgbe_l2_tn_filter_init(eth_dev); 1287 1288 /* initialize flow filter lists */ 1289 ixgbe_filterlist_init(); 1290 1291 /* initialize bandwidth configuration info */ 1292 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf)); 1293 1294 /* initialize Traffic Manager configuration */ 1295 ixgbe_tm_conf_init(eth_dev); 1296 1297 return 0; 1298 } 1299 1300 static int 1301 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1302 { 1303 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1304 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1305 struct ixgbe_hw *hw; 1306 int retries = 0; 1307 int ret; 1308 1309 PMD_INIT_FUNC_TRACE(); 1310 1311 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1312 return 0; 1313 1314 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1315 1316 if (hw->adapter_stopped == 0) 1317 ixgbe_dev_close(eth_dev); 1318 1319 eth_dev->dev_ops = NULL; 1320 eth_dev->rx_pkt_burst = NULL; 1321 eth_dev->tx_pkt_burst = NULL; 1322 1323 /* Unlock any pending hardware semaphore */ 1324 ixgbe_swfw_lock_reset(hw); 1325 1326 /* disable uio intr before callback unregister */ 1327 rte_intr_disable(intr_handle); 1328 1329 do { 1330 ret = rte_intr_callback_unregister(intr_handle, 1331 ixgbe_dev_interrupt_handler, eth_dev); 1332 if (ret >= 0) { 1333 break; 1334 } else if (ret != -EAGAIN) { 1335 PMD_INIT_LOG(ERR, 1336 "intr callback unregister failed: %d", 1337 ret); 1338 return ret; 1339 } 1340 rte_delay_ms(100); 1341 } while (retries++ < (10 + IXGBE_LINK_UP_TIME)); 1342 1343 /* cancel the delay handler before remove dev */ 1344 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, eth_dev); 1345 1346 /* uninitialize PF if max_vfs not zero */ 1347 ixgbe_pf_host_uninit(eth_dev); 1348 1349 /* remove all the fdir filters & hash */ 1350 ixgbe_fdir_filter_uninit(eth_dev); 1351 1352 /* remove all the L2 tunnel filters & hash */ 1353 ixgbe_l2_tn_filter_uninit(eth_dev); 1354 1355 /* Remove all ntuple filters of the device */ 1356 ixgbe_ntuple_filter_uninit(eth_dev); 1357 1358 /* clear all the filters list */ 1359 ixgbe_filterlist_flush(); 1360 1361 /* Remove all Traffic Manager configuration */ 1362 ixgbe_tm_conf_uninit(eth_dev); 1363 1364 #ifdef RTE_LIBRTE_SECURITY 1365 rte_free(eth_dev->security_ctx); 1366 #endif 1367 1368 return 0; 1369 } 1370 1371 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev) 1372 { 1373 struct ixgbe_filter_info *filter_info = 1374 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1375 struct ixgbe_5tuple_filter *p_5tuple; 1376 1377 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) { 1378 TAILQ_REMOVE(&filter_info->fivetuple_list, 1379 p_5tuple, 1380 entries); 1381 rte_free(p_5tuple); 1382 } 1383 memset(filter_info->fivetuple_mask, 0, 1384 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE); 1385 1386 return 0; 1387 } 1388 1389 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev) 1390 { 1391 struct ixgbe_hw_fdir_info *fdir_info = 1392 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1393 struct ixgbe_fdir_filter *fdir_filter; 1394 1395 if (fdir_info->hash_map) 1396 rte_free(fdir_info->hash_map); 1397 if (fdir_info->hash_handle) 1398 rte_hash_free(fdir_info->hash_handle); 1399 1400 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 1401 TAILQ_REMOVE(&fdir_info->fdir_list, 1402 fdir_filter, 1403 entries); 1404 rte_free(fdir_filter); 1405 } 1406 1407 return 0; 1408 } 1409 1410 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev) 1411 { 1412 struct ixgbe_l2_tn_info *l2_tn_info = 1413 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1414 struct ixgbe_l2_tn_filter *l2_tn_filter; 1415 1416 if (l2_tn_info->hash_map) 1417 rte_free(l2_tn_info->hash_map); 1418 if (l2_tn_info->hash_handle) 1419 rte_hash_free(l2_tn_info->hash_handle); 1420 1421 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 1422 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, 1423 l2_tn_filter, 1424 entries); 1425 rte_free(l2_tn_filter); 1426 } 1427 1428 return 0; 1429 } 1430 1431 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev) 1432 { 1433 struct ixgbe_hw_fdir_info *fdir_info = 1434 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1435 char fdir_hash_name[RTE_HASH_NAMESIZE]; 1436 struct rte_hash_parameters fdir_hash_params = { 1437 .name = fdir_hash_name, 1438 .entries = IXGBE_MAX_FDIR_FILTER_NUM, 1439 .key_len = sizeof(union ixgbe_atr_input), 1440 .hash_func = rte_hash_crc, 1441 .hash_func_init_val = 0, 1442 .socket_id = rte_socket_id(), 1443 }; 1444 1445 TAILQ_INIT(&fdir_info->fdir_list); 1446 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 1447 "fdir_%s", eth_dev->device->name); 1448 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params); 1449 if (!fdir_info->hash_handle) { 1450 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 1451 return -EINVAL; 1452 } 1453 fdir_info->hash_map = rte_zmalloc("ixgbe", 1454 sizeof(struct ixgbe_fdir_filter *) * 1455 IXGBE_MAX_FDIR_FILTER_NUM, 1456 0); 1457 if (!fdir_info->hash_map) { 1458 PMD_INIT_LOG(ERR, 1459 "Failed to allocate memory for fdir hash map!"); 1460 return -ENOMEM; 1461 } 1462 fdir_info->mask_added = FALSE; 1463 1464 return 0; 1465 } 1466 1467 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) 1468 { 1469 struct ixgbe_l2_tn_info *l2_tn_info = 1470 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1471 char l2_tn_hash_name[RTE_HASH_NAMESIZE]; 1472 struct rte_hash_parameters l2_tn_hash_params = { 1473 .name = l2_tn_hash_name, 1474 .entries = IXGBE_MAX_L2_TN_FILTER_NUM, 1475 .key_len = sizeof(struct ixgbe_l2_tn_key), 1476 .hash_func = rte_hash_crc, 1477 .hash_func_init_val = 0, 1478 .socket_id = rte_socket_id(), 1479 }; 1480 1481 TAILQ_INIT(&l2_tn_info->l2_tn_list); 1482 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE, 1483 "l2_tn_%s", eth_dev->device->name); 1484 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params); 1485 if (!l2_tn_info->hash_handle) { 1486 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!"); 1487 return -EINVAL; 1488 } 1489 l2_tn_info->hash_map = rte_zmalloc("ixgbe", 1490 sizeof(struct ixgbe_l2_tn_filter *) * 1491 IXGBE_MAX_L2_TN_FILTER_NUM, 1492 0); 1493 if (!l2_tn_info->hash_map) { 1494 PMD_INIT_LOG(ERR, 1495 "Failed to allocate memory for L2 TN hash map!"); 1496 return -ENOMEM; 1497 } 1498 l2_tn_info->e_tag_en = FALSE; 1499 l2_tn_info->e_tag_fwd_en = FALSE; 1500 l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG; 1501 1502 return 0; 1503 } 1504 /* 1505 * Negotiate mailbox API version with the PF. 1506 * After reset API version is always set to the basic one (ixgbe_mbox_api_10). 1507 * Then we try to negotiate starting with the most recent one. 1508 * If all negotiation attempts fail, then we will proceed with 1509 * the default one (ixgbe_mbox_api_10). 1510 */ 1511 static void 1512 ixgbevf_negotiate_api(struct ixgbe_hw *hw) 1513 { 1514 int32_t i; 1515 1516 /* start with highest supported, proceed down */ 1517 static const enum ixgbe_pfvf_api_rev sup_ver[] = { 1518 ixgbe_mbox_api_13, 1519 ixgbe_mbox_api_12, 1520 ixgbe_mbox_api_11, 1521 ixgbe_mbox_api_10, 1522 }; 1523 1524 for (i = 0; 1525 i != RTE_DIM(sup_ver) && 1526 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0; 1527 i++) 1528 ; 1529 } 1530 1531 static void 1532 generate_random_mac_addr(struct ether_addr *mac_addr) 1533 { 1534 uint64_t random; 1535 1536 /* Set Organizationally Unique Identifier (OUI) prefix. */ 1537 mac_addr->addr_bytes[0] = 0x00; 1538 mac_addr->addr_bytes[1] = 0x09; 1539 mac_addr->addr_bytes[2] = 0xC0; 1540 /* Force indication of locally assigned MAC address. */ 1541 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR; 1542 /* Generate the last 3 bytes of the MAC address with a random number. */ 1543 random = rte_rand(); 1544 memcpy(&mac_addr->addr_bytes[3], &random, 3); 1545 } 1546 1547 /* 1548 * Virtual Function device init 1549 */ 1550 static int 1551 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev) 1552 { 1553 int diag; 1554 uint32_t tc, tcs; 1555 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1556 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1557 struct ixgbe_hw *hw = 1558 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1559 struct ixgbe_vfta *shadow_vfta = 1560 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1561 struct ixgbe_hwstrip *hwstrip = 1562 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1563 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr; 1564 1565 PMD_INIT_FUNC_TRACE(); 1566 1567 eth_dev->dev_ops = &ixgbevf_eth_dev_ops; 1568 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1569 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1570 1571 /* for secondary processes, we don't initialise any further as primary 1572 * has already done this work. Only check we don't need a different 1573 * RX function 1574 */ 1575 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1576 struct ixgbe_tx_queue *txq; 1577 /* TX queue function in primary, set by last queue initialized 1578 * Tx queue may not initialized by primary process 1579 */ 1580 if (eth_dev->data->tx_queues) { 1581 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1]; 1582 ixgbe_set_tx_function(eth_dev, txq); 1583 } else { 1584 /* Use default TX function if we get here */ 1585 PMD_INIT_LOG(NOTICE, 1586 "No TX queues configured yet. Using default TX function."); 1587 } 1588 1589 ixgbe_set_rx_function(eth_dev); 1590 1591 return 0; 1592 } 1593 1594 rte_eth_copy_pci_info(eth_dev, pci_dev); 1595 1596 hw->device_id = pci_dev->id.device_id; 1597 hw->vendor_id = pci_dev->id.vendor_id; 1598 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1599 1600 /* initialize the vfta */ 1601 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1602 1603 /* initialize the hw strip bitmap*/ 1604 memset(hwstrip, 0, sizeof(*hwstrip)); 1605 1606 /* Initialize the shared code (base driver) */ 1607 diag = ixgbe_init_shared_code(hw); 1608 if (diag != IXGBE_SUCCESS) { 1609 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag); 1610 return -EIO; 1611 } 1612 1613 /* init_mailbox_params */ 1614 hw->mbx.ops.init_params(hw); 1615 1616 /* Reset the hw statistics */ 1617 ixgbevf_dev_stats_reset(eth_dev); 1618 1619 /* Disable the interrupts for VF */ 1620 ixgbevf_intr_disable(eth_dev); 1621 1622 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */ 1623 diag = hw->mac.ops.reset_hw(hw); 1624 1625 /* 1626 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when 1627 * the underlying PF driver has not assigned a MAC address to the VF. 1628 * In this case, assign a random MAC address. 1629 */ 1630 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) { 1631 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1632 /* 1633 * This error code will be propagated to the app by 1634 * rte_eth_dev_reset, so use a public error code rather than 1635 * the internal-only IXGBE_ERR_RESET_FAILED 1636 */ 1637 return -EAGAIN; 1638 } 1639 1640 /* negotiate mailbox API version to use with the PF. */ 1641 ixgbevf_negotiate_api(hw); 1642 1643 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */ 1644 ixgbevf_get_queues(hw, &tcs, &tc); 1645 1646 /* Allocate memory for storing MAC addresses */ 1647 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN * 1648 hw->mac.num_rar_entries, 0); 1649 if (eth_dev->data->mac_addrs == NULL) { 1650 PMD_INIT_LOG(ERR, 1651 "Failed to allocate %u bytes needed to store " 1652 "MAC addresses", 1653 ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1654 return -ENOMEM; 1655 } 1656 1657 /* Generate a random MAC address, if none was assigned by PF. */ 1658 if (is_zero_ether_addr(perm_addr)) { 1659 generate_random_mac_addr(perm_addr); 1660 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1); 1661 if (diag) { 1662 rte_free(eth_dev->data->mac_addrs); 1663 eth_dev->data->mac_addrs = NULL; 1664 return diag; 1665 } 1666 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF"); 1667 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address " 1668 "%02x:%02x:%02x:%02x:%02x:%02x", 1669 perm_addr->addr_bytes[0], 1670 perm_addr->addr_bytes[1], 1671 perm_addr->addr_bytes[2], 1672 perm_addr->addr_bytes[3], 1673 perm_addr->addr_bytes[4], 1674 perm_addr->addr_bytes[5]); 1675 } 1676 1677 /* Copy the permanent MAC address */ 1678 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]); 1679 1680 /* reset the hardware with the new settings */ 1681 diag = hw->mac.ops.start_hw(hw); 1682 switch (diag) { 1683 case 0: 1684 break; 1685 1686 default: 1687 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1688 return -EIO; 1689 } 1690 1691 rte_intr_callback_register(intr_handle, 1692 ixgbevf_dev_interrupt_handler, eth_dev); 1693 rte_intr_enable(intr_handle); 1694 ixgbevf_intr_enable(eth_dev); 1695 1696 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s", 1697 eth_dev->data->port_id, pci_dev->id.vendor_id, 1698 pci_dev->id.device_id, "ixgbe_mac_82599_vf"); 1699 1700 return 0; 1701 } 1702 1703 /* Virtual Function device uninit */ 1704 1705 static int 1706 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev) 1707 { 1708 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1709 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1710 struct ixgbe_hw *hw; 1711 1712 PMD_INIT_FUNC_TRACE(); 1713 1714 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1715 return 0; 1716 1717 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1718 1719 if (hw->adapter_stopped == 0) 1720 ixgbevf_dev_close(eth_dev); 1721 1722 eth_dev->dev_ops = NULL; 1723 eth_dev->rx_pkt_burst = NULL; 1724 eth_dev->tx_pkt_burst = NULL; 1725 1726 /* Disable the interrupts for VF */ 1727 ixgbevf_intr_disable(eth_dev); 1728 1729 rte_intr_disable(intr_handle); 1730 rte_intr_callback_unregister(intr_handle, 1731 ixgbevf_dev_interrupt_handler, eth_dev); 1732 1733 return 0; 1734 } 1735 1736 static int 1737 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1738 struct rte_pci_device *pci_dev) 1739 { 1740 char name[RTE_ETH_NAME_MAX_LEN]; 1741 struct rte_eth_dev *pf_ethdev; 1742 struct rte_eth_devargs eth_da; 1743 int i, retval; 1744 1745 if (pci_dev->device.devargs) { 1746 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 1747 ð_da); 1748 if (retval) 1749 return retval; 1750 } else 1751 memset(ð_da, 0, sizeof(eth_da)); 1752 1753 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 1754 sizeof(struct ixgbe_adapter), 1755 eth_dev_pci_specific_init, pci_dev, 1756 eth_ixgbe_dev_init, NULL); 1757 1758 if (retval || eth_da.nb_representor_ports < 1) 1759 return retval; 1760 1761 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1762 if (pf_ethdev == NULL) 1763 return -ENODEV; 1764 1765 /* probe VF representor ports */ 1766 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1767 struct ixgbe_vf_info *vfinfo; 1768 struct ixgbe_vf_representor representor; 1769 1770 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA( 1771 pf_ethdev->data->dev_private); 1772 if (vfinfo == NULL) { 1773 PMD_DRV_LOG(ERR, 1774 "no virtual functions supported by PF"); 1775 break; 1776 } 1777 1778 representor.vf_id = eth_da.representor_ports[i]; 1779 representor.switch_domain_id = vfinfo->switch_domain_id; 1780 representor.pf_ethdev = pf_ethdev; 1781 1782 /* representor port net_bdf_port */ 1783 snprintf(name, sizeof(name), "net_%s_representor_%d", 1784 pci_dev->device.name, 1785 eth_da.representor_ports[i]); 1786 1787 retval = rte_eth_dev_create(&pci_dev->device, name, 1788 sizeof(struct ixgbe_vf_representor), NULL, NULL, 1789 ixgbe_vf_representor_init, &representor); 1790 1791 if (retval) 1792 PMD_DRV_LOG(ERR, "failed to create ixgbe vf " 1793 "representor %s.", name); 1794 } 1795 1796 return 0; 1797 } 1798 1799 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev) 1800 { 1801 struct rte_eth_dev *ethdev; 1802 1803 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1804 if (!ethdev) 1805 return -ENODEV; 1806 1807 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 1808 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit); 1809 else 1810 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit); 1811 } 1812 1813 static struct rte_pci_driver rte_ixgbe_pmd = { 1814 .id_table = pci_id_ixgbe_map, 1815 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 1816 RTE_PCI_DRV_IOVA_AS_VA, 1817 .probe = eth_ixgbe_pci_probe, 1818 .remove = eth_ixgbe_pci_remove, 1819 }; 1820 1821 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1822 struct rte_pci_device *pci_dev) 1823 { 1824 return rte_eth_dev_pci_generic_probe(pci_dev, 1825 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init); 1826 } 1827 1828 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev) 1829 { 1830 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit); 1831 } 1832 1833 /* 1834 * virtual function driver struct 1835 */ 1836 static struct rte_pci_driver rte_ixgbevf_pmd = { 1837 .id_table = pci_id_ixgbevf_map, 1838 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA, 1839 .probe = eth_ixgbevf_pci_probe, 1840 .remove = eth_ixgbevf_pci_remove, 1841 }; 1842 1843 static int 1844 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1845 { 1846 struct ixgbe_hw *hw = 1847 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1848 struct ixgbe_vfta *shadow_vfta = 1849 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1850 uint32_t vfta; 1851 uint32_t vid_idx; 1852 uint32_t vid_bit; 1853 1854 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 1855 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 1856 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx)); 1857 if (on) 1858 vfta |= vid_bit; 1859 else 1860 vfta &= ~vid_bit; 1861 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta); 1862 1863 /* update local VFTA copy */ 1864 shadow_vfta->vfta[vid_idx] = vfta; 1865 1866 return 0; 1867 } 1868 1869 static void 1870 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 1871 { 1872 if (on) 1873 ixgbe_vlan_hw_strip_enable(dev, queue); 1874 else 1875 ixgbe_vlan_hw_strip_disable(dev, queue); 1876 } 1877 1878 static int 1879 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1880 enum rte_vlan_type vlan_type, 1881 uint16_t tpid) 1882 { 1883 struct ixgbe_hw *hw = 1884 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1885 int ret = 0; 1886 uint32_t reg; 1887 uint32_t qinq; 1888 1889 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1890 qinq &= IXGBE_DMATXCTL_GDV; 1891 1892 switch (vlan_type) { 1893 case ETH_VLAN_TYPE_INNER: 1894 if (qinq) { 1895 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1896 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1897 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1898 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1899 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1900 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1901 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1902 } else { 1903 ret = -ENOTSUP; 1904 PMD_DRV_LOG(ERR, "Inner type is not supported" 1905 " by single VLAN"); 1906 } 1907 break; 1908 case ETH_VLAN_TYPE_OUTER: 1909 if (qinq) { 1910 /* Only the high 16-bits is valid */ 1911 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid << 1912 IXGBE_EXVET_VET_EXT_SHIFT); 1913 } else { 1914 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1915 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1916 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1917 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1918 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1919 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1920 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1921 } 1922 1923 break; 1924 default: 1925 ret = -EINVAL; 1926 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type); 1927 break; 1928 } 1929 1930 return ret; 1931 } 1932 1933 void 1934 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev) 1935 { 1936 struct ixgbe_hw *hw = 1937 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1938 uint32_t vlnctrl; 1939 1940 PMD_INIT_FUNC_TRACE(); 1941 1942 /* Filter Table Disable */ 1943 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1944 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 1945 1946 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1947 } 1948 1949 void 1950 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1951 { 1952 struct ixgbe_hw *hw = 1953 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1954 struct ixgbe_vfta *shadow_vfta = 1955 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1956 uint32_t vlnctrl; 1957 uint16_t i; 1958 1959 PMD_INIT_FUNC_TRACE(); 1960 1961 /* Filter Table Enable */ 1962 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1963 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; 1964 vlnctrl |= IXGBE_VLNCTRL_VFE; 1965 1966 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1967 1968 /* write whatever is in local vfta copy */ 1969 for (i = 0; i < IXGBE_VFTA_SIZE; i++) 1970 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]); 1971 } 1972 1973 static void 1974 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on) 1975 { 1976 struct ixgbe_hwstrip *hwstrip = 1977 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private); 1978 struct ixgbe_rx_queue *rxq; 1979 1980 if (queue >= IXGBE_MAX_RX_QUEUE_NUM) 1981 return; 1982 1983 if (on) 1984 IXGBE_SET_HWSTRIP(hwstrip, queue); 1985 else 1986 IXGBE_CLEAR_HWSTRIP(hwstrip, queue); 1987 1988 if (queue >= dev->data->nb_rx_queues) 1989 return; 1990 1991 rxq = dev->data->rx_queues[queue]; 1992 1993 if (on) { 1994 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; 1995 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 1996 } else { 1997 rxq->vlan_flags = PKT_RX_VLAN; 1998 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 1999 } 2000 } 2001 2002 static void 2003 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue) 2004 { 2005 struct ixgbe_hw *hw = 2006 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2007 uint32_t ctrl; 2008 2009 PMD_INIT_FUNC_TRACE(); 2010 2011 if (hw->mac.type == ixgbe_mac_82598EB) { 2012 /* No queue level support */ 2013 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2014 return; 2015 } 2016 2017 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2018 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2019 ctrl &= ~IXGBE_RXDCTL_VME; 2020 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2021 2022 /* record those setting for HW strip per queue */ 2023 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0); 2024 } 2025 2026 static void 2027 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue) 2028 { 2029 struct ixgbe_hw *hw = 2030 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2031 uint32_t ctrl; 2032 2033 PMD_INIT_FUNC_TRACE(); 2034 2035 if (hw->mac.type == ixgbe_mac_82598EB) { 2036 /* No queue level supported */ 2037 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2038 return; 2039 } 2040 2041 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2042 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2043 ctrl |= IXGBE_RXDCTL_VME; 2044 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2045 2046 /* record those setting for HW strip per queue */ 2047 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1); 2048 } 2049 2050 static void 2051 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev) 2052 { 2053 struct ixgbe_hw *hw = 2054 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2055 uint32_t ctrl; 2056 2057 PMD_INIT_FUNC_TRACE(); 2058 2059 /* DMATXCTRL: Geric Double VLAN Disable */ 2060 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2061 ctrl &= ~IXGBE_DMATXCTL_GDV; 2062 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2063 2064 /* CTRL_EXT: Global Double VLAN Disable */ 2065 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2066 ctrl &= ~IXGBE_EXTENDED_VLAN; 2067 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2068 2069 } 2070 2071 static void 2072 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) 2073 { 2074 struct ixgbe_hw *hw = 2075 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2076 uint32_t ctrl; 2077 2078 PMD_INIT_FUNC_TRACE(); 2079 2080 /* DMATXCTRL: Geric Double VLAN Enable */ 2081 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2082 ctrl |= IXGBE_DMATXCTL_GDV; 2083 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2084 2085 /* CTRL_EXT: Global Double VLAN Enable */ 2086 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2087 ctrl |= IXGBE_EXTENDED_VLAN; 2088 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2089 2090 /* Clear pooling mode of PFVTCTL. It's required by X550. */ 2091 if (hw->mac.type == ixgbe_mac_X550 || 2092 hw->mac.type == ixgbe_mac_X550EM_x || 2093 hw->mac.type == ixgbe_mac_X550EM_a) { 2094 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 2095 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 2096 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 2097 } 2098 2099 /* 2100 * VET EXT field in the EXVET register = 0x8100 by default 2101 * So no need to change. Same to VT field of DMATXCTL register 2102 */ 2103 } 2104 2105 void 2106 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev) 2107 { 2108 struct ixgbe_hw *hw = 2109 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2110 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 2111 uint32_t ctrl; 2112 uint16_t i; 2113 struct ixgbe_rx_queue *rxq; 2114 bool on; 2115 2116 PMD_INIT_FUNC_TRACE(); 2117 2118 if (hw->mac.type == ixgbe_mac_82598EB) { 2119 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2120 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2121 ctrl |= IXGBE_VLNCTRL_VME; 2122 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2123 } else { 2124 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2125 ctrl &= ~IXGBE_VLNCTRL_VME; 2126 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2127 } 2128 } else { 2129 /* 2130 * Other 10G NIC, the VLAN strip can be setup 2131 * per queue in RXDCTL 2132 */ 2133 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2134 rxq = dev->data->rx_queues[i]; 2135 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx)); 2136 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2137 ctrl |= IXGBE_RXDCTL_VME; 2138 on = TRUE; 2139 } else { 2140 ctrl &= ~IXGBE_RXDCTL_VME; 2141 on = FALSE; 2142 } 2143 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl); 2144 2145 /* record those setting for HW strip per queue */ 2146 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on); 2147 } 2148 } 2149 } 2150 2151 static void 2152 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask) 2153 { 2154 uint16_t i; 2155 struct rte_eth_rxmode *rxmode; 2156 struct ixgbe_rx_queue *rxq; 2157 2158 if (mask & ETH_VLAN_STRIP_MASK) { 2159 rxmode = &dev->data->dev_conf.rxmode; 2160 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 2161 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2162 rxq = dev->data->rx_queues[i]; 2163 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 2164 } 2165 else 2166 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2167 rxq = dev->data->rx_queues[i]; 2168 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 2169 } 2170 } 2171 } 2172 2173 static int 2174 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask) 2175 { 2176 struct rte_eth_rxmode *rxmode; 2177 rxmode = &dev->data->dev_conf.rxmode; 2178 2179 if (mask & ETH_VLAN_STRIP_MASK) { 2180 ixgbe_vlan_hw_strip_config(dev); 2181 } 2182 2183 if (mask & ETH_VLAN_FILTER_MASK) { 2184 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 2185 ixgbe_vlan_hw_filter_enable(dev); 2186 else 2187 ixgbe_vlan_hw_filter_disable(dev); 2188 } 2189 2190 if (mask & ETH_VLAN_EXTEND_MASK) { 2191 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2192 ixgbe_vlan_hw_extend_enable(dev); 2193 else 2194 ixgbe_vlan_hw_extend_disable(dev); 2195 } 2196 2197 return 0; 2198 } 2199 2200 static int 2201 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2202 { 2203 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 2204 2205 ixgbe_vlan_offload_config(dev, mask); 2206 2207 return 0; 2208 } 2209 2210 static void 2211 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev) 2212 { 2213 struct ixgbe_hw *hw = 2214 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2215 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */ 2216 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2217 2218 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */ 2219 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl); 2220 } 2221 2222 static int 2223 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q) 2224 { 2225 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2226 2227 switch (nb_rx_q) { 2228 case 1: 2229 case 2: 2230 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS; 2231 break; 2232 case 4: 2233 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS; 2234 break; 2235 default: 2236 return -EINVAL; 2237 } 2238 2239 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 2240 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2241 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 2242 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2243 return 0; 2244 } 2245 2246 static int 2247 ixgbe_check_mq_mode(struct rte_eth_dev *dev) 2248 { 2249 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 2250 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2251 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2252 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2253 2254 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 2255 /* check multi-queue mode */ 2256 switch (dev_conf->rxmode.mq_mode) { 2257 case ETH_MQ_RX_VMDQ_DCB: 2258 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV"); 2259 break; 2260 case ETH_MQ_RX_VMDQ_DCB_RSS: 2261 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */ 2262 PMD_INIT_LOG(ERR, "SRIOV active," 2263 " unsupported mq_mode rx %d.", 2264 dev_conf->rxmode.mq_mode); 2265 return -EINVAL; 2266 case ETH_MQ_RX_RSS: 2267 case ETH_MQ_RX_VMDQ_RSS: 2268 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS; 2269 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) 2270 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) { 2271 PMD_INIT_LOG(ERR, "SRIOV is active," 2272 " invalid queue number" 2273 " for VMDQ RSS, allowed" 2274 " value are 1, 2 or 4."); 2275 return -EINVAL; 2276 } 2277 break; 2278 case ETH_MQ_RX_VMDQ_ONLY: 2279 case ETH_MQ_RX_NONE: 2280 /* if nothing mq mode configure, use default scheme */ 2281 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY; 2282 break; 2283 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/ 2284 /* SRIOV only works in VMDq enable mode */ 2285 PMD_INIT_LOG(ERR, "SRIOV is active," 2286 " wrong mq_mode rx %d.", 2287 dev_conf->rxmode.mq_mode); 2288 return -EINVAL; 2289 } 2290 2291 switch (dev_conf->txmode.mq_mode) { 2292 case ETH_MQ_TX_VMDQ_DCB: 2293 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV"); 2294 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB; 2295 break; 2296 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */ 2297 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY; 2298 break; 2299 } 2300 2301 /* check valid queue number */ 2302 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) || 2303 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) { 2304 PMD_INIT_LOG(ERR, "SRIOV is active," 2305 " nb_rx_q=%d nb_tx_q=%d queue number" 2306 " must be less than or equal to %d.", 2307 nb_rx_q, nb_tx_q, 2308 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool); 2309 return -EINVAL; 2310 } 2311 } else { 2312 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) { 2313 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is" 2314 " not supported."); 2315 return -EINVAL; 2316 } 2317 /* check configuration for vmdb+dcb mode */ 2318 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) { 2319 const struct rte_eth_vmdq_dcb_conf *conf; 2320 2321 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2322 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.", 2323 IXGBE_VMDQ_DCB_NB_QUEUES); 2324 return -EINVAL; 2325 } 2326 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf; 2327 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2328 conf->nb_queue_pools == ETH_32_POOLS)) { 2329 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2330 " nb_queue_pools must be %d or %d.", 2331 ETH_16_POOLS, ETH_32_POOLS); 2332 return -EINVAL; 2333 } 2334 } 2335 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) { 2336 const struct rte_eth_vmdq_dcb_tx_conf *conf; 2337 2338 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2339 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d", 2340 IXGBE_VMDQ_DCB_NB_QUEUES); 2341 return -EINVAL; 2342 } 2343 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf; 2344 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2345 conf->nb_queue_pools == ETH_32_POOLS)) { 2346 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2347 " nb_queue_pools != %d and" 2348 " nb_queue_pools != %d.", 2349 ETH_16_POOLS, ETH_32_POOLS); 2350 return -EINVAL; 2351 } 2352 } 2353 2354 /* For DCB mode check our configuration before we go further */ 2355 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) { 2356 const struct rte_eth_dcb_rx_conf *conf; 2357 2358 conf = &dev_conf->rx_adv_conf.dcb_rx_conf; 2359 if (!(conf->nb_tcs == ETH_4_TCS || 2360 conf->nb_tcs == ETH_8_TCS)) { 2361 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2362 " and nb_tcs != %d.", 2363 ETH_4_TCS, ETH_8_TCS); 2364 return -EINVAL; 2365 } 2366 } 2367 2368 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) { 2369 const struct rte_eth_dcb_tx_conf *conf; 2370 2371 conf = &dev_conf->tx_adv_conf.dcb_tx_conf; 2372 if (!(conf->nb_tcs == ETH_4_TCS || 2373 conf->nb_tcs == ETH_8_TCS)) { 2374 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2375 " and nb_tcs != %d.", 2376 ETH_4_TCS, ETH_8_TCS); 2377 return -EINVAL; 2378 } 2379 } 2380 2381 /* 2382 * When DCB/VT is off, maximum number of queues changes, 2383 * except for 82598EB, which remains constant. 2384 */ 2385 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 2386 hw->mac.type != ixgbe_mac_82598EB) { 2387 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) { 2388 PMD_INIT_LOG(ERR, 2389 "Neither VT nor DCB are enabled, " 2390 "nb_tx_q > %d.", 2391 IXGBE_NONE_MODE_TX_NB_QUEUES); 2392 return -EINVAL; 2393 } 2394 } 2395 } 2396 return 0; 2397 } 2398 2399 static int 2400 ixgbe_dev_configure(struct rte_eth_dev *dev) 2401 { 2402 struct ixgbe_interrupt *intr = 2403 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2404 struct ixgbe_adapter *adapter = 2405 (struct ixgbe_adapter *)dev->data->dev_private; 2406 int ret; 2407 2408 PMD_INIT_FUNC_TRACE(); 2409 /* multipe queue mode checking */ 2410 ret = ixgbe_check_mq_mode(dev); 2411 if (ret != 0) { 2412 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.", 2413 ret); 2414 return ret; 2415 } 2416 2417 /* set flag to update link status after init */ 2418 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2419 2420 /* 2421 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 2422 * allocation or vector Rx preconditions we will reset it. 2423 */ 2424 adapter->rx_bulk_alloc_allowed = true; 2425 adapter->rx_vec_allowed = true; 2426 2427 return 0; 2428 } 2429 2430 static void 2431 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) 2432 { 2433 struct ixgbe_hw *hw = 2434 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2435 struct ixgbe_interrupt *intr = 2436 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2437 uint32_t gpie; 2438 2439 /* only set up it on X550EM_X */ 2440 if (hw->mac.type == ixgbe_mac_X550EM_x) { 2441 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 2442 gpie |= IXGBE_SDP0_GPIEN_X550EM_x; 2443 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 2444 if (hw->phy.type == ixgbe_phy_x550em_ext_t) 2445 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x; 2446 } 2447 } 2448 2449 int 2450 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 2451 uint16_t tx_rate, uint64_t q_msk) 2452 { 2453 struct ixgbe_hw *hw; 2454 struct ixgbe_vf_info *vfinfo; 2455 struct rte_eth_link link; 2456 uint8_t nb_q_per_pool; 2457 uint32_t queue_stride; 2458 uint32_t queue_idx, idx = 0, vf_idx; 2459 uint32_t queue_end; 2460 uint16_t total_rate = 0; 2461 struct rte_pci_device *pci_dev; 2462 2463 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2464 rte_eth_link_get_nowait(dev->data->port_id, &link); 2465 2466 if (vf >= pci_dev->max_vfs) 2467 return -EINVAL; 2468 2469 if (tx_rate > link.link_speed) 2470 return -EINVAL; 2471 2472 if (q_msk == 0) 2473 return 0; 2474 2475 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2476 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 2477 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2478 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2479 queue_idx = vf * queue_stride; 2480 queue_end = queue_idx + nb_q_per_pool - 1; 2481 if (queue_end >= hw->mac.max_tx_queues) 2482 return -EINVAL; 2483 2484 if (vfinfo) { 2485 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) { 2486 if (vf_idx == vf) 2487 continue; 2488 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate); 2489 idx++) 2490 total_rate += vfinfo[vf_idx].tx_rate[idx]; 2491 } 2492 } else { 2493 return -EINVAL; 2494 } 2495 2496 /* Store tx_rate for this vf. */ 2497 for (idx = 0; idx < nb_q_per_pool; idx++) { 2498 if (((uint64_t)0x1 << idx) & q_msk) { 2499 if (vfinfo[vf].tx_rate[idx] != tx_rate) 2500 vfinfo[vf].tx_rate[idx] = tx_rate; 2501 total_rate += tx_rate; 2502 } 2503 } 2504 2505 if (total_rate > dev->data->dev_link.link_speed) { 2506 /* Reset stored TX rate of the VF if it causes exceed 2507 * link speed. 2508 */ 2509 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate)); 2510 return -EINVAL; 2511 } 2512 2513 /* Set RTTBCNRC of each queue/pool for vf X */ 2514 for (; queue_idx <= queue_end; queue_idx++) { 2515 if (0x1 & q_msk) 2516 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate); 2517 q_msk = q_msk >> 1; 2518 } 2519 2520 return 0; 2521 } 2522 2523 /* 2524 * Configure device link speed and setup link. 2525 * It returns 0 on success. 2526 */ 2527 static int 2528 ixgbe_dev_start(struct rte_eth_dev *dev) 2529 { 2530 struct ixgbe_hw *hw = 2531 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2532 struct ixgbe_vf_info *vfinfo = 2533 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2534 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2535 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2536 uint32_t intr_vector = 0; 2537 int err, link_up = 0, negotiate = 0; 2538 uint32_t speed = 0; 2539 uint32_t allowed_speeds = 0; 2540 int mask = 0; 2541 int status; 2542 uint16_t vf, idx; 2543 uint32_t *link_speeds; 2544 struct ixgbe_tm_conf *tm_conf = 2545 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2546 2547 PMD_INIT_FUNC_TRACE(); 2548 2549 /* IXGBE devices don't support: 2550 * - half duplex (checked afterwards for valid speeds) 2551 * - fixed speed: TODO implement 2552 */ 2553 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) { 2554 PMD_INIT_LOG(ERR, 2555 "Invalid link_speeds for port %u, fix speed not supported", 2556 dev->data->port_id); 2557 return -EINVAL; 2558 } 2559 2560 /* Stop the link setup handler before resetting the HW. */ 2561 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 2562 2563 /* disable uio/vfio intr/eventfd mapping */ 2564 rte_intr_disable(intr_handle); 2565 2566 /* stop adapter */ 2567 hw->adapter_stopped = 0; 2568 ixgbe_stop_adapter(hw); 2569 2570 /* reinitialize adapter 2571 * this calls reset and start 2572 */ 2573 status = ixgbe_pf_reset_hw(hw); 2574 if (status != 0) 2575 return -1; 2576 hw->mac.ops.start_hw(hw); 2577 hw->mac.get_link_status = true; 2578 2579 /* configure PF module if SRIOV enabled */ 2580 ixgbe_pf_host_configure(dev); 2581 2582 ixgbe_dev_phy_intr_setup(dev); 2583 2584 /* check and configure queue intr-vector mapping */ 2585 if ((rte_intr_cap_multiple(intr_handle) || 2586 !RTE_ETH_DEV_SRIOV(dev).active) && 2587 dev->data->dev_conf.intr_conf.rxq != 0) { 2588 intr_vector = dev->data->nb_rx_queues; 2589 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) { 2590 PMD_INIT_LOG(ERR, "At most %d intr queues supported", 2591 IXGBE_MAX_INTR_QUEUE_NUM); 2592 return -ENOTSUP; 2593 } 2594 if (rte_intr_efd_enable(intr_handle, intr_vector)) 2595 return -1; 2596 } 2597 2598 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 2599 intr_handle->intr_vec = 2600 rte_zmalloc("intr_vec", 2601 dev->data->nb_rx_queues * sizeof(int), 0); 2602 if (intr_handle->intr_vec == NULL) { 2603 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 2604 " intr_vec", dev->data->nb_rx_queues); 2605 return -ENOMEM; 2606 } 2607 } 2608 2609 /* confiugre msix for sleep until rx interrupt */ 2610 ixgbe_configure_msix(dev); 2611 2612 /* initialize transmission unit */ 2613 ixgbe_dev_tx_init(dev); 2614 2615 /* This can fail when allocating mbufs for descriptor rings */ 2616 err = ixgbe_dev_rx_init(dev); 2617 if (err) { 2618 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 2619 goto error; 2620 } 2621 2622 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 2623 ETH_VLAN_EXTEND_MASK; 2624 err = ixgbe_vlan_offload_config(dev, mask); 2625 if (err) { 2626 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 2627 goto error; 2628 } 2629 2630 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) { 2631 /* Enable vlan filtering for VMDq */ 2632 ixgbe_vmdq_vlan_hw_filter_enable(dev); 2633 } 2634 2635 /* Configure DCB hw */ 2636 ixgbe_configure_dcb(dev); 2637 2638 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) { 2639 err = ixgbe_fdir_configure(dev); 2640 if (err) 2641 goto error; 2642 } 2643 2644 /* Restore vf rate limit */ 2645 if (vfinfo != NULL) { 2646 for (vf = 0; vf < pci_dev->max_vfs; vf++) 2647 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++) 2648 if (vfinfo[vf].tx_rate[idx] != 0) 2649 ixgbe_set_vf_rate_limit( 2650 dev, vf, 2651 vfinfo[vf].tx_rate[idx], 2652 1 << idx); 2653 } 2654 2655 ixgbe_restore_statistics_mapping(dev); 2656 2657 err = ixgbe_dev_rxtx_start(dev); 2658 if (err < 0) { 2659 PMD_INIT_LOG(ERR, "Unable to start rxtx queues"); 2660 goto error; 2661 } 2662 2663 /* Skip link setup if loopback mode is enabled. */ 2664 if (dev->data->dev_conf.lpbk_mode != 0) { 2665 err = ixgbe_check_supported_loopback_mode(dev); 2666 if (err < 0) { 2667 PMD_INIT_LOG(ERR, "Unsupported loopback mode"); 2668 goto error; 2669 } else { 2670 goto skip_link_setup; 2671 } 2672 } 2673 2674 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) { 2675 err = hw->mac.ops.setup_sfp(hw); 2676 if (err) 2677 goto error; 2678 } 2679 2680 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2681 /* Turn on the copper */ 2682 ixgbe_set_phy_power(hw, true); 2683 } else { 2684 /* Turn on the laser */ 2685 ixgbe_enable_tx_laser(hw); 2686 } 2687 2688 err = ixgbe_check_link(hw, &speed, &link_up, 0); 2689 if (err) 2690 goto error; 2691 dev->data->dev_link.link_status = link_up; 2692 2693 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate); 2694 if (err) 2695 goto error; 2696 2697 switch (hw->mac.type) { 2698 case ixgbe_mac_X550: 2699 case ixgbe_mac_X550EM_x: 2700 case ixgbe_mac_X550EM_a: 2701 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2702 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G | 2703 ETH_LINK_SPEED_10G; 2704 break; 2705 default: 2706 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2707 ETH_LINK_SPEED_10G; 2708 } 2709 2710 link_speeds = &dev->data->dev_conf.link_speeds; 2711 if (*link_speeds & ~allowed_speeds) { 2712 PMD_INIT_LOG(ERR, "Invalid link setting"); 2713 goto error; 2714 } 2715 2716 speed = 0x0; 2717 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) { 2718 switch (hw->mac.type) { 2719 case ixgbe_mac_82598EB: 2720 speed = IXGBE_LINK_SPEED_82598_AUTONEG; 2721 break; 2722 case ixgbe_mac_82599EB: 2723 case ixgbe_mac_X540: 2724 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2725 break; 2726 case ixgbe_mac_X550: 2727 case ixgbe_mac_X550EM_x: 2728 case ixgbe_mac_X550EM_a: 2729 speed = IXGBE_LINK_SPEED_X550_AUTONEG; 2730 break; 2731 default: 2732 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2733 } 2734 } else { 2735 if (*link_speeds & ETH_LINK_SPEED_10G) 2736 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2737 if (*link_speeds & ETH_LINK_SPEED_5G) 2738 speed |= IXGBE_LINK_SPEED_5GB_FULL; 2739 if (*link_speeds & ETH_LINK_SPEED_2_5G) 2740 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 2741 if (*link_speeds & ETH_LINK_SPEED_1G) 2742 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2743 if (*link_speeds & ETH_LINK_SPEED_100M) 2744 speed |= IXGBE_LINK_SPEED_100_FULL; 2745 } 2746 2747 err = ixgbe_setup_link(hw, speed, link_up); 2748 if (err) 2749 goto error; 2750 2751 skip_link_setup: 2752 2753 if (rte_intr_allow_others(intr_handle)) { 2754 /* check if lsc interrupt is enabled */ 2755 if (dev->data->dev_conf.intr_conf.lsc != 0) 2756 ixgbe_dev_lsc_interrupt_setup(dev, TRUE); 2757 else 2758 ixgbe_dev_lsc_interrupt_setup(dev, FALSE); 2759 ixgbe_dev_macsec_interrupt_setup(dev); 2760 } else { 2761 rte_intr_callback_unregister(intr_handle, 2762 ixgbe_dev_interrupt_handler, dev); 2763 if (dev->data->dev_conf.intr_conf.lsc != 0) 2764 PMD_INIT_LOG(INFO, "lsc won't enable because of" 2765 " no intr multiplex"); 2766 } 2767 2768 /* check if rxq interrupt is enabled */ 2769 if (dev->data->dev_conf.intr_conf.rxq != 0 && 2770 rte_intr_dp_is_en(intr_handle)) 2771 ixgbe_dev_rxq_interrupt_setup(dev); 2772 2773 /* enable uio/vfio intr/eventfd mapping */ 2774 rte_intr_enable(intr_handle); 2775 2776 /* resume enabled intr since hw reset */ 2777 ixgbe_enable_intr(dev); 2778 ixgbe_l2_tunnel_conf(dev); 2779 ixgbe_filter_restore(dev); 2780 2781 if (tm_conf->root && !tm_conf->committed) 2782 PMD_DRV_LOG(WARNING, 2783 "please call hierarchy_commit() " 2784 "before starting the port"); 2785 2786 /* 2787 * Update link status right before return, because it may 2788 * start link configuration process in a separate thread. 2789 */ 2790 ixgbe_dev_link_update(dev, 0); 2791 2792 return 0; 2793 2794 error: 2795 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err); 2796 ixgbe_dev_clear_queues(dev); 2797 return -EIO; 2798 } 2799 2800 /* 2801 * Stop device: disable rx and tx functions to allow for reconfiguring. 2802 */ 2803 static void 2804 ixgbe_dev_stop(struct rte_eth_dev *dev) 2805 { 2806 struct rte_eth_link link; 2807 struct ixgbe_adapter *adapter = 2808 (struct ixgbe_adapter *)dev->data->dev_private; 2809 struct ixgbe_hw *hw = 2810 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2811 struct ixgbe_vf_info *vfinfo = 2812 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2813 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2814 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2815 int vf; 2816 struct ixgbe_tm_conf *tm_conf = 2817 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2818 2819 PMD_INIT_FUNC_TRACE(); 2820 2821 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 2822 2823 /* disable interrupts */ 2824 ixgbe_disable_intr(hw); 2825 2826 /* reset the NIC */ 2827 ixgbe_pf_reset_hw(hw); 2828 hw->adapter_stopped = 0; 2829 2830 /* stop adapter */ 2831 ixgbe_stop_adapter(hw); 2832 2833 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++) 2834 vfinfo[vf].clear_to_send = false; 2835 2836 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2837 /* Turn off the copper */ 2838 ixgbe_set_phy_power(hw, false); 2839 } else { 2840 /* Turn off the laser */ 2841 ixgbe_disable_tx_laser(hw); 2842 } 2843 2844 ixgbe_dev_clear_queues(dev); 2845 2846 /* Clear stored conf */ 2847 dev->data->scattered_rx = 0; 2848 dev->data->lro = 0; 2849 2850 /* Clear recorded link status */ 2851 memset(&link, 0, sizeof(link)); 2852 rte_eth_linkstatus_set(dev, &link); 2853 2854 if (!rte_intr_allow_others(intr_handle)) 2855 /* resume to the default handler */ 2856 rte_intr_callback_register(intr_handle, 2857 ixgbe_dev_interrupt_handler, 2858 (void *)dev); 2859 2860 /* Clean datapath event and queue/vec mapping */ 2861 rte_intr_efd_disable(intr_handle); 2862 if (intr_handle->intr_vec != NULL) { 2863 rte_free(intr_handle->intr_vec); 2864 intr_handle->intr_vec = NULL; 2865 } 2866 2867 /* reset hierarchy commit */ 2868 tm_conf->committed = false; 2869 2870 adapter->rss_reta_updated = 0; 2871 } 2872 2873 /* 2874 * Set device link up: enable tx. 2875 */ 2876 static int 2877 ixgbe_dev_set_link_up(struct rte_eth_dev *dev) 2878 { 2879 struct ixgbe_hw *hw = 2880 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2881 if (hw->mac.type == ixgbe_mac_82599EB) { 2882 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2883 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2884 /* Not suported in bypass mode */ 2885 PMD_INIT_LOG(ERR, "Set link up is not supported " 2886 "by device id 0x%x", hw->device_id); 2887 return -ENOTSUP; 2888 } 2889 #endif 2890 } 2891 2892 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2893 /* Turn on the copper */ 2894 ixgbe_set_phy_power(hw, true); 2895 } else { 2896 /* Turn on the laser */ 2897 ixgbe_enable_tx_laser(hw); 2898 } 2899 2900 return 0; 2901 } 2902 2903 /* 2904 * Set device link down: disable tx. 2905 */ 2906 static int 2907 ixgbe_dev_set_link_down(struct rte_eth_dev *dev) 2908 { 2909 struct ixgbe_hw *hw = 2910 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2911 if (hw->mac.type == ixgbe_mac_82599EB) { 2912 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2913 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2914 /* Not suported in bypass mode */ 2915 PMD_INIT_LOG(ERR, "Set link down is not supported " 2916 "by device id 0x%x", hw->device_id); 2917 return -ENOTSUP; 2918 } 2919 #endif 2920 } 2921 2922 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2923 /* Turn off the copper */ 2924 ixgbe_set_phy_power(hw, false); 2925 } else { 2926 /* Turn off the laser */ 2927 ixgbe_disable_tx_laser(hw); 2928 } 2929 2930 return 0; 2931 } 2932 2933 /* 2934 * Reset and stop device. 2935 */ 2936 static void 2937 ixgbe_dev_close(struct rte_eth_dev *dev) 2938 { 2939 struct ixgbe_hw *hw = 2940 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2941 2942 PMD_INIT_FUNC_TRACE(); 2943 2944 ixgbe_pf_reset_hw(hw); 2945 2946 ixgbe_dev_stop(dev); 2947 hw->adapter_stopped = 1; 2948 2949 ixgbe_dev_free_queues(dev); 2950 2951 ixgbe_disable_pcie_master(hw); 2952 2953 /* reprogram the RAR[0] in case user changed it. */ 2954 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2955 } 2956 2957 /* 2958 * Reset PF device. 2959 */ 2960 static int 2961 ixgbe_dev_reset(struct rte_eth_dev *dev) 2962 { 2963 int ret; 2964 2965 /* When a DPDK PMD PF begin to reset PF port, it should notify all 2966 * its VF to make them align with it. The detailed notification 2967 * mechanism is PMD specific. As to ixgbe PF, it is rather complex. 2968 * To avoid unexpected behavior in VF, currently reset of PF with 2969 * SR-IOV activation is not supported. It might be supported later. 2970 */ 2971 if (dev->data->sriov.active) 2972 return -ENOTSUP; 2973 2974 ret = eth_ixgbe_dev_uninit(dev); 2975 if (ret) 2976 return ret; 2977 2978 ret = eth_ixgbe_dev_init(dev, NULL); 2979 2980 return ret; 2981 } 2982 2983 static void 2984 ixgbe_read_stats_registers(struct ixgbe_hw *hw, 2985 struct ixgbe_hw_stats *hw_stats, 2986 struct ixgbe_macsec_stats *macsec_stats, 2987 uint64_t *total_missed_rx, uint64_t *total_qbrc, 2988 uint64_t *total_qprc, uint64_t *total_qprdc) 2989 { 2990 uint32_t bprc, lxon, lxoff, total; 2991 uint32_t delta_gprc = 0; 2992 unsigned i; 2993 /* Workaround for RX byte count not including CRC bytes when CRC 2994 * strip is enabled. CRC bytes are removed from counters when crc_strip 2995 * is disabled. 2996 */ 2997 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) & 2998 IXGBE_HLREG0_RXCRCSTRP); 2999 3000 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 3001 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC); 3002 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC); 3003 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC); 3004 3005 for (i = 0; i < 8; i++) { 3006 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 3007 3008 /* global total per queue */ 3009 hw_stats->mpc[i] += mp; 3010 /* Running comprehensive total for stats display */ 3011 *total_missed_rx += hw_stats->mpc[i]; 3012 if (hw->mac.type == ixgbe_mac_82598EB) { 3013 hw_stats->rnbc[i] += 3014 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 3015 hw_stats->pxonrxc[i] += 3016 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 3017 hw_stats->pxoffrxc[i] += 3018 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 3019 } else { 3020 hw_stats->pxonrxc[i] += 3021 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 3022 hw_stats->pxoffrxc[i] += 3023 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 3024 hw_stats->pxon2offc[i] += 3025 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 3026 } 3027 hw_stats->pxontxc[i] += 3028 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 3029 hw_stats->pxofftxc[i] += 3030 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 3031 } 3032 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3033 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 3034 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 3035 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 3036 3037 delta_gprc += delta_qprc; 3038 3039 hw_stats->qprc[i] += delta_qprc; 3040 hw_stats->qptc[i] += delta_qptc; 3041 3042 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 3043 hw_stats->qbrc[i] += 3044 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32); 3045 if (crc_strip == 0) 3046 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN; 3047 3048 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 3049 hw_stats->qbtc[i] += 3050 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32); 3051 3052 hw_stats->qprdc[i] += delta_qprdc; 3053 *total_qprdc += hw_stats->qprdc[i]; 3054 3055 *total_qprc += hw_stats->qprc[i]; 3056 *total_qbrc += hw_stats->qbrc[i]; 3057 } 3058 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC); 3059 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC); 3060 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 3061 3062 /* 3063 * An errata states that gprc actually counts good + missed packets: 3064 * Workaround to set gprc to summated queue packet receives 3065 */ 3066 hw_stats->gprc = *total_qprc; 3067 3068 if (hw->mac.type != ixgbe_mac_82598EB) { 3069 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 3070 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32); 3071 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 3072 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32); 3073 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 3074 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32); 3075 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 3076 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 3077 } else { 3078 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 3079 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 3080 /* 82598 only has a counter in the high register */ 3081 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 3082 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 3083 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 3084 } 3085 uint64_t old_tpr = hw_stats->tpr; 3086 3087 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 3088 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT); 3089 3090 if (crc_strip == 0) 3091 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN; 3092 3093 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC); 3094 hw_stats->gptc += delta_gptc; 3095 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN; 3096 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN; 3097 3098 /* 3099 * Workaround: mprc hardware is incorrectly counting 3100 * broadcasts, so for now we subtract those. 3101 */ 3102 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 3103 hw_stats->bprc += bprc; 3104 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 3105 if (hw->mac.type == ixgbe_mac_82598EB) 3106 hw_stats->mprc -= bprc; 3107 3108 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 3109 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 3110 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 3111 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 3112 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 3113 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 3114 3115 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 3116 hw_stats->lxontxc += lxon; 3117 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 3118 hw_stats->lxofftxc += lxoff; 3119 total = lxon + lxoff; 3120 3121 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 3122 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 3123 hw_stats->gptc -= total; 3124 hw_stats->mptc -= total; 3125 hw_stats->ptc64 -= total; 3126 hw_stats->gotc -= total * ETHER_MIN_LEN; 3127 3128 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 3129 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 3130 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 3131 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 3132 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC); 3133 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC); 3134 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC); 3135 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 3136 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 3137 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 3138 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 3139 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 3140 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 3141 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC); 3142 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 3143 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST); 3144 /* Only read FCOE on 82599 */ 3145 if (hw->mac.type != ixgbe_mac_82598EB) { 3146 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 3147 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 3148 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 3149 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 3150 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 3151 } 3152 3153 /* Flow Director Stats registers */ 3154 if (hw->mac.type != ixgbe_mac_82598EB) { 3155 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 3156 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 3157 hw_stats->fdirustat_add += IXGBE_READ_REG(hw, 3158 IXGBE_FDIRUSTAT) & 0xFFFF; 3159 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw, 3160 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF; 3161 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw, 3162 IXGBE_FDIRFSTAT) & 0xFFFF; 3163 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw, 3164 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF; 3165 } 3166 /* MACsec Stats registers */ 3167 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT); 3168 macsec_stats->out_pkts_encrypted += 3169 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE); 3170 macsec_stats->out_pkts_protected += 3171 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP); 3172 macsec_stats->out_octets_encrypted += 3173 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE); 3174 macsec_stats->out_octets_protected += 3175 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP); 3176 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT); 3177 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD); 3178 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI); 3179 macsec_stats->in_pkts_unknownsci += 3180 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI); 3181 macsec_stats->in_octets_decrypted += 3182 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD); 3183 macsec_stats->in_octets_validated += 3184 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV); 3185 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH); 3186 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY); 3187 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE); 3188 for (i = 0; i < 2; i++) { 3189 macsec_stats->in_pkts_ok += 3190 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i)); 3191 macsec_stats->in_pkts_invalid += 3192 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i)); 3193 macsec_stats->in_pkts_notvalid += 3194 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i)); 3195 } 3196 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA); 3197 macsec_stats->in_pkts_notusingsa += 3198 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA); 3199 } 3200 3201 /* 3202 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c 3203 */ 3204 static int 3205 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3206 { 3207 struct ixgbe_hw *hw = 3208 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3209 struct ixgbe_hw_stats *hw_stats = 3210 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3211 struct ixgbe_macsec_stats *macsec_stats = 3212 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3213 dev->data->dev_private); 3214 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3215 unsigned i; 3216 3217 total_missed_rx = 0; 3218 total_qbrc = 0; 3219 total_qprc = 0; 3220 total_qprdc = 0; 3221 3222 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3223 &total_qbrc, &total_qprc, &total_qprdc); 3224 3225 if (stats == NULL) 3226 return -EINVAL; 3227 3228 /* Fill out the rte_eth_stats statistics structure */ 3229 stats->ipackets = total_qprc; 3230 stats->ibytes = total_qbrc; 3231 stats->opackets = hw_stats->gptc; 3232 stats->obytes = hw_stats->gotc; 3233 3234 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3235 stats->q_ipackets[i] = hw_stats->qprc[i]; 3236 stats->q_opackets[i] = hw_stats->qptc[i]; 3237 stats->q_ibytes[i] = hw_stats->qbrc[i]; 3238 stats->q_obytes[i] = hw_stats->qbtc[i]; 3239 stats->q_errors[i] = hw_stats->qprdc[i]; 3240 } 3241 3242 /* Rx Errors */ 3243 stats->imissed = total_missed_rx; 3244 stats->ierrors = hw_stats->crcerrs + 3245 hw_stats->mspdc + 3246 hw_stats->rlec + 3247 hw_stats->ruc + 3248 hw_stats->roc + 3249 hw_stats->illerrc + 3250 hw_stats->errbc + 3251 hw_stats->rfc + 3252 hw_stats->fccrc + 3253 hw_stats->fclast; 3254 3255 /* Tx Errors */ 3256 stats->oerrors = 0; 3257 return 0; 3258 } 3259 3260 static void 3261 ixgbe_dev_stats_reset(struct rte_eth_dev *dev) 3262 { 3263 struct ixgbe_hw_stats *stats = 3264 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3265 3266 /* HW registers are cleared on read */ 3267 ixgbe_dev_stats_get(dev, NULL); 3268 3269 /* Reset software totals */ 3270 memset(stats, 0, sizeof(*stats)); 3271 } 3272 3273 /* This function calculates the number of xstats based on the current config */ 3274 static unsigned 3275 ixgbe_xstats_calc_num(void) { 3276 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS + 3277 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) + 3278 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES); 3279 } 3280 3281 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3282 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size) 3283 { 3284 const unsigned cnt_stats = ixgbe_xstats_calc_num(); 3285 unsigned stat, i, count; 3286 3287 if (xstats_names != NULL) { 3288 count = 0; 3289 3290 /* Note: limit >= cnt_stats checked upstream 3291 * in rte_eth_xstats_names() 3292 */ 3293 3294 /* Extended stats from ixgbe_hw_stats */ 3295 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3296 snprintf(xstats_names[count].name, 3297 sizeof(xstats_names[count].name), 3298 "%s", 3299 rte_ixgbe_stats_strings[i].name); 3300 count++; 3301 } 3302 3303 /* MACsec Stats */ 3304 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3305 snprintf(xstats_names[count].name, 3306 sizeof(xstats_names[count].name), 3307 "%s", 3308 rte_ixgbe_macsec_strings[i].name); 3309 count++; 3310 } 3311 3312 /* RX Priority Stats */ 3313 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3314 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3315 snprintf(xstats_names[count].name, 3316 sizeof(xstats_names[count].name), 3317 "rx_priority%u_%s", i, 3318 rte_ixgbe_rxq_strings[stat].name); 3319 count++; 3320 } 3321 } 3322 3323 /* TX Priority Stats */ 3324 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3325 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3326 snprintf(xstats_names[count].name, 3327 sizeof(xstats_names[count].name), 3328 "tx_priority%u_%s", i, 3329 rte_ixgbe_txq_strings[stat].name); 3330 count++; 3331 } 3332 } 3333 } 3334 return cnt_stats; 3335 } 3336 3337 static int ixgbe_dev_xstats_get_names_by_id( 3338 struct rte_eth_dev *dev, 3339 struct rte_eth_xstat_name *xstats_names, 3340 const uint64_t *ids, 3341 unsigned int limit) 3342 { 3343 if (!ids) { 3344 const unsigned int cnt_stats = ixgbe_xstats_calc_num(); 3345 unsigned int stat, i, count; 3346 3347 if (xstats_names != NULL) { 3348 count = 0; 3349 3350 /* Note: limit >= cnt_stats checked upstream 3351 * in rte_eth_xstats_names() 3352 */ 3353 3354 /* Extended stats from ixgbe_hw_stats */ 3355 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3356 snprintf(xstats_names[count].name, 3357 sizeof(xstats_names[count].name), 3358 "%s", 3359 rte_ixgbe_stats_strings[i].name); 3360 count++; 3361 } 3362 3363 /* MACsec Stats */ 3364 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3365 snprintf(xstats_names[count].name, 3366 sizeof(xstats_names[count].name), 3367 "%s", 3368 rte_ixgbe_macsec_strings[i].name); 3369 count++; 3370 } 3371 3372 /* RX Priority Stats */ 3373 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3374 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3375 snprintf(xstats_names[count].name, 3376 sizeof(xstats_names[count].name), 3377 "rx_priority%u_%s", i, 3378 rte_ixgbe_rxq_strings[stat].name); 3379 count++; 3380 } 3381 } 3382 3383 /* TX Priority Stats */ 3384 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3385 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3386 snprintf(xstats_names[count].name, 3387 sizeof(xstats_names[count].name), 3388 "tx_priority%u_%s", i, 3389 rte_ixgbe_txq_strings[stat].name); 3390 count++; 3391 } 3392 } 3393 } 3394 return cnt_stats; 3395 } 3396 3397 uint16_t i; 3398 uint16_t size = ixgbe_xstats_calc_num(); 3399 struct rte_eth_xstat_name xstats_names_copy[size]; 3400 3401 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL, 3402 size); 3403 3404 for (i = 0; i < limit; i++) { 3405 if (ids[i] >= size) { 3406 PMD_INIT_LOG(ERR, "id value isn't valid"); 3407 return -1; 3408 } 3409 strcpy(xstats_names[i].name, 3410 xstats_names_copy[ids[i]].name); 3411 } 3412 return limit; 3413 } 3414 3415 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3416 struct rte_eth_xstat_name *xstats_names, unsigned limit) 3417 { 3418 unsigned i; 3419 3420 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL) 3421 return -ENOMEM; 3422 3423 if (xstats_names != NULL) 3424 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) 3425 snprintf(xstats_names[i].name, 3426 sizeof(xstats_names[i].name), 3427 "%s", rte_ixgbevf_stats_strings[i].name); 3428 return IXGBEVF_NB_XSTATS; 3429 } 3430 3431 static int 3432 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3433 unsigned n) 3434 { 3435 struct ixgbe_hw *hw = 3436 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3437 struct ixgbe_hw_stats *hw_stats = 3438 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3439 struct ixgbe_macsec_stats *macsec_stats = 3440 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3441 dev->data->dev_private); 3442 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3443 unsigned i, stat, count = 0; 3444 3445 count = ixgbe_xstats_calc_num(); 3446 3447 if (n < count) 3448 return count; 3449 3450 total_missed_rx = 0; 3451 total_qbrc = 0; 3452 total_qprc = 0; 3453 total_qprdc = 0; 3454 3455 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3456 &total_qbrc, &total_qprc, &total_qprdc); 3457 3458 /* If this is a reset xstats is NULL, and we have cleared the 3459 * registers by reading them. 3460 */ 3461 if (!xstats) 3462 return 0; 3463 3464 /* Extended stats from ixgbe_hw_stats */ 3465 count = 0; 3466 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3467 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3468 rte_ixgbe_stats_strings[i].offset); 3469 xstats[count].id = count; 3470 count++; 3471 } 3472 3473 /* MACsec Stats */ 3474 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3475 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) + 3476 rte_ixgbe_macsec_strings[i].offset); 3477 xstats[count].id = count; 3478 count++; 3479 } 3480 3481 /* RX Priority Stats */ 3482 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3483 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3484 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3485 rte_ixgbe_rxq_strings[stat].offset + 3486 (sizeof(uint64_t) * i)); 3487 xstats[count].id = count; 3488 count++; 3489 } 3490 } 3491 3492 /* TX Priority Stats */ 3493 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3494 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3495 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3496 rte_ixgbe_txq_strings[stat].offset + 3497 (sizeof(uint64_t) * i)); 3498 xstats[count].id = count; 3499 count++; 3500 } 3501 } 3502 return count; 3503 } 3504 3505 static int 3506 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 3507 uint64_t *values, unsigned int n) 3508 { 3509 if (!ids) { 3510 struct ixgbe_hw *hw = 3511 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3512 struct ixgbe_hw_stats *hw_stats = 3513 IXGBE_DEV_PRIVATE_TO_STATS( 3514 dev->data->dev_private); 3515 struct ixgbe_macsec_stats *macsec_stats = 3516 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3517 dev->data->dev_private); 3518 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3519 unsigned int i, stat, count = 0; 3520 3521 count = ixgbe_xstats_calc_num(); 3522 3523 if (!ids && n < count) 3524 return count; 3525 3526 total_missed_rx = 0; 3527 total_qbrc = 0; 3528 total_qprc = 0; 3529 total_qprdc = 0; 3530 3531 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, 3532 &total_missed_rx, &total_qbrc, &total_qprc, 3533 &total_qprdc); 3534 3535 /* If this is a reset xstats is NULL, and we have cleared the 3536 * registers by reading them. 3537 */ 3538 if (!ids && !values) 3539 return 0; 3540 3541 /* Extended stats from ixgbe_hw_stats */ 3542 count = 0; 3543 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3544 values[count] = *(uint64_t *)(((char *)hw_stats) + 3545 rte_ixgbe_stats_strings[i].offset); 3546 count++; 3547 } 3548 3549 /* MACsec Stats */ 3550 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3551 values[count] = *(uint64_t *)(((char *)macsec_stats) + 3552 rte_ixgbe_macsec_strings[i].offset); 3553 count++; 3554 } 3555 3556 /* RX Priority Stats */ 3557 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3558 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3559 values[count] = 3560 *(uint64_t *)(((char *)hw_stats) + 3561 rte_ixgbe_rxq_strings[stat].offset + 3562 (sizeof(uint64_t) * i)); 3563 count++; 3564 } 3565 } 3566 3567 /* TX Priority Stats */ 3568 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3569 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3570 values[count] = 3571 *(uint64_t *)(((char *)hw_stats) + 3572 rte_ixgbe_txq_strings[stat].offset + 3573 (sizeof(uint64_t) * i)); 3574 count++; 3575 } 3576 } 3577 return count; 3578 } 3579 3580 uint16_t i; 3581 uint16_t size = ixgbe_xstats_calc_num(); 3582 uint64_t values_copy[size]; 3583 3584 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size); 3585 3586 for (i = 0; i < n; i++) { 3587 if (ids[i] >= size) { 3588 PMD_INIT_LOG(ERR, "id value isn't valid"); 3589 return -1; 3590 } 3591 values[i] = values_copy[ids[i]]; 3592 } 3593 return n; 3594 } 3595 3596 static void 3597 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev) 3598 { 3599 struct ixgbe_hw_stats *stats = 3600 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3601 struct ixgbe_macsec_stats *macsec_stats = 3602 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3603 dev->data->dev_private); 3604 3605 unsigned count = ixgbe_xstats_calc_num(); 3606 3607 /* HW registers are cleared on read */ 3608 ixgbe_dev_xstats_get(dev, NULL, count); 3609 3610 /* Reset software totals */ 3611 memset(stats, 0, sizeof(*stats)); 3612 memset(macsec_stats, 0, sizeof(*macsec_stats)); 3613 } 3614 3615 static void 3616 ixgbevf_update_stats(struct rte_eth_dev *dev) 3617 { 3618 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3619 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3620 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3621 3622 /* Good Rx packet, include VF loopback */ 3623 UPDATE_VF_STAT(IXGBE_VFGPRC, 3624 hw_stats->last_vfgprc, hw_stats->vfgprc); 3625 3626 /* Good Rx octets, include VF loopback */ 3627 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB, 3628 hw_stats->last_vfgorc, hw_stats->vfgorc); 3629 3630 /* Good Tx packet, include VF loopback */ 3631 UPDATE_VF_STAT(IXGBE_VFGPTC, 3632 hw_stats->last_vfgptc, hw_stats->vfgptc); 3633 3634 /* Good Tx octets, include VF loopback */ 3635 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB, 3636 hw_stats->last_vfgotc, hw_stats->vfgotc); 3637 3638 /* Rx Multicst Packet */ 3639 UPDATE_VF_STAT(IXGBE_VFMPRC, 3640 hw_stats->last_vfmprc, hw_stats->vfmprc); 3641 } 3642 3643 static int 3644 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3645 unsigned n) 3646 { 3647 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3648 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3649 unsigned i; 3650 3651 if (n < IXGBEVF_NB_XSTATS) 3652 return IXGBEVF_NB_XSTATS; 3653 3654 ixgbevf_update_stats(dev); 3655 3656 if (!xstats) 3657 return 0; 3658 3659 /* Extended stats */ 3660 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) { 3661 xstats[i].id = i; 3662 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + 3663 rte_ixgbevf_stats_strings[i].offset); 3664 } 3665 3666 return IXGBEVF_NB_XSTATS; 3667 } 3668 3669 static int 3670 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3671 { 3672 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3673 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3674 3675 ixgbevf_update_stats(dev); 3676 3677 if (stats == NULL) 3678 return -EINVAL; 3679 3680 stats->ipackets = hw_stats->vfgprc; 3681 stats->ibytes = hw_stats->vfgorc; 3682 stats->opackets = hw_stats->vfgptc; 3683 stats->obytes = hw_stats->vfgotc; 3684 return 0; 3685 } 3686 3687 static void 3688 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev) 3689 { 3690 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3691 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3692 3693 /* Sync HW register to the last stats */ 3694 ixgbevf_dev_stats_get(dev, NULL); 3695 3696 /* reset HW current stats*/ 3697 hw_stats->vfgprc = 0; 3698 hw_stats->vfgorc = 0; 3699 hw_stats->vfgptc = 0; 3700 hw_stats->vfgotc = 0; 3701 } 3702 3703 static int 3704 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 3705 { 3706 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3707 u16 eeprom_verh, eeprom_verl; 3708 u32 etrack_id; 3709 int ret; 3710 3711 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh); 3712 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl); 3713 3714 etrack_id = (eeprom_verh << 16) | eeprom_verl; 3715 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id); 3716 3717 ret += 1; /* add the size of '\0' */ 3718 if (fw_size < (u32)ret) 3719 return ret; 3720 else 3721 return 0; 3722 } 3723 3724 static void 3725 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3726 { 3727 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3728 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3729 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 3730 3731 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3732 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3733 if (RTE_ETH_DEV_SRIOV(dev).active == 0) { 3734 /* 3735 * When DCB/VT is off, maximum number of queues changes, 3736 * except for 82598EB, which remains constant. 3737 */ 3738 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 3739 hw->mac.type != ixgbe_mac_82598EB) 3740 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES; 3741 } 3742 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */ 3743 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */ 3744 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3745 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3746 dev_info->max_vfs = pci_dev->max_vfs; 3747 if (hw->mac.type == ixgbe_mac_82598EB) 3748 dev_info->max_vmdq_pools = ETH_16_POOLS; 3749 else 3750 dev_info->max_vmdq_pools = ETH_64_POOLS; 3751 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD; 3752 dev_info->min_mtu = ETHER_MIN_MTU; 3753 dev_info->vmdq_queue_num = dev_info->max_rx_queues; 3754 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3755 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3756 dev_info->rx_queue_offload_capa); 3757 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3758 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3759 3760 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3761 .rx_thresh = { 3762 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3763 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3764 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3765 }, 3766 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3767 .rx_drop_en = 0, 3768 .offloads = 0, 3769 }; 3770 3771 dev_info->default_txconf = (struct rte_eth_txconf) { 3772 .tx_thresh = { 3773 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3774 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3775 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3776 }, 3777 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3778 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3779 .offloads = 0, 3780 }; 3781 3782 dev_info->rx_desc_lim = rx_desc_lim; 3783 dev_info->tx_desc_lim = tx_desc_lim; 3784 3785 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 3786 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 3787 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 3788 3789 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 3790 if (hw->mac.type == ixgbe_mac_X540 || 3791 hw->mac.type == ixgbe_mac_X540_vf || 3792 hw->mac.type == ixgbe_mac_X550 || 3793 hw->mac.type == ixgbe_mac_X550_vf) { 3794 dev_info->speed_capa |= ETH_LINK_SPEED_100M; 3795 } 3796 if (hw->mac.type == ixgbe_mac_X550) { 3797 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G; 3798 dev_info->speed_capa |= ETH_LINK_SPEED_5G; 3799 } 3800 3801 /* Driver-preferred Rx/Tx parameters */ 3802 dev_info->default_rxportconf.burst_size = 32; 3803 dev_info->default_txportconf.burst_size = 32; 3804 dev_info->default_rxportconf.nb_queues = 1; 3805 dev_info->default_txportconf.nb_queues = 1; 3806 dev_info->default_rxportconf.ring_size = 256; 3807 dev_info->default_txportconf.ring_size = 256; 3808 } 3809 3810 static const uint32_t * 3811 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 3812 { 3813 static const uint32_t ptypes[] = { 3814 /* For non-vec functions, 3815 * refers to ixgbe_rxd_pkt_info_to_pkt_type(); 3816 * for vec functions, 3817 * refers to _recv_raw_pkts_vec(). 3818 */ 3819 RTE_PTYPE_L2_ETHER, 3820 RTE_PTYPE_L3_IPV4, 3821 RTE_PTYPE_L3_IPV4_EXT, 3822 RTE_PTYPE_L3_IPV6, 3823 RTE_PTYPE_L3_IPV6_EXT, 3824 RTE_PTYPE_L4_SCTP, 3825 RTE_PTYPE_L4_TCP, 3826 RTE_PTYPE_L4_UDP, 3827 RTE_PTYPE_TUNNEL_IP, 3828 RTE_PTYPE_INNER_L3_IPV6, 3829 RTE_PTYPE_INNER_L3_IPV6_EXT, 3830 RTE_PTYPE_INNER_L4_TCP, 3831 RTE_PTYPE_INNER_L4_UDP, 3832 RTE_PTYPE_UNKNOWN 3833 }; 3834 3835 if (dev->rx_pkt_burst == ixgbe_recv_pkts || 3836 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc || 3837 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc || 3838 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc) 3839 return ptypes; 3840 3841 #if defined(RTE_ARCH_X86) 3842 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec || 3843 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec) 3844 return ptypes; 3845 #endif 3846 return NULL; 3847 } 3848 3849 static void 3850 ixgbevf_dev_info_get(struct rte_eth_dev *dev, 3851 struct rte_eth_dev_info *dev_info) 3852 { 3853 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3854 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3855 3856 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3857 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3858 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */ 3859 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */ 3860 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD; 3861 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3862 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3863 dev_info->max_vfs = pci_dev->max_vfs; 3864 if (hw->mac.type == ixgbe_mac_82598EB) 3865 dev_info->max_vmdq_pools = ETH_16_POOLS; 3866 else 3867 dev_info->max_vmdq_pools = ETH_64_POOLS; 3868 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3869 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3870 dev_info->rx_queue_offload_capa); 3871 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3872 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3873 3874 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3875 .rx_thresh = { 3876 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3877 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3878 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3879 }, 3880 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3881 .rx_drop_en = 0, 3882 .offloads = 0, 3883 }; 3884 3885 dev_info->default_txconf = (struct rte_eth_txconf) { 3886 .tx_thresh = { 3887 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3888 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3889 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3890 }, 3891 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3892 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3893 .offloads = 0, 3894 }; 3895 3896 dev_info->rx_desc_lim = rx_desc_lim; 3897 dev_info->tx_desc_lim = tx_desc_lim; 3898 } 3899 3900 static int 3901 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3902 int *link_up, int wait_to_complete) 3903 { 3904 struct ixgbe_mbx_info *mbx = &hw->mbx; 3905 struct ixgbe_mac_info *mac = &hw->mac; 3906 uint32_t links_reg, in_msg; 3907 int ret_val = 0; 3908 3909 /* If we were hit with a reset drop the link */ 3910 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout) 3911 mac->get_link_status = true; 3912 3913 if (!mac->get_link_status) 3914 goto out; 3915 3916 /* if link status is down no point in checking to see if pf is up */ 3917 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 3918 if (!(links_reg & IXGBE_LINKS_UP)) 3919 goto out; 3920 3921 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs 3922 * before the link status is correct 3923 */ 3924 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) { 3925 int i; 3926 3927 for (i = 0; i < 5; i++) { 3928 rte_delay_us(100); 3929 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 3930 3931 if (!(links_reg & IXGBE_LINKS_UP)) 3932 goto out; 3933 } 3934 } 3935 3936 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 3937 case IXGBE_LINKS_SPEED_10G_82599: 3938 *speed = IXGBE_LINK_SPEED_10GB_FULL; 3939 if (hw->mac.type >= ixgbe_mac_X550) { 3940 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 3941 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 3942 } 3943 break; 3944 case IXGBE_LINKS_SPEED_1G_82599: 3945 *speed = IXGBE_LINK_SPEED_1GB_FULL; 3946 break; 3947 case IXGBE_LINKS_SPEED_100_82599: 3948 *speed = IXGBE_LINK_SPEED_100_FULL; 3949 if (hw->mac.type == ixgbe_mac_X550) { 3950 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 3951 *speed = IXGBE_LINK_SPEED_5GB_FULL; 3952 } 3953 break; 3954 case IXGBE_LINKS_SPEED_10_X550EM_A: 3955 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3956 /* Since Reserved in older MAC's */ 3957 if (hw->mac.type >= ixgbe_mac_X550) 3958 *speed = IXGBE_LINK_SPEED_10_FULL; 3959 break; 3960 default: 3961 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3962 } 3963 3964 /* if the read failed it could just be a mailbox collision, best wait 3965 * until we are called again and don't report an error 3966 */ 3967 if (mbx->ops.read(hw, &in_msg, 1, 0)) 3968 goto out; 3969 3970 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) { 3971 /* msg is not CTS and is NACK we must have lost CTS status */ 3972 if (in_msg & IXGBE_VT_MSGTYPE_NACK) 3973 mac->get_link_status = false; 3974 goto out; 3975 } 3976 3977 /* the pf is talking, if we timed out in the past we reinit */ 3978 if (!mbx->timeout) { 3979 ret_val = -1; 3980 goto out; 3981 } 3982 3983 /* if we passed all the tests above then the link is up and we no 3984 * longer need to check for link 3985 */ 3986 mac->get_link_status = false; 3987 3988 out: 3989 *link_up = !mac->get_link_status; 3990 return ret_val; 3991 } 3992 3993 static void 3994 ixgbe_dev_setup_link_alarm_handler(void *param) 3995 { 3996 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 3997 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3998 struct ixgbe_interrupt *intr = 3999 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4000 u32 speed; 4001 bool autoneg = false; 4002 4003 speed = hw->phy.autoneg_advertised; 4004 if (!speed) 4005 ixgbe_get_link_capabilities(hw, &speed, &autoneg); 4006 4007 ixgbe_setup_link(hw, speed, true); 4008 4009 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 4010 } 4011 4012 /* return 0 means link status changed, -1 means not changed */ 4013 int 4014 ixgbe_dev_link_update_share(struct rte_eth_dev *dev, 4015 int wait_to_complete, int vf) 4016 { 4017 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4018 struct rte_eth_link link; 4019 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4020 struct ixgbe_interrupt *intr = 4021 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4022 int link_up; 4023 int diag; 4024 int wait = 1; 4025 4026 memset(&link, 0, sizeof(link)); 4027 link.link_status = ETH_LINK_DOWN; 4028 link.link_speed = ETH_SPEED_NUM_NONE; 4029 link.link_duplex = ETH_LINK_HALF_DUPLEX; 4030 link.link_autoneg = ETH_LINK_AUTONEG; 4031 4032 hw->mac.get_link_status = true; 4033 4034 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) 4035 return rte_eth_linkstatus_set(dev, &link); 4036 4037 /* check if it needs to wait to complete, if lsc interrupt is enabled */ 4038 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0) 4039 wait = 0; 4040 4041 if (vf) 4042 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait); 4043 else 4044 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait); 4045 4046 if (diag != 0) { 4047 link.link_speed = ETH_SPEED_NUM_100M; 4048 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4049 return rte_eth_linkstatus_set(dev, &link); 4050 } 4051 4052 if (link_up == 0) { 4053 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) { 4054 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 4055 rte_eal_alarm_set(10, 4056 ixgbe_dev_setup_link_alarm_handler, dev); 4057 } 4058 return rte_eth_linkstatus_set(dev, &link); 4059 } 4060 4061 link.link_status = ETH_LINK_UP; 4062 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4063 4064 switch (link_speed) { 4065 default: 4066 case IXGBE_LINK_SPEED_UNKNOWN: 4067 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4068 link.link_speed = ETH_SPEED_NUM_100M; 4069 break; 4070 4071 case IXGBE_LINK_SPEED_100_FULL: 4072 link.link_speed = ETH_SPEED_NUM_100M; 4073 break; 4074 4075 case IXGBE_LINK_SPEED_1GB_FULL: 4076 link.link_speed = ETH_SPEED_NUM_1G; 4077 break; 4078 4079 case IXGBE_LINK_SPEED_2_5GB_FULL: 4080 link.link_speed = ETH_SPEED_NUM_2_5G; 4081 break; 4082 4083 case IXGBE_LINK_SPEED_5GB_FULL: 4084 link.link_speed = ETH_SPEED_NUM_5G; 4085 break; 4086 4087 case IXGBE_LINK_SPEED_10GB_FULL: 4088 link.link_speed = ETH_SPEED_NUM_10G; 4089 break; 4090 } 4091 4092 return rte_eth_linkstatus_set(dev, &link); 4093 } 4094 4095 static int 4096 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4097 { 4098 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0); 4099 } 4100 4101 static int 4102 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4103 { 4104 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1); 4105 } 4106 4107 static void 4108 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 4109 { 4110 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4111 uint32_t fctrl; 4112 4113 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4114 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4115 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4116 } 4117 4118 static void 4119 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 4120 { 4121 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4122 uint32_t fctrl; 4123 4124 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4125 fctrl &= (~IXGBE_FCTRL_UPE); 4126 if (dev->data->all_multicast == 1) 4127 fctrl |= IXGBE_FCTRL_MPE; 4128 else 4129 fctrl &= (~IXGBE_FCTRL_MPE); 4130 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4131 } 4132 4133 static void 4134 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 4135 { 4136 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4137 uint32_t fctrl; 4138 4139 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4140 fctrl |= IXGBE_FCTRL_MPE; 4141 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4142 } 4143 4144 static void 4145 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 4146 { 4147 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4148 uint32_t fctrl; 4149 4150 if (dev->data->promiscuous == 1) 4151 return; /* must remain in all_multicast mode */ 4152 4153 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4154 fctrl &= (~IXGBE_FCTRL_MPE); 4155 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4156 } 4157 4158 /** 4159 * It clears the interrupt causes and enables the interrupt. 4160 * It will be called once only during nic initialized. 4161 * 4162 * @param dev 4163 * Pointer to struct rte_eth_dev. 4164 * @param on 4165 * Enable or Disable. 4166 * 4167 * @return 4168 * - On success, zero. 4169 * - On failure, a negative value. 4170 */ 4171 static int 4172 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 4173 { 4174 struct ixgbe_interrupt *intr = 4175 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4176 4177 ixgbe_dev_link_status_print(dev); 4178 if (on) 4179 intr->mask |= IXGBE_EICR_LSC; 4180 else 4181 intr->mask &= ~IXGBE_EICR_LSC; 4182 4183 return 0; 4184 } 4185 4186 /** 4187 * It clears the interrupt causes and enables the interrupt. 4188 * It will be called once only during nic initialized. 4189 * 4190 * @param dev 4191 * Pointer to struct rte_eth_dev. 4192 * 4193 * @return 4194 * - On success, zero. 4195 * - On failure, a negative value. 4196 */ 4197 static int 4198 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev) 4199 { 4200 struct ixgbe_interrupt *intr = 4201 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4202 4203 intr->mask |= IXGBE_EICR_RTX_QUEUE; 4204 4205 return 0; 4206 } 4207 4208 /** 4209 * It clears the interrupt causes and enables the interrupt. 4210 * It will be called once only during nic initialized. 4211 * 4212 * @param dev 4213 * Pointer to struct rte_eth_dev. 4214 * 4215 * @return 4216 * - On success, zero. 4217 * - On failure, a negative value. 4218 */ 4219 static int 4220 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev) 4221 { 4222 struct ixgbe_interrupt *intr = 4223 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4224 4225 intr->mask |= IXGBE_EICR_LINKSEC; 4226 4227 return 0; 4228 } 4229 4230 /* 4231 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update. 4232 * 4233 * @param dev 4234 * Pointer to struct rte_eth_dev. 4235 * 4236 * @return 4237 * - On success, zero. 4238 * - On failure, a negative value. 4239 */ 4240 static int 4241 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev) 4242 { 4243 uint32_t eicr; 4244 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4245 struct ixgbe_interrupt *intr = 4246 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4247 4248 /* clear all cause mask */ 4249 ixgbe_disable_intr(hw); 4250 4251 /* read-on-clear nic registers here */ 4252 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4253 PMD_DRV_LOG(DEBUG, "eicr %x", eicr); 4254 4255 intr->flags = 0; 4256 4257 /* set flag for async link update */ 4258 if (eicr & IXGBE_EICR_LSC) 4259 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 4260 4261 if (eicr & IXGBE_EICR_MAILBOX) 4262 intr->flags |= IXGBE_FLAG_MAILBOX; 4263 4264 if (eicr & IXGBE_EICR_LINKSEC) 4265 intr->flags |= IXGBE_FLAG_MACSEC; 4266 4267 if (hw->mac.type == ixgbe_mac_X550EM_x && 4268 hw->phy.type == ixgbe_phy_x550em_ext_t && 4269 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x)) 4270 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT; 4271 4272 return 0; 4273 } 4274 4275 /** 4276 * It gets and then prints the link status. 4277 * 4278 * @param dev 4279 * Pointer to struct rte_eth_dev. 4280 * 4281 * @return 4282 * - On success, zero. 4283 * - On failure, a negative value. 4284 */ 4285 static void 4286 ixgbe_dev_link_status_print(struct rte_eth_dev *dev) 4287 { 4288 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4289 struct rte_eth_link link; 4290 4291 rte_eth_linkstatus_get(dev, &link); 4292 4293 if (link.link_status) { 4294 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", 4295 (int)(dev->data->port_id), 4296 (unsigned)link.link_speed, 4297 link.link_duplex == ETH_LINK_FULL_DUPLEX ? 4298 "full-duplex" : "half-duplex"); 4299 } else { 4300 PMD_INIT_LOG(INFO, " Port %d: Link Down", 4301 (int)(dev->data->port_id)); 4302 } 4303 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 4304 pci_dev->addr.domain, 4305 pci_dev->addr.bus, 4306 pci_dev->addr.devid, 4307 pci_dev->addr.function); 4308 } 4309 4310 /* 4311 * It executes link_update after knowing an interrupt occurred. 4312 * 4313 * @param dev 4314 * Pointer to struct rte_eth_dev. 4315 * 4316 * @return 4317 * - On success, zero. 4318 * - On failure, a negative value. 4319 */ 4320 static int 4321 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev) 4322 { 4323 struct ixgbe_interrupt *intr = 4324 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4325 int64_t timeout; 4326 struct ixgbe_hw *hw = 4327 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4328 4329 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags); 4330 4331 if (intr->flags & IXGBE_FLAG_MAILBOX) { 4332 ixgbe_pf_mbx_process(dev); 4333 intr->flags &= ~IXGBE_FLAG_MAILBOX; 4334 } 4335 4336 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4337 ixgbe_handle_lasi(hw); 4338 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4339 } 4340 4341 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4342 struct rte_eth_link link; 4343 4344 /* get the link status before link update, for predicting later */ 4345 rte_eth_linkstatus_get(dev, &link); 4346 4347 ixgbe_dev_link_update(dev, 0); 4348 4349 /* likely to up */ 4350 if (!link.link_status) 4351 /* handle it 1 sec later, wait it being stable */ 4352 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT; 4353 /* likely to down */ 4354 else 4355 /* handle it 4 sec later, wait it being stable */ 4356 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT; 4357 4358 ixgbe_dev_link_status_print(dev); 4359 if (rte_eal_alarm_set(timeout * 1000, 4360 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0) 4361 PMD_DRV_LOG(ERR, "Error setting alarm"); 4362 else { 4363 /* remember original mask */ 4364 intr->mask_original = intr->mask; 4365 /* only disable lsc interrupt */ 4366 intr->mask &= ~IXGBE_EIMS_LSC; 4367 } 4368 } 4369 4370 PMD_DRV_LOG(DEBUG, "enable intr immediately"); 4371 ixgbe_enable_intr(dev); 4372 4373 return 0; 4374 } 4375 4376 /** 4377 * Interrupt handler which shall be registered for alarm callback for delayed 4378 * handling specific interrupt to wait for the stable nic state. As the 4379 * NIC interrupt state is not stable for ixgbe after link is just down, 4380 * it needs to wait 4 seconds to get the stable status. 4381 * 4382 * @param handle 4383 * Pointer to interrupt handle. 4384 * @param param 4385 * The address of parameter (struct rte_eth_dev *) regsitered before. 4386 * 4387 * @return 4388 * void 4389 */ 4390 static void 4391 ixgbe_dev_interrupt_delayed_handler(void *param) 4392 { 4393 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4394 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4395 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4396 struct ixgbe_interrupt *intr = 4397 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4398 struct ixgbe_hw *hw = 4399 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4400 uint32_t eicr; 4401 4402 ixgbe_disable_intr(hw); 4403 4404 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4405 if (eicr & IXGBE_EICR_MAILBOX) 4406 ixgbe_pf_mbx_process(dev); 4407 4408 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4409 ixgbe_handle_lasi(hw); 4410 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4411 } 4412 4413 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4414 ixgbe_dev_link_update(dev, 0); 4415 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 4416 ixgbe_dev_link_status_print(dev); 4417 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, 4418 NULL); 4419 } 4420 4421 if (intr->flags & IXGBE_FLAG_MACSEC) { 4422 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, 4423 NULL); 4424 intr->flags &= ~IXGBE_FLAG_MACSEC; 4425 } 4426 4427 /* restore original mask */ 4428 intr->mask = intr->mask_original; 4429 intr->mask_original = 0; 4430 4431 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr); 4432 ixgbe_enable_intr(dev); 4433 rte_intr_enable(intr_handle); 4434 } 4435 4436 /** 4437 * Interrupt handler triggered by NIC for handling 4438 * specific interrupt. 4439 * 4440 * @param handle 4441 * Pointer to interrupt handle. 4442 * @param param 4443 * The address of parameter (struct rte_eth_dev *) regsitered before. 4444 * 4445 * @return 4446 * void 4447 */ 4448 static void 4449 ixgbe_dev_interrupt_handler(void *param) 4450 { 4451 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4452 4453 ixgbe_dev_interrupt_get_status(dev); 4454 ixgbe_dev_interrupt_action(dev); 4455 } 4456 4457 static int 4458 ixgbe_dev_led_on(struct rte_eth_dev *dev) 4459 { 4460 struct ixgbe_hw *hw; 4461 4462 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4463 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4464 } 4465 4466 static int 4467 ixgbe_dev_led_off(struct rte_eth_dev *dev) 4468 { 4469 struct ixgbe_hw *hw; 4470 4471 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4472 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4473 } 4474 4475 static int 4476 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4477 { 4478 struct ixgbe_hw *hw; 4479 uint32_t mflcn_reg; 4480 uint32_t fccfg_reg; 4481 int rx_pause; 4482 int tx_pause; 4483 4484 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4485 4486 fc_conf->pause_time = hw->fc.pause_time; 4487 fc_conf->high_water = hw->fc.high_water[0]; 4488 fc_conf->low_water = hw->fc.low_water[0]; 4489 fc_conf->send_xon = hw->fc.send_xon; 4490 fc_conf->autoneg = !hw->fc.disable_fc_autoneg; 4491 4492 /* 4493 * Return rx_pause status according to actual setting of 4494 * MFLCN register. 4495 */ 4496 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4497 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE)) 4498 rx_pause = 1; 4499 else 4500 rx_pause = 0; 4501 4502 /* 4503 * Return tx_pause status according to actual setting of 4504 * FCCFG register. 4505 */ 4506 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4507 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY)) 4508 tx_pause = 1; 4509 else 4510 tx_pause = 0; 4511 4512 if (rx_pause && tx_pause) 4513 fc_conf->mode = RTE_FC_FULL; 4514 else if (rx_pause) 4515 fc_conf->mode = RTE_FC_RX_PAUSE; 4516 else if (tx_pause) 4517 fc_conf->mode = RTE_FC_TX_PAUSE; 4518 else 4519 fc_conf->mode = RTE_FC_NONE; 4520 4521 return 0; 4522 } 4523 4524 static int 4525 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4526 { 4527 struct ixgbe_hw *hw; 4528 int err; 4529 uint32_t rx_buf_size; 4530 uint32_t max_high_water; 4531 uint32_t mflcn; 4532 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4533 ixgbe_fc_none, 4534 ixgbe_fc_rx_pause, 4535 ixgbe_fc_tx_pause, 4536 ixgbe_fc_full 4537 }; 4538 4539 PMD_INIT_FUNC_TRACE(); 4540 4541 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4542 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)); 4543 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4544 4545 /* 4546 * At least reserve one Ethernet frame for watermark 4547 * high_water/low_water in kilo bytes for ixgbe 4548 */ 4549 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4550 if ((fc_conf->high_water > max_high_water) || 4551 (fc_conf->high_water < fc_conf->low_water)) { 4552 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4553 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4554 return -EINVAL; 4555 } 4556 4557 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode]; 4558 hw->fc.pause_time = fc_conf->pause_time; 4559 hw->fc.high_water[0] = fc_conf->high_water; 4560 hw->fc.low_water[0] = fc_conf->low_water; 4561 hw->fc.send_xon = fc_conf->send_xon; 4562 hw->fc.disable_fc_autoneg = !fc_conf->autoneg; 4563 4564 err = ixgbe_fc_enable(hw); 4565 4566 /* Not negotiated is not an error case */ 4567 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) { 4568 4569 /* check if we want to forward MAC frames - driver doesn't have native 4570 * capability to do that, so we'll write the registers ourselves */ 4571 4572 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4573 4574 /* set or clear MFLCN.PMCF bit depending on configuration */ 4575 if (fc_conf->mac_ctrl_frame_fwd != 0) 4576 mflcn |= IXGBE_MFLCN_PMCF; 4577 else 4578 mflcn &= ~IXGBE_MFLCN_PMCF; 4579 4580 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn); 4581 IXGBE_WRITE_FLUSH(hw); 4582 4583 return 0; 4584 } 4585 4586 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err); 4587 return -EIO; 4588 } 4589 4590 /** 4591 * ixgbe_pfc_enable_generic - Enable flow control 4592 * @hw: pointer to hardware structure 4593 * @tc_num: traffic class number 4594 * Enable flow control according to the current settings. 4595 */ 4596 static int 4597 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num) 4598 { 4599 int ret_val = 0; 4600 uint32_t mflcn_reg, fccfg_reg; 4601 uint32_t reg; 4602 uint32_t fcrtl, fcrth; 4603 uint8_t i; 4604 uint8_t nb_rx_en; 4605 4606 /* Validate the water mark configuration */ 4607 if (!hw->fc.pause_time) { 4608 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4609 goto out; 4610 } 4611 4612 /* Low water mark of zero causes XOFF floods */ 4613 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 4614 /* High/Low water can not be 0 */ 4615 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) { 4616 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4617 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4618 goto out; 4619 } 4620 4621 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) { 4622 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4623 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4624 goto out; 4625 } 4626 } 4627 /* Negotiate the fc mode to use */ 4628 ixgbe_fc_autoneg(hw); 4629 4630 /* Disable any previous flow control settings */ 4631 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4632 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE); 4633 4634 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4635 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 4636 4637 switch (hw->fc.current_mode) { 4638 case ixgbe_fc_none: 4639 /* 4640 * If the count of enabled RX Priority Flow control >1, 4641 * and the TX pause can not be disabled 4642 */ 4643 nb_rx_en = 0; 4644 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4645 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4646 if (reg & IXGBE_FCRTH_FCEN) 4647 nb_rx_en++; 4648 } 4649 if (nb_rx_en > 1) 4650 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4651 break; 4652 case ixgbe_fc_rx_pause: 4653 /* 4654 * Rx Flow control is enabled and Tx Flow control is 4655 * disabled by software override. Since there really 4656 * isn't a way to advertise that we are capable of RX 4657 * Pause ONLY, we will advertise that we support both 4658 * symmetric and asymmetric Rx PAUSE. Later, we will 4659 * disable the adapter's ability to send PAUSE frames. 4660 */ 4661 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4662 /* 4663 * If the count of enabled RX Priority Flow control >1, 4664 * and the TX pause can not be disabled 4665 */ 4666 nb_rx_en = 0; 4667 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4668 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4669 if (reg & IXGBE_FCRTH_FCEN) 4670 nb_rx_en++; 4671 } 4672 if (nb_rx_en > 1) 4673 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4674 break; 4675 case ixgbe_fc_tx_pause: 4676 /* 4677 * Tx Flow control is enabled, and Rx Flow control is 4678 * disabled by software override. 4679 */ 4680 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4681 break; 4682 case ixgbe_fc_full: 4683 /* Flow control (both Rx and Tx) is enabled by SW override. */ 4684 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4685 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4686 break; 4687 default: 4688 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly"); 4689 ret_val = IXGBE_ERR_CONFIG; 4690 goto out; 4691 } 4692 4693 /* Set 802.3x based flow control settings. */ 4694 mflcn_reg |= IXGBE_MFLCN_DPF; 4695 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 4696 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 4697 4698 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 4699 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 4700 hw->fc.high_water[tc_num]) { 4701 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE; 4702 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl); 4703 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN; 4704 } else { 4705 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0); 4706 /* 4707 * In order to prevent Tx hangs when the internal Tx 4708 * switch is enabled we must set the high water mark 4709 * to the maximum FCRTH value. This allows the Tx 4710 * switch to function even under heavy Rx workloads. 4711 */ 4712 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32; 4713 } 4714 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth); 4715 4716 /* Configure pause time (2 TCs per register) */ 4717 reg = hw->fc.pause_time * 0x00010001; 4718 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 4719 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 4720 4721 /* Configure flow control refresh threshold value */ 4722 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 4723 4724 out: 4725 return ret_val; 4726 } 4727 4728 static int 4729 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num) 4730 { 4731 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4732 int32_t ret_val = IXGBE_NOT_IMPLEMENTED; 4733 4734 if (hw->mac.type != ixgbe_mac_82598EB) { 4735 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num); 4736 } 4737 return ret_val; 4738 } 4739 4740 static int 4741 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf) 4742 { 4743 int err; 4744 uint32_t rx_buf_size; 4745 uint32_t max_high_water; 4746 uint8_t tc_num; 4747 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 4748 struct ixgbe_hw *hw = 4749 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4750 struct ixgbe_dcb_config *dcb_config = 4751 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 4752 4753 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4754 ixgbe_fc_none, 4755 ixgbe_fc_rx_pause, 4756 ixgbe_fc_tx_pause, 4757 ixgbe_fc_full 4758 }; 4759 4760 PMD_INIT_FUNC_TRACE(); 4761 4762 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map); 4763 tc_num = map[pfc_conf->priority]; 4764 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)); 4765 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4766 /* 4767 * At least reserve one Ethernet frame for watermark 4768 * high_water/low_water in kilo bytes for ixgbe 4769 */ 4770 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4771 if ((pfc_conf->fc.high_water > max_high_water) || 4772 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) { 4773 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4774 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4775 return -EINVAL; 4776 } 4777 4778 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode]; 4779 hw->fc.pause_time = pfc_conf->fc.pause_time; 4780 hw->fc.send_xon = pfc_conf->fc.send_xon; 4781 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water; 4782 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; 4783 4784 err = ixgbe_dcb_pfc_enable(dev, tc_num); 4785 4786 /* Not negotiated is not an error case */ 4787 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) 4788 return 0; 4789 4790 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err); 4791 return -EIO; 4792 } 4793 4794 static int 4795 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 4796 struct rte_eth_rss_reta_entry64 *reta_conf, 4797 uint16_t reta_size) 4798 { 4799 uint16_t i, sp_reta_size; 4800 uint8_t j, mask; 4801 uint32_t reta, r; 4802 uint16_t idx, shift; 4803 struct ixgbe_adapter *adapter = 4804 (struct ixgbe_adapter *)dev->data->dev_private; 4805 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4806 uint32_t reta_reg; 4807 4808 PMD_INIT_FUNC_TRACE(); 4809 4810 if (!ixgbe_rss_update_sp(hw->mac.type)) { 4811 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " 4812 "NIC."); 4813 return -ENOTSUP; 4814 } 4815 4816 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 4817 if (reta_size != sp_reta_size) { 4818 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 4819 "(%d) doesn't match the number hardware can supported " 4820 "(%d)", reta_size, sp_reta_size); 4821 return -EINVAL; 4822 } 4823 4824 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 4825 idx = i / RTE_RETA_GROUP_SIZE; 4826 shift = i % RTE_RETA_GROUP_SIZE; 4827 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 4828 IXGBE_4_BIT_MASK); 4829 if (!mask) 4830 continue; 4831 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 4832 if (mask == IXGBE_4_BIT_MASK) 4833 r = 0; 4834 else 4835 r = IXGBE_READ_REG(hw, reta_reg); 4836 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) { 4837 if (mask & (0x1 << j)) 4838 reta |= reta_conf[idx].reta[shift + j] << 4839 (CHAR_BIT * j); 4840 else 4841 reta |= r & (IXGBE_8_BIT_MASK << 4842 (CHAR_BIT * j)); 4843 } 4844 IXGBE_WRITE_REG(hw, reta_reg, reta); 4845 } 4846 adapter->rss_reta_updated = 1; 4847 4848 return 0; 4849 } 4850 4851 static int 4852 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 4853 struct rte_eth_rss_reta_entry64 *reta_conf, 4854 uint16_t reta_size) 4855 { 4856 uint16_t i, sp_reta_size; 4857 uint8_t j, mask; 4858 uint32_t reta; 4859 uint16_t idx, shift; 4860 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4861 uint32_t reta_reg; 4862 4863 PMD_INIT_FUNC_TRACE(); 4864 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 4865 if (reta_size != sp_reta_size) { 4866 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 4867 "(%d) doesn't match the number hardware can supported " 4868 "(%d)", reta_size, sp_reta_size); 4869 return -EINVAL; 4870 } 4871 4872 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 4873 idx = i / RTE_RETA_GROUP_SIZE; 4874 shift = i % RTE_RETA_GROUP_SIZE; 4875 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 4876 IXGBE_4_BIT_MASK); 4877 if (!mask) 4878 continue; 4879 4880 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 4881 reta = IXGBE_READ_REG(hw, reta_reg); 4882 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) { 4883 if (mask & (0x1 << j)) 4884 reta_conf[idx].reta[shift + j] = 4885 ((reta >> (CHAR_BIT * j)) & 4886 IXGBE_8_BIT_MASK); 4887 } 4888 } 4889 4890 return 0; 4891 } 4892 4893 static int 4894 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr, 4895 uint32_t index, uint32_t pool) 4896 { 4897 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4898 uint32_t enable_addr = 1; 4899 4900 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes, 4901 pool, enable_addr); 4902 } 4903 4904 static void 4905 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) 4906 { 4907 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4908 4909 ixgbe_clear_rar(hw, index); 4910 } 4911 4912 static int 4913 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr) 4914 { 4915 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4916 4917 ixgbe_remove_rar(dev, 0); 4918 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs); 4919 4920 return 0; 4921 } 4922 4923 static bool 4924 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 4925 { 4926 if (strcmp(dev->device->driver->name, drv->driver.name)) 4927 return false; 4928 4929 return true; 4930 } 4931 4932 bool 4933 is_ixgbe_supported(struct rte_eth_dev *dev) 4934 { 4935 return is_device_supported(dev, &rte_ixgbe_pmd); 4936 } 4937 4938 static int 4939 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 4940 { 4941 uint32_t hlreg0; 4942 uint32_t maxfrs; 4943 struct ixgbe_hw *hw; 4944 struct rte_eth_dev_info dev_info; 4945 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD; 4946 struct rte_eth_dev_data *dev_data = dev->data; 4947 4948 ixgbe_dev_info_get(dev, &dev_info); 4949 4950 /* check that mtu is within the allowed range */ 4951 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) 4952 return -EINVAL; 4953 4954 /* If device is started, refuse mtu that requires the support of 4955 * scattered packets when this feature has not been enabled before. 4956 */ 4957 if (dev_data->dev_started && !dev_data->scattered_rx && 4958 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE > 4959 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 4960 PMD_INIT_LOG(ERR, "Stop port first."); 4961 return -EINVAL; 4962 } 4963 4964 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4965 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4966 4967 /* switch to jumbo mode if needed */ 4968 if (frame_size > ETHER_MAX_LEN) { 4969 dev->data->dev_conf.rxmode.offloads |= 4970 DEV_RX_OFFLOAD_JUMBO_FRAME; 4971 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4972 } else { 4973 dev->data->dev_conf.rxmode.offloads &= 4974 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 4975 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; 4976 } 4977 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4978 4979 /* update max frame size */ 4980 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 4981 4982 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS); 4983 maxfrs &= 0x0000FFFF; 4984 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16); 4985 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs); 4986 4987 return 0; 4988 } 4989 4990 /* 4991 * Virtual Function operations 4992 */ 4993 static void 4994 ixgbevf_intr_disable(struct rte_eth_dev *dev) 4995 { 4996 struct ixgbe_interrupt *intr = 4997 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4998 struct ixgbe_hw *hw = 4999 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5000 5001 PMD_INIT_FUNC_TRACE(); 5002 5003 /* Clear interrupt mask to stop from interrupts being generated */ 5004 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK); 5005 5006 IXGBE_WRITE_FLUSH(hw); 5007 5008 /* Clear mask value. */ 5009 intr->mask = 0; 5010 } 5011 5012 static void 5013 ixgbevf_intr_enable(struct rte_eth_dev *dev) 5014 { 5015 struct ixgbe_interrupt *intr = 5016 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5017 struct ixgbe_hw *hw = 5018 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5019 5020 PMD_INIT_FUNC_TRACE(); 5021 5022 /* VF enable interrupt autoclean */ 5023 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK); 5024 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK); 5025 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK); 5026 5027 IXGBE_WRITE_FLUSH(hw); 5028 5029 /* Save IXGBE_VTEIMS value to mask. */ 5030 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK; 5031 } 5032 5033 static int 5034 ixgbevf_dev_configure(struct rte_eth_dev *dev) 5035 { 5036 struct rte_eth_conf *conf = &dev->data->dev_conf; 5037 struct ixgbe_adapter *adapter = 5038 (struct ixgbe_adapter *)dev->data->dev_private; 5039 5040 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d", 5041 dev->data->port_id); 5042 5043 /* 5044 * VF has no ability to enable/disable HW CRC 5045 * Keep the persistent behavior the same as Host PF 5046 */ 5047 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC 5048 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) { 5049 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip"); 5050 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC; 5051 } 5052 #else 5053 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) { 5054 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip"); 5055 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC; 5056 } 5057 #endif 5058 5059 /* 5060 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 5061 * allocation or vector Rx preconditions we will reset it. 5062 */ 5063 adapter->rx_bulk_alloc_allowed = true; 5064 adapter->rx_vec_allowed = true; 5065 5066 return 0; 5067 } 5068 5069 static int 5070 ixgbevf_dev_start(struct rte_eth_dev *dev) 5071 { 5072 struct ixgbe_hw *hw = 5073 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5074 uint32_t intr_vector = 0; 5075 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5076 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5077 5078 int err, mask = 0; 5079 5080 PMD_INIT_FUNC_TRACE(); 5081 5082 /* Stop the link setup handler before resetting the HW. */ 5083 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 5084 5085 err = hw->mac.ops.reset_hw(hw); 5086 if (err) { 5087 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err); 5088 return err; 5089 } 5090 hw->mac.get_link_status = true; 5091 5092 /* negotiate mailbox API version to use with the PF. */ 5093 ixgbevf_negotiate_api(hw); 5094 5095 ixgbevf_dev_tx_init(dev); 5096 5097 /* This can fail when allocating mbufs for descriptor rings */ 5098 err = ixgbevf_dev_rx_init(dev); 5099 if (err) { 5100 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err); 5101 ixgbe_dev_clear_queues(dev); 5102 return err; 5103 } 5104 5105 /* Set vfta */ 5106 ixgbevf_set_vfta_all(dev, 1); 5107 5108 /* Set HW strip */ 5109 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 5110 ETH_VLAN_EXTEND_MASK; 5111 err = ixgbevf_vlan_offload_config(dev, mask); 5112 if (err) { 5113 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err); 5114 ixgbe_dev_clear_queues(dev); 5115 return err; 5116 } 5117 5118 ixgbevf_dev_rxtx_start(dev); 5119 5120 /* check and configure queue intr-vector mapping */ 5121 if (rte_intr_cap_multiple(intr_handle) && 5122 dev->data->dev_conf.intr_conf.rxq) { 5123 /* According to datasheet, only vector 0/1/2 can be used, 5124 * now only one vector is used for Rx queue 5125 */ 5126 intr_vector = 1; 5127 if (rte_intr_efd_enable(intr_handle, intr_vector)) 5128 return -1; 5129 } 5130 5131 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 5132 intr_handle->intr_vec = 5133 rte_zmalloc("intr_vec", 5134 dev->data->nb_rx_queues * sizeof(int), 0); 5135 if (intr_handle->intr_vec == NULL) { 5136 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 5137 " intr_vec", dev->data->nb_rx_queues); 5138 return -ENOMEM; 5139 } 5140 } 5141 ixgbevf_configure_msix(dev); 5142 5143 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt 5144 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ). 5145 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( ) 5146 * is not cleared, it will fail when following rte_intr_enable( ) tries 5147 * to map Rx queue interrupt to other VFIO vectors. 5148 * So clear uio/vfio intr/evevnfd first to avoid failure. 5149 */ 5150 rte_intr_disable(intr_handle); 5151 5152 rte_intr_enable(intr_handle); 5153 5154 /* Re-enable interrupt for VF */ 5155 ixgbevf_intr_enable(dev); 5156 5157 /* 5158 * Update link status right before return, because it may 5159 * start link configuration process in a separate thread. 5160 */ 5161 ixgbevf_dev_link_update(dev, 0); 5162 5163 return 0; 5164 } 5165 5166 static void 5167 ixgbevf_dev_stop(struct rte_eth_dev *dev) 5168 { 5169 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5170 struct ixgbe_adapter *adapter = 5171 (struct ixgbe_adapter *)dev->data->dev_private; 5172 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5173 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5174 5175 PMD_INIT_FUNC_TRACE(); 5176 5177 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 5178 5179 ixgbevf_intr_disable(dev); 5180 5181 hw->adapter_stopped = 1; 5182 ixgbe_stop_adapter(hw); 5183 5184 /* 5185 * Clear what we set, but we still keep shadow_vfta to 5186 * restore after device starts 5187 */ 5188 ixgbevf_set_vfta_all(dev, 0); 5189 5190 /* Clear stored conf */ 5191 dev->data->scattered_rx = 0; 5192 5193 ixgbe_dev_clear_queues(dev); 5194 5195 /* Clean datapath event and queue/vec mapping */ 5196 rte_intr_efd_disable(intr_handle); 5197 if (intr_handle->intr_vec != NULL) { 5198 rte_free(intr_handle->intr_vec); 5199 intr_handle->intr_vec = NULL; 5200 } 5201 5202 adapter->rss_reta_updated = 0; 5203 } 5204 5205 static void 5206 ixgbevf_dev_close(struct rte_eth_dev *dev) 5207 { 5208 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5209 5210 PMD_INIT_FUNC_TRACE(); 5211 5212 ixgbe_reset_hw(hw); 5213 5214 ixgbevf_dev_stop(dev); 5215 5216 ixgbe_dev_free_queues(dev); 5217 5218 /** 5219 * Remove the VF MAC address ro ensure 5220 * that the VF traffic goes to the PF 5221 * after stop, close and detach of the VF 5222 **/ 5223 ixgbevf_remove_mac_addr(dev, 0); 5224 } 5225 5226 /* 5227 * Reset VF device 5228 */ 5229 static int 5230 ixgbevf_dev_reset(struct rte_eth_dev *dev) 5231 { 5232 int ret; 5233 5234 ret = eth_ixgbevf_dev_uninit(dev); 5235 if (ret) 5236 return ret; 5237 5238 ret = eth_ixgbevf_dev_init(dev); 5239 5240 return ret; 5241 } 5242 5243 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) 5244 { 5245 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5246 struct ixgbe_vfta *shadow_vfta = 5247 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5248 int i = 0, j = 0, vfta = 0, mask = 1; 5249 5250 for (i = 0; i < IXGBE_VFTA_SIZE; i++) { 5251 vfta = shadow_vfta->vfta[i]; 5252 if (vfta) { 5253 mask = 1; 5254 for (j = 0; j < 32; j++) { 5255 if (vfta & mask) 5256 ixgbe_set_vfta(hw, (i<<5)+j, 0, 5257 on, false); 5258 mask <<= 1; 5259 } 5260 } 5261 } 5262 5263 } 5264 5265 static int 5266 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 5267 { 5268 struct ixgbe_hw *hw = 5269 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5270 struct ixgbe_vfta *shadow_vfta = 5271 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5272 uint32_t vid_idx = 0; 5273 uint32_t vid_bit = 0; 5274 int ret = 0; 5275 5276 PMD_INIT_FUNC_TRACE(); 5277 5278 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */ 5279 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false); 5280 if (ret) { 5281 PMD_INIT_LOG(ERR, "Unable to set VF vlan"); 5282 return ret; 5283 } 5284 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 5285 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 5286 5287 /* Save what we set and retore it after device reset */ 5288 if (on) 5289 shadow_vfta->vfta[vid_idx] |= vid_bit; 5290 else 5291 shadow_vfta->vfta[vid_idx] &= ~vid_bit; 5292 5293 return 0; 5294 } 5295 5296 static void 5297 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 5298 { 5299 struct ixgbe_hw *hw = 5300 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5301 uint32_t ctrl; 5302 5303 PMD_INIT_FUNC_TRACE(); 5304 5305 if (queue >= hw->mac.max_rx_queues) 5306 return; 5307 5308 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 5309 if (on) 5310 ctrl |= IXGBE_RXDCTL_VME; 5311 else 5312 ctrl &= ~IXGBE_RXDCTL_VME; 5313 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 5314 5315 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on); 5316 } 5317 5318 static int 5319 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask) 5320 { 5321 struct ixgbe_rx_queue *rxq; 5322 uint16_t i; 5323 int on = 0; 5324 5325 /* VF function only support hw strip feature, others are not support */ 5326 if (mask & ETH_VLAN_STRIP_MASK) { 5327 for (i = 0; i < dev->data->nb_rx_queues; i++) { 5328 rxq = dev->data->rx_queues[i]; 5329 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP); 5330 ixgbevf_vlan_strip_queue_set(dev, i, on); 5331 } 5332 } 5333 5334 return 0; 5335 } 5336 5337 static int 5338 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 5339 { 5340 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 5341 5342 ixgbevf_vlan_offload_config(dev, mask); 5343 5344 return 0; 5345 } 5346 5347 int 5348 ixgbe_vt_check(struct ixgbe_hw *hw) 5349 { 5350 uint32_t reg_val; 5351 5352 /* if Virtualization Technology is enabled */ 5353 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 5354 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) { 5355 PMD_INIT_LOG(ERR, "VT must be enabled for this setting"); 5356 return -1; 5357 } 5358 5359 return 0; 5360 } 5361 5362 static uint32_t 5363 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr) 5364 { 5365 uint32_t vector = 0; 5366 5367 switch (hw->mac.mc_filter_type) { 5368 case 0: /* use bits [47:36] of the address */ 5369 vector = ((uc_addr->addr_bytes[4] >> 4) | 5370 (((uint16_t)uc_addr->addr_bytes[5]) << 4)); 5371 break; 5372 case 1: /* use bits [46:35] of the address */ 5373 vector = ((uc_addr->addr_bytes[4] >> 3) | 5374 (((uint16_t)uc_addr->addr_bytes[5]) << 5)); 5375 break; 5376 case 2: /* use bits [45:34] of the address */ 5377 vector = ((uc_addr->addr_bytes[4] >> 2) | 5378 (((uint16_t)uc_addr->addr_bytes[5]) << 6)); 5379 break; 5380 case 3: /* use bits [43:32] of the address */ 5381 vector = ((uc_addr->addr_bytes[4]) | 5382 (((uint16_t)uc_addr->addr_bytes[5]) << 8)); 5383 break; 5384 default: /* Invalid mc_filter_type */ 5385 break; 5386 } 5387 5388 /* vector can only be 12-bits or boundary will be exceeded */ 5389 vector &= 0xFFF; 5390 return vector; 5391 } 5392 5393 static int 5394 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr, 5395 uint8_t on) 5396 { 5397 uint32_t vector; 5398 uint32_t uta_idx; 5399 uint32_t reg_val; 5400 uint32_t uta_shift; 5401 uint32_t rc; 5402 const uint32_t ixgbe_uta_idx_mask = 0x7F; 5403 const uint32_t ixgbe_uta_bit_shift = 5; 5404 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1; 5405 const uint32_t bit1 = 0x1; 5406 5407 struct ixgbe_hw *hw = 5408 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5409 struct ixgbe_uta_info *uta_info = 5410 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5411 5412 /* The UTA table only exists on 82599 hardware and newer */ 5413 if (hw->mac.type < ixgbe_mac_82599EB) 5414 return -ENOTSUP; 5415 5416 vector = ixgbe_uta_vector(hw, mac_addr); 5417 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask; 5418 uta_shift = vector & ixgbe_uta_bit_mask; 5419 5420 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0); 5421 if (rc == on) 5422 return 0; 5423 5424 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx)); 5425 if (on) { 5426 uta_info->uta_in_use++; 5427 reg_val |= (bit1 << uta_shift); 5428 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift); 5429 } else { 5430 uta_info->uta_in_use--; 5431 reg_val &= ~(bit1 << uta_shift); 5432 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift); 5433 } 5434 5435 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val); 5436 5437 if (uta_info->uta_in_use > 0) 5438 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 5439 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 5440 else 5441 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 5442 5443 return 0; 5444 } 5445 5446 static int 5447 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) 5448 { 5449 int i; 5450 struct ixgbe_hw *hw = 5451 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5452 struct ixgbe_uta_info *uta_info = 5453 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5454 5455 /* The UTA table only exists on 82599 hardware and newer */ 5456 if (hw->mac.type < ixgbe_mac_82599EB) 5457 return -ENOTSUP; 5458 5459 if (on) { 5460 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5461 uta_info->uta_shadow[i] = ~0; 5462 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); 5463 } 5464 } else { 5465 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5466 uta_info->uta_shadow[i] = 0; 5467 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 5468 } 5469 } 5470 return 0; 5471 5472 } 5473 5474 uint32_t 5475 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val) 5476 { 5477 uint32_t new_val = orig_val; 5478 5479 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG) 5480 new_val |= IXGBE_VMOLR_AUPE; 5481 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC) 5482 new_val |= IXGBE_VMOLR_ROMPE; 5483 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC) 5484 new_val |= IXGBE_VMOLR_ROPE; 5485 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST) 5486 new_val |= IXGBE_VMOLR_BAM; 5487 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST) 5488 new_val |= IXGBE_VMOLR_MPE; 5489 5490 return new_val; 5491 } 5492 5493 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */ 5494 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */ 5495 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */ 5496 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */ 5497 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \ 5498 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \ 5499 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN)) 5500 5501 static int 5502 ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 5503 struct rte_eth_mirror_conf *mirror_conf, 5504 uint8_t rule_id, uint8_t on) 5505 { 5506 uint32_t mr_ctl, vlvf; 5507 uint32_t mp_lsb = 0; 5508 uint32_t mv_msb = 0; 5509 uint32_t mv_lsb = 0; 5510 uint32_t mp_msb = 0; 5511 uint8_t i = 0; 5512 int reg_index = 0; 5513 uint64_t vlan_mask = 0; 5514 5515 const uint8_t pool_mask_offset = 32; 5516 const uint8_t vlan_mask_offset = 32; 5517 const uint8_t dst_pool_offset = 8; 5518 const uint8_t rule_mr_offset = 4; 5519 const uint8_t mirror_rule_mask = 0x0F; 5520 5521 struct ixgbe_mirror_info *mr_info = 5522 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5523 struct ixgbe_hw *hw = 5524 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5525 uint8_t mirror_type = 0; 5526 5527 if (ixgbe_vt_check(hw) < 0) 5528 return -ENOTSUP; 5529 5530 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5531 return -EINVAL; 5532 5533 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) { 5534 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.", 5535 mirror_conf->rule_type); 5536 return -EINVAL; 5537 } 5538 5539 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5540 mirror_type |= IXGBE_MRCTL_VLME; 5541 /* Check if vlan id is valid and find conresponding VLAN ID 5542 * index in VLVF 5543 */ 5544 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) { 5545 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) { 5546 /* search vlan id related pool vlan filter 5547 * index 5548 */ 5549 reg_index = ixgbe_find_vlvf_slot( 5550 hw, 5551 mirror_conf->vlan.vlan_id[i], 5552 false); 5553 if (reg_index < 0) 5554 return -EINVAL; 5555 vlvf = IXGBE_READ_REG(hw, 5556 IXGBE_VLVF(reg_index)); 5557 if ((vlvf & IXGBE_VLVF_VIEN) && 5558 ((vlvf & IXGBE_VLVF_VLANID_MASK) == 5559 mirror_conf->vlan.vlan_id[i])) 5560 vlan_mask |= (1ULL << reg_index); 5561 else 5562 return -EINVAL; 5563 } 5564 } 5565 5566 if (on) { 5567 mv_lsb = vlan_mask & 0xFFFFFFFF; 5568 mv_msb = vlan_mask >> vlan_mask_offset; 5569 5570 mr_info->mr_conf[rule_id].vlan.vlan_mask = 5571 mirror_conf->vlan.vlan_mask; 5572 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) { 5573 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) 5574 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 5575 mirror_conf->vlan.vlan_id[i]; 5576 } 5577 } else { 5578 mv_lsb = 0; 5579 mv_msb = 0; 5580 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0; 5581 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) 5582 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0; 5583 } 5584 } 5585 5586 /** 5587 * if enable pool mirror, write related pool mask register,if disable 5588 * pool mirror, clear PFMRVM register 5589 */ 5590 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5591 mirror_type |= IXGBE_MRCTL_VPME; 5592 if (on) { 5593 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF; 5594 mp_msb = mirror_conf->pool_mask >> pool_mask_offset; 5595 mr_info->mr_conf[rule_id].pool_mask = 5596 mirror_conf->pool_mask; 5597 5598 } else { 5599 mp_lsb = 0; 5600 mp_msb = 0; 5601 mr_info->mr_conf[rule_id].pool_mask = 0; 5602 } 5603 } 5604 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT) 5605 mirror_type |= IXGBE_MRCTL_UPME; 5606 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT) 5607 mirror_type |= IXGBE_MRCTL_DPME; 5608 5609 /* read mirror control register and recalculate it */ 5610 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id)); 5611 5612 if (on) { 5613 mr_ctl |= mirror_type; 5614 mr_ctl &= mirror_rule_mask; 5615 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset; 5616 } else { 5617 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask); 5618 } 5619 5620 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type; 5621 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool; 5622 5623 /* write mirrror control register */ 5624 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5625 5626 /* write pool mirrror control register */ 5627 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5628 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb); 5629 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), 5630 mp_msb); 5631 } 5632 /* write VLAN mirrror control register */ 5633 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5634 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb); 5635 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), 5636 mv_msb); 5637 } 5638 5639 return 0; 5640 } 5641 5642 static int 5643 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id) 5644 { 5645 int mr_ctl = 0; 5646 uint32_t lsb_val = 0; 5647 uint32_t msb_val = 0; 5648 const uint8_t rule_mr_offset = 4; 5649 5650 struct ixgbe_hw *hw = 5651 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5652 struct ixgbe_mirror_info *mr_info = 5653 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5654 5655 if (ixgbe_vt_check(hw) < 0) 5656 return -ENOTSUP; 5657 5658 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5659 return -EINVAL; 5660 5661 memset(&mr_info->mr_conf[rule_id], 0, 5662 sizeof(struct rte_eth_mirror_conf)); 5663 5664 /* clear PFVMCTL register */ 5665 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5666 5667 /* clear pool mask register */ 5668 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val); 5669 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val); 5670 5671 /* clear vlan mask register */ 5672 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val); 5673 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val); 5674 5675 return 0; 5676 } 5677 5678 static int 5679 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5680 { 5681 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5682 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5683 struct ixgbe_interrupt *intr = 5684 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5685 struct ixgbe_hw *hw = 5686 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5687 uint32_t vec = IXGBE_MISC_VEC_ID; 5688 5689 if (rte_intr_allow_others(intr_handle)) 5690 vec = IXGBE_RX_VEC_START; 5691 intr->mask |= (1 << vec); 5692 RTE_SET_USED(queue_id); 5693 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5694 5695 rte_intr_enable(intr_handle); 5696 5697 return 0; 5698 } 5699 5700 static int 5701 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5702 { 5703 struct ixgbe_interrupt *intr = 5704 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5705 struct ixgbe_hw *hw = 5706 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5707 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5708 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5709 uint32_t vec = IXGBE_MISC_VEC_ID; 5710 5711 if (rte_intr_allow_others(intr_handle)) 5712 vec = IXGBE_RX_VEC_START; 5713 intr->mask &= ~(1 << vec); 5714 RTE_SET_USED(queue_id); 5715 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5716 5717 return 0; 5718 } 5719 5720 static int 5721 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5722 { 5723 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5724 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5725 uint32_t mask; 5726 struct ixgbe_hw *hw = 5727 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5728 struct ixgbe_interrupt *intr = 5729 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5730 5731 if (queue_id < 16) { 5732 ixgbe_disable_intr(hw); 5733 intr->mask |= (1 << queue_id); 5734 ixgbe_enable_intr(dev); 5735 } else if (queue_id < 32) { 5736 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5737 mask &= (1 << queue_id); 5738 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5739 } else if (queue_id < 64) { 5740 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5741 mask &= (1 << (queue_id - 32)); 5742 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5743 } 5744 rte_intr_enable(intr_handle); 5745 5746 return 0; 5747 } 5748 5749 static int 5750 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5751 { 5752 uint32_t mask; 5753 struct ixgbe_hw *hw = 5754 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5755 struct ixgbe_interrupt *intr = 5756 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5757 5758 if (queue_id < 16) { 5759 ixgbe_disable_intr(hw); 5760 intr->mask &= ~(1 << queue_id); 5761 ixgbe_enable_intr(dev); 5762 } else if (queue_id < 32) { 5763 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5764 mask &= ~(1 << queue_id); 5765 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5766 } else if (queue_id < 64) { 5767 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5768 mask &= ~(1 << (queue_id - 32)); 5769 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5770 } 5771 5772 return 0; 5773 } 5774 5775 static void 5776 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 5777 uint8_t queue, uint8_t msix_vector) 5778 { 5779 uint32_t tmp, idx; 5780 5781 if (direction == -1) { 5782 /* other causes */ 5783 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5784 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC); 5785 tmp &= ~0xFF; 5786 tmp |= msix_vector; 5787 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp); 5788 } else { 5789 /* rx or tx cause */ 5790 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5791 idx = ((16 * (queue & 1)) + (8 * direction)); 5792 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1)); 5793 tmp &= ~(0xFF << idx); 5794 tmp |= (msix_vector << idx); 5795 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp); 5796 } 5797 } 5798 5799 /** 5800 * set the IVAR registers, mapping interrupt causes to vectors 5801 * @param hw 5802 * pointer to ixgbe_hw struct 5803 * @direction 5804 * 0 for Rx, 1 for Tx, -1 for other causes 5805 * @queue 5806 * queue to map the corresponding interrupt to 5807 * @msix_vector 5808 * the vector to map to the corresponding queue 5809 */ 5810 static void 5811 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 5812 uint8_t queue, uint8_t msix_vector) 5813 { 5814 uint32_t tmp, idx; 5815 5816 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5817 if (hw->mac.type == ixgbe_mac_82598EB) { 5818 if (direction == -1) 5819 direction = 0; 5820 idx = (((direction * 64) + queue) >> 2) & 0x1F; 5821 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx)); 5822 tmp &= ~(0xFF << (8 * (queue & 0x3))); 5823 tmp |= (msix_vector << (8 * (queue & 0x3))); 5824 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp); 5825 } else if ((hw->mac.type == ixgbe_mac_82599EB) || 5826 (hw->mac.type == ixgbe_mac_X540) || 5827 (hw->mac.type == ixgbe_mac_X550)) { 5828 if (direction == -1) { 5829 /* other causes */ 5830 idx = ((queue & 1) * 8); 5831 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC); 5832 tmp &= ~(0xFF << idx); 5833 tmp |= (msix_vector << idx); 5834 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp); 5835 } else { 5836 /* rx or tx causes */ 5837 idx = ((16 * (queue & 1)) + (8 * direction)); 5838 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 5839 tmp &= ~(0xFF << idx); 5840 tmp |= (msix_vector << idx); 5841 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp); 5842 } 5843 } 5844 } 5845 5846 static void 5847 ixgbevf_configure_msix(struct rte_eth_dev *dev) 5848 { 5849 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5850 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5851 struct ixgbe_hw *hw = 5852 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5853 uint32_t q_idx; 5854 uint32_t vector_idx = IXGBE_MISC_VEC_ID; 5855 uint32_t base = IXGBE_MISC_VEC_ID; 5856 5857 /* Configure VF other cause ivar */ 5858 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx); 5859 5860 /* won't configure msix register if no mapping is done 5861 * between intr vector and event fd. 5862 */ 5863 if (!rte_intr_dp_is_en(intr_handle)) 5864 return; 5865 5866 if (rte_intr_allow_others(intr_handle)) { 5867 base = IXGBE_RX_VEC_START; 5868 vector_idx = IXGBE_RX_VEC_START; 5869 } 5870 5871 /* Configure all RX queues of VF */ 5872 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) { 5873 /* Force all queue use vector 0, 5874 * as IXGBE_VF_MAXMSIVECOTR = 1 5875 */ 5876 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx); 5877 intr_handle->intr_vec[q_idx] = vector_idx; 5878 if (vector_idx < base + intr_handle->nb_efd - 1) 5879 vector_idx++; 5880 } 5881 5882 /* As RX queue setting above show, all queues use the vector 0. 5883 * Set only the ITR value of IXGBE_MISC_VEC_ID. 5884 */ 5885 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID), 5886 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 5887 | IXGBE_EITR_CNT_WDIS); 5888 } 5889 5890 /** 5891 * Sets up the hardware to properly generate MSI-X interrupts 5892 * @hw 5893 * board private structure 5894 */ 5895 static void 5896 ixgbe_configure_msix(struct rte_eth_dev *dev) 5897 { 5898 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5899 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5900 struct ixgbe_hw *hw = 5901 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5902 uint32_t queue_id, base = IXGBE_MISC_VEC_ID; 5903 uint32_t vec = IXGBE_MISC_VEC_ID; 5904 uint32_t mask; 5905 uint32_t gpie; 5906 5907 /* won't configure msix register if no mapping is done 5908 * between intr vector and event fd 5909 * but if misx has been enabled already, need to configure 5910 * auto clean, auto mask and throttling. 5911 */ 5912 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 5913 if (!rte_intr_dp_is_en(intr_handle) && 5914 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT))) 5915 return; 5916 5917 if (rte_intr_allow_others(intr_handle)) 5918 vec = base = IXGBE_RX_VEC_START; 5919 5920 /* setup GPIE for MSI-x mode */ 5921 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 5922 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5923 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME; 5924 /* auto clearing and auto setting corresponding bits in EIMS 5925 * when MSI-X interrupt is triggered 5926 */ 5927 if (hw->mac.type == ixgbe_mac_82598EB) { 5928 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5929 } else { 5930 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5931 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5932 } 5933 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5934 5935 /* Populate the IVAR table and set the ITR values to the 5936 * corresponding register. 5937 */ 5938 if (rte_intr_dp_is_en(intr_handle)) { 5939 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; 5940 queue_id++) { 5941 /* by default, 1:1 mapping */ 5942 ixgbe_set_ivar_map(hw, 0, queue_id, vec); 5943 intr_handle->intr_vec[queue_id] = vec; 5944 if (vec < base + intr_handle->nb_efd - 1) 5945 vec++; 5946 } 5947 5948 switch (hw->mac.type) { 5949 case ixgbe_mac_82598EB: 5950 ixgbe_set_ivar_map(hw, -1, 5951 IXGBE_IVAR_OTHER_CAUSES_INDEX, 5952 IXGBE_MISC_VEC_ID); 5953 break; 5954 case ixgbe_mac_82599EB: 5955 case ixgbe_mac_X540: 5956 case ixgbe_mac_X550: 5957 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID); 5958 break; 5959 default: 5960 break; 5961 } 5962 } 5963 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID), 5964 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 5965 | IXGBE_EITR_CNT_WDIS); 5966 5967 /* set up to autoclear timer, and the vectors */ 5968 mask = IXGBE_EIMS_ENABLE_MASK; 5969 mask &= ~(IXGBE_EIMS_OTHER | 5970 IXGBE_EIMS_MAILBOX | 5971 IXGBE_EIMS_LSC); 5972 5973 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask); 5974 } 5975 5976 int 5977 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, 5978 uint16_t queue_idx, uint16_t tx_rate) 5979 { 5980 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5981 struct rte_eth_rxmode *rxmode; 5982 uint32_t rf_dec, rf_int; 5983 uint32_t bcnrc_val; 5984 uint16_t link_speed = dev->data->dev_link.link_speed; 5985 5986 if (queue_idx >= hw->mac.max_tx_queues) 5987 return -EINVAL; 5988 5989 if (tx_rate != 0) { 5990 /* Calculate the rate factor values to set */ 5991 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate; 5992 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate; 5993 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate; 5994 5995 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA; 5996 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) & 5997 IXGBE_RTTBCNRC_RF_INT_MASK_M); 5998 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK); 5999 } else { 6000 bcnrc_val = 0; 6001 } 6002 6003 rxmode = &dev->data->dev_conf.rxmode; 6004 /* 6005 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 6006 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise 6007 * set as 0x4. 6008 */ 6009 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) && 6010 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE)) 6011 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 6012 IXGBE_MMW_SIZE_JUMBO_FRAME); 6013 else 6014 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 6015 IXGBE_MMW_SIZE_DEFAULT); 6016 6017 /* Set RTTBCNRC of queue X */ 6018 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx); 6019 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 6020 IXGBE_WRITE_FLUSH(hw); 6021 6022 return 0; 6023 } 6024 6025 static int 6026 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr, 6027 __attribute__((unused)) uint32_t index, 6028 __attribute__((unused)) uint32_t pool) 6029 { 6030 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6031 int diag; 6032 6033 /* 6034 * On a 82599 VF, adding again the same MAC addr is not an idempotent 6035 * operation. Trap this case to avoid exhausting the [very limited] 6036 * set of PF resources used to store VF MAC addresses. 6037 */ 6038 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0) 6039 return -1; 6040 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6041 if (diag != 0) 6042 PMD_DRV_LOG(ERR, "Unable to add MAC address " 6043 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d", 6044 mac_addr->addr_bytes[0], 6045 mac_addr->addr_bytes[1], 6046 mac_addr->addr_bytes[2], 6047 mac_addr->addr_bytes[3], 6048 mac_addr->addr_bytes[4], 6049 mac_addr->addr_bytes[5], 6050 diag); 6051 return diag; 6052 } 6053 6054 static void 6055 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index) 6056 { 6057 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6058 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr; 6059 struct ether_addr *mac_addr; 6060 uint32_t i; 6061 int diag; 6062 6063 /* 6064 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does 6065 * not support the deletion of a given MAC address. 6066 * Instead, it imposes to delete all MAC addresses, then to add again 6067 * all MAC addresses with the exception of the one to be deleted. 6068 */ 6069 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL); 6070 6071 /* 6072 * Add again all MAC addresses, with the exception of the deleted one 6073 * and of the permanent MAC address. 6074 */ 6075 for (i = 0, mac_addr = dev->data->mac_addrs; 6076 i < hw->mac.num_rar_entries; i++, mac_addr++) { 6077 /* Skip the deleted MAC address */ 6078 if (i == index) 6079 continue; 6080 /* Skip NULL MAC addresses */ 6081 if (is_zero_ether_addr(mac_addr)) 6082 continue; 6083 /* Skip the permanent MAC address */ 6084 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0) 6085 continue; 6086 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6087 if (diag != 0) 6088 PMD_DRV_LOG(ERR, 6089 "Adding again MAC address " 6090 "%02x:%02x:%02x:%02x:%02x:%02x failed " 6091 "diag=%d", 6092 mac_addr->addr_bytes[0], 6093 mac_addr->addr_bytes[1], 6094 mac_addr->addr_bytes[2], 6095 mac_addr->addr_bytes[3], 6096 mac_addr->addr_bytes[4], 6097 mac_addr->addr_bytes[5], 6098 diag); 6099 } 6100 } 6101 6102 static int 6103 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr) 6104 { 6105 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6106 6107 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0); 6108 6109 return 0; 6110 } 6111 6112 int 6113 ixgbe_syn_filter_set(struct rte_eth_dev *dev, 6114 struct rte_eth_syn_filter *filter, 6115 bool add) 6116 { 6117 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6118 struct ixgbe_filter_info *filter_info = 6119 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6120 uint32_t syn_info; 6121 uint32_t synqf; 6122 6123 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6124 return -EINVAL; 6125 6126 syn_info = filter_info->syn_info; 6127 6128 if (add) { 6129 if (syn_info & IXGBE_SYN_FILTER_ENABLE) 6130 return -EINVAL; 6131 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) & 6132 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE); 6133 6134 if (filter->hig_pri) 6135 synqf |= IXGBE_SYN_FILTER_SYNQFP; 6136 else 6137 synqf &= ~IXGBE_SYN_FILTER_SYNQFP; 6138 } else { 6139 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6140 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE)) 6141 return -ENOENT; 6142 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE); 6143 } 6144 6145 filter_info->syn_info = synqf; 6146 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 6147 IXGBE_WRITE_FLUSH(hw); 6148 return 0; 6149 } 6150 6151 static int 6152 ixgbe_syn_filter_get(struct rte_eth_dev *dev, 6153 struct rte_eth_syn_filter *filter) 6154 { 6155 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6156 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6157 6158 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 6159 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0; 6160 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1); 6161 return 0; 6162 } 6163 return -ENOENT; 6164 } 6165 6166 static int 6167 ixgbe_syn_filter_handle(struct rte_eth_dev *dev, 6168 enum rte_filter_op filter_op, 6169 void *arg) 6170 { 6171 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6172 int ret; 6173 6174 MAC_TYPE_FILTER_SUP(hw->mac.type); 6175 6176 if (filter_op == RTE_ETH_FILTER_NOP) 6177 return 0; 6178 6179 if (arg == NULL) { 6180 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u", 6181 filter_op); 6182 return -EINVAL; 6183 } 6184 6185 switch (filter_op) { 6186 case RTE_ETH_FILTER_ADD: 6187 ret = ixgbe_syn_filter_set(dev, 6188 (struct rte_eth_syn_filter *)arg, 6189 TRUE); 6190 break; 6191 case RTE_ETH_FILTER_DELETE: 6192 ret = ixgbe_syn_filter_set(dev, 6193 (struct rte_eth_syn_filter *)arg, 6194 FALSE); 6195 break; 6196 case RTE_ETH_FILTER_GET: 6197 ret = ixgbe_syn_filter_get(dev, 6198 (struct rte_eth_syn_filter *)arg); 6199 break; 6200 default: 6201 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op); 6202 ret = -EINVAL; 6203 break; 6204 } 6205 6206 return ret; 6207 } 6208 6209 6210 static inline enum ixgbe_5tuple_protocol 6211 convert_protocol_type(uint8_t protocol_value) 6212 { 6213 if (protocol_value == IPPROTO_TCP) 6214 return IXGBE_FILTER_PROTOCOL_TCP; 6215 else if (protocol_value == IPPROTO_UDP) 6216 return IXGBE_FILTER_PROTOCOL_UDP; 6217 else if (protocol_value == IPPROTO_SCTP) 6218 return IXGBE_FILTER_PROTOCOL_SCTP; 6219 else 6220 return IXGBE_FILTER_PROTOCOL_NONE; 6221 } 6222 6223 /* inject a 5-tuple filter to HW */ 6224 static inline void 6225 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev, 6226 struct ixgbe_5tuple_filter *filter) 6227 { 6228 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6229 int i; 6230 uint32_t ftqf, sdpqf; 6231 uint32_t l34timir = 0; 6232 uint8_t mask = 0xff; 6233 6234 i = filter->index; 6235 6236 sdpqf = (uint32_t)(filter->filter_info.dst_port << 6237 IXGBE_SDPQF_DSTPORT_SHIFT); 6238 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT); 6239 6240 ftqf = (uint32_t)(filter->filter_info.proto & 6241 IXGBE_FTQF_PROTOCOL_MASK); 6242 ftqf |= (uint32_t)((filter->filter_info.priority & 6243 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT); 6244 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */ 6245 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK; 6246 if (filter->filter_info.dst_ip_mask == 0) 6247 mask &= IXGBE_FTQF_DEST_ADDR_MASK; 6248 if (filter->filter_info.src_port_mask == 0) 6249 mask &= IXGBE_FTQF_SOURCE_PORT_MASK; 6250 if (filter->filter_info.dst_port_mask == 0) 6251 mask &= IXGBE_FTQF_DEST_PORT_MASK; 6252 if (filter->filter_info.proto_mask == 0) 6253 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK; 6254 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT; 6255 ftqf |= IXGBE_FTQF_POOL_MASK_EN; 6256 ftqf |= IXGBE_FTQF_QUEUE_ENABLE; 6257 6258 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip); 6259 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip); 6260 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf); 6261 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf); 6262 6263 l34timir |= IXGBE_L34T_IMIR_RESERVE; 6264 l34timir |= (uint32_t)(filter->queue << 6265 IXGBE_L34T_IMIR_QUEUE_SHIFT); 6266 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir); 6267 } 6268 6269 /* 6270 * add a 5tuple filter 6271 * 6272 * @param 6273 * dev: Pointer to struct rte_eth_dev. 6274 * index: the index the filter allocates. 6275 * filter: ponter to the filter that will be added. 6276 * rx_queue: the queue id the filter assigned to. 6277 * 6278 * @return 6279 * - On success, zero. 6280 * - On failure, a negative value. 6281 */ 6282 static int 6283 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 6284 struct ixgbe_5tuple_filter *filter) 6285 { 6286 struct ixgbe_filter_info *filter_info = 6287 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6288 int i, idx, shift; 6289 6290 /* 6291 * look for an unused 5tuple filter index, 6292 * and insert the filter to list. 6293 */ 6294 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) { 6295 idx = i / (sizeof(uint32_t) * NBBY); 6296 shift = i % (sizeof(uint32_t) * NBBY); 6297 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) { 6298 filter_info->fivetuple_mask[idx] |= 1 << shift; 6299 filter->index = i; 6300 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list, 6301 filter, 6302 entries); 6303 break; 6304 } 6305 } 6306 if (i >= IXGBE_MAX_FTQF_FILTERS) { 6307 PMD_DRV_LOG(ERR, "5tuple filters are full."); 6308 return -ENOSYS; 6309 } 6310 6311 ixgbe_inject_5tuple_filter(dev, filter); 6312 6313 return 0; 6314 } 6315 6316 /* 6317 * remove a 5tuple filter 6318 * 6319 * @param 6320 * dev: Pointer to struct rte_eth_dev. 6321 * filter: the pointer of the filter will be removed. 6322 */ 6323 static void 6324 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 6325 struct ixgbe_5tuple_filter *filter) 6326 { 6327 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6328 struct ixgbe_filter_info *filter_info = 6329 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6330 uint16_t index = filter->index; 6331 6332 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &= 6333 ~(1 << (index % (sizeof(uint32_t) * NBBY))); 6334 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries); 6335 rte_free(filter); 6336 6337 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0); 6338 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0); 6339 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0); 6340 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0); 6341 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0); 6342 } 6343 6344 static int 6345 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 6346 { 6347 struct ixgbe_hw *hw; 6348 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD; 6349 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode; 6350 6351 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6352 6353 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN)) 6354 return -EINVAL; 6355 6356 /* refuse mtu that requires the support of scattered packets when this 6357 * feature has not been enabled before. 6358 */ 6359 if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) && 6360 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE > 6361 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) 6362 return -EINVAL; 6363 6364 /* 6365 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU 6366 * request of the version 2.0 of the mailbox API. 6367 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0 6368 * of the mailbox API. 6369 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers 6370 * prior to 3.11.33 which contains the following change: 6371 * "ixgbe: Enable jumbo frames support w/ SR-IOV" 6372 */ 6373 ixgbevf_rlpml_set_vf(hw, max_frame); 6374 6375 /* update max frame size */ 6376 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame; 6377 return 0; 6378 } 6379 6380 static inline struct ixgbe_5tuple_filter * 6381 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list, 6382 struct ixgbe_5tuple_filter_info *key) 6383 { 6384 struct ixgbe_5tuple_filter *it; 6385 6386 TAILQ_FOREACH(it, filter_list, entries) { 6387 if (memcmp(key, &it->filter_info, 6388 sizeof(struct ixgbe_5tuple_filter_info)) == 0) { 6389 return it; 6390 } 6391 } 6392 return NULL; 6393 } 6394 6395 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/ 6396 static inline int 6397 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter, 6398 struct ixgbe_5tuple_filter_info *filter_info) 6399 { 6400 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM || 6401 filter->priority > IXGBE_5TUPLE_MAX_PRI || 6402 filter->priority < IXGBE_5TUPLE_MIN_PRI) 6403 return -EINVAL; 6404 6405 switch (filter->dst_ip_mask) { 6406 case UINT32_MAX: 6407 filter_info->dst_ip_mask = 0; 6408 filter_info->dst_ip = filter->dst_ip; 6409 break; 6410 case 0: 6411 filter_info->dst_ip_mask = 1; 6412 break; 6413 default: 6414 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 6415 return -EINVAL; 6416 } 6417 6418 switch (filter->src_ip_mask) { 6419 case UINT32_MAX: 6420 filter_info->src_ip_mask = 0; 6421 filter_info->src_ip = filter->src_ip; 6422 break; 6423 case 0: 6424 filter_info->src_ip_mask = 1; 6425 break; 6426 default: 6427 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 6428 return -EINVAL; 6429 } 6430 6431 switch (filter->dst_port_mask) { 6432 case UINT16_MAX: 6433 filter_info->dst_port_mask = 0; 6434 filter_info->dst_port = filter->dst_port; 6435 break; 6436 case 0: 6437 filter_info->dst_port_mask = 1; 6438 break; 6439 default: 6440 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 6441 return -EINVAL; 6442 } 6443 6444 switch (filter->src_port_mask) { 6445 case UINT16_MAX: 6446 filter_info->src_port_mask = 0; 6447 filter_info->src_port = filter->src_port; 6448 break; 6449 case 0: 6450 filter_info->src_port_mask = 1; 6451 break; 6452 default: 6453 PMD_DRV_LOG(ERR, "invalid src_port mask."); 6454 return -EINVAL; 6455 } 6456 6457 switch (filter->proto_mask) { 6458 case UINT8_MAX: 6459 filter_info->proto_mask = 0; 6460 filter_info->proto = 6461 convert_protocol_type(filter->proto); 6462 break; 6463 case 0: 6464 filter_info->proto_mask = 1; 6465 break; 6466 default: 6467 PMD_DRV_LOG(ERR, "invalid protocol mask."); 6468 return -EINVAL; 6469 } 6470 6471 filter_info->priority = (uint8_t)filter->priority; 6472 return 0; 6473 } 6474 6475 /* 6476 * add or delete a ntuple filter 6477 * 6478 * @param 6479 * dev: Pointer to struct rte_eth_dev. 6480 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6481 * add: if true, add filter, if false, remove filter 6482 * 6483 * @return 6484 * - On success, zero. 6485 * - On failure, a negative value. 6486 */ 6487 int 6488 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 6489 struct rte_eth_ntuple_filter *ntuple_filter, 6490 bool add) 6491 { 6492 struct ixgbe_filter_info *filter_info = 6493 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6494 struct ixgbe_5tuple_filter_info filter_5tuple; 6495 struct ixgbe_5tuple_filter *filter; 6496 int ret; 6497 6498 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6499 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6500 return -EINVAL; 6501 } 6502 6503 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6504 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6505 if (ret < 0) 6506 return ret; 6507 6508 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6509 &filter_5tuple); 6510 if (filter != NULL && add) { 6511 PMD_DRV_LOG(ERR, "filter exists."); 6512 return -EEXIST; 6513 } 6514 if (filter == NULL && !add) { 6515 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6516 return -ENOENT; 6517 } 6518 6519 if (add) { 6520 filter = rte_zmalloc("ixgbe_5tuple_filter", 6521 sizeof(struct ixgbe_5tuple_filter), 0); 6522 if (filter == NULL) 6523 return -ENOMEM; 6524 rte_memcpy(&filter->filter_info, 6525 &filter_5tuple, 6526 sizeof(struct ixgbe_5tuple_filter_info)); 6527 filter->queue = ntuple_filter->queue; 6528 ret = ixgbe_add_5tuple_filter(dev, filter); 6529 if (ret < 0) { 6530 rte_free(filter); 6531 return ret; 6532 } 6533 } else 6534 ixgbe_remove_5tuple_filter(dev, filter); 6535 6536 return 0; 6537 } 6538 6539 /* 6540 * get a ntuple filter 6541 * 6542 * @param 6543 * dev: Pointer to struct rte_eth_dev. 6544 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6545 * 6546 * @return 6547 * - On success, zero. 6548 * - On failure, a negative value. 6549 */ 6550 static int 6551 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev, 6552 struct rte_eth_ntuple_filter *ntuple_filter) 6553 { 6554 struct ixgbe_filter_info *filter_info = 6555 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6556 struct ixgbe_5tuple_filter_info filter_5tuple; 6557 struct ixgbe_5tuple_filter *filter; 6558 int ret; 6559 6560 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6561 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6562 return -EINVAL; 6563 } 6564 6565 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6566 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6567 if (ret < 0) 6568 return ret; 6569 6570 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6571 &filter_5tuple); 6572 if (filter == NULL) { 6573 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6574 return -ENOENT; 6575 } 6576 ntuple_filter->queue = filter->queue; 6577 return 0; 6578 } 6579 6580 /* 6581 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter. 6582 * @dev: pointer to rte_eth_dev structure 6583 * @filter_op:operation will be taken. 6584 * @arg: a pointer to specific structure corresponding to the filter_op 6585 * 6586 * @return 6587 * - On success, zero. 6588 * - On failure, a negative value. 6589 */ 6590 static int 6591 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev, 6592 enum rte_filter_op filter_op, 6593 void *arg) 6594 { 6595 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6596 int ret; 6597 6598 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type); 6599 6600 if (filter_op == RTE_ETH_FILTER_NOP) 6601 return 0; 6602 6603 if (arg == NULL) { 6604 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 6605 filter_op); 6606 return -EINVAL; 6607 } 6608 6609 switch (filter_op) { 6610 case RTE_ETH_FILTER_ADD: 6611 ret = ixgbe_add_del_ntuple_filter(dev, 6612 (struct rte_eth_ntuple_filter *)arg, 6613 TRUE); 6614 break; 6615 case RTE_ETH_FILTER_DELETE: 6616 ret = ixgbe_add_del_ntuple_filter(dev, 6617 (struct rte_eth_ntuple_filter *)arg, 6618 FALSE); 6619 break; 6620 case RTE_ETH_FILTER_GET: 6621 ret = ixgbe_get_ntuple_filter(dev, 6622 (struct rte_eth_ntuple_filter *)arg); 6623 break; 6624 default: 6625 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 6626 ret = -EINVAL; 6627 break; 6628 } 6629 return ret; 6630 } 6631 6632 int 6633 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 6634 struct rte_eth_ethertype_filter *filter, 6635 bool add) 6636 { 6637 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6638 struct ixgbe_filter_info *filter_info = 6639 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6640 uint32_t etqf = 0; 6641 uint32_t etqs = 0; 6642 int ret; 6643 struct ixgbe_ethertype_filter ethertype_filter; 6644 6645 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6646 return -EINVAL; 6647 6648 if (filter->ether_type == ETHER_TYPE_IPv4 || 6649 filter->ether_type == ETHER_TYPE_IPv6) { 6650 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in" 6651 " ethertype filter.", filter->ether_type); 6652 return -EINVAL; 6653 } 6654 6655 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) { 6656 PMD_DRV_LOG(ERR, "mac compare is unsupported."); 6657 return -EINVAL; 6658 } 6659 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) { 6660 PMD_DRV_LOG(ERR, "drop option is unsupported."); 6661 return -EINVAL; 6662 } 6663 6664 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6665 if (ret >= 0 && add) { 6666 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.", 6667 filter->ether_type); 6668 return -EEXIST; 6669 } 6670 if (ret < 0 && !add) { 6671 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6672 filter->ether_type); 6673 return -ENOENT; 6674 } 6675 6676 if (add) { 6677 etqf = IXGBE_ETQF_FILTER_EN; 6678 etqf |= (uint32_t)filter->ether_type; 6679 etqs |= (uint32_t)((filter->queue << 6680 IXGBE_ETQS_RX_QUEUE_SHIFT) & 6681 IXGBE_ETQS_RX_QUEUE); 6682 etqs |= IXGBE_ETQS_QUEUE_EN; 6683 6684 ethertype_filter.ethertype = filter->ether_type; 6685 ethertype_filter.etqf = etqf; 6686 ethertype_filter.etqs = etqs; 6687 ethertype_filter.conf = FALSE; 6688 ret = ixgbe_ethertype_filter_insert(filter_info, 6689 ðertype_filter); 6690 if (ret < 0) { 6691 PMD_DRV_LOG(ERR, "ethertype filters are full."); 6692 return -ENOSPC; 6693 } 6694 } else { 6695 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret); 6696 if (ret < 0) 6697 return -ENOSYS; 6698 } 6699 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf); 6700 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs); 6701 IXGBE_WRITE_FLUSH(hw); 6702 6703 return 0; 6704 } 6705 6706 static int 6707 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, 6708 struct rte_eth_ethertype_filter *filter) 6709 { 6710 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6711 struct ixgbe_filter_info *filter_info = 6712 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6713 uint32_t etqf, etqs; 6714 int ret; 6715 6716 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6717 if (ret < 0) { 6718 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6719 filter->ether_type); 6720 return -ENOENT; 6721 } 6722 6723 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret)); 6724 if (etqf & IXGBE_ETQF_FILTER_EN) { 6725 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret)); 6726 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE; 6727 filter->flags = 0; 6728 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> 6729 IXGBE_ETQS_RX_QUEUE_SHIFT; 6730 return 0; 6731 } 6732 return -ENOENT; 6733 } 6734 6735 /* 6736 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter. 6737 * @dev: pointer to rte_eth_dev structure 6738 * @filter_op:operation will be taken. 6739 * @arg: a pointer to specific structure corresponding to the filter_op 6740 */ 6741 static int 6742 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev, 6743 enum rte_filter_op filter_op, 6744 void *arg) 6745 { 6746 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6747 int ret; 6748 6749 MAC_TYPE_FILTER_SUP(hw->mac.type); 6750 6751 if (filter_op == RTE_ETH_FILTER_NOP) 6752 return 0; 6753 6754 if (arg == NULL) { 6755 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 6756 filter_op); 6757 return -EINVAL; 6758 } 6759 6760 switch (filter_op) { 6761 case RTE_ETH_FILTER_ADD: 6762 ret = ixgbe_add_del_ethertype_filter(dev, 6763 (struct rte_eth_ethertype_filter *)arg, 6764 TRUE); 6765 break; 6766 case RTE_ETH_FILTER_DELETE: 6767 ret = ixgbe_add_del_ethertype_filter(dev, 6768 (struct rte_eth_ethertype_filter *)arg, 6769 FALSE); 6770 break; 6771 case RTE_ETH_FILTER_GET: 6772 ret = ixgbe_get_ethertype_filter(dev, 6773 (struct rte_eth_ethertype_filter *)arg); 6774 break; 6775 default: 6776 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 6777 ret = -EINVAL; 6778 break; 6779 } 6780 return ret; 6781 } 6782 6783 static int 6784 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 6785 enum rte_filter_type filter_type, 6786 enum rte_filter_op filter_op, 6787 void *arg) 6788 { 6789 int ret = 0; 6790 6791 switch (filter_type) { 6792 case RTE_ETH_FILTER_NTUPLE: 6793 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg); 6794 break; 6795 case RTE_ETH_FILTER_ETHERTYPE: 6796 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg); 6797 break; 6798 case RTE_ETH_FILTER_SYN: 6799 ret = ixgbe_syn_filter_handle(dev, filter_op, arg); 6800 break; 6801 case RTE_ETH_FILTER_FDIR: 6802 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg); 6803 break; 6804 case RTE_ETH_FILTER_L2_TUNNEL: 6805 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg); 6806 break; 6807 case RTE_ETH_FILTER_GENERIC: 6808 if (filter_op != RTE_ETH_FILTER_GET) 6809 return -EINVAL; 6810 *(const void **)arg = &ixgbe_flow_ops; 6811 break; 6812 default: 6813 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 6814 filter_type); 6815 ret = -EINVAL; 6816 break; 6817 } 6818 6819 return ret; 6820 } 6821 6822 static u8 * 6823 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw, 6824 u8 **mc_addr_ptr, u32 *vmdq) 6825 { 6826 u8 *mc_addr; 6827 6828 *vmdq = 0; 6829 mc_addr = *mc_addr_ptr; 6830 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr)); 6831 return mc_addr; 6832 } 6833 6834 static int 6835 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 6836 struct ether_addr *mc_addr_set, 6837 uint32_t nb_mc_addr) 6838 { 6839 struct ixgbe_hw *hw; 6840 u8 *mc_addr_list; 6841 6842 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6843 mc_addr_list = (u8 *)mc_addr_set; 6844 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr, 6845 ixgbe_dev_addr_list_itr, TRUE); 6846 } 6847 6848 static uint64_t 6849 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev) 6850 { 6851 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6852 uint64_t systime_cycles; 6853 6854 switch (hw->mac.type) { 6855 case ixgbe_mac_X550: 6856 case ixgbe_mac_X550EM_x: 6857 case ixgbe_mac_X550EM_a: 6858 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */ 6859 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 6860 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 6861 * NSEC_PER_SEC; 6862 break; 6863 default: 6864 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 6865 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 6866 << 32; 6867 } 6868 6869 return systime_cycles; 6870 } 6871 6872 static uint64_t 6873 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) 6874 { 6875 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6876 uint64_t rx_tstamp_cycles; 6877 6878 switch (hw->mac.type) { 6879 case ixgbe_mac_X550: 6880 case ixgbe_mac_X550EM_x: 6881 case ixgbe_mac_X550EM_a: 6882 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 6883 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 6884 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 6885 * NSEC_PER_SEC; 6886 break; 6887 default: 6888 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 6889 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 6890 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 6891 << 32; 6892 } 6893 6894 return rx_tstamp_cycles; 6895 } 6896 6897 static uint64_t 6898 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 6899 { 6900 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6901 uint64_t tx_tstamp_cycles; 6902 6903 switch (hw->mac.type) { 6904 case ixgbe_mac_X550: 6905 case ixgbe_mac_X550EM_x: 6906 case ixgbe_mac_X550EM_a: 6907 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 6908 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 6909 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 6910 * NSEC_PER_SEC; 6911 break; 6912 default: 6913 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 6914 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 6915 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 6916 << 32; 6917 } 6918 6919 return tx_tstamp_cycles; 6920 } 6921 6922 static void 6923 ixgbe_start_timecounters(struct rte_eth_dev *dev) 6924 { 6925 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6926 struct ixgbe_adapter *adapter = 6927 (struct ixgbe_adapter *)dev->data->dev_private; 6928 struct rte_eth_link link; 6929 uint32_t incval = 0; 6930 uint32_t shift = 0; 6931 6932 /* Get current link speed. */ 6933 ixgbe_dev_link_update(dev, 1); 6934 rte_eth_linkstatus_get(dev, &link); 6935 6936 switch (link.link_speed) { 6937 case ETH_SPEED_NUM_100M: 6938 incval = IXGBE_INCVAL_100; 6939 shift = IXGBE_INCVAL_SHIFT_100; 6940 break; 6941 case ETH_SPEED_NUM_1G: 6942 incval = IXGBE_INCVAL_1GB; 6943 shift = IXGBE_INCVAL_SHIFT_1GB; 6944 break; 6945 case ETH_SPEED_NUM_10G: 6946 default: 6947 incval = IXGBE_INCVAL_10GB; 6948 shift = IXGBE_INCVAL_SHIFT_10GB; 6949 break; 6950 } 6951 6952 switch (hw->mac.type) { 6953 case ixgbe_mac_X550: 6954 case ixgbe_mac_X550EM_x: 6955 case ixgbe_mac_X550EM_a: 6956 /* Independent of link speed. */ 6957 incval = 1; 6958 /* Cycles read will be interpreted as ns. */ 6959 shift = 0; 6960 /* Fall-through */ 6961 case ixgbe_mac_X540: 6962 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval); 6963 break; 6964 case ixgbe_mac_82599EB: 6965 incval >>= IXGBE_INCVAL_SHIFT_82599; 6966 shift -= IXGBE_INCVAL_SHIFT_82599; 6967 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 6968 (1 << IXGBE_INCPER_SHIFT_82599) | incval); 6969 break; 6970 default: 6971 /* Not supported. */ 6972 return; 6973 } 6974 6975 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 6976 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 6977 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 6978 6979 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6980 adapter->systime_tc.cc_shift = shift; 6981 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; 6982 6983 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6984 adapter->rx_tstamp_tc.cc_shift = shift; 6985 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 6986 6987 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6988 adapter->tx_tstamp_tc.cc_shift = shift; 6989 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 6990 } 6991 6992 static int 6993 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 6994 { 6995 struct ixgbe_adapter *adapter = 6996 (struct ixgbe_adapter *)dev->data->dev_private; 6997 6998 adapter->systime_tc.nsec += delta; 6999 adapter->rx_tstamp_tc.nsec += delta; 7000 adapter->tx_tstamp_tc.nsec += delta; 7001 7002 return 0; 7003 } 7004 7005 static int 7006 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 7007 { 7008 uint64_t ns; 7009 struct ixgbe_adapter *adapter = 7010 (struct ixgbe_adapter *)dev->data->dev_private; 7011 7012 ns = rte_timespec_to_ns(ts); 7013 /* Set the timecounters to a new value. */ 7014 adapter->systime_tc.nsec = ns; 7015 adapter->rx_tstamp_tc.nsec = ns; 7016 adapter->tx_tstamp_tc.nsec = ns; 7017 7018 return 0; 7019 } 7020 7021 static int 7022 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 7023 { 7024 uint64_t ns, systime_cycles; 7025 struct ixgbe_adapter *adapter = 7026 (struct ixgbe_adapter *)dev->data->dev_private; 7027 7028 systime_cycles = ixgbe_read_systime_cyclecounter(dev); 7029 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 7030 *ts = rte_ns_to_timespec(ns); 7031 7032 return 0; 7033 } 7034 7035 static int 7036 ixgbe_timesync_enable(struct rte_eth_dev *dev) 7037 { 7038 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7039 uint32_t tsync_ctl; 7040 uint32_t tsauxc; 7041 7042 /* Stop the timesync system time. */ 7043 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0); 7044 /* Reset the timesync system time value. */ 7045 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0); 7046 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0); 7047 7048 /* Enable system time for platforms where it isn't on by default. */ 7049 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC); 7050 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME; 7051 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc); 7052 7053 ixgbe_start_timecounters(dev); 7054 7055 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7056 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 7057 (ETHER_TYPE_1588 | 7058 IXGBE_ETQF_FILTER_EN | 7059 IXGBE_ETQF_1588)); 7060 7061 /* Enable timestamping of received PTP packets. */ 7062 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7063 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED; 7064 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7065 7066 /* Enable timestamping of transmitted PTP packets. */ 7067 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7068 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED; 7069 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7070 7071 IXGBE_WRITE_FLUSH(hw); 7072 7073 return 0; 7074 } 7075 7076 static int 7077 ixgbe_timesync_disable(struct rte_eth_dev *dev) 7078 { 7079 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7080 uint32_t tsync_ctl; 7081 7082 /* Disable timestamping of transmitted PTP packets. */ 7083 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7084 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED; 7085 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7086 7087 /* Disable timestamping of received PTP packets. */ 7088 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7089 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED; 7090 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7091 7092 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7093 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0); 7094 7095 /* Stop incrementating the System Time registers. */ 7096 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0); 7097 7098 return 0; 7099 } 7100 7101 static int 7102 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 7103 struct timespec *timestamp, 7104 uint32_t flags __rte_unused) 7105 { 7106 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7107 struct ixgbe_adapter *adapter = 7108 (struct ixgbe_adapter *)dev->data->dev_private; 7109 uint32_t tsync_rxctl; 7110 uint64_t rx_tstamp_cycles; 7111 uint64_t ns; 7112 7113 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7114 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0) 7115 return -EINVAL; 7116 7117 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev); 7118 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 7119 *timestamp = rte_ns_to_timespec(ns); 7120 7121 return 0; 7122 } 7123 7124 static int 7125 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 7126 struct timespec *timestamp) 7127 { 7128 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7129 struct ixgbe_adapter *adapter = 7130 (struct ixgbe_adapter *)dev->data->dev_private; 7131 uint32_t tsync_txctl; 7132 uint64_t tx_tstamp_cycles; 7133 uint64_t ns; 7134 7135 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7136 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0) 7137 return -EINVAL; 7138 7139 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev); 7140 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 7141 *timestamp = rte_ns_to_timespec(ns); 7142 7143 return 0; 7144 } 7145 7146 static int 7147 ixgbe_get_reg_length(struct rte_eth_dev *dev) 7148 { 7149 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7150 int count = 0; 7151 int g_ind = 0; 7152 const struct reg_info *reg_group; 7153 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7154 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7155 7156 while ((reg_group = reg_set[g_ind++])) 7157 count += ixgbe_regs_group_count(reg_group); 7158 7159 return count; 7160 } 7161 7162 static int 7163 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused) 7164 { 7165 int count = 0; 7166 int g_ind = 0; 7167 const struct reg_info *reg_group; 7168 7169 while ((reg_group = ixgbevf_regs[g_ind++])) 7170 count += ixgbe_regs_group_count(reg_group); 7171 7172 return count; 7173 } 7174 7175 static int 7176 ixgbe_get_regs(struct rte_eth_dev *dev, 7177 struct rte_dev_reg_info *regs) 7178 { 7179 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7180 uint32_t *data = regs->data; 7181 int g_ind = 0; 7182 int count = 0; 7183 const struct reg_info *reg_group; 7184 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7185 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7186 7187 if (data == NULL) { 7188 regs->length = ixgbe_get_reg_length(dev); 7189 regs->width = sizeof(uint32_t); 7190 return 0; 7191 } 7192 7193 /* Support only full register dump */ 7194 if ((regs->length == 0) || 7195 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) { 7196 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7197 hw->device_id; 7198 while ((reg_group = reg_set[g_ind++])) 7199 count += ixgbe_read_regs_group(dev, &data[count], 7200 reg_group); 7201 return 0; 7202 } 7203 7204 return -ENOTSUP; 7205 } 7206 7207 static int 7208 ixgbevf_get_regs(struct rte_eth_dev *dev, 7209 struct rte_dev_reg_info *regs) 7210 { 7211 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7212 uint32_t *data = regs->data; 7213 int g_ind = 0; 7214 int count = 0; 7215 const struct reg_info *reg_group; 7216 7217 if (data == NULL) { 7218 regs->length = ixgbevf_get_reg_length(dev); 7219 regs->width = sizeof(uint32_t); 7220 return 0; 7221 } 7222 7223 /* Support only full register dump */ 7224 if ((regs->length == 0) || 7225 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) { 7226 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7227 hw->device_id; 7228 while ((reg_group = ixgbevf_regs[g_ind++])) 7229 count += ixgbe_read_regs_group(dev, &data[count], 7230 reg_group); 7231 return 0; 7232 } 7233 7234 return -ENOTSUP; 7235 } 7236 7237 static int 7238 ixgbe_get_eeprom_length(struct rte_eth_dev *dev) 7239 { 7240 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7241 7242 /* Return unit is byte count */ 7243 return hw->eeprom.word_size * 2; 7244 } 7245 7246 static int 7247 ixgbe_get_eeprom(struct rte_eth_dev *dev, 7248 struct rte_dev_eeprom_info *in_eeprom) 7249 { 7250 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7251 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7252 uint16_t *data = in_eeprom->data; 7253 int first, length; 7254 7255 first = in_eeprom->offset >> 1; 7256 length = in_eeprom->length >> 1; 7257 if ((first > hw->eeprom.word_size) || 7258 ((first + length) > hw->eeprom.word_size)) 7259 return -EINVAL; 7260 7261 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7262 7263 return eeprom->ops.read_buffer(hw, first, length, data); 7264 } 7265 7266 static int 7267 ixgbe_set_eeprom(struct rte_eth_dev *dev, 7268 struct rte_dev_eeprom_info *in_eeprom) 7269 { 7270 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7271 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7272 uint16_t *data = in_eeprom->data; 7273 int first, length; 7274 7275 first = in_eeprom->offset >> 1; 7276 length = in_eeprom->length >> 1; 7277 if ((first > hw->eeprom.word_size) || 7278 ((first + length) > hw->eeprom.word_size)) 7279 return -EINVAL; 7280 7281 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7282 7283 return eeprom->ops.write_buffer(hw, first, length, data); 7284 } 7285 7286 static int 7287 ixgbe_get_module_info(struct rte_eth_dev *dev, 7288 struct rte_eth_dev_module_info *modinfo) 7289 { 7290 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7291 uint32_t status; 7292 uint8_t sff8472_rev, addr_mode; 7293 bool page_swap = false; 7294 7295 /* Check whether we support SFF-8472 or not */ 7296 status = hw->phy.ops.read_i2c_eeprom(hw, 7297 IXGBE_SFF_SFF_8472_COMP, 7298 &sff8472_rev); 7299 if (status != 0) 7300 return -EIO; 7301 7302 /* addressing mode is not supported */ 7303 status = hw->phy.ops.read_i2c_eeprom(hw, 7304 IXGBE_SFF_SFF_8472_SWAP, 7305 &addr_mode); 7306 if (status != 0) 7307 return -EIO; 7308 7309 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 7310 PMD_DRV_LOG(ERR, 7311 "Address change required to access page 0xA2, " 7312 "but not supported. Please report the module " 7313 "type to the driver maintainers."); 7314 page_swap = true; 7315 } 7316 7317 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) { 7318 /* We have a SFP, but it does not support SFF-8472 */ 7319 modinfo->type = RTE_ETH_MODULE_SFF_8079; 7320 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 7321 } else { 7322 /* We have a SFP which supports a revision of SFF-8472. */ 7323 modinfo->type = RTE_ETH_MODULE_SFF_8472; 7324 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 7325 } 7326 7327 return 0; 7328 } 7329 7330 static int 7331 ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 7332 struct rte_dev_eeprom_info *info) 7333 { 7334 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7335 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 7336 uint8_t databyte = 0xFF; 7337 uint8_t *data = info->data; 7338 uint32_t i = 0; 7339 7340 if (info->length == 0) 7341 return -EINVAL; 7342 7343 for (i = info->offset; i < info->offset + info->length; i++) { 7344 if (i < RTE_ETH_MODULE_SFF_8079_LEN) 7345 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 7346 else 7347 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 7348 7349 if (status != 0) 7350 return -EIO; 7351 7352 data[i - info->offset] = databyte; 7353 } 7354 7355 return 0; 7356 } 7357 7358 uint16_t 7359 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) { 7360 switch (mac_type) { 7361 case ixgbe_mac_X550: 7362 case ixgbe_mac_X550EM_x: 7363 case ixgbe_mac_X550EM_a: 7364 return ETH_RSS_RETA_SIZE_512; 7365 case ixgbe_mac_X550_vf: 7366 case ixgbe_mac_X550EM_x_vf: 7367 case ixgbe_mac_X550EM_a_vf: 7368 return ETH_RSS_RETA_SIZE_64; 7369 default: 7370 return ETH_RSS_RETA_SIZE_128; 7371 } 7372 } 7373 7374 uint32_t 7375 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) { 7376 switch (mac_type) { 7377 case ixgbe_mac_X550: 7378 case ixgbe_mac_X550EM_x: 7379 case ixgbe_mac_X550EM_a: 7380 if (reta_idx < ETH_RSS_RETA_SIZE_128) 7381 return IXGBE_RETA(reta_idx >> 2); 7382 else 7383 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2); 7384 case ixgbe_mac_X550_vf: 7385 case ixgbe_mac_X550EM_x_vf: 7386 case ixgbe_mac_X550EM_a_vf: 7387 return IXGBE_VFRETA(reta_idx >> 2); 7388 default: 7389 return IXGBE_RETA(reta_idx >> 2); 7390 } 7391 } 7392 7393 uint32_t 7394 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) { 7395 switch (mac_type) { 7396 case ixgbe_mac_X550_vf: 7397 case ixgbe_mac_X550EM_x_vf: 7398 case ixgbe_mac_X550EM_a_vf: 7399 return IXGBE_VFMRQC; 7400 default: 7401 return IXGBE_MRQC; 7402 } 7403 } 7404 7405 uint32_t 7406 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) { 7407 switch (mac_type) { 7408 case ixgbe_mac_X550_vf: 7409 case ixgbe_mac_X550EM_x_vf: 7410 case ixgbe_mac_X550EM_a_vf: 7411 return IXGBE_VFRSSRK(i); 7412 default: 7413 return IXGBE_RSSRK(i); 7414 } 7415 } 7416 7417 bool 7418 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) { 7419 switch (mac_type) { 7420 case ixgbe_mac_82599_vf: 7421 case ixgbe_mac_X540_vf: 7422 return 0; 7423 default: 7424 return 1; 7425 } 7426 } 7427 7428 static int 7429 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 7430 struct rte_eth_dcb_info *dcb_info) 7431 { 7432 struct ixgbe_dcb_config *dcb_config = 7433 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 7434 struct ixgbe_dcb_tc_config *tc; 7435 struct rte_eth_dcb_tc_queue_mapping *tc_queue; 7436 uint8_t nb_tcs; 7437 uint8_t i, j; 7438 7439 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG) 7440 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs; 7441 else 7442 dcb_info->nb_tcs = 1; 7443 7444 tc_queue = &dcb_info->tc_queue; 7445 nb_tcs = dcb_info->nb_tcs; 7446 7447 if (dcb_config->vt_mode) { /* vt is enabled*/ 7448 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf = 7449 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf; 7450 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7451 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i]; 7452 if (RTE_ETH_DEV_SRIOV(dev).active > 0) { 7453 for (j = 0; j < nb_tcs; j++) { 7454 tc_queue->tc_rxq[0][j].base = j; 7455 tc_queue->tc_rxq[0][j].nb_queue = 1; 7456 tc_queue->tc_txq[0][j].base = j; 7457 tc_queue->tc_txq[0][j].nb_queue = 1; 7458 } 7459 } else { 7460 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) { 7461 for (j = 0; j < nb_tcs; j++) { 7462 tc_queue->tc_rxq[i][j].base = 7463 i * nb_tcs + j; 7464 tc_queue->tc_rxq[i][j].nb_queue = 1; 7465 tc_queue->tc_txq[i][j].base = 7466 i * nb_tcs + j; 7467 tc_queue->tc_txq[i][j].nb_queue = 1; 7468 } 7469 } 7470 } 7471 } else { /* vt is disabled*/ 7472 struct rte_eth_dcb_rx_conf *rx_conf = 7473 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 7474 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7475 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i]; 7476 if (dcb_info->nb_tcs == ETH_4_TCS) { 7477 for (i = 0; i < dcb_info->nb_tcs; i++) { 7478 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32; 7479 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7480 } 7481 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7482 dcb_info->tc_queue.tc_txq[0][1].base = 64; 7483 dcb_info->tc_queue.tc_txq[0][2].base = 96; 7484 dcb_info->tc_queue.tc_txq[0][3].base = 112; 7485 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64; 7486 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7487 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7488 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7489 } else if (dcb_info->nb_tcs == ETH_8_TCS) { 7490 for (i = 0; i < dcb_info->nb_tcs; i++) { 7491 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16; 7492 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7493 } 7494 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7495 dcb_info->tc_queue.tc_txq[0][1].base = 32; 7496 dcb_info->tc_queue.tc_txq[0][2].base = 64; 7497 dcb_info->tc_queue.tc_txq[0][3].base = 80; 7498 dcb_info->tc_queue.tc_txq[0][4].base = 96; 7499 dcb_info->tc_queue.tc_txq[0][5].base = 104; 7500 dcb_info->tc_queue.tc_txq[0][6].base = 112; 7501 dcb_info->tc_queue.tc_txq[0][7].base = 120; 7502 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32; 7503 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7504 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7505 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7506 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8; 7507 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8; 7508 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8; 7509 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8; 7510 } 7511 } 7512 for (i = 0; i < dcb_info->nb_tcs; i++) { 7513 tc = &dcb_config->tc_config[i]; 7514 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent; 7515 } 7516 return 0; 7517 } 7518 7519 /* Update e-tag ether type */ 7520 static int 7521 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw, 7522 uint16_t ether_type) 7523 { 7524 uint32_t etag_etype; 7525 7526 if (hw->mac.type != ixgbe_mac_X550 && 7527 hw->mac.type != ixgbe_mac_X550EM_x && 7528 hw->mac.type != ixgbe_mac_X550EM_a) { 7529 return -ENOTSUP; 7530 } 7531 7532 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7533 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK; 7534 etag_etype |= ether_type; 7535 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7536 IXGBE_WRITE_FLUSH(hw); 7537 7538 return 0; 7539 } 7540 7541 /* Config l2 tunnel ether type */ 7542 static int 7543 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev, 7544 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7545 { 7546 int ret = 0; 7547 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7548 struct ixgbe_l2_tn_info *l2_tn_info = 7549 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7550 7551 if (l2_tunnel == NULL) 7552 return -EINVAL; 7553 7554 switch (l2_tunnel->l2_tunnel_type) { 7555 case RTE_L2_TUNNEL_TYPE_E_TAG: 7556 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type; 7557 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type); 7558 break; 7559 default: 7560 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7561 ret = -EINVAL; 7562 break; 7563 } 7564 7565 return ret; 7566 } 7567 7568 /* Enable e-tag tunnel */ 7569 static int 7570 ixgbe_e_tag_enable(struct ixgbe_hw *hw) 7571 { 7572 uint32_t etag_etype; 7573 7574 if (hw->mac.type != ixgbe_mac_X550 && 7575 hw->mac.type != ixgbe_mac_X550EM_x && 7576 hw->mac.type != ixgbe_mac_X550EM_a) { 7577 return -ENOTSUP; 7578 } 7579 7580 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7581 etag_etype |= IXGBE_ETAG_ETYPE_VALID; 7582 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7583 IXGBE_WRITE_FLUSH(hw); 7584 7585 return 0; 7586 } 7587 7588 /* Enable l2 tunnel */ 7589 static int 7590 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev, 7591 enum rte_eth_tunnel_type l2_tunnel_type) 7592 { 7593 int ret = 0; 7594 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7595 struct ixgbe_l2_tn_info *l2_tn_info = 7596 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7597 7598 switch (l2_tunnel_type) { 7599 case RTE_L2_TUNNEL_TYPE_E_TAG: 7600 l2_tn_info->e_tag_en = TRUE; 7601 ret = ixgbe_e_tag_enable(hw); 7602 break; 7603 default: 7604 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7605 ret = -EINVAL; 7606 break; 7607 } 7608 7609 return ret; 7610 } 7611 7612 /* Disable e-tag tunnel */ 7613 static int 7614 ixgbe_e_tag_disable(struct ixgbe_hw *hw) 7615 { 7616 uint32_t etag_etype; 7617 7618 if (hw->mac.type != ixgbe_mac_X550 && 7619 hw->mac.type != ixgbe_mac_X550EM_x && 7620 hw->mac.type != ixgbe_mac_X550EM_a) { 7621 return -ENOTSUP; 7622 } 7623 7624 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7625 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID; 7626 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7627 IXGBE_WRITE_FLUSH(hw); 7628 7629 return 0; 7630 } 7631 7632 /* Disable l2 tunnel */ 7633 static int 7634 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev, 7635 enum rte_eth_tunnel_type l2_tunnel_type) 7636 { 7637 int ret = 0; 7638 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7639 struct ixgbe_l2_tn_info *l2_tn_info = 7640 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7641 7642 switch (l2_tunnel_type) { 7643 case RTE_L2_TUNNEL_TYPE_E_TAG: 7644 l2_tn_info->e_tag_en = FALSE; 7645 ret = ixgbe_e_tag_disable(hw); 7646 break; 7647 default: 7648 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7649 ret = -EINVAL; 7650 break; 7651 } 7652 7653 return ret; 7654 } 7655 7656 static int 7657 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev, 7658 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7659 { 7660 int ret = 0; 7661 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7662 uint32_t i, rar_entries; 7663 uint32_t rar_low, rar_high; 7664 7665 if (hw->mac.type != ixgbe_mac_X550 && 7666 hw->mac.type != ixgbe_mac_X550EM_x && 7667 hw->mac.type != ixgbe_mac_X550EM_a) { 7668 return -ENOTSUP; 7669 } 7670 7671 rar_entries = ixgbe_get_num_rx_addrs(hw); 7672 7673 for (i = 1; i < rar_entries; i++) { 7674 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7675 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 7676 if ((rar_high & IXGBE_RAH_AV) && 7677 (rar_high & IXGBE_RAH_ADTYPE) && 7678 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) == 7679 l2_tunnel->tunnel_id)) { 7680 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 7681 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 7682 7683 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL); 7684 7685 return ret; 7686 } 7687 } 7688 7689 return ret; 7690 } 7691 7692 static int 7693 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev, 7694 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7695 { 7696 int ret = 0; 7697 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7698 uint32_t i, rar_entries; 7699 uint32_t rar_low, rar_high; 7700 7701 if (hw->mac.type != ixgbe_mac_X550 && 7702 hw->mac.type != ixgbe_mac_X550EM_x && 7703 hw->mac.type != ixgbe_mac_X550EM_a) { 7704 return -ENOTSUP; 7705 } 7706 7707 /* One entry for one tunnel. Try to remove potential existing entry. */ 7708 ixgbe_e_tag_filter_del(dev, l2_tunnel); 7709 7710 rar_entries = ixgbe_get_num_rx_addrs(hw); 7711 7712 for (i = 1; i < rar_entries; i++) { 7713 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7714 if (rar_high & IXGBE_RAH_AV) { 7715 continue; 7716 } else { 7717 ixgbe_set_vmdq(hw, i, l2_tunnel->pool); 7718 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE; 7719 rar_low = l2_tunnel->tunnel_id; 7720 7721 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low); 7722 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high); 7723 7724 return ret; 7725 } 7726 } 7727 7728 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full." 7729 " Please remove a rule before adding a new one."); 7730 return -EINVAL; 7731 } 7732 7733 static inline struct ixgbe_l2_tn_filter * 7734 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info, 7735 struct ixgbe_l2_tn_key *key) 7736 { 7737 int ret; 7738 7739 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key); 7740 if (ret < 0) 7741 return NULL; 7742 7743 return l2_tn_info->hash_map[ret]; 7744 } 7745 7746 static inline int 7747 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7748 struct ixgbe_l2_tn_filter *l2_tn_filter) 7749 { 7750 int ret; 7751 7752 ret = rte_hash_add_key(l2_tn_info->hash_handle, 7753 &l2_tn_filter->key); 7754 7755 if (ret < 0) { 7756 PMD_DRV_LOG(ERR, 7757 "Failed to insert L2 tunnel filter" 7758 " to hash table %d!", 7759 ret); 7760 return ret; 7761 } 7762 7763 l2_tn_info->hash_map[ret] = l2_tn_filter; 7764 7765 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 7766 7767 return 0; 7768 } 7769 7770 static inline int 7771 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7772 struct ixgbe_l2_tn_key *key) 7773 { 7774 int ret; 7775 struct ixgbe_l2_tn_filter *l2_tn_filter; 7776 7777 ret = rte_hash_del_key(l2_tn_info->hash_handle, key); 7778 7779 if (ret < 0) { 7780 PMD_DRV_LOG(ERR, 7781 "No such L2 tunnel filter to delete %d!", 7782 ret); 7783 return ret; 7784 } 7785 7786 l2_tn_filter = l2_tn_info->hash_map[ret]; 7787 l2_tn_info->hash_map[ret] = NULL; 7788 7789 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 7790 rte_free(l2_tn_filter); 7791 7792 return 0; 7793 } 7794 7795 /* Add l2 tunnel filter */ 7796 int 7797 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 7798 struct rte_eth_l2_tunnel_conf *l2_tunnel, 7799 bool restore) 7800 { 7801 int ret; 7802 struct ixgbe_l2_tn_info *l2_tn_info = 7803 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7804 struct ixgbe_l2_tn_key key; 7805 struct ixgbe_l2_tn_filter *node; 7806 7807 if (!restore) { 7808 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 7809 key.tn_id = l2_tunnel->tunnel_id; 7810 7811 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key); 7812 7813 if (node) { 7814 PMD_DRV_LOG(ERR, 7815 "The L2 tunnel filter already exists!"); 7816 return -EINVAL; 7817 } 7818 7819 node = rte_zmalloc("ixgbe_l2_tn", 7820 sizeof(struct ixgbe_l2_tn_filter), 7821 0); 7822 if (!node) 7823 return -ENOMEM; 7824 7825 rte_memcpy(&node->key, 7826 &key, 7827 sizeof(struct ixgbe_l2_tn_key)); 7828 node->pool = l2_tunnel->pool; 7829 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node); 7830 if (ret < 0) { 7831 rte_free(node); 7832 return ret; 7833 } 7834 } 7835 7836 switch (l2_tunnel->l2_tunnel_type) { 7837 case RTE_L2_TUNNEL_TYPE_E_TAG: 7838 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel); 7839 break; 7840 default: 7841 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7842 ret = -EINVAL; 7843 break; 7844 } 7845 7846 if ((!restore) && (ret < 0)) 7847 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 7848 7849 return ret; 7850 } 7851 7852 /* Delete l2 tunnel filter */ 7853 int 7854 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 7855 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7856 { 7857 int ret; 7858 struct ixgbe_l2_tn_info *l2_tn_info = 7859 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7860 struct ixgbe_l2_tn_key key; 7861 7862 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 7863 key.tn_id = l2_tunnel->tunnel_id; 7864 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 7865 if (ret < 0) 7866 return ret; 7867 7868 switch (l2_tunnel->l2_tunnel_type) { 7869 case RTE_L2_TUNNEL_TYPE_E_TAG: 7870 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel); 7871 break; 7872 default: 7873 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7874 ret = -EINVAL; 7875 break; 7876 } 7877 7878 return ret; 7879 } 7880 7881 /** 7882 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter. 7883 * @dev: pointer to rte_eth_dev structure 7884 * @filter_op:operation will be taken. 7885 * @arg: a pointer to specific structure corresponding to the filter_op 7886 */ 7887 static int 7888 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev, 7889 enum rte_filter_op filter_op, 7890 void *arg) 7891 { 7892 int ret; 7893 7894 if (filter_op == RTE_ETH_FILTER_NOP) 7895 return 0; 7896 7897 if (arg == NULL) { 7898 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 7899 filter_op); 7900 return -EINVAL; 7901 } 7902 7903 switch (filter_op) { 7904 case RTE_ETH_FILTER_ADD: 7905 ret = ixgbe_dev_l2_tunnel_filter_add 7906 (dev, 7907 (struct rte_eth_l2_tunnel_conf *)arg, 7908 FALSE); 7909 break; 7910 case RTE_ETH_FILTER_DELETE: 7911 ret = ixgbe_dev_l2_tunnel_filter_del 7912 (dev, 7913 (struct rte_eth_l2_tunnel_conf *)arg); 7914 break; 7915 default: 7916 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 7917 ret = -EINVAL; 7918 break; 7919 } 7920 return ret; 7921 } 7922 7923 static int 7924 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en) 7925 { 7926 int ret = 0; 7927 uint32_t ctrl; 7928 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7929 7930 if (hw->mac.type != ixgbe_mac_X550 && 7931 hw->mac.type != ixgbe_mac_X550EM_x && 7932 hw->mac.type != ixgbe_mac_X550EM_a) { 7933 return -ENOTSUP; 7934 } 7935 7936 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 7937 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 7938 if (en) 7939 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG; 7940 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 7941 7942 return ret; 7943 } 7944 7945 /* Enable l2 tunnel forwarding */ 7946 static int 7947 ixgbe_dev_l2_tunnel_forwarding_enable 7948 (struct rte_eth_dev *dev, 7949 enum rte_eth_tunnel_type l2_tunnel_type) 7950 { 7951 struct ixgbe_l2_tn_info *l2_tn_info = 7952 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7953 int ret = 0; 7954 7955 switch (l2_tunnel_type) { 7956 case RTE_L2_TUNNEL_TYPE_E_TAG: 7957 l2_tn_info->e_tag_fwd_en = TRUE; 7958 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1); 7959 break; 7960 default: 7961 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7962 ret = -EINVAL; 7963 break; 7964 } 7965 7966 return ret; 7967 } 7968 7969 /* Disable l2 tunnel forwarding */ 7970 static int 7971 ixgbe_dev_l2_tunnel_forwarding_disable 7972 (struct rte_eth_dev *dev, 7973 enum rte_eth_tunnel_type l2_tunnel_type) 7974 { 7975 struct ixgbe_l2_tn_info *l2_tn_info = 7976 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7977 int ret = 0; 7978 7979 switch (l2_tunnel_type) { 7980 case RTE_L2_TUNNEL_TYPE_E_TAG: 7981 l2_tn_info->e_tag_fwd_en = FALSE; 7982 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0); 7983 break; 7984 default: 7985 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7986 ret = -EINVAL; 7987 break; 7988 } 7989 7990 return ret; 7991 } 7992 7993 static int 7994 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev, 7995 struct rte_eth_l2_tunnel_conf *l2_tunnel, 7996 bool en) 7997 { 7998 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 7999 int ret = 0; 8000 uint32_t vmtir, vmvir; 8001 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8002 8003 if (l2_tunnel->vf_id >= pci_dev->max_vfs) { 8004 PMD_DRV_LOG(ERR, 8005 "VF id %u should be less than %u", 8006 l2_tunnel->vf_id, 8007 pci_dev->max_vfs); 8008 return -EINVAL; 8009 } 8010 8011 if (hw->mac.type != ixgbe_mac_X550 && 8012 hw->mac.type != ixgbe_mac_X550EM_x && 8013 hw->mac.type != ixgbe_mac_X550EM_a) { 8014 return -ENOTSUP; 8015 } 8016 8017 if (en) 8018 vmtir = l2_tunnel->tunnel_id; 8019 else 8020 vmtir = 0; 8021 8022 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir); 8023 8024 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id)); 8025 vmvir &= ~IXGBE_VMVIR_TAGA_MASK; 8026 if (en) 8027 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT; 8028 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir); 8029 8030 return ret; 8031 } 8032 8033 /* Enable l2 tunnel tag insertion */ 8034 static int 8035 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev, 8036 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8037 { 8038 int ret = 0; 8039 8040 switch (l2_tunnel->l2_tunnel_type) { 8041 case RTE_L2_TUNNEL_TYPE_E_TAG: 8042 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1); 8043 break; 8044 default: 8045 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8046 ret = -EINVAL; 8047 break; 8048 } 8049 8050 return ret; 8051 } 8052 8053 /* Disable l2 tunnel tag insertion */ 8054 static int 8055 ixgbe_dev_l2_tunnel_insertion_disable 8056 (struct rte_eth_dev *dev, 8057 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8058 { 8059 int ret = 0; 8060 8061 switch (l2_tunnel->l2_tunnel_type) { 8062 case RTE_L2_TUNNEL_TYPE_E_TAG: 8063 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0); 8064 break; 8065 default: 8066 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8067 ret = -EINVAL; 8068 break; 8069 } 8070 8071 return ret; 8072 } 8073 8074 static int 8075 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev, 8076 bool en) 8077 { 8078 int ret = 0; 8079 uint32_t qde; 8080 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8081 8082 if (hw->mac.type != ixgbe_mac_X550 && 8083 hw->mac.type != ixgbe_mac_X550EM_x && 8084 hw->mac.type != ixgbe_mac_X550EM_a) { 8085 return -ENOTSUP; 8086 } 8087 8088 qde = IXGBE_READ_REG(hw, IXGBE_QDE); 8089 if (en) 8090 qde |= IXGBE_QDE_STRIP_TAG; 8091 else 8092 qde &= ~IXGBE_QDE_STRIP_TAG; 8093 qde &= ~IXGBE_QDE_READ; 8094 qde |= IXGBE_QDE_WRITE; 8095 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde); 8096 8097 return ret; 8098 } 8099 8100 /* Enable l2 tunnel tag stripping */ 8101 static int 8102 ixgbe_dev_l2_tunnel_stripping_enable 8103 (struct rte_eth_dev *dev, 8104 enum rte_eth_tunnel_type l2_tunnel_type) 8105 { 8106 int ret = 0; 8107 8108 switch (l2_tunnel_type) { 8109 case RTE_L2_TUNNEL_TYPE_E_TAG: 8110 ret = ixgbe_e_tag_stripping_en_dis(dev, 1); 8111 break; 8112 default: 8113 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8114 ret = -EINVAL; 8115 break; 8116 } 8117 8118 return ret; 8119 } 8120 8121 /* Disable l2 tunnel tag stripping */ 8122 static int 8123 ixgbe_dev_l2_tunnel_stripping_disable 8124 (struct rte_eth_dev *dev, 8125 enum rte_eth_tunnel_type l2_tunnel_type) 8126 { 8127 int ret = 0; 8128 8129 switch (l2_tunnel_type) { 8130 case RTE_L2_TUNNEL_TYPE_E_TAG: 8131 ret = ixgbe_e_tag_stripping_en_dis(dev, 0); 8132 break; 8133 default: 8134 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8135 ret = -EINVAL; 8136 break; 8137 } 8138 8139 return ret; 8140 } 8141 8142 /* Enable/disable l2 tunnel offload functions */ 8143 static int 8144 ixgbe_dev_l2_tunnel_offload_set 8145 (struct rte_eth_dev *dev, 8146 struct rte_eth_l2_tunnel_conf *l2_tunnel, 8147 uint32_t mask, 8148 uint8_t en) 8149 { 8150 int ret = 0; 8151 8152 if (l2_tunnel == NULL) 8153 return -EINVAL; 8154 8155 ret = -EINVAL; 8156 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) { 8157 if (en) 8158 ret = ixgbe_dev_l2_tunnel_enable( 8159 dev, 8160 l2_tunnel->l2_tunnel_type); 8161 else 8162 ret = ixgbe_dev_l2_tunnel_disable( 8163 dev, 8164 l2_tunnel->l2_tunnel_type); 8165 } 8166 8167 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) { 8168 if (en) 8169 ret = ixgbe_dev_l2_tunnel_insertion_enable( 8170 dev, 8171 l2_tunnel); 8172 else 8173 ret = ixgbe_dev_l2_tunnel_insertion_disable( 8174 dev, 8175 l2_tunnel); 8176 } 8177 8178 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) { 8179 if (en) 8180 ret = ixgbe_dev_l2_tunnel_stripping_enable( 8181 dev, 8182 l2_tunnel->l2_tunnel_type); 8183 else 8184 ret = ixgbe_dev_l2_tunnel_stripping_disable( 8185 dev, 8186 l2_tunnel->l2_tunnel_type); 8187 } 8188 8189 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) { 8190 if (en) 8191 ret = ixgbe_dev_l2_tunnel_forwarding_enable( 8192 dev, 8193 l2_tunnel->l2_tunnel_type); 8194 else 8195 ret = ixgbe_dev_l2_tunnel_forwarding_disable( 8196 dev, 8197 l2_tunnel->l2_tunnel_type); 8198 } 8199 8200 return ret; 8201 } 8202 8203 static int 8204 ixgbe_update_vxlan_port(struct ixgbe_hw *hw, 8205 uint16_t port) 8206 { 8207 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port); 8208 IXGBE_WRITE_FLUSH(hw); 8209 8210 return 0; 8211 } 8212 8213 /* There's only one register for VxLAN UDP port. 8214 * So, we cannot add several ports. Will update it. 8215 */ 8216 static int 8217 ixgbe_add_vxlan_port(struct ixgbe_hw *hw, 8218 uint16_t port) 8219 { 8220 if (port == 0) { 8221 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 8222 return -EINVAL; 8223 } 8224 8225 return ixgbe_update_vxlan_port(hw, port); 8226 } 8227 8228 /* We cannot delete the VxLAN port. For there's a register for VxLAN 8229 * UDP port, it must have a value. 8230 * So, will reset it to the original value 0. 8231 */ 8232 static int 8233 ixgbe_del_vxlan_port(struct ixgbe_hw *hw, 8234 uint16_t port) 8235 { 8236 uint16_t cur_port; 8237 8238 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL); 8239 8240 if (cur_port != port) { 8241 PMD_DRV_LOG(ERR, "Port %u does not exist.", port); 8242 return -EINVAL; 8243 } 8244 8245 return ixgbe_update_vxlan_port(hw, 0); 8246 } 8247 8248 /* Add UDP tunneling port */ 8249 static int 8250 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 8251 struct rte_eth_udp_tunnel *udp_tunnel) 8252 { 8253 int ret = 0; 8254 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8255 8256 if (hw->mac.type != ixgbe_mac_X550 && 8257 hw->mac.type != ixgbe_mac_X550EM_x && 8258 hw->mac.type != ixgbe_mac_X550EM_a) { 8259 return -ENOTSUP; 8260 } 8261 8262 if (udp_tunnel == NULL) 8263 return -EINVAL; 8264 8265 switch (udp_tunnel->prot_type) { 8266 case RTE_TUNNEL_TYPE_VXLAN: 8267 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port); 8268 break; 8269 8270 case RTE_TUNNEL_TYPE_GENEVE: 8271 case RTE_TUNNEL_TYPE_TEREDO: 8272 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8273 ret = -EINVAL; 8274 break; 8275 8276 default: 8277 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8278 ret = -EINVAL; 8279 break; 8280 } 8281 8282 return ret; 8283 } 8284 8285 /* Remove UDP tunneling port */ 8286 static int 8287 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 8288 struct rte_eth_udp_tunnel *udp_tunnel) 8289 { 8290 int ret = 0; 8291 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8292 8293 if (hw->mac.type != ixgbe_mac_X550 && 8294 hw->mac.type != ixgbe_mac_X550EM_x && 8295 hw->mac.type != ixgbe_mac_X550EM_a) { 8296 return -ENOTSUP; 8297 } 8298 8299 if (udp_tunnel == NULL) 8300 return -EINVAL; 8301 8302 switch (udp_tunnel->prot_type) { 8303 case RTE_TUNNEL_TYPE_VXLAN: 8304 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port); 8305 break; 8306 case RTE_TUNNEL_TYPE_GENEVE: 8307 case RTE_TUNNEL_TYPE_TEREDO: 8308 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8309 ret = -EINVAL; 8310 break; 8311 default: 8312 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8313 ret = -EINVAL; 8314 break; 8315 } 8316 8317 return ret; 8318 } 8319 8320 static void 8321 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev) 8322 { 8323 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8324 8325 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC); 8326 } 8327 8328 static void 8329 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev) 8330 { 8331 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8332 8333 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE); 8334 } 8335 8336 static void 8337 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev) 8338 { 8339 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8340 8341 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI); 8342 } 8343 8344 static void 8345 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev) 8346 { 8347 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8348 8349 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI); 8350 } 8351 8352 static void ixgbevf_mbx_process(struct rte_eth_dev *dev) 8353 { 8354 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8355 u32 in_msg = 0; 8356 8357 /* peek the message first */ 8358 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM); 8359 8360 /* PF reset VF event */ 8361 if (in_msg == IXGBE_PF_CONTROL_MSG) { 8362 /* dummy mbx read to ack pf */ 8363 if (ixgbe_read_mbx(hw, &in_msg, 1, 0)) 8364 return; 8365 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 8366 NULL); 8367 } 8368 } 8369 8370 static int 8371 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev) 8372 { 8373 uint32_t eicr; 8374 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8375 struct ixgbe_interrupt *intr = 8376 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8377 ixgbevf_intr_disable(dev); 8378 8379 /* read-on-clear nic registers here */ 8380 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR); 8381 intr->flags = 0; 8382 8383 /* only one misc vector supported - mailbox */ 8384 eicr &= IXGBE_VTEICR_MASK; 8385 if (eicr == IXGBE_MISC_VEC_ID) 8386 intr->flags |= IXGBE_FLAG_MAILBOX; 8387 8388 return 0; 8389 } 8390 8391 static int 8392 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev) 8393 { 8394 struct ixgbe_interrupt *intr = 8395 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8396 8397 if (intr->flags & IXGBE_FLAG_MAILBOX) { 8398 ixgbevf_mbx_process(dev); 8399 intr->flags &= ~IXGBE_FLAG_MAILBOX; 8400 } 8401 8402 ixgbevf_intr_enable(dev); 8403 8404 return 0; 8405 } 8406 8407 static void 8408 ixgbevf_dev_interrupt_handler(void *param) 8409 { 8410 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 8411 8412 ixgbevf_dev_interrupt_get_status(dev); 8413 ixgbevf_dev_interrupt_action(dev); 8414 } 8415 8416 /** 8417 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path 8418 * @hw: pointer to hardware structure 8419 * 8420 * Stops the transmit data path and waits for the HW to internally empty 8421 * the Tx security block 8422 **/ 8423 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw) 8424 { 8425 #define IXGBE_MAX_SECTX_POLL 40 8426 8427 int i; 8428 int sectxreg; 8429 8430 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8431 sectxreg |= IXGBE_SECTXCTRL_TX_DIS; 8432 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8433 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) { 8434 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT); 8435 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY) 8436 break; 8437 /* Use interrupt-safe sleep just in case */ 8438 usec_delay(1000); 8439 } 8440 8441 /* For informational purposes only */ 8442 if (i >= IXGBE_MAX_SECTX_POLL) 8443 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security " 8444 "path fully disabled. Continuing with init."); 8445 8446 return IXGBE_SUCCESS; 8447 } 8448 8449 /** 8450 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path 8451 * @hw: pointer to hardware structure 8452 * 8453 * Enables the transmit data path. 8454 **/ 8455 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw) 8456 { 8457 uint32_t sectxreg; 8458 8459 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8460 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS; 8461 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8462 IXGBE_WRITE_FLUSH(hw); 8463 8464 return IXGBE_SUCCESS; 8465 } 8466 8467 /* restore n-tuple filter */ 8468 static inline void 8469 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev) 8470 { 8471 struct ixgbe_filter_info *filter_info = 8472 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8473 struct ixgbe_5tuple_filter *node; 8474 8475 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) { 8476 ixgbe_inject_5tuple_filter(dev, node); 8477 } 8478 } 8479 8480 /* restore ethernet type filter */ 8481 static inline void 8482 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev) 8483 { 8484 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8485 struct ixgbe_filter_info *filter_info = 8486 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8487 int i; 8488 8489 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8490 if (filter_info->ethertype_mask & (1 << i)) { 8491 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 8492 filter_info->ethertype_filters[i].etqf); 8493 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 8494 filter_info->ethertype_filters[i].etqs); 8495 IXGBE_WRITE_FLUSH(hw); 8496 } 8497 } 8498 } 8499 8500 /* restore SYN filter */ 8501 static inline void 8502 ixgbe_syn_filter_restore(struct rte_eth_dev *dev) 8503 { 8504 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8505 struct ixgbe_filter_info *filter_info = 8506 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8507 uint32_t synqf; 8508 8509 synqf = filter_info->syn_info; 8510 8511 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 8512 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 8513 IXGBE_WRITE_FLUSH(hw); 8514 } 8515 } 8516 8517 /* restore L2 tunnel filter */ 8518 static inline void 8519 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev) 8520 { 8521 struct ixgbe_l2_tn_info *l2_tn_info = 8522 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8523 struct ixgbe_l2_tn_filter *node; 8524 struct rte_eth_l2_tunnel_conf l2_tn_conf; 8525 8526 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) { 8527 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type; 8528 l2_tn_conf.tunnel_id = node->key.tn_id; 8529 l2_tn_conf.pool = node->pool; 8530 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE); 8531 } 8532 } 8533 8534 /* restore rss filter */ 8535 static inline void 8536 ixgbe_rss_filter_restore(struct rte_eth_dev *dev) 8537 { 8538 struct ixgbe_filter_info *filter_info = 8539 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8540 8541 if (filter_info->rss_info.conf.queue_num) 8542 ixgbe_config_rss_filter(dev, 8543 &filter_info->rss_info, TRUE); 8544 } 8545 8546 static int 8547 ixgbe_filter_restore(struct rte_eth_dev *dev) 8548 { 8549 ixgbe_ntuple_filter_restore(dev); 8550 ixgbe_ethertype_filter_restore(dev); 8551 ixgbe_syn_filter_restore(dev); 8552 ixgbe_fdir_filter_restore(dev); 8553 ixgbe_l2_tn_filter_restore(dev); 8554 ixgbe_rss_filter_restore(dev); 8555 8556 return 0; 8557 } 8558 8559 static void 8560 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev) 8561 { 8562 struct ixgbe_l2_tn_info *l2_tn_info = 8563 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8564 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8565 8566 if (l2_tn_info->e_tag_en) 8567 (void)ixgbe_e_tag_enable(hw); 8568 8569 if (l2_tn_info->e_tag_fwd_en) 8570 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1); 8571 8572 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type); 8573 } 8574 8575 /* remove all the n-tuple filters */ 8576 void 8577 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev) 8578 { 8579 struct ixgbe_filter_info *filter_info = 8580 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8581 struct ixgbe_5tuple_filter *p_5tuple; 8582 8583 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) 8584 ixgbe_remove_5tuple_filter(dev, p_5tuple); 8585 } 8586 8587 /* remove all the ether type filters */ 8588 void 8589 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev) 8590 { 8591 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8592 struct ixgbe_filter_info *filter_info = 8593 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8594 int i; 8595 8596 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8597 if (filter_info->ethertype_mask & (1 << i) && 8598 !filter_info->ethertype_filters[i].conf) { 8599 (void)ixgbe_ethertype_filter_remove(filter_info, 8600 (uint8_t)i); 8601 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0); 8602 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0); 8603 IXGBE_WRITE_FLUSH(hw); 8604 } 8605 } 8606 } 8607 8608 /* remove the SYN filter */ 8609 void 8610 ixgbe_clear_syn_filter(struct rte_eth_dev *dev) 8611 { 8612 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8613 struct ixgbe_filter_info *filter_info = 8614 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8615 8616 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) { 8617 filter_info->syn_info = 0; 8618 8619 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0); 8620 IXGBE_WRITE_FLUSH(hw); 8621 } 8622 } 8623 8624 /* remove all the L2 tunnel filters */ 8625 int 8626 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev) 8627 { 8628 struct ixgbe_l2_tn_info *l2_tn_info = 8629 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8630 struct ixgbe_l2_tn_filter *l2_tn_filter; 8631 struct rte_eth_l2_tunnel_conf l2_tn_conf; 8632 int ret = 0; 8633 8634 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 8635 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type; 8636 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id; 8637 l2_tn_conf.pool = l2_tn_filter->pool; 8638 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf); 8639 if (ret < 0) 8640 return ret; 8641 } 8642 8643 return 0; 8644 } 8645 8646 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd); 8647 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map); 8648 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 8649 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd); 8650 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map); 8651 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci"); 8652 8653 RTE_INIT(ixgbe_init_log) 8654 { 8655 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init"); 8656 if (ixgbe_logtype_init >= 0) 8657 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE); 8658 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver"); 8659 if (ixgbe_logtype_driver >= 0) 8660 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE); 8661 } 8662