1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <inttypes.h> 13 #include <netinet/in.h> 14 #include <rte_string_fns.h> 15 #include <rte_byteorder.h> 16 #include <rte_common.h> 17 #include <rte_cycles.h> 18 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_bus_pci.h> 24 #include <rte_branch_prediction.h> 25 #include <rte_memory.h> 26 #include <rte_kvargs.h> 27 #include <rte_eal.h> 28 #include <rte_alarm.h> 29 #include <rte_ether.h> 30 #include <rte_ethdev_driver.h> 31 #include <rte_ethdev_pci.h> 32 #include <rte_malloc.h> 33 #include <rte_random.h> 34 #include <rte_dev.h> 35 #include <rte_hash_crc.h> 36 #ifdef RTE_LIBRTE_SECURITY 37 #include <rte_security_driver.h> 38 #endif 39 40 #include "ixgbe_logs.h" 41 #include "base/ixgbe_api.h" 42 #include "base/ixgbe_vf.h" 43 #include "base/ixgbe_common.h" 44 #include "ixgbe_ethdev.h" 45 #include "ixgbe_bypass.h" 46 #include "ixgbe_rxtx.h" 47 #include "base/ixgbe_type.h" 48 #include "base/ixgbe_phy.h" 49 #include "ixgbe_regs.h" 50 51 /* 52 * High threshold controlling when to start sending XOFF frames. Must be at 53 * least 8 bytes less than receive packet buffer size. This value is in units 54 * of 1024 bytes. 55 */ 56 #define IXGBE_FC_HI 0x80 57 58 /* 59 * Low threshold controlling when to start sending XON frames. This value is 60 * in units of 1024 bytes. 61 */ 62 #define IXGBE_FC_LO 0x40 63 64 /* Timer value included in XOFF frames. */ 65 #define IXGBE_FC_PAUSE 0x680 66 67 /*Default value of Max Rx Queue*/ 68 #define IXGBE_MAX_RX_QUEUE_NUM 128 69 70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */ 71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */ 72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */ 73 74 #define IXGBE_MMW_SIZE_DEFAULT 0x4 75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14 76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */ 77 78 /* 79 * Default values for RX/TX configuration 80 */ 81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32 82 #define IXGBE_DEFAULT_RX_PTHRESH 8 83 #define IXGBE_DEFAULT_RX_HTHRESH 8 84 #define IXGBE_DEFAULT_RX_WTHRESH 0 85 86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32 87 #define IXGBE_DEFAULT_TX_PTHRESH 32 88 #define IXGBE_DEFAULT_TX_HTHRESH 0 89 #define IXGBE_DEFAULT_TX_WTHRESH 0 90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32 91 92 /* Bit shift and mask */ 93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2) 94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t) 95 #define IXGBE_8_BIT_WIDTH CHAR_BIT 96 #define IXGBE_8_BIT_MASK UINT8_MAX 97 98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */ 99 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0])) 101 102 /* Additional timesync values. */ 103 #define NSEC_PER_SEC 1000000000L 104 #define IXGBE_INCVAL_10GB 0x66666666 105 #define IXGBE_INCVAL_1GB 0x40000000 106 #define IXGBE_INCVAL_100 0x50000000 107 #define IXGBE_INCVAL_SHIFT_10GB 28 108 #define IXGBE_INCVAL_SHIFT_1GB 24 109 #define IXGBE_INCVAL_SHIFT_100 21 110 #define IXGBE_INCVAL_SHIFT_82599 7 111 #define IXGBE_INCPER_SHIFT_82599 24 112 113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL 114 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000 117 #define IXGBE_ETAG_ETYPE 0x00005084 118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff 119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000 120 #define IXGBE_RAH_ADTYPE 0x40000000 121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff 122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */ 125 #define IXGBE_QDE_STRIP_TAG 0x00000004 126 #define IXGBE_VTEICR_MASK 0x07 127 128 #define IXGBE_EXVET_VET_EXT_SHIFT 16 129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000 130 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk" 132 133 static const char * const ixgbevf_valid_arguments[] = { 134 IXGBEVF_DEVARG_PFLINK_FULLCHK, 135 NULL 136 }; 137 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev); 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev); 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev); 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev); 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev); 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev); 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev); 146 static int ixgbe_dev_start(struct rte_eth_dev *dev); 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev); 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev); 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev); 150 static void ixgbe_dev_close(struct rte_eth_dev *dev); 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev); 152 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 153 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 154 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 155 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev, 157 int wait_to_complete); 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev, 159 struct rte_eth_stats *stats); 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev, 161 struct rte_eth_xstat *xstats, unsigned n); 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, 163 struct rte_eth_xstat *xstats, unsigned n); 164 static int 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 166 uint64_t *values, unsigned int n); 167 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev); 168 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev); 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 170 struct rte_eth_xstat_name *xstats_names, 171 unsigned int size); 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev, 173 struct rte_eth_xstat_name *xstats_names, unsigned limit); 174 static int ixgbe_dev_xstats_get_names_by_id( 175 struct rte_eth_dev *dev, 176 struct rte_eth_xstat_name *xstats_names, 177 const uint64_t *ids, 178 unsigned int limit); 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 180 uint16_t queue_id, 181 uint8_t stat_idx, 182 uint8_t is_rx); 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 184 size_t fw_size); 185 static void ixgbe_dev_info_get(struct rte_eth_dev *dev, 186 struct rte_eth_dev_info *dev_info); 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); 188 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev, 189 struct rte_eth_dev_info *dev_info); 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 191 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev, 193 uint16_t vlan_id, int on); 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 195 enum rte_vlan_type vlan_type, 196 uint16_t tpid_id); 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, 198 uint16_t queue, bool on); 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, 200 int on); 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, 202 int mask); 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask); 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask); 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue); 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue); 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev); 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev); 209 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev); 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev); 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, 213 struct rte_eth_fc_conf *fc_conf); 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, 215 struct rte_eth_fc_conf *fc_conf); 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 217 struct rte_eth_pfc_conf *pfc_conf); 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 219 struct rte_eth_rss_reta_entry64 *reta_conf, 220 uint16_t reta_size); 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 222 struct rte_eth_rss_reta_entry64 *reta_conf, 223 uint16_t reta_size); 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev); 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev); 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev); 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev); 230 static void ixgbe_dev_interrupt_handler(void *param); 231 static void ixgbe_dev_interrupt_delayed_handler(void *param); 232 static void ixgbe_dev_setup_link_alarm_handler(void *param); 233 234 static int ixgbe_add_rar(struct rte_eth_dev *dev, 235 struct rte_ether_addr *mac_addr, 236 uint32_t index, uint32_t pool); 237 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index); 238 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, 239 struct rte_ether_addr *mac_addr); 240 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config); 241 static bool is_device_supported(struct rte_eth_dev *dev, 242 struct rte_pci_driver *drv); 243 244 /* For Virtual Function support */ 245 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev); 246 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev); 247 static int ixgbevf_dev_configure(struct rte_eth_dev *dev); 248 static int ixgbevf_dev_start(struct rte_eth_dev *dev); 249 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev, 250 int wait_to_complete); 251 static void ixgbevf_dev_stop(struct rte_eth_dev *dev); 252 static void ixgbevf_dev_close(struct rte_eth_dev *dev); 253 static int ixgbevf_dev_reset(struct rte_eth_dev *dev); 254 static void ixgbevf_intr_disable(struct rte_eth_dev *dev); 255 static void ixgbevf_intr_enable(struct rte_eth_dev *dev); 256 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev, 257 struct rte_eth_stats *stats); 258 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev); 259 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, 260 uint16_t vlan_id, int on); 261 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, 262 uint16_t queue, int on); 263 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask); 264 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask); 265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on); 266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 267 uint16_t queue_id); 268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 269 uint16_t queue_id); 270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 271 uint8_t queue, uint8_t msix_vector); 272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev); 273 static void ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev); 274 static void ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev); 275 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev); 276 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev); 277 278 /* For Eth VMDQ APIs support */ 279 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct 280 rte_ether_addr * mac_addr, uint8_t on); 281 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on); 282 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 283 struct rte_eth_mirror_conf *mirror_conf, 284 uint8_t rule_id, uint8_t on); 285 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, 286 uint8_t rule_id); 287 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 288 uint16_t queue_id); 289 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 290 uint16_t queue_id); 291 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 292 uint8_t queue, uint8_t msix_vector); 293 static void ixgbe_configure_msix(struct rte_eth_dev *dev); 294 295 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev, 296 struct rte_ether_addr *mac_addr, 297 uint32_t index, uint32_t pool); 298 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index); 299 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 300 struct rte_ether_addr *mac_addr); 301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev, 302 struct rte_eth_syn_filter *filter); 303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev, 304 enum rte_filter_op filter_op, 305 void *arg); 306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 307 struct ixgbe_5tuple_filter *filter); 308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 309 struct ixgbe_5tuple_filter *filter); 310 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev, 311 enum rte_filter_op filter_op, 312 void *arg); 313 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev, 314 struct rte_eth_ntuple_filter *filter); 315 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev, 316 enum rte_filter_op filter_op, 317 void *arg); 318 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, 319 struct rte_eth_ethertype_filter *filter); 320 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 321 enum rte_filter_type filter_type, 322 enum rte_filter_op filter_op, 323 void *arg); 324 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 325 326 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 327 struct rte_ether_addr *mc_addr_set, 328 uint32_t nb_mc_addr); 329 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 330 struct rte_eth_dcb_info *dcb_info); 331 332 static int ixgbe_get_reg_length(struct rte_eth_dev *dev); 333 static int ixgbe_get_regs(struct rte_eth_dev *dev, 334 struct rte_dev_reg_info *regs); 335 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev); 336 static int ixgbe_get_eeprom(struct rte_eth_dev *dev, 337 struct rte_dev_eeprom_info *eeprom); 338 static int ixgbe_set_eeprom(struct rte_eth_dev *dev, 339 struct rte_dev_eeprom_info *eeprom); 340 341 static int ixgbe_get_module_info(struct rte_eth_dev *dev, 342 struct rte_eth_dev_module_info *modinfo); 343 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 344 struct rte_dev_eeprom_info *info); 345 346 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev); 347 static int ixgbevf_get_regs(struct rte_eth_dev *dev, 348 struct rte_dev_reg_info *regs); 349 350 static int ixgbe_timesync_enable(struct rte_eth_dev *dev); 351 static int ixgbe_timesync_disable(struct rte_eth_dev *dev); 352 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 353 struct timespec *timestamp, 354 uint32_t flags); 355 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 356 struct timespec *timestamp); 357 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 358 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev, 359 struct timespec *timestamp); 360 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev, 361 const struct timespec *timestamp); 362 static void ixgbevf_dev_interrupt_handler(void *param); 363 364 static int ixgbe_dev_l2_tunnel_eth_type_conf 365 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel); 366 static int ixgbe_dev_l2_tunnel_offload_set 367 (struct rte_eth_dev *dev, 368 struct rte_eth_l2_tunnel_conf *l2_tunnel, 369 uint32_t mask, 370 uint8_t en); 371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev, 372 enum rte_filter_op filter_op, 373 void *arg); 374 375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 376 struct rte_eth_udp_tunnel *udp_tunnel); 377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 378 struct rte_eth_udp_tunnel *udp_tunnel); 379 static int ixgbe_filter_restore(struct rte_eth_dev *dev); 380 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev); 381 382 /* 383 * Define VF Stats MACRO for Non "cleared on read" register 384 */ 385 #define UPDATE_VF_STAT(reg, last, cur) \ 386 { \ 387 uint32_t latest = IXGBE_READ_REG(hw, reg); \ 388 cur += (latest - last) & UINT_MAX; \ 389 last = latest; \ 390 } 391 392 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \ 393 { \ 394 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \ 395 u64 new_msb = IXGBE_READ_REG(hw, msb); \ 396 u64 latest = ((new_msb << 32) | new_lsb); \ 397 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \ 398 last = latest; \ 399 } 400 401 #define IXGBE_SET_HWSTRIP(h, q) do {\ 402 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 403 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 404 (h)->bitmap[idx] |= 1 << bit;\ 405 } while (0) 406 407 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\ 408 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 409 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 410 (h)->bitmap[idx] &= ~(1 << bit);\ 411 } while (0) 412 413 #define IXGBE_GET_HWSTRIP(h, q, r) do {\ 414 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 415 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 416 (r) = (h)->bitmap[idx] >> bit & 1;\ 417 } while (0) 418 419 int ixgbe_logtype_init; 420 int ixgbe_logtype_driver; 421 422 /* 423 * The set of PCI devices this driver supports 424 */ 425 static const struct rte_pci_id pci_id_ixgbe_map[] = { 426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) }, 427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) }, 428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) }, 429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) }, 430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) }, 431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) }, 432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) }, 433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) }, 434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) }, 435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) }, 436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) }, 437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) }, 438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) }, 439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) }, 440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) }, 441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) }, 442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) }, 443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) }, 444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) }, 445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) }, 446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) }, 447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) }, 448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) }, 449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) }, 450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) }, 451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) }, 452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) }, 453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) }, 454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) }, 455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) }, 456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) }, 457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) }, 458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) }, 459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) }, 460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) }, 461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) }, 462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) }, 463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) }, 464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) }, 465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) }, 466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) }, 467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) }, 468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) }, 469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) }, 470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) }, 471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) }, 472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) }, 473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) }, 474 #ifdef RTE_LIBRTE_IXGBE_BYPASS 475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) }, 476 #endif 477 { .vendor_id = 0, /* sentinel */ }, 478 }; 479 480 /* 481 * The set of PCI devices this driver supports (for 82599 VF) 482 */ 483 static const struct rte_pci_id pci_id_ixgbevf_map[] = { 484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) }, 485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) }, 486 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) }, 487 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) }, 488 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) }, 489 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) }, 490 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) }, 491 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) }, 492 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) }, 493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) }, 494 { .vendor_id = 0, /* sentinel */ }, 495 }; 496 497 static const struct rte_eth_desc_lim rx_desc_lim = { 498 .nb_max = IXGBE_MAX_RING_DESC, 499 .nb_min = IXGBE_MIN_RING_DESC, 500 .nb_align = IXGBE_RXD_ALIGN, 501 }; 502 503 static const struct rte_eth_desc_lim tx_desc_lim = { 504 .nb_max = IXGBE_MAX_RING_DESC, 505 .nb_min = IXGBE_MIN_RING_DESC, 506 .nb_align = IXGBE_TXD_ALIGN, 507 .nb_seg_max = IXGBE_TX_MAX_SEG, 508 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG, 509 }; 510 511 static const struct eth_dev_ops ixgbe_eth_dev_ops = { 512 .dev_configure = ixgbe_dev_configure, 513 .dev_start = ixgbe_dev_start, 514 .dev_stop = ixgbe_dev_stop, 515 .dev_set_link_up = ixgbe_dev_set_link_up, 516 .dev_set_link_down = ixgbe_dev_set_link_down, 517 .dev_close = ixgbe_dev_close, 518 .dev_reset = ixgbe_dev_reset, 519 .promiscuous_enable = ixgbe_dev_promiscuous_enable, 520 .promiscuous_disable = ixgbe_dev_promiscuous_disable, 521 .allmulticast_enable = ixgbe_dev_allmulticast_enable, 522 .allmulticast_disable = ixgbe_dev_allmulticast_disable, 523 .link_update = ixgbe_dev_link_update, 524 .stats_get = ixgbe_dev_stats_get, 525 .xstats_get = ixgbe_dev_xstats_get, 526 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id, 527 .stats_reset = ixgbe_dev_stats_reset, 528 .xstats_reset = ixgbe_dev_xstats_reset, 529 .xstats_get_names = ixgbe_dev_xstats_get_names, 530 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id, 531 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set, 532 .fw_version_get = ixgbe_fw_version_get, 533 .dev_infos_get = ixgbe_dev_info_get, 534 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 535 .mtu_set = ixgbe_dev_mtu_set, 536 .vlan_filter_set = ixgbe_vlan_filter_set, 537 .vlan_tpid_set = ixgbe_vlan_tpid_set, 538 .vlan_offload_set = ixgbe_vlan_offload_set, 539 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set, 540 .rx_queue_start = ixgbe_dev_rx_queue_start, 541 .rx_queue_stop = ixgbe_dev_rx_queue_stop, 542 .tx_queue_start = ixgbe_dev_tx_queue_start, 543 .tx_queue_stop = ixgbe_dev_tx_queue_stop, 544 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 545 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable, 546 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable, 547 .rx_queue_release = ixgbe_dev_rx_queue_release, 548 .rx_queue_count = ixgbe_dev_rx_queue_count, 549 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done, 550 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status, 551 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status, 552 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 553 .tx_queue_release = ixgbe_dev_tx_queue_release, 554 .dev_led_on = ixgbe_dev_led_on, 555 .dev_led_off = ixgbe_dev_led_off, 556 .flow_ctrl_get = ixgbe_flow_ctrl_get, 557 .flow_ctrl_set = ixgbe_flow_ctrl_set, 558 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set, 559 .mac_addr_add = ixgbe_add_rar, 560 .mac_addr_remove = ixgbe_remove_rar, 561 .mac_addr_set = ixgbe_set_default_mac_addr, 562 .uc_hash_table_set = ixgbe_uc_hash_table_set, 563 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set, 564 .mirror_rule_set = ixgbe_mirror_rule_set, 565 .mirror_rule_reset = ixgbe_mirror_rule_reset, 566 .set_queue_rate_limit = ixgbe_set_queue_rate_limit, 567 .reta_update = ixgbe_dev_rss_reta_update, 568 .reta_query = ixgbe_dev_rss_reta_query, 569 .rss_hash_update = ixgbe_dev_rss_hash_update, 570 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 571 .filter_ctrl = ixgbe_dev_filter_ctrl, 572 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 573 .rxq_info_get = ixgbe_rxq_info_get, 574 .txq_info_get = ixgbe_txq_info_get, 575 .timesync_enable = ixgbe_timesync_enable, 576 .timesync_disable = ixgbe_timesync_disable, 577 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp, 578 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp, 579 .get_reg = ixgbe_get_regs, 580 .get_eeprom_length = ixgbe_get_eeprom_length, 581 .get_eeprom = ixgbe_get_eeprom, 582 .set_eeprom = ixgbe_set_eeprom, 583 .get_module_info = ixgbe_get_module_info, 584 .get_module_eeprom = ixgbe_get_module_eeprom, 585 .get_dcb_info = ixgbe_dev_get_dcb_info, 586 .timesync_adjust_time = ixgbe_timesync_adjust_time, 587 .timesync_read_time = ixgbe_timesync_read_time, 588 .timesync_write_time = ixgbe_timesync_write_time, 589 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf, 590 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set, 591 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add, 592 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del, 593 .tm_ops_get = ixgbe_tm_ops_get, 594 }; 595 596 /* 597 * dev_ops for virtual function, bare necessities for basic vf 598 * operation have been implemented 599 */ 600 static const struct eth_dev_ops ixgbevf_eth_dev_ops = { 601 .dev_configure = ixgbevf_dev_configure, 602 .dev_start = ixgbevf_dev_start, 603 .dev_stop = ixgbevf_dev_stop, 604 .link_update = ixgbevf_dev_link_update, 605 .stats_get = ixgbevf_dev_stats_get, 606 .xstats_get = ixgbevf_dev_xstats_get, 607 .stats_reset = ixgbevf_dev_stats_reset, 608 .xstats_reset = ixgbevf_dev_stats_reset, 609 .xstats_get_names = ixgbevf_dev_xstats_get_names, 610 .dev_close = ixgbevf_dev_close, 611 .dev_reset = ixgbevf_dev_reset, 612 .promiscuous_enable = ixgbevf_dev_promiscuous_enable, 613 .promiscuous_disable = ixgbevf_dev_promiscuous_disable, 614 .allmulticast_enable = ixgbevf_dev_allmulticast_enable, 615 .allmulticast_disable = ixgbevf_dev_allmulticast_disable, 616 .dev_infos_get = ixgbevf_dev_info_get, 617 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 618 .mtu_set = ixgbevf_dev_set_mtu, 619 .vlan_filter_set = ixgbevf_vlan_filter_set, 620 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set, 621 .vlan_offload_set = ixgbevf_vlan_offload_set, 622 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 623 .rx_queue_release = ixgbe_dev_rx_queue_release, 624 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done, 625 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status, 626 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status, 627 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 628 .tx_queue_release = ixgbe_dev_tx_queue_release, 629 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable, 630 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable, 631 .mac_addr_add = ixgbevf_add_mac_addr, 632 .mac_addr_remove = ixgbevf_remove_mac_addr, 633 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 634 .rxq_info_get = ixgbe_rxq_info_get, 635 .txq_info_get = ixgbe_txq_info_get, 636 .mac_addr_set = ixgbevf_set_default_mac_addr, 637 .get_reg = ixgbevf_get_regs, 638 .reta_update = ixgbe_dev_rss_reta_update, 639 .reta_query = ixgbe_dev_rss_reta_query, 640 .rss_hash_update = ixgbe_dev_rss_hash_update, 641 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 642 }; 643 644 /* store statistics names and its offset in stats structure */ 645 struct rte_ixgbe_xstats_name_off { 646 char name[RTE_ETH_XSTATS_NAME_SIZE]; 647 unsigned offset; 648 }; 649 650 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = { 651 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)}, 652 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)}, 653 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)}, 654 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)}, 655 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)}, 656 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)}, 657 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)}, 658 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)}, 659 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)}, 660 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)}, 661 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)}, 662 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)}, 663 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)}, 664 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)}, 665 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 666 prc1023)}, 667 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 668 prc1522)}, 669 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)}, 670 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)}, 671 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)}, 672 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)}, 673 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)}, 674 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)}, 675 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)}, 676 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)}, 677 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)}, 678 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)}, 679 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)}, 680 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)}, 681 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)}, 682 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)}, 683 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)}, 684 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)}, 685 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 686 ptc1023)}, 687 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 688 ptc1522)}, 689 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)}, 690 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)}, 691 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)}, 692 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)}, 693 694 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats, 695 fdirustat_add)}, 696 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats, 697 fdirustat_remove)}, 698 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats, 699 fdirfstat_fadd)}, 700 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats, 701 fdirfstat_fremove)}, 702 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats, 703 fdirmatch)}, 704 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats, 705 fdirmiss)}, 706 707 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)}, 708 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)}, 709 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, 710 fclast)}, 711 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)}, 712 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)}, 713 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)}, 714 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)}, 715 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats, 716 fcoe_noddp)}, 717 {"rx_fcoe_no_direct_data_placement_ext_buff", 718 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)}, 719 720 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 721 lxontxc)}, 722 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 723 lxonrxc)}, 724 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 725 lxofftxc)}, 726 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 727 lxoffrxc)}, 728 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)}, 729 }; 730 731 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \ 732 sizeof(rte_ixgbe_stats_strings[0])) 733 734 /* MACsec statistics */ 735 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = { 736 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 737 out_pkts_untagged)}, 738 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats, 739 out_pkts_encrypted)}, 740 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats, 741 out_pkts_protected)}, 742 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats, 743 out_octets_encrypted)}, 744 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats, 745 out_octets_protected)}, 746 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 747 in_pkts_untagged)}, 748 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats, 749 in_pkts_badtag)}, 750 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats, 751 in_pkts_nosci)}, 752 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats, 753 in_pkts_unknownsci)}, 754 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats, 755 in_octets_decrypted)}, 756 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats, 757 in_octets_validated)}, 758 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats, 759 in_pkts_unchecked)}, 760 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats, 761 in_pkts_delayed)}, 762 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats, 763 in_pkts_late)}, 764 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats, 765 in_pkts_ok)}, 766 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats, 767 in_pkts_invalid)}, 768 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats, 769 in_pkts_notvalid)}, 770 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats, 771 in_pkts_unusedsa)}, 772 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats, 773 in_pkts_notusingsa)}, 774 }; 775 776 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \ 777 sizeof(rte_ixgbe_macsec_strings[0])) 778 779 /* Per-queue statistics */ 780 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = { 781 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)}, 782 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)}, 783 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)}, 784 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)}, 785 }; 786 787 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \ 788 sizeof(rte_ixgbe_rxq_strings[0])) 789 #define IXGBE_NB_RXQ_PRIO_VALUES 8 790 791 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = { 792 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)}, 793 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)}, 794 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats, 795 pxon2offc)}, 796 }; 797 798 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \ 799 sizeof(rte_ixgbe_txq_strings[0])) 800 #define IXGBE_NB_TXQ_PRIO_VALUES 8 801 802 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = { 803 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)}, 804 }; 805 806 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \ 807 sizeof(rte_ixgbevf_stats_strings[0])) 808 809 /* 810 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h. 811 */ 812 static inline int 813 ixgbe_is_sfp(struct ixgbe_hw *hw) 814 { 815 switch (hw->phy.type) { 816 case ixgbe_phy_sfp_avago: 817 case ixgbe_phy_sfp_ftl: 818 case ixgbe_phy_sfp_intel: 819 case ixgbe_phy_sfp_unknown: 820 case ixgbe_phy_sfp_passive_tyco: 821 case ixgbe_phy_sfp_passive_unknown: 822 return 1; 823 default: 824 return 0; 825 } 826 } 827 828 static inline int32_t 829 ixgbe_pf_reset_hw(struct ixgbe_hw *hw) 830 { 831 uint32_t ctrl_ext; 832 int32_t status; 833 834 status = ixgbe_reset_hw(hw); 835 836 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 837 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 838 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 839 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 840 IXGBE_WRITE_FLUSH(hw); 841 842 if (status == IXGBE_ERR_SFP_NOT_PRESENT) 843 status = IXGBE_SUCCESS; 844 return status; 845 } 846 847 static inline void 848 ixgbe_enable_intr(struct rte_eth_dev *dev) 849 { 850 struct ixgbe_interrupt *intr = 851 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 852 struct ixgbe_hw *hw = 853 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 854 855 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask); 856 IXGBE_WRITE_FLUSH(hw); 857 } 858 859 /* 860 * This function is based on ixgbe_disable_intr() in base/ixgbe.h. 861 */ 862 static void 863 ixgbe_disable_intr(struct ixgbe_hw *hw) 864 { 865 PMD_INIT_FUNC_TRACE(); 866 867 if (hw->mac.type == ixgbe_mac_82598EB) { 868 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0); 869 } else { 870 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000); 871 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0); 872 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0); 873 } 874 IXGBE_WRITE_FLUSH(hw); 875 } 876 877 /* 878 * This function resets queue statistics mapping registers. 879 * From Niantic datasheet, Initialization of Statistics section: 880 * "...if software requires the queue counters, the RQSMR and TQSM registers 881 * must be re-programmed following a device reset. 882 */ 883 static void 884 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw) 885 { 886 uint32_t i; 887 888 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) { 889 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0); 890 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0); 891 } 892 } 893 894 895 static int 896 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 897 uint16_t queue_id, 898 uint8_t stat_idx, 899 uint8_t is_rx) 900 { 901 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8 902 #define NB_QMAP_FIELDS_PER_QSM_REG 4 903 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f 904 905 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 906 struct ixgbe_stat_mapping_registers *stat_mappings = 907 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private); 908 uint32_t qsmr_mask = 0; 909 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK; 910 uint32_t q_map; 911 uint8_t n, offset; 912 913 if ((hw->mac.type != ixgbe_mac_82599EB) && 914 (hw->mac.type != ixgbe_mac_X540) && 915 (hw->mac.type != ixgbe_mac_X550) && 916 (hw->mac.type != ixgbe_mac_X550EM_x) && 917 (hw->mac.type != ixgbe_mac_X550EM_a)) 918 return -ENOSYS; 919 920 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d", 921 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 922 queue_id, stat_idx); 923 924 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG); 925 if (n >= IXGBE_NB_STAT_MAPPING_REGS) { 926 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded"); 927 return -EIO; 928 } 929 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG); 930 931 /* Now clear any previous stat_idx set */ 932 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 933 if (!is_rx) 934 stat_mappings->tqsm[n] &= ~clearing_mask; 935 else 936 stat_mappings->rqsmr[n] &= ~clearing_mask; 937 938 q_map = (uint32_t)stat_idx; 939 q_map &= QMAP_FIELD_RESERVED_BITS_MASK; 940 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 941 if (!is_rx) 942 stat_mappings->tqsm[n] |= qsmr_mask; 943 else 944 stat_mappings->rqsmr[n] |= qsmr_mask; 945 946 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d", 947 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 948 queue_id, stat_idx); 949 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n, 950 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]); 951 952 /* Now write the mapping in the appropriate register */ 953 if (is_rx) { 954 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d", 955 stat_mappings->rqsmr[n], n); 956 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]); 957 } else { 958 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d", 959 stat_mappings->tqsm[n], n); 960 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]); 961 } 962 return 0; 963 } 964 965 static void 966 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev) 967 { 968 struct ixgbe_stat_mapping_registers *stat_mappings = 969 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private); 970 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 971 int i; 972 973 /* write whatever was in stat mapping table to the NIC */ 974 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) { 975 /* rx */ 976 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]); 977 978 /* tx */ 979 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]); 980 } 981 } 982 983 static void 984 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config) 985 { 986 uint8_t i; 987 struct ixgbe_dcb_tc_config *tc; 988 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS; 989 990 dcb_config->num_tcs.pg_tcs = dcb_max_tc; 991 dcb_config->num_tcs.pfc_tcs = dcb_max_tc; 992 for (i = 0; i < dcb_max_tc; i++) { 993 tc = &dcb_config->tc_config[i]; 994 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i; 995 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 996 (uint8_t)(100/dcb_max_tc + (i & 1)); 997 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i; 998 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 999 (uint8_t)(100/dcb_max_tc + (i & 1)); 1000 tc->pfc = ixgbe_dcb_pfc_disabled; 1001 } 1002 1003 /* Initialize default user to priority mapping, UPx->TC0 */ 1004 tc = &dcb_config->tc_config[0]; 1005 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 1006 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 1007 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) { 1008 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100; 1009 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100; 1010 } 1011 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal; 1012 dcb_config->pfc_mode_enable = false; 1013 dcb_config->vt_mode = true; 1014 dcb_config->round_robin_enable = false; 1015 /* support all DCB capabilities in 82599 */ 1016 dcb_config->support.capabilities = 0xFF; 1017 1018 /*we only support 4 Tcs for X540, X550 */ 1019 if (hw->mac.type == ixgbe_mac_X540 || 1020 hw->mac.type == ixgbe_mac_X550 || 1021 hw->mac.type == ixgbe_mac_X550EM_x || 1022 hw->mac.type == ixgbe_mac_X550EM_a) { 1023 dcb_config->num_tcs.pg_tcs = 4; 1024 dcb_config->num_tcs.pfc_tcs = 4; 1025 } 1026 } 1027 1028 /* 1029 * Ensure that all locks are released before first NVM or PHY access 1030 */ 1031 static void 1032 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw) 1033 { 1034 uint16_t mask; 1035 1036 /* 1037 * Phy lock should not fail in this early stage. If this is the case, 1038 * it is due to an improper exit of the application. 1039 * So force the release of the faulty lock. Release of common lock 1040 * is done automatically by swfw_sync function. 1041 */ 1042 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func; 1043 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1044 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func); 1045 } 1046 ixgbe_release_swfw_semaphore(hw, mask); 1047 1048 /* 1049 * These ones are more tricky since they are common to all ports; but 1050 * swfw_sync retries last long enough (1s) to be almost sure that if 1051 * lock can not be taken it is due to an improper lock of the 1052 * semaphore. 1053 */ 1054 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM; 1055 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1056 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 1057 } 1058 ixgbe_release_swfw_semaphore(hw, mask); 1059 } 1060 1061 /* 1062 * This function is based on code in ixgbe_attach() in base/ixgbe.c. 1063 * It returns 0 on success. 1064 */ 1065 static int 1066 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) 1067 { 1068 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1069 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1070 struct ixgbe_hw *hw = 1071 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1072 struct ixgbe_vfta *shadow_vfta = 1073 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1074 struct ixgbe_hwstrip *hwstrip = 1075 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1076 struct ixgbe_dcb_config *dcb_config = 1077 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private); 1078 struct ixgbe_filter_info *filter_info = 1079 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1080 struct ixgbe_bw_conf *bw_conf = 1081 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private); 1082 uint32_t ctrl_ext; 1083 uint16_t csum; 1084 int diag, i; 1085 1086 PMD_INIT_FUNC_TRACE(); 1087 1088 eth_dev->dev_ops = &ixgbe_eth_dev_ops; 1089 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1090 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1091 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts; 1092 1093 /* 1094 * For secondary processes, we don't initialise any further as primary 1095 * has already done this work. Only check we don't need a different 1096 * RX and TX function. 1097 */ 1098 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1099 struct ixgbe_tx_queue *txq; 1100 /* TX queue function in primary, set by last queue initialized 1101 * Tx queue may not initialized by primary process 1102 */ 1103 if (eth_dev->data->tx_queues) { 1104 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1]; 1105 ixgbe_set_tx_function(eth_dev, txq); 1106 } else { 1107 /* Use default TX function if we get here */ 1108 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. " 1109 "Using default TX function."); 1110 } 1111 1112 ixgbe_set_rx_function(eth_dev); 1113 1114 return 0; 1115 } 1116 1117 rte_eth_copy_pci_info(eth_dev, pci_dev); 1118 1119 /* Vendor and Device ID need to be set before init of shared code */ 1120 hw->device_id = pci_dev->id.device_id; 1121 hw->vendor_id = pci_dev->id.vendor_id; 1122 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1123 hw->allow_unsupported_sfp = 1; 1124 1125 /* Initialize the shared code (base driver) */ 1126 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1127 diag = ixgbe_bypass_init_shared_code(hw); 1128 #else 1129 diag = ixgbe_init_shared_code(hw); 1130 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1131 1132 if (diag != IXGBE_SUCCESS) { 1133 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag); 1134 return -EIO; 1135 } 1136 1137 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 1138 PMD_INIT_LOG(ERR, "\nERROR: " 1139 "Firmware recovery mode detected. Limiting functionality.\n" 1140 "Refer to the Intel(R) Ethernet Adapters and Devices " 1141 "User Guide for details on firmware recovery mode."); 1142 return -EIO; 1143 } 1144 1145 /* pick up the PCI bus settings for reporting later */ 1146 ixgbe_get_bus_info(hw); 1147 1148 /* Unlock any pending hardware semaphore */ 1149 ixgbe_swfw_lock_reset(hw); 1150 1151 #ifdef RTE_LIBRTE_SECURITY 1152 /* Initialize security_ctx only for primary process*/ 1153 if (ixgbe_ipsec_ctx_create(eth_dev)) 1154 return -ENOMEM; 1155 #endif 1156 1157 /* Initialize DCB configuration*/ 1158 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config)); 1159 ixgbe_dcb_init(hw, dcb_config); 1160 /* Get Hardware Flow Control setting */ 1161 hw->fc.requested_mode = ixgbe_fc_full; 1162 hw->fc.current_mode = ixgbe_fc_full; 1163 hw->fc.pause_time = IXGBE_FC_PAUSE; 1164 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 1165 hw->fc.low_water[i] = IXGBE_FC_LO; 1166 hw->fc.high_water[i] = IXGBE_FC_HI; 1167 } 1168 hw->fc.send_xon = 1; 1169 1170 /* Make sure we have a good EEPROM before we read from it */ 1171 diag = ixgbe_validate_eeprom_checksum(hw, &csum); 1172 if (diag != IXGBE_SUCCESS) { 1173 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag); 1174 return -EIO; 1175 } 1176 1177 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1178 diag = ixgbe_bypass_init_hw(hw); 1179 #else 1180 diag = ixgbe_init_hw(hw); 1181 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1182 1183 /* 1184 * Devices with copper phys will fail to initialise if ixgbe_init_hw() 1185 * is called too soon after the kernel driver unbinding/binding occurs. 1186 * The failure occurs in ixgbe_identify_phy_generic() for all devices, 1187 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is 1188 * also called. See ixgbe_identify_phy_82599(). The reason for the 1189 * failure is not known, and only occuts when virtualisation features 1190 * are disabled in the bios. A delay of 100ms was found to be enough by 1191 * trial-and-error, and is doubled to be safe. 1192 */ 1193 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) { 1194 rte_delay_ms(200); 1195 diag = ixgbe_init_hw(hw); 1196 } 1197 1198 if (diag == IXGBE_ERR_SFP_NOT_PRESENT) 1199 diag = IXGBE_SUCCESS; 1200 1201 if (diag == IXGBE_ERR_EEPROM_VERSION) { 1202 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/" 1203 "LOM. Please be aware there may be issues associated " 1204 "with your hardware."); 1205 PMD_INIT_LOG(ERR, "If you are experiencing problems " 1206 "please contact your Intel or hardware representative " 1207 "who provided you with this hardware."); 1208 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED) 1209 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module"); 1210 if (diag) { 1211 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag); 1212 return -EIO; 1213 } 1214 1215 /* Reset the hw statistics */ 1216 ixgbe_dev_stats_reset(eth_dev); 1217 1218 /* disable interrupt */ 1219 ixgbe_disable_intr(hw); 1220 1221 /* reset mappings for queue statistics hw counters*/ 1222 ixgbe_reset_qstat_mappings(hw); 1223 1224 /* Allocate memory for storing MAC addresses */ 1225 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN * 1226 hw->mac.num_rar_entries, 0); 1227 if (eth_dev->data->mac_addrs == NULL) { 1228 PMD_INIT_LOG(ERR, 1229 "Failed to allocate %u bytes needed to store " 1230 "MAC addresses", 1231 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1232 return -ENOMEM; 1233 } 1234 /* Copy the permanent MAC address */ 1235 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr, 1236 ð_dev->data->mac_addrs[0]); 1237 1238 /* Allocate memory for storing hash filter MAC addresses */ 1239 eth_dev->data->hash_mac_addrs = rte_zmalloc( 1240 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0); 1241 if (eth_dev->data->hash_mac_addrs == NULL) { 1242 PMD_INIT_LOG(ERR, 1243 "Failed to allocate %d bytes needed to store MAC addresses", 1244 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC); 1245 return -ENOMEM; 1246 } 1247 1248 /* initialize the vfta */ 1249 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1250 1251 /* initialize the hw strip bitmap*/ 1252 memset(hwstrip, 0, sizeof(*hwstrip)); 1253 1254 /* initialize PF if max_vfs not zero */ 1255 ixgbe_pf_host_init(eth_dev); 1256 1257 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 1258 /* let hardware know driver is loaded */ 1259 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD; 1260 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 1261 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 1262 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 1263 IXGBE_WRITE_FLUSH(hw); 1264 1265 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 1266 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d", 1267 (int) hw->mac.type, (int) hw->phy.type, 1268 (int) hw->phy.sfp_type); 1269 else 1270 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d", 1271 (int) hw->mac.type, (int) hw->phy.type); 1272 1273 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 1274 eth_dev->data->port_id, pci_dev->id.vendor_id, 1275 pci_dev->id.device_id); 1276 1277 rte_intr_callback_register(intr_handle, 1278 ixgbe_dev_interrupt_handler, eth_dev); 1279 1280 /* enable uio/vfio intr/eventfd mapping */ 1281 rte_intr_enable(intr_handle); 1282 1283 /* enable support intr */ 1284 ixgbe_enable_intr(eth_dev); 1285 1286 /* initialize filter info */ 1287 memset(filter_info, 0, 1288 sizeof(struct ixgbe_filter_info)); 1289 1290 /* initialize 5tuple filter list */ 1291 TAILQ_INIT(&filter_info->fivetuple_list); 1292 1293 /* initialize flow director filter list & hash */ 1294 ixgbe_fdir_filter_init(eth_dev); 1295 1296 /* initialize l2 tunnel filter list & hash */ 1297 ixgbe_l2_tn_filter_init(eth_dev); 1298 1299 /* initialize flow filter lists */ 1300 ixgbe_filterlist_init(); 1301 1302 /* initialize bandwidth configuration info */ 1303 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf)); 1304 1305 /* initialize Traffic Manager configuration */ 1306 ixgbe_tm_conf_init(eth_dev); 1307 1308 return 0; 1309 } 1310 1311 static int 1312 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1313 { 1314 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1315 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1316 struct ixgbe_hw *hw; 1317 int retries = 0; 1318 int ret; 1319 1320 PMD_INIT_FUNC_TRACE(); 1321 1322 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1323 return 0; 1324 1325 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1326 1327 if (hw->adapter_stopped == 0) 1328 ixgbe_dev_close(eth_dev); 1329 1330 eth_dev->dev_ops = NULL; 1331 eth_dev->rx_pkt_burst = NULL; 1332 eth_dev->tx_pkt_burst = NULL; 1333 1334 /* Unlock any pending hardware semaphore */ 1335 ixgbe_swfw_lock_reset(hw); 1336 1337 /* disable uio intr before callback unregister */ 1338 rte_intr_disable(intr_handle); 1339 1340 do { 1341 ret = rte_intr_callback_unregister(intr_handle, 1342 ixgbe_dev_interrupt_handler, eth_dev); 1343 if (ret >= 0) { 1344 break; 1345 } else if (ret != -EAGAIN) { 1346 PMD_INIT_LOG(ERR, 1347 "intr callback unregister failed: %d", 1348 ret); 1349 return ret; 1350 } 1351 rte_delay_ms(100); 1352 } while (retries++ < (10 + IXGBE_LINK_UP_TIME)); 1353 1354 /* cancel the delay handler before remove dev */ 1355 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, eth_dev); 1356 1357 /* cancel the link handler before remove dev */ 1358 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, eth_dev); 1359 1360 /* uninitialize PF if max_vfs not zero */ 1361 ixgbe_pf_host_uninit(eth_dev); 1362 1363 /* remove all the fdir filters & hash */ 1364 ixgbe_fdir_filter_uninit(eth_dev); 1365 1366 /* remove all the L2 tunnel filters & hash */ 1367 ixgbe_l2_tn_filter_uninit(eth_dev); 1368 1369 /* Remove all ntuple filters of the device */ 1370 ixgbe_ntuple_filter_uninit(eth_dev); 1371 1372 /* clear all the filters list */ 1373 ixgbe_filterlist_flush(); 1374 1375 /* Remove all Traffic Manager configuration */ 1376 ixgbe_tm_conf_uninit(eth_dev); 1377 1378 #ifdef RTE_LIBRTE_SECURITY 1379 rte_free(eth_dev->security_ctx); 1380 #endif 1381 1382 return 0; 1383 } 1384 1385 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev) 1386 { 1387 struct ixgbe_filter_info *filter_info = 1388 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1389 struct ixgbe_5tuple_filter *p_5tuple; 1390 1391 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) { 1392 TAILQ_REMOVE(&filter_info->fivetuple_list, 1393 p_5tuple, 1394 entries); 1395 rte_free(p_5tuple); 1396 } 1397 memset(filter_info->fivetuple_mask, 0, 1398 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE); 1399 1400 return 0; 1401 } 1402 1403 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev) 1404 { 1405 struct ixgbe_hw_fdir_info *fdir_info = 1406 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1407 struct ixgbe_fdir_filter *fdir_filter; 1408 1409 if (fdir_info->hash_map) 1410 rte_free(fdir_info->hash_map); 1411 if (fdir_info->hash_handle) 1412 rte_hash_free(fdir_info->hash_handle); 1413 1414 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 1415 TAILQ_REMOVE(&fdir_info->fdir_list, 1416 fdir_filter, 1417 entries); 1418 rte_free(fdir_filter); 1419 } 1420 1421 return 0; 1422 } 1423 1424 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev) 1425 { 1426 struct ixgbe_l2_tn_info *l2_tn_info = 1427 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1428 struct ixgbe_l2_tn_filter *l2_tn_filter; 1429 1430 if (l2_tn_info->hash_map) 1431 rte_free(l2_tn_info->hash_map); 1432 if (l2_tn_info->hash_handle) 1433 rte_hash_free(l2_tn_info->hash_handle); 1434 1435 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 1436 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, 1437 l2_tn_filter, 1438 entries); 1439 rte_free(l2_tn_filter); 1440 } 1441 1442 return 0; 1443 } 1444 1445 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev) 1446 { 1447 struct ixgbe_hw_fdir_info *fdir_info = 1448 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1449 char fdir_hash_name[RTE_HASH_NAMESIZE]; 1450 struct rte_hash_parameters fdir_hash_params = { 1451 .name = fdir_hash_name, 1452 .entries = IXGBE_MAX_FDIR_FILTER_NUM, 1453 .key_len = sizeof(union ixgbe_atr_input), 1454 .hash_func = rte_hash_crc, 1455 .hash_func_init_val = 0, 1456 .socket_id = rte_socket_id(), 1457 }; 1458 1459 TAILQ_INIT(&fdir_info->fdir_list); 1460 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 1461 "fdir_%s", eth_dev->device->name); 1462 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params); 1463 if (!fdir_info->hash_handle) { 1464 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 1465 return -EINVAL; 1466 } 1467 fdir_info->hash_map = rte_zmalloc("ixgbe", 1468 sizeof(struct ixgbe_fdir_filter *) * 1469 IXGBE_MAX_FDIR_FILTER_NUM, 1470 0); 1471 if (!fdir_info->hash_map) { 1472 PMD_INIT_LOG(ERR, 1473 "Failed to allocate memory for fdir hash map!"); 1474 return -ENOMEM; 1475 } 1476 fdir_info->mask_added = FALSE; 1477 1478 return 0; 1479 } 1480 1481 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) 1482 { 1483 struct ixgbe_l2_tn_info *l2_tn_info = 1484 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1485 char l2_tn_hash_name[RTE_HASH_NAMESIZE]; 1486 struct rte_hash_parameters l2_tn_hash_params = { 1487 .name = l2_tn_hash_name, 1488 .entries = IXGBE_MAX_L2_TN_FILTER_NUM, 1489 .key_len = sizeof(struct ixgbe_l2_tn_key), 1490 .hash_func = rte_hash_crc, 1491 .hash_func_init_val = 0, 1492 .socket_id = rte_socket_id(), 1493 }; 1494 1495 TAILQ_INIT(&l2_tn_info->l2_tn_list); 1496 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE, 1497 "l2_tn_%s", eth_dev->device->name); 1498 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params); 1499 if (!l2_tn_info->hash_handle) { 1500 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!"); 1501 return -EINVAL; 1502 } 1503 l2_tn_info->hash_map = rte_zmalloc("ixgbe", 1504 sizeof(struct ixgbe_l2_tn_filter *) * 1505 IXGBE_MAX_L2_TN_FILTER_NUM, 1506 0); 1507 if (!l2_tn_info->hash_map) { 1508 PMD_INIT_LOG(ERR, 1509 "Failed to allocate memory for L2 TN hash map!"); 1510 return -ENOMEM; 1511 } 1512 l2_tn_info->e_tag_en = FALSE; 1513 l2_tn_info->e_tag_fwd_en = FALSE; 1514 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG; 1515 1516 return 0; 1517 } 1518 /* 1519 * Negotiate mailbox API version with the PF. 1520 * After reset API version is always set to the basic one (ixgbe_mbox_api_10). 1521 * Then we try to negotiate starting with the most recent one. 1522 * If all negotiation attempts fail, then we will proceed with 1523 * the default one (ixgbe_mbox_api_10). 1524 */ 1525 static void 1526 ixgbevf_negotiate_api(struct ixgbe_hw *hw) 1527 { 1528 int32_t i; 1529 1530 /* start with highest supported, proceed down */ 1531 static const enum ixgbe_pfvf_api_rev sup_ver[] = { 1532 ixgbe_mbox_api_13, 1533 ixgbe_mbox_api_12, 1534 ixgbe_mbox_api_11, 1535 ixgbe_mbox_api_10, 1536 }; 1537 1538 for (i = 0; 1539 i != RTE_DIM(sup_ver) && 1540 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0; 1541 i++) 1542 ; 1543 } 1544 1545 static void 1546 generate_random_mac_addr(struct rte_ether_addr *mac_addr) 1547 { 1548 uint64_t random; 1549 1550 /* Set Organizationally Unique Identifier (OUI) prefix. */ 1551 mac_addr->addr_bytes[0] = 0x00; 1552 mac_addr->addr_bytes[1] = 0x09; 1553 mac_addr->addr_bytes[2] = 0xC0; 1554 /* Force indication of locally assigned MAC address. */ 1555 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR; 1556 /* Generate the last 3 bytes of the MAC address with a random number. */ 1557 random = rte_rand(); 1558 memcpy(&mac_addr->addr_bytes[3], &random, 3); 1559 } 1560 1561 static int 1562 devarg_handle_int(__rte_unused const char *key, const char *value, 1563 void *extra_args) 1564 { 1565 uint16_t *n = extra_args; 1566 1567 if (value == NULL || extra_args == NULL) 1568 return -EINVAL; 1569 1570 *n = (uint16_t)strtoul(value, NULL, 0); 1571 if (*n == USHRT_MAX && errno == ERANGE) 1572 return -1; 1573 1574 return 0; 1575 } 1576 1577 static void 1578 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter, 1579 struct rte_devargs *devargs) 1580 { 1581 struct rte_kvargs *kvlist; 1582 uint16_t pflink_fullchk; 1583 1584 if (devargs == NULL) 1585 return; 1586 1587 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments); 1588 if (kvlist == NULL) 1589 return; 1590 1591 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 && 1592 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK, 1593 devarg_handle_int, &pflink_fullchk) == 0 && 1594 pflink_fullchk == 1) 1595 adapter->pflink_fullchk = 1; 1596 1597 rte_kvargs_free(kvlist); 1598 } 1599 1600 /* 1601 * Virtual Function device init 1602 */ 1603 static int 1604 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev) 1605 { 1606 int diag; 1607 uint32_t tc, tcs; 1608 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1609 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1610 struct ixgbe_hw *hw = 1611 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1612 struct ixgbe_vfta *shadow_vfta = 1613 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1614 struct ixgbe_hwstrip *hwstrip = 1615 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1616 struct rte_ether_addr *perm_addr = 1617 (struct rte_ether_addr *)hw->mac.perm_addr; 1618 1619 PMD_INIT_FUNC_TRACE(); 1620 1621 eth_dev->dev_ops = &ixgbevf_eth_dev_ops; 1622 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1623 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1624 1625 /* for secondary processes, we don't initialise any further as primary 1626 * has already done this work. Only check we don't need a different 1627 * RX function 1628 */ 1629 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1630 struct ixgbe_tx_queue *txq; 1631 /* TX queue function in primary, set by last queue initialized 1632 * Tx queue may not initialized by primary process 1633 */ 1634 if (eth_dev->data->tx_queues) { 1635 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1]; 1636 ixgbe_set_tx_function(eth_dev, txq); 1637 } else { 1638 /* Use default TX function if we get here */ 1639 PMD_INIT_LOG(NOTICE, 1640 "No TX queues configured yet. Using default TX function."); 1641 } 1642 1643 ixgbe_set_rx_function(eth_dev); 1644 1645 return 0; 1646 } 1647 1648 ixgbevf_parse_devargs(eth_dev->data->dev_private, 1649 pci_dev->device.devargs); 1650 1651 rte_eth_copy_pci_info(eth_dev, pci_dev); 1652 1653 hw->device_id = pci_dev->id.device_id; 1654 hw->vendor_id = pci_dev->id.vendor_id; 1655 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1656 1657 /* initialize the vfta */ 1658 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1659 1660 /* initialize the hw strip bitmap*/ 1661 memset(hwstrip, 0, sizeof(*hwstrip)); 1662 1663 /* Initialize the shared code (base driver) */ 1664 diag = ixgbe_init_shared_code(hw); 1665 if (diag != IXGBE_SUCCESS) { 1666 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag); 1667 return -EIO; 1668 } 1669 1670 /* init_mailbox_params */ 1671 hw->mbx.ops.init_params(hw); 1672 1673 /* Reset the hw statistics */ 1674 ixgbevf_dev_stats_reset(eth_dev); 1675 1676 /* Disable the interrupts for VF */ 1677 ixgbevf_intr_disable(eth_dev); 1678 1679 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */ 1680 diag = hw->mac.ops.reset_hw(hw); 1681 1682 /* 1683 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when 1684 * the underlying PF driver has not assigned a MAC address to the VF. 1685 * In this case, assign a random MAC address. 1686 */ 1687 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) { 1688 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1689 /* 1690 * This error code will be propagated to the app by 1691 * rte_eth_dev_reset, so use a public error code rather than 1692 * the internal-only IXGBE_ERR_RESET_FAILED 1693 */ 1694 return -EAGAIN; 1695 } 1696 1697 /* negotiate mailbox API version to use with the PF. */ 1698 ixgbevf_negotiate_api(hw); 1699 1700 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */ 1701 ixgbevf_get_queues(hw, &tcs, &tc); 1702 1703 /* Allocate memory for storing MAC addresses */ 1704 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN * 1705 hw->mac.num_rar_entries, 0); 1706 if (eth_dev->data->mac_addrs == NULL) { 1707 PMD_INIT_LOG(ERR, 1708 "Failed to allocate %u bytes needed to store " 1709 "MAC addresses", 1710 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1711 return -ENOMEM; 1712 } 1713 1714 /* Generate a random MAC address, if none was assigned by PF. */ 1715 if (rte_is_zero_ether_addr(perm_addr)) { 1716 generate_random_mac_addr(perm_addr); 1717 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1); 1718 if (diag) { 1719 rte_free(eth_dev->data->mac_addrs); 1720 eth_dev->data->mac_addrs = NULL; 1721 return diag; 1722 } 1723 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF"); 1724 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address " 1725 "%02x:%02x:%02x:%02x:%02x:%02x", 1726 perm_addr->addr_bytes[0], 1727 perm_addr->addr_bytes[1], 1728 perm_addr->addr_bytes[2], 1729 perm_addr->addr_bytes[3], 1730 perm_addr->addr_bytes[4], 1731 perm_addr->addr_bytes[5]); 1732 } 1733 1734 /* Copy the permanent MAC address */ 1735 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]); 1736 1737 /* reset the hardware with the new settings */ 1738 diag = hw->mac.ops.start_hw(hw); 1739 switch (diag) { 1740 case 0: 1741 break; 1742 1743 default: 1744 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1745 return -EIO; 1746 } 1747 1748 rte_intr_callback_register(intr_handle, 1749 ixgbevf_dev_interrupt_handler, eth_dev); 1750 rte_intr_enable(intr_handle); 1751 ixgbevf_intr_enable(eth_dev); 1752 1753 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s", 1754 eth_dev->data->port_id, pci_dev->id.vendor_id, 1755 pci_dev->id.device_id, "ixgbe_mac_82599_vf"); 1756 1757 return 0; 1758 } 1759 1760 /* Virtual Function device uninit */ 1761 1762 static int 1763 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev) 1764 { 1765 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1766 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1767 struct ixgbe_hw *hw; 1768 1769 PMD_INIT_FUNC_TRACE(); 1770 1771 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1772 return 0; 1773 1774 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1775 1776 if (hw->adapter_stopped == 0) 1777 ixgbevf_dev_close(eth_dev); 1778 1779 eth_dev->dev_ops = NULL; 1780 eth_dev->rx_pkt_burst = NULL; 1781 eth_dev->tx_pkt_burst = NULL; 1782 1783 /* Disable the interrupts for VF */ 1784 ixgbevf_intr_disable(eth_dev); 1785 1786 rte_intr_disable(intr_handle); 1787 rte_intr_callback_unregister(intr_handle, 1788 ixgbevf_dev_interrupt_handler, eth_dev); 1789 1790 return 0; 1791 } 1792 1793 static int 1794 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1795 struct rte_pci_device *pci_dev) 1796 { 1797 char name[RTE_ETH_NAME_MAX_LEN]; 1798 struct rte_eth_dev *pf_ethdev; 1799 struct rte_eth_devargs eth_da; 1800 int i, retval; 1801 1802 if (pci_dev->device.devargs) { 1803 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 1804 ð_da); 1805 if (retval) 1806 return retval; 1807 } else 1808 memset(ð_da, 0, sizeof(eth_da)); 1809 1810 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 1811 sizeof(struct ixgbe_adapter), 1812 eth_dev_pci_specific_init, pci_dev, 1813 eth_ixgbe_dev_init, NULL); 1814 1815 if (retval || eth_da.nb_representor_ports < 1) 1816 return retval; 1817 1818 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1819 if (pf_ethdev == NULL) 1820 return -ENODEV; 1821 1822 /* probe VF representor ports */ 1823 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1824 struct ixgbe_vf_info *vfinfo; 1825 struct ixgbe_vf_representor representor; 1826 1827 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA( 1828 pf_ethdev->data->dev_private); 1829 if (vfinfo == NULL) { 1830 PMD_DRV_LOG(ERR, 1831 "no virtual functions supported by PF"); 1832 break; 1833 } 1834 1835 representor.vf_id = eth_da.representor_ports[i]; 1836 representor.switch_domain_id = vfinfo->switch_domain_id; 1837 representor.pf_ethdev = pf_ethdev; 1838 1839 /* representor port net_bdf_port */ 1840 snprintf(name, sizeof(name), "net_%s_representor_%d", 1841 pci_dev->device.name, 1842 eth_da.representor_ports[i]); 1843 1844 retval = rte_eth_dev_create(&pci_dev->device, name, 1845 sizeof(struct ixgbe_vf_representor), NULL, NULL, 1846 ixgbe_vf_representor_init, &representor); 1847 1848 if (retval) 1849 PMD_DRV_LOG(ERR, "failed to create ixgbe vf " 1850 "representor %s.", name); 1851 } 1852 1853 return 0; 1854 } 1855 1856 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev) 1857 { 1858 struct rte_eth_dev *ethdev; 1859 1860 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1861 if (!ethdev) 1862 return -ENODEV; 1863 1864 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 1865 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit); 1866 else 1867 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit); 1868 } 1869 1870 static struct rte_pci_driver rte_ixgbe_pmd = { 1871 .id_table = pci_id_ixgbe_map, 1872 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1873 .probe = eth_ixgbe_pci_probe, 1874 .remove = eth_ixgbe_pci_remove, 1875 }; 1876 1877 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1878 struct rte_pci_device *pci_dev) 1879 { 1880 return rte_eth_dev_pci_generic_probe(pci_dev, 1881 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init); 1882 } 1883 1884 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev) 1885 { 1886 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit); 1887 } 1888 1889 /* 1890 * virtual function driver struct 1891 */ 1892 static struct rte_pci_driver rte_ixgbevf_pmd = { 1893 .id_table = pci_id_ixgbevf_map, 1894 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1895 .probe = eth_ixgbevf_pci_probe, 1896 .remove = eth_ixgbevf_pci_remove, 1897 }; 1898 1899 static int 1900 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1901 { 1902 struct ixgbe_hw *hw = 1903 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1904 struct ixgbe_vfta *shadow_vfta = 1905 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1906 uint32_t vfta; 1907 uint32_t vid_idx; 1908 uint32_t vid_bit; 1909 1910 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 1911 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 1912 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx)); 1913 if (on) 1914 vfta |= vid_bit; 1915 else 1916 vfta &= ~vid_bit; 1917 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta); 1918 1919 /* update local VFTA copy */ 1920 shadow_vfta->vfta[vid_idx] = vfta; 1921 1922 return 0; 1923 } 1924 1925 static void 1926 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 1927 { 1928 if (on) 1929 ixgbe_vlan_hw_strip_enable(dev, queue); 1930 else 1931 ixgbe_vlan_hw_strip_disable(dev, queue); 1932 } 1933 1934 static int 1935 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1936 enum rte_vlan_type vlan_type, 1937 uint16_t tpid) 1938 { 1939 struct ixgbe_hw *hw = 1940 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1941 int ret = 0; 1942 uint32_t reg; 1943 uint32_t qinq; 1944 1945 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1946 qinq &= IXGBE_DMATXCTL_GDV; 1947 1948 switch (vlan_type) { 1949 case ETH_VLAN_TYPE_INNER: 1950 if (qinq) { 1951 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1952 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1953 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1954 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1955 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1956 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1957 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1958 } else { 1959 ret = -ENOTSUP; 1960 PMD_DRV_LOG(ERR, "Inner type is not supported" 1961 " by single VLAN"); 1962 } 1963 break; 1964 case ETH_VLAN_TYPE_OUTER: 1965 if (qinq) { 1966 /* Only the high 16-bits is valid */ 1967 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid << 1968 IXGBE_EXVET_VET_EXT_SHIFT); 1969 } else { 1970 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1971 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1972 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1973 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1974 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1975 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1976 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1977 } 1978 1979 break; 1980 default: 1981 ret = -EINVAL; 1982 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type); 1983 break; 1984 } 1985 1986 return ret; 1987 } 1988 1989 void 1990 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev) 1991 { 1992 struct ixgbe_hw *hw = 1993 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1994 uint32_t vlnctrl; 1995 1996 PMD_INIT_FUNC_TRACE(); 1997 1998 /* Filter Table Disable */ 1999 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2000 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 2001 2002 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 2003 } 2004 2005 void 2006 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev) 2007 { 2008 struct ixgbe_hw *hw = 2009 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2010 struct ixgbe_vfta *shadow_vfta = 2011 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 2012 uint32_t vlnctrl; 2013 uint16_t i; 2014 2015 PMD_INIT_FUNC_TRACE(); 2016 2017 /* Filter Table Enable */ 2018 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2019 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; 2020 vlnctrl |= IXGBE_VLNCTRL_VFE; 2021 2022 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 2023 2024 /* write whatever is in local vfta copy */ 2025 for (i = 0; i < IXGBE_VFTA_SIZE; i++) 2026 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]); 2027 } 2028 2029 static void 2030 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on) 2031 { 2032 struct ixgbe_hwstrip *hwstrip = 2033 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private); 2034 struct ixgbe_rx_queue *rxq; 2035 2036 if (queue >= IXGBE_MAX_RX_QUEUE_NUM) 2037 return; 2038 2039 if (on) 2040 IXGBE_SET_HWSTRIP(hwstrip, queue); 2041 else 2042 IXGBE_CLEAR_HWSTRIP(hwstrip, queue); 2043 2044 if (queue >= dev->data->nb_rx_queues) 2045 return; 2046 2047 rxq = dev->data->rx_queues[queue]; 2048 2049 if (on) { 2050 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; 2051 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 2052 } else { 2053 rxq->vlan_flags = PKT_RX_VLAN; 2054 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 2055 } 2056 } 2057 2058 static void 2059 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue) 2060 { 2061 struct ixgbe_hw *hw = 2062 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2063 uint32_t ctrl; 2064 2065 PMD_INIT_FUNC_TRACE(); 2066 2067 if (hw->mac.type == ixgbe_mac_82598EB) { 2068 /* No queue level support */ 2069 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2070 return; 2071 } 2072 2073 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2074 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2075 ctrl &= ~IXGBE_RXDCTL_VME; 2076 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2077 2078 /* record those setting for HW strip per queue */ 2079 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0); 2080 } 2081 2082 static void 2083 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue) 2084 { 2085 struct ixgbe_hw *hw = 2086 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2087 uint32_t ctrl; 2088 2089 PMD_INIT_FUNC_TRACE(); 2090 2091 if (hw->mac.type == ixgbe_mac_82598EB) { 2092 /* No queue level supported */ 2093 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2094 return; 2095 } 2096 2097 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2098 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2099 ctrl |= IXGBE_RXDCTL_VME; 2100 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2101 2102 /* record those setting for HW strip per queue */ 2103 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1); 2104 } 2105 2106 static void 2107 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev) 2108 { 2109 struct ixgbe_hw *hw = 2110 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2111 uint32_t ctrl; 2112 2113 PMD_INIT_FUNC_TRACE(); 2114 2115 /* DMATXCTRL: Geric Double VLAN Disable */ 2116 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2117 ctrl &= ~IXGBE_DMATXCTL_GDV; 2118 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2119 2120 /* CTRL_EXT: Global Double VLAN Disable */ 2121 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2122 ctrl &= ~IXGBE_EXTENDED_VLAN; 2123 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2124 2125 } 2126 2127 static void 2128 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) 2129 { 2130 struct ixgbe_hw *hw = 2131 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2132 uint32_t ctrl; 2133 2134 PMD_INIT_FUNC_TRACE(); 2135 2136 /* DMATXCTRL: Geric Double VLAN Enable */ 2137 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2138 ctrl |= IXGBE_DMATXCTL_GDV; 2139 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2140 2141 /* CTRL_EXT: Global Double VLAN Enable */ 2142 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2143 ctrl |= IXGBE_EXTENDED_VLAN; 2144 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2145 2146 /* Clear pooling mode of PFVTCTL. It's required by X550. */ 2147 if (hw->mac.type == ixgbe_mac_X550 || 2148 hw->mac.type == ixgbe_mac_X550EM_x || 2149 hw->mac.type == ixgbe_mac_X550EM_a) { 2150 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 2151 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 2152 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 2153 } 2154 2155 /* 2156 * VET EXT field in the EXVET register = 0x8100 by default 2157 * So no need to change. Same to VT field of DMATXCTL register 2158 */ 2159 } 2160 2161 void 2162 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev) 2163 { 2164 struct ixgbe_hw *hw = 2165 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2166 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 2167 uint32_t ctrl; 2168 uint16_t i; 2169 struct ixgbe_rx_queue *rxq; 2170 bool on; 2171 2172 PMD_INIT_FUNC_TRACE(); 2173 2174 if (hw->mac.type == ixgbe_mac_82598EB) { 2175 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2176 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2177 ctrl |= IXGBE_VLNCTRL_VME; 2178 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2179 } else { 2180 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2181 ctrl &= ~IXGBE_VLNCTRL_VME; 2182 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2183 } 2184 } else { 2185 /* 2186 * Other 10G NIC, the VLAN strip can be setup 2187 * per queue in RXDCTL 2188 */ 2189 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2190 rxq = dev->data->rx_queues[i]; 2191 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx)); 2192 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2193 ctrl |= IXGBE_RXDCTL_VME; 2194 on = TRUE; 2195 } else { 2196 ctrl &= ~IXGBE_RXDCTL_VME; 2197 on = FALSE; 2198 } 2199 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl); 2200 2201 /* record those setting for HW strip per queue */ 2202 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on); 2203 } 2204 } 2205 } 2206 2207 static void 2208 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask) 2209 { 2210 uint16_t i; 2211 struct rte_eth_rxmode *rxmode; 2212 struct ixgbe_rx_queue *rxq; 2213 2214 if (mask & ETH_VLAN_STRIP_MASK) { 2215 rxmode = &dev->data->dev_conf.rxmode; 2216 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 2217 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2218 rxq = dev->data->rx_queues[i]; 2219 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 2220 } 2221 else 2222 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2223 rxq = dev->data->rx_queues[i]; 2224 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 2225 } 2226 } 2227 } 2228 2229 static int 2230 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask) 2231 { 2232 struct rte_eth_rxmode *rxmode; 2233 rxmode = &dev->data->dev_conf.rxmode; 2234 2235 if (mask & ETH_VLAN_STRIP_MASK) { 2236 ixgbe_vlan_hw_strip_config(dev); 2237 } 2238 2239 if (mask & ETH_VLAN_FILTER_MASK) { 2240 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 2241 ixgbe_vlan_hw_filter_enable(dev); 2242 else 2243 ixgbe_vlan_hw_filter_disable(dev); 2244 } 2245 2246 if (mask & ETH_VLAN_EXTEND_MASK) { 2247 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2248 ixgbe_vlan_hw_extend_enable(dev); 2249 else 2250 ixgbe_vlan_hw_extend_disable(dev); 2251 } 2252 2253 return 0; 2254 } 2255 2256 static int 2257 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2258 { 2259 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 2260 2261 ixgbe_vlan_offload_config(dev, mask); 2262 2263 return 0; 2264 } 2265 2266 static void 2267 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev) 2268 { 2269 struct ixgbe_hw *hw = 2270 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2271 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */ 2272 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2273 2274 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */ 2275 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl); 2276 } 2277 2278 static int 2279 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q) 2280 { 2281 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2282 2283 switch (nb_rx_q) { 2284 case 1: 2285 case 2: 2286 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS; 2287 break; 2288 case 4: 2289 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS; 2290 break; 2291 default: 2292 return -EINVAL; 2293 } 2294 2295 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 2296 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2297 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 2298 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2299 return 0; 2300 } 2301 2302 static int 2303 ixgbe_check_mq_mode(struct rte_eth_dev *dev) 2304 { 2305 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 2306 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2307 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2308 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2309 2310 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 2311 /* check multi-queue mode */ 2312 switch (dev_conf->rxmode.mq_mode) { 2313 case ETH_MQ_RX_VMDQ_DCB: 2314 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV"); 2315 break; 2316 case ETH_MQ_RX_VMDQ_DCB_RSS: 2317 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */ 2318 PMD_INIT_LOG(ERR, "SRIOV active," 2319 " unsupported mq_mode rx %d.", 2320 dev_conf->rxmode.mq_mode); 2321 return -EINVAL; 2322 case ETH_MQ_RX_RSS: 2323 case ETH_MQ_RX_VMDQ_RSS: 2324 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS; 2325 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) 2326 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) { 2327 PMD_INIT_LOG(ERR, "SRIOV is active," 2328 " invalid queue number" 2329 " for VMDQ RSS, allowed" 2330 " value are 1, 2 or 4."); 2331 return -EINVAL; 2332 } 2333 break; 2334 case ETH_MQ_RX_VMDQ_ONLY: 2335 case ETH_MQ_RX_NONE: 2336 /* if nothing mq mode configure, use default scheme */ 2337 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY; 2338 break; 2339 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/ 2340 /* SRIOV only works in VMDq enable mode */ 2341 PMD_INIT_LOG(ERR, "SRIOV is active," 2342 " wrong mq_mode rx %d.", 2343 dev_conf->rxmode.mq_mode); 2344 return -EINVAL; 2345 } 2346 2347 switch (dev_conf->txmode.mq_mode) { 2348 case ETH_MQ_TX_VMDQ_DCB: 2349 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV"); 2350 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB; 2351 break; 2352 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */ 2353 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY; 2354 break; 2355 } 2356 2357 /* check valid queue number */ 2358 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) || 2359 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) { 2360 PMD_INIT_LOG(ERR, "SRIOV is active," 2361 " nb_rx_q=%d nb_tx_q=%d queue number" 2362 " must be less than or equal to %d.", 2363 nb_rx_q, nb_tx_q, 2364 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool); 2365 return -EINVAL; 2366 } 2367 } else { 2368 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) { 2369 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is" 2370 " not supported."); 2371 return -EINVAL; 2372 } 2373 /* check configuration for vmdb+dcb mode */ 2374 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) { 2375 const struct rte_eth_vmdq_dcb_conf *conf; 2376 2377 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2378 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.", 2379 IXGBE_VMDQ_DCB_NB_QUEUES); 2380 return -EINVAL; 2381 } 2382 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf; 2383 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2384 conf->nb_queue_pools == ETH_32_POOLS)) { 2385 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2386 " nb_queue_pools must be %d or %d.", 2387 ETH_16_POOLS, ETH_32_POOLS); 2388 return -EINVAL; 2389 } 2390 } 2391 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) { 2392 const struct rte_eth_vmdq_dcb_tx_conf *conf; 2393 2394 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2395 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d", 2396 IXGBE_VMDQ_DCB_NB_QUEUES); 2397 return -EINVAL; 2398 } 2399 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf; 2400 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2401 conf->nb_queue_pools == ETH_32_POOLS)) { 2402 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2403 " nb_queue_pools != %d and" 2404 " nb_queue_pools != %d.", 2405 ETH_16_POOLS, ETH_32_POOLS); 2406 return -EINVAL; 2407 } 2408 } 2409 2410 /* For DCB mode check our configuration before we go further */ 2411 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) { 2412 const struct rte_eth_dcb_rx_conf *conf; 2413 2414 conf = &dev_conf->rx_adv_conf.dcb_rx_conf; 2415 if (!(conf->nb_tcs == ETH_4_TCS || 2416 conf->nb_tcs == ETH_8_TCS)) { 2417 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2418 " and nb_tcs != %d.", 2419 ETH_4_TCS, ETH_8_TCS); 2420 return -EINVAL; 2421 } 2422 } 2423 2424 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) { 2425 const struct rte_eth_dcb_tx_conf *conf; 2426 2427 conf = &dev_conf->tx_adv_conf.dcb_tx_conf; 2428 if (!(conf->nb_tcs == ETH_4_TCS || 2429 conf->nb_tcs == ETH_8_TCS)) { 2430 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2431 " and nb_tcs != %d.", 2432 ETH_4_TCS, ETH_8_TCS); 2433 return -EINVAL; 2434 } 2435 } 2436 2437 /* 2438 * When DCB/VT is off, maximum number of queues changes, 2439 * except for 82598EB, which remains constant. 2440 */ 2441 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 2442 hw->mac.type != ixgbe_mac_82598EB) { 2443 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) { 2444 PMD_INIT_LOG(ERR, 2445 "Neither VT nor DCB are enabled, " 2446 "nb_tx_q > %d.", 2447 IXGBE_NONE_MODE_TX_NB_QUEUES); 2448 return -EINVAL; 2449 } 2450 } 2451 } 2452 return 0; 2453 } 2454 2455 static int 2456 ixgbe_dev_configure(struct rte_eth_dev *dev) 2457 { 2458 struct ixgbe_interrupt *intr = 2459 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2460 struct ixgbe_adapter *adapter = dev->data->dev_private; 2461 int ret; 2462 2463 PMD_INIT_FUNC_TRACE(); 2464 /* multipe queue mode checking */ 2465 ret = ixgbe_check_mq_mode(dev); 2466 if (ret != 0) { 2467 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.", 2468 ret); 2469 return ret; 2470 } 2471 2472 /* set flag to update link status after init */ 2473 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2474 2475 /* 2476 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 2477 * allocation or vector Rx preconditions we will reset it. 2478 */ 2479 adapter->rx_bulk_alloc_allowed = true; 2480 adapter->rx_vec_allowed = true; 2481 2482 return 0; 2483 } 2484 2485 static void 2486 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) 2487 { 2488 struct ixgbe_hw *hw = 2489 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2490 struct ixgbe_interrupt *intr = 2491 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2492 uint32_t gpie; 2493 2494 /* only set up it on X550EM_X */ 2495 if (hw->mac.type == ixgbe_mac_X550EM_x) { 2496 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 2497 gpie |= IXGBE_SDP0_GPIEN_X550EM_x; 2498 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 2499 if (hw->phy.type == ixgbe_phy_x550em_ext_t) 2500 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x; 2501 } 2502 } 2503 2504 int 2505 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 2506 uint16_t tx_rate, uint64_t q_msk) 2507 { 2508 struct ixgbe_hw *hw; 2509 struct ixgbe_vf_info *vfinfo; 2510 struct rte_eth_link link; 2511 uint8_t nb_q_per_pool; 2512 uint32_t queue_stride; 2513 uint32_t queue_idx, idx = 0, vf_idx; 2514 uint32_t queue_end; 2515 uint16_t total_rate = 0; 2516 struct rte_pci_device *pci_dev; 2517 2518 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2519 rte_eth_link_get_nowait(dev->data->port_id, &link); 2520 2521 if (vf >= pci_dev->max_vfs) 2522 return -EINVAL; 2523 2524 if (tx_rate > link.link_speed) 2525 return -EINVAL; 2526 2527 if (q_msk == 0) 2528 return 0; 2529 2530 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2531 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 2532 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2533 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2534 queue_idx = vf * queue_stride; 2535 queue_end = queue_idx + nb_q_per_pool - 1; 2536 if (queue_end >= hw->mac.max_tx_queues) 2537 return -EINVAL; 2538 2539 if (vfinfo) { 2540 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) { 2541 if (vf_idx == vf) 2542 continue; 2543 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate); 2544 idx++) 2545 total_rate += vfinfo[vf_idx].tx_rate[idx]; 2546 } 2547 } else { 2548 return -EINVAL; 2549 } 2550 2551 /* Store tx_rate for this vf. */ 2552 for (idx = 0; idx < nb_q_per_pool; idx++) { 2553 if (((uint64_t)0x1 << idx) & q_msk) { 2554 if (vfinfo[vf].tx_rate[idx] != tx_rate) 2555 vfinfo[vf].tx_rate[idx] = tx_rate; 2556 total_rate += tx_rate; 2557 } 2558 } 2559 2560 if (total_rate > dev->data->dev_link.link_speed) { 2561 /* Reset stored TX rate of the VF if it causes exceed 2562 * link speed. 2563 */ 2564 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate)); 2565 return -EINVAL; 2566 } 2567 2568 /* Set RTTBCNRC of each queue/pool for vf X */ 2569 for (; queue_idx <= queue_end; queue_idx++) { 2570 if (0x1 & q_msk) 2571 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate); 2572 q_msk = q_msk >> 1; 2573 } 2574 2575 return 0; 2576 } 2577 2578 /* 2579 * Configure device link speed and setup link. 2580 * It returns 0 on success. 2581 */ 2582 static int 2583 ixgbe_dev_start(struct rte_eth_dev *dev) 2584 { 2585 struct ixgbe_hw *hw = 2586 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2587 struct ixgbe_vf_info *vfinfo = 2588 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2589 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2590 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2591 uint32_t intr_vector = 0; 2592 int err, link_up = 0, negotiate = 0; 2593 uint32_t speed = 0; 2594 uint32_t allowed_speeds = 0; 2595 int mask = 0; 2596 int status; 2597 uint16_t vf, idx; 2598 uint32_t *link_speeds; 2599 struct ixgbe_tm_conf *tm_conf = 2600 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2601 2602 PMD_INIT_FUNC_TRACE(); 2603 2604 /* IXGBE devices don't support: 2605 * - half duplex (checked afterwards for valid speeds) 2606 * - fixed speed: TODO implement 2607 */ 2608 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) { 2609 PMD_INIT_LOG(ERR, 2610 "Invalid link_speeds for port %u, fix speed not supported", 2611 dev->data->port_id); 2612 return -EINVAL; 2613 } 2614 2615 /* Stop the link setup handler before resetting the HW. */ 2616 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 2617 2618 /* disable uio/vfio intr/eventfd mapping */ 2619 rte_intr_disable(intr_handle); 2620 2621 /* stop adapter */ 2622 hw->adapter_stopped = 0; 2623 ixgbe_stop_adapter(hw); 2624 2625 /* reinitialize adapter 2626 * this calls reset and start 2627 */ 2628 status = ixgbe_pf_reset_hw(hw); 2629 if (status != 0) 2630 return -1; 2631 hw->mac.ops.start_hw(hw); 2632 hw->mac.get_link_status = true; 2633 2634 /* configure PF module if SRIOV enabled */ 2635 ixgbe_pf_host_configure(dev); 2636 2637 ixgbe_dev_phy_intr_setup(dev); 2638 2639 /* check and configure queue intr-vector mapping */ 2640 if ((rte_intr_cap_multiple(intr_handle) || 2641 !RTE_ETH_DEV_SRIOV(dev).active) && 2642 dev->data->dev_conf.intr_conf.rxq != 0) { 2643 intr_vector = dev->data->nb_rx_queues; 2644 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) { 2645 PMD_INIT_LOG(ERR, "At most %d intr queues supported", 2646 IXGBE_MAX_INTR_QUEUE_NUM); 2647 return -ENOTSUP; 2648 } 2649 if (rte_intr_efd_enable(intr_handle, intr_vector)) 2650 return -1; 2651 } 2652 2653 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 2654 intr_handle->intr_vec = 2655 rte_zmalloc("intr_vec", 2656 dev->data->nb_rx_queues * sizeof(int), 0); 2657 if (intr_handle->intr_vec == NULL) { 2658 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 2659 " intr_vec", dev->data->nb_rx_queues); 2660 return -ENOMEM; 2661 } 2662 } 2663 2664 /* confiugre msix for sleep until rx interrupt */ 2665 ixgbe_configure_msix(dev); 2666 2667 /* initialize transmission unit */ 2668 ixgbe_dev_tx_init(dev); 2669 2670 /* This can fail when allocating mbufs for descriptor rings */ 2671 err = ixgbe_dev_rx_init(dev); 2672 if (err) { 2673 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 2674 goto error; 2675 } 2676 2677 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 2678 ETH_VLAN_EXTEND_MASK; 2679 err = ixgbe_vlan_offload_config(dev, mask); 2680 if (err) { 2681 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 2682 goto error; 2683 } 2684 2685 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) { 2686 /* Enable vlan filtering for VMDq */ 2687 ixgbe_vmdq_vlan_hw_filter_enable(dev); 2688 } 2689 2690 /* Configure DCB hw */ 2691 ixgbe_configure_dcb(dev); 2692 2693 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) { 2694 err = ixgbe_fdir_configure(dev); 2695 if (err) 2696 goto error; 2697 } 2698 2699 /* Restore vf rate limit */ 2700 if (vfinfo != NULL) { 2701 for (vf = 0; vf < pci_dev->max_vfs; vf++) 2702 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++) 2703 if (vfinfo[vf].tx_rate[idx] != 0) 2704 ixgbe_set_vf_rate_limit( 2705 dev, vf, 2706 vfinfo[vf].tx_rate[idx], 2707 1 << idx); 2708 } 2709 2710 ixgbe_restore_statistics_mapping(dev); 2711 2712 err = ixgbe_dev_rxtx_start(dev); 2713 if (err < 0) { 2714 PMD_INIT_LOG(ERR, "Unable to start rxtx queues"); 2715 goto error; 2716 } 2717 2718 /* Skip link setup if loopback mode is enabled. */ 2719 if (dev->data->dev_conf.lpbk_mode != 0) { 2720 err = ixgbe_check_supported_loopback_mode(dev); 2721 if (err < 0) { 2722 PMD_INIT_LOG(ERR, "Unsupported loopback mode"); 2723 goto error; 2724 } else { 2725 goto skip_link_setup; 2726 } 2727 } 2728 2729 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) { 2730 err = hw->mac.ops.setup_sfp(hw); 2731 if (err) 2732 goto error; 2733 } 2734 2735 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2736 /* Turn on the copper */ 2737 ixgbe_set_phy_power(hw, true); 2738 } else { 2739 /* Turn on the laser */ 2740 ixgbe_enable_tx_laser(hw); 2741 } 2742 2743 err = ixgbe_check_link(hw, &speed, &link_up, 0); 2744 if (err) 2745 goto error; 2746 dev->data->dev_link.link_status = link_up; 2747 2748 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate); 2749 if (err) 2750 goto error; 2751 2752 switch (hw->mac.type) { 2753 case ixgbe_mac_X550: 2754 case ixgbe_mac_X550EM_x: 2755 case ixgbe_mac_X550EM_a: 2756 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2757 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G | 2758 ETH_LINK_SPEED_10G; 2759 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 2760 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 2761 allowed_speeds = ETH_LINK_SPEED_10M | 2762 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G; 2763 break; 2764 default: 2765 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2766 ETH_LINK_SPEED_10G; 2767 } 2768 2769 link_speeds = &dev->data->dev_conf.link_speeds; 2770 if (*link_speeds & ~allowed_speeds) { 2771 PMD_INIT_LOG(ERR, "Invalid link setting"); 2772 goto error; 2773 } 2774 2775 speed = 0x0; 2776 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) { 2777 switch (hw->mac.type) { 2778 case ixgbe_mac_82598EB: 2779 speed = IXGBE_LINK_SPEED_82598_AUTONEG; 2780 break; 2781 case ixgbe_mac_82599EB: 2782 case ixgbe_mac_X540: 2783 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2784 break; 2785 case ixgbe_mac_X550: 2786 case ixgbe_mac_X550EM_x: 2787 case ixgbe_mac_X550EM_a: 2788 speed = IXGBE_LINK_SPEED_X550_AUTONEG; 2789 break; 2790 default: 2791 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2792 } 2793 } else { 2794 if (*link_speeds & ETH_LINK_SPEED_10G) 2795 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2796 if (*link_speeds & ETH_LINK_SPEED_5G) 2797 speed |= IXGBE_LINK_SPEED_5GB_FULL; 2798 if (*link_speeds & ETH_LINK_SPEED_2_5G) 2799 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 2800 if (*link_speeds & ETH_LINK_SPEED_1G) 2801 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2802 if (*link_speeds & ETH_LINK_SPEED_100M) 2803 speed |= IXGBE_LINK_SPEED_100_FULL; 2804 if (*link_speeds & ETH_LINK_SPEED_10M) 2805 speed |= IXGBE_LINK_SPEED_10_FULL; 2806 } 2807 2808 err = ixgbe_setup_link(hw, speed, link_up); 2809 if (err) 2810 goto error; 2811 2812 skip_link_setup: 2813 2814 if (rte_intr_allow_others(intr_handle)) { 2815 /* check if lsc interrupt is enabled */ 2816 if (dev->data->dev_conf.intr_conf.lsc != 0) 2817 ixgbe_dev_lsc_interrupt_setup(dev, TRUE); 2818 else 2819 ixgbe_dev_lsc_interrupt_setup(dev, FALSE); 2820 ixgbe_dev_macsec_interrupt_setup(dev); 2821 } else { 2822 rte_intr_callback_unregister(intr_handle, 2823 ixgbe_dev_interrupt_handler, dev); 2824 if (dev->data->dev_conf.intr_conf.lsc != 0) 2825 PMD_INIT_LOG(INFO, "lsc won't enable because of" 2826 " no intr multiplex"); 2827 } 2828 2829 /* check if rxq interrupt is enabled */ 2830 if (dev->data->dev_conf.intr_conf.rxq != 0 && 2831 rte_intr_dp_is_en(intr_handle)) 2832 ixgbe_dev_rxq_interrupt_setup(dev); 2833 2834 /* enable uio/vfio intr/eventfd mapping */ 2835 rte_intr_enable(intr_handle); 2836 2837 /* resume enabled intr since hw reset */ 2838 ixgbe_enable_intr(dev); 2839 ixgbe_l2_tunnel_conf(dev); 2840 ixgbe_filter_restore(dev); 2841 2842 if (tm_conf->root && !tm_conf->committed) 2843 PMD_DRV_LOG(WARNING, 2844 "please call hierarchy_commit() " 2845 "before starting the port"); 2846 2847 /* 2848 * Update link status right before return, because it may 2849 * start link configuration process in a separate thread. 2850 */ 2851 ixgbe_dev_link_update(dev, 0); 2852 2853 return 0; 2854 2855 error: 2856 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err); 2857 ixgbe_dev_clear_queues(dev); 2858 return -EIO; 2859 } 2860 2861 /* 2862 * Stop device: disable rx and tx functions to allow for reconfiguring. 2863 */ 2864 static void 2865 ixgbe_dev_stop(struct rte_eth_dev *dev) 2866 { 2867 struct rte_eth_link link; 2868 struct ixgbe_adapter *adapter = dev->data->dev_private; 2869 struct ixgbe_hw *hw = 2870 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2871 struct ixgbe_vf_info *vfinfo = 2872 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2873 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2874 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2875 int vf; 2876 struct ixgbe_tm_conf *tm_conf = 2877 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2878 2879 PMD_INIT_FUNC_TRACE(); 2880 2881 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 2882 2883 /* disable interrupts */ 2884 ixgbe_disable_intr(hw); 2885 2886 /* reset the NIC */ 2887 ixgbe_pf_reset_hw(hw); 2888 hw->adapter_stopped = 0; 2889 2890 /* stop adapter */ 2891 ixgbe_stop_adapter(hw); 2892 2893 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++) 2894 vfinfo[vf].clear_to_send = false; 2895 2896 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2897 /* Turn off the copper */ 2898 ixgbe_set_phy_power(hw, false); 2899 } else { 2900 /* Turn off the laser */ 2901 ixgbe_disable_tx_laser(hw); 2902 } 2903 2904 ixgbe_dev_clear_queues(dev); 2905 2906 /* Clear stored conf */ 2907 dev->data->scattered_rx = 0; 2908 dev->data->lro = 0; 2909 2910 /* Clear recorded link status */ 2911 memset(&link, 0, sizeof(link)); 2912 rte_eth_linkstatus_set(dev, &link); 2913 2914 if (!rte_intr_allow_others(intr_handle)) 2915 /* resume to the default handler */ 2916 rte_intr_callback_register(intr_handle, 2917 ixgbe_dev_interrupt_handler, 2918 (void *)dev); 2919 2920 /* Clean datapath event and queue/vec mapping */ 2921 rte_intr_efd_disable(intr_handle); 2922 if (intr_handle->intr_vec != NULL) { 2923 rte_free(intr_handle->intr_vec); 2924 intr_handle->intr_vec = NULL; 2925 } 2926 2927 /* reset hierarchy commit */ 2928 tm_conf->committed = false; 2929 2930 adapter->rss_reta_updated = 0; 2931 } 2932 2933 /* 2934 * Set device link up: enable tx. 2935 */ 2936 static int 2937 ixgbe_dev_set_link_up(struct rte_eth_dev *dev) 2938 { 2939 struct ixgbe_hw *hw = 2940 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2941 if (hw->mac.type == ixgbe_mac_82599EB) { 2942 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2943 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2944 /* Not suported in bypass mode */ 2945 PMD_INIT_LOG(ERR, "Set link up is not supported " 2946 "by device id 0x%x", hw->device_id); 2947 return -ENOTSUP; 2948 } 2949 #endif 2950 } 2951 2952 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2953 /* Turn on the copper */ 2954 ixgbe_set_phy_power(hw, true); 2955 } else { 2956 /* Turn on the laser */ 2957 ixgbe_enable_tx_laser(hw); 2958 } 2959 2960 return 0; 2961 } 2962 2963 /* 2964 * Set device link down: disable tx. 2965 */ 2966 static int 2967 ixgbe_dev_set_link_down(struct rte_eth_dev *dev) 2968 { 2969 struct ixgbe_hw *hw = 2970 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2971 if (hw->mac.type == ixgbe_mac_82599EB) { 2972 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2973 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2974 /* Not suported in bypass mode */ 2975 PMD_INIT_LOG(ERR, "Set link down is not supported " 2976 "by device id 0x%x", hw->device_id); 2977 return -ENOTSUP; 2978 } 2979 #endif 2980 } 2981 2982 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2983 /* Turn off the copper */ 2984 ixgbe_set_phy_power(hw, false); 2985 } else { 2986 /* Turn off the laser */ 2987 ixgbe_disable_tx_laser(hw); 2988 } 2989 2990 return 0; 2991 } 2992 2993 /* 2994 * Reset and stop device. 2995 */ 2996 static void 2997 ixgbe_dev_close(struct rte_eth_dev *dev) 2998 { 2999 struct ixgbe_hw *hw = 3000 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3001 3002 PMD_INIT_FUNC_TRACE(); 3003 3004 ixgbe_pf_reset_hw(hw); 3005 3006 ixgbe_dev_stop(dev); 3007 hw->adapter_stopped = 1; 3008 3009 ixgbe_dev_free_queues(dev); 3010 3011 ixgbe_disable_pcie_master(hw); 3012 3013 /* reprogram the RAR[0] in case user changed it. */ 3014 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 3015 } 3016 3017 /* 3018 * Reset PF device. 3019 */ 3020 static int 3021 ixgbe_dev_reset(struct rte_eth_dev *dev) 3022 { 3023 int ret; 3024 3025 /* When a DPDK PMD PF begin to reset PF port, it should notify all 3026 * its VF to make them align with it. The detailed notification 3027 * mechanism is PMD specific. As to ixgbe PF, it is rather complex. 3028 * To avoid unexpected behavior in VF, currently reset of PF with 3029 * SR-IOV activation is not supported. It might be supported later. 3030 */ 3031 if (dev->data->sriov.active) 3032 return -ENOTSUP; 3033 3034 ret = eth_ixgbe_dev_uninit(dev); 3035 if (ret) 3036 return ret; 3037 3038 ret = eth_ixgbe_dev_init(dev, NULL); 3039 3040 return ret; 3041 } 3042 3043 static void 3044 ixgbe_read_stats_registers(struct ixgbe_hw *hw, 3045 struct ixgbe_hw_stats *hw_stats, 3046 struct ixgbe_macsec_stats *macsec_stats, 3047 uint64_t *total_missed_rx, uint64_t *total_qbrc, 3048 uint64_t *total_qprc, uint64_t *total_qprdc) 3049 { 3050 uint32_t bprc, lxon, lxoff, total; 3051 uint32_t delta_gprc = 0; 3052 unsigned i; 3053 /* Workaround for RX byte count not including CRC bytes when CRC 3054 * strip is enabled. CRC bytes are removed from counters when crc_strip 3055 * is disabled. 3056 */ 3057 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) & 3058 IXGBE_HLREG0_RXCRCSTRP); 3059 3060 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 3061 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC); 3062 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC); 3063 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC); 3064 3065 for (i = 0; i < 8; i++) { 3066 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 3067 3068 /* global total per queue */ 3069 hw_stats->mpc[i] += mp; 3070 /* Running comprehensive total for stats display */ 3071 *total_missed_rx += hw_stats->mpc[i]; 3072 if (hw->mac.type == ixgbe_mac_82598EB) { 3073 hw_stats->rnbc[i] += 3074 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 3075 hw_stats->pxonrxc[i] += 3076 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 3077 hw_stats->pxoffrxc[i] += 3078 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 3079 } else { 3080 hw_stats->pxonrxc[i] += 3081 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 3082 hw_stats->pxoffrxc[i] += 3083 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 3084 hw_stats->pxon2offc[i] += 3085 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 3086 } 3087 hw_stats->pxontxc[i] += 3088 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 3089 hw_stats->pxofftxc[i] += 3090 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 3091 } 3092 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3093 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 3094 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 3095 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 3096 3097 delta_gprc += delta_qprc; 3098 3099 hw_stats->qprc[i] += delta_qprc; 3100 hw_stats->qptc[i] += delta_qptc; 3101 3102 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 3103 hw_stats->qbrc[i] += 3104 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32); 3105 if (crc_strip == 0) 3106 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN; 3107 3108 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 3109 hw_stats->qbtc[i] += 3110 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32); 3111 3112 hw_stats->qprdc[i] += delta_qprdc; 3113 *total_qprdc += hw_stats->qprdc[i]; 3114 3115 *total_qprc += hw_stats->qprc[i]; 3116 *total_qbrc += hw_stats->qbrc[i]; 3117 } 3118 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC); 3119 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC); 3120 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 3121 3122 /* 3123 * An errata states that gprc actually counts good + missed packets: 3124 * Workaround to set gprc to summated queue packet receives 3125 */ 3126 hw_stats->gprc = *total_qprc; 3127 3128 if (hw->mac.type != ixgbe_mac_82598EB) { 3129 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 3130 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32); 3131 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 3132 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32); 3133 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 3134 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32); 3135 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 3136 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 3137 } else { 3138 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 3139 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 3140 /* 82598 only has a counter in the high register */ 3141 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 3142 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 3143 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 3144 } 3145 uint64_t old_tpr = hw_stats->tpr; 3146 3147 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 3148 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT); 3149 3150 if (crc_strip == 0) 3151 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN; 3152 3153 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC); 3154 hw_stats->gptc += delta_gptc; 3155 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN; 3156 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN; 3157 3158 /* 3159 * Workaround: mprc hardware is incorrectly counting 3160 * broadcasts, so for now we subtract those. 3161 */ 3162 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 3163 hw_stats->bprc += bprc; 3164 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 3165 if (hw->mac.type == ixgbe_mac_82598EB) 3166 hw_stats->mprc -= bprc; 3167 3168 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 3169 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 3170 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 3171 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 3172 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 3173 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 3174 3175 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 3176 hw_stats->lxontxc += lxon; 3177 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 3178 hw_stats->lxofftxc += lxoff; 3179 total = lxon + lxoff; 3180 3181 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 3182 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 3183 hw_stats->gptc -= total; 3184 hw_stats->mptc -= total; 3185 hw_stats->ptc64 -= total; 3186 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN; 3187 3188 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 3189 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 3190 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 3191 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 3192 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC); 3193 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC); 3194 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC); 3195 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 3196 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 3197 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 3198 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 3199 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 3200 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 3201 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC); 3202 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 3203 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST); 3204 /* Only read FCOE on 82599 */ 3205 if (hw->mac.type != ixgbe_mac_82598EB) { 3206 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 3207 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 3208 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 3209 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 3210 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 3211 } 3212 3213 /* Flow Director Stats registers */ 3214 if (hw->mac.type != ixgbe_mac_82598EB) { 3215 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 3216 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 3217 hw_stats->fdirustat_add += IXGBE_READ_REG(hw, 3218 IXGBE_FDIRUSTAT) & 0xFFFF; 3219 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw, 3220 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF; 3221 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw, 3222 IXGBE_FDIRFSTAT) & 0xFFFF; 3223 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw, 3224 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF; 3225 } 3226 /* MACsec Stats registers */ 3227 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT); 3228 macsec_stats->out_pkts_encrypted += 3229 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE); 3230 macsec_stats->out_pkts_protected += 3231 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP); 3232 macsec_stats->out_octets_encrypted += 3233 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE); 3234 macsec_stats->out_octets_protected += 3235 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP); 3236 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT); 3237 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD); 3238 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI); 3239 macsec_stats->in_pkts_unknownsci += 3240 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI); 3241 macsec_stats->in_octets_decrypted += 3242 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD); 3243 macsec_stats->in_octets_validated += 3244 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV); 3245 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH); 3246 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY); 3247 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE); 3248 for (i = 0; i < 2; i++) { 3249 macsec_stats->in_pkts_ok += 3250 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i)); 3251 macsec_stats->in_pkts_invalid += 3252 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i)); 3253 macsec_stats->in_pkts_notvalid += 3254 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i)); 3255 } 3256 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA); 3257 macsec_stats->in_pkts_notusingsa += 3258 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA); 3259 } 3260 3261 /* 3262 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c 3263 */ 3264 static int 3265 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3266 { 3267 struct ixgbe_hw *hw = 3268 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3269 struct ixgbe_hw_stats *hw_stats = 3270 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3271 struct ixgbe_macsec_stats *macsec_stats = 3272 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3273 dev->data->dev_private); 3274 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3275 unsigned i; 3276 3277 total_missed_rx = 0; 3278 total_qbrc = 0; 3279 total_qprc = 0; 3280 total_qprdc = 0; 3281 3282 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3283 &total_qbrc, &total_qprc, &total_qprdc); 3284 3285 if (stats == NULL) 3286 return -EINVAL; 3287 3288 /* Fill out the rte_eth_stats statistics structure */ 3289 stats->ipackets = total_qprc; 3290 stats->ibytes = total_qbrc; 3291 stats->opackets = hw_stats->gptc; 3292 stats->obytes = hw_stats->gotc; 3293 3294 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3295 stats->q_ipackets[i] = hw_stats->qprc[i]; 3296 stats->q_opackets[i] = hw_stats->qptc[i]; 3297 stats->q_ibytes[i] = hw_stats->qbrc[i]; 3298 stats->q_obytes[i] = hw_stats->qbtc[i]; 3299 stats->q_errors[i] = hw_stats->qprdc[i]; 3300 } 3301 3302 /* Rx Errors */ 3303 stats->imissed = total_missed_rx; 3304 stats->ierrors = hw_stats->crcerrs + 3305 hw_stats->mspdc + 3306 hw_stats->rlec + 3307 hw_stats->ruc + 3308 hw_stats->roc + 3309 hw_stats->illerrc + 3310 hw_stats->errbc + 3311 hw_stats->rfc + 3312 hw_stats->fccrc + 3313 hw_stats->fclast; 3314 3315 /* Tx Errors */ 3316 stats->oerrors = 0; 3317 return 0; 3318 } 3319 3320 static void 3321 ixgbe_dev_stats_reset(struct rte_eth_dev *dev) 3322 { 3323 struct ixgbe_hw_stats *stats = 3324 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3325 3326 /* HW registers are cleared on read */ 3327 ixgbe_dev_stats_get(dev, NULL); 3328 3329 /* Reset software totals */ 3330 memset(stats, 0, sizeof(*stats)); 3331 } 3332 3333 /* This function calculates the number of xstats based on the current config */ 3334 static unsigned 3335 ixgbe_xstats_calc_num(void) { 3336 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS + 3337 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) + 3338 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES); 3339 } 3340 3341 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3342 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size) 3343 { 3344 const unsigned cnt_stats = ixgbe_xstats_calc_num(); 3345 unsigned stat, i, count; 3346 3347 if (xstats_names != NULL) { 3348 count = 0; 3349 3350 /* Note: limit >= cnt_stats checked upstream 3351 * in rte_eth_xstats_names() 3352 */ 3353 3354 /* Extended stats from ixgbe_hw_stats */ 3355 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3356 strlcpy(xstats_names[count].name, 3357 rte_ixgbe_stats_strings[i].name, 3358 sizeof(xstats_names[count].name)); 3359 count++; 3360 } 3361 3362 /* MACsec Stats */ 3363 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3364 strlcpy(xstats_names[count].name, 3365 rte_ixgbe_macsec_strings[i].name, 3366 sizeof(xstats_names[count].name)); 3367 count++; 3368 } 3369 3370 /* RX Priority Stats */ 3371 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3372 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3373 snprintf(xstats_names[count].name, 3374 sizeof(xstats_names[count].name), 3375 "rx_priority%u_%s", i, 3376 rte_ixgbe_rxq_strings[stat].name); 3377 count++; 3378 } 3379 } 3380 3381 /* TX Priority Stats */ 3382 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3383 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3384 snprintf(xstats_names[count].name, 3385 sizeof(xstats_names[count].name), 3386 "tx_priority%u_%s", i, 3387 rte_ixgbe_txq_strings[stat].name); 3388 count++; 3389 } 3390 } 3391 } 3392 return cnt_stats; 3393 } 3394 3395 static int ixgbe_dev_xstats_get_names_by_id( 3396 struct rte_eth_dev *dev, 3397 struct rte_eth_xstat_name *xstats_names, 3398 const uint64_t *ids, 3399 unsigned int limit) 3400 { 3401 if (!ids) { 3402 const unsigned int cnt_stats = ixgbe_xstats_calc_num(); 3403 unsigned int stat, i, count; 3404 3405 if (xstats_names != NULL) { 3406 count = 0; 3407 3408 /* Note: limit >= cnt_stats checked upstream 3409 * in rte_eth_xstats_names() 3410 */ 3411 3412 /* Extended stats from ixgbe_hw_stats */ 3413 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3414 strlcpy(xstats_names[count].name, 3415 rte_ixgbe_stats_strings[i].name, 3416 sizeof(xstats_names[count].name)); 3417 count++; 3418 } 3419 3420 /* MACsec Stats */ 3421 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3422 strlcpy(xstats_names[count].name, 3423 rte_ixgbe_macsec_strings[i].name, 3424 sizeof(xstats_names[count].name)); 3425 count++; 3426 } 3427 3428 /* RX Priority Stats */ 3429 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3430 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3431 snprintf(xstats_names[count].name, 3432 sizeof(xstats_names[count].name), 3433 "rx_priority%u_%s", i, 3434 rte_ixgbe_rxq_strings[stat].name); 3435 count++; 3436 } 3437 } 3438 3439 /* TX Priority Stats */ 3440 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3441 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3442 snprintf(xstats_names[count].name, 3443 sizeof(xstats_names[count].name), 3444 "tx_priority%u_%s", i, 3445 rte_ixgbe_txq_strings[stat].name); 3446 count++; 3447 } 3448 } 3449 } 3450 return cnt_stats; 3451 } 3452 3453 uint16_t i; 3454 uint16_t size = ixgbe_xstats_calc_num(); 3455 struct rte_eth_xstat_name xstats_names_copy[size]; 3456 3457 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL, 3458 size); 3459 3460 for (i = 0; i < limit; i++) { 3461 if (ids[i] >= size) { 3462 PMD_INIT_LOG(ERR, "id value isn't valid"); 3463 return -1; 3464 } 3465 strcpy(xstats_names[i].name, 3466 xstats_names_copy[ids[i]].name); 3467 } 3468 return limit; 3469 } 3470 3471 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3472 struct rte_eth_xstat_name *xstats_names, unsigned limit) 3473 { 3474 unsigned i; 3475 3476 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL) 3477 return -ENOMEM; 3478 3479 if (xstats_names != NULL) 3480 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) 3481 strlcpy(xstats_names[i].name, 3482 rte_ixgbevf_stats_strings[i].name, 3483 sizeof(xstats_names[i].name)); 3484 return IXGBEVF_NB_XSTATS; 3485 } 3486 3487 static int 3488 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3489 unsigned n) 3490 { 3491 struct ixgbe_hw *hw = 3492 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3493 struct ixgbe_hw_stats *hw_stats = 3494 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3495 struct ixgbe_macsec_stats *macsec_stats = 3496 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3497 dev->data->dev_private); 3498 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3499 unsigned i, stat, count = 0; 3500 3501 count = ixgbe_xstats_calc_num(); 3502 3503 if (n < count) 3504 return count; 3505 3506 total_missed_rx = 0; 3507 total_qbrc = 0; 3508 total_qprc = 0; 3509 total_qprdc = 0; 3510 3511 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3512 &total_qbrc, &total_qprc, &total_qprdc); 3513 3514 /* If this is a reset xstats is NULL, and we have cleared the 3515 * registers by reading them. 3516 */ 3517 if (!xstats) 3518 return 0; 3519 3520 /* Extended stats from ixgbe_hw_stats */ 3521 count = 0; 3522 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3523 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3524 rte_ixgbe_stats_strings[i].offset); 3525 xstats[count].id = count; 3526 count++; 3527 } 3528 3529 /* MACsec Stats */ 3530 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3531 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) + 3532 rte_ixgbe_macsec_strings[i].offset); 3533 xstats[count].id = count; 3534 count++; 3535 } 3536 3537 /* RX Priority Stats */ 3538 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3539 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3540 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3541 rte_ixgbe_rxq_strings[stat].offset + 3542 (sizeof(uint64_t) * i)); 3543 xstats[count].id = count; 3544 count++; 3545 } 3546 } 3547 3548 /* TX Priority Stats */ 3549 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3550 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3551 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3552 rte_ixgbe_txq_strings[stat].offset + 3553 (sizeof(uint64_t) * i)); 3554 xstats[count].id = count; 3555 count++; 3556 } 3557 } 3558 return count; 3559 } 3560 3561 static int 3562 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 3563 uint64_t *values, unsigned int n) 3564 { 3565 if (!ids) { 3566 struct ixgbe_hw *hw = 3567 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3568 struct ixgbe_hw_stats *hw_stats = 3569 IXGBE_DEV_PRIVATE_TO_STATS( 3570 dev->data->dev_private); 3571 struct ixgbe_macsec_stats *macsec_stats = 3572 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3573 dev->data->dev_private); 3574 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3575 unsigned int i, stat, count = 0; 3576 3577 count = ixgbe_xstats_calc_num(); 3578 3579 if (!ids && n < count) 3580 return count; 3581 3582 total_missed_rx = 0; 3583 total_qbrc = 0; 3584 total_qprc = 0; 3585 total_qprdc = 0; 3586 3587 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, 3588 &total_missed_rx, &total_qbrc, &total_qprc, 3589 &total_qprdc); 3590 3591 /* If this is a reset xstats is NULL, and we have cleared the 3592 * registers by reading them. 3593 */ 3594 if (!ids && !values) 3595 return 0; 3596 3597 /* Extended stats from ixgbe_hw_stats */ 3598 count = 0; 3599 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3600 values[count] = *(uint64_t *)(((char *)hw_stats) + 3601 rte_ixgbe_stats_strings[i].offset); 3602 count++; 3603 } 3604 3605 /* MACsec Stats */ 3606 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3607 values[count] = *(uint64_t *)(((char *)macsec_stats) + 3608 rte_ixgbe_macsec_strings[i].offset); 3609 count++; 3610 } 3611 3612 /* RX Priority Stats */ 3613 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3614 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3615 values[count] = 3616 *(uint64_t *)(((char *)hw_stats) + 3617 rte_ixgbe_rxq_strings[stat].offset + 3618 (sizeof(uint64_t) * i)); 3619 count++; 3620 } 3621 } 3622 3623 /* TX Priority Stats */ 3624 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3625 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3626 values[count] = 3627 *(uint64_t *)(((char *)hw_stats) + 3628 rte_ixgbe_txq_strings[stat].offset + 3629 (sizeof(uint64_t) * i)); 3630 count++; 3631 } 3632 } 3633 return count; 3634 } 3635 3636 uint16_t i; 3637 uint16_t size = ixgbe_xstats_calc_num(); 3638 uint64_t values_copy[size]; 3639 3640 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size); 3641 3642 for (i = 0; i < n; i++) { 3643 if (ids[i] >= size) { 3644 PMD_INIT_LOG(ERR, "id value isn't valid"); 3645 return -1; 3646 } 3647 values[i] = values_copy[ids[i]]; 3648 } 3649 return n; 3650 } 3651 3652 static void 3653 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev) 3654 { 3655 struct ixgbe_hw_stats *stats = 3656 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3657 struct ixgbe_macsec_stats *macsec_stats = 3658 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3659 dev->data->dev_private); 3660 3661 unsigned count = ixgbe_xstats_calc_num(); 3662 3663 /* HW registers are cleared on read */ 3664 ixgbe_dev_xstats_get(dev, NULL, count); 3665 3666 /* Reset software totals */ 3667 memset(stats, 0, sizeof(*stats)); 3668 memset(macsec_stats, 0, sizeof(*macsec_stats)); 3669 } 3670 3671 static void 3672 ixgbevf_update_stats(struct rte_eth_dev *dev) 3673 { 3674 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3675 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3676 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3677 3678 /* Good Rx packet, include VF loopback */ 3679 UPDATE_VF_STAT(IXGBE_VFGPRC, 3680 hw_stats->last_vfgprc, hw_stats->vfgprc); 3681 3682 /* Good Rx octets, include VF loopback */ 3683 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB, 3684 hw_stats->last_vfgorc, hw_stats->vfgorc); 3685 3686 /* Good Tx packet, include VF loopback */ 3687 UPDATE_VF_STAT(IXGBE_VFGPTC, 3688 hw_stats->last_vfgptc, hw_stats->vfgptc); 3689 3690 /* Good Tx octets, include VF loopback */ 3691 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB, 3692 hw_stats->last_vfgotc, hw_stats->vfgotc); 3693 3694 /* Rx Multicst Packet */ 3695 UPDATE_VF_STAT(IXGBE_VFMPRC, 3696 hw_stats->last_vfmprc, hw_stats->vfmprc); 3697 } 3698 3699 static int 3700 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3701 unsigned n) 3702 { 3703 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3704 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3705 unsigned i; 3706 3707 if (n < IXGBEVF_NB_XSTATS) 3708 return IXGBEVF_NB_XSTATS; 3709 3710 ixgbevf_update_stats(dev); 3711 3712 if (!xstats) 3713 return 0; 3714 3715 /* Extended stats */ 3716 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) { 3717 xstats[i].id = i; 3718 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + 3719 rte_ixgbevf_stats_strings[i].offset); 3720 } 3721 3722 return IXGBEVF_NB_XSTATS; 3723 } 3724 3725 static int 3726 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3727 { 3728 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3729 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3730 3731 ixgbevf_update_stats(dev); 3732 3733 if (stats == NULL) 3734 return -EINVAL; 3735 3736 stats->ipackets = hw_stats->vfgprc; 3737 stats->ibytes = hw_stats->vfgorc; 3738 stats->opackets = hw_stats->vfgptc; 3739 stats->obytes = hw_stats->vfgotc; 3740 return 0; 3741 } 3742 3743 static void 3744 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev) 3745 { 3746 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3747 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3748 3749 /* Sync HW register to the last stats */ 3750 ixgbevf_dev_stats_get(dev, NULL); 3751 3752 /* reset HW current stats*/ 3753 hw_stats->vfgprc = 0; 3754 hw_stats->vfgorc = 0; 3755 hw_stats->vfgptc = 0; 3756 hw_stats->vfgotc = 0; 3757 } 3758 3759 static int 3760 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 3761 { 3762 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3763 u16 eeprom_verh, eeprom_verl; 3764 u32 etrack_id; 3765 int ret; 3766 3767 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh); 3768 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl); 3769 3770 etrack_id = (eeprom_verh << 16) | eeprom_verl; 3771 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id); 3772 3773 ret += 1; /* add the size of '\0' */ 3774 if (fw_size < (u32)ret) 3775 return ret; 3776 else 3777 return 0; 3778 } 3779 3780 static void 3781 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3782 { 3783 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3784 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3785 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 3786 3787 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3788 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3789 if (RTE_ETH_DEV_SRIOV(dev).active == 0) { 3790 /* 3791 * When DCB/VT is off, maximum number of queues changes, 3792 * except for 82598EB, which remains constant. 3793 */ 3794 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 3795 hw->mac.type != ixgbe_mac_82598EB) 3796 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES; 3797 } 3798 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */ 3799 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */ 3800 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3801 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3802 dev_info->max_vfs = pci_dev->max_vfs; 3803 if (hw->mac.type == ixgbe_mac_82598EB) 3804 dev_info->max_vmdq_pools = ETH_16_POOLS; 3805 else 3806 dev_info->max_vmdq_pools = ETH_64_POOLS; 3807 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD; 3808 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 3809 dev_info->vmdq_queue_num = dev_info->max_rx_queues; 3810 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3811 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3812 dev_info->rx_queue_offload_capa); 3813 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3814 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3815 3816 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3817 .rx_thresh = { 3818 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3819 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3820 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3821 }, 3822 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3823 .rx_drop_en = 0, 3824 .offloads = 0, 3825 }; 3826 3827 dev_info->default_txconf = (struct rte_eth_txconf) { 3828 .tx_thresh = { 3829 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3830 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3831 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3832 }, 3833 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3834 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3835 .offloads = 0, 3836 }; 3837 3838 dev_info->rx_desc_lim = rx_desc_lim; 3839 dev_info->tx_desc_lim = tx_desc_lim; 3840 3841 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 3842 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 3843 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 3844 3845 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 3846 if (hw->mac.type == ixgbe_mac_X540 || 3847 hw->mac.type == ixgbe_mac_X540_vf || 3848 hw->mac.type == ixgbe_mac_X550 || 3849 hw->mac.type == ixgbe_mac_X550_vf) { 3850 dev_info->speed_capa |= ETH_LINK_SPEED_100M; 3851 } 3852 if (hw->mac.type == ixgbe_mac_X550) { 3853 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G; 3854 dev_info->speed_capa |= ETH_LINK_SPEED_5G; 3855 } 3856 3857 /* Driver-preferred Rx/Tx parameters */ 3858 dev_info->default_rxportconf.burst_size = 32; 3859 dev_info->default_txportconf.burst_size = 32; 3860 dev_info->default_rxportconf.nb_queues = 1; 3861 dev_info->default_txportconf.nb_queues = 1; 3862 dev_info->default_rxportconf.ring_size = 256; 3863 dev_info->default_txportconf.ring_size = 256; 3864 } 3865 3866 static const uint32_t * 3867 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 3868 { 3869 static const uint32_t ptypes[] = { 3870 /* For non-vec functions, 3871 * refers to ixgbe_rxd_pkt_info_to_pkt_type(); 3872 * for vec functions, 3873 * refers to _recv_raw_pkts_vec(). 3874 */ 3875 RTE_PTYPE_L2_ETHER, 3876 RTE_PTYPE_L3_IPV4, 3877 RTE_PTYPE_L3_IPV4_EXT, 3878 RTE_PTYPE_L3_IPV6, 3879 RTE_PTYPE_L3_IPV6_EXT, 3880 RTE_PTYPE_L4_SCTP, 3881 RTE_PTYPE_L4_TCP, 3882 RTE_PTYPE_L4_UDP, 3883 RTE_PTYPE_TUNNEL_IP, 3884 RTE_PTYPE_INNER_L3_IPV6, 3885 RTE_PTYPE_INNER_L3_IPV6_EXT, 3886 RTE_PTYPE_INNER_L4_TCP, 3887 RTE_PTYPE_INNER_L4_UDP, 3888 RTE_PTYPE_UNKNOWN 3889 }; 3890 3891 if (dev->rx_pkt_burst == ixgbe_recv_pkts || 3892 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc || 3893 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc || 3894 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc) 3895 return ptypes; 3896 3897 #if defined(RTE_ARCH_X86) 3898 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec || 3899 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec) 3900 return ptypes; 3901 #endif 3902 return NULL; 3903 } 3904 3905 static void 3906 ixgbevf_dev_info_get(struct rte_eth_dev *dev, 3907 struct rte_eth_dev_info *dev_info) 3908 { 3909 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3910 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3911 3912 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3913 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3914 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */ 3915 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */ 3916 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD; 3917 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3918 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3919 dev_info->max_vfs = pci_dev->max_vfs; 3920 if (hw->mac.type == ixgbe_mac_82598EB) 3921 dev_info->max_vmdq_pools = ETH_16_POOLS; 3922 else 3923 dev_info->max_vmdq_pools = ETH_64_POOLS; 3924 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3925 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3926 dev_info->rx_queue_offload_capa); 3927 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3928 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3929 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 3930 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 3931 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 3932 3933 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3934 .rx_thresh = { 3935 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3936 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3937 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3938 }, 3939 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3940 .rx_drop_en = 0, 3941 .offloads = 0, 3942 }; 3943 3944 dev_info->default_txconf = (struct rte_eth_txconf) { 3945 .tx_thresh = { 3946 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3947 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3948 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3949 }, 3950 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3951 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3952 .offloads = 0, 3953 }; 3954 3955 dev_info->rx_desc_lim = rx_desc_lim; 3956 dev_info->tx_desc_lim = tx_desc_lim; 3957 } 3958 3959 static int 3960 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3961 int *link_up, int wait_to_complete) 3962 { 3963 struct ixgbe_adapter *adapter = container_of(hw, 3964 struct ixgbe_adapter, hw); 3965 struct ixgbe_mbx_info *mbx = &hw->mbx; 3966 struct ixgbe_mac_info *mac = &hw->mac; 3967 uint32_t links_reg, in_msg; 3968 int ret_val = 0; 3969 3970 /* If we were hit with a reset drop the link */ 3971 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout) 3972 mac->get_link_status = true; 3973 3974 if (!mac->get_link_status) 3975 goto out; 3976 3977 /* if link status is down no point in checking to see if pf is up */ 3978 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 3979 if (!(links_reg & IXGBE_LINKS_UP)) 3980 goto out; 3981 3982 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs 3983 * before the link status is correct 3984 */ 3985 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) { 3986 int i; 3987 3988 for (i = 0; i < 5; i++) { 3989 rte_delay_us(100); 3990 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 3991 3992 if (!(links_reg & IXGBE_LINKS_UP)) 3993 goto out; 3994 } 3995 } 3996 3997 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 3998 case IXGBE_LINKS_SPEED_10G_82599: 3999 *speed = IXGBE_LINK_SPEED_10GB_FULL; 4000 if (hw->mac.type >= ixgbe_mac_X550) { 4001 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4002 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4003 } 4004 break; 4005 case IXGBE_LINKS_SPEED_1G_82599: 4006 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4007 break; 4008 case IXGBE_LINKS_SPEED_100_82599: 4009 *speed = IXGBE_LINK_SPEED_100_FULL; 4010 if (hw->mac.type == ixgbe_mac_X550) { 4011 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4012 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4013 } 4014 break; 4015 case IXGBE_LINKS_SPEED_10_X550EM_A: 4016 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4017 /* Since Reserved in older MAC's */ 4018 if (hw->mac.type >= ixgbe_mac_X550) 4019 *speed = IXGBE_LINK_SPEED_10_FULL; 4020 break; 4021 default: 4022 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4023 } 4024 4025 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) { 4026 if (*speed == IXGBE_LINK_SPEED_UNKNOWN) 4027 mac->get_link_status = true; 4028 else 4029 mac->get_link_status = false; 4030 4031 goto out; 4032 } 4033 4034 /* if the read failed it could just be a mailbox collision, best wait 4035 * until we are called again and don't report an error 4036 */ 4037 if (mbx->ops.read(hw, &in_msg, 1, 0)) 4038 goto out; 4039 4040 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) { 4041 /* msg is not CTS and is NACK we must have lost CTS status */ 4042 if (in_msg & IXGBE_VT_MSGTYPE_NACK) 4043 mac->get_link_status = false; 4044 goto out; 4045 } 4046 4047 /* the pf is talking, if we timed out in the past we reinit */ 4048 if (!mbx->timeout) { 4049 ret_val = -1; 4050 goto out; 4051 } 4052 4053 /* if we passed all the tests above then the link is up and we no 4054 * longer need to check for link 4055 */ 4056 mac->get_link_status = false; 4057 4058 out: 4059 *link_up = !mac->get_link_status; 4060 return ret_val; 4061 } 4062 4063 static void 4064 ixgbe_dev_setup_link_alarm_handler(void *param) 4065 { 4066 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4067 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4068 struct ixgbe_interrupt *intr = 4069 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4070 u32 speed; 4071 bool autoneg = false; 4072 4073 speed = hw->phy.autoneg_advertised; 4074 if (!speed) 4075 ixgbe_get_link_capabilities(hw, &speed, &autoneg); 4076 4077 ixgbe_setup_link(hw, speed, true); 4078 4079 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 4080 } 4081 4082 /* return 0 means link status changed, -1 means not changed */ 4083 int 4084 ixgbe_dev_link_update_share(struct rte_eth_dev *dev, 4085 int wait_to_complete, int vf) 4086 { 4087 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4088 struct rte_eth_link link; 4089 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4090 struct ixgbe_interrupt *intr = 4091 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4092 int link_up; 4093 int diag; 4094 int wait = 1; 4095 4096 memset(&link, 0, sizeof(link)); 4097 link.link_status = ETH_LINK_DOWN; 4098 link.link_speed = ETH_SPEED_NUM_NONE; 4099 link.link_duplex = ETH_LINK_HALF_DUPLEX; 4100 link.link_autoneg = ETH_LINK_AUTONEG; 4101 4102 hw->mac.get_link_status = true; 4103 4104 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) 4105 return rte_eth_linkstatus_set(dev, &link); 4106 4107 /* check if it needs to wait to complete, if lsc interrupt is enabled */ 4108 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0) 4109 wait = 0; 4110 4111 if (vf) 4112 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait); 4113 else 4114 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait); 4115 4116 if (diag != 0) { 4117 link.link_speed = ETH_SPEED_NUM_100M; 4118 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4119 return rte_eth_linkstatus_set(dev, &link); 4120 } 4121 4122 if (link_up == 0) { 4123 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) { 4124 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 4125 rte_eal_alarm_set(10, 4126 ixgbe_dev_setup_link_alarm_handler, dev); 4127 } 4128 return rte_eth_linkstatus_set(dev, &link); 4129 } 4130 4131 link.link_status = ETH_LINK_UP; 4132 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4133 4134 switch (link_speed) { 4135 default: 4136 case IXGBE_LINK_SPEED_UNKNOWN: 4137 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 4138 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 4139 link.link_speed = ETH_SPEED_NUM_10M; 4140 else 4141 link.link_speed = ETH_SPEED_NUM_100M; 4142 break; 4143 4144 case IXGBE_LINK_SPEED_100_FULL: 4145 link.link_speed = ETH_SPEED_NUM_100M; 4146 break; 4147 4148 case IXGBE_LINK_SPEED_1GB_FULL: 4149 link.link_speed = ETH_SPEED_NUM_1G; 4150 break; 4151 4152 case IXGBE_LINK_SPEED_2_5GB_FULL: 4153 link.link_speed = ETH_SPEED_NUM_2_5G; 4154 break; 4155 4156 case IXGBE_LINK_SPEED_5GB_FULL: 4157 link.link_speed = ETH_SPEED_NUM_5G; 4158 break; 4159 4160 case IXGBE_LINK_SPEED_10GB_FULL: 4161 link.link_speed = ETH_SPEED_NUM_10G; 4162 break; 4163 } 4164 4165 return rte_eth_linkstatus_set(dev, &link); 4166 } 4167 4168 static int 4169 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4170 { 4171 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0); 4172 } 4173 4174 static int 4175 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4176 { 4177 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1); 4178 } 4179 4180 static void 4181 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 4182 { 4183 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4184 uint32_t fctrl; 4185 4186 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4187 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4188 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4189 } 4190 4191 static void 4192 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 4193 { 4194 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4195 uint32_t fctrl; 4196 4197 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4198 fctrl &= (~IXGBE_FCTRL_UPE); 4199 if (dev->data->all_multicast == 1) 4200 fctrl |= IXGBE_FCTRL_MPE; 4201 else 4202 fctrl &= (~IXGBE_FCTRL_MPE); 4203 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4204 } 4205 4206 static void 4207 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 4208 { 4209 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4210 uint32_t fctrl; 4211 4212 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4213 fctrl |= IXGBE_FCTRL_MPE; 4214 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4215 } 4216 4217 static void 4218 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 4219 { 4220 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4221 uint32_t fctrl; 4222 4223 if (dev->data->promiscuous == 1) 4224 return; /* must remain in all_multicast mode */ 4225 4226 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4227 fctrl &= (~IXGBE_FCTRL_MPE); 4228 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4229 } 4230 4231 /** 4232 * It clears the interrupt causes and enables the interrupt. 4233 * It will be called once only during nic initialized. 4234 * 4235 * @param dev 4236 * Pointer to struct rte_eth_dev. 4237 * @param on 4238 * Enable or Disable. 4239 * 4240 * @return 4241 * - On success, zero. 4242 * - On failure, a negative value. 4243 */ 4244 static int 4245 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 4246 { 4247 struct ixgbe_interrupt *intr = 4248 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4249 4250 ixgbe_dev_link_status_print(dev); 4251 if (on) 4252 intr->mask |= IXGBE_EICR_LSC; 4253 else 4254 intr->mask &= ~IXGBE_EICR_LSC; 4255 4256 return 0; 4257 } 4258 4259 /** 4260 * It clears the interrupt causes and enables the interrupt. 4261 * It will be called once only during nic initialized. 4262 * 4263 * @param dev 4264 * Pointer to struct rte_eth_dev. 4265 * 4266 * @return 4267 * - On success, zero. 4268 * - On failure, a negative value. 4269 */ 4270 static int 4271 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev) 4272 { 4273 struct ixgbe_interrupt *intr = 4274 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4275 4276 intr->mask |= IXGBE_EICR_RTX_QUEUE; 4277 4278 return 0; 4279 } 4280 4281 /** 4282 * It clears the interrupt causes and enables the interrupt. 4283 * It will be called once only during nic initialized. 4284 * 4285 * @param dev 4286 * Pointer to struct rte_eth_dev. 4287 * 4288 * @return 4289 * - On success, zero. 4290 * - On failure, a negative value. 4291 */ 4292 static int 4293 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev) 4294 { 4295 struct ixgbe_interrupt *intr = 4296 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4297 4298 intr->mask |= IXGBE_EICR_LINKSEC; 4299 4300 return 0; 4301 } 4302 4303 /* 4304 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update. 4305 * 4306 * @param dev 4307 * Pointer to struct rte_eth_dev. 4308 * 4309 * @return 4310 * - On success, zero. 4311 * - On failure, a negative value. 4312 */ 4313 static int 4314 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev) 4315 { 4316 uint32_t eicr; 4317 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4318 struct ixgbe_interrupt *intr = 4319 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4320 4321 /* clear all cause mask */ 4322 ixgbe_disable_intr(hw); 4323 4324 /* read-on-clear nic registers here */ 4325 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4326 PMD_DRV_LOG(DEBUG, "eicr %x", eicr); 4327 4328 intr->flags = 0; 4329 4330 /* set flag for async link update */ 4331 if (eicr & IXGBE_EICR_LSC) 4332 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 4333 4334 if (eicr & IXGBE_EICR_MAILBOX) 4335 intr->flags |= IXGBE_FLAG_MAILBOX; 4336 4337 if (eicr & IXGBE_EICR_LINKSEC) 4338 intr->flags |= IXGBE_FLAG_MACSEC; 4339 4340 if (hw->mac.type == ixgbe_mac_X550EM_x && 4341 hw->phy.type == ixgbe_phy_x550em_ext_t && 4342 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x)) 4343 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT; 4344 4345 return 0; 4346 } 4347 4348 /** 4349 * It gets and then prints the link status. 4350 * 4351 * @param dev 4352 * Pointer to struct rte_eth_dev. 4353 * 4354 * @return 4355 * - On success, zero. 4356 * - On failure, a negative value. 4357 */ 4358 static void 4359 ixgbe_dev_link_status_print(struct rte_eth_dev *dev) 4360 { 4361 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4362 struct rte_eth_link link; 4363 4364 rte_eth_linkstatus_get(dev, &link); 4365 4366 if (link.link_status) { 4367 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", 4368 (int)(dev->data->port_id), 4369 (unsigned)link.link_speed, 4370 link.link_duplex == ETH_LINK_FULL_DUPLEX ? 4371 "full-duplex" : "half-duplex"); 4372 } else { 4373 PMD_INIT_LOG(INFO, " Port %d: Link Down", 4374 (int)(dev->data->port_id)); 4375 } 4376 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 4377 pci_dev->addr.domain, 4378 pci_dev->addr.bus, 4379 pci_dev->addr.devid, 4380 pci_dev->addr.function); 4381 } 4382 4383 /* 4384 * It executes link_update after knowing an interrupt occurred. 4385 * 4386 * @param dev 4387 * Pointer to struct rte_eth_dev. 4388 * 4389 * @return 4390 * - On success, zero. 4391 * - On failure, a negative value. 4392 */ 4393 static int 4394 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev) 4395 { 4396 struct ixgbe_interrupt *intr = 4397 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4398 int64_t timeout; 4399 struct ixgbe_hw *hw = 4400 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4401 4402 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags); 4403 4404 if (intr->flags & IXGBE_FLAG_MAILBOX) { 4405 ixgbe_pf_mbx_process(dev); 4406 intr->flags &= ~IXGBE_FLAG_MAILBOX; 4407 } 4408 4409 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4410 ixgbe_handle_lasi(hw); 4411 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4412 } 4413 4414 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4415 struct rte_eth_link link; 4416 4417 /* get the link status before link update, for predicting later */ 4418 rte_eth_linkstatus_get(dev, &link); 4419 4420 ixgbe_dev_link_update(dev, 0); 4421 4422 /* likely to up */ 4423 if (!link.link_status) 4424 /* handle it 1 sec later, wait it being stable */ 4425 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT; 4426 /* likely to down */ 4427 else 4428 /* handle it 4 sec later, wait it being stable */ 4429 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT; 4430 4431 ixgbe_dev_link_status_print(dev); 4432 if (rte_eal_alarm_set(timeout * 1000, 4433 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0) 4434 PMD_DRV_LOG(ERR, "Error setting alarm"); 4435 else { 4436 /* remember original mask */ 4437 intr->mask_original = intr->mask; 4438 /* only disable lsc interrupt */ 4439 intr->mask &= ~IXGBE_EIMS_LSC; 4440 } 4441 } 4442 4443 PMD_DRV_LOG(DEBUG, "enable intr immediately"); 4444 ixgbe_enable_intr(dev); 4445 4446 return 0; 4447 } 4448 4449 /** 4450 * Interrupt handler which shall be registered for alarm callback for delayed 4451 * handling specific interrupt to wait for the stable nic state. As the 4452 * NIC interrupt state is not stable for ixgbe after link is just down, 4453 * it needs to wait 4 seconds to get the stable status. 4454 * 4455 * @param handle 4456 * Pointer to interrupt handle. 4457 * @param param 4458 * The address of parameter (struct rte_eth_dev *) regsitered before. 4459 * 4460 * @return 4461 * void 4462 */ 4463 static void 4464 ixgbe_dev_interrupt_delayed_handler(void *param) 4465 { 4466 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4467 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4468 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4469 struct ixgbe_interrupt *intr = 4470 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4471 struct ixgbe_hw *hw = 4472 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4473 uint32_t eicr; 4474 4475 ixgbe_disable_intr(hw); 4476 4477 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4478 if (eicr & IXGBE_EICR_MAILBOX) 4479 ixgbe_pf_mbx_process(dev); 4480 4481 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4482 ixgbe_handle_lasi(hw); 4483 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4484 } 4485 4486 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4487 ixgbe_dev_link_update(dev, 0); 4488 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 4489 ixgbe_dev_link_status_print(dev); 4490 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, 4491 NULL); 4492 } 4493 4494 if (intr->flags & IXGBE_FLAG_MACSEC) { 4495 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, 4496 NULL); 4497 intr->flags &= ~IXGBE_FLAG_MACSEC; 4498 } 4499 4500 /* restore original mask */ 4501 intr->mask = intr->mask_original; 4502 intr->mask_original = 0; 4503 4504 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr); 4505 ixgbe_enable_intr(dev); 4506 rte_intr_ack(intr_handle); 4507 } 4508 4509 /** 4510 * Interrupt handler triggered by NIC for handling 4511 * specific interrupt. 4512 * 4513 * @param handle 4514 * Pointer to interrupt handle. 4515 * @param param 4516 * The address of parameter (struct rte_eth_dev *) regsitered before. 4517 * 4518 * @return 4519 * void 4520 */ 4521 static void 4522 ixgbe_dev_interrupt_handler(void *param) 4523 { 4524 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4525 4526 ixgbe_dev_interrupt_get_status(dev); 4527 ixgbe_dev_interrupt_action(dev); 4528 } 4529 4530 static int 4531 ixgbe_dev_led_on(struct rte_eth_dev *dev) 4532 { 4533 struct ixgbe_hw *hw; 4534 4535 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4536 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4537 } 4538 4539 static int 4540 ixgbe_dev_led_off(struct rte_eth_dev *dev) 4541 { 4542 struct ixgbe_hw *hw; 4543 4544 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4545 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4546 } 4547 4548 static int 4549 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4550 { 4551 struct ixgbe_hw *hw; 4552 uint32_t mflcn_reg; 4553 uint32_t fccfg_reg; 4554 int rx_pause; 4555 int tx_pause; 4556 4557 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4558 4559 fc_conf->pause_time = hw->fc.pause_time; 4560 fc_conf->high_water = hw->fc.high_water[0]; 4561 fc_conf->low_water = hw->fc.low_water[0]; 4562 fc_conf->send_xon = hw->fc.send_xon; 4563 fc_conf->autoneg = !hw->fc.disable_fc_autoneg; 4564 4565 /* 4566 * Return rx_pause status according to actual setting of 4567 * MFLCN register. 4568 */ 4569 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4570 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE)) 4571 rx_pause = 1; 4572 else 4573 rx_pause = 0; 4574 4575 /* 4576 * Return tx_pause status according to actual setting of 4577 * FCCFG register. 4578 */ 4579 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4580 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY)) 4581 tx_pause = 1; 4582 else 4583 tx_pause = 0; 4584 4585 if (rx_pause && tx_pause) 4586 fc_conf->mode = RTE_FC_FULL; 4587 else if (rx_pause) 4588 fc_conf->mode = RTE_FC_RX_PAUSE; 4589 else if (tx_pause) 4590 fc_conf->mode = RTE_FC_TX_PAUSE; 4591 else 4592 fc_conf->mode = RTE_FC_NONE; 4593 4594 return 0; 4595 } 4596 4597 static int 4598 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4599 { 4600 struct ixgbe_hw *hw; 4601 int err; 4602 uint32_t rx_buf_size; 4603 uint32_t max_high_water; 4604 uint32_t mflcn; 4605 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4606 ixgbe_fc_none, 4607 ixgbe_fc_rx_pause, 4608 ixgbe_fc_tx_pause, 4609 ixgbe_fc_full 4610 }; 4611 4612 PMD_INIT_FUNC_TRACE(); 4613 4614 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4615 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)); 4616 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4617 4618 /* 4619 * At least reserve one Ethernet frame for watermark 4620 * high_water/low_water in kilo bytes for ixgbe 4621 */ 4622 max_high_water = (rx_buf_size - 4623 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4624 if ((fc_conf->high_water > max_high_water) || 4625 (fc_conf->high_water < fc_conf->low_water)) { 4626 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4627 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4628 return -EINVAL; 4629 } 4630 4631 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode]; 4632 hw->fc.pause_time = fc_conf->pause_time; 4633 hw->fc.high_water[0] = fc_conf->high_water; 4634 hw->fc.low_water[0] = fc_conf->low_water; 4635 hw->fc.send_xon = fc_conf->send_xon; 4636 hw->fc.disable_fc_autoneg = !fc_conf->autoneg; 4637 4638 err = ixgbe_fc_enable(hw); 4639 4640 /* Not negotiated is not an error case */ 4641 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) { 4642 4643 /* check if we want to forward MAC frames - driver doesn't have native 4644 * capability to do that, so we'll write the registers ourselves */ 4645 4646 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4647 4648 /* set or clear MFLCN.PMCF bit depending on configuration */ 4649 if (fc_conf->mac_ctrl_frame_fwd != 0) 4650 mflcn |= IXGBE_MFLCN_PMCF; 4651 else 4652 mflcn &= ~IXGBE_MFLCN_PMCF; 4653 4654 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn); 4655 IXGBE_WRITE_FLUSH(hw); 4656 4657 return 0; 4658 } 4659 4660 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err); 4661 return -EIO; 4662 } 4663 4664 /** 4665 * ixgbe_pfc_enable_generic - Enable flow control 4666 * @hw: pointer to hardware structure 4667 * @tc_num: traffic class number 4668 * Enable flow control according to the current settings. 4669 */ 4670 static int 4671 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num) 4672 { 4673 int ret_val = 0; 4674 uint32_t mflcn_reg, fccfg_reg; 4675 uint32_t reg; 4676 uint32_t fcrtl, fcrth; 4677 uint8_t i; 4678 uint8_t nb_rx_en; 4679 4680 /* Validate the water mark configuration */ 4681 if (!hw->fc.pause_time) { 4682 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4683 goto out; 4684 } 4685 4686 /* Low water mark of zero causes XOFF floods */ 4687 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 4688 /* High/Low water can not be 0 */ 4689 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) { 4690 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4691 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4692 goto out; 4693 } 4694 4695 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) { 4696 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4697 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4698 goto out; 4699 } 4700 } 4701 /* Negotiate the fc mode to use */ 4702 ixgbe_fc_autoneg(hw); 4703 4704 /* Disable any previous flow control settings */ 4705 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4706 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE); 4707 4708 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4709 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 4710 4711 switch (hw->fc.current_mode) { 4712 case ixgbe_fc_none: 4713 /* 4714 * If the count of enabled RX Priority Flow control >1, 4715 * and the TX pause can not be disabled 4716 */ 4717 nb_rx_en = 0; 4718 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4719 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4720 if (reg & IXGBE_FCRTH_FCEN) 4721 nb_rx_en++; 4722 } 4723 if (nb_rx_en > 1) 4724 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4725 break; 4726 case ixgbe_fc_rx_pause: 4727 /* 4728 * Rx Flow control is enabled and Tx Flow control is 4729 * disabled by software override. Since there really 4730 * isn't a way to advertise that we are capable of RX 4731 * Pause ONLY, we will advertise that we support both 4732 * symmetric and asymmetric Rx PAUSE. Later, we will 4733 * disable the adapter's ability to send PAUSE frames. 4734 */ 4735 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4736 /* 4737 * If the count of enabled RX Priority Flow control >1, 4738 * and the TX pause can not be disabled 4739 */ 4740 nb_rx_en = 0; 4741 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4742 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4743 if (reg & IXGBE_FCRTH_FCEN) 4744 nb_rx_en++; 4745 } 4746 if (nb_rx_en > 1) 4747 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4748 break; 4749 case ixgbe_fc_tx_pause: 4750 /* 4751 * Tx Flow control is enabled, and Rx Flow control is 4752 * disabled by software override. 4753 */ 4754 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4755 break; 4756 case ixgbe_fc_full: 4757 /* Flow control (both Rx and Tx) is enabled by SW override. */ 4758 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4759 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4760 break; 4761 default: 4762 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly"); 4763 ret_val = IXGBE_ERR_CONFIG; 4764 goto out; 4765 } 4766 4767 /* Set 802.3x based flow control settings. */ 4768 mflcn_reg |= IXGBE_MFLCN_DPF; 4769 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 4770 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 4771 4772 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 4773 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 4774 hw->fc.high_water[tc_num]) { 4775 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE; 4776 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl); 4777 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN; 4778 } else { 4779 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0); 4780 /* 4781 * In order to prevent Tx hangs when the internal Tx 4782 * switch is enabled we must set the high water mark 4783 * to the maximum FCRTH value. This allows the Tx 4784 * switch to function even under heavy Rx workloads. 4785 */ 4786 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32; 4787 } 4788 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth); 4789 4790 /* Configure pause time (2 TCs per register) */ 4791 reg = hw->fc.pause_time * 0x00010001; 4792 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 4793 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 4794 4795 /* Configure flow control refresh threshold value */ 4796 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 4797 4798 out: 4799 return ret_val; 4800 } 4801 4802 static int 4803 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num) 4804 { 4805 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4806 int32_t ret_val = IXGBE_NOT_IMPLEMENTED; 4807 4808 if (hw->mac.type != ixgbe_mac_82598EB) { 4809 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num); 4810 } 4811 return ret_val; 4812 } 4813 4814 static int 4815 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf) 4816 { 4817 int err; 4818 uint32_t rx_buf_size; 4819 uint32_t max_high_water; 4820 uint8_t tc_num; 4821 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 4822 struct ixgbe_hw *hw = 4823 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4824 struct ixgbe_dcb_config *dcb_config = 4825 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 4826 4827 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4828 ixgbe_fc_none, 4829 ixgbe_fc_rx_pause, 4830 ixgbe_fc_tx_pause, 4831 ixgbe_fc_full 4832 }; 4833 4834 PMD_INIT_FUNC_TRACE(); 4835 4836 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map); 4837 tc_num = map[pfc_conf->priority]; 4838 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)); 4839 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4840 /* 4841 * At least reserve one Ethernet frame for watermark 4842 * high_water/low_water in kilo bytes for ixgbe 4843 */ 4844 max_high_water = (rx_buf_size - 4845 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4846 if ((pfc_conf->fc.high_water > max_high_water) || 4847 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) { 4848 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4849 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4850 return -EINVAL; 4851 } 4852 4853 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode]; 4854 hw->fc.pause_time = pfc_conf->fc.pause_time; 4855 hw->fc.send_xon = pfc_conf->fc.send_xon; 4856 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water; 4857 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; 4858 4859 err = ixgbe_dcb_pfc_enable(dev, tc_num); 4860 4861 /* Not negotiated is not an error case */ 4862 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) 4863 return 0; 4864 4865 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err); 4866 return -EIO; 4867 } 4868 4869 static int 4870 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 4871 struct rte_eth_rss_reta_entry64 *reta_conf, 4872 uint16_t reta_size) 4873 { 4874 uint16_t i, sp_reta_size; 4875 uint8_t j, mask; 4876 uint32_t reta, r; 4877 uint16_t idx, shift; 4878 struct ixgbe_adapter *adapter = dev->data->dev_private; 4879 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4880 uint32_t reta_reg; 4881 4882 PMD_INIT_FUNC_TRACE(); 4883 4884 if (!ixgbe_rss_update_sp(hw->mac.type)) { 4885 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " 4886 "NIC."); 4887 return -ENOTSUP; 4888 } 4889 4890 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 4891 if (reta_size != sp_reta_size) { 4892 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 4893 "(%d) doesn't match the number hardware can supported " 4894 "(%d)", reta_size, sp_reta_size); 4895 return -EINVAL; 4896 } 4897 4898 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 4899 idx = i / RTE_RETA_GROUP_SIZE; 4900 shift = i % RTE_RETA_GROUP_SIZE; 4901 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 4902 IXGBE_4_BIT_MASK); 4903 if (!mask) 4904 continue; 4905 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 4906 if (mask == IXGBE_4_BIT_MASK) 4907 r = 0; 4908 else 4909 r = IXGBE_READ_REG(hw, reta_reg); 4910 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) { 4911 if (mask & (0x1 << j)) 4912 reta |= reta_conf[idx].reta[shift + j] << 4913 (CHAR_BIT * j); 4914 else 4915 reta |= r & (IXGBE_8_BIT_MASK << 4916 (CHAR_BIT * j)); 4917 } 4918 IXGBE_WRITE_REG(hw, reta_reg, reta); 4919 } 4920 adapter->rss_reta_updated = 1; 4921 4922 return 0; 4923 } 4924 4925 static int 4926 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 4927 struct rte_eth_rss_reta_entry64 *reta_conf, 4928 uint16_t reta_size) 4929 { 4930 uint16_t i, sp_reta_size; 4931 uint8_t j, mask; 4932 uint32_t reta; 4933 uint16_t idx, shift; 4934 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4935 uint32_t reta_reg; 4936 4937 PMD_INIT_FUNC_TRACE(); 4938 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 4939 if (reta_size != sp_reta_size) { 4940 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 4941 "(%d) doesn't match the number hardware can supported " 4942 "(%d)", reta_size, sp_reta_size); 4943 return -EINVAL; 4944 } 4945 4946 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 4947 idx = i / RTE_RETA_GROUP_SIZE; 4948 shift = i % RTE_RETA_GROUP_SIZE; 4949 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 4950 IXGBE_4_BIT_MASK); 4951 if (!mask) 4952 continue; 4953 4954 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 4955 reta = IXGBE_READ_REG(hw, reta_reg); 4956 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) { 4957 if (mask & (0x1 << j)) 4958 reta_conf[idx].reta[shift + j] = 4959 ((reta >> (CHAR_BIT * j)) & 4960 IXGBE_8_BIT_MASK); 4961 } 4962 } 4963 4964 return 0; 4965 } 4966 4967 static int 4968 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 4969 uint32_t index, uint32_t pool) 4970 { 4971 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4972 uint32_t enable_addr = 1; 4973 4974 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes, 4975 pool, enable_addr); 4976 } 4977 4978 static void 4979 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) 4980 { 4981 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4982 4983 ixgbe_clear_rar(hw, index); 4984 } 4985 4986 static int 4987 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 4988 { 4989 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4990 4991 ixgbe_remove_rar(dev, 0); 4992 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs); 4993 4994 return 0; 4995 } 4996 4997 static bool 4998 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 4999 { 5000 if (strcmp(dev->device->driver->name, drv->driver.name)) 5001 return false; 5002 5003 return true; 5004 } 5005 5006 bool 5007 is_ixgbe_supported(struct rte_eth_dev *dev) 5008 { 5009 return is_device_supported(dev, &rte_ixgbe_pmd); 5010 } 5011 5012 static int 5013 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 5014 { 5015 uint32_t hlreg0; 5016 uint32_t maxfrs; 5017 struct ixgbe_hw *hw; 5018 struct rte_eth_dev_info dev_info; 5019 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD; 5020 struct rte_eth_dev_data *dev_data = dev->data; 5021 5022 ixgbe_dev_info_get(dev, &dev_info); 5023 5024 /* check that mtu is within the allowed range */ 5025 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) 5026 return -EINVAL; 5027 5028 /* If device is started, refuse mtu that requires the support of 5029 * scattered packets when this feature has not been enabled before. 5030 */ 5031 if (dev_data->dev_started && !dev_data->scattered_rx && 5032 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE > 5033 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 5034 PMD_INIT_LOG(ERR, "Stop port first."); 5035 return -EINVAL; 5036 } 5037 5038 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5039 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 5040 5041 /* switch to jumbo mode if needed */ 5042 if (frame_size > RTE_ETHER_MAX_LEN) { 5043 dev->data->dev_conf.rxmode.offloads |= 5044 DEV_RX_OFFLOAD_JUMBO_FRAME; 5045 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 5046 } else { 5047 dev->data->dev_conf.rxmode.offloads &= 5048 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 5049 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; 5050 } 5051 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 5052 5053 /* update max frame size */ 5054 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 5055 5056 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS); 5057 maxfrs &= 0x0000FFFF; 5058 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16); 5059 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs); 5060 5061 return 0; 5062 } 5063 5064 /* 5065 * Virtual Function operations 5066 */ 5067 static void 5068 ixgbevf_intr_disable(struct rte_eth_dev *dev) 5069 { 5070 struct ixgbe_interrupt *intr = 5071 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5072 struct ixgbe_hw *hw = 5073 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5074 5075 PMD_INIT_FUNC_TRACE(); 5076 5077 /* Clear interrupt mask to stop from interrupts being generated */ 5078 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK); 5079 5080 IXGBE_WRITE_FLUSH(hw); 5081 5082 /* Clear mask value. */ 5083 intr->mask = 0; 5084 } 5085 5086 static void 5087 ixgbevf_intr_enable(struct rte_eth_dev *dev) 5088 { 5089 struct ixgbe_interrupt *intr = 5090 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5091 struct ixgbe_hw *hw = 5092 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5093 5094 PMD_INIT_FUNC_TRACE(); 5095 5096 /* VF enable interrupt autoclean */ 5097 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK); 5098 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK); 5099 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK); 5100 5101 IXGBE_WRITE_FLUSH(hw); 5102 5103 /* Save IXGBE_VTEIMS value to mask. */ 5104 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK; 5105 } 5106 5107 static int 5108 ixgbevf_dev_configure(struct rte_eth_dev *dev) 5109 { 5110 struct rte_eth_conf *conf = &dev->data->dev_conf; 5111 struct ixgbe_adapter *adapter = dev->data->dev_private; 5112 5113 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d", 5114 dev->data->port_id); 5115 5116 /* 5117 * VF has no ability to enable/disable HW CRC 5118 * Keep the persistent behavior the same as Host PF 5119 */ 5120 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC 5121 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) { 5122 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip"); 5123 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC; 5124 } 5125 #else 5126 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) { 5127 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip"); 5128 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC; 5129 } 5130 #endif 5131 5132 /* 5133 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 5134 * allocation or vector Rx preconditions we will reset it. 5135 */ 5136 adapter->rx_bulk_alloc_allowed = true; 5137 adapter->rx_vec_allowed = true; 5138 5139 return 0; 5140 } 5141 5142 static int 5143 ixgbevf_dev_start(struct rte_eth_dev *dev) 5144 { 5145 struct ixgbe_hw *hw = 5146 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5147 uint32_t intr_vector = 0; 5148 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5149 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5150 5151 int err, mask = 0; 5152 5153 PMD_INIT_FUNC_TRACE(); 5154 5155 /* Stop the link setup handler before resetting the HW. */ 5156 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 5157 5158 err = hw->mac.ops.reset_hw(hw); 5159 if (err) { 5160 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err); 5161 return err; 5162 } 5163 hw->mac.get_link_status = true; 5164 5165 /* negotiate mailbox API version to use with the PF. */ 5166 ixgbevf_negotiate_api(hw); 5167 5168 ixgbevf_dev_tx_init(dev); 5169 5170 /* This can fail when allocating mbufs for descriptor rings */ 5171 err = ixgbevf_dev_rx_init(dev); 5172 if (err) { 5173 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err); 5174 ixgbe_dev_clear_queues(dev); 5175 return err; 5176 } 5177 5178 /* Set vfta */ 5179 ixgbevf_set_vfta_all(dev, 1); 5180 5181 /* Set HW strip */ 5182 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 5183 ETH_VLAN_EXTEND_MASK; 5184 err = ixgbevf_vlan_offload_config(dev, mask); 5185 if (err) { 5186 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err); 5187 ixgbe_dev_clear_queues(dev); 5188 return err; 5189 } 5190 5191 ixgbevf_dev_rxtx_start(dev); 5192 5193 /* check and configure queue intr-vector mapping */ 5194 if (rte_intr_cap_multiple(intr_handle) && 5195 dev->data->dev_conf.intr_conf.rxq) { 5196 /* According to datasheet, only vector 0/1/2 can be used, 5197 * now only one vector is used for Rx queue 5198 */ 5199 intr_vector = 1; 5200 if (rte_intr_efd_enable(intr_handle, intr_vector)) 5201 return -1; 5202 } 5203 5204 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 5205 intr_handle->intr_vec = 5206 rte_zmalloc("intr_vec", 5207 dev->data->nb_rx_queues * sizeof(int), 0); 5208 if (intr_handle->intr_vec == NULL) { 5209 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 5210 " intr_vec", dev->data->nb_rx_queues); 5211 return -ENOMEM; 5212 } 5213 } 5214 ixgbevf_configure_msix(dev); 5215 5216 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt 5217 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ). 5218 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( ) 5219 * is not cleared, it will fail when following rte_intr_enable( ) tries 5220 * to map Rx queue interrupt to other VFIO vectors. 5221 * So clear uio/vfio intr/evevnfd first to avoid failure. 5222 */ 5223 rte_intr_disable(intr_handle); 5224 5225 rte_intr_enable(intr_handle); 5226 5227 /* Re-enable interrupt for VF */ 5228 ixgbevf_intr_enable(dev); 5229 5230 /* 5231 * Update link status right before return, because it may 5232 * start link configuration process in a separate thread. 5233 */ 5234 ixgbevf_dev_link_update(dev, 0); 5235 5236 return 0; 5237 } 5238 5239 static void 5240 ixgbevf_dev_stop(struct rte_eth_dev *dev) 5241 { 5242 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5243 struct ixgbe_adapter *adapter = dev->data->dev_private; 5244 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5245 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5246 5247 PMD_INIT_FUNC_TRACE(); 5248 5249 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 5250 5251 ixgbevf_intr_disable(dev); 5252 5253 hw->adapter_stopped = 1; 5254 ixgbe_stop_adapter(hw); 5255 5256 /* 5257 * Clear what we set, but we still keep shadow_vfta to 5258 * restore after device starts 5259 */ 5260 ixgbevf_set_vfta_all(dev, 0); 5261 5262 /* Clear stored conf */ 5263 dev->data->scattered_rx = 0; 5264 5265 ixgbe_dev_clear_queues(dev); 5266 5267 /* Clean datapath event and queue/vec mapping */ 5268 rte_intr_efd_disable(intr_handle); 5269 if (intr_handle->intr_vec != NULL) { 5270 rte_free(intr_handle->intr_vec); 5271 intr_handle->intr_vec = NULL; 5272 } 5273 5274 adapter->rss_reta_updated = 0; 5275 } 5276 5277 static void 5278 ixgbevf_dev_close(struct rte_eth_dev *dev) 5279 { 5280 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5281 5282 PMD_INIT_FUNC_TRACE(); 5283 5284 ixgbe_reset_hw(hw); 5285 5286 ixgbevf_dev_stop(dev); 5287 5288 ixgbe_dev_free_queues(dev); 5289 5290 /** 5291 * Remove the VF MAC address ro ensure 5292 * that the VF traffic goes to the PF 5293 * after stop, close and detach of the VF 5294 **/ 5295 ixgbevf_remove_mac_addr(dev, 0); 5296 } 5297 5298 /* 5299 * Reset VF device 5300 */ 5301 static int 5302 ixgbevf_dev_reset(struct rte_eth_dev *dev) 5303 { 5304 int ret; 5305 5306 ret = eth_ixgbevf_dev_uninit(dev); 5307 if (ret) 5308 return ret; 5309 5310 ret = eth_ixgbevf_dev_init(dev); 5311 5312 return ret; 5313 } 5314 5315 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) 5316 { 5317 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5318 struct ixgbe_vfta *shadow_vfta = 5319 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5320 int i = 0, j = 0, vfta = 0, mask = 1; 5321 5322 for (i = 0; i < IXGBE_VFTA_SIZE; i++) { 5323 vfta = shadow_vfta->vfta[i]; 5324 if (vfta) { 5325 mask = 1; 5326 for (j = 0; j < 32; j++) { 5327 if (vfta & mask) 5328 ixgbe_set_vfta(hw, (i<<5)+j, 0, 5329 on, false); 5330 mask <<= 1; 5331 } 5332 } 5333 } 5334 5335 } 5336 5337 static int 5338 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 5339 { 5340 struct ixgbe_hw *hw = 5341 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5342 struct ixgbe_vfta *shadow_vfta = 5343 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5344 uint32_t vid_idx = 0; 5345 uint32_t vid_bit = 0; 5346 int ret = 0; 5347 5348 PMD_INIT_FUNC_TRACE(); 5349 5350 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */ 5351 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false); 5352 if (ret) { 5353 PMD_INIT_LOG(ERR, "Unable to set VF vlan"); 5354 return ret; 5355 } 5356 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 5357 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 5358 5359 /* Save what we set and retore it after device reset */ 5360 if (on) 5361 shadow_vfta->vfta[vid_idx] |= vid_bit; 5362 else 5363 shadow_vfta->vfta[vid_idx] &= ~vid_bit; 5364 5365 return 0; 5366 } 5367 5368 static void 5369 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 5370 { 5371 struct ixgbe_hw *hw = 5372 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5373 uint32_t ctrl; 5374 5375 PMD_INIT_FUNC_TRACE(); 5376 5377 if (queue >= hw->mac.max_rx_queues) 5378 return; 5379 5380 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 5381 if (on) 5382 ctrl |= IXGBE_RXDCTL_VME; 5383 else 5384 ctrl &= ~IXGBE_RXDCTL_VME; 5385 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 5386 5387 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on); 5388 } 5389 5390 static int 5391 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask) 5392 { 5393 struct ixgbe_rx_queue *rxq; 5394 uint16_t i; 5395 int on = 0; 5396 5397 /* VF function only support hw strip feature, others are not support */ 5398 if (mask & ETH_VLAN_STRIP_MASK) { 5399 for (i = 0; i < dev->data->nb_rx_queues; i++) { 5400 rxq = dev->data->rx_queues[i]; 5401 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP); 5402 ixgbevf_vlan_strip_queue_set(dev, i, on); 5403 } 5404 } 5405 5406 return 0; 5407 } 5408 5409 static int 5410 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 5411 { 5412 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 5413 5414 ixgbevf_vlan_offload_config(dev, mask); 5415 5416 return 0; 5417 } 5418 5419 int 5420 ixgbe_vt_check(struct ixgbe_hw *hw) 5421 { 5422 uint32_t reg_val; 5423 5424 /* if Virtualization Technology is enabled */ 5425 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 5426 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) { 5427 PMD_INIT_LOG(ERR, "VT must be enabled for this setting"); 5428 return -1; 5429 } 5430 5431 return 0; 5432 } 5433 5434 static uint32_t 5435 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr) 5436 { 5437 uint32_t vector = 0; 5438 5439 switch (hw->mac.mc_filter_type) { 5440 case 0: /* use bits [47:36] of the address */ 5441 vector = ((uc_addr->addr_bytes[4] >> 4) | 5442 (((uint16_t)uc_addr->addr_bytes[5]) << 4)); 5443 break; 5444 case 1: /* use bits [46:35] of the address */ 5445 vector = ((uc_addr->addr_bytes[4] >> 3) | 5446 (((uint16_t)uc_addr->addr_bytes[5]) << 5)); 5447 break; 5448 case 2: /* use bits [45:34] of the address */ 5449 vector = ((uc_addr->addr_bytes[4] >> 2) | 5450 (((uint16_t)uc_addr->addr_bytes[5]) << 6)); 5451 break; 5452 case 3: /* use bits [43:32] of the address */ 5453 vector = ((uc_addr->addr_bytes[4]) | 5454 (((uint16_t)uc_addr->addr_bytes[5]) << 8)); 5455 break; 5456 default: /* Invalid mc_filter_type */ 5457 break; 5458 } 5459 5460 /* vector can only be 12-bits or boundary will be exceeded */ 5461 vector &= 0xFFF; 5462 return vector; 5463 } 5464 5465 static int 5466 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, 5467 struct rte_ether_addr *mac_addr, uint8_t on) 5468 { 5469 uint32_t vector; 5470 uint32_t uta_idx; 5471 uint32_t reg_val; 5472 uint32_t uta_shift; 5473 uint32_t rc; 5474 const uint32_t ixgbe_uta_idx_mask = 0x7F; 5475 const uint32_t ixgbe_uta_bit_shift = 5; 5476 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1; 5477 const uint32_t bit1 = 0x1; 5478 5479 struct ixgbe_hw *hw = 5480 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5481 struct ixgbe_uta_info *uta_info = 5482 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5483 5484 /* The UTA table only exists on 82599 hardware and newer */ 5485 if (hw->mac.type < ixgbe_mac_82599EB) 5486 return -ENOTSUP; 5487 5488 vector = ixgbe_uta_vector(hw, mac_addr); 5489 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask; 5490 uta_shift = vector & ixgbe_uta_bit_mask; 5491 5492 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0); 5493 if (rc == on) 5494 return 0; 5495 5496 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx)); 5497 if (on) { 5498 uta_info->uta_in_use++; 5499 reg_val |= (bit1 << uta_shift); 5500 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift); 5501 } else { 5502 uta_info->uta_in_use--; 5503 reg_val &= ~(bit1 << uta_shift); 5504 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift); 5505 } 5506 5507 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val); 5508 5509 if (uta_info->uta_in_use > 0) 5510 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 5511 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 5512 else 5513 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 5514 5515 return 0; 5516 } 5517 5518 static int 5519 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) 5520 { 5521 int i; 5522 struct ixgbe_hw *hw = 5523 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5524 struct ixgbe_uta_info *uta_info = 5525 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5526 5527 /* The UTA table only exists on 82599 hardware and newer */ 5528 if (hw->mac.type < ixgbe_mac_82599EB) 5529 return -ENOTSUP; 5530 5531 if (on) { 5532 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5533 uta_info->uta_shadow[i] = ~0; 5534 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); 5535 } 5536 } else { 5537 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5538 uta_info->uta_shadow[i] = 0; 5539 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 5540 } 5541 } 5542 return 0; 5543 5544 } 5545 5546 uint32_t 5547 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val) 5548 { 5549 uint32_t new_val = orig_val; 5550 5551 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG) 5552 new_val |= IXGBE_VMOLR_AUPE; 5553 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC) 5554 new_val |= IXGBE_VMOLR_ROMPE; 5555 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC) 5556 new_val |= IXGBE_VMOLR_ROPE; 5557 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST) 5558 new_val |= IXGBE_VMOLR_BAM; 5559 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST) 5560 new_val |= IXGBE_VMOLR_MPE; 5561 5562 return new_val; 5563 } 5564 5565 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */ 5566 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */ 5567 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */ 5568 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */ 5569 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \ 5570 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \ 5571 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN)) 5572 5573 static int 5574 ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 5575 struct rte_eth_mirror_conf *mirror_conf, 5576 uint8_t rule_id, uint8_t on) 5577 { 5578 uint32_t mr_ctl, vlvf; 5579 uint32_t mp_lsb = 0; 5580 uint32_t mv_msb = 0; 5581 uint32_t mv_lsb = 0; 5582 uint32_t mp_msb = 0; 5583 uint8_t i = 0; 5584 int reg_index = 0; 5585 uint64_t vlan_mask = 0; 5586 5587 const uint8_t pool_mask_offset = 32; 5588 const uint8_t vlan_mask_offset = 32; 5589 const uint8_t dst_pool_offset = 8; 5590 const uint8_t rule_mr_offset = 4; 5591 const uint8_t mirror_rule_mask = 0x0F; 5592 5593 struct ixgbe_mirror_info *mr_info = 5594 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5595 struct ixgbe_hw *hw = 5596 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5597 uint8_t mirror_type = 0; 5598 5599 if (ixgbe_vt_check(hw) < 0) 5600 return -ENOTSUP; 5601 5602 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5603 return -EINVAL; 5604 5605 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) { 5606 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.", 5607 mirror_conf->rule_type); 5608 return -EINVAL; 5609 } 5610 5611 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5612 mirror_type |= IXGBE_MRCTL_VLME; 5613 /* Check if vlan id is valid and find conresponding VLAN ID 5614 * index in VLVF 5615 */ 5616 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) { 5617 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) { 5618 /* search vlan id related pool vlan filter 5619 * index 5620 */ 5621 reg_index = ixgbe_find_vlvf_slot( 5622 hw, 5623 mirror_conf->vlan.vlan_id[i], 5624 false); 5625 if (reg_index < 0) 5626 return -EINVAL; 5627 vlvf = IXGBE_READ_REG(hw, 5628 IXGBE_VLVF(reg_index)); 5629 if ((vlvf & IXGBE_VLVF_VIEN) && 5630 ((vlvf & IXGBE_VLVF_VLANID_MASK) == 5631 mirror_conf->vlan.vlan_id[i])) 5632 vlan_mask |= (1ULL << reg_index); 5633 else 5634 return -EINVAL; 5635 } 5636 } 5637 5638 if (on) { 5639 mv_lsb = vlan_mask & 0xFFFFFFFF; 5640 mv_msb = vlan_mask >> vlan_mask_offset; 5641 5642 mr_info->mr_conf[rule_id].vlan.vlan_mask = 5643 mirror_conf->vlan.vlan_mask; 5644 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) { 5645 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) 5646 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 5647 mirror_conf->vlan.vlan_id[i]; 5648 } 5649 } else { 5650 mv_lsb = 0; 5651 mv_msb = 0; 5652 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0; 5653 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) 5654 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0; 5655 } 5656 } 5657 5658 /** 5659 * if enable pool mirror, write related pool mask register,if disable 5660 * pool mirror, clear PFMRVM register 5661 */ 5662 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5663 mirror_type |= IXGBE_MRCTL_VPME; 5664 if (on) { 5665 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF; 5666 mp_msb = mirror_conf->pool_mask >> pool_mask_offset; 5667 mr_info->mr_conf[rule_id].pool_mask = 5668 mirror_conf->pool_mask; 5669 5670 } else { 5671 mp_lsb = 0; 5672 mp_msb = 0; 5673 mr_info->mr_conf[rule_id].pool_mask = 0; 5674 } 5675 } 5676 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT) 5677 mirror_type |= IXGBE_MRCTL_UPME; 5678 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT) 5679 mirror_type |= IXGBE_MRCTL_DPME; 5680 5681 /* read mirror control register and recalculate it */ 5682 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id)); 5683 5684 if (on) { 5685 mr_ctl |= mirror_type; 5686 mr_ctl &= mirror_rule_mask; 5687 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset; 5688 } else { 5689 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask); 5690 } 5691 5692 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type; 5693 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool; 5694 5695 /* write mirrror control register */ 5696 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5697 5698 /* write pool mirrror control register */ 5699 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5700 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb); 5701 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), 5702 mp_msb); 5703 } 5704 /* write VLAN mirrror control register */ 5705 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5706 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb); 5707 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), 5708 mv_msb); 5709 } 5710 5711 return 0; 5712 } 5713 5714 static int 5715 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id) 5716 { 5717 int mr_ctl = 0; 5718 uint32_t lsb_val = 0; 5719 uint32_t msb_val = 0; 5720 const uint8_t rule_mr_offset = 4; 5721 5722 struct ixgbe_hw *hw = 5723 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5724 struct ixgbe_mirror_info *mr_info = 5725 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5726 5727 if (ixgbe_vt_check(hw) < 0) 5728 return -ENOTSUP; 5729 5730 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5731 return -EINVAL; 5732 5733 memset(&mr_info->mr_conf[rule_id], 0, 5734 sizeof(struct rte_eth_mirror_conf)); 5735 5736 /* clear PFVMCTL register */ 5737 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5738 5739 /* clear pool mask register */ 5740 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val); 5741 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val); 5742 5743 /* clear vlan mask register */ 5744 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val); 5745 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val); 5746 5747 return 0; 5748 } 5749 5750 static int 5751 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5752 { 5753 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5754 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5755 struct ixgbe_interrupt *intr = 5756 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5757 struct ixgbe_hw *hw = 5758 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5759 uint32_t vec = IXGBE_MISC_VEC_ID; 5760 5761 if (rte_intr_allow_others(intr_handle)) 5762 vec = IXGBE_RX_VEC_START; 5763 intr->mask |= (1 << vec); 5764 RTE_SET_USED(queue_id); 5765 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5766 5767 rte_intr_ack(intr_handle); 5768 5769 return 0; 5770 } 5771 5772 static int 5773 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5774 { 5775 struct ixgbe_interrupt *intr = 5776 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5777 struct ixgbe_hw *hw = 5778 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5779 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5780 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5781 uint32_t vec = IXGBE_MISC_VEC_ID; 5782 5783 if (rte_intr_allow_others(intr_handle)) 5784 vec = IXGBE_RX_VEC_START; 5785 intr->mask &= ~(1 << vec); 5786 RTE_SET_USED(queue_id); 5787 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5788 5789 return 0; 5790 } 5791 5792 static int 5793 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5794 { 5795 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5796 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5797 uint32_t mask; 5798 struct ixgbe_hw *hw = 5799 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5800 struct ixgbe_interrupt *intr = 5801 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5802 5803 if (queue_id < 16) { 5804 ixgbe_disable_intr(hw); 5805 intr->mask |= (1 << queue_id); 5806 ixgbe_enable_intr(dev); 5807 } else if (queue_id < 32) { 5808 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5809 mask &= (1 << queue_id); 5810 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5811 } else if (queue_id < 64) { 5812 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5813 mask &= (1 << (queue_id - 32)); 5814 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5815 } 5816 rte_intr_ack(intr_handle); 5817 5818 return 0; 5819 } 5820 5821 static int 5822 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5823 { 5824 uint32_t mask; 5825 struct ixgbe_hw *hw = 5826 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5827 struct ixgbe_interrupt *intr = 5828 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5829 5830 if (queue_id < 16) { 5831 ixgbe_disable_intr(hw); 5832 intr->mask &= ~(1 << queue_id); 5833 ixgbe_enable_intr(dev); 5834 } else if (queue_id < 32) { 5835 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5836 mask &= ~(1 << queue_id); 5837 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5838 } else if (queue_id < 64) { 5839 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5840 mask &= ~(1 << (queue_id - 32)); 5841 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5842 } 5843 5844 return 0; 5845 } 5846 5847 static void 5848 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 5849 uint8_t queue, uint8_t msix_vector) 5850 { 5851 uint32_t tmp, idx; 5852 5853 if (direction == -1) { 5854 /* other causes */ 5855 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5856 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC); 5857 tmp &= ~0xFF; 5858 tmp |= msix_vector; 5859 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp); 5860 } else { 5861 /* rx or tx cause */ 5862 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5863 idx = ((16 * (queue & 1)) + (8 * direction)); 5864 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1)); 5865 tmp &= ~(0xFF << idx); 5866 tmp |= (msix_vector << idx); 5867 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp); 5868 } 5869 } 5870 5871 /** 5872 * set the IVAR registers, mapping interrupt causes to vectors 5873 * @param hw 5874 * pointer to ixgbe_hw struct 5875 * @direction 5876 * 0 for Rx, 1 for Tx, -1 for other causes 5877 * @queue 5878 * queue to map the corresponding interrupt to 5879 * @msix_vector 5880 * the vector to map to the corresponding queue 5881 */ 5882 static void 5883 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 5884 uint8_t queue, uint8_t msix_vector) 5885 { 5886 uint32_t tmp, idx; 5887 5888 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5889 if (hw->mac.type == ixgbe_mac_82598EB) { 5890 if (direction == -1) 5891 direction = 0; 5892 idx = (((direction * 64) + queue) >> 2) & 0x1F; 5893 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx)); 5894 tmp &= ~(0xFF << (8 * (queue & 0x3))); 5895 tmp |= (msix_vector << (8 * (queue & 0x3))); 5896 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp); 5897 } else if ((hw->mac.type == ixgbe_mac_82599EB) || 5898 (hw->mac.type == ixgbe_mac_X540) || 5899 (hw->mac.type == ixgbe_mac_X550) || 5900 (hw->mac.type == ixgbe_mac_X550EM_x)) { 5901 if (direction == -1) { 5902 /* other causes */ 5903 idx = ((queue & 1) * 8); 5904 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC); 5905 tmp &= ~(0xFF << idx); 5906 tmp |= (msix_vector << idx); 5907 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp); 5908 } else { 5909 /* rx or tx causes */ 5910 idx = ((16 * (queue & 1)) + (8 * direction)); 5911 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 5912 tmp &= ~(0xFF << idx); 5913 tmp |= (msix_vector << idx); 5914 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp); 5915 } 5916 } 5917 } 5918 5919 static void 5920 ixgbevf_configure_msix(struct rte_eth_dev *dev) 5921 { 5922 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5923 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5924 struct ixgbe_hw *hw = 5925 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5926 uint32_t q_idx; 5927 uint32_t vector_idx = IXGBE_MISC_VEC_ID; 5928 uint32_t base = IXGBE_MISC_VEC_ID; 5929 5930 /* Configure VF other cause ivar */ 5931 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx); 5932 5933 /* won't configure msix register if no mapping is done 5934 * between intr vector and event fd. 5935 */ 5936 if (!rte_intr_dp_is_en(intr_handle)) 5937 return; 5938 5939 if (rte_intr_allow_others(intr_handle)) { 5940 base = IXGBE_RX_VEC_START; 5941 vector_idx = IXGBE_RX_VEC_START; 5942 } 5943 5944 /* Configure all RX queues of VF */ 5945 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) { 5946 /* Force all queue use vector 0, 5947 * as IXGBE_VF_MAXMSIVECOTR = 1 5948 */ 5949 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx); 5950 intr_handle->intr_vec[q_idx] = vector_idx; 5951 if (vector_idx < base + intr_handle->nb_efd - 1) 5952 vector_idx++; 5953 } 5954 5955 /* As RX queue setting above show, all queues use the vector 0. 5956 * Set only the ITR value of IXGBE_MISC_VEC_ID. 5957 */ 5958 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID), 5959 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 5960 | IXGBE_EITR_CNT_WDIS); 5961 } 5962 5963 /** 5964 * Sets up the hardware to properly generate MSI-X interrupts 5965 * @hw 5966 * board private structure 5967 */ 5968 static void 5969 ixgbe_configure_msix(struct rte_eth_dev *dev) 5970 { 5971 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5972 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5973 struct ixgbe_hw *hw = 5974 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5975 uint32_t queue_id, base = IXGBE_MISC_VEC_ID; 5976 uint32_t vec = IXGBE_MISC_VEC_ID; 5977 uint32_t mask; 5978 uint32_t gpie; 5979 5980 /* won't configure msix register if no mapping is done 5981 * between intr vector and event fd 5982 * but if misx has been enabled already, need to configure 5983 * auto clean, auto mask and throttling. 5984 */ 5985 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 5986 if (!rte_intr_dp_is_en(intr_handle) && 5987 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT))) 5988 return; 5989 5990 if (rte_intr_allow_others(intr_handle)) 5991 vec = base = IXGBE_RX_VEC_START; 5992 5993 /* setup GPIE for MSI-x mode */ 5994 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 5995 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5996 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME; 5997 /* auto clearing and auto setting corresponding bits in EIMS 5998 * when MSI-X interrupt is triggered 5999 */ 6000 if (hw->mac.type == ixgbe_mac_82598EB) { 6001 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 6002 } else { 6003 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 6004 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 6005 } 6006 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 6007 6008 /* Populate the IVAR table and set the ITR values to the 6009 * corresponding register. 6010 */ 6011 if (rte_intr_dp_is_en(intr_handle)) { 6012 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; 6013 queue_id++) { 6014 /* by default, 1:1 mapping */ 6015 ixgbe_set_ivar_map(hw, 0, queue_id, vec); 6016 intr_handle->intr_vec[queue_id] = vec; 6017 if (vec < base + intr_handle->nb_efd - 1) 6018 vec++; 6019 } 6020 6021 switch (hw->mac.type) { 6022 case ixgbe_mac_82598EB: 6023 ixgbe_set_ivar_map(hw, -1, 6024 IXGBE_IVAR_OTHER_CAUSES_INDEX, 6025 IXGBE_MISC_VEC_ID); 6026 break; 6027 case ixgbe_mac_82599EB: 6028 case ixgbe_mac_X540: 6029 case ixgbe_mac_X550: 6030 case ixgbe_mac_X550EM_x: 6031 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID); 6032 break; 6033 default: 6034 break; 6035 } 6036 } 6037 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID), 6038 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 6039 | IXGBE_EITR_CNT_WDIS); 6040 6041 /* set up to autoclear timer, and the vectors */ 6042 mask = IXGBE_EIMS_ENABLE_MASK; 6043 mask &= ~(IXGBE_EIMS_OTHER | 6044 IXGBE_EIMS_MAILBOX | 6045 IXGBE_EIMS_LSC); 6046 6047 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask); 6048 } 6049 6050 int 6051 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, 6052 uint16_t queue_idx, uint16_t tx_rate) 6053 { 6054 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6055 struct rte_eth_rxmode *rxmode; 6056 uint32_t rf_dec, rf_int; 6057 uint32_t bcnrc_val; 6058 uint16_t link_speed = dev->data->dev_link.link_speed; 6059 6060 if (queue_idx >= hw->mac.max_tx_queues) 6061 return -EINVAL; 6062 6063 if (tx_rate != 0) { 6064 /* Calculate the rate factor values to set */ 6065 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate; 6066 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate; 6067 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate; 6068 6069 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA; 6070 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) & 6071 IXGBE_RTTBCNRC_RF_INT_MASK_M); 6072 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK); 6073 } else { 6074 bcnrc_val = 0; 6075 } 6076 6077 rxmode = &dev->data->dev_conf.rxmode; 6078 /* 6079 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 6080 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise 6081 * set as 0x4. 6082 */ 6083 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) && 6084 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE)) 6085 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 6086 IXGBE_MMW_SIZE_JUMBO_FRAME); 6087 else 6088 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 6089 IXGBE_MMW_SIZE_DEFAULT); 6090 6091 /* Set RTTBCNRC of queue X */ 6092 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx); 6093 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 6094 IXGBE_WRITE_FLUSH(hw); 6095 6096 return 0; 6097 } 6098 6099 static int 6100 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 6101 __attribute__((unused)) uint32_t index, 6102 __attribute__((unused)) uint32_t pool) 6103 { 6104 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6105 int diag; 6106 6107 /* 6108 * On a 82599 VF, adding again the same MAC addr is not an idempotent 6109 * operation. Trap this case to avoid exhausting the [very limited] 6110 * set of PF resources used to store VF MAC addresses. 6111 */ 6112 if (memcmp(hw->mac.perm_addr, mac_addr, 6113 sizeof(struct rte_ether_addr)) == 0) 6114 return -1; 6115 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6116 if (diag != 0) 6117 PMD_DRV_LOG(ERR, "Unable to add MAC address " 6118 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d", 6119 mac_addr->addr_bytes[0], 6120 mac_addr->addr_bytes[1], 6121 mac_addr->addr_bytes[2], 6122 mac_addr->addr_bytes[3], 6123 mac_addr->addr_bytes[4], 6124 mac_addr->addr_bytes[5], 6125 diag); 6126 return diag; 6127 } 6128 6129 static void 6130 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index) 6131 { 6132 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6133 struct rte_ether_addr *perm_addr = 6134 (struct rte_ether_addr *)hw->mac.perm_addr; 6135 struct rte_ether_addr *mac_addr; 6136 uint32_t i; 6137 int diag; 6138 6139 /* 6140 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does 6141 * not support the deletion of a given MAC address. 6142 * Instead, it imposes to delete all MAC addresses, then to add again 6143 * all MAC addresses with the exception of the one to be deleted. 6144 */ 6145 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL); 6146 6147 /* 6148 * Add again all MAC addresses, with the exception of the deleted one 6149 * and of the permanent MAC address. 6150 */ 6151 for (i = 0, mac_addr = dev->data->mac_addrs; 6152 i < hw->mac.num_rar_entries; i++, mac_addr++) { 6153 /* Skip the deleted MAC address */ 6154 if (i == index) 6155 continue; 6156 /* Skip NULL MAC addresses */ 6157 if (rte_is_zero_ether_addr(mac_addr)) 6158 continue; 6159 /* Skip the permanent MAC address */ 6160 if (memcmp(perm_addr, mac_addr, 6161 sizeof(struct rte_ether_addr)) == 0) 6162 continue; 6163 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6164 if (diag != 0) 6165 PMD_DRV_LOG(ERR, 6166 "Adding again MAC address " 6167 "%02x:%02x:%02x:%02x:%02x:%02x failed " 6168 "diag=%d", 6169 mac_addr->addr_bytes[0], 6170 mac_addr->addr_bytes[1], 6171 mac_addr->addr_bytes[2], 6172 mac_addr->addr_bytes[3], 6173 mac_addr->addr_bytes[4], 6174 mac_addr->addr_bytes[5], 6175 diag); 6176 } 6177 } 6178 6179 static int 6180 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 6181 struct rte_ether_addr *addr) 6182 { 6183 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6184 6185 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0); 6186 6187 return 0; 6188 } 6189 6190 int 6191 ixgbe_syn_filter_set(struct rte_eth_dev *dev, 6192 struct rte_eth_syn_filter *filter, 6193 bool add) 6194 { 6195 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6196 struct ixgbe_filter_info *filter_info = 6197 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6198 uint32_t syn_info; 6199 uint32_t synqf; 6200 6201 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6202 return -EINVAL; 6203 6204 syn_info = filter_info->syn_info; 6205 6206 if (add) { 6207 if (syn_info & IXGBE_SYN_FILTER_ENABLE) 6208 return -EINVAL; 6209 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) & 6210 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE); 6211 6212 if (filter->hig_pri) 6213 synqf |= IXGBE_SYN_FILTER_SYNQFP; 6214 else 6215 synqf &= ~IXGBE_SYN_FILTER_SYNQFP; 6216 } else { 6217 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6218 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE)) 6219 return -ENOENT; 6220 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE); 6221 } 6222 6223 filter_info->syn_info = synqf; 6224 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 6225 IXGBE_WRITE_FLUSH(hw); 6226 return 0; 6227 } 6228 6229 static int 6230 ixgbe_syn_filter_get(struct rte_eth_dev *dev, 6231 struct rte_eth_syn_filter *filter) 6232 { 6233 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6234 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6235 6236 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 6237 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0; 6238 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1); 6239 return 0; 6240 } 6241 return -ENOENT; 6242 } 6243 6244 static int 6245 ixgbe_syn_filter_handle(struct rte_eth_dev *dev, 6246 enum rte_filter_op filter_op, 6247 void *arg) 6248 { 6249 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6250 int ret; 6251 6252 MAC_TYPE_FILTER_SUP(hw->mac.type); 6253 6254 if (filter_op == RTE_ETH_FILTER_NOP) 6255 return 0; 6256 6257 if (arg == NULL) { 6258 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u", 6259 filter_op); 6260 return -EINVAL; 6261 } 6262 6263 switch (filter_op) { 6264 case RTE_ETH_FILTER_ADD: 6265 ret = ixgbe_syn_filter_set(dev, 6266 (struct rte_eth_syn_filter *)arg, 6267 TRUE); 6268 break; 6269 case RTE_ETH_FILTER_DELETE: 6270 ret = ixgbe_syn_filter_set(dev, 6271 (struct rte_eth_syn_filter *)arg, 6272 FALSE); 6273 break; 6274 case RTE_ETH_FILTER_GET: 6275 ret = ixgbe_syn_filter_get(dev, 6276 (struct rte_eth_syn_filter *)arg); 6277 break; 6278 default: 6279 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op); 6280 ret = -EINVAL; 6281 break; 6282 } 6283 6284 return ret; 6285 } 6286 6287 6288 static inline enum ixgbe_5tuple_protocol 6289 convert_protocol_type(uint8_t protocol_value) 6290 { 6291 if (protocol_value == IPPROTO_TCP) 6292 return IXGBE_FILTER_PROTOCOL_TCP; 6293 else if (protocol_value == IPPROTO_UDP) 6294 return IXGBE_FILTER_PROTOCOL_UDP; 6295 else if (protocol_value == IPPROTO_SCTP) 6296 return IXGBE_FILTER_PROTOCOL_SCTP; 6297 else 6298 return IXGBE_FILTER_PROTOCOL_NONE; 6299 } 6300 6301 /* inject a 5-tuple filter to HW */ 6302 static inline void 6303 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev, 6304 struct ixgbe_5tuple_filter *filter) 6305 { 6306 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6307 int i; 6308 uint32_t ftqf, sdpqf; 6309 uint32_t l34timir = 0; 6310 uint8_t mask = 0xff; 6311 6312 i = filter->index; 6313 6314 sdpqf = (uint32_t)(filter->filter_info.dst_port << 6315 IXGBE_SDPQF_DSTPORT_SHIFT); 6316 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT); 6317 6318 ftqf = (uint32_t)(filter->filter_info.proto & 6319 IXGBE_FTQF_PROTOCOL_MASK); 6320 ftqf |= (uint32_t)((filter->filter_info.priority & 6321 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT); 6322 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */ 6323 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK; 6324 if (filter->filter_info.dst_ip_mask == 0) 6325 mask &= IXGBE_FTQF_DEST_ADDR_MASK; 6326 if (filter->filter_info.src_port_mask == 0) 6327 mask &= IXGBE_FTQF_SOURCE_PORT_MASK; 6328 if (filter->filter_info.dst_port_mask == 0) 6329 mask &= IXGBE_FTQF_DEST_PORT_MASK; 6330 if (filter->filter_info.proto_mask == 0) 6331 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK; 6332 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT; 6333 ftqf |= IXGBE_FTQF_POOL_MASK_EN; 6334 ftqf |= IXGBE_FTQF_QUEUE_ENABLE; 6335 6336 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip); 6337 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip); 6338 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf); 6339 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf); 6340 6341 l34timir |= IXGBE_L34T_IMIR_RESERVE; 6342 l34timir |= (uint32_t)(filter->queue << 6343 IXGBE_L34T_IMIR_QUEUE_SHIFT); 6344 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir); 6345 } 6346 6347 /* 6348 * add a 5tuple filter 6349 * 6350 * @param 6351 * dev: Pointer to struct rte_eth_dev. 6352 * index: the index the filter allocates. 6353 * filter: ponter to the filter that will be added. 6354 * rx_queue: the queue id the filter assigned to. 6355 * 6356 * @return 6357 * - On success, zero. 6358 * - On failure, a negative value. 6359 */ 6360 static int 6361 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 6362 struct ixgbe_5tuple_filter *filter) 6363 { 6364 struct ixgbe_filter_info *filter_info = 6365 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6366 int i, idx, shift; 6367 6368 /* 6369 * look for an unused 5tuple filter index, 6370 * and insert the filter to list. 6371 */ 6372 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) { 6373 idx = i / (sizeof(uint32_t) * NBBY); 6374 shift = i % (sizeof(uint32_t) * NBBY); 6375 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) { 6376 filter_info->fivetuple_mask[idx] |= 1 << shift; 6377 filter->index = i; 6378 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list, 6379 filter, 6380 entries); 6381 break; 6382 } 6383 } 6384 if (i >= IXGBE_MAX_FTQF_FILTERS) { 6385 PMD_DRV_LOG(ERR, "5tuple filters are full."); 6386 return -ENOSYS; 6387 } 6388 6389 ixgbe_inject_5tuple_filter(dev, filter); 6390 6391 return 0; 6392 } 6393 6394 /* 6395 * remove a 5tuple filter 6396 * 6397 * @param 6398 * dev: Pointer to struct rte_eth_dev. 6399 * filter: the pointer of the filter will be removed. 6400 */ 6401 static void 6402 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 6403 struct ixgbe_5tuple_filter *filter) 6404 { 6405 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6406 struct ixgbe_filter_info *filter_info = 6407 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6408 uint16_t index = filter->index; 6409 6410 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &= 6411 ~(1 << (index % (sizeof(uint32_t) * NBBY))); 6412 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries); 6413 rte_free(filter); 6414 6415 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0); 6416 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0); 6417 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0); 6418 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0); 6419 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0); 6420 } 6421 6422 static int 6423 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 6424 { 6425 struct ixgbe_hw *hw; 6426 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD; 6427 struct rte_eth_dev_data *dev_data = dev->data; 6428 6429 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6430 6431 if (mtu < RTE_ETHER_MIN_MTU || 6432 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN) 6433 return -EINVAL; 6434 6435 /* If device is started, refuse mtu that requires the support of 6436 * scattered packets when this feature has not been enabled before. 6437 */ 6438 if (dev_data->dev_started && !dev_data->scattered_rx && 6439 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE > 6440 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 6441 PMD_INIT_LOG(ERR, "Stop port first."); 6442 return -EINVAL; 6443 } 6444 6445 /* 6446 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU 6447 * request of the version 2.0 of the mailbox API. 6448 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0 6449 * of the mailbox API. 6450 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers 6451 * prior to 3.11.33 which contains the following change: 6452 * "ixgbe: Enable jumbo frames support w/ SR-IOV" 6453 */ 6454 ixgbevf_rlpml_set_vf(hw, max_frame); 6455 6456 /* update max frame size */ 6457 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame; 6458 return 0; 6459 } 6460 6461 static inline struct ixgbe_5tuple_filter * 6462 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list, 6463 struct ixgbe_5tuple_filter_info *key) 6464 { 6465 struct ixgbe_5tuple_filter *it; 6466 6467 TAILQ_FOREACH(it, filter_list, entries) { 6468 if (memcmp(key, &it->filter_info, 6469 sizeof(struct ixgbe_5tuple_filter_info)) == 0) { 6470 return it; 6471 } 6472 } 6473 return NULL; 6474 } 6475 6476 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/ 6477 static inline int 6478 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter, 6479 struct ixgbe_5tuple_filter_info *filter_info) 6480 { 6481 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM || 6482 filter->priority > IXGBE_5TUPLE_MAX_PRI || 6483 filter->priority < IXGBE_5TUPLE_MIN_PRI) 6484 return -EINVAL; 6485 6486 switch (filter->dst_ip_mask) { 6487 case UINT32_MAX: 6488 filter_info->dst_ip_mask = 0; 6489 filter_info->dst_ip = filter->dst_ip; 6490 break; 6491 case 0: 6492 filter_info->dst_ip_mask = 1; 6493 break; 6494 default: 6495 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 6496 return -EINVAL; 6497 } 6498 6499 switch (filter->src_ip_mask) { 6500 case UINT32_MAX: 6501 filter_info->src_ip_mask = 0; 6502 filter_info->src_ip = filter->src_ip; 6503 break; 6504 case 0: 6505 filter_info->src_ip_mask = 1; 6506 break; 6507 default: 6508 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 6509 return -EINVAL; 6510 } 6511 6512 switch (filter->dst_port_mask) { 6513 case UINT16_MAX: 6514 filter_info->dst_port_mask = 0; 6515 filter_info->dst_port = filter->dst_port; 6516 break; 6517 case 0: 6518 filter_info->dst_port_mask = 1; 6519 break; 6520 default: 6521 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 6522 return -EINVAL; 6523 } 6524 6525 switch (filter->src_port_mask) { 6526 case UINT16_MAX: 6527 filter_info->src_port_mask = 0; 6528 filter_info->src_port = filter->src_port; 6529 break; 6530 case 0: 6531 filter_info->src_port_mask = 1; 6532 break; 6533 default: 6534 PMD_DRV_LOG(ERR, "invalid src_port mask."); 6535 return -EINVAL; 6536 } 6537 6538 switch (filter->proto_mask) { 6539 case UINT8_MAX: 6540 filter_info->proto_mask = 0; 6541 filter_info->proto = 6542 convert_protocol_type(filter->proto); 6543 break; 6544 case 0: 6545 filter_info->proto_mask = 1; 6546 break; 6547 default: 6548 PMD_DRV_LOG(ERR, "invalid protocol mask."); 6549 return -EINVAL; 6550 } 6551 6552 filter_info->priority = (uint8_t)filter->priority; 6553 return 0; 6554 } 6555 6556 /* 6557 * add or delete a ntuple filter 6558 * 6559 * @param 6560 * dev: Pointer to struct rte_eth_dev. 6561 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6562 * add: if true, add filter, if false, remove filter 6563 * 6564 * @return 6565 * - On success, zero. 6566 * - On failure, a negative value. 6567 */ 6568 int 6569 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 6570 struct rte_eth_ntuple_filter *ntuple_filter, 6571 bool add) 6572 { 6573 struct ixgbe_filter_info *filter_info = 6574 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6575 struct ixgbe_5tuple_filter_info filter_5tuple; 6576 struct ixgbe_5tuple_filter *filter; 6577 int ret; 6578 6579 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6580 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6581 return -EINVAL; 6582 } 6583 6584 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6585 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6586 if (ret < 0) 6587 return ret; 6588 6589 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6590 &filter_5tuple); 6591 if (filter != NULL && add) { 6592 PMD_DRV_LOG(ERR, "filter exists."); 6593 return -EEXIST; 6594 } 6595 if (filter == NULL && !add) { 6596 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6597 return -ENOENT; 6598 } 6599 6600 if (add) { 6601 filter = rte_zmalloc("ixgbe_5tuple_filter", 6602 sizeof(struct ixgbe_5tuple_filter), 0); 6603 if (filter == NULL) 6604 return -ENOMEM; 6605 rte_memcpy(&filter->filter_info, 6606 &filter_5tuple, 6607 sizeof(struct ixgbe_5tuple_filter_info)); 6608 filter->queue = ntuple_filter->queue; 6609 ret = ixgbe_add_5tuple_filter(dev, filter); 6610 if (ret < 0) { 6611 rte_free(filter); 6612 return ret; 6613 } 6614 } else 6615 ixgbe_remove_5tuple_filter(dev, filter); 6616 6617 return 0; 6618 } 6619 6620 /* 6621 * get a ntuple filter 6622 * 6623 * @param 6624 * dev: Pointer to struct rte_eth_dev. 6625 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6626 * 6627 * @return 6628 * - On success, zero. 6629 * - On failure, a negative value. 6630 */ 6631 static int 6632 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev, 6633 struct rte_eth_ntuple_filter *ntuple_filter) 6634 { 6635 struct ixgbe_filter_info *filter_info = 6636 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6637 struct ixgbe_5tuple_filter_info filter_5tuple; 6638 struct ixgbe_5tuple_filter *filter; 6639 int ret; 6640 6641 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6642 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6643 return -EINVAL; 6644 } 6645 6646 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6647 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6648 if (ret < 0) 6649 return ret; 6650 6651 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6652 &filter_5tuple); 6653 if (filter == NULL) { 6654 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6655 return -ENOENT; 6656 } 6657 ntuple_filter->queue = filter->queue; 6658 return 0; 6659 } 6660 6661 /* 6662 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter. 6663 * @dev: pointer to rte_eth_dev structure 6664 * @filter_op:operation will be taken. 6665 * @arg: a pointer to specific structure corresponding to the filter_op 6666 * 6667 * @return 6668 * - On success, zero. 6669 * - On failure, a negative value. 6670 */ 6671 static int 6672 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev, 6673 enum rte_filter_op filter_op, 6674 void *arg) 6675 { 6676 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6677 int ret; 6678 6679 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type); 6680 6681 if (filter_op == RTE_ETH_FILTER_NOP) 6682 return 0; 6683 6684 if (arg == NULL) { 6685 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 6686 filter_op); 6687 return -EINVAL; 6688 } 6689 6690 switch (filter_op) { 6691 case RTE_ETH_FILTER_ADD: 6692 ret = ixgbe_add_del_ntuple_filter(dev, 6693 (struct rte_eth_ntuple_filter *)arg, 6694 TRUE); 6695 break; 6696 case RTE_ETH_FILTER_DELETE: 6697 ret = ixgbe_add_del_ntuple_filter(dev, 6698 (struct rte_eth_ntuple_filter *)arg, 6699 FALSE); 6700 break; 6701 case RTE_ETH_FILTER_GET: 6702 ret = ixgbe_get_ntuple_filter(dev, 6703 (struct rte_eth_ntuple_filter *)arg); 6704 break; 6705 default: 6706 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 6707 ret = -EINVAL; 6708 break; 6709 } 6710 return ret; 6711 } 6712 6713 int 6714 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 6715 struct rte_eth_ethertype_filter *filter, 6716 bool add) 6717 { 6718 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6719 struct ixgbe_filter_info *filter_info = 6720 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6721 uint32_t etqf = 0; 6722 uint32_t etqs = 0; 6723 int ret; 6724 struct ixgbe_ethertype_filter ethertype_filter; 6725 6726 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6727 return -EINVAL; 6728 6729 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 || 6730 filter->ether_type == RTE_ETHER_TYPE_IPV6) { 6731 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in" 6732 " ethertype filter.", filter->ether_type); 6733 return -EINVAL; 6734 } 6735 6736 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) { 6737 PMD_DRV_LOG(ERR, "mac compare is unsupported."); 6738 return -EINVAL; 6739 } 6740 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) { 6741 PMD_DRV_LOG(ERR, "drop option is unsupported."); 6742 return -EINVAL; 6743 } 6744 6745 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6746 if (ret >= 0 && add) { 6747 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.", 6748 filter->ether_type); 6749 return -EEXIST; 6750 } 6751 if (ret < 0 && !add) { 6752 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6753 filter->ether_type); 6754 return -ENOENT; 6755 } 6756 6757 if (add) { 6758 etqf = IXGBE_ETQF_FILTER_EN; 6759 etqf |= (uint32_t)filter->ether_type; 6760 etqs |= (uint32_t)((filter->queue << 6761 IXGBE_ETQS_RX_QUEUE_SHIFT) & 6762 IXGBE_ETQS_RX_QUEUE); 6763 etqs |= IXGBE_ETQS_QUEUE_EN; 6764 6765 ethertype_filter.ethertype = filter->ether_type; 6766 ethertype_filter.etqf = etqf; 6767 ethertype_filter.etqs = etqs; 6768 ethertype_filter.conf = FALSE; 6769 ret = ixgbe_ethertype_filter_insert(filter_info, 6770 ðertype_filter); 6771 if (ret < 0) { 6772 PMD_DRV_LOG(ERR, "ethertype filters are full."); 6773 return -ENOSPC; 6774 } 6775 } else { 6776 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret); 6777 if (ret < 0) 6778 return -ENOSYS; 6779 } 6780 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf); 6781 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs); 6782 IXGBE_WRITE_FLUSH(hw); 6783 6784 return 0; 6785 } 6786 6787 static int 6788 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, 6789 struct rte_eth_ethertype_filter *filter) 6790 { 6791 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6792 struct ixgbe_filter_info *filter_info = 6793 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6794 uint32_t etqf, etqs; 6795 int ret; 6796 6797 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6798 if (ret < 0) { 6799 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6800 filter->ether_type); 6801 return -ENOENT; 6802 } 6803 6804 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret)); 6805 if (etqf & IXGBE_ETQF_FILTER_EN) { 6806 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret)); 6807 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE; 6808 filter->flags = 0; 6809 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> 6810 IXGBE_ETQS_RX_QUEUE_SHIFT; 6811 return 0; 6812 } 6813 return -ENOENT; 6814 } 6815 6816 /* 6817 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter. 6818 * @dev: pointer to rte_eth_dev structure 6819 * @filter_op:operation will be taken. 6820 * @arg: a pointer to specific structure corresponding to the filter_op 6821 */ 6822 static int 6823 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev, 6824 enum rte_filter_op filter_op, 6825 void *arg) 6826 { 6827 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6828 int ret; 6829 6830 MAC_TYPE_FILTER_SUP(hw->mac.type); 6831 6832 if (filter_op == RTE_ETH_FILTER_NOP) 6833 return 0; 6834 6835 if (arg == NULL) { 6836 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 6837 filter_op); 6838 return -EINVAL; 6839 } 6840 6841 switch (filter_op) { 6842 case RTE_ETH_FILTER_ADD: 6843 ret = ixgbe_add_del_ethertype_filter(dev, 6844 (struct rte_eth_ethertype_filter *)arg, 6845 TRUE); 6846 break; 6847 case RTE_ETH_FILTER_DELETE: 6848 ret = ixgbe_add_del_ethertype_filter(dev, 6849 (struct rte_eth_ethertype_filter *)arg, 6850 FALSE); 6851 break; 6852 case RTE_ETH_FILTER_GET: 6853 ret = ixgbe_get_ethertype_filter(dev, 6854 (struct rte_eth_ethertype_filter *)arg); 6855 break; 6856 default: 6857 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 6858 ret = -EINVAL; 6859 break; 6860 } 6861 return ret; 6862 } 6863 6864 static int 6865 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 6866 enum rte_filter_type filter_type, 6867 enum rte_filter_op filter_op, 6868 void *arg) 6869 { 6870 int ret = 0; 6871 6872 switch (filter_type) { 6873 case RTE_ETH_FILTER_NTUPLE: 6874 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg); 6875 break; 6876 case RTE_ETH_FILTER_ETHERTYPE: 6877 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg); 6878 break; 6879 case RTE_ETH_FILTER_SYN: 6880 ret = ixgbe_syn_filter_handle(dev, filter_op, arg); 6881 break; 6882 case RTE_ETH_FILTER_FDIR: 6883 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg); 6884 break; 6885 case RTE_ETH_FILTER_L2_TUNNEL: 6886 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg); 6887 break; 6888 case RTE_ETH_FILTER_GENERIC: 6889 if (filter_op != RTE_ETH_FILTER_GET) 6890 return -EINVAL; 6891 *(const void **)arg = &ixgbe_flow_ops; 6892 break; 6893 default: 6894 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 6895 filter_type); 6896 ret = -EINVAL; 6897 break; 6898 } 6899 6900 return ret; 6901 } 6902 6903 static u8 * 6904 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw, 6905 u8 **mc_addr_ptr, u32 *vmdq) 6906 { 6907 u8 *mc_addr; 6908 6909 *vmdq = 0; 6910 mc_addr = *mc_addr_ptr; 6911 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr)); 6912 return mc_addr; 6913 } 6914 6915 static int 6916 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 6917 struct rte_ether_addr *mc_addr_set, 6918 uint32_t nb_mc_addr) 6919 { 6920 struct ixgbe_hw *hw; 6921 u8 *mc_addr_list; 6922 6923 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6924 mc_addr_list = (u8 *)mc_addr_set; 6925 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr, 6926 ixgbe_dev_addr_list_itr, TRUE); 6927 } 6928 6929 static uint64_t 6930 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev) 6931 { 6932 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6933 uint64_t systime_cycles; 6934 6935 switch (hw->mac.type) { 6936 case ixgbe_mac_X550: 6937 case ixgbe_mac_X550EM_x: 6938 case ixgbe_mac_X550EM_a: 6939 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */ 6940 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 6941 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 6942 * NSEC_PER_SEC; 6943 break; 6944 default: 6945 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 6946 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 6947 << 32; 6948 } 6949 6950 return systime_cycles; 6951 } 6952 6953 static uint64_t 6954 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) 6955 { 6956 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6957 uint64_t rx_tstamp_cycles; 6958 6959 switch (hw->mac.type) { 6960 case ixgbe_mac_X550: 6961 case ixgbe_mac_X550EM_x: 6962 case ixgbe_mac_X550EM_a: 6963 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 6964 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 6965 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 6966 * NSEC_PER_SEC; 6967 break; 6968 default: 6969 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 6970 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 6971 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 6972 << 32; 6973 } 6974 6975 return rx_tstamp_cycles; 6976 } 6977 6978 static uint64_t 6979 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 6980 { 6981 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6982 uint64_t tx_tstamp_cycles; 6983 6984 switch (hw->mac.type) { 6985 case ixgbe_mac_X550: 6986 case ixgbe_mac_X550EM_x: 6987 case ixgbe_mac_X550EM_a: 6988 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 6989 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 6990 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 6991 * NSEC_PER_SEC; 6992 break; 6993 default: 6994 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 6995 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 6996 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 6997 << 32; 6998 } 6999 7000 return tx_tstamp_cycles; 7001 } 7002 7003 static void 7004 ixgbe_start_timecounters(struct rte_eth_dev *dev) 7005 { 7006 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7007 struct ixgbe_adapter *adapter = dev->data->dev_private; 7008 struct rte_eth_link link; 7009 uint32_t incval = 0; 7010 uint32_t shift = 0; 7011 7012 /* Get current link speed. */ 7013 ixgbe_dev_link_update(dev, 1); 7014 rte_eth_linkstatus_get(dev, &link); 7015 7016 switch (link.link_speed) { 7017 case ETH_SPEED_NUM_100M: 7018 incval = IXGBE_INCVAL_100; 7019 shift = IXGBE_INCVAL_SHIFT_100; 7020 break; 7021 case ETH_SPEED_NUM_1G: 7022 incval = IXGBE_INCVAL_1GB; 7023 shift = IXGBE_INCVAL_SHIFT_1GB; 7024 break; 7025 case ETH_SPEED_NUM_10G: 7026 default: 7027 incval = IXGBE_INCVAL_10GB; 7028 shift = IXGBE_INCVAL_SHIFT_10GB; 7029 break; 7030 } 7031 7032 switch (hw->mac.type) { 7033 case ixgbe_mac_X550: 7034 case ixgbe_mac_X550EM_x: 7035 case ixgbe_mac_X550EM_a: 7036 /* Independent of link speed. */ 7037 incval = 1; 7038 /* Cycles read will be interpreted as ns. */ 7039 shift = 0; 7040 /* Fall-through */ 7041 case ixgbe_mac_X540: 7042 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval); 7043 break; 7044 case ixgbe_mac_82599EB: 7045 incval >>= IXGBE_INCVAL_SHIFT_82599; 7046 shift -= IXGBE_INCVAL_SHIFT_82599; 7047 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 7048 (1 << IXGBE_INCPER_SHIFT_82599) | incval); 7049 break; 7050 default: 7051 /* Not supported. */ 7052 return; 7053 } 7054 7055 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 7056 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 7057 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 7058 7059 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 7060 adapter->systime_tc.cc_shift = shift; 7061 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; 7062 7063 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 7064 adapter->rx_tstamp_tc.cc_shift = shift; 7065 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 7066 7067 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 7068 adapter->tx_tstamp_tc.cc_shift = shift; 7069 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 7070 } 7071 7072 static int 7073 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 7074 { 7075 struct ixgbe_adapter *adapter = dev->data->dev_private; 7076 7077 adapter->systime_tc.nsec += delta; 7078 adapter->rx_tstamp_tc.nsec += delta; 7079 adapter->tx_tstamp_tc.nsec += delta; 7080 7081 return 0; 7082 } 7083 7084 static int 7085 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 7086 { 7087 uint64_t ns; 7088 struct ixgbe_adapter *adapter = dev->data->dev_private; 7089 7090 ns = rte_timespec_to_ns(ts); 7091 /* Set the timecounters to a new value. */ 7092 adapter->systime_tc.nsec = ns; 7093 adapter->rx_tstamp_tc.nsec = ns; 7094 adapter->tx_tstamp_tc.nsec = ns; 7095 7096 return 0; 7097 } 7098 7099 static int 7100 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 7101 { 7102 uint64_t ns, systime_cycles; 7103 struct ixgbe_adapter *adapter = dev->data->dev_private; 7104 7105 systime_cycles = ixgbe_read_systime_cyclecounter(dev); 7106 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 7107 *ts = rte_ns_to_timespec(ns); 7108 7109 return 0; 7110 } 7111 7112 static int 7113 ixgbe_timesync_enable(struct rte_eth_dev *dev) 7114 { 7115 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7116 uint32_t tsync_ctl; 7117 uint32_t tsauxc; 7118 7119 /* Stop the timesync system time. */ 7120 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0); 7121 /* Reset the timesync system time value. */ 7122 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0); 7123 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0); 7124 7125 /* Enable system time for platforms where it isn't on by default. */ 7126 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC); 7127 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME; 7128 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc); 7129 7130 ixgbe_start_timecounters(dev); 7131 7132 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7133 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 7134 (RTE_ETHER_TYPE_1588 | 7135 IXGBE_ETQF_FILTER_EN | 7136 IXGBE_ETQF_1588)); 7137 7138 /* Enable timestamping of received PTP packets. */ 7139 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7140 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED; 7141 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7142 7143 /* Enable timestamping of transmitted PTP packets. */ 7144 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7145 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED; 7146 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7147 7148 IXGBE_WRITE_FLUSH(hw); 7149 7150 return 0; 7151 } 7152 7153 static int 7154 ixgbe_timesync_disable(struct rte_eth_dev *dev) 7155 { 7156 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7157 uint32_t tsync_ctl; 7158 7159 /* Disable timestamping of transmitted PTP packets. */ 7160 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7161 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED; 7162 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7163 7164 /* Disable timestamping of received PTP packets. */ 7165 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7166 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED; 7167 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7168 7169 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7170 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0); 7171 7172 /* Stop incrementating the System Time registers. */ 7173 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0); 7174 7175 return 0; 7176 } 7177 7178 static int 7179 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 7180 struct timespec *timestamp, 7181 uint32_t flags __rte_unused) 7182 { 7183 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7184 struct ixgbe_adapter *adapter = dev->data->dev_private; 7185 uint32_t tsync_rxctl; 7186 uint64_t rx_tstamp_cycles; 7187 uint64_t ns; 7188 7189 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7190 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0) 7191 return -EINVAL; 7192 7193 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev); 7194 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 7195 *timestamp = rte_ns_to_timespec(ns); 7196 7197 return 0; 7198 } 7199 7200 static int 7201 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 7202 struct timespec *timestamp) 7203 { 7204 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7205 struct ixgbe_adapter *adapter = dev->data->dev_private; 7206 uint32_t tsync_txctl; 7207 uint64_t tx_tstamp_cycles; 7208 uint64_t ns; 7209 7210 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7211 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0) 7212 return -EINVAL; 7213 7214 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev); 7215 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 7216 *timestamp = rte_ns_to_timespec(ns); 7217 7218 return 0; 7219 } 7220 7221 static int 7222 ixgbe_get_reg_length(struct rte_eth_dev *dev) 7223 { 7224 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7225 int count = 0; 7226 int g_ind = 0; 7227 const struct reg_info *reg_group; 7228 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7229 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7230 7231 while ((reg_group = reg_set[g_ind++])) 7232 count += ixgbe_regs_group_count(reg_group); 7233 7234 return count; 7235 } 7236 7237 static int 7238 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused) 7239 { 7240 int count = 0; 7241 int g_ind = 0; 7242 const struct reg_info *reg_group; 7243 7244 while ((reg_group = ixgbevf_regs[g_ind++])) 7245 count += ixgbe_regs_group_count(reg_group); 7246 7247 return count; 7248 } 7249 7250 static int 7251 ixgbe_get_regs(struct rte_eth_dev *dev, 7252 struct rte_dev_reg_info *regs) 7253 { 7254 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7255 uint32_t *data = regs->data; 7256 int g_ind = 0; 7257 int count = 0; 7258 const struct reg_info *reg_group; 7259 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7260 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7261 7262 if (data == NULL) { 7263 regs->length = ixgbe_get_reg_length(dev); 7264 regs->width = sizeof(uint32_t); 7265 return 0; 7266 } 7267 7268 /* Support only full register dump */ 7269 if ((regs->length == 0) || 7270 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) { 7271 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7272 hw->device_id; 7273 while ((reg_group = reg_set[g_ind++])) 7274 count += ixgbe_read_regs_group(dev, &data[count], 7275 reg_group); 7276 return 0; 7277 } 7278 7279 return -ENOTSUP; 7280 } 7281 7282 static int 7283 ixgbevf_get_regs(struct rte_eth_dev *dev, 7284 struct rte_dev_reg_info *regs) 7285 { 7286 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7287 uint32_t *data = regs->data; 7288 int g_ind = 0; 7289 int count = 0; 7290 const struct reg_info *reg_group; 7291 7292 if (data == NULL) { 7293 regs->length = ixgbevf_get_reg_length(dev); 7294 regs->width = sizeof(uint32_t); 7295 return 0; 7296 } 7297 7298 /* Support only full register dump */ 7299 if ((regs->length == 0) || 7300 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) { 7301 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7302 hw->device_id; 7303 while ((reg_group = ixgbevf_regs[g_ind++])) 7304 count += ixgbe_read_regs_group(dev, &data[count], 7305 reg_group); 7306 return 0; 7307 } 7308 7309 return -ENOTSUP; 7310 } 7311 7312 static int 7313 ixgbe_get_eeprom_length(struct rte_eth_dev *dev) 7314 { 7315 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7316 7317 /* Return unit is byte count */ 7318 return hw->eeprom.word_size * 2; 7319 } 7320 7321 static int 7322 ixgbe_get_eeprom(struct rte_eth_dev *dev, 7323 struct rte_dev_eeprom_info *in_eeprom) 7324 { 7325 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7326 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7327 uint16_t *data = in_eeprom->data; 7328 int first, length; 7329 7330 first = in_eeprom->offset >> 1; 7331 length = in_eeprom->length >> 1; 7332 if ((first > hw->eeprom.word_size) || 7333 ((first + length) > hw->eeprom.word_size)) 7334 return -EINVAL; 7335 7336 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7337 7338 return eeprom->ops.read_buffer(hw, first, length, data); 7339 } 7340 7341 static int 7342 ixgbe_set_eeprom(struct rte_eth_dev *dev, 7343 struct rte_dev_eeprom_info *in_eeprom) 7344 { 7345 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7346 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7347 uint16_t *data = in_eeprom->data; 7348 int first, length; 7349 7350 first = in_eeprom->offset >> 1; 7351 length = in_eeprom->length >> 1; 7352 if ((first > hw->eeprom.word_size) || 7353 ((first + length) > hw->eeprom.word_size)) 7354 return -EINVAL; 7355 7356 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7357 7358 return eeprom->ops.write_buffer(hw, first, length, data); 7359 } 7360 7361 static int 7362 ixgbe_get_module_info(struct rte_eth_dev *dev, 7363 struct rte_eth_dev_module_info *modinfo) 7364 { 7365 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7366 uint32_t status; 7367 uint8_t sff8472_rev, addr_mode; 7368 bool page_swap = false; 7369 7370 /* Check whether we support SFF-8472 or not */ 7371 status = hw->phy.ops.read_i2c_eeprom(hw, 7372 IXGBE_SFF_SFF_8472_COMP, 7373 &sff8472_rev); 7374 if (status != 0) 7375 return -EIO; 7376 7377 /* addressing mode is not supported */ 7378 status = hw->phy.ops.read_i2c_eeprom(hw, 7379 IXGBE_SFF_SFF_8472_SWAP, 7380 &addr_mode); 7381 if (status != 0) 7382 return -EIO; 7383 7384 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 7385 PMD_DRV_LOG(ERR, 7386 "Address change required to access page 0xA2, " 7387 "but not supported. Please report the module " 7388 "type to the driver maintainers."); 7389 page_swap = true; 7390 } 7391 7392 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) { 7393 /* We have a SFP, but it does not support SFF-8472 */ 7394 modinfo->type = RTE_ETH_MODULE_SFF_8079; 7395 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 7396 } else { 7397 /* We have a SFP which supports a revision of SFF-8472. */ 7398 modinfo->type = RTE_ETH_MODULE_SFF_8472; 7399 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 7400 } 7401 7402 return 0; 7403 } 7404 7405 static int 7406 ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 7407 struct rte_dev_eeprom_info *info) 7408 { 7409 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7410 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 7411 uint8_t databyte = 0xFF; 7412 uint8_t *data = info->data; 7413 uint32_t i = 0; 7414 7415 if (info->length == 0) 7416 return -EINVAL; 7417 7418 for (i = info->offset; i < info->offset + info->length; i++) { 7419 if (i < RTE_ETH_MODULE_SFF_8079_LEN) 7420 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 7421 else 7422 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 7423 7424 if (status != 0) 7425 return -EIO; 7426 7427 data[i - info->offset] = databyte; 7428 } 7429 7430 return 0; 7431 } 7432 7433 uint16_t 7434 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) { 7435 switch (mac_type) { 7436 case ixgbe_mac_X550: 7437 case ixgbe_mac_X550EM_x: 7438 case ixgbe_mac_X550EM_a: 7439 return ETH_RSS_RETA_SIZE_512; 7440 case ixgbe_mac_X550_vf: 7441 case ixgbe_mac_X550EM_x_vf: 7442 case ixgbe_mac_X550EM_a_vf: 7443 return ETH_RSS_RETA_SIZE_64; 7444 case ixgbe_mac_X540_vf: 7445 case ixgbe_mac_82599_vf: 7446 return 0; 7447 default: 7448 return ETH_RSS_RETA_SIZE_128; 7449 } 7450 } 7451 7452 uint32_t 7453 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) { 7454 switch (mac_type) { 7455 case ixgbe_mac_X550: 7456 case ixgbe_mac_X550EM_x: 7457 case ixgbe_mac_X550EM_a: 7458 if (reta_idx < ETH_RSS_RETA_SIZE_128) 7459 return IXGBE_RETA(reta_idx >> 2); 7460 else 7461 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2); 7462 case ixgbe_mac_X550_vf: 7463 case ixgbe_mac_X550EM_x_vf: 7464 case ixgbe_mac_X550EM_a_vf: 7465 return IXGBE_VFRETA(reta_idx >> 2); 7466 default: 7467 return IXGBE_RETA(reta_idx >> 2); 7468 } 7469 } 7470 7471 uint32_t 7472 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) { 7473 switch (mac_type) { 7474 case ixgbe_mac_X550_vf: 7475 case ixgbe_mac_X550EM_x_vf: 7476 case ixgbe_mac_X550EM_a_vf: 7477 return IXGBE_VFMRQC; 7478 default: 7479 return IXGBE_MRQC; 7480 } 7481 } 7482 7483 uint32_t 7484 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) { 7485 switch (mac_type) { 7486 case ixgbe_mac_X550_vf: 7487 case ixgbe_mac_X550EM_x_vf: 7488 case ixgbe_mac_X550EM_a_vf: 7489 return IXGBE_VFRSSRK(i); 7490 default: 7491 return IXGBE_RSSRK(i); 7492 } 7493 } 7494 7495 bool 7496 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) { 7497 switch (mac_type) { 7498 case ixgbe_mac_82599_vf: 7499 case ixgbe_mac_X540_vf: 7500 return 0; 7501 default: 7502 return 1; 7503 } 7504 } 7505 7506 static int 7507 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 7508 struct rte_eth_dcb_info *dcb_info) 7509 { 7510 struct ixgbe_dcb_config *dcb_config = 7511 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 7512 struct ixgbe_dcb_tc_config *tc; 7513 struct rte_eth_dcb_tc_queue_mapping *tc_queue; 7514 uint8_t nb_tcs; 7515 uint8_t i, j; 7516 7517 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG) 7518 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs; 7519 else 7520 dcb_info->nb_tcs = 1; 7521 7522 tc_queue = &dcb_info->tc_queue; 7523 nb_tcs = dcb_info->nb_tcs; 7524 7525 if (dcb_config->vt_mode) { /* vt is enabled*/ 7526 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf = 7527 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf; 7528 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7529 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i]; 7530 if (RTE_ETH_DEV_SRIOV(dev).active > 0) { 7531 for (j = 0; j < nb_tcs; j++) { 7532 tc_queue->tc_rxq[0][j].base = j; 7533 tc_queue->tc_rxq[0][j].nb_queue = 1; 7534 tc_queue->tc_txq[0][j].base = j; 7535 tc_queue->tc_txq[0][j].nb_queue = 1; 7536 } 7537 } else { 7538 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) { 7539 for (j = 0; j < nb_tcs; j++) { 7540 tc_queue->tc_rxq[i][j].base = 7541 i * nb_tcs + j; 7542 tc_queue->tc_rxq[i][j].nb_queue = 1; 7543 tc_queue->tc_txq[i][j].base = 7544 i * nb_tcs + j; 7545 tc_queue->tc_txq[i][j].nb_queue = 1; 7546 } 7547 } 7548 } 7549 } else { /* vt is disabled*/ 7550 struct rte_eth_dcb_rx_conf *rx_conf = 7551 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 7552 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7553 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i]; 7554 if (dcb_info->nb_tcs == ETH_4_TCS) { 7555 for (i = 0; i < dcb_info->nb_tcs; i++) { 7556 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32; 7557 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7558 } 7559 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7560 dcb_info->tc_queue.tc_txq[0][1].base = 64; 7561 dcb_info->tc_queue.tc_txq[0][2].base = 96; 7562 dcb_info->tc_queue.tc_txq[0][3].base = 112; 7563 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64; 7564 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7565 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7566 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7567 } else if (dcb_info->nb_tcs == ETH_8_TCS) { 7568 for (i = 0; i < dcb_info->nb_tcs; i++) { 7569 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16; 7570 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7571 } 7572 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7573 dcb_info->tc_queue.tc_txq[0][1].base = 32; 7574 dcb_info->tc_queue.tc_txq[0][2].base = 64; 7575 dcb_info->tc_queue.tc_txq[0][3].base = 80; 7576 dcb_info->tc_queue.tc_txq[0][4].base = 96; 7577 dcb_info->tc_queue.tc_txq[0][5].base = 104; 7578 dcb_info->tc_queue.tc_txq[0][6].base = 112; 7579 dcb_info->tc_queue.tc_txq[0][7].base = 120; 7580 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32; 7581 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7582 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7583 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7584 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8; 7585 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8; 7586 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8; 7587 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8; 7588 } 7589 } 7590 for (i = 0; i < dcb_info->nb_tcs; i++) { 7591 tc = &dcb_config->tc_config[i]; 7592 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent; 7593 } 7594 return 0; 7595 } 7596 7597 /* Update e-tag ether type */ 7598 static int 7599 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw, 7600 uint16_t ether_type) 7601 { 7602 uint32_t etag_etype; 7603 7604 if (hw->mac.type != ixgbe_mac_X550 && 7605 hw->mac.type != ixgbe_mac_X550EM_x && 7606 hw->mac.type != ixgbe_mac_X550EM_a) { 7607 return -ENOTSUP; 7608 } 7609 7610 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7611 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK; 7612 etag_etype |= ether_type; 7613 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7614 IXGBE_WRITE_FLUSH(hw); 7615 7616 return 0; 7617 } 7618 7619 /* Config l2 tunnel ether type */ 7620 static int 7621 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev, 7622 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7623 { 7624 int ret = 0; 7625 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7626 struct ixgbe_l2_tn_info *l2_tn_info = 7627 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7628 7629 if (l2_tunnel == NULL) 7630 return -EINVAL; 7631 7632 switch (l2_tunnel->l2_tunnel_type) { 7633 case RTE_L2_TUNNEL_TYPE_E_TAG: 7634 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type; 7635 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type); 7636 break; 7637 default: 7638 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7639 ret = -EINVAL; 7640 break; 7641 } 7642 7643 return ret; 7644 } 7645 7646 /* Enable e-tag tunnel */ 7647 static int 7648 ixgbe_e_tag_enable(struct ixgbe_hw *hw) 7649 { 7650 uint32_t etag_etype; 7651 7652 if (hw->mac.type != ixgbe_mac_X550 && 7653 hw->mac.type != ixgbe_mac_X550EM_x && 7654 hw->mac.type != ixgbe_mac_X550EM_a) { 7655 return -ENOTSUP; 7656 } 7657 7658 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7659 etag_etype |= IXGBE_ETAG_ETYPE_VALID; 7660 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7661 IXGBE_WRITE_FLUSH(hw); 7662 7663 return 0; 7664 } 7665 7666 /* Enable l2 tunnel */ 7667 static int 7668 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev, 7669 enum rte_eth_tunnel_type l2_tunnel_type) 7670 { 7671 int ret = 0; 7672 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7673 struct ixgbe_l2_tn_info *l2_tn_info = 7674 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7675 7676 switch (l2_tunnel_type) { 7677 case RTE_L2_TUNNEL_TYPE_E_TAG: 7678 l2_tn_info->e_tag_en = TRUE; 7679 ret = ixgbe_e_tag_enable(hw); 7680 break; 7681 default: 7682 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7683 ret = -EINVAL; 7684 break; 7685 } 7686 7687 return ret; 7688 } 7689 7690 /* Disable e-tag tunnel */ 7691 static int 7692 ixgbe_e_tag_disable(struct ixgbe_hw *hw) 7693 { 7694 uint32_t etag_etype; 7695 7696 if (hw->mac.type != ixgbe_mac_X550 && 7697 hw->mac.type != ixgbe_mac_X550EM_x && 7698 hw->mac.type != ixgbe_mac_X550EM_a) { 7699 return -ENOTSUP; 7700 } 7701 7702 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7703 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID; 7704 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7705 IXGBE_WRITE_FLUSH(hw); 7706 7707 return 0; 7708 } 7709 7710 /* Disable l2 tunnel */ 7711 static int 7712 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev, 7713 enum rte_eth_tunnel_type l2_tunnel_type) 7714 { 7715 int ret = 0; 7716 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7717 struct ixgbe_l2_tn_info *l2_tn_info = 7718 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7719 7720 switch (l2_tunnel_type) { 7721 case RTE_L2_TUNNEL_TYPE_E_TAG: 7722 l2_tn_info->e_tag_en = FALSE; 7723 ret = ixgbe_e_tag_disable(hw); 7724 break; 7725 default: 7726 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7727 ret = -EINVAL; 7728 break; 7729 } 7730 7731 return ret; 7732 } 7733 7734 static int 7735 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev, 7736 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7737 { 7738 int ret = 0; 7739 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7740 uint32_t i, rar_entries; 7741 uint32_t rar_low, rar_high; 7742 7743 if (hw->mac.type != ixgbe_mac_X550 && 7744 hw->mac.type != ixgbe_mac_X550EM_x && 7745 hw->mac.type != ixgbe_mac_X550EM_a) { 7746 return -ENOTSUP; 7747 } 7748 7749 rar_entries = ixgbe_get_num_rx_addrs(hw); 7750 7751 for (i = 1; i < rar_entries; i++) { 7752 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7753 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 7754 if ((rar_high & IXGBE_RAH_AV) && 7755 (rar_high & IXGBE_RAH_ADTYPE) && 7756 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) == 7757 l2_tunnel->tunnel_id)) { 7758 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 7759 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 7760 7761 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL); 7762 7763 return ret; 7764 } 7765 } 7766 7767 return ret; 7768 } 7769 7770 static int 7771 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev, 7772 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7773 { 7774 int ret = 0; 7775 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7776 uint32_t i, rar_entries; 7777 uint32_t rar_low, rar_high; 7778 7779 if (hw->mac.type != ixgbe_mac_X550 && 7780 hw->mac.type != ixgbe_mac_X550EM_x && 7781 hw->mac.type != ixgbe_mac_X550EM_a) { 7782 return -ENOTSUP; 7783 } 7784 7785 /* One entry for one tunnel. Try to remove potential existing entry. */ 7786 ixgbe_e_tag_filter_del(dev, l2_tunnel); 7787 7788 rar_entries = ixgbe_get_num_rx_addrs(hw); 7789 7790 for (i = 1; i < rar_entries; i++) { 7791 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7792 if (rar_high & IXGBE_RAH_AV) { 7793 continue; 7794 } else { 7795 ixgbe_set_vmdq(hw, i, l2_tunnel->pool); 7796 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE; 7797 rar_low = l2_tunnel->tunnel_id; 7798 7799 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low); 7800 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high); 7801 7802 return ret; 7803 } 7804 } 7805 7806 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full." 7807 " Please remove a rule before adding a new one."); 7808 return -EINVAL; 7809 } 7810 7811 static inline struct ixgbe_l2_tn_filter * 7812 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info, 7813 struct ixgbe_l2_tn_key *key) 7814 { 7815 int ret; 7816 7817 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key); 7818 if (ret < 0) 7819 return NULL; 7820 7821 return l2_tn_info->hash_map[ret]; 7822 } 7823 7824 static inline int 7825 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7826 struct ixgbe_l2_tn_filter *l2_tn_filter) 7827 { 7828 int ret; 7829 7830 ret = rte_hash_add_key(l2_tn_info->hash_handle, 7831 &l2_tn_filter->key); 7832 7833 if (ret < 0) { 7834 PMD_DRV_LOG(ERR, 7835 "Failed to insert L2 tunnel filter" 7836 " to hash table %d!", 7837 ret); 7838 return ret; 7839 } 7840 7841 l2_tn_info->hash_map[ret] = l2_tn_filter; 7842 7843 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 7844 7845 return 0; 7846 } 7847 7848 static inline int 7849 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7850 struct ixgbe_l2_tn_key *key) 7851 { 7852 int ret; 7853 struct ixgbe_l2_tn_filter *l2_tn_filter; 7854 7855 ret = rte_hash_del_key(l2_tn_info->hash_handle, key); 7856 7857 if (ret < 0) { 7858 PMD_DRV_LOG(ERR, 7859 "No such L2 tunnel filter to delete %d!", 7860 ret); 7861 return ret; 7862 } 7863 7864 l2_tn_filter = l2_tn_info->hash_map[ret]; 7865 l2_tn_info->hash_map[ret] = NULL; 7866 7867 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 7868 rte_free(l2_tn_filter); 7869 7870 return 0; 7871 } 7872 7873 /* Add l2 tunnel filter */ 7874 int 7875 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 7876 struct rte_eth_l2_tunnel_conf *l2_tunnel, 7877 bool restore) 7878 { 7879 int ret; 7880 struct ixgbe_l2_tn_info *l2_tn_info = 7881 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7882 struct ixgbe_l2_tn_key key; 7883 struct ixgbe_l2_tn_filter *node; 7884 7885 if (!restore) { 7886 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 7887 key.tn_id = l2_tunnel->tunnel_id; 7888 7889 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key); 7890 7891 if (node) { 7892 PMD_DRV_LOG(ERR, 7893 "The L2 tunnel filter already exists!"); 7894 return -EINVAL; 7895 } 7896 7897 node = rte_zmalloc("ixgbe_l2_tn", 7898 sizeof(struct ixgbe_l2_tn_filter), 7899 0); 7900 if (!node) 7901 return -ENOMEM; 7902 7903 rte_memcpy(&node->key, 7904 &key, 7905 sizeof(struct ixgbe_l2_tn_key)); 7906 node->pool = l2_tunnel->pool; 7907 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node); 7908 if (ret < 0) { 7909 rte_free(node); 7910 return ret; 7911 } 7912 } 7913 7914 switch (l2_tunnel->l2_tunnel_type) { 7915 case RTE_L2_TUNNEL_TYPE_E_TAG: 7916 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel); 7917 break; 7918 default: 7919 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7920 ret = -EINVAL; 7921 break; 7922 } 7923 7924 if ((!restore) && (ret < 0)) 7925 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 7926 7927 return ret; 7928 } 7929 7930 /* Delete l2 tunnel filter */ 7931 int 7932 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 7933 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7934 { 7935 int ret; 7936 struct ixgbe_l2_tn_info *l2_tn_info = 7937 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7938 struct ixgbe_l2_tn_key key; 7939 7940 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 7941 key.tn_id = l2_tunnel->tunnel_id; 7942 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 7943 if (ret < 0) 7944 return ret; 7945 7946 switch (l2_tunnel->l2_tunnel_type) { 7947 case RTE_L2_TUNNEL_TYPE_E_TAG: 7948 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel); 7949 break; 7950 default: 7951 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7952 ret = -EINVAL; 7953 break; 7954 } 7955 7956 return ret; 7957 } 7958 7959 /** 7960 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter. 7961 * @dev: pointer to rte_eth_dev structure 7962 * @filter_op:operation will be taken. 7963 * @arg: a pointer to specific structure corresponding to the filter_op 7964 */ 7965 static int 7966 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev, 7967 enum rte_filter_op filter_op, 7968 void *arg) 7969 { 7970 int ret; 7971 7972 if (filter_op == RTE_ETH_FILTER_NOP) 7973 return 0; 7974 7975 if (arg == NULL) { 7976 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 7977 filter_op); 7978 return -EINVAL; 7979 } 7980 7981 switch (filter_op) { 7982 case RTE_ETH_FILTER_ADD: 7983 ret = ixgbe_dev_l2_tunnel_filter_add 7984 (dev, 7985 (struct rte_eth_l2_tunnel_conf *)arg, 7986 FALSE); 7987 break; 7988 case RTE_ETH_FILTER_DELETE: 7989 ret = ixgbe_dev_l2_tunnel_filter_del 7990 (dev, 7991 (struct rte_eth_l2_tunnel_conf *)arg); 7992 break; 7993 default: 7994 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 7995 ret = -EINVAL; 7996 break; 7997 } 7998 return ret; 7999 } 8000 8001 static int 8002 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en) 8003 { 8004 int ret = 0; 8005 uint32_t ctrl; 8006 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8007 8008 if (hw->mac.type != ixgbe_mac_X550 && 8009 hw->mac.type != ixgbe_mac_X550EM_x && 8010 hw->mac.type != ixgbe_mac_X550EM_a) { 8011 return -ENOTSUP; 8012 } 8013 8014 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 8015 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 8016 if (en) 8017 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG; 8018 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 8019 8020 return ret; 8021 } 8022 8023 /* Enable l2 tunnel forwarding */ 8024 static int 8025 ixgbe_dev_l2_tunnel_forwarding_enable 8026 (struct rte_eth_dev *dev, 8027 enum rte_eth_tunnel_type l2_tunnel_type) 8028 { 8029 struct ixgbe_l2_tn_info *l2_tn_info = 8030 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8031 int ret = 0; 8032 8033 switch (l2_tunnel_type) { 8034 case RTE_L2_TUNNEL_TYPE_E_TAG: 8035 l2_tn_info->e_tag_fwd_en = TRUE; 8036 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1); 8037 break; 8038 default: 8039 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8040 ret = -EINVAL; 8041 break; 8042 } 8043 8044 return ret; 8045 } 8046 8047 /* Disable l2 tunnel forwarding */ 8048 static int 8049 ixgbe_dev_l2_tunnel_forwarding_disable 8050 (struct rte_eth_dev *dev, 8051 enum rte_eth_tunnel_type l2_tunnel_type) 8052 { 8053 struct ixgbe_l2_tn_info *l2_tn_info = 8054 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8055 int ret = 0; 8056 8057 switch (l2_tunnel_type) { 8058 case RTE_L2_TUNNEL_TYPE_E_TAG: 8059 l2_tn_info->e_tag_fwd_en = FALSE; 8060 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0); 8061 break; 8062 default: 8063 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8064 ret = -EINVAL; 8065 break; 8066 } 8067 8068 return ret; 8069 } 8070 8071 static int 8072 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev, 8073 struct rte_eth_l2_tunnel_conf *l2_tunnel, 8074 bool en) 8075 { 8076 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 8077 int ret = 0; 8078 uint32_t vmtir, vmvir; 8079 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8080 8081 if (l2_tunnel->vf_id >= pci_dev->max_vfs) { 8082 PMD_DRV_LOG(ERR, 8083 "VF id %u should be less than %u", 8084 l2_tunnel->vf_id, 8085 pci_dev->max_vfs); 8086 return -EINVAL; 8087 } 8088 8089 if (hw->mac.type != ixgbe_mac_X550 && 8090 hw->mac.type != ixgbe_mac_X550EM_x && 8091 hw->mac.type != ixgbe_mac_X550EM_a) { 8092 return -ENOTSUP; 8093 } 8094 8095 if (en) 8096 vmtir = l2_tunnel->tunnel_id; 8097 else 8098 vmtir = 0; 8099 8100 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir); 8101 8102 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id)); 8103 vmvir &= ~IXGBE_VMVIR_TAGA_MASK; 8104 if (en) 8105 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT; 8106 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir); 8107 8108 return ret; 8109 } 8110 8111 /* Enable l2 tunnel tag insertion */ 8112 static int 8113 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev, 8114 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8115 { 8116 int ret = 0; 8117 8118 switch (l2_tunnel->l2_tunnel_type) { 8119 case RTE_L2_TUNNEL_TYPE_E_TAG: 8120 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1); 8121 break; 8122 default: 8123 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8124 ret = -EINVAL; 8125 break; 8126 } 8127 8128 return ret; 8129 } 8130 8131 /* Disable l2 tunnel tag insertion */ 8132 static int 8133 ixgbe_dev_l2_tunnel_insertion_disable 8134 (struct rte_eth_dev *dev, 8135 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8136 { 8137 int ret = 0; 8138 8139 switch (l2_tunnel->l2_tunnel_type) { 8140 case RTE_L2_TUNNEL_TYPE_E_TAG: 8141 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0); 8142 break; 8143 default: 8144 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8145 ret = -EINVAL; 8146 break; 8147 } 8148 8149 return ret; 8150 } 8151 8152 static int 8153 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev, 8154 bool en) 8155 { 8156 int ret = 0; 8157 uint32_t qde; 8158 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8159 8160 if (hw->mac.type != ixgbe_mac_X550 && 8161 hw->mac.type != ixgbe_mac_X550EM_x && 8162 hw->mac.type != ixgbe_mac_X550EM_a) { 8163 return -ENOTSUP; 8164 } 8165 8166 qde = IXGBE_READ_REG(hw, IXGBE_QDE); 8167 if (en) 8168 qde |= IXGBE_QDE_STRIP_TAG; 8169 else 8170 qde &= ~IXGBE_QDE_STRIP_TAG; 8171 qde &= ~IXGBE_QDE_READ; 8172 qde |= IXGBE_QDE_WRITE; 8173 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde); 8174 8175 return ret; 8176 } 8177 8178 /* Enable l2 tunnel tag stripping */ 8179 static int 8180 ixgbe_dev_l2_tunnel_stripping_enable 8181 (struct rte_eth_dev *dev, 8182 enum rte_eth_tunnel_type l2_tunnel_type) 8183 { 8184 int ret = 0; 8185 8186 switch (l2_tunnel_type) { 8187 case RTE_L2_TUNNEL_TYPE_E_TAG: 8188 ret = ixgbe_e_tag_stripping_en_dis(dev, 1); 8189 break; 8190 default: 8191 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8192 ret = -EINVAL; 8193 break; 8194 } 8195 8196 return ret; 8197 } 8198 8199 /* Disable l2 tunnel tag stripping */ 8200 static int 8201 ixgbe_dev_l2_tunnel_stripping_disable 8202 (struct rte_eth_dev *dev, 8203 enum rte_eth_tunnel_type l2_tunnel_type) 8204 { 8205 int ret = 0; 8206 8207 switch (l2_tunnel_type) { 8208 case RTE_L2_TUNNEL_TYPE_E_TAG: 8209 ret = ixgbe_e_tag_stripping_en_dis(dev, 0); 8210 break; 8211 default: 8212 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8213 ret = -EINVAL; 8214 break; 8215 } 8216 8217 return ret; 8218 } 8219 8220 /* Enable/disable l2 tunnel offload functions */ 8221 static int 8222 ixgbe_dev_l2_tunnel_offload_set 8223 (struct rte_eth_dev *dev, 8224 struct rte_eth_l2_tunnel_conf *l2_tunnel, 8225 uint32_t mask, 8226 uint8_t en) 8227 { 8228 int ret = 0; 8229 8230 if (l2_tunnel == NULL) 8231 return -EINVAL; 8232 8233 ret = -EINVAL; 8234 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) { 8235 if (en) 8236 ret = ixgbe_dev_l2_tunnel_enable( 8237 dev, 8238 l2_tunnel->l2_tunnel_type); 8239 else 8240 ret = ixgbe_dev_l2_tunnel_disable( 8241 dev, 8242 l2_tunnel->l2_tunnel_type); 8243 } 8244 8245 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) { 8246 if (en) 8247 ret = ixgbe_dev_l2_tunnel_insertion_enable( 8248 dev, 8249 l2_tunnel); 8250 else 8251 ret = ixgbe_dev_l2_tunnel_insertion_disable( 8252 dev, 8253 l2_tunnel); 8254 } 8255 8256 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) { 8257 if (en) 8258 ret = ixgbe_dev_l2_tunnel_stripping_enable( 8259 dev, 8260 l2_tunnel->l2_tunnel_type); 8261 else 8262 ret = ixgbe_dev_l2_tunnel_stripping_disable( 8263 dev, 8264 l2_tunnel->l2_tunnel_type); 8265 } 8266 8267 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) { 8268 if (en) 8269 ret = ixgbe_dev_l2_tunnel_forwarding_enable( 8270 dev, 8271 l2_tunnel->l2_tunnel_type); 8272 else 8273 ret = ixgbe_dev_l2_tunnel_forwarding_disable( 8274 dev, 8275 l2_tunnel->l2_tunnel_type); 8276 } 8277 8278 return ret; 8279 } 8280 8281 static int 8282 ixgbe_update_vxlan_port(struct ixgbe_hw *hw, 8283 uint16_t port) 8284 { 8285 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port); 8286 IXGBE_WRITE_FLUSH(hw); 8287 8288 return 0; 8289 } 8290 8291 /* There's only one register for VxLAN UDP port. 8292 * So, we cannot add several ports. Will update it. 8293 */ 8294 static int 8295 ixgbe_add_vxlan_port(struct ixgbe_hw *hw, 8296 uint16_t port) 8297 { 8298 if (port == 0) { 8299 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 8300 return -EINVAL; 8301 } 8302 8303 return ixgbe_update_vxlan_port(hw, port); 8304 } 8305 8306 /* We cannot delete the VxLAN port. For there's a register for VxLAN 8307 * UDP port, it must have a value. 8308 * So, will reset it to the original value 0. 8309 */ 8310 static int 8311 ixgbe_del_vxlan_port(struct ixgbe_hw *hw, 8312 uint16_t port) 8313 { 8314 uint16_t cur_port; 8315 8316 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL); 8317 8318 if (cur_port != port) { 8319 PMD_DRV_LOG(ERR, "Port %u does not exist.", port); 8320 return -EINVAL; 8321 } 8322 8323 return ixgbe_update_vxlan_port(hw, 0); 8324 } 8325 8326 /* Add UDP tunneling port */ 8327 static int 8328 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 8329 struct rte_eth_udp_tunnel *udp_tunnel) 8330 { 8331 int ret = 0; 8332 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8333 8334 if (hw->mac.type != ixgbe_mac_X550 && 8335 hw->mac.type != ixgbe_mac_X550EM_x && 8336 hw->mac.type != ixgbe_mac_X550EM_a) { 8337 return -ENOTSUP; 8338 } 8339 8340 if (udp_tunnel == NULL) 8341 return -EINVAL; 8342 8343 switch (udp_tunnel->prot_type) { 8344 case RTE_TUNNEL_TYPE_VXLAN: 8345 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port); 8346 break; 8347 8348 case RTE_TUNNEL_TYPE_GENEVE: 8349 case RTE_TUNNEL_TYPE_TEREDO: 8350 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8351 ret = -EINVAL; 8352 break; 8353 8354 default: 8355 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8356 ret = -EINVAL; 8357 break; 8358 } 8359 8360 return ret; 8361 } 8362 8363 /* Remove UDP tunneling port */ 8364 static int 8365 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 8366 struct rte_eth_udp_tunnel *udp_tunnel) 8367 { 8368 int ret = 0; 8369 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8370 8371 if (hw->mac.type != ixgbe_mac_X550 && 8372 hw->mac.type != ixgbe_mac_X550EM_x && 8373 hw->mac.type != ixgbe_mac_X550EM_a) { 8374 return -ENOTSUP; 8375 } 8376 8377 if (udp_tunnel == NULL) 8378 return -EINVAL; 8379 8380 switch (udp_tunnel->prot_type) { 8381 case RTE_TUNNEL_TYPE_VXLAN: 8382 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port); 8383 break; 8384 case RTE_TUNNEL_TYPE_GENEVE: 8385 case RTE_TUNNEL_TYPE_TEREDO: 8386 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8387 ret = -EINVAL; 8388 break; 8389 default: 8390 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8391 ret = -EINVAL; 8392 break; 8393 } 8394 8395 return ret; 8396 } 8397 8398 static void 8399 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev) 8400 { 8401 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8402 8403 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC); 8404 } 8405 8406 static void 8407 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev) 8408 { 8409 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8410 8411 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE); 8412 } 8413 8414 static void 8415 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev) 8416 { 8417 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8418 8419 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI); 8420 } 8421 8422 static void 8423 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev) 8424 { 8425 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8426 8427 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI); 8428 } 8429 8430 static void ixgbevf_mbx_process(struct rte_eth_dev *dev) 8431 { 8432 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8433 u32 in_msg = 0; 8434 8435 /* peek the message first */ 8436 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM); 8437 8438 /* PF reset VF event */ 8439 if (in_msg == IXGBE_PF_CONTROL_MSG) { 8440 /* dummy mbx read to ack pf */ 8441 if (ixgbe_read_mbx(hw, &in_msg, 1, 0)) 8442 return; 8443 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 8444 NULL); 8445 } 8446 } 8447 8448 static int 8449 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev) 8450 { 8451 uint32_t eicr; 8452 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8453 struct ixgbe_interrupt *intr = 8454 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8455 ixgbevf_intr_disable(dev); 8456 8457 /* read-on-clear nic registers here */ 8458 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR); 8459 intr->flags = 0; 8460 8461 /* only one misc vector supported - mailbox */ 8462 eicr &= IXGBE_VTEICR_MASK; 8463 if (eicr == IXGBE_MISC_VEC_ID) 8464 intr->flags |= IXGBE_FLAG_MAILBOX; 8465 8466 return 0; 8467 } 8468 8469 static int 8470 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev) 8471 { 8472 struct ixgbe_interrupt *intr = 8473 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8474 8475 if (intr->flags & IXGBE_FLAG_MAILBOX) { 8476 ixgbevf_mbx_process(dev); 8477 intr->flags &= ~IXGBE_FLAG_MAILBOX; 8478 } 8479 8480 ixgbevf_intr_enable(dev); 8481 8482 return 0; 8483 } 8484 8485 static void 8486 ixgbevf_dev_interrupt_handler(void *param) 8487 { 8488 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 8489 8490 ixgbevf_dev_interrupt_get_status(dev); 8491 ixgbevf_dev_interrupt_action(dev); 8492 } 8493 8494 /** 8495 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path 8496 * @hw: pointer to hardware structure 8497 * 8498 * Stops the transmit data path and waits for the HW to internally empty 8499 * the Tx security block 8500 **/ 8501 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw) 8502 { 8503 #define IXGBE_MAX_SECTX_POLL 40 8504 8505 int i; 8506 int sectxreg; 8507 8508 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8509 sectxreg |= IXGBE_SECTXCTRL_TX_DIS; 8510 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8511 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) { 8512 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT); 8513 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY) 8514 break; 8515 /* Use interrupt-safe sleep just in case */ 8516 usec_delay(1000); 8517 } 8518 8519 /* For informational purposes only */ 8520 if (i >= IXGBE_MAX_SECTX_POLL) 8521 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security " 8522 "path fully disabled. Continuing with init."); 8523 8524 return IXGBE_SUCCESS; 8525 } 8526 8527 /** 8528 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path 8529 * @hw: pointer to hardware structure 8530 * 8531 * Enables the transmit data path. 8532 **/ 8533 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw) 8534 { 8535 uint32_t sectxreg; 8536 8537 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8538 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS; 8539 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8540 IXGBE_WRITE_FLUSH(hw); 8541 8542 return IXGBE_SUCCESS; 8543 } 8544 8545 /* restore n-tuple filter */ 8546 static inline void 8547 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev) 8548 { 8549 struct ixgbe_filter_info *filter_info = 8550 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8551 struct ixgbe_5tuple_filter *node; 8552 8553 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) { 8554 ixgbe_inject_5tuple_filter(dev, node); 8555 } 8556 } 8557 8558 /* restore ethernet type filter */ 8559 static inline void 8560 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev) 8561 { 8562 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8563 struct ixgbe_filter_info *filter_info = 8564 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8565 int i; 8566 8567 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8568 if (filter_info->ethertype_mask & (1 << i)) { 8569 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 8570 filter_info->ethertype_filters[i].etqf); 8571 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 8572 filter_info->ethertype_filters[i].etqs); 8573 IXGBE_WRITE_FLUSH(hw); 8574 } 8575 } 8576 } 8577 8578 /* restore SYN filter */ 8579 static inline void 8580 ixgbe_syn_filter_restore(struct rte_eth_dev *dev) 8581 { 8582 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8583 struct ixgbe_filter_info *filter_info = 8584 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8585 uint32_t synqf; 8586 8587 synqf = filter_info->syn_info; 8588 8589 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 8590 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 8591 IXGBE_WRITE_FLUSH(hw); 8592 } 8593 } 8594 8595 /* restore L2 tunnel filter */ 8596 static inline void 8597 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev) 8598 { 8599 struct ixgbe_l2_tn_info *l2_tn_info = 8600 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8601 struct ixgbe_l2_tn_filter *node; 8602 struct rte_eth_l2_tunnel_conf l2_tn_conf; 8603 8604 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) { 8605 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type; 8606 l2_tn_conf.tunnel_id = node->key.tn_id; 8607 l2_tn_conf.pool = node->pool; 8608 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE); 8609 } 8610 } 8611 8612 /* restore rss filter */ 8613 static inline void 8614 ixgbe_rss_filter_restore(struct rte_eth_dev *dev) 8615 { 8616 struct ixgbe_filter_info *filter_info = 8617 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8618 8619 if (filter_info->rss_info.conf.queue_num) 8620 ixgbe_config_rss_filter(dev, 8621 &filter_info->rss_info, TRUE); 8622 } 8623 8624 static int 8625 ixgbe_filter_restore(struct rte_eth_dev *dev) 8626 { 8627 ixgbe_ntuple_filter_restore(dev); 8628 ixgbe_ethertype_filter_restore(dev); 8629 ixgbe_syn_filter_restore(dev); 8630 ixgbe_fdir_filter_restore(dev); 8631 ixgbe_l2_tn_filter_restore(dev); 8632 ixgbe_rss_filter_restore(dev); 8633 8634 return 0; 8635 } 8636 8637 static void 8638 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev) 8639 { 8640 struct ixgbe_l2_tn_info *l2_tn_info = 8641 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8642 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8643 8644 if (l2_tn_info->e_tag_en) 8645 (void)ixgbe_e_tag_enable(hw); 8646 8647 if (l2_tn_info->e_tag_fwd_en) 8648 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1); 8649 8650 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type); 8651 } 8652 8653 /* remove all the n-tuple filters */ 8654 void 8655 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev) 8656 { 8657 struct ixgbe_filter_info *filter_info = 8658 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8659 struct ixgbe_5tuple_filter *p_5tuple; 8660 8661 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) 8662 ixgbe_remove_5tuple_filter(dev, p_5tuple); 8663 } 8664 8665 /* remove all the ether type filters */ 8666 void 8667 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev) 8668 { 8669 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8670 struct ixgbe_filter_info *filter_info = 8671 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8672 int i; 8673 8674 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8675 if (filter_info->ethertype_mask & (1 << i) && 8676 !filter_info->ethertype_filters[i].conf) { 8677 (void)ixgbe_ethertype_filter_remove(filter_info, 8678 (uint8_t)i); 8679 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0); 8680 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0); 8681 IXGBE_WRITE_FLUSH(hw); 8682 } 8683 } 8684 } 8685 8686 /* remove the SYN filter */ 8687 void 8688 ixgbe_clear_syn_filter(struct rte_eth_dev *dev) 8689 { 8690 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8691 struct ixgbe_filter_info *filter_info = 8692 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8693 8694 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) { 8695 filter_info->syn_info = 0; 8696 8697 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0); 8698 IXGBE_WRITE_FLUSH(hw); 8699 } 8700 } 8701 8702 /* remove all the L2 tunnel filters */ 8703 int 8704 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev) 8705 { 8706 struct ixgbe_l2_tn_info *l2_tn_info = 8707 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8708 struct ixgbe_l2_tn_filter *l2_tn_filter; 8709 struct rte_eth_l2_tunnel_conf l2_tn_conf; 8710 int ret = 0; 8711 8712 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 8713 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type; 8714 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id; 8715 l2_tn_conf.pool = l2_tn_filter->pool; 8716 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf); 8717 if (ret < 0) 8718 return ret; 8719 } 8720 8721 return 0; 8722 } 8723 8724 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd); 8725 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map); 8726 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 8727 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd); 8728 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map); 8729 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci"); 8730 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf, 8731 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>"); 8732 8733 RTE_INIT(ixgbe_init_log) 8734 { 8735 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init"); 8736 if (ixgbe_logtype_init >= 0) 8737 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE); 8738 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver"); 8739 if (ixgbe_logtype_driver >= 0) 8740 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE); 8741 } 8742