1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <inttypes.h> 13 #include <netinet/in.h> 14 #include <rte_byteorder.h> 15 #include <rte_common.h> 16 #include <rte_cycles.h> 17 18 #include <rte_interrupts.h> 19 #include <rte_log.h> 20 #include <rte_debug.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_branch_prediction.h> 24 #include <rte_memory.h> 25 #include <rte_eal.h> 26 #include <rte_alarm.h> 27 #include <rte_ether.h> 28 #include <rte_ethdev_driver.h> 29 #include <rte_ethdev_pci.h> 30 #include <rte_malloc.h> 31 #include <rte_random.h> 32 #include <rte_dev.h> 33 #include <rte_hash_crc.h> 34 #ifdef RTE_LIBRTE_SECURITY 35 #include <rte_security_driver.h> 36 #endif 37 38 #include "ixgbe_logs.h" 39 #include "base/ixgbe_api.h" 40 #include "base/ixgbe_vf.h" 41 #include "base/ixgbe_common.h" 42 #include "ixgbe_ethdev.h" 43 #include "ixgbe_bypass.h" 44 #include "ixgbe_rxtx.h" 45 #include "base/ixgbe_type.h" 46 #include "base/ixgbe_phy.h" 47 #include "ixgbe_regs.h" 48 49 /* 50 * High threshold controlling when to start sending XOFF frames. Must be at 51 * least 8 bytes less than receive packet buffer size. This value is in units 52 * of 1024 bytes. 53 */ 54 #define IXGBE_FC_HI 0x80 55 56 /* 57 * Low threshold controlling when to start sending XON frames. This value is 58 * in units of 1024 bytes. 59 */ 60 #define IXGBE_FC_LO 0x40 61 62 /* Timer value included in XOFF frames. */ 63 #define IXGBE_FC_PAUSE 0x680 64 65 /*Default value of Max Rx Queue*/ 66 #define IXGBE_MAX_RX_QUEUE_NUM 128 67 68 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */ 69 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */ 70 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */ 71 72 #define IXGBE_MMW_SIZE_DEFAULT 0x4 73 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14 74 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */ 75 76 /* 77 * Default values for RX/TX configuration 78 */ 79 #define IXGBE_DEFAULT_RX_FREE_THRESH 32 80 #define IXGBE_DEFAULT_RX_PTHRESH 8 81 #define IXGBE_DEFAULT_RX_HTHRESH 8 82 #define IXGBE_DEFAULT_RX_WTHRESH 0 83 84 #define IXGBE_DEFAULT_TX_FREE_THRESH 32 85 #define IXGBE_DEFAULT_TX_PTHRESH 32 86 #define IXGBE_DEFAULT_TX_HTHRESH 0 87 #define IXGBE_DEFAULT_TX_WTHRESH 0 88 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32 89 90 /* Bit shift and mask */ 91 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2) 92 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t) 93 #define IXGBE_8_BIT_WIDTH CHAR_BIT 94 #define IXGBE_8_BIT_MASK UINT8_MAX 95 96 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */ 97 98 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0])) 99 100 /* Additional timesync values. */ 101 #define NSEC_PER_SEC 1000000000L 102 #define IXGBE_INCVAL_10GB 0x66666666 103 #define IXGBE_INCVAL_1GB 0x40000000 104 #define IXGBE_INCVAL_100 0x50000000 105 #define IXGBE_INCVAL_SHIFT_10GB 28 106 #define IXGBE_INCVAL_SHIFT_1GB 24 107 #define IXGBE_INCVAL_SHIFT_100 21 108 #define IXGBE_INCVAL_SHIFT_82599 7 109 #define IXGBE_INCPER_SHIFT_82599 24 110 111 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL 112 113 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000 114 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000 115 #define IXGBE_ETAG_ETYPE 0x00005084 116 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff 117 #define IXGBE_ETAG_ETYPE_VALID 0x80000000 118 #define IXGBE_RAH_ADTYPE 0x40000000 119 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff 120 #define IXGBE_VMVIR_TAGA_MASK 0x18000000 121 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000 122 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */ 123 #define IXGBE_QDE_STRIP_TAG 0x00000004 124 #define IXGBE_VTEICR_MASK 0x07 125 126 #define IXGBE_EXVET_VET_EXT_SHIFT 16 127 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000 128 129 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 130 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev); 131 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev); 132 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev); 133 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev); 134 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev); 135 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev); 136 static int ixgbe_dev_configure(struct rte_eth_dev *dev); 137 static int ixgbe_dev_start(struct rte_eth_dev *dev); 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev); 139 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev); 140 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev); 141 static void ixgbe_dev_close(struct rte_eth_dev *dev); 142 static int ixgbe_dev_reset(struct rte_eth_dev *dev); 143 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 144 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 145 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 146 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 147 static int ixgbe_dev_link_update(struct rte_eth_dev *dev, 148 int wait_to_complete); 149 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev, 150 struct rte_eth_stats *stats); 151 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev, 152 struct rte_eth_xstat *xstats, unsigned n); 153 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, 154 struct rte_eth_xstat *xstats, unsigned n); 155 static int 156 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 157 uint64_t *values, unsigned int n); 158 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev); 159 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev); 160 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 161 struct rte_eth_xstat_name *xstats_names, 162 unsigned int size); 163 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev, 164 struct rte_eth_xstat_name *xstats_names, unsigned limit); 165 static int ixgbe_dev_xstats_get_names_by_id( 166 struct rte_eth_dev *dev, 167 struct rte_eth_xstat_name *xstats_names, 168 const uint64_t *ids, 169 unsigned int limit); 170 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 171 uint16_t queue_id, 172 uint8_t stat_idx, 173 uint8_t is_rx); 174 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 175 size_t fw_size); 176 static void ixgbe_dev_info_get(struct rte_eth_dev *dev, 177 struct rte_eth_dev_info *dev_info); 178 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); 179 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev, 180 struct rte_eth_dev_info *dev_info); 181 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 182 183 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev, 184 uint16_t vlan_id, int on); 185 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 186 enum rte_vlan_type vlan_type, 187 uint16_t tpid_id); 188 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, 189 uint16_t queue, bool on); 190 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, 191 int on); 192 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, 193 int mask); 194 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask); 195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask); 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue); 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue); 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev); 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev); 200 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev); 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev); 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, 204 struct rte_eth_fc_conf *fc_conf); 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, 206 struct rte_eth_fc_conf *fc_conf); 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 208 struct rte_eth_pfc_conf *pfc_conf); 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 210 struct rte_eth_rss_reta_entry64 *reta_conf, 211 uint16_t reta_size); 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 213 struct rte_eth_rss_reta_entry64 *reta_conf, 214 uint16_t reta_size); 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev); 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); 217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev); 218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); 219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev); 220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev); 221 static void ixgbe_dev_interrupt_handler(void *param); 222 static void ixgbe_dev_interrupt_delayed_handler(void *param); 223 static void ixgbe_dev_setup_link_alarm_handler(void *param); 224 225 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr, 226 uint32_t index, uint32_t pool); 227 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index); 228 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, 229 struct ether_addr *mac_addr); 230 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config); 231 static bool is_device_supported(struct rte_eth_dev *dev, 232 struct rte_pci_driver *drv); 233 234 /* For Virtual Function support */ 235 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev); 236 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev); 237 static int ixgbevf_dev_configure(struct rte_eth_dev *dev); 238 static int ixgbevf_dev_start(struct rte_eth_dev *dev); 239 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev, 240 int wait_to_complete); 241 static void ixgbevf_dev_stop(struct rte_eth_dev *dev); 242 static void ixgbevf_dev_close(struct rte_eth_dev *dev); 243 static int ixgbevf_dev_reset(struct rte_eth_dev *dev); 244 static void ixgbevf_intr_disable(struct rte_eth_dev *dev); 245 static void ixgbevf_intr_enable(struct rte_eth_dev *dev); 246 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev, 247 struct rte_eth_stats *stats); 248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev); 249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, 250 uint16_t vlan_id, int on); 251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, 252 uint16_t queue, int on); 253 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask); 254 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask); 255 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on); 256 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 257 uint16_t queue_id); 258 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 259 uint16_t queue_id); 260 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 261 uint8_t queue, uint8_t msix_vector); 262 static void ixgbevf_configure_msix(struct rte_eth_dev *dev); 263 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev); 264 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev); 265 266 /* For Eth VMDQ APIs support */ 267 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct 268 ether_addr * mac_addr, uint8_t on); 269 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on); 270 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 271 struct rte_eth_mirror_conf *mirror_conf, 272 uint8_t rule_id, uint8_t on); 273 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, 274 uint8_t rule_id); 275 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 276 uint16_t queue_id); 277 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 278 uint16_t queue_id); 279 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 280 uint8_t queue, uint8_t msix_vector); 281 static void ixgbe_configure_msix(struct rte_eth_dev *dev); 282 283 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev, 284 struct ether_addr *mac_addr, 285 uint32_t index, uint32_t pool); 286 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index); 287 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 288 struct ether_addr *mac_addr); 289 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev, 290 struct rte_eth_syn_filter *filter); 291 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev, 292 enum rte_filter_op filter_op, 293 void *arg); 294 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 295 struct ixgbe_5tuple_filter *filter); 296 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 297 struct ixgbe_5tuple_filter *filter); 298 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev, 299 enum rte_filter_op filter_op, 300 void *arg); 301 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev, 302 struct rte_eth_ntuple_filter *filter); 303 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev, 304 enum rte_filter_op filter_op, 305 void *arg); 306 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, 307 struct rte_eth_ethertype_filter *filter); 308 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 309 enum rte_filter_type filter_type, 310 enum rte_filter_op filter_op, 311 void *arg); 312 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 313 314 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 315 struct ether_addr *mc_addr_set, 316 uint32_t nb_mc_addr); 317 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 318 struct rte_eth_dcb_info *dcb_info); 319 320 static int ixgbe_get_reg_length(struct rte_eth_dev *dev); 321 static int ixgbe_get_regs(struct rte_eth_dev *dev, 322 struct rte_dev_reg_info *regs); 323 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev); 324 static int ixgbe_get_eeprom(struct rte_eth_dev *dev, 325 struct rte_dev_eeprom_info *eeprom); 326 static int ixgbe_set_eeprom(struct rte_eth_dev *dev, 327 struct rte_dev_eeprom_info *eeprom); 328 329 static int ixgbe_get_module_info(struct rte_eth_dev *dev, 330 struct rte_eth_dev_module_info *modinfo); 331 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 332 struct rte_dev_eeprom_info *info); 333 334 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev); 335 static int ixgbevf_get_regs(struct rte_eth_dev *dev, 336 struct rte_dev_reg_info *regs); 337 338 static int ixgbe_timesync_enable(struct rte_eth_dev *dev); 339 static int ixgbe_timesync_disable(struct rte_eth_dev *dev); 340 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 341 struct timespec *timestamp, 342 uint32_t flags); 343 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 344 struct timespec *timestamp); 345 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 346 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev, 347 struct timespec *timestamp); 348 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev, 349 const struct timespec *timestamp); 350 static void ixgbevf_dev_interrupt_handler(void *param); 351 352 static int ixgbe_dev_l2_tunnel_eth_type_conf 353 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel); 354 static int ixgbe_dev_l2_tunnel_offload_set 355 (struct rte_eth_dev *dev, 356 struct rte_eth_l2_tunnel_conf *l2_tunnel, 357 uint32_t mask, 358 uint8_t en); 359 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev, 360 enum rte_filter_op filter_op, 361 void *arg); 362 363 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 364 struct rte_eth_udp_tunnel *udp_tunnel); 365 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 366 struct rte_eth_udp_tunnel *udp_tunnel); 367 static int ixgbe_filter_restore(struct rte_eth_dev *dev); 368 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev); 369 370 /* 371 * Define VF Stats MACRO for Non "cleared on read" register 372 */ 373 #define UPDATE_VF_STAT(reg, last, cur) \ 374 { \ 375 uint32_t latest = IXGBE_READ_REG(hw, reg); \ 376 cur += (latest - last) & UINT_MAX; \ 377 last = latest; \ 378 } 379 380 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \ 381 { \ 382 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \ 383 u64 new_msb = IXGBE_READ_REG(hw, msb); \ 384 u64 latest = ((new_msb << 32) | new_lsb); \ 385 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \ 386 last = latest; \ 387 } 388 389 #define IXGBE_SET_HWSTRIP(h, q) do {\ 390 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 391 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 392 (h)->bitmap[idx] |= 1 << bit;\ 393 } while (0) 394 395 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\ 396 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 397 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 398 (h)->bitmap[idx] &= ~(1 << bit);\ 399 } while (0) 400 401 #define IXGBE_GET_HWSTRIP(h, q, r) do {\ 402 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 403 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 404 (r) = (h)->bitmap[idx] >> bit & 1;\ 405 } while (0) 406 407 int ixgbe_logtype_init; 408 int ixgbe_logtype_driver; 409 410 /* 411 * The set of PCI devices this driver supports 412 */ 413 static const struct rte_pci_id pci_id_ixgbe_map[] = { 414 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) }, 415 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) }, 416 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) }, 417 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) }, 418 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) }, 419 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) }, 420 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) }, 421 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) }, 422 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) }, 423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) }, 424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) }, 425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) }, 426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) }, 427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) }, 428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) }, 429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) }, 430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) }, 431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) }, 432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) }, 433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) }, 434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) }, 435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) }, 436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) }, 437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) }, 438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) }, 439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) }, 440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) }, 441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) }, 442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) }, 443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) }, 444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) }, 445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) }, 446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) }, 447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) }, 448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) }, 449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) }, 450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) }, 451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) }, 452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) }, 453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) }, 454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) }, 455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) }, 456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) }, 457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) }, 458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) }, 459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) }, 460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) }, 461 #ifdef RTE_LIBRTE_IXGBE_BYPASS 462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) }, 463 #endif 464 { .vendor_id = 0, /* sentinel */ }, 465 }; 466 467 /* 468 * The set of PCI devices this driver supports (for 82599 VF) 469 */ 470 static const struct rte_pci_id pci_id_ixgbevf_map[] = { 471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) }, 472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) }, 473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) }, 474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) }, 475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) }, 476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) }, 477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) }, 478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) }, 479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) }, 480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) }, 481 { .vendor_id = 0, /* sentinel */ }, 482 }; 483 484 static const struct rte_eth_desc_lim rx_desc_lim = { 485 .nb_max = IXGBE_MAX_RING_DESC, 486 .nb_min = IXGBE_MIN_RING_DESC, 487 .nb_align = IXGBE_RXD_ALIGN, 488 }; 489 490 static const struct rte_eth_desc_lim tx_desc_lim = { 491 .nb_max = IXGBE_MAX_RING_DESC, 492 .nb_min = IXGBE_MIN_RING_DESC, 493 .nb_align = IXGBE_TXD_ALIGN, 494 .nb_seg_max = IXGBE_TX_MAX_SEG, 495 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG, 496 }; 497 498 static const struct eth_dev_ops ixgbe_eth_dev_ops = { 499 .dev_configure = ixgbe_dev_configure, 500 .dev_start = ixgbe_dev_start, 501 .dev_stop = ixgbe_dev_stop, 502 .dev_set_link_up = ixgbe_dev_set_link_up, 503 .dev_set_link_down = ixgbe_dev_set_link_down, 504 .dev_close = ixgbe_dev_close, 505 .dev_reset = ixgbe_dev_reset, 506 .promiscuous_enable = ixgbe_dev_promiscuous_enable, 507 .promiscuous_disable = ixgbe_dev_promiscuous_disable, 508 .allmulticast_enable = ixgbe_dev_allmulticast_enable, 509 .allmulticast_disable = ixgbe_dev_allmulticast_disable, 510 .link_update = ixgbe_dev_link_update, 511 .stats_get = ixgbe_dev_stats_get, 512 .xstats_get = ixgbe_dev_xstats_get, 513 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id, 514 .stats_reset = ixgbe_dev_stats_reset, 515 .xstats_reset = ixgbe_dev_xstats_reset, 516 .xstats_get_names = ixgbe_dev_xstats_get_names, 517 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id, 518 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set, 519 .fw_version_get = ixgbe_fw_version_get, 520 .dev_infos_get = ixgbe_dev_info_get, 521 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 522 .mtu_set = ixgbe_dev_mtu_set, 523 .vlan_filter_set = ixgbe_vlan_filter_set, 524 .vlan_tpid_set = ixgbe_vlan_tpid_set, 525 .vlan_offload_set = ixgbe_vlan_offload_set, 526 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set, 527 .rx_queue_start = ixgbe_dev_rx_queue_start, 528 .rx_queue_stop = ixgbe_dev_rx_queue_stop, 529 .tx_queue_start = ixgbe_dev_tx_queue_start, 530 .tx_queue_stop = ixgbe_dev_tx_queue_stop, 531 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 532 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable, 533 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable, 534 .rx_queue_release = ixgbe_dev_rx_queue_release, 535 .rx_queue_count = ixgbe_dev_rx_queue_count, 536 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done, 537 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status, 538 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status, 539 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 540 .tx_queue_release = ixgbe_dev_tx_queue_release, 541 .dev_led_on = ixgbe_dev_led_on, 542 .dev_led_off = ixgbe_dev_led_off, 543 .flow_ctrl_get = ixgbe_flow_ctrl_get, 544 .flow_ctrl_set = ixgbe_flow_ctrl_set, 545 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set, 546 .mac_addr_add = ixgbe_add_rar, 547 .mac_addr_remove = ixgbe_remove_rar, 548 .mac_addr_set = ixgbe_set_default_mac_addr, 549 .uc_hash_table_set = ixgbe_uc_hash_table_set, 550 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set, 551 .mirror_rule_set = ixgbe_mirror_rule_set, 552 .mirror_rule_reset = ixgbe_mirror_rule_reset, 553 .set_queue_rate_limit = ixgbe_set_queue_rate_limit, 554 .reta_update = ixgbe_dev_rss_reta_update, 555 .reta_query = ixgbe_dev_rss_reta_query, 556 .rss_hash_update = ixgbe_dev_rss_hash_update, 557 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 558 .filter_ctrl = ixgbe_dev_filter_ctrl, 559 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 560 .rxq_info_get = ixgbe_rxq_info_get, 561 .txq_info_get = ixgbe_txq_info_get, 562 .timesync_enable = ixgbe_timesync_enable, 563 .timesync_disable = ixgbe_timesync_disable, 564 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp, 565 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp, 566 .get_reg = ixgbe_get_regs, 567 .get_eeprom_length = ixgbe_get_eeprom_length, 568 .get_eeprom = ixgbe_get_eeprom, 569 .set_eeprom = ixgbe_set_eeprom, 570 .get_module_info = ixgbe_get_module_info, 571 .get_module_eeprom = ixgbe_get_module_eeprom, 572 .get_dcb_info = ixgbe_dev_get_dcb_info, 573 .timesync_adjust_time = ixgbe_timesync_adjust_time, 574 .timesync_read_time = ixgbe_timesync_read_time, 575 .timesync_write_time = ixgbe_timesync_write_time, 576 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf, 577 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set, 578 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add, 579 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del, 580 .tm_ops_get = ixgbe_tm_ops_get, 581 }; 582 583 /* 584 * dev_ops for virtual function, bare necessities for basic vf 585 * operation have been implemented 586 */ 587 static const struct eth_dev_ops ixgbevf_eth_dev_ops = { 588 .dev_configure = ixgbevf_dev_configure, 589 .dev_start = ixgbevf_dev_start, 590 .dev_stop = ixgbevf_dev_stop, 591 .link_update = ixgbevf_dev_link_update, 592 .stats_get = ixgbevf_dev_stats_get, 593 .xstats_get = ixgbevf_dev_xstats_get, 594 .stats_reset = ixgbevf_dev_stats_reset, 595 .xstats_reset = ixgbevf_dev_stats_reset, 596 .xstats_get_names = ixgbevf_dev_xstats_get_names, 597 .dev_close = ixgbevf_dev_close, 598 .dev_reset = ixgbevf_dev_reset, 599 .allmulticast_enable = ixgbevf_dev_allmulticast_enable, 600 .allmulticast_disable = ixgbevf_dev_allmulticast_disable, 601 .dev_infos_get = ixgbevf_dev_info_get, 602 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 603 .mtu_set = ixgbevf_dev_set_mtu, 604 .vlan_filter_set = ixgbevf_vlan_filter_set, 605 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set, 606 .vlan_offload_set = ixgbevf_vlan_offload_set, 607 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 608 .rx_queue_release = ixgbe_dev_rx_queue_release, 609 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done, 610 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status, 611 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status, 612 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 613 .tx_queue_release = ixgbe_dev_tx_queue_release, 614 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable, 615 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable, 616 .mac_addr_add = ixgbevf_add_mac_addr, 617 .mac_addr_remove = ixgbevf_remove_mac_addr, 618 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 619 .rxq_info_get = ixgbe_rxq_info_get, 620 .txq_info_get = ixgbe_txq_info_get, 621 .mac_addr_set = ixgbevf_set_default_mac_addr, 622 .get_reg = ixgbevf_get_regs, 623 .reta_update = ixgbe_dev_rss_reta_update, 624 .reta_query = ixgbe_dev_rss_reta_query, 625 .rss_hash_update = ixgbe_dev_rss_hash_update, 626 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 627 }; 628 629 /* store statistics names and its offset in stats structure */ 630 struct rte_ixgbe_xstats_name_off { 631 char name[RTE_ETH_XSTATS_NAME_SIZE]; 632 unsigned offset; 633 }; 634 635 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = { 636 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)}, 637 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)}, 638 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)}, 639 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)}, 640 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)}, 641 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)}, 642 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)}, 643 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)}, 644 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)}, 645 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)}, 646 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)}, 647 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)}, 648 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)}, 649 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)}, 650 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 651 prc1023)}, 652 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 653 prc1522)}, 654 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)}, 655 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)}, 656 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)}, 657 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)}, 658 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)}, 659 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)}, 660 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)}, 661 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)}, 662 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)}, 663 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)}, 664 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)}, 665 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)}, 666 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)}, 667 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)}, 668 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)}, 669 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)}, 670 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 671 ptc1023)}, 672 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 673 ptc1522)}, 674 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)}, 675 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)}, 676 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)}, 677 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)}, 678 679 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats, 680 fdirustat_add)}, 681 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats, 682 fdirustat_remove)}, 683 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats, 684 fdirfstat_fadd)}, 685 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats, 686 fdirfstat_fremove)}, 687 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats, 688 fdirmatch)}, 689 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats, 690 fdirmiss)}, 691 692 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)}, 693 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)}, 694 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, 695 fclast)}, 696 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)}, 697 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)}, 698 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)}, 699 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)}, 700 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats, 701 fcoe_noddp)}, 702 {"rx_fcoe_no_direct_data_placement_ext_buff", 703 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)}, 704 705 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 706 lxontxc)}, 707 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 708 lxonrxc)}, 709 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 710 lxofftxc)}, 711 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 712 lxoffrxc)}, 713 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)}, 714 }; 715 716 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \ 717 sizeof(rte_ixgbe_stats_strings[0])) 718 719 /* MACsec statistics */ 720 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = { 721 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 722 out_pkts_untagged)}, 723 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats, 724 out_pkts_encrypted)}, 725 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats, 726 out_pkts_protected)}, 727 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats, 728 out_octets_encrypted)}, 729 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats, 730 out_octets_protected)}, 731 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 732 in_pkts_untagged)}, 733 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats, 734 in_pkts_badtag)}, 735 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats, 736 in_pkts_nosci)}, 737 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats, 738 in_pkts_unknownsci)}, 739 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats, 740 in_octets_decrypted)}, 741 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats, 742 in_octets_validated)}, 743 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats, 744 in_pkts_unchecked)}, 745 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats, 746 in_pkts_delayed)}, 747 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats, 748 in_pkts_late)}, 749 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats, 750 in_pkts_ok)}, 751 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats, 752 in_pkts_invalid)}, 753 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats, 754 in_pkts_notvalid)}, 755 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats, 756 in_pkts_unusedsa)}, 757 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats, 758 in_pkts_notusingsa)}, 759 }; 760 761 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \ 762 sizeof(rte_ixgbe_macsec_strings[0])) 763 764 /* Per-queue statistics */ 765 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = { 766 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)}, 767 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)}, 768 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)}, 769 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)}, 770 }; 771 772 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \ 773 sizeof(rte_ixgbe_rxq_strings[0])) 774 #define IXGBE_NB_RXQ_PRIO_VALUES 8 775 776 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = { 777 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)}, 778 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)}, 779 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats, 780 pxon2offc)}, 781 }; 782 783 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \ 784 sizeof(rte_ixgbe_txq_strings[0])) 785 #define IXGBE_NB_TXQ_PRIO_VALUES 8 786 787 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = { 788 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)}, 789 }; 790 791 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \ 792 sizeof(rte_ixgbevf_stats_strings[0])) 793 794 /* 795 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h. 796 */ 797 static inline int 798 ixgbe_is_sfp(struct ixgbe_hw *hw) 799 { 800 switch (hw->phy.type) { 801 case ixgbe_phy_sfp_avago: 802 case ixgbe_phy_sfp_ftl: 803 case ixgbe_phy_sfp_intel: 804 case ixgbe_phy_sfp_unknown: 805 case ixgbe_phy_sfp_passive_tyco: 806 case ixgbe_phy_sfp_passive_unknown: 807 return 1; 808 default: 809 return 0; 810 } 811 } 812 813 static inline int32_t 814 ixgbe_pf_reset_hw(struct ixgbe_hw *hw) 815 { 816 uint32_t ctrl_ext; 817 int32_t status; 818 819 status = ixgbe_reset_hw(hw); 820 821 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 822 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 823 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 824 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 825 IXGBE_WRITE_FLUSH(hw); 826 827 if (status == IXGBE_ERR_SFP_NOT_PRESENT) 828 status = IXGBE_SUCCESS; 829 return status; 830 } 831 832 static inline void 833 ixgbe_enable_intr(struct rte_eth_dev *dev) 834 { 835 struct ixgbe_interrupt *intr = 836 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 837 struct ixgbe_hw *hw = 838 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 839 840 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask); 841 IXGBE_WRITE_FLUSH(hw); 842 } 843 844 /* 845 * This function is based on ixgbe_disable_intr() in base/ixgbe.h. 846 */ 847 static void 848 ixgbe_disable_intr(struct ixgbe_hw *hw) 849 { 850 PMD_INIT_FUNC_TRACE(); 851 852 if (hw->mac.type == ixgbe_mac_82598EB) { 853 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0); 854 } else { 855 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000); 856 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0); 857 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0); 858 } 859 IXGBE_WRITE_FLUSH(hw); 860 } 861 862 /* 863 * This function resets queue statistics mapping registers. 864 * From Niantic datasheet, Initialization of Statistics section: 865 * "...if software requires the queue counters, the RQSMR and TQSM registers 866 * must be re-programmed following a device reset. 867 */ 868 static void 869 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw) 870 { 871 uint32_t i; 872 873 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) { 874 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0); 875 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0); 876 } 877 } 878 879 880 static int 881 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 882 uint16_t queue_id, 883 uint8_t stat_idx, 884 uint8_t is_rx) 885 { 886 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8 887 #define NB_QMAP_FIELDS_PER_QSM_REG 4 888 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f 889 890 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 891 struct ixgbe_stat_mapping_registers *stat_mappings = 892 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private); 893 uint32_t qsmr_mask = 0; 894 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK; 895 uint32_t q_map; 896 uint8_t n, offset; 897 898 if ((hw->mac.type != ixgbe_mac_82599EB) && 899 (hw->mac.type != ixgbe_mac_X540) && 900 (hw->mac.type != ixgbe_mac_X550) && 901 (hw->mac.type != ixgbe_mac_X550EM_x) && 902 (hw->mac.type != ixgbe_mac_X550EM_a)) 903 return -ENOSYS; 904 905 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d", 906 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 907 queue_id, stat_idx); 908 909 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG); 910 if (n >= IXGBE_NB_STAT_MAPPING_REGS) { 911 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded"); 912 return -EIO; 913 } 914 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG); 915 916 /* Now clear any previous stat_idx set */ 917 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 918 if (!is_rx) 919 stat_mappings->tqsm[n] &= ~clearing_mask; 920 else 921 stat_mappings->rqsmr[n] &= ~clearing_mask; 922 923 q_map = (uint32_t)stat_idx; 924 q_map &= QMAP_FIELD_RESERVED_BITS_MASK; 925 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 926 if (!is_rx) 927 stat_mappings->tqsm[n] |= qsmr_mask; 928 else 929 stat_mappings->rqsmr[n] |= qsmr_mask; 930 931 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d", 932 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 933 queue_id, stat_idx); 934 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n, 935 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]); 936 937 /* Now write the mapping in the appropriate register */ 938 if (is_rx) { 939 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d", 940 stat_mappings->rqsmr[n], n); 941 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]); 942 } else { 943 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d", 944 stat_mappings->tqsm[n], n); 945 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]); 946 } 947 return 0; 948 } 949 950 static void 951 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev) 952 { 953 struct ixgbe_stat_mapping_registers *stat_mappings = 954 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private); 955 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 956 int i; 957 958 /* write whatever was in stat mapping table to the NIC */ 959 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) { 960 /* rx */ 961 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]); 962 963 /* tx */ 964 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]); 965 } 966 } 967 968 static void 969 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config) 970 { 971 uint8_t i; 972 struct ixgbe_dcb_tc_config *tc; 973 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS; 974 975 dcb_config->num_tcs.pg_tcs = dcb_max_tc; 976 dcb_config->num_tcs.pfc_tcs = dcb_max_tc; 977 for (i = 0; i < dcb_max_tc; i++) { 978 tc = &dcb_config->tc_config[i]; 979 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i; 980 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 981 (uint8_t)(100/dcb_max_tc + (i & 1)); 982 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i; 983 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 984 (uint8_t)(100/dcb_max_tc + (i & 1)); 985 tc->pfc = ixgbe_dcb_pfc_disabled; 986 } 987 988 /* Initialize default user to priority mapping, UPx->TC0 */ 989 tc = &dcb_config->tc_config[0]; 990 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 991 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 992 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) { 993 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100; 994 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100; 995 } 996 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal; 997 dcb_config->pfc_mode_enable = false; 998 dcb_config->vt_mode = true; 999 dcb_config->round_robin_enable = false; 1000 /* support all DCB capabilities in 82599 */ 1001 dcb_config->support.capabilities = 0xFF; 1002 1003 /*we only support 4 Tcs for X540, X550 */ 1004 if (hw->mac.type == ixgbe_mac_X540 || 1005 hw->mac.type == ixgbe_mac_X550 || 1006 hw->mac.type == ixgbe_mac_X550EM_x || 1007 hw->mac.type == ixgbe_mac_X550EM_a) { 1008 dcb_config->num_tcs.pg_tcs = 4; 1009 dcb_config->num_tcs.pfc_tcs = 4; 1010 } 1011 } 1012 1013 /* 1014 * Ensure that all locks are released before first NVM or PHY access 1015 */ 1016 static void 1017 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw) 1018 { 1019 uint16_t mask; 1020 1021 /* 1022 * Phy lock should not fail in this early stage. If this is the case, 1023 * it is due to an improper exit of the application. 1024 * So force the release of the faulty lock. Release of common lock 1025 * is done automatically by swfw_sync function. 1026 */ 1027 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func; 1028 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1029 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func); 1030 } 1031 ixgbe_release_swfw_semaphore(hw, mask); 1032 1033 /* 1034 * These ones are more tricky since they are common to all ports; but 1035 * swfw_sync retries last long enough (1s) to be almost sure that if 1036 * lock can not be taken it is due to an improper lock of the 1037 * semaphore. 1038 */ 1039 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM; 1040 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1041 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 1042 } 1043 ixgbe_release_swfw_semaphore(hw, mask); 1044 } 1045 1046 /* 1047 * This function is based on code in ixgbe_attach() in base/ixgbe.c. 1048 * It returns 0 on success. 1049 */ 1050 static int 1051 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) 1052 { 1053 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1054 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1055 struct ixgbe_hw *hw = 1056 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1057 struct ixgbe_vfta *shadow_vfta = 1058 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1059 struct ixgbe_hwstrip *hwstrip = 1060 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1061 struct ixgbe_dcb_config *dcb_config = 1062 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private); 1063 struct ixgbe_filter_info *filter_info = 1064 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1065 struct ixgbe_bw_conf *bw_conf = 1066 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private); 1067 uint32_t ctrl_ext; 1068 uint16_t csum; 1069 int diag, i; 1070 1071 PMD_INIT_FUNC_TRACE(); 1072 1073 eth_dev->dev_ops = &ixgbe_eth_dev_ops; 1074 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1075 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1076 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts; 1077 1078 /* 1079 * For secondary processes, we don't initialise any further as primary 1080 * has already done this work. Only check we don't need a different 1081 * RX and TX function. 1082 */ 1083 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1084 struct ixgbe_tx_queue *txq; 1085 /* TX queue function in primary, set by last queue initialized 1086 * Tx queue may not initialized by primary process 1087 */ 1088 if (eth_dev->data->tx_queues) { 1089 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1]; 1090 ixgbe_set_tx_function(eth_dev, txq); 1091 } else { 1092 /* Use default TX function if we get here */ 1093 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. " 1094 "Using default TX function."); 1095 } 1096 1097 ixgbe_set_rx_function(eth_dev); 1098 1099 return 0; 1100 } 1101 1102 rte_eth_copy_pci_info(eth_dev, pci_dev); 1103 1104 /* Vendor and Device ID need to be set before init of shared code */ 1105 hw->device_id = pci_dev->id.device_id; 1106 hw->vendor_id = pci_dev->id.vendor_id; 1107 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1108 hw->allow_unsupported_sfp = 1; 1109 1110 /* Initialize the shared code (base driver) */ 1111 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1112 diag = ixgbe_bypass_init_shared_code(hw); 1113 #else 1114 diag = ixgbe_init_shared_code(hw); 1115 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1116 1117 if (diag != IXGBE_SUCCESS) { 1118 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag); 1119 return -EIO; 1120 } 1121 1122 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 1123 PMD_INIT_LOG(ERR, "\nERROR: " 1124 "Firmware recovery mode detected. Limiting functionality.\n" 1125 "Refer to the Intel(R) Ethernet Adapters and Devices " 1126 "User Guide for details on firmware recovery mode."); 1127 return -EIO; 1128 } 1129 1130 /* pick up the PCI bus settings for reporting later */ 1131 ixgbe_get_bus_info(hw); 1132 1133 /* Unlock any pending hardware semaphore */ 1134 ixgbe_swfw_lock_reset(hw); 1135 1136 #ifdef RTE_LIBRTE_SECURITY 1137 /* Initialize security_ctx only for primary process*/ 1138 if (ixgbe_ipsec_ctx_create(eth_dev)) 1139 return -ENOMEM; 1140 #endif 1141 1142 /* Initialize DCB configuration*/ 1143 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config)); 1144 ixgbe_dcb_init(hw, dcb_config); 1145 /* Get Hardware Flow Control setting */ 1146 hw->fc.requested_mode = ixgbe_fc_full; 1147 hw->fc.current_mode = ixgbe_fc_full; 1148 hw->fc.pause_time = IXGBE_FC_PAUSE; 1149 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 1150 hw->fc.low_water[i] = IXGBE_FC_LO; 1151 hw->fc.high_water[i] = IXGBE_FC_HI; 1152 } 1153 hw->fc.send_xon = 1; 1154 1155 /* Make sure we have a good EEPROM before we read from it */ 1156 diag = ixgbe_validate_eeprom_checksum(hw, &csum); 1157 if (diag != IXGBE_SUCCESS) { 1158 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag); 1159 return -EIO; 1160 } 1161 1162 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1163 diag = ixgbe_bypass_init_hw(hw); 1164 #else 1165 diag = ixgbe_init_hw(hw); 1166 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1167 1168 /* 1169 * Devices with copper phys will fail to initialise if ixgbe_init_hw() 1170 * is called too soon after the kernel driver unbinding/binding occurs. 1171 * The failure occurs in ixgbe_identify_phy_generic() for all devices, 1172 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is 1173 * also called. See ixgbe_identify_phy_82599(). The reason for the 1174 * failure is not known, and only occuts when virtualisation features 1175 * are disabled in the bios. A delay of 100ms was found to be enough by 1176 * trial-and-error, and is doubled to be safe. 1177 */ 1178 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) { 1179 rte_delay_ms(200); 1180 diag = ixgbe_init_hw(hw); 1181 } 1182 1183 if (diag == IXGBE_ERR_SFP_NOT_PRESENT) 1184 diag = IXGBE_SUCCESS; 1185 1186 if (diag == IXGBE_ERR_EEPROM_VERSION) { 1187 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/" 1188 "LOM. Please be aware there may be issues associated " 1189 "with your hardware."); 1190 PMD_INIT_LOG(ERR, "If you are experiencing problems " 1191 "please contact your Intel or hardware representative " 1192 "who provided you with this hardware."); 1193 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED) 1194 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module"); 1195 if (diag) { 1196 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag); 1197 return -EIO; 1198 } 1199 1200 /* Reset the hw statistics */ 1201 ixgbe_dev_stats_reset(eth_dev); 1202 1203 /* disable interrupt */ 1204 ixgbe_disable_intr(hw); 1205 1206 /* reset mappings for queue statistics hw counters*/ 1207 ixgbe_reset_qstat_mappings(hw); 1208 1209 /* Allocate memory for storing MAC addresses */ 1210 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN * 1211 hw->mac.num_rar_entries, 0); 1212 if (eth_dev->data->mac_addrs == NULL) { 1213 PMD_INIT_LOG(ERR, 1214 "Failed to allocate %u bytes needed to store " 1215 "MAC addresses", 1216 ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1217 return -ENOMEM; 1218 } 1219 /* Copy the permanent MAC address */ 1220 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr, 1221 ð_dev->data->mac_addrs[0]); 1222 1223 /* Allocate memory for storing hash filter MAC addresses */ 1224 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN * 1225 IXGBE_VMDQ_NUM_UC_MAC, 0); 1226 if (eth_dev->data->hash_mac_addrs == NULL) { 1227 PMD_INIT_LOG(ERR, 1228 "Failed to allocate %d bytes needed to store MAC addresses", 1229 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC); 1230 return -ENOMEM; 1231 } 1232 1233 /* initialize the vfta */ 1234 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1235 1236 /* initialize the hw strip bitmap*/ 1237 memset(hwstrip, 0, sizeof(*hwstrip)); 1238 1239 /* initialize PF if max_vfs not zero */ 1240 ixgbe_pf_host_init(eth_dev); 1241 1242 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 1243 /* let hardware know driver is loaded */ 1244 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD; 1245 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 1246 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 1247 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 1248 IXGBE_WRITE_FLUSH(hw); 1249 1250 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 1251 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d", 1252 (int) hw->mac.type, (int) hw->phy.type, 1253 (int) hw->phy.sfp_type); 1254 else 1255 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d", 1256 (int) hw->mac.type, (int) hw->phy.type); 1257 1258 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 1259 eth_dev->data->port_id, pci_dev->id.vendor_id, 1260 pci_dev->id.device_id); 1261 1262 rte_intr_callback_register(intr_handle, 1263 ixgbe_dev_interrupt_handler, eth_dev); 1264 1265 /* enable uio/vfio intr/eventfd mapping */ 1266 rte_intr_enable(intr_handle); 1267 1268 /* enable support intr */ 1269 ixgbe_enable_intr(eth_dev); 1270 1271 /* initialize filter info */ 1272 memset(filter_info, 0, 1273 sizeof(struct ixgbe_filter_info)); 1274 1275 /* initialize 5tuple filter list */ 1276 TAILQ_INIT(&filter_info->fivetuple_list); 1277 1278 /* initialize flow director filter list & hash */ 1279 ixgbe_fdir_filter_init(eth_dev); 1280 1281 /* initialize l2 tunnel filter list & hash */ 1282 ixgbe_l2_tn_filter_init(eth_dev); 1283 1284 /* initialize flow filter lists */ 1285 ixgbe_filterlist_init(); 1286 1287 /* initialize bandwidth configuration info */ 1288 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf)); 1289 1290 /* initialize Traffic Manager configuration */ 1291 ixgbe_tm_conf_init(eth_dev); 1292 1293 return 0; 1294 } 1295 1296 static int 1297 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1298 { 1299 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1300 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1301 struct ixgbe_hw *hw; 1302 int retries = 0; 1303 int ret; 1304 1305 PMD_INIT_FUNC_TRACE(); 1306 1307 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1308 return 0; 1309 1310 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1311 1312 if (hw->adapter_stopped == 0) 1313 ixgbe_dev_close(eth_dev); 1314 1315 eth_dev->dev_ops = NULL; 1316 eth_dev->rx_pkt_burst = NULL; 1317 eth_dev->tx_pkt_burst = NULL; 1318 1319 /* Unlock any pending hardware semaphore */ 1320 ixgbe_swfw_lock_reset(hw); 1321 1322 /* disable uio intr before callback unregister */ 1323 rte_intr_disable(intr_handle); 1324 1325 do { 1326 ret = rte_intr_callback_unregister(intr_handle, 1327 ixgbe_dev_interrupt_handler, eth_dev); 1328 if (ret >= 0) { 1329 break; 1330 } else if (ret != -EAGAIN) { 1331 PMD_INIT_LOG(ERR, 1332 "intr callback unregister failed: %d", 1333 ret); 1334 return ret; 1335 } 1336 rte_delay_ms(100); 1337 } while (retries++ < (10 + IXGBE_LINK_UP_TIME)); 1338 1339 /* uninitialize PF if max_vfs not zero */ 1340 ixgbe_pf_host_uninit(eth_dev); 1341 1342 /* remove all the fdir filters & hash */ 1343 ixgbe_fdir_filter_uninit(eth_dev); 1344 1345 /* remove all the L2 tunnel filters & hash */ 1346 ixgbe_l2_tn_filter_uninit(eth_dev); 1347 1348 /* Remove all ntuple filters of the device */ 1349 ixgbe_ntuple_filter_uninit(eth_dev); 1350 1351 /* clear all the filters list */ 1352 ixgbe_filterlist_flush(); 1353 1354 /* Remove all Traffic Manager configuration */ 1355 ixgbe_tm_conf_uninit(eth_dev); 1356 1357 #ifdef RTE_LIBRTE_SECURITY 1358 rte_free(eth_dev->security_ctx); 1359 #endif 1360 1361 return 0; 1362 } 1363 1364 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev) 1365 { 1366 struct ixgbe_filter_info *filter_info = 1367 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1368 struct ixgbe_5tuple_filter *p_5tuple; 1369 1370 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) { 1371 TAILQ_REMOVE(&filter_info->fivetuple_list, 1372 p_5tuple, 1373 entries); 1374 rte_free(p_5tuple); 1375 } 1376 memset(filter_info->fivetuple_mask, 0, 1377 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE); 1378 1379 return 0; 1380 } 1381 1382 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev) 1383 { 1384 struct ixgbe_hw_fdir_info *fdir_info = 1385 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1386 struct ixgbe_fdir_filter *fdir_filter; 1387 1388 if (fdir_info->hash_map) 1389 rte_free(fdir_info->hash_map); 1390 if (fdir_info->hash_handle) 1391 rte_hash_free(fdir_info->hash_handle); 1392 1393 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 1394 TAILQ_REMOVE(&fdir_info->fdir_list, 1395 fdir_filter, 1396 entries); 1397 rte_free(fdir_filter); 1398 } 1399 1400 return 0; 1401 } 1402 1403 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev) 1404 { 1405 struct ixgbe_l2_tn_info *l2_tn_info = 1406 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1407 struct ixgbe_l2_tn_filter *l2_tn_filter; 1408 1409 if (l2_tn_info->hash_map) 1410 rte_free(l2_tn_info->hash_map); 1411 if (l2_tn_info->hash_handle) 1412 rte_hash_free(l2_tn_info->hash_handle); 1413 1414 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 1415 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, 1416 l2_tn_filter, 1417 entries); 1418 rte_free(l2_tn_filter); 1419 } 1420 1421 return 0; 1422 } 1423 1424 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev) 1425 { 1426 struct ixgbe_hw_fdir_info *fdir_info = 1427 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1428 char fdir_hash_name[RTE_HASH_NAMESIZE]; 1429 struct rte_hash_parameters fdir_hash_params = { 1430 .name = fdir_hash_name, 1431 .entries = IXGBE_MAX_FDIR_FILTER_NUM, 1432 .key_len = sizeof(union ixgbe_atr_input), 1433 .hash_func = rte_hash_crc, 1434 .hash_func_init_val = 0, 1435 .socket_id = rte_socket_id(), 1436 }; 1437 1438 TAILQ_INIT(&fdir_info->fdir_list); 1439 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 1440 "fdir_%s", eth_dev->device->name); 1441 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params); 1442 if (!fdir_info->hash_handle) { 1443 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 1444 return -EINVAL; 1445 } 1446 fdir_info->hash_map = rte_zmalloc("ixgbe", 1447 sizeof(struct ixgbe_fdir_filter *) * 1448 IXGBE_MAX_FDIR_FILTER_NUM, 1449 0); 1450 if (!fdir_info->hash_map) { 1451 PMD_INIT_LOG(ERR, 1452 "Failed to allocate memory for fdir hash map!"); 1453 return -ENOMEM; 1454 } 1455 fdir_info->mask_added = FALSE; 1456 1457 return 0; 1458 } 1459 1460 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) 1461 { 1462 struct ixgbe_l2_tn_info *l2_tn_info = 1463 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1464 char l2_tn_hash_name[RTE_HASH_NAMESIZE]; 1465 struct rte_hash_parameters l2_tn_hash_params = { 1466 .name = l2_tn_hash_name, 1467 .entries = IXGBE_MAX_L2_TN_FILTER_NUM, 1468 .key_len = sizeof(struct ixgbe_l2_tn_key), 1469 .hash_func = rte_hash_crc, 1470 .hash_func_init_val = 0, 1471 .socket_id = rte_socket_id(), 1472 }; 1473 1474 TAILQ_INIT(&l2_tn_info->l2_tn_list); 1475 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE, 1476 "l2_tn_%s", eth_dev->device->name); 1477 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params); 1478 if (!l2_tn_info->hash_handle) { 1479 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!"); 1480 return -EINVAL; 1481 } 1482 l2_tn_info->hash_map = rte_zmalloc("ixgbe", 1483 sizeof(struct ixgbe_l2_tn_filter *) * 1484 IXGBE_MAX_L2_TN_FILTER_NUM, 1485 0); 1486 if (!l2_tn_info->hash_map) { 1487 PMD_INIT_LOG(ERR, 1488 "Failed to allocate memory for L2 TN hash map!"); 1489 return -ENOMEM; 1490 } 1491 l2_tn_info->e_tag_en = FALSE; 1492 l2_tn_info->e_tag_fwd_en = FALSE; 1493 l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG; 1494 1495 return 0; 1496 } 1497 /* 1498 * Negotiate mailbox API version with the PF. 1499 * After reset API version is always set to the basic one (ixgbe_mbox_api_10). 1500 * Then we try to negotiate starting with the most recent one. 1501 * If all negotiation attempts fail, then we will proceed with 1502 * the default one (ixgbe_mbox_api_10). 1503 */ 1504 static void 1505 ixgbevf_negotiate_api(struct ixgbe_hw *hw) 1506 { 1507 int32_t i; 1508 1509 /* start with highest supported, proceed down */ 1510 static const enum ixgbe_pfvf_api_rev sup_ver[] = { 1511 ixgbe_mbox_api_12, 1512 ixgbe_mbox_api_11, 1513 ixgbe_mbox_api_10, 1514 }; 1515 1516 for (i = 0; 1517 i != RTE_DIM(sup_ver) && 1518 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0; 1519 i++) 1520 ; 1521 } 1522 1523 static void 1524 generate_random_mac_addr(struct ether_addr *mac_addr) 1525 { 1526 uint64_t random; 1527 1528 /* Set Organizationally Unique Identifier (OUI) prefix. */ 1529 mac_addr->addr_bytes[0] = 0x00; 1530 mac_addr->addr_bytes[1] = 0x09; 1531 mac_addr->addr_bytes[2] = 0xC0; 1532 /* Force indication of locally assigned MAC address. */ 1533 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR; 1534 /* Generate the last 3 bytes of the MAC address with a random number. */ 1535 random = rte_rand(); 1536 memcpy(&mac_addr->addr_bytes[3], &random, 3); 1537 } 1538 1539 /* 1540 * Virtual Function device init 1541 */ 1542 static int 1543 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev) 1544 { 1545 int diag; 1546 uint32_t tc, tcs; 1547 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1548 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1549 struct ixgbe_hw *hw = 1550 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1551 struct ixgbe_vfta *shadow_vfta = 1552 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1553 struct ixgbe_hwstrip *hwstrip = 1554 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1555 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr; 1556 1557 PMD_INIT_FUNC_TRACE(); 1558 1559 eth_dev->dev_ops = &ixgbevf_eth_dev_ops; 1560 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1561 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1562 1563 /* for secondary processes, we don't initialise any further as primary 1564 * has already done this work. Only check we don't need a different 1565 * RX function 1566 */ 1567 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1568 struct ixgbe_tx_queue *txq; 1569 /* TX queue function in primary, set by last queue initialized 1570 * Tx queue may not initialized by primary process 1571 */ 1572 if (eth_dev->data->tx_queues) { 1573 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1]; 1574 ixgbe_set_tx_function(eth_dev, txq); 1575 } else { 1576 /* Use default TX function if we get here */ 1577 PMD_INIT_LOG(NOTICE, 1578 "No TX queues configured yet. Using default TX function."); 1579 } 1580 1581 ixgbe_set_rx_function(eth_dev); 1582 1583 return 0; 1584 } 1585 1586 rte_eth_copy_pci_info(eth_dev, pci_dev); 1587 1588 hw->device_id = pci_dev->id.device_id; 1589 hw->vendor_id = pci_dev->id.vendor_id; 1590 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1591 1592 /* initialize the vfta */ 1593 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1594 1595 /* initialize the hw strip bitmap*/ 1596 memset(hwstrip, 0, sizeof(*hwstrip)); 1597 1598 /* Initialize the shared code (base driver) */ 1599 diag = ixgbe_init_shared_code(hw); 1600 if (diag != IXGBE_SUCCESS) { 1601 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag); 1602 return -EIO; 1603 } 1604 1605 /* init_mailbox_params */ 1606 hw->mbx.ops.init_params(hw); 1607 1608 /* Reset the hw statistics */ 1609 ixgbevf_dev_stats_reset(eth_dev); 1610 1611 /* Disable the interrupts for VF */ 1612 ixgbevf_intr_disable(eth_dev); 1613 1614 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */ 1615 diag = hw->mac.ops.reset_hw(hw); 1616 1617 /* 1618 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when 1619 * the underlying PF driver has not assigned a MAC address to the VF. 1620 * In this case, assign a random MAC address. 1621 */ 1622 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) { 1623 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1624 /* 1625 * This error code will be propagated to the app by 1626 * rte_eth_dev_reset, so use a public error code rather than 1627 * the internal-only IXGBE_ERR_RESET_FAILED 1628 */ 1629 return -EAGAIN; 1630 } 1631 1632 /* negotiate mailbox API version to use with the PF. */ 1633 ixgbevf_negotiate_api(hw); 1634 1635 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */ 1636 ixgbevf_get_queues(hw, &tcs, &tc); 1637 1638 /* Allocate memory for storing MAC addresses */ 1639 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN * 1640 hw->mac.num_rar_entries, 0); 1641 if (eth_dev->data->mac_addrs == NULL) { 1642 PMD_INIT_LOG(ERR, 1643 "Failed to allocate %u bytes needed to store " 1644 "MAC addresses", 1645 ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1646 return -ENOMEM; 1647 } 1648 1649 /* Generate a random MAC address, if none was assigned by PF. */ 1650 if (is_zero_ether_addr(perm_addr)) { 1651 generate_random_mac_addr(perm_addr); 1652 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1); 1653 if (diag) { 1654 rte_free(eth_dev->data->mac_addrs); 1655 eth_dev->data->mac_addrs = NULL; 1656 return diag; 1657 } 1658 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF"); 1659 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address " 1660 "%02x:%02x:%02x:%02x:%02x:%02x", 1661 perm_addr->addr_bytes[0], 1662 perm_addr->addr_bytes[1], 1663 perm_addr->addr_bytes[2], 1664 perm_addr->addr_bytes[3], 1665 perm_addr->addr_bytes[4], 1666 perm_addr->addr_bytes[5]); 1667 } 1668 1669 /* Copy the permanent MAC address */ 1670 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]); 1671 1672 /* reset the hardware with the new settings */ 1673 diag = hw->mac.ops.start_hw(hw); 1674 switch (diag) { 1675 case 0: 1676 break; 1677 1678 default: 1679 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1680 return -EIO; 1681 } 1682 1683 rte_intr_callback_register(intr_handle, 1684 ixgbevf_dev_interrupt_handler, eth_dev); 1685 rte_intr_enable(intr_handle); 1686 ixgbevf_intr_enable(eth_dev); 1687 1688 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s", 1689 eth_dev->data->port_id, pci_dev->id.vendor_id, 1690 pci_dev->id.device_id, "ixgbe_mac_82599_vf"); 1691 1692 return 0; 1693 } 1694 1695 /* Virtual Function device uninit */ 1696 1697 static int 1698 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev) 1699 { 1700 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1701 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1702 struct ixgbe_hw *hw; 1703 1704 PMD_INIT_FUNC_TRACE(); 1705 1706 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1707 return 0; 1708 1709 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1710 1711 if (hw->adapter_stopped == 0) 1712 ixgbevf_dev_close(eth_dev); 1713 1714 eth_dev->dev_ops = NULL; 1715 eth_dev->rx_pkt_burst = NULL; 1716 eth_dev->tx_pkt_burst = NULL; 1717 1718 /* Disable the interrupts for VF */ 1719 ixgbevf_intr_disable(eth_dev); 1720 1721 rte_intr_disable(intr_handle); 1722 rte_intr_callback_unregister(intr_handle, 1723 ixgbevf_dev_interrupt_handler, eth_dev); 1724 1725 return 0; 1726 } 1727 1728 static int 1729 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1730 struct rte_pci_device *pci_dev) 1731 { 1732 char name[RTE_ETH_NAME_MAX_LEN]; 1733 struct rte_eth_dev *pf_ethdev; 1734 struct rte_eth_devargs eth_da; 1735 int i, retval; 1736 1737 if (pci_dev->device.devargs) { 1738 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 1739 ð_da); 1740 if (retval) 1741 return retval; 1742 } else 1743 memset(ð_da, 0, sizeof(eth_da)); 1744 1745 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 1746 sizeof(struct ixgbe_adapter), 1747 eth_dev_pci_specific_init, pci_dev, 1748 eth_ixgbe_dev_init, NULL); 1749 1750 if (retval || eth_da.nb_representor_ports < 1) 1751 return retval; 1752 1753 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1754 if (pf_ethdev == NULL) 1755 return -ENODEV; 1756 1757 /* probe VF representor ports */ 1758 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1759 struct ixgbe_vf_info *vfinfo; 1760 struct ixgbe_vf_representor representor; 1761 1762 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA( 1763 pf_ethdev->data->dev_private); 1764 if (vfinfo == NULL) { 1765 PMD_DRV_LOG(ERR, 1766 "no virtual functions supported by PF"); 1767 break; 1768 } 1769 1770 representor.vf_id = eth_da.representor_ports[i]; 1771 representor.switch_domain_id = vfinfo->switch_domain_id; 1772 representor.pf_ethdev = pf_ethdev; 1773 1774 /* representor port net_bdf_port */ 1775 snprintf(name, sizeof(name), "net_%s_representor_%d", 1776 pci_dev->device.name, 1777 eth_da.representor_ports[i]); 1778 1779 retval = rte_eth_dev_create(&pci_dev->device, name, 1780 sizeof(struct ixgbe_vf_representor), NULL, NULL, 1781 ixgbe_vf_representor_init, &representor); 1782 1783 if (retval) 1784 PMD_DRV_LOG(ERR, "failed to create ixgbe vf " 1785 "representor %s.", name); 1786 } 1787 1788 return 0; 1789 } 1790 1791 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev) 1792 { 1793 struct rte_eth_dev *ethdev; 1794 1795 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1796 if (!ethdev) 1797 return -ENODEV; 1798 1799 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 1800 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit); 1801 else 1802 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit); 1803 } 1804 1805 static struct rte_pci_driver rte_ixgbe_pmd = { 1806 .id_table = pci_id_ixgbe_map, 1807 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 1808 RTE_PCI_DRV_IOVA_AS_VA, 1809 .probe = eth_ixgbe_pci_probe, 1810 .remove = eth_ixgbe_pci_remove, 1811 }; 1812 1813 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1814 struct rte_pci_device *pci_dev) 1815 { 1816 return rte_eth_dev_pci_generic_probe(pci_dev, 1817 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init); 1818 } 1819 1820 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev) 1821 { 1822 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit); 1823 } 1824 1825 /* 1826 * virtual function driver struct 1827 */ 1828 static struct rte_pci_driver rte_ixgbevf_pmd = { 1829 .id_table = pci_id_ixgbevf_map, 1830 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA, 1831 .probe = eth_ixgbevf_pci_probe, 1832 .remove = eth_ixgbevf_pci_remove, 1833 }; 1834 1835 static int 1836 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1837 { 1838 struct ixgbe_hw *hw = 1839 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1840 struct ixgbe_vfta *shadow_vfta = 1841 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1842 uint32_t vfta; 1843 uint32_t vid_idx; 1844 uint32_t vid_bit; 1845 1846 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 1847 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 1848 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx)); 1849 if (on) 1850 vfta |= vid_bit; 1851 else 1852 vfta &= ~vid_bit; 1853 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta); 1854 1855 /* update local VFTA copy */ 1856 shadow_vfta->vfta[vid_idx] = vfta; 1857 1858 return 0; 1859 } 1860 1861 static void 1862 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 1863 { 1864 if (on) 1865 ixgbe_vlan_hw_strip_enable(dev, queue); 1866 else 1867 ixgbe_vlan_hw_strip_disable(dev, queue); 1868 } 1869 1870 static int 1871 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1872 enum rte_vlan_type vlan_type, 1873 uint16_t tpid) 1874 { 1875 struct ixgbe_hw *hw = 1876 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1877 int ret = 0; 1878 uint32_t reg; 1879 uint32_t qinq; 1880 1881 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1882 qinq &= IXGBE_DMATXCTL_GDV; 1883 1884 switch (vlan_type) { 1885 case ETH_VLAN_TYPE_INNER: 1886 if (qinq) { 1887 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1888 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1889 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1890 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1891 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1892 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1893 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1894 } else { 1895 ret = -ENOTSUP; 1896 PMD_DRV_LOG(ERR, "Inner type is not supported" 1897 " by single VLAN"); 1898 } 1899 break; 1900 case ETH_VLAN_TYPE_OUTER: 1901 if (qinq) { 1902 /* Only the high 16-bits is valid */ 1903 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid << 1904 IXGBE_EXVET_VET_EXT_SHIFT); 1905 } else { 1906 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1907 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1908 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1909 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1910 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1911 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1912 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1913 } 1914 1915 break; 1916 default: 1917 ret = -EINVAL; 1918 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type); 1919 break; 1920 } 1921 1922 return ret; 1923 } 1924 1925 void 1926 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev) 1927 { 1928 struct ixgbe_hw *hw = 1929 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1930 uint32_t vlnctrl; 1931 1932 PMD_INIT_FUNC_TRACE(); 1933 1934 /* Filter Table Disable */ 1935 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1936 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 1937 1938 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1939 } 1940 1941 void 1942 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1943 { 1944 struct ixgbe_hw *hw = 1945 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1946 struct ixgbe_vfta *shadow_vfta = 1947 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1948 uint32_t vlnctrl; 1949 uint16_t i; 1950 1951 PMD_INIT_FUNC_TRACE(); 1952 1953 /* Filter Table Enable */ 1954 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1955 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; 1956 vlnctrl |= IXGBE_VLNCTRL_VFE; 1957 1958 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1959 1960 /* write whatever is in local vfta copy */ 1961 for (i = 0; i < IXGBE_VFTA_SIZE; i++) 1962 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]); 1963 } 1964 1965 static void 1966 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on) 1967 { 1968 struct ixgbe_hwstrip *hwstrip = 1969 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private); 1970 struct ixgbe_rx_queue *rxq; 1971 1972 if (queue >= IXGBE_MAX_RX_QUEUE_NUM) 1973 return; 1974 1975 if (on) 1976 IXGBE_SET_HWSTRIP(hwstrip, queue); 1977 else 1978 IXGBE_CLEAR_HWSTRIP(hwstrip, queue); 1979 1980 if (queue >= dev->data->nb_rx_queues) 1981 return; 1982 1983 rxq = dev->data->rx_queues[queue]; 1984 1985 if (on) { 1986 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; 1987 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 1988 } else { 1989 rxq->vlan_flags = PKT_RX_VLAN; 1990 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 1991 } 1992 } 1993 1994 static void 1995 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue) 1996 { 1997 struct ixgbe_hw *hw = 1998 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1999 uint32_t ctrl; 2000 2001 PMD_INIT_FUNC_TRACE(); 2002 2003 if (hw->mac.type == ixgbe_mac_82598EB) { 2004 /* No queue level support */ 2005 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2006 return; 2007 } 2008 2009 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2010 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2011 ctrl &= ~IXGBE_RXDCTL_VME; 2012 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2013 2014 /* record those setting for HW strip per queue */ 2015 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0); 2016 } 2017 2018 static void 2019 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue) 2020 { 2021 struct ixgbe_hw *hw = 2022 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2023 uint32_t ctrl; 2024 2025 PMD_INIT_FUNC_TRACE(); 2026 2027 if (hw->mac.type == ixgbe_mac_82598EB) { 2028 /* No queue level supported */ 2029 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2030 return; 2031 } 2032 2033 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2034 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2035 ctrl |= IXGBE_RXDCTL_VME; 2036 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2037 2038 /* record those setting for HW strip per queue */ 2039 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1); 2040 } 2041 2042 static void 2043 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev) 2044 { 2045 struct ixgbe_hw *hw = 2046 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2047 uint32_t ctrl; 2048 2049 PMD_INIT_FUNC_TRACE(); 2050 2051 /* DMATXCTRL: Geric Double VLAN Disable */ 2052 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2053 ctrl &= ~IXGBE_DMATXCTL_GDV; 2054 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2055 2056 /* CTRL_EXT: Global Double VLAN Disable */ 2057 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2058 ctrl &= ~IXGBE_EXTENDED_VLAN; 2059 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2060 2061 } 2062 2063 static void 2064 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) 2065 { 2066 struct ixgbe_hw *hw = 2067 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2068 uint32_t ctrl; 2069 2070 PMD_INIT_FUNC_TRACE(); 2071 2072 /* DMATXCTRL: Geric Double VLAN Enable */ 2073 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2074 ctrl |= IXGBE_DMATXCTL_GDV; 2075 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2076 2077 /* CTRL_EXT: Global Double VLAN Enable */ 2078 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2079 ctrl |= IXGBE_EXTENDED_VLAN; 2080 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2081 2082 /* Clear pooling mode of PFVTCTL. It's required by X550. */ 2083 if (hw->mac.type == ixgbe_mac_X550 || 2084 hw->mac.type == ixgbe_mac_X550EM_x || 2085 hw->mac.type == ixgbe_mac_X550EM_a) { 2086 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 2087 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 2088 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 2089 } 2090 2091 /* 2092 * VET EXT field in the EXVET register = 0x8100 by default 2093 * So no need to change. Same to VT field of DMATXCTL register 2094 */ 2095 } 2096 2097 void 2098 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev) 2099 { 2100 struct ixgbe_hw *hw = 2101 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2102 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 2103 uint32_t ctrl; 2104 uint16_t i; 2105 struct ixgbe_rx_queue *rxq; 2106 bool on; 2107 2108 PMD_INIT_FUNC_TRACE(); 2109 2110 if (hw->mac.type == ixgbe_mac_82598EB) { 2111 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2112 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2113 ctrl |= IXGBE_VLNCTRL_VME; 2114 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2115 } else { 2116 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2117 ctrl &= ~IXGBE_VLNCTRL_VME; 2118 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2119 } 2120 } else { 2121 /* 2122 * Other 10G NIC, the VLAN strip can be setup 2123 * per queue in RXDCTL 2124 */ 2125 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2126 rxq = dev->data->rx_queues[i]; 2127 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx)); 2128 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2129 ctrl |= IXGBE_RXDCTL_VME; 2130 on = TRUE; 2131 } else { 2132 ctrl &= ~IXGBE_RXDCTL_VME; 2133 on = FALSE; 2134 } 2135 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl); 2136 2137 /* record those setting for HW strip per queue */ 2138 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on); 2139 } 2140 } 2141 } 2142 2143 static void 2144 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask) 2145 { 2146 uint16_t i; 2147 struct rte_eth_rxmode *rxmode; 2148 struct ixgbe_rx_queue *rxq; 2149 2150 if (mask & ETH_VLAN_STRIP_MASK) { 2151 rxmode = &dev->data->dev_conf.rxmode; 2152 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 2153 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2154 rxq = dev->data->rx_queues[i]; 2155 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 2156 } 2157 else 2158 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2159 rxq = dev->data->rx_queues[i]; 2160 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 2161 } 2162 } 2163 } 2164 2165 static int 2166 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask) 2167 { 2168 struct rte_eth_rxmode *rxmode; 2169 rxmode = &dev->data->dev_conf.rxmode; 2170 2171 if (mask & ETH_VLAN_STRIP_MASK) { 2172 ixgbe_vlan_hw_strip_config(dev); 2173 } 2174 2175 if (mask & ETH_VLAN_FILTER_MASK) { 2176 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 2177 ixgbe_vlan_hw_filter_enable(dev); 2178 else 2179 ixgbe_vlan_hw_filter_disable(dev); 2180 } 2181 2182 if (mask & ETH_VLAN_EXTEND_MASK) { 2183 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2184 ixgbe_vlan_hw_extend_enable(dev); 2185 else 2186 ixgbe_vlan_hw_extend_disable(dev); 2187 } 2188 2189 return 0; 2190 } 2191 2192 static int 2193 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2194 { 2195 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 2196 2197 ixgbe_vlan_offload_config(dev, mask); 2198 2199 return 0; 2200 } 2201 2202 static void 2203 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev) 2204 { 2205 struct ixgbe_hw *hw = 2206 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2207 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */ 2208 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2209 2210 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */ 2211 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl); 2212 } 2213 2214 static int 2215 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q) 2216 { 2217 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2218 2219 switch (nb_rx_q) { 2220 case 1: 2221 case 2: 2222 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS; 2223 break; 2224 case 4: 2225 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS; 2226 break; 2227 default: 2228 return -EINVAL; 2229 } 2230 2231 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 2232 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2233 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 2234 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2235 return 0; 2236 } 2237 2238 static int 2239 ixgbe_check_mq_mode(struct rte_eth_dev *dev) 2240 { 2241 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 2242 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2243 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2244 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2245 2246 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 2247 /* check multi-queue mode */ 2248 switch (dev_conf->rxmode.mq_mode) { 2249 case ETH_MQ_RX_VMDQ_DCB: 2250 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV"); 2251 break; 2252 case ETH_MQ_RX_VMDQ_DCB_RSS: 2253 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */ 2254 PMD_INIT_LOG(ERR, "SRIOV active," 2255 " unsupported mq_mode rx %d.", 2256 dev_conf->rxmode.mq_mode); 2257 return -EINVAL; 2258 case ETH_MQ_RX_RSS: 2259 case ETH_MQ_RX_VMDQ_RSS: 2260 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS; 2261 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) 2262 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) { 2263 PMD_INIT_LOG(ERR, "SRIOV is active," 2264 " invalid queue number" 2265 " for VMDQ RSS, allowed" 2266 " value are 1, 2 or 4."); 2267 return -EINVAL; 2268 } 2269 break; 2270 case ETH_MQ_RX_VMDQ_ONLY: 2271 case ETH_MQ_RX_NONE: 2272 /* if nothing mq mode configure, use default scheme */ 2273 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY; 2274 break; 2275 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/ 2276 /* SRIOV only works in VMDq enable mode */ 2277 PMD_INIT_LOG(ERR, "SRIOV is active," 2278 " wrong mq_mode rx %d.", 2279 dev_conf->rxmode.mq_mode); 2280 return -EINVAL; 2281 } 2282 2283 switch (dev_conf->txmode.mq_mode) { 2284 case ETH_MQ_TX_VMDQ_DCB: 2285 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV"); 2286 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB; 2287 break; 2288 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */ 2289 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY; 2290 break; 2291 } 2292 2293 /* check valid queue number */ 2294 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) || 2295 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) { 2296 PMD_INIT_LOG(ERR, "SRIOV is active," 2297 " nb_rx_q=%d nb_tx_q=%d queue number" 2298 " must be less than or equal to %d.", 2299 nb_rx_q, nb_tx_q, 2300 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool); 2301 return -EINVAL; 2302 } 2303 } else { 2304 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) { 2305 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is" 2306 " not supported."); 2307 return -EINVAL; 2308 } 2309 /* check configuration for vmdb+dcb mode */ 2310 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) { 2311 const struct rte_eth_vmdq_dcb_conf *conf; 2312 2313 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2314 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.", 2315 IXGBE_VMDQ_DCB_NB_QUEUES); 2316 return -EINVAL; 2317 } 2318 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf; 2319 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2320 conf->nb_queue_pools == ETH_32_POOLS)) { 2321 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2322 " nb_queue_pools must be %d or %d.", 2323 ETH_16_POOLS, ETH_32_POOLS); 2324 return -EINVAL; 2325 } 2326 } 2327 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) { 2328 const struct rte_eth_vmdq_dcb_tx_conf *conf; 2329 2330 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2331 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d", 2332 IXGBE_VMDQ_DCB_NB_QUEUES); 2333 return -EINVAL; 2334 } 2335 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf; 2336 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2337 conf->nb_queue_pools == ETH_32_POOLS)) { 2338 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2339 " nb_queue_pools != %d and" 2340 " nb_queue_pools != %d.", 2341 ETH_16_POOLS, ETH_32_POOLS); 2342 return -EINVAL; 2343 } 2344 } 2345 2346 /* For DCB mode check our configuration before we go further */ 2347 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) { 2348 const struct rte_eth_dcb_rx_conf *conf; 2349 2350 conf = &dev_conf->rx_adv_conf.dcb_rx_conf; 2351 if (!(conf->nb_tcs == ETH_4_TCS || 2352 conf->nb_tcs == ETH_8_TCS)) { 2353 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2354 " and nb_tcs != %d.", 2355 ETH_4_TCS, ETH_8_TCS); 2356 return -EINVAL; 2357 } 2358 } 2359 2360 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) { 2361 const struct rte_eth_dcb_tx_conf *conf; 2362 2363 conf = &dev_conf->tx_adv_conf.dcb_tx_conf; 2364 if (!(conf->nb_tcs == ETH_4_TCS || 2365 conf->nb_tcs == ETH_8_TCS)) { 2366 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2367 " and nb_tcs != %d.", 2368 ETH_4_TCS, ETH_8_TCS); 2369 return -EINVAL; 2370 } 2371 } 2372 2373 /* 2374 * When DCB/VT is off, maximum number of queues changes, 2375 * except for 82598EB, which remains constant. 2376 */ 2377 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 2378 hw->mac.type != ixgbe_mac_82598EB) { 2379 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) { 2380 PMD_INIT_LOG(ERR, 2381 "Neither VT nor DCB are enabled, " 2382 "nb_tx_q > %d.", 2383 IXGBE_NONE_MODE_TX_NB_QUEUES); 2384 return -EINVAL; 2385 } 2386 } 2387 } 2388 return 0; 2389 } 2390 2391 static int 2392 ixgbe_dev_configure(struct rte_eth_dev *dev) 2393 { 2394 struct ixgbe_interrupt *intr = 2395 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2396 struct ixgbe_adapter *adapter = 2397 (struct ixgbe_adapter *)dev->data->dev_private; 2398 int ret; 2399 2400 PMD_INIT_FUNC_TRACE(); 2401 /* multipe queue mode checking */ 2402 ret = ixgbe_check_mq_mode(dev); 2403 if (ret != 0) { 2404 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.", 2405 ret); 2406 return ret; 2407 } 2408 2409 /* set flag to update link status after init */ 2410 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2411 2412 /* 2413 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 2414 * allocation or vector Rx preconditions we will reset it. 2415 */ 2416 adapter->rx_bulk_alloc_allowed = true; 2417 adapter->rx_vec_allowed = true; 2418 2419 return 0; 2420 } 2421 2422 static void 2423 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) 2424 { 2425 struct ixgbe_hw *hw = 2426 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2427 struct ixgbe_interrupt *intr = 2428 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2429 uint32_t gpie; 2430 2431 /* only set up it on X550EM_X */ 2432 if (hw->mac.type == ixgbe_mac_X550EM_x) { 2433 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 2434 gpie |= IXGBE_SDP0_GPIEN_X550EM_x; 2435 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 2436 if (hw->phy.type == ixgbe_phy_x550em_ext_t) 2437 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x; 2438 } 2439 } 2440 2441 int 2442 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 2443 uint16_t tx_rate, uint64_t q_msk) 2444 { 2445 struct ixgbe_hw *hw; 2446 struct ixgbe_vf_info *vfinfo; 2447 struct rte_eth_link link; 2448 uint8_t nb_q_per_pool; 2449 uint32_t queue_stride; 2450 uint32_t queue_idx, idx = 0, vf_idx; 2451 uint32_t queue_end; 2452 uint16_t total_rate = 0; 2453 struct rte_pci_device *pci_dev; 2454 2455 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2456 rte_eth_link_get_nowait(dev->data->port_id, &link); 2457 2458 if (vf >= pci_dev->max_vfs) 2459 return -EINVAL; 2460 2461 if (tx_rate > link.link_speed) 2462 return -EINVAL; 2463 2464 if (q_msk == 0) 2465 return 0; 2466 2467 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2468 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 2469 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2470 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2471 queue_idx = vf * queue_stride; 2472 queue_end = queue_idx + nb_q_per_pool - 1; 2473 if (queue_end >= hw->mac.max_tx_queues) 2474 return -EINVAL; 2475 2476 if (vfinfo) { 2477 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) { 2478 if (vf_idx == vf) 2479 continue; 2480 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate); 2481 idx++) 2482 total_rate += vfinfo[vf_idx].tx_rate[idx]; 2483 } 2484 } else { 2485 return -EINVAL; 2486 } 2487 2488 /* Store tx_rate for this vf. */ 2489 for (idx = 0; idx < nb_q_per_pool; idx++) { 2490 if (((uint64_t)0x1 << idx) & q_msk) { 2491 if (vfinfo[vf].tx_rate[idx] != tx_rate) 2492 vfinfo[vf].tx_rate[idx] = tx_rate; 2493 total_rate += tx_rate; 2494 } 2495 } 2496 2497 if (total_rate > dev->data->dev_link.link_speed) { 2498 /* Reset stored TX rate of the VF if it causes exceed 2499 * link speed. 2500 */ 2501 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate)); 2502 return -EINVAL; 2503 } 2504 2505 /* Set RTTBCNRC of each queue/pool for vf X */ 2506 for (; queue_idx <= queue_end; queue_idx++) { 2507 if (0x1 & q_msk) 2508 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate); 2509 q_msk = q_msk >> 1; 2510 } 2511 2512 return 0; 2513 } 2514 2515 /* 2516 * Configure device link speed and setup link. 2517 * It returns 0 on success. 2518 */ 2519 static int 2520 ixgbe_dev_start(struct rte_eth_dev *dev) 2521 { 2522 struct ixgbe_hw *hw = 2523 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2524 struct ixgbe_vf_info *vfinfo = 2525 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2526 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2527 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2528 uint32_t intr_vector = 0; 2529 int err, link_up = 0, negotiate = 0; 2530 uint32_t speed = 0; 2531 uint32_t allowed_speeds = 0; 2532 int mask = 0; 2533 int status; 2534 uint16_t vf, idx; 2535 uint32_t *link_speeds; 2536 struct ixgbe_tm_conf *tm_conf = 2537 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2538 2539 PMD_INIT_FUNC_TRACE(); 2540 2541 /* IXGBE devices don't support: 2542 * - half duplex (checked afterwards for valid speeds) 2543 * - fixed speed: TODO implement 2544 */ 2545 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) { 2546 PMD_INIT_LOG(ERR, 2547 "Invalid link_speeds for port %u, fix speed not supported", 2548 dev->data->port_id); 2549 return -EINVAL; 2550 } 2551 2552 /* Stop the link setup handler before resetting the HW. */ 2553 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 2554 2555 /* disable uio/vfio intr/eventfd mapping */ 2556 rte_intr_disable(intr_handle); 2557 2558 /* stop adapter */ 2559 hw->adapter_stopped = 0; 2560 ixgbe_stop_adapter(hw); 2561 2562 /* reinitialize adapter 2563 * this calls reset and start 2564 */ 2565 status = ixgbe_pf_reset_hw(hw); 2566 if (status != 0) 2567 return -1; 2568 hw->mac.ops.start_hw(hw); 2569 hw->mac.get_link_status = true; 2570 2571 /* configure PF module if SRIOV enabled */ 2572 ixgbe_pf_host_configure(dev); 2573 2574 ixgbe_dev_phy_intr_setup(dev); 2575 2576 /* check and configure queue intr-vector mapping */ 2577 if ((rte_intr_cap_multiple(intr_handle) || 2578 !RTE_ETH_DEV_SRIOV(dev).active) && 2579 dev->data->dev_conf.intr_conf.rxq != 0) { 2580 intr_vector = dev->data->nb_rx_queues; 2581 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) { 2582 PMD_INIT_LOG(ERR, "At most %d intr queues supported", 2583 IXGBE_MAX_INTR_QUEUE_NUM); 2584 return -ENOTSUP; 2585 } 2586 if (rte_intr_efd_enable(intr_handle, intr_vector)) 2587 return -1; 2588 } 2589 2590 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 2591 intr_handle->intr_vec = 2592 rte_zmalloc("intr_vec", 2593 dev->data->nb_rx_queues * sizeof(int), 0); 2594 if (intr_handle->intr_vec == NULL) { 2595 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 2596 " intr_vec", dev->data->nb_rx_queues); 2597 return -ENOMEM; 2598 } 2599 } 2600 2601 /* confiugre msix for sleep until rx interrupt */ 2602 ixgbe_configure_msix(dev); 2603 2604 /* initialize transmission unit */ 2605 ixgbe_dev_tx_init(dev); 2606 2607 /* This can fail when allocating mbufs for descriptor rings */ 2608 err = ixgbe_dev_rx_init(dev); 2609 if (err) { 2610 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 2611 goto error; 2612 } 2613 2614 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 2615 ETH_VLAN_EXTEND_MASK; 2616 err = ixgbe_vlan_offload_config(dev, mask); 2617 if (err) { 2618 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 2619 goto error; 2620 } 2621 2622 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) { 2623 /* Enable vlan filtering for VMDq */ 2624 ixgbe_vmdq_vlan_hw_filter_enable(dev); 2625 } 2626 2627 /* Configure DCB hw */ 2628 ixgbe_configure_dcb(dev); 2629 2630 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) { 2631 err = ixgbe_fdir_configure(dev); 2632 if (err) 2633 goto error; 2634 } 2635 2636 /* Restore vf rate limit */ 2637 if (vfinfo != NULL) { 2638 for (vf = 0; vf < pci_dev->max_vfs; vf++) 2639 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++) 2640 if (vfinfo[vf].tx_rate[idx] != 0) 2641 ixgbe_set_vf_rate_limit( 2642 dev, vf, 2643 vfinfo[vf].tx_rate[idx], 2644 1 << idx); 2645 } 2646 2647 ixgbe_restore_statistics_mapping(dev); 2648 2649 err = ixgbe_dev_rxtx_start(dev); 2650 if (err < 0) { 2651 PMD_INIT_LOG(ERR, "Unable to start rxtx queues"); 2652 goto error; 2653 } 2654 2655 /* Skip link setup if loopback mode is enabled. */ 2656 if (dev->data->dev_conf.lpbk_mode != 0) { 2657 err = ixgbe_check_supported_loopback_mode(dev); 2658 if (err < 0) { 2659 PMD_INIT_LOG(ERR, "Unsupported loopback mode"); 2660 goto error; 2661 } else { 2662 goto skip_link_setup; 2663 } 2664 } 2665 2666 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) { 2667 err = hw->mac.ops.setup_sfp(hw); 2668 if (err) 2669 goto error; 2670 } 2671 2672 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2673 /* Turn on the copper */ 2674 ixgbe_set_phy_power(hw, true); 2675 } else { 2676 /* Turn on the laser */ 2677 ixgbe_enable_tx_laser(hw); 2678 } 2679 2680 err = ixgbe_check_link(hw, &speed, &link_up, 0); 2681 if (err) 2682 goto error; 2683 dev->data->dev_link.link_status = link_up; 2684 2685 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate); 2686 if (err) 2687 goto error; 2688 2689 switch (hw->mac.type) { 2690 case ixgbe_mac_X550: 2691 case ixgbe_mac_X550EM_x: 2692 case ixgbe_mac_X550EM_a: 2693 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2694 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G | 2695 ETH_LINK_SPEED_10G; 2696 break; 2697 default: 2698 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2699 ETH_LINK_SPEED_10G; 2700 } 2701 2702 link_speeds = &dev->data->dev_conf.link_speeds; 2703 if (*link_speeds & ~allowed_speeds) { 2704 PMD_INIT_LOG(ERR, "Invalid link setting"); 2705 goto error; 2706 } 2707 2708 speed = 0x0; 2709 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) { 2710 switch (hw->mac.type) { 2711 case ixgbe_mac_82598EB: 2712 speed = IXGBE_LINK_SPEED_82598_AUTONEG; 2713 break; 2714 case ixgbe_mac_82599EB: 2715 case ixgbe_mac_X540: 2716 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2717 break; 2718 case ixgbe_mac_X550: 2719 case ixgbe_mac_X550EM_x: 2720 case ixgbe_mac_X550EM_a: 2721 speed = IXGBE_LINK_SPEED_X550_AUTONEG; 2722 break; 2723 default: 2724 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2725 } 2726 } else { 2727 if (*link_speeds & ETH_LINK_SPEED_10G) 2728 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2729 if (*link_speeds & ETH_LINK_SPEED_5G) 2730 speed |= IXGBE_LINK_SPEED_5GB_FULL; 2731 if (*link_speeds & ETH_LINK_SPEED_2_5G) 2732 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 2733 if (*link_speeds & ETH_LINK_SPEED_1G) 2734 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2735 if (*link_speeds & ETH_LINK_SPEED_100M) 2736 speed |= IXGBE_LINK_SPEED_100_FULL; 2737 } 2738 2739 err = ixgbe_setup_link(hw, speed, link_up); 2740 if (err) 2741 goto error; 2742 2743 skip_link_setup: 2744 2745 if (rte_intr_allow_others(intr_handle)) { 2746 /* check if lsc interrupt is enabled */ 2747 if (dev->data->dev_conf.intr_conf.lsc != 0) 2748 ixgbe_dev_lsc_interrupt_setup(dev, TRUE); 2749 else 2750 ixgbe_dev_lsc_interrupt_setup(dev, FALSE); 2751 ixgbe_dev_macsec_interrupt_setup(dev); 2752 } else { 2753 rte_intr_callback_unregister(intr_handle, 2754 ixgbe_dev_interrupt_handler, dev); 2755 if (dev->data->dev_conf.intr_conf.lsc != 0) 2756 PMD_INIT_LOG(INFO, "lsc won't enable because of" 2757 " no intr multiplex"); 2758 } 2759 2760 /* check if rxq interrupt is enabled */ 2761 if (dev->data->dev_conf.intr_conf.rxq != 0 && 2762 rte_intr_dp_is_en(intr_handle)) 2763 ixgbe_dev_rxq_interrupt_setup(dev); 2764 2765 /* enable uio/vfio intr/eventfd mapping */ 2766 rte_intr_enable(intr_handle); 2767 2768 /* resume enabled intr since hw reset */ 2769 ixgbe_enable_intr(dev); 2770 ixgbe_l2_tunnel_conf(dev); 2771 ixgbe_filter_restore(dev); 2772 2773 if (tm_conf->root && !tm_conf->committed) 2774 PMD_DRV_LOG(WARNING, 2775 "please call hierarchy_commit() " 2776 "before starting the port"); 2777 2778 /* 2779 * Update link status right before return, because it may 2780 * start link configuration process in a separate thread. 2781 */ 2782 ixgbe_dev_link_update(dev, 0); 2783 2784 return 0; 2785 2786 error: 2787 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err); 2788 ixgbe_dev_clear_queues(dev); 2789 return -EIO; 2790 } 2791 2792 /* 2793 * Stop device: disable rx and tx functions to allow for reconfiguring. 2794 */ 2795 static void 2796 ixgbe_dev_stop(struct rte_eth_dev *dev) 2797 { 2798 struct rte_eth_link link; 2799 struct ixgbe_adapter *adapter = 2800 (struct ixgbe_adapter *)dev->data->dev_private; 2801 struct ixgbe_hw *hw = 2802 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2803 struct ixgbe_vf_info *vfinfo = 2804 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2805 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2806 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2807 int vf; 2808 struct ixgbe_tm_conf *tm_conf = 2809 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2810 2811 PMD_INIT_FUNC_TRACE(); 2812 2813 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 2814 2815 /* disable interrupts */ 2816 ixgbe_disable_intr(hw); 2817 2818 /* reset the NIC */ 2819 ixgbe_pf_reset_hw(hw); 2820 hw->adapter_stopped = 0; 2821 2822 /* stop adapter */ 2823 ixgbe_stop_adapter(hw); 2824 2825 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++) 2826 vfinfo[vf].clear_to_send = false; 2827 2828 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2829 /* Turn off the copper */ 2830 ixgbe_set_phy_power(hw, false); 2831 } else { 2832 /* Turn off the laser */ 2833 ixgbe_disable_tx_laser(hw); 2834 } 2835 2836 ixgbe_dev_clear_queues(dev); 2837 2838 /* Clear stored conf */ 2839 dev->data->scattered_rx = 0; 2840 dev->data->lro = 0; 2841 2842 /* Clear recorded link status */ 2843 memset(&link, 0, sizeof(link)); 2844 rte_eth_linkstatus_set(dev, &link); 2845 2846 if (!rte_intr_allow_others(intr_handle)) 2847 /* resume to the default handler */ 2848 rte_intr_callback_register(intr_handle, 2849 ixgbe_dev_interrupt_handler, 2850 (void *)dev); 2851 2852 /* Clean datapath event and queue/vec mapping */ 2853 rte_intr_efd_disable(intr_handle); 2854 if (intr_handle->intr_vec != NULL) { 2855 rte_free(intr_handle->intr_vec); 2856 intr_handle->intr_vec = NULL; 2857 } 2858 2859 /* reset hierarchy commit */ 2860 tm_conf->committed = false; 2861 2862 adapter->rss_reta_updated = 0; 2863 } 2864 2865 /* 2866 * Set device link up: enable tx. 2867 */ 2868 static int 2869 ixgbe_dev_set_link_up(struct rte_eth_dev *dev) 2870 { 2871 struct ixgbe_hw *hw = 2872 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2873 if (hw->mac.type == ixgbe_mac_82599EB) { 2874 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2875 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2876 /* Not suported in bypass mode */ 2877 PMD_INIT_LOG(ERR, "Set link up is not supported " 2878 "by device id 0x%x", hw->device_id); 2879 return -ENOTSUP; 2880 } 2881 #endif 2882 } 2883 2884 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2885 /* Turn on the copper */ 2886 ixgbe_set_phy_power(hw, true); 2887 } else { 2888 /* Turn on the laser */ 2889 ixgbe_enable_tx_laser(hw); 2890 } 2891 2892 return 0; 2893 } 2894 2895 /* 2896 * Set device link down: disable tx. 2897 */ 2898 static int 2899 ixgbe_dev_set_link_down(struct rte_eth_dev *dev) 2900 { 2901 struct ixgbe_hw *hw = 2902 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2903 if (hw->mac.type == ixgbe_mac_82599EB) { 2904 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2905 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2906 /* Not suported in bypass mode */ 2907 PMD_INIT_LOG(ERR, "Set link down is not supported " 2908 "by device id 0x%x", hw->device_id); 2909 return -ENOTSUP; 2910 } 2911 #endif 2912 } 2913 2914 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2915 /* Turn off the copper */ 2916 ixgbe_set_phy_power(hw, false); 2917 } else { 2918 /* Turn off the laser */ 2919 ixgbe_disable_tx_laser(hw); 2920 } 2921 2922 return 0; 2923 } 2924 2925 /* 2926 * Reset and stop device. 2927 */ 2928 static void 2929 ixgbe_dev_close(struct rte_eth_dev *dev) 2930 { 2931 struct ixgbe_hw *hw = 2932 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2933 2934 PMD_INIT_FUNC_TRACE(); 2935 2936 ixgbe_pf_reset_hw(hw); 2937 2938 ixgbe_dev_stop(dev); 2939 hw->adapter_stopped = 1; 2940 2941 ixgbe_dev_free_queues(dev); 2942 2943 ixgbe_disable_pcie_master(hw); 2944 2945 /* reprogram the RAR[0] in case user changed it. */ 2946 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2947 } 2948 2949 /* 2950 * Reset PF device. 2951 */ 2952 static int 2953 ixgbe_dev_reset(struct rte_eth_dev *dev) 2954 { 2955 int ret; 2956 2957 /* When a DPDK PMD PF begin to reset PF port, it should notify all 2958 * its VF to make them align with it. The detailed notification 2959 * mechanism is PMD specific. As to ixgbe PF, it is rather complex. 2960 * To avoid unexpected behavior in VF, currently reset of PF with 2961 * SR-IOV activation is not supported. It might be supported later. 2962 */ 2963 if (dev->data->sriov.active) 2964 return -ENOTSUP; 2965 2966 ret = eth_ixgbe_dev_uninit(dev); 2967 if (ret) 2968 return ret; 2969 2970 ret = eth_ixgbe_dev_init(dev, NULL); 2971 2972 return ret; 2973 } 2974 2975 static void 2976 ixgbe_read_stats_registers(struct ixgbe_hw *hw, 2977 struct ixgbe_hw_stats *hw_stats, 2978 struct ixgbe_macsec_stats *macsec_stats, 2979 uint64_t *total_missed_rx, uint64_t *total_qbrc, 2980 uint64_t *total_qprc, uint64_t *total_qprdc) 2981 { 2982 uint32_t bprc, lxon, lxoff, total; 2983 uint32_t delta_gprc = 0; 2984 unsigned i; 2985 /* Workaround for RX byte count not including CRC bytes when CRC 2986 * strip is enabled. CRC bytes are removed from counters when crc_strip 2987 * is disabled. 2988 */ 2989 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) & 2990 IXGBE_HLREG0_RXCRCSTRP); 2991 2992 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 2993 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC); 2994 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC); 2995 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC); 2996 2997 for (i = 0; i < 8; i++) { 2998 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 2999 3000 /* global total per queue */ 3001 hw_stats->mpc[i] += mp; 3002 /* Running comprehensive total for stats display */ 3003 *total_missed_rx += hw_stats->mpc[i]; 3004 if (hw->mac.type == ixgbe_mac_82598EB) { 3005 hw_stats->rnbc[i] += 3006 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 3007 hw_stats->pxonrxc[i] += 3008 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 3009 hw_stats->pxoffrxc[i] += 3010 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 3011 } else { 3012 hw_stats->pxonrxc[i] += 3013 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 3014 hw_stats->pxoffrxc[i] += 3015 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 3016 hw_stats->pxon2offc[i] += 3017 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 3018 } 3019 hw_stats->pxontxc[i] += 3020 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 3021 hw_stats->pxofftxc[i] += 3022 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 3023 } 3024 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3025 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 3026 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 3027 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 3028 3029 delta_gprc += delta_qprc; 3030 3031 hw_stats->qprc[i] += delta_qprc; 3032 hw_stats->qptc[i] += delta_qptc; 3033 3034 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 3035 hw_stats->qbrc[i] += 3036 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32); 3037 if (crc_strip == 0) 3038 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN; 3039 3040 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 3041 hw_stats->qbtc[i] += 3042 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32); 3043 3044 hw_stats->qprdc[i] += delta_qprdc; 3045 *total_qprdc += hw_stats->qprdc[i]; 3046 3047 *total_qprc += hw_stats->qprc[i]; 3048 *total_qbrc += hw_stats->qbrc[i]; 3049 } 3050 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC); 3051 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC); 3052 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 3053 3054 /* 3055 * An errata states that gprc actually counts good + missed packets: 3056 * Workaround to set gprc to summated queue packet receives 3057 */ 3058 hw_stats->gprc = *total_qprc; 3059 3060 if (hw->mac.type != ixgbe_mac_82598EB) { 3061 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 3062 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32); 3063 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 3064 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32); 3065 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 3066 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32); 3067 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 3068 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 3069 } else { 3070 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 3071 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 3072 /* 82598 only has a counter in the high register */ 3073 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 3074 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 3075 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 3076 } 3077 uint64_t old_tpr = hw_stats->tpr; 3078 3079 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 3080 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT); 3081 3082 if (crc_strip == 0) 3083 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN; 3084 3085 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC); 3086 hw_stats->gptc += delta_gptc; 3087 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN; 3088 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN; 3089 3090 /* 3091 * Workaround: mprc hardware is incorrectly counting 3092 * broadcasts, so for now we subtract those. 3093 */ 3094 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 3095 hw_stats->bprc += bprc; 3096 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 3097 if (hw->mac.type == ixgbe_mac_82598EB) 3098 hw_stats->mprc -= bprc; 3099 3100 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 3101 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 3102 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 3103 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 3104 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 3105 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 3106 3107 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 3108 hw_stats->lxontxc += lxon; 3109 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 3110 hw_stats->lxofftxc += lxoff; 3111 total = lxon + lxoff; 3112 3113 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 3114 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 3115 hw_stats->gptc -= total; 3116 hw_stats->mptc -= total; 3117 hw_stats->ptc64 -= total; 3118 hw_stats->gotc -= total * ETHER_MIN_LEN; 3119 3120 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 3121 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 3122 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 3123 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 3124 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC); 3125 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC); 3126 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC); 3127 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 3128 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 3129 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 3130 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 3131 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 3132 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 3133 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC); 3134 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 3135 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST); 3136 /* Only read FCOE on 82599 */ 3137 if (hw->mac.type != ixgbe_mac_82598EB) { 3138 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 3139 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 3140 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 3141 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 3142 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 3143 } 3144 3145 /* Flow Director Stats registers */ 3146 if (hw->mac.type != ixgbe_mac_82598EB) { 3147 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 3148 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 3149 hw_stats->fdirustat_add += IXGBE_READ_REG(hw, 3150 IXGBE_FDIRUSTAT) & 0xFFFF; 3151 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw, 3152 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF; 3153 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw, 3154 IXGBE_FDIRFSTAT) & 0xFFFF; 3155 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw, 3156 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF; 3157 } 3158 /* MACsec Stats registers */ 3159 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT); 3160 macsec_stats->out_pkts_encrypted += 3161 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE); 3162 macsec_stats->out_pkts_protected += 3163 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP); 3164 macsec_stats->out_octets_encrypted += 3165 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE); 3166 macsec_stats->out_octets_protected += 3167 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP); 3168 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT); 3169 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD); 3170 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI); 3171 macsec_stats->in_pkts_unknownsci += 3172 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI); 3173 macsec_stats->in_octets_decrypted += 3174 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD); 3175 macsec_stats->in_octets_validated += 3176 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV); 3177 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH); 3178 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY); 3179 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE); 3180 for (i = 0; i < 2; i++) { 3181 macsec_stats->in_pkts_ok += 3182 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i)); 3183 macsec_stats->in_pkts_invalid += 3184 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i)); 3185 macsec_stats->in_pkts_notvalid += 3186 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i)); 3187 } 3188 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA); 3189 macsec_stats->in_pkts_notusingsa += 3190 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA); 3191 } 3192 3193 /* 3194 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c 3195 */ 3196 static int 3197 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3198 { 3199 struct ixgbe_hw *hw = 3200 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3201 struct ixgbe_hw_stats *hw_stats = 3202 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3203 struct ixgbe_macsec_stats *macsec_stats = 3204 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3205 dev->data->dev_private); 3206 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3207 unsigned i; 3208 3209 total_missed_rx = 0; 3210 total_qbrc = 0; 3211 total_qprc = 0; 3212 total_qprdc = 0; 3213 3214 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3215 &total_qbrc, &total_qprc, &total_qprdc); 3216 3217 if (stats == NULL) 3218 return -EINVAL; 3219 3220 /* Fill out the rte_eth_stats statistics structure */ 3221 stats->ipackets = total_qprc; 3222 stats->ibytes = total_qbrc; 3223 stats->opackets = hw_stats->gptc; 3224 stats->obytes = hw_stats->gotc; 3225 3226 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3227 stats->q_ipackets[i] = hw_stats->qprc[i]; 3228 stats->q_opackets[i] = hw_stats->qptc[i]; 3229 stats->q_ibytes[i] = hw_stats->qbrc[i]; 3230 stats->q_obytes[i] = hw_stats->qbtc[i]; 3231 stats->q_errors[i] = hw_stats->qprdc[i]; 3232 } 3233 3234 /* Rx Errors */ 3235 stats->imissed = total_missed_rx; 3236 stats->ierrors = hw_stats->crcerrs + 3237 hw_stats->mspdc + 3238 hw_stats->rlec + 3239 hw_stats->ruc + 3240 hw_stats->roc + 3241 hw_stats->illerrc + 3242 hw_stats->errbc + 3243 hw_stats->rfc + 3244 hw_stats->fccrc + 3245 hw_stats->fclast; 3246 3247 /* Tx Errors */ 3248 stats->oerrors = 0; 3249 return 0; 3250 } 3251 3252 static void 3253 ixgbe_dev_stats_reset(struct rte_eth_dev *dev) 3254 { 3255 struct ixgbe_hw_stats *stats = 3256 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3257 3258 /* HW registers are cleared on read */ 3259 ixgbe_dev_stats_get(dev, NULL); 3260 3261 /* Reset software totals */ 3262 memset(stats, 0, sizeof(*stats)); 3263 } 3264 3265 /* This function calculates the number of xstats based on the current config */ 3266 static unsigned 3267 ixgbe_xstats_calc_num(void) { 3268 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS + 3269 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) + 3270 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES); 3271 } 3272 3273 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3274 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size) 3275 { 3276 const unsigned cnt_stats = ixgbe_xstats_calc_num(); 3277 unsigned stat, i, count; 3278 3279 if (xstats_names != NULL) { 3280 count = 0; 3281 3282 /* Note: limit >= cnt_stats checked upstream 3283 * in rte_eth_xstats_names() 3284 */ 3285 3286 /* Extended stats from ixgbe_hw_stats */ 3287 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3288 snprintf(xstats_names[count].name, 3289 sizeof(xstats_names[count].name), 3290 "%s", 3291 rte_ixgbe_stats_strings[i].name); 3292 count++; 3293 } 3294 3295 /* MACsec Stats */ 3296 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3297 snprintf(xstats_names[count].name, 3298 sizeof(xstats_names[count].name), 3299 "%s", 3300 rte_ixgbe_macsec_strings[i].name); 3301 count++; 3302 } 3303 3304 /* RX Priority Stats */ 3305 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3306 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3307 snprintf(xstats_names[count].name, 3308 sizeof(xstats_names[count].name), 3309 "rx_priority%u_%s", i, 3310 rte_ixgbe_rxq_strings[stat].name); 3311 count++; 3312 } 3313 } 3314 3315 /* TX Priority Stats */ 3316 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3317 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3318 snprintf(xstats_names[count].name, 3319 sizeof(xstats_names[count].name), 3320 "tx_priority%u_%s", i, 3321 rte_ixgbe_txq_strings[stat].name); 3322 count++; 3323 } 3324 } 3325 } 3326 return cnt_stats; 3327 } 3328 3329 static int ixgbe_dev_xstats_get_names_by_id( 3330 struct rte_eth_dev *dev, 3331 struct rte_eth_xstat_name *xstats_names, 3332 const uint64_t *ids, 3333 unsigned int limit) 3334 { 3335 if (!ids) { 3336 const unsigned int cnt_stats = ixgbe_xstats_calc_num(); 3337 unsigned int stat, i, count; 3338 3339 if (xstats_names != NULL) { 3340 count = 0; 3341 3342 /* Note: limit >= cnt_stats checked upstream 3343 * in rte_eth_xstats_names() 3344 */ 3345 3346 /* Extended stats from ixgbe_hw_stats */ 3347 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3348 snprintf(xstats_names[count].name, 3349 sizeof(xstats_names[count].name), 3350 "%s", 3351 rte_ixgbe_stats_strings[i].name); 3352 count++; 3353 } 3354 3355 /* MACsec Stats */ 3356 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3357 snprintf(xstats_names[count].name, 3358 sizeof(xstats_names[count].name), 3359 "%s", 3360 rte_ixgbe_macsec_strings[i].name); 3361 count++; 3362 } 3363 3364 /* RX Priority Stats */ 3365 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3366 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3367 snprintf(xstats_names[count].name, 3368 sizeof(xstats_names[count].name), 3369 "rx_priority%u_%s", i, 3370 rte_ixgbe_rxq_strings[stat].name); 3371 count++; 3372 } 3373 } 3374 3375 /* TX Priority Stats */ 3376 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3377 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3378 snprintf(xstats_names[count].name, 3379 sizeof(xstats_names[count].name), 3380 "tx_priority%u_%s", i, 3381 rte_ixgbe_txq_strings[stat].name); 3382 count++; 3383 } 3384 } 3385 } 3386 return cnt_stats; 3387 } 3388 3389 uint16_t i; 3390 uint16_t size = ixgbe_xstats_calc_num(); 3391 struct rte_eth_xstat_name xstats_names_copy[size]; 3392 3393 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL, 3394 size); 3395 3396 for (i = 0; i < limit; i++) { 3397 if (ids[i] >= size) { 3398 PMD_INIT_LOG(ERR, "id value isn't valid"); 3399 return -1; 3400 } 3401 strcpy(xstats_names[i].name, 3402 xstats_names_copy[ids[i]].name); 3403 } 3404 return limit; 3405 } 3406 3407 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3408 struct rte_eth_xstat_name *xstats_names, unsigned limit) 3409 { 3410 unsigned i; 3411 3412 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL) 3413 return -ENOMEM; 3414 3415 if (xstats_names != NULL) 3416 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) 3417 snprintf(xstats_names[i].name, 3418 sizeof(xstats_names[i].name), 3419 "%s", rte_ixgbevf_stats_strings[i].name); 3420 return IXGBEVF_NB_XSTATS; 3421 } 3422 3423 static int 3424 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3425 unsigned n) 3426 { 3427 struct ixgbe_hw *hw = 3428 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3429 struct ixgbe_hw_stats *hw_stats = 3430 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3431 struct ixgbe_macsec_stats *macsec_stats = 3432 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3433 dev->data->dev_private); 3434 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3435 unsigned i, stat, count = 0; 3436 3437 count = ixgbe_xstats_calc_num(); 3438 3439 if (n < count) 3440 return count; 3441 3442 total_missed_rx = 0; 3443 total_qbrc = 0; 3444 total_qprc = 0; 3445 total_qprdc = 0; 3446 3447 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3448 &total_qbrc, &total_qprc, &total_qprdc); 3449 3450 /* If this is a reset xstats is NULL, and we have cleared the 3451 * registers by reading them. 3452 */ 3453 if (!xstats) 3454 return 0; 3455 3456 /* Extended stats from ixgbe_hw_stats */ 3457 count = 0; 3458 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3459 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3460 rte_ixgbe_stats_strings[i].offset); 3461 xstats[count].id = count; 3462 count++; 3463 } 3464 3465 /* MACsec Stats */ 3466 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3467 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) + 3468 rte_ixgbe_macsec_strings[i].offset); 3469 xstats[count].id = count; 3470 count++; 3471 } 3472 3473 /* RX Priority Stats */ 3474 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3475 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3476 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3477 rte_ixgbe_rxq_strings[stat].offset + 3478 (sizeof(uint64_t) * i)); 3479 xstats[count].id = count; 3480 count++; 3481 } 3482 } 3483 3484 /* TX Priority Stats */ 3485 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3486 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3487 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3488 rte_ixgbe_txq_strings[stat].offset + 3489 (sizeof(uint64_t) * i)); 3490 xstats[count].id = count; 3491 count++; 3492 } 3493 } 3494 return count; 3495 } 3496 3497 static int 3498 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 3499 uint64_t *values, unsigned int n) 3500 { 3501 if (!ids) { 3502 struct ixgbe_hw *hw = 3503 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3504 struct ixgbe_hw_stats *hw_stats = 3505 IXGBE_DEV_PRIVATE_TO_STATS( 3506 dev->data->dev_private); 3507 struct ixgbe_macsec_stats *macsec_stats = 3508 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3509 dev->data->dev_private); 3510 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3511 unsigned int i, stat, count = 0; 3512 3513 count = ixgbe_xstats_calc_num(); 3514 3515 if (!ids && n < count) 3516 return count; 3517 3518 total_missed_rx = 0; 3519 total_qbrc = 0; 3520 total_qprc = 0; 3521 total_qprdc = 0; 3522 3523 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, 3524 &total_missed_rx, &total_qbrc, &total_qprc, 3525 &total_qprdc); 3526 3527 /* If this is a reset xstats is NULL, and we have cleared the 3528 * registers by reading them. 3529 */ 3530 if (!ids && !values) 3531 return 0; 3532 3533 /* Extended stats from ixgbe_hw_stats */ 3534 count = 0; 3535 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3536 values[count] = *(uint64_t *)(((char *)hw_stats) + 3537 rte_ixgbe_stats_strings[i].offset); 3538 count++; 3539 } 3540 3541 /* MACsec Stats */ 3542 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3543 values[count] = *(uint64_t *)(((char *)macsec_stats) + 3544 rte_ixgbe_macsec_strings[i].offset); 3545 count++; 3546 } 3547 3548 /* RX Priority Stats */ 3549 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3550 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3551 values[count] = 3552 *(uint64_t *)(((char *)hw_stats) + 3553 rte_ixgbe_rxq_strings[stat].offset + 3554 (sizeof(uint64_t) * i)); 3555 count++; 3556 } 3557 } 3558 3559 /* TX Priority Stats */ 3560 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3561 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3562 values[count] = 3563 *(uint64_t *)(((char *)hw_stats) + 3564 rte_ixgbe_txq_strings[stat].offset + 3565 (sizeof(uint64_t) * i)); 3566 count++; 3567 } 3568 } 3569 return count; 3570 } 3571 3572 uint16_t i; 3573 uint16_t size = ixgbe_xstats_calc_num(); 3574 uint64_t values_copy[size]; 3575 3576 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size); 3577 3578 for (i = 0; i < n; i++) { 3579 if (ids[i] >= size) { 3580 PMD_INIT_LOG(ERR, "id value isn't valid"); 3581 return -1; 3582 } 3583 values[i] = values_copy[ids[i]]; 3584 } 3585 return n; 3586 } 3587 3588 static void 3589 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev) 3590 { 3591 struct ixgbe_hw_stats *stats = 3592 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3593 struct ixgbe_macsec_stats *macsec_stats = 3594 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3595 dev->data->dev_private); 3596 3597 unsigned count = ixgbe_xstats_calc_num(); 3598 3599 /* HW registers are cleared on read */ 3600 ixgbe_dev_xstats_get(dev, NULL, count); 3601 3602 /* Reset software totals */ 3603 memset(stats, 0, sizeof(*stats)); 3604 memset(macsec_stats, 0, sizeof(*macsec_stats)); 3605 } 3606 3607 static void 3608 ixgbevf_update_stats(struct rte_eth_dev *dev) 3609 { 3610 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3611 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3612 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3613 3614 /* Good Rx packet, include VF loopback */ 3615 UPDATE_VF_STAT(IXGBE_VFGPRC, 3616 hw_stats->last_vfgprc, hw_stats->vfgprc); 3617 3618 /* Good Rx octets, include VF loopback */ 3619 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB, 3620 hw_stats->last_vfgorc, hw_stats->vfgorc); 3621 3622 /* Good Tx packet, include VF loopback */ 3623 UPDATE_VF_STAT(IXGBE_VFGPTC, 3624 hw_stats->last_vfgptc, hw_stats->vfgptc); 3625 3626 /* Good Tx octets, include VF loopback */ 3627 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB, 3628 hw_stats->last_vfgotc, hw_stats->vfgotc); 3629 3630 /* Rx Multicst Packet */ 3631 UPDATE_VF_STAT(IXGBE_VFMPRC, 3632 hw_stats->last_vfmprc, hw_stats->vfmprc); 3633 } 3634 3635 static int 3636 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3637 unsigned n) 3638 { 3639 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3640 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3641 unsigned i; 3642 3643 if (n < IXGBEVF_NB_XSTATS) 3644 return IXGBEVF_NB_XSTATS; 3645 3646 ixgbevf_update_stats(dev); 3647 3648 if (!xstats) 3649 return 0; 3650 3651 /* Extended stats */ 3652 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) { 3653 xstats[i].id = i; 3654 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + 3655 rte_ixgbevf_stats_strings[i].offset); 3656 } 3657 3658 return IXGBEVF_NB_XSTATS; 3659 } 3660 3661 static int 3662 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3663 { 3664 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3665 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3666 3667 ixgbevf_update_stats(dev); 3668 3669 if (stats == NULL) 3670 return -EINVAL; 3671 3672 stats->ipackets = hw_stats->vfgprc; 3673 stats->ibytes = hw_stats->vfgorc; 3674 stats->opackets = hw_stats->vfgptc; 3675 stats->obytes = hw_stats->vfgotc; 3676 return 0; 3677 } 3678 3679 static void 3680 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev) 3681 { 3682 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3683 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3684 3685 /* Sync HW register to the last stats */ 3686 ixgbevf_dev_stats_get(dev, NULL); 3687 3688 /* reset HW current stats*/ 3689 hw_stats->vfgprc = 0; 3690 hw_stats->vfgorc = 0; 3691 hw_stats->vfgptc = 0; 3692 hw_stats->vfgotc = 0; 3693 } 3694 3695 static int 3696 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 3697 { 3698 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3699 u16 eeprom_verh, eeprom_verl; 3700 u32 etrack_id; 3701 int ret; 3702 3703 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh); 3704 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl); 3705 3706 etrack_id = (eeprom_verh << 16) | eeprom_verl; 3707 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id); 3708 3709 ret += 1; /* add the size of '\0' */ 3710 if (fw_size < (u32)ret) 3711 return ret; 3712 else 3713 return 0; 3714 } 3715 3716 static void 3717 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3718 { 3719 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3720 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3721 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 3722 3723 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3724 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3725 if (RTE_ETH_DEV_SRIOV(dev).active == 0) { 3726 /* 3727 * When DCB/VT is off, maximum number of queues changes, 3728 * except for 82598EB, which remains constant. 3729 */ 3730 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 3731 hw->mac.type != ixgbe_mac_82598EB) 3732 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES; 3733 } 3734 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */ 3735 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */ 3736 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3737 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3738 dev_info->max_vfs = pci_dev->max_vfs; 3739 if (hw->mac.type == ixgbe_mac_82598EB) 3740 dev_info->max_vmdq_pools = ETH_16_POOLS; 3741 else 3742 dev_info->max_vmdq_pools = ETH_64_POOLS; 3743 dev_info->vmdq_queue_num = dev_info->max_rx_queues; 3744 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3745 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3746 dev_info->rx_queue_offload_capa); 3747 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3748 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3749 3750 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3751 .rx_thresh = { 3752 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3753 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3754 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3755 }, 3756 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3757 .rx_drop_en = 0, 3758 .offloads = 0, 3759 }; 3760 3761 dev_info->default_txconf = (struct rte_eth_txconf) { 3762 .tx_thresh = { 3763 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3764 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3765 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3766 }, 3767 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3768 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3769 .offloads = 0, 3770 }; 3771 3772 dev_info->rx_desc_lim = rx_desc_lim; 3773 dev_info->tx_desc_lim = tx_desc_lim; 3774 3775 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 3776 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 3777 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 3778 3779 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 3780 if (hw->mac.type == ixgbe_mac_X540 || 3781 hw->mac.type == ixgbe_mac_X540_vf || 3782 hw->mac.type == ixgbe_mac_X550 || 3783 hw->mac.type == ixgbe_mac_X550_vf) { 3784 dev_info->speed_capa |= ETH_LINK_SPEED_100M; 3785 } 3786 if (hw->mac.type == ixgbe_mac_X550) { 3787 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G; 3788 dev_info->speed_capa |= ETH_LINK_SPEED_5G; 3789 } 3790 3791 /* Driver-preferred Rx/Tx parameters */ 3792 dev_info->default_rxportconf.burst_size = 32; 3793 dev_info->default_txportconf.burst_size = 32; 3794 dev_info->default_rxportconf.nb_queues = 1; 3795 dev_info->default_txportconf.nb_queues = 1; 3796 dev_info->default_rxportconf.ring_size = 256; 3797 dev_info->default_txportconf.ring_size = 256; 3798 } 3799 3800 static const uint32_t * 3801 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 3802 { 3803 static const uint32_t ptypes[] = { 3804 /* For non-vec functions, 3805 * refers to ixgbe_rxd_pkt_info_to_pkt_type(); 3806 * for vec functions, 3807 * refers to _recv_raw_pkts_vec(). 3808 */ 3809 RTE_PTYPE_L2_ETHER, 3810 RTE_PTYPE_L3_IPV4, 3811 RTE_PTYPE_L3_IPV4_EXT, 3812 RTE_PTYPE_L3_IPV6, 3813 RTE_PTYPE_L3_IPV6_EXT, 3814 RTE_PTYPE_L4_SCTP, 3815 RTE_PTYPE_L4_TCP, 3816 RTE_PTYPE_L4_UDP, 3817 RTE_PTYPE_TUNNEL_IP, 3818 RTE_PTYPE_INNER_L3_IPV6, 3819 RTE_PTYPE_INNER_L3_IPV6_EXT, 3820 RTE_PTYPE_INNER_L4_TCP, 3821 RTE_PTYPE_INNER_L4_UDP, 3822 RTE_PTYPE_UNKNOWN 3823 }; 3824 3825 if (dev->rx_pkt_burst == ixgbe_recv_pkts || 3826 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc || 3827 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc || 3828 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc) 3829 return ptypes; 3830 3831 #if defined(RTE_ARCH_X86) 3832 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec || 3833 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec) 3834 return ptypes; 3835 #endif 3836 return NULL; 3837 } 3838 3839 static void 3840 ixgbevf_dev_info_get(struct rte_eth_dev *dev, 3841 struct rte_eth_dev_info *dev_info) 3842 { 3843 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3844 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3845 3846 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3847 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3848 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */ 3849 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */ 3850 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3851 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3852 dev_info->max_vfs = pci_dev->max_vfs; 3853 if (hw->mac.type == ixgbe_mac_82598EB) 3854 dev_info->max_vmdq_pools = ETH_16_POOLS; 3855 else 3856 dev_info->max_vmdq_pools = ETH_64_POOLS; 3857 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3858 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3859 dev_info->rx_queue_offload_capa); 3860 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3861 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3862 3863 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3864 .rx_thresh = { 3865 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3866 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3867 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3868 }, 3869 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3870 .rx_drop_en = 0, 3871 .offloads = 0, 3872 }; 3873 3874 dev_info->default_txconf = (struct rte_eth_txconf) { 3875 .tx_thresh = { 3876 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3877 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3878 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3879 }, 3880 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3881 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3882 .offloads = 0, 3883 }; 3884 3885 dev_info->rx_desc_lim = rx_desc_lim; 3886 dev_info->tx_desc_lim = tx_desc_lim; 3887 } 3888 3889 static int 3890 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3891 int *link_up, int wait_to_complete) 3892 { 3893 struct ixgbe_mbx_info *mbx = &hw->mbx; 3894 struct ixgbe_mac_info *mac = &hw->mac; 3895 uint32_t links_reg, in_msg; 3896 int ret_val = 0; 3897 3898 /* If we were hit with a reset drop the link */ 3899 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout) 3900 mac->get_link_status = true; 3901 3902 if (!mac->get_link_status) 3903 goto out; 3904 3905 /* if link status is down no point in checking to see if pf is up */ 3906 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 3907 if (!(links_reg & IXGBE_LINKS_UP)) 3908 goto out; 3909 3910 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs 3911 * before the link status is correct 3912 */ 3913 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) { 3914 int i; 3915 3916 for (i = 0; i < 5; i++) { 3917 rte_delay_us(100); 3918 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 3919 3920 if (!(links_reg & IXGBE_LINKS_UP)) 3921 goto out; 3922 } 3923 } 3924 3925 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 3926 case IXGBE_LINKS_SPEED_10G_82599: 3927 *speed = IXGBE_LINK_SPEED_10GB_FULL; 3928 if (hw->mac.type >= ixgbe_mac_X550) { 3929 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 3930 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 3931 } 3932 break; 3933 case IXGBE_LINKS_SPEED_1G_82599: 3934 *speed = IXGBE_LINK_SPEED_1GB_FULL; 3935 break; 3936 case IXGBE_LINKS_SPEED_100_82599: 3937 *speed = IXGBE_LINK_SPEED_100_FULL; 3938 if (hw->mac.type == ixgbe_mac_X550) { 3939 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 3940 *speed = IXGBE_LINK_SPEED_5GB_FULL; 3941 } 3942 break; 3943 case IXGBE_LINKS_SPEED_10_X550EM_A: 3944 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3945 /* Since Reserved in older MAC's */ 3946 if (hw->mac.type >= ixgbe_mac_X550) 3947 *speed = IXGBE_LINK_SPEED_10_FULL; 3948 break; 3949 default: 3950 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3951 } 3952 3953 /* if the read failed it could just be a mailbox collision, best wait 3954 * until we are called again and don't report an error 3955 */ 3956 if (mbx->ops.read(hw, &in_msg, 1, 0)) 3957 goto out; 3958 3959 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) { 3960 /* msg is not CTS and is NACK we must have lost CTS status */ 3961 if (in_msg & IXGBE_VT_MSGTYPE_NACK) 3962 mac->get_link_status = false; 3963 goto out; 3964 } 3965 3966 /* the pf is talking, if we timed out in the past we reinit */ 3967 if (!mbx->timeout) { 3968 ret_val = -1; 3969 goto out; 3970 } 3971 3972 /* if we passed all the tests above then the link is up and we no 3973 * longer need to check for link 3974 */ 3975 mac->get_link_status = false; 3976 3977 out: 3978 *link_up = !mac->get_link_status; 3979 return ret_val; 3980 } 3981 3982 static void 3983 ixgbe_dev_setup_link_alarm_handler(void *param) 3984 { 3985 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 3986 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3987 struct ixgbe_interrupt *intr = 3988 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 3989 u32 speed; 3990 bool autoneg = false; 3991 3992 speed = hw->phy.autoneg_advertised; 3993 if (!speed) 3994 ixgbe_get_link_capabilities(hw, &speed, &autoneg); 3995 3996 ixgbe_setup_link(hw, speed, true); 3997 3998 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 3999 } 4000 4001 /* return 0 means link status changed, -1 means not changed */ 4002 int 4003 ixgbe_dev_link_update_share(struct rte_eth_dev *dev, 4004 int wait_to_complete, int vf) 4005 { 4006 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4007 struct rte_eth_link link; 4008 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4009 struct ixgbe_interrupt *intr = 4010 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4011 int link_up; 4012 int diag; 4013 int wait = 1; 4014 4015 memset(&link, 0, sizeof(link)); 4016 link.link_status = ETH_LINK_DOWN; 4017 link.link_speed = ETH_SPEED_NUM_NONE; 4018 link.link_duplex = ETH_LINK_HALF_DUPLEX; 4019 link.link_autoneg = ETH_LINK_AUTONEG; 4020 4021 hw->mac.get_link_status = true; 4022 4023 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) 4024 return rte_eth_linkstatus_set(dev, &link); 4025 4026 /* check if it needs to wait to complete, if lsc interrupt is enabled */ 4027 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0) 4028 wait = 0; 4029 4030 if (vf) 4031 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait); 4032 else 4033 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait); 4034 4035 if (diag != 0) { 4036 link.link_speed = ETH_SPEED_NUM_100M; 4037 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4038 return rte_eth_linkstatus_set(dev, &link); 4039 } 4040 4041 if (link_up == 0) { 4042 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) { 4043 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 4044 rte_eal_alarm_set(10, 4045 ixgbe_dev_setup_link_alarm_handler, dev); 4046 } 4047 return rte_eth_linkstatus_set(dev, &link); 4048 } 4049 4050 link.link_status = ETH_LINK_UP; 4051 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4052 4053 switch (link_speed) { 4054 default: 4055 case IXGBE_LINK_SPEED_UNKNOWN: 4056 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4057 link.link_speed = ETH_SPEED_NUM_100M; 4058 break; 4059 4060 case IXGBE_LINK_SPEED_100_FULL: 4061 link.link_speed = ETH_SPEED_NUM_100M; 4062 break; 4063 4064 case IXGBE_LINK_SPEED_1GB_FULL: 4065 link.link_speed = ETH_SPEED_NUM_1G; 4066 break; 4067 4068 case IXGBE_LINK_SPEED_2_5GB_FULL: 4069 link.link_speed = ETH_SPEED_NUM_2_5G; 4070 break; 4071 4072 case IXGBE_LINK_SPEED_5GB_FULL: 4073 link.link_speed = ETH_SPEED_NUM_5G; 4074 break; 4075 4076 case IXGBE_LINK_SPEED_10GB_FULL: 4077 link.link_speed = ETH_SPEED_NUM_10G; 4078 break; 4079 } 4080 4081 return rte_eth_linkstatus_set(dev, &link); 4082 } 4083 4084 static int 4085 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4086 { 4087 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0); 4088 } 4089 4090 static int 4091 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4092 { 4093 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1); 4094 } 4095 4096 static void 4097 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 4098 { 4099 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4100 uint32_t fctrl; 4101 4102 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4103 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4104 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4105 } 4106 4107 static void 4108 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 4109 { 4110 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4111 uint32_t fctrl; 4112 4113 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4114 fctrl &= (~IXGBE_FCTRL_UPE); 4115 if (dev->data->all_multicast == 1) 4116 fctrl |= IXGBE_FCTRL_MPE; 4117 else 4118 fctrl &= (~IXGBE_FCTRL_MPE); 4119 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4120 } 4121 4122 static void 4123 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 4124 { 4125 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4126 uint32_t fctrl; 4127 4128 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4129 fctrl |= IXGBE_FCTRL_MPE; 4130 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4131 } 4132 4133 static void 4134 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 4135 { 4136 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4137 uint32_t fctrl; 4138 4139 if (dev->data->promiscuous == 1) 4140 return; /* must remain in all_multicast mode */ 4141 4142 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4143 fctrl &= (~IXGBE_FCTRL_MPE); 4144 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4145 } 4146 4147 /** 4148 * It clears the interrupt causes and enables the interrupt. 4149 * It will be called once only during nic initialized. 4150 * 4151 * @param dev 4152 * Pointer to struct rte_eth_dev. 4153 * @param on 4154 * Enable or Disable. 4155 * 4156 * @return 4157 * - On success, zero. 4158 * - On failure, a negative value. 4159 */ 4160 static int 4161 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 4162 { 4163 struct ixgbe_interrupt *intr = 4164 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4165 4166 ixgbe_dev_link_status_print(dev); 4167 if (on) 4168 intr->mask |= IXGBE_EICR_LSC; 4169 else 4170 intr->mask &= ~IXGBE_EICR_LSC; 4171 4172 return 0; 4173 } 4174 4175 /** 4176 * It clears the interrupt causes and enables the interrupt. 4177 * It will be called once only during nic initialized. 4178 * 4179 * @param dev 4180 * Pointer to struct rte_eth_dev. 4181 * 4182 * @return 4183 * - On success, zero. 4184 * - On failure, a negative value. 4185 */ 4186 static int 4187 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev) 4188 { 4189 struct ixgbe_interrupt *intr = 4190 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4191 4192 intr->mask |= IXGBE_EICR_RTX_QUEUE; 4193 4194 return 0; 4195 } 4196 4197 /** 4198 * It clears the interrupt causes and enables the interrupt. 4199 * It will be called once only during nic initialized. 4200 * 4201 * @param dev 4202 * Pointer to struct rte_eth_dev. 4203 * 4204 * @return 4205 * - On success, zero. 4206 * - On failure, a negative value. 4207 */ 4208 static int 4209 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev) 4210 { 4211 struct ixgbe_interrupt *intr = 4212 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4213 4214 intr->mask |= IXGBE_EICR_LINKSEC; 4215 4216 return 0; 4217 } 4218 4219 /* 4220 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update. 4221 * 4222 * @param dev 4223 * Pointer to struct rte_eth_dev. 4224 * 4225 * @return 4226 * - On success, zero. 4227 * - On failure, a negative value. 4228 */ 4229 static int 4230 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev) 4231 { 4232 uint32_t eicr; 4233 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4234 struct ixgbe_interrupt *intr = 4235 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4236 4237 /* clear all cause mask */ 4238 ixgbe_disable_intr(hw); 4239 4240 /* read-on-clear nic registers here */ 4241 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4242 PMD_DRV_LOG(DEBUG, "eicr %x", eicr); 4243 4244 intr->flags = 0; 4245 4246 /* set flag for async link update */ 4247 if (eicr & IXGBE_EICR_LSC) 4248 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 4249 4250 if (eicr & IXGBE_EICR_MAILBOX) 4251 intr->flags |= IXGBE_FLAG_MAILBOX; 4252 4253 if (eicr & IXGBE_EICR_LINKSEC) 4254 intr->flags |= IXGBE_FLAG_MACSEC; 4255 4256 if (hw->mac.type == ixgbe_mac_X550EM_x && 4257 hw->phy.type == ixgbe_phy_x550em_ext_t && 4258 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x)) 4259 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT; 4260 4261 return 0; 4262 } 4263 4264 /** 4265 * It gets and then prints the link status. 4266 * 4267 * @param dev 4268 * Pointer to struct rte_eth_dev. 4269 * 4270 * @return 4271 * - On success, zero. 4272 * - On failure, a negative value. 4273 */ 4274 static void 4275 ixgbe_dev_link_status_print(struct rte_eth_dev *dev) 4276 { 4277 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4278 struct rte_eth_link link; 4279 4280 rte_eth_linkstatus_get(dev, &link); 4281 4282 if (link.link_status) { 4283 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", 4284 (int)(dev->data->port_id), 4285 (unsigned)link.link_speed, 4286 link.link_duplex == ETH_LINK_FULL_DUPLEX ? 4287 "full-duplex" : "half-duplex"); 4288 } else { 4289 PMD_INIT_LOG(INFO, " Port %d: Link Down", 4290 (int)(dev->data->port_id)); 4291 } 4292 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 4293 pci_dev->addr.domain, 4294 pci_dev->addr.bus, 4295 pci_dev->addr.devid, 4296 pci_dev->addr.function); 4297 } 4298 4299 /* 4300 * It executes link_update after knowing an interrupt occurred. 4301 * 4302 * @param dev 4303 * Pointer to struct rte_eth_dev. 4304 * 4305 * @return 4306 * - On success, zero. 4307 * - On failure, a negative value. 4308 */ 4309 static int 4310 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev) 4311 { 4312 struct ixgbe_interrupt *intr = 4313 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4314 int64_t timeout; 4315 struct ixgbe_hw *hw = 4316 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4317 4318 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags); 4319 4320 if (intr->flags & IXGBE_FLAG_MAILBOX) { 4321 ixgbe_pf_mbx_process(dev); 4322 intr->flags &= ~IXGBE_FLAG_MAILBOX; 4323 } 4324 4325 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4326 ixgbe_handle_lasi(hw); 4327 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4328 } 4329 4330 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4331 struct rte_eth_link link; 4332 4333 /* get the link status before link update, for predicting later */ 4334 rte_eth_linkstatus_get(dev, &link); 4335 4336 ixgbe_dev_link_update(dev, 0); 4337 4338 /* likely to up */ 4339 if (!link.link_status) 4340 /* handle it 1 sec later, wait it being stable */ 4341 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT; 4342 /* likely to down */ 4343 else 4344 /* handle it 4 sec later, wait it being stable */ 4345 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT; 4346 4347 ixgbe_dev_link_status_print(dev); 4348 if (rte_eal_alarm_set(timeout * 1000, 4349 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0) 4350 PMD_DRV_LOG(ERR, "Error setting alarm"); 4351 else { 4352 /* remember original mask */ 4353 intr->mask_original = intr->mask; 4354 /* only disable lsc interrupt */ 4355 intr->mask &= ~IXGBE_EIMS_LSC; 4356 } 4357 } 4358 4359 PMD_DRV_LOG(DEBUG, "enable intr immediately"); 4360 ixgbe_enable_intr(dev); 4361 4362 return 0; 4363 } 4364 4365 /** 4366 * Interrupt handler which shall be registered for alarm callback for delayed 4367 * handling specific interrupt to wait for the stable nic state. As the 4368 * NIC interrupt state is not stable for ixgbe after link is just down, 4369 * it needs to wait 4 seconds to get the stable status. 4370 * 4371 * @param handle 4372 * Pointer to interrupt handle. 4373 * @param param 4374 * The address of parameter (struct rte_eth_dev *) regsitered before. 4375 * 4376 * @return 4377 * void 4378 */ 4379 static void 4380 ixgbe_dev_interrupt_delayed_handler(void *param) 4381 { 4382 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4383 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4384 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4385 struct ixgbe_interrupt *intr = 4386 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4387 struct ixgbe_hw *hw = 4388 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4389 uint32_t eicr; 4390 4391 ixgbe_disable_intr(hw); 4392 4393 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4394 if (eicr & IXGBE_EICR_MAILBOX) 4395 ixgbe_pf_mbx_process(dev); 4396 4397 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4398 ixgbe_handle_lasi(hw); 4399 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4400 } 4401 4402 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4403 ixgbe_dev_link_update(dev, 0); 4404 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 4405 ixgbe_dev_link_status_print(dev); 4406 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, 4407 NULL); 4408 } 4409 4410 if (intr->flags & IXGBE_FLAG_MACSEC) { 4411 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, 4412 NULL); 4413 intr->flags &= ~IXGBE_FLAG_MACSEC; 4414 } 4415 4416 /* restore original mask */ 4417 intr->mask = intr->mask_original; 4418 intr->mask_original = 0; 4419 4420 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr); 4421 ixgbe_enable_intr(dev); 4422 rte_intr_enable(intr_handle); 4423 } 4424 4425 /** 4426 * Interrupt handler triggered by NIC for handling 4427 * specific interrupt. 4428 * 4429 * @param handle 4430 * Pointer to interrupt handle. 4431 * @param param 4432 * The address of parameter (struct rte_eth_dev *) regsitered before. 4433 * 4434 * @return 4435 * void 4436 */ 4437 static void 4438 ixgbe_dev_interrupt_handler(void *param) 4439 { 4440 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4441 4442 ixgbe_dev_interrupt_get_status(dev); 4443 ixgbe_dev_interrupt_action(dev); 4444 } 4445 4446 static int 4447 ixgbe_dev_led_on(struct rte_eth_dev *dev) 4448 { 4449 struct ixgbe_hw *hw; 4450 4451 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4452 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4453 } 4454 4455 static int 4456 ixgbe_dev_led_off(struct rte_eth_dev *dev) 4457 { 4458 struct ixgbe_hw *hw; 4459 4460 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4461 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4462 } 4463 4464 static int 4465 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4466 { 4467 struct ixgbe_hw *hw; 4468 uint32_t mflcn_reg; 4469 uint32_t fccfg_reg; 4470 int rx_pause; 4471 int tx_pause; 4472 4473 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4474 4475 fc_conf->pause_time = hw->fc.pause_time; 4476 fc_conf->high_water = hw->fc.high_water[0]; 4477 fc_conf->low_water = hw->fc.low_water[0]; 4478 fc_conf->send_xon = hw->fc.send_xon; 4479 fc_conf->autoneg = !hw->fc.disable_fc_autoneg; 4480 4481 /* 4482 * Return rx_pause status according to actual setting of 4483 * MFLCN register. 4484 */ 4485 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4486 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE)) 4487 rx_pause = 1; 4488 else 4489 rx_pause = 0; 4490 4491 /* 4492 * Return tx_pause status according to actual setting of 4493 * FCCFG register. 4494 */ 4495 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4496 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY)) 4497 tx_pause = 1; 4498 else 4499 tx_pause = 0; 4500 4501 if (rx_pause && tx_pause) 4502 fc_conf->mode = RTE_FC_FULL; 4503 else if (rx_pause) 4504 fc_conf->mode = RTE_FC_RX_PAUSE; 4505 else if (tx_pause) 4506 fc_conf->mode = RTE_FC_TX_PAUSE; 4507 else 4508 fc_conf->mode = RTE_FC_NONE; 4509 4510 return 0; 4511 } 4512 4513 static int 4514 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4515 { 4516 struct ixgbe_hw *hw; 4517 int err; 4518 uint32_t rx_buf_size; 4519 uint32_t max_high_water; 4520 uint32_t mflcn; 4521 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4522 ixgbe_fc_none, 4523 ixgbe_fc_rx_pause, 4524 ixgbe_fc_tx_pause, 4525 ixgbe_fc_full 4526 }; 4527 4528 PMD_INIT_FUNC_TRACE(); 4529 4530 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4531 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)); 4532 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4533 4534 /* 4535 * At least reserve one Ethernet frame for watermark 4536 * high_water/low_water in kilo bytes for ixgbe 4537 */ 4538 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4539 if ((fc_conf->high_water > max_high_water) || 4540 (fc_conf->high_water < fc_conf->low_water)) { 4541 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4542 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4543 return -EINVAL; 4544 } 4545 4546 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode]; 4547 hw->fc.pause_time = fc_conf->pause_time; 4548 hw->fc.high_water[0] = fc_conf->high_water; 4549 hw->fc.low_water[0] = fc_conf->low_water; 4550 hw->fc.send_xon = fc_conf->send_xon; 4551 hw->fc.disable_fc_autoneg = !fc_conf->autoneg; 4552 4553 err = ixgbe_fc_enable(hw); 4554 4555 /* Not negotiated is not an error case */ 4556 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) { 4557 4558 /* check if we want to forward MAC frames - driver doesn't have native 4559 * capability to do that, so we'll write the registers ourselves */ 4560 4561 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4562 4563 /* set or clear MFLCN.PMCF bit depending on configuration */ 4564 if (fc_conf->mac_ctrl_frame_fwd != 0) 4565 mflcn |= IXGBE_MFLCN_PMCF; 4566 else 4567 mflcn &= ~IXGBE_MFLCN_PMCF; 4568 4569 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn); 4570 IXGBE_WRITE_FLUSH(hw); 4571 4572 return 0; 4573 } 4574 4575 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err); 4576 return -EIO; 4577 } 4578 4579 /** 4580 * ixgbe_pfc_enable_generic - Enable flow control 4581 * @hw: pointer to hardware structure 4582 * @tc_num: traffic class number 4583 * Enable flow control according to the current settings. 4584 */ 4585 static int 4586 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num) 4587 { 4588 int ret_val = 0; 4589 uint32_t mflcn_reg, fccfg_reg; 4590 uint32_t reg; 4591 uint32_t fcrtl, fcrth; 4592 uint8_t i; 4593 uint8_t nb_rx_en; 4594 4595 /* Validate the water mark configuration */ 4596 if (!hw->fc.pause_time) { 4597 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4598 goto out; 4599 } 4600 4601 /* Low water mark of zero causes XOFF floods */ 4602 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 4603 /* High/Low water can not be 0 */ 4604 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) { 4605 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4606 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4607 goto out; 4608 } 4609 4610 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) { 4611 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4612 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4613 goto out; 4614 } 4615 } 4616 /* Negotiate the fc mode to use */ 4617 ixgbe_fc_autoneg(hw); 4618 4619 /* Disable any previous flow control settings */ 4620 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4621 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE); 4622 4623 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4624 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 4625 4626 switch (hw->fc.current_mode) { 4627 case ixgbe_fc_none: 4628 /* 4629 * If the count of enabled RX Priority Flow control >1, 4630 * and the TX pause can not be disabled 4631 */ 4632 nb_rx_en = 0; 4633 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4634 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4635 if (reg & IXGBE_FCRTH_FCEN) 4636 nb_rx_en++; 4637 } 4638 if (nb_rx_en > 1) 4639 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4640 break; 4641 case ixgbe_fc_rx_pause: 4642 /* 4643 * Rx Flow control is enabled and Tx Flow control is 4644 * disabled by software override. Since there really 4645 * isn't a way to advertise that we are capable of RX 4646 * Pause ONLY, we will advertise that we support both 4647 * symmetric and asymmetric Rx PAUSE. Later, we will 4648 * disable the adapter's ability to send PAUSE frames. 4649 */ 4650 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4651 /* 4652 * If the count of enabled RX Priority Flow control >1, 4653 * and the TX pause can not be disabled 4654 */ 4655 nb_rx_en = 0; 4656 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4657 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4658 if (reg & IXGBE_FCRTH_FCEN) 4659 nb_rx_en++; 4660 } 4661 if (nb_rx_en > 1) 4662 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4663 break; 4664 case ixgbe_fc_tx_pause: 4665 /* 4666 * Tx Flow control is enabled, and Rx Flow control is 4667 * disabled by software override. 4668 */ 4669 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4670 break; 4671 case ixgbe_fc_full: 4672 /* Flow control (both Rx and Tx) is enabled by SW override. */ 4673 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4674 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4675 break; 4676 default: 4677 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly"); 4678 ret_val = IXGBE_ERR_CONFIG; 4679 goto out; 4680 } 4681 4682 /* Set 802.3x based flow control settings. */ 4683 mflcn_reg |= IXGBE_MFLCN_DPF; 4684 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 4685 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 4686 4687 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 4688 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 4689 hw->fc.high_water[tc_num]) { 4690 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE; 4691 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl); 4692 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN; 4693 } else { 4694 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0); 4695 /* 4696 * In order to prevent Tx hangs when the internal Tx 4697 * switch is enabled we must set the high water mark 4698 * to the maximum FCRTH value. This allows the Tx 4699 * switch to function even under heavy Rx workloads. 4700 */ 4701 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32; 4702 } 4703 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth); 4704 4705 /* Configure pause time (2 TCs per register) */ 4706 reg = hw->fc.pause_time * 0x00010001; 4707 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 4708 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 4709 4710 /* Configure flow control refresh threshold value */ 4711 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 4712 4713 out: 4714 return ret_val; 4715 } 4716 4717 static int 4718 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num) 4719 { 4720 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4721 int32_t ret_val = IXGBE_NOT_IMPLEMENTED; 4722 4723 if (hw->mac.type != ixgbe_mac_82598EB) { 4724 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num); 4725 } 4726 return ret_val; 4727 } 4728 4729 static int 4730 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf) 4731 { 4732 int err; 4733 uint32_t rx_buf_size; 4734 uint32_t max_high_water; 4735 uint8_t tc_num; 4736 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 4737 struct ixgbe_hw *hw = 4738 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4739 struct ixgbe_dcb_config *dcb_config = 4740 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 4741 4742 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4743 ixgbe_fc_none, 4744 ixgbe_fc_rx_pause, 4745 ixgbe_fc_tx_pause, 4746 ixgbe_fc_full 4747 }; 4748 4749 PMD_INIT_FUNC_TRACE(); 4750 4751 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map); 4752 tc_num = map[pfc_conf->priority]; 4753 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)); 4754 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4755 /* 4756 * At least reserve one Ethernet frame for watermark 4757 * high_water/low_water in kilo bytes for ixgbe 4758 */ 4759 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4760 if ((pfc_conf->fc.high_water > max_high_water) || 4761 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) { 4762 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4763 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4764 return -EINVAL; 4765 } 4766 4767 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode]; 4768 hw->fc.pause_time = pfc_conf->fc.pause_time; 4769 hw->fc.send_xon = pfc_conf->fc.send_xon; 4770 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water; 4771 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; 4772 4773 err = ixgbe_dcb_pfc_enable(dev, tc_num); 4774 4775 /* Not negotiated is not an error case */ 4776 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) 4777 return 0; 4778 4779 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err); 4780 return -EIO; 4781 } 4782 4783 static int 4784 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 4785 struct rte_eth_rss_reta_entry64 *reta_conf, 4786 uint16_t reta_size) 4787 { 4788 uint16_t i, sp_reta_size; 4789 uint8_t j, mask; 4790 uint32_t reta, r; 4791 uint16_t idx, shift; 4792 struct ixgbe_adapter *adapter = 4793 (struct ixgbe_adapter *)dev->data->dev_private; 4794 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4795 uint32_t reta_reg; 4796 4797 PMD_INIT_FUNC_TRACE(); 4798 4799 if (!ixgbe_rss_update_sp(hw->mac.type)) { 4800 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " 4801 "NIC."); 4802 return -ENOTSUP; 4803 } 4804 4805 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 4806 if (reta_size != sp_reta_size) { 4807 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 4808 "(%d) doesn't match the number hardware can supported " 4809 "(%d)", reta_size, sp_reta_size); 4810 return -EINVAL; 4811 } 4812 4813 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 4814 idx = i / RTE_RETA_GROUP_SIZE; 4815 shift = i % RTE_RETA_GROUP_SIZE; 4816 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 4817 IXGBE_4_BIT_MASK); 4818 if (!mask) 4819 continue; 4820 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 4821 if (mask == IXGBE_4_BIT_MASK) 4822 r = 0; 4823 else 4824 r = IXGBE_READ_REG(hw, reta_reg); 4825 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) { 4826 if (mask & (0x1 << j)) 4827 reta |= reta_conf[idx].reta[shift + j] << 4828 (CHAR_BIT * j); 4829 else 4830 reta |= r & (IXGBE_8_BIT_MASK << 4831 (CHAR_BIT * j)); 4832 } 4833 IXGBE_WRITE_REG(hw, reta_reg, reta); 4834 } 4835 adapter->rss_reta_updated = 1; 4836 4837 return 0; 4838 } 4839 4840 static int 4841 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 4842 struct rte_eth_rss_reta_entry64 *reta_conf, 4843 uint16_t reta_size) 4844 { 4845 uint16_t i, sp_reta_size; 4846 uint8_t j, mask; 4847 uint32_t reta; 4848 uint16_t idx, shift; 4849 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4850 uint32_t reta_reg; 4851 4852 PMD_INIT_FUNC_TRACE(); 4853 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 4854 if (reta_size != sp_reta_size) { 4855 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 4856 "(%d) doesn't match the number hardware can supported " 4857 "(%d)", reta_size, sp_reta_size); 4858 return -EINVAL; 4859 } 4860 4861 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 4862 idx = i / RTE_RETA_GROUP_SIZE; 4863 shift = i % RTE_RETA_GROUP_SIZE; 4864 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 4865 IXGBE_4_BIT_MASK); 4866 if (!mask) 4867 continue; 4868 4869 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 4870 reta = IXGBE_READ_REG(hw, reta_reg); 4871 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) { 4872 if (mask & (0x1 << j)) 4873 reta_conf[idx].reta[shift + j] = 4874 ((reta >> (CHAR_BIT * j)) & 4875 IXGBE_8_BIT_MASK); 4876 } 4877 } 4878 4879 return 0; 4880 } 4881 4882 static int 4883 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr, 4884 uint32_t index, uint32_t pool) 4885 { 4886 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4887 uint32_t enable_addr = 1; 4888 4889 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes, 4890 pool, enable_addr); 4891 } 4892 4893 static void 4894 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) 4895 { 4896 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4897 4898 ixgbe_clear_rar(hw, index); 4899 } 4900 4901 static int 4902 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr) 4903 { 4904 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4905 4906 ixgbe_remove_rar(dev, 0); 4907 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs); 4908 4909 return 0; 4910 } 4911 4912 static bool 4913 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 4914 { 4915 if (strcmp(dev->device->driver->name, drv->driver.name)) 4916 return false; 4917 4918 return true; 4919 } 4920 4921 bool 4922 is_ixgbe_supported(struct rte_eth_dev *dev) 4923 { 4924 return is_device_supported(dev, &rte_ixgbe_pmd); 4925 } 4926 4927 static int 4928 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 4929 { 4930 uint32_t hlreg0; 4931 uint32_t maxfrs; 4932 struct ixgbe_hw *hw; 4933 struct rte_eth_dev_info dev_info; 4934 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 4935 struct rte_eth_dev_data *dev_data = dev->data; 4936 4937 ixgbe_dev_info_get(dev, &dev_info); 4938 4939 /* check that mtu is within the allowed range */ 4940 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) 4941 return -EINVAL; 4942 4943 /* If device is started, refuse mtu that requires the support of 4944 * scattered packets when this feature has not been enabled before. 4945 */ 4946 if (dev_data->dev_started && !dev_data->scattered_rx && 4947 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE > 4948 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 4949 PMD_INIT_LOG(ERR, "Stop port first."); 4950 return -EINVAL; 4951 } 4952 4953 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4954 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4955 4956 /* switch to jumbo mode if needed */ 4957 if (frame_size > ETHER_MAX_LEN) { 4958 dev->data->dev_conf.rxmode.offloads |= 4959 DEV_RX_OFFLOAD_JUMBO_FRAME; 4960 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4961 } else { 4962 dev->data->dev_conf.rxmode.offloads &= 4963 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 4964 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; 4965 } 4966 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4967 4968 /* update max frame size */ 4969 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 4970 4971 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS); 4972 maxfrs &= 0x0000FFFF; 4973 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16); 4974 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs); 4975 4976 return 0; 4977 } 4978 4979 /* 4980 * Virtual Function operations 4981 */ 4982 static void 4983 ixgbevf_intr_disable(struct rte_eth_dev *dev) 4984 { 4985 struct ixgbe_interrupt *intr = 4986 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4987 struct ixgbe_hw *hw = 4988 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4989 4990 PMD_INIT_FUNC_TRACE(); 4991 4992 /* Clear interrupt mask to stop from interrupts being generated */ 4993 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK); 4994 4995 IXGBE_WRITE_FLUSH(hw); 4996 4997 /* Clear mask value. */ 4998 intr->mask = 0; 4999 } 5000 5001 static void 5002 ixgbevf_intr_enable(struct rte_eth_dev *dev) 5003 { 5004 struct ixgbe_interrupt *intr = 5005 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5006 struct ixgbe_hw *hw = 5007 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5008 5009 PMD_INIT_FUNC_TRACE(); 5010 5011 /* VF enable interrupt autoclean */ 5012 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK); 5013 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK); 5014 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK); 5015 5016 IXGBE_WRITE_FLUSH(hw); 5017 5018 /* Save IXGBE_VTEIMS value to mask. */ 5019 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK; 5020 } 5021 5022 static int 5023 ixgbevf_dev_configure(struct rte_eth_dev *dev) 5024 { 5025 struct rte_eth_conf *conf = &dev->data->dev_conf; 5026 struct ixgbe_adapter *adapter = 5027 (struct ixgbe_adapter *)dev->data->dev_private; 5028 5029 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d", 5030 dev->data->port_id); 5031 5032 /* 5033 * VF has no ability to enable/disable HW CRC 5034 * Keep the persistent behavior the same as Host PF 5035 */ 5036 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC 5037 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) { 5038 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip"); 5039 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC; 5040 } 5041 #else 5042 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) { 5043 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip"); 5044 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC; 5045 } 5046 #endif 5047 5048 /* 5049 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 5050 * allocation or vector Rx preconditions we will reset it. 5051 */ 5052 adapter->rx_bulk_alloc_allowed = true; 5053 adapter->rx_vec_allowed = true; 5054 5055 return 0; 5056 } 5057 5058 static int 5059 ixgbevf_dev_start(struct rte_eth_dev *dev) 5060 { 5061 struct ixgbe_hw *hw = 5062 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5063 uint32_t intr_vector = 0; 5064 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5065 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5066 5067 int err, mask = 0; 5068 5069 PMD_INIT_FUNC_TRACE(); 5070 5071 /* Stop the link setup handler before resetting the HW. */ 5072 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 5073 5074 err = hw->mac.ops.reset_hw(hw); 5075 if (err) { 5076 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err); 5077 return err; 5078 } 5079 hw->mac.get_link_status = true; 5080 5081 /* negotiate mailbox API version to use with the PF. */ 5082 ixgbevf_negotiate_api(hw); 5083 5084 ixgbevf_dev_tx_init(dev); 5085 5086 /* This can fail when allocating mbufs for descriptor rings */ 5087 err = ixgbevf_dev_rx_init(dev); 5088 if (err) { 5089 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err); 5090 ixgbe_dev_clear_queues(dev); 5091 return err; 5092 } 5093 5094 /* Set vfta */ 5095 ixgbevf_set_vfta_all(dev, 1); 5096 5097 /* Set HW strip */ 5098 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 5099 ETH_VLAN_EXTEND_MASK; 5100 err = ixgbevf_vlan_offload_config(dev, mask); 5101 if (err) { 5102 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err); 5103 ixgbe_dev_clear_queues(dev); 5104 return err; 5105 } 5106 5107 ixgbevf_dev_rxtx_start(dev); 5108 5109 /* check and configure queue intr-vector mapping */ 5110 if (rte_intr_cap_multiple(intr_handle) && 5111 dev->data->dev_conf.intr_conf.rxq) { 5112 /* According to datasheet, only vector 0/1/2 can be used, 5113 * now only one vector is used for Rx queue 5114 */ 5115 intr_vector = 1; 5116 if (rte_intr_efd_enable(intr_handle, intr_vector)) 5117 return -1; 5118 } 5119 5120 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 5121 intr_handle->intr_vec = 5122 rte_zmalloc("intr_vec", 5123 dev->data->nb_rx_queues * sizeof(int), 0); 5124 if (intr_handle->intr_vec == NULL) { 5125 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 5126 " intr_vec", dev->data->nb_rx_queues); 5127 return -ENOMEM; 5128 } 5129 } 5130 ixgbevf_configure_msix(dev); 5131 5132 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt 5133 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ). 5134 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( ) 5135 * is not cleared, it will fail when following rte_intr_enable( ) tries 5136 * to map Rx queue interrupt to other VFIO vectors. 5137 * So clear uio/vfio intr/evevnfd first to avoid failure. 5138 */ 5139 rte_intr_disable(intr_handle); 5140 5141 rte_intr_enable(intr_handle); 5142 5143 /* Re-enable interrupt for VF */ 5144 ixgbevf_intr_enable(dev); 5145 5146 /* 5147 * Update link status right before return, because it may 5148 * start link configuration process in a separate thread. 5149 */ 5150 ixgbevf_dev_link_update(dev, 0); 5151 5152 return 0; 5153 } 5154 5155 static void 5156 ixgbevf_dev_stop(struct rte_eth_dev *dev) 5157 { 5158 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5159 struct ixgbe_adapter *adapter = 5160 (struct ixgbe_adapter *)dev->data->dev_private; 5161 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5162 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5163 5164 PMD_INIT_FUNC_TRACE(); 5165 5166 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 5167 5168 ixgbevf_intr_disable(dev); 5169 5170 hw->adapter_stopped = 1; 5171 ixgbe_stop_adapter(hw); 5172 5173 /* 5174 * Clear what we set, but we still keep shadow_vfta to 5175 * restore after device starts 5176 */ 5177 ixgbevf_set_vfta_all(dev, 0); 5178 5179 /* Clear stored conf */ 5180 dev->data->scattered_rx = 0; 5181 5182 ixgbe_dev_clear_queues(dev); 5183 5184 /* Clean datapath event and queue/vec mapping */ 5185 rte_intr_efd_disable(intr_handle); 5186 if (intr_handle->intr_vec != NULL) { 5187 rte_free(intr_handle->intr_vec); 5188 intr_handle->intr_vec = NULL; 5189 } 5190 5191 adapter->rss_reta_updated = 0; 5192 } 5193 5194 static void 5195 ixgbevf_dev_close(struct rte_eth_dev *dev) 5196 { 5197 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5198 5199 PMD_INIT_FUNC_TRACE(); 5200 5201 ixgbe_reset_hw(hw); 5202 5203 ixgbevf_dev_stop(dev); 5204 5205 ixgbe_dev_free_queues(dev); 5206 5207 /** 5208 * Remove the VF MAC address ro ensure 5209 * that the VF traffic goes to the PF 5210 * after stop, close and detach of the VF 5211 **/ 5212 ixgbevf_remove_mac_addr(dev, 0); 5213 } 5214 5215 /* 5216 * Reset VF device 5217 */ 5218 static int 5219 ixgbevf_dev_reset(struct rte_eth_dev *dev) 5220 { 5221 int ret; 5222 5223 ret = eth_ixgbevf_dev_uninit(dev); 5224 if (ret) 5225 return ret; 5226 5227 ret = eth_ixgbevf_dev_init(dev); 5228 5229 return ret; 5230 } 5231 5232 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) 5233 { 5234 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5235 struct ixgbe_vfta *shadow_vfta = 5236 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5237 int i = 0, j = 0, vfta = 0, mask = 1; 5238 5239 for (i = 0; i < IXGBE_VFTA_SIZE; i++) { 5240 vfta = shadow_vfta->vfta[i]; 5241 if (vfta) { 5242 mask = 1; 5243 for (j = 0; j < 32; j++) { 5244 if (vfta & mask) 5245 ixgbe_set_vfta(hw, (i<<5)+j, 0, 5246 on, false); 5247 mask <<= 1; 5248 } 5249 } 5250 } 5251 5252 } 5253 5254 static int 5255 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 5256 { 5257 struct ixgbe_hw *hw = 5258 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5259 struct ixgbe_vfta *shadow_vfta = 5260 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5261 uint32_t vid_idx = 0; 5262 uint32_t vid_bit = 0; 5263 int ret = 0; 5264 5265 PMD_INIT_FUNC_TRACE(); 5266 5267 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */ 5268 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false); 5269 if (ret) { 5270 PMD_INIT_LOG(ERR, "Unable to set VF vlan"); 5271 return ret; 5272 } 5273 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 5274 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 5275 5276 /* Save what we set and retore it after device reset */ 5277 if (on) 5278 shadow_vfta->vfta[vid_idx] |= vid_bit; 5279 else 5280 shadow_vfta->vfta[vid_idx] &= ~vid_bit; 5281 5282 return 0; 5283 } 5284 5285 static void 5286 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 5287 { 5288 struct ixgbe_hw *hw = 5289 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5290 uint32_t ctrl; 5291 5292 PMD_INIT_FUNC_TRACE(); 5293 5294 if (queue >= hw->mac.max_rx_queues) 5295 return; 5296 5297 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 5298 if (on) 5299 ctrl |= IXGBE_RXDCTL_VME; 5300 else 5301 ctrl &= ~IXGBE_RXDCTL_VME; 5302 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 5303 5304 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on); 5305 } 5306 5307 static int 5308 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask) 5309 { 5310 struct ixgbe_rx_queue *rxq; 5311 uint16_t i; 5312 int on = 0; 5313 5314 /* VF function only support hw strip feature, others are not support */ 5315 if (mask & ETH_VLAN_STRIP_MASK) { 5316 for (i = 0; i < dev->data->nb_rx_queues; i++) { 5317 rxq = dev->data->rx_queues[i]; 5318 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP); 5319 ixgbevf_vlan_strip_queue_set(dev, i, on); 5320 } 5321 } 5322 5323 return 0; 5324 } 5325 5326 static int 5327 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 5328 { 5329 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 5330 5331 ixgbevf_vlan_offload_config(dev, mask); 5332 5333 return 0; 5334 } 5335 5336 int 5337 ixgbe_vt_check(struct ixgbe_hw *hw) 5338 { 5339 uint32_t reg_val; 5340 5341 /* if Virtualization Technology is enabled */ 5342 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 5343 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) { 5344 PMD_INIT_LOG(ERR, "VT must be enabled for this setting"); 5345 return -1; 5346 } 5347 5348 return 0; 5349 } 5350 5351 static uint32_t 5352 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr) 5353 { 5354 uint32_t vector = 0; 5355 5356 switch (hw->mac.mc_filter_type) { 5357 case 0: /* use bits [47:36] of the address */ 5358 vector = ((uc_addr->addr_bytes[4] >> 4) | 5359 (((uint16_t)uc_addr->addr_bytes[5]) << 4)); 5360 break; 5361 case 1: /* use bits [46:35] of the address */ 5362 vector = ((uc_addr->addr_bytes[4] >> 3) | 5363 (((uint16_t)uc_addr->addr_bytes[5]) << 5)); 5364 break; 5365 case 2: /* use bits [45:34] of the address */ 5366 vector = ((uc_addr->addr_bytes[4] >> 2) | 5367 (((uint16_t)uc_addr->addr_bytes[5]) << 6)); 5368 break; 5369 case 3: /* use bits [43:32] of the address */ 5370 vector = ((uc_addr->addr_bytes[4]) | 5371 (((uint16_t)uc_addr->addr_bytes[5]) << 8)); 5372 break; 5373 default: /* Invalid mc_filter_type */ 5374 break; 5375 } 5376 5377 /* vector can only be 12-bits or boundary will be exceeded */ 5378 vector &= 0xFFF; 5379 return vector; 5380 } 5381 5382 static int 5383 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr, 5384 uint8_t on) 5385 { 5386 uint32_t vector; 5387 uint32_t uta_idx; 5388 uint32_t reg_val; 5389 uint32_t uta_shift; 5390 uint32_t rc; 5391 const uint32_t ixgbe_uta_idx_mask = 0x7F; 5392 const uint32_t ixgbe_uta_bit_shift = 5; 5393 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1; 5394 const uint32_t bit1 = 0x1; 5395 5396 struct ixgbe_hw *hw = 5397 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5398 struct ixgbe_uta_info *uta_info = 5399 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5400 5401 /* The UTA table only exists on 82599 hardware and newer */ 5402 if (hw->mac.type < ixgbe_mac_82599EB) 5403 return -ENOTSUP; 5404 5405 vector = ixgbe_uta_vector(hw, mac_addr); 5406 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask; 5407 uta_shift = vector & ixgbe_uta_bit_mask; 5408 5409 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0); 5410 if (rc == on) 5411 return 0; 5412 5413 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx)); 5414 if (on) { 5415 uta_info->uta_in_use++; 5416 reg_val |= (bit1 << uta_shift); 5417 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift); 5418 } else { 5419 uta_info->uta_in_use--; 5420 reg_val &= ~(bit1 << uta_shift); 5421 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift); 5422 } 5423 5424 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val); 5425 5426 if (uta_info->uta_in_use > 0) 5427 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 5428 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 5429 else 5430 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 5431 5432 return 0; 5433 } 5434 5435 static int 5436 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) 5437 { 5438 int i; 5439 struct ixgbe_hw *hw = 5440 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5441 struct ixgbe_uta_info *uta_info = 5442 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5443 5444 /* The UTA table only exists on 82599 hardware and newer */ 5445 if (hw->mac.type < ixgbe_mac_82599EB) 5446 return -ENOTSUP; 5447 5448 if (on) { 5449 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5450 uta_info->uta_shadow[i] = ~0; 5451 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); 5452 } 5453 } else { 5454 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5455 uta_info->uta_shadow[i] = 0; 5456 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 5457 } 5458 } 5459 return 0; 5460 5461 } 5462 5463 uint32_t 5464 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val) 5465 { 5466 uint32_t new_val = orig_val; 5467 5468 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG) 5469 new_val |= IXGBE_VMOLR_AUPE; 5470 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC) 5471 new_val |= IXGBE_VMOLR_ROMPE; 5472 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC) 5473 new_val |= IXGBE_VMOLR_ROPE; 5474 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST) 5475 new_val |= IXGBE_VMOLR_BAM; 5476 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST) 5477 new_val |= IXGBE_VMOLR_MPE; 5478 5479 return new_val; 5480 } 5481 5482 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */ 5483 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */ 5484 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */ 5485 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */ 5486 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \ 5487 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \ 5488 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN)) 5489 5490 static int 5491 ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 5492 struct rte_eth_mirror_conf *mirror_conf, 5493 uint8_t rule_id, uint8_t on) 5494 { 5495 uint32_t mr_ctl, vlvf; 5496 uint32_t mp_lsb = 0; 5497 uint32_t mv_msb = 0; 5498 uint32_t mv_lsb = 0; 5499 uint32_t mp_msb = 0; 5500 uint8_t i = 0; 5501 int reg_index = 0; 5502 uint64_t vlan_mask = 0; 5503 5504 const uint8_t pool_mask_offset = 32; 5505 const uint8_t vlan_mask_offset = 32; 5506 const uint8_t dst_pool_offset = 8; 5507 const uint8_t rule_mr_offset = 4; 5508 const uint8_t mirror_rule_mask = 0x0F; 5509 5510 struct ixgbe_mirror_info *mr_info = 5511 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5512 struct ixgbe_hw *hw = 5513 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5514 uint8_t mirror_type = 0; 5515 5516 if (ixgbe_vt_check(hw) < 0) 5517 return -ENOTSUP; 5518 5519 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5520 return -EINVAL; 5521 5522 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) { 5523 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.", 5524 mirror_conf->rule_type); 5525 return -EINVAL; 5526 } 5527 5528 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5529 mirror_type |= IXGBE_MRCTL_VLME; 5530 /* Check if vlan id is valid and find conresponding VLAN ID 5531 * index in VLVF 5532 */ 5533 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) { 5534 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) { 5535 /* search vlan id related pool vlan filter 5536 * index 5537 */ 5538 reg_index = ixgbe_find_vlvf_slot( 5539 hw, 5540 mirror_conf->vlan.vlan_id[i], 5541 false); 5542 if (reg_index < 0) 5543 return -EINVAL; 5544 vlvf = IXGBE_READ_REG(hw, 5545 IXGBE_VLVF(reg_index)); 5546 if ((vlvf & IXGBE_VLVF_VIEN) && 5547 ((vlvf & IXGBE_VLVF_VLANID_MASK) == 5548 mirror_conf->vlan.vlan_id[i])) 5549 vlan_mask |= (1ULL << reg_index); 5550 else 5551 return -EINVAL; 5552 } 5553 } 5554 5555 if (on) { 5556 mv_lsb = vlan_mask & 0xFFFFFFFF; 5557 mv_msb = vlan_mask >> vlan_mask_offset; 5558 5559 mr_info->mr_conf[rule_id].vlan.vlan_mask = 5560 mirror_conf->vlan.vlan_mask; 5561 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) { 5562 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) 5563 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 5564 mirror_conf->vlan.vlan_id[i]; 5565 } 5566 } else { 5567 mv_lsb = 0; 5568 mv_msb = 0; 5569 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0; 5570 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) 5571 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0; 5572 } 5573 } 5574 5575 /** 5576 * if enable pool mirror, write related pool mask register,if disable 5577 * pool mirror, clear PFMRVM register 5578 */ 5579 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5580 mirror_type |= IXGBE_MRCTL_VPME; 5581 if (on) { 5582 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF; 5583 mp_msb = mirror_conf->pool_mask >> pool_mask_offset; 5584 mr_info->mr_conf[rule_id].pool_mask = 5585 mirror_conf->pool_mask; 5586 5587 } else { 5588 mp_lsb = 0; 5589 mp_msb = 0; 5590 mr_info->mr_conf[rule_id].pool_mask = 0; 5591 } 5592 } 5593 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT) 5594 mirror_type |= IXGBE_MRCTL_UPME; 5595 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT) 5596 mirror_type |= IXGBE_MRCTL_DPME; 5597 5598 /* read mirror control register and recalculate it */ 5599 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id)); 5600 5601 if (on) { 5602 mr_ctl |= mirror_type; 5603 mr_ctl &= mirror_rule_mask; 5604 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset; 5605 } else { 5606 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask); 5607 } 5608 5609 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type; 5610 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool; 5611 5612 /* write mirrror control register */ 5613 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5614 5615 /* write pool mirrror control register */ 5616 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5617 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb); 5618 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), 5619 mp_msb); 5620 } 5621 /* write VLAN mirrror control register */ 5622 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5623 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb); 5624 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), 5625 mv_msb); 5626 } 5627 5628 return 0; 5629 } 5630 5631 static int 5632 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id) 5633 { 5634 int mr_ctl = 0; 5635 uint32_t lsb_val = 0; 5636 uint32_t msb_val = 0; 5637 const uint8_t rule_mr_offset = 4; 5638 5639 struct ixgbe_hw *hw = 5640 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5641 struct ixgbe_mirror_info *mr_info = 5642 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5643 5644 if (ixgbe_vt_check(hw) < 0) 5645 return -ENOTSUP; 5646 5647 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5648 return -EINVAL; 5649 5650 memset(&mr_info->mr_conf[rule_id], 0, 5651 sizeof(struct rte_eth_mirror_conf)); 5652 5653 /* clear PFVMCTL register */ 5654 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5655 5656 /* clear pool mask register */ 5657 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val); 5658 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val); 5659 5660 /* clear vlan mask register */ 5661 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val); 5662 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val); 5663 5664 return 0; 5665 } 5666 5667 static int 5668 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5669 { 5670 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5671 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5672 struct ixgbe_interrupt *intr = 5673 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5674 struct ixgbe_hw *hw = 5675 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5676 uint32_t vec = IXGBE_MISC_VEC_ID; 5677 5678 if (rte_intr_allow_others(intr_handle)) 5679 vec = IXGBE_RX_VEC_START; 5680 intr->mask |= (1 << vec); 5681 RTE_SET_USED(queue_id); 5682 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5683 5684 rte_intr_enable(intr_handle); 5685 5686 return 0; 5687 } 5688 5689 static int 5690 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5691 { 5692 struct ixgbe_interrupt *intr = 5693 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5694 struct ixgbe_hw *hw = 5695 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5696 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5697 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5698 uint32_t vec = IXGBE_MISC_VEC_ID; 5699 5700 if (rte_intr_allow_others(intr_handle)) 5701 vec = IXGBE_RX_VEC_START; 5702 intr->mask &= ~(1 << vec); 5703 RTE_SET_USED(queue_id); 5704 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5705 5706 return 0; 5707 } 5708 5709 static int 5710 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5711 { 5712 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5713 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5714 uint32_t mask; 5715 struct ixgbe_hw *hw = 5716 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5717 struct ixgbe_interrupt *intr = 5718 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5719 5720 if (queue_id < 16) { 5721 ixgbe_disable_intr(hw); 5722 intr->mask |= (1 << queue_id); 5723 ixgbe_enable_intr(dev); 5724 } else if (queue_id < 32) { 5725 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5726 mask &= (1 << queue_id); 5727 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5728 } else if (queue_id < 64) { 5729 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5730 mask &= (1 << (queue_id - 32)); 5731 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5732 } 5733 rte_intr_enable(intr_handle); 5734 5735 return 0; 5736 } 5737 5738 static int 5739 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5740 { 5741 uint32_t mask; 5742 struct ixgbe_hw *hw = 5743 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5744 struct ixgbe_interrupt *intr = 5745 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5746 5747 if (queue_id < 16) { 5748 ixgbe_disable_intr(hw); 5749 intr->mask &= ~(1 << queue_id); 5750 ixgbe_enable_intr(dev); 5751 } else if (queue_id < 32) { 5752 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5753 mask &= ~(1 << queue_id); 5754 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5755 } else if (queue_id < 64) { 5756 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5757 mask &= ~(1 << (queue_id - 32)); 5758 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5759 } 5760 5761 return 0; 5762 } 5763 5764 static void 5765 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 5766 uint8_t queue, uint8_t msix_vector) 5767 { 5768 uint32_t tmp, idx; 5769 5770 if (direction == -1) { 5771 /* other causes */ 5772 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5773 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC); 5774 tmp &= ~0xFF; 5775 tmp |= msix_vector; 5776 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp); 5777 } else { 5778 /* rx or tx cause */ 5779 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5780 idx = ((16 * (queue & 1)) + (8 * direction)); 5781 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1)); 5782 tmp &= ~(0xFF << idx); 5783 tmp |= (msix_vector << idx); 5784 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp); 5785 } 5786 } 5787 5788 /** 5789 * set the IVAR registers, mapping interrupt causes to vectors 5790 * @param hw 5791 * pointer to ixgbe_hw struct 5792 * @direction 5793 * 0 for Rx, 1 for Tx, -1 for other causes 5794 * @queue 5795 * queue to map the corresponding interrupt to 5796 * @msix_vector 5797 * the vector to map to the corresponding queue 5798 */ 5799 static void 5800 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 5801 uint8_t queue, uint8_t msix_vector) 5802 { 5803 uint32_t tmp, idx; 5804 5805 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5806 if (hw->mac.type == ixgbe_mac_82598EB) { 5807 if (direction == -1) 5808 direction = 0; 5809 idx = (((direction * 64) + queue) >> 2) & 0x1F; 5810 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx)); 5811 tmp &= ~(0xFF << (8 * (queue & 0x3))); 5812 tmp |= (msix_vector << (8 * (queue & 0x3))); 5813 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp); 5814 } else if ((hw->mac.type == ixgbe_mac_82599EB) || 5815 (hw->mac.type == ixgbe_mac_X540) || 5816 (hw->mac.type == ixgbe_mac_X550)) { 5817 if (direction == -1) { 5818 /* other causes */ 5819 idx = ((queue & 1) * 8); 5820 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC); 5821 tmp &= ~(0xFF << idx); 5822 tmp |= (msix_vector << idx); 5823 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp); 5824 } else { 5825 /* rx or tx causes */ 5826 idx = ((16 * (queue & 1)) + (8 * direction)); 5827 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 5828 tmp &= ~(0xFF << idx); 5829 tmp |= (msix_vector << idx); 5830 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp); 5831 } 5832 } 5833 } 5834 5835 static void 5836 ixgbevf_configure_msix(struct rte_eth_dev *dev) 5837 { 5838 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5839 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5840 struct ixgbe_hw *hw = 5841 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5842 uint32_t q_idx; 5843 uint32_t vector_idx = IXGBE_MISC_VEC_ID; 5844 uint32_t base = IXGBE_MISC_VEC_ID; 5845 5846 /* Configure VF other cause ivar */ 5847 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx); 5848 5849 /* won't configure msix register if no mapping is done 5850 * between intr vector and event fd. 5851 */ 5852 if (!rte_intr_dp_is_en(intr_handle)) 5853 return; 5854 5855 if (rte_intr_allow_others(intr_handle)) { 5856 base = IXGBE_RX_VEC_START; 5857 vector_idx = IXGBE_RX_VEC_START; 5858 } 5859 5860 /* Configure all RX queues of VF */ 5861 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) { 5862 /* Force all queue use vector 0, 5863 * as IXGBE_VF_MAXMSIVECOTR = 1 5864 */ 5865 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx); 5866 intr_handle->intr_vec[q_idx] = vector_idx; 5867 if (vector_idx < base + intr_handle->nb_efd - 1) 5868 vector_idx++; 5869 } 5870 5871 /* As RX queue setting above show, all queues use the vector 0. 5872 * Set only the ITR value of IXGBE_MISC_VEC_ID. 5873 */ 5874 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID), 5875 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 5876 | IXGBE_EITR_CNT_WDIS); 5877 } 5878 5879 /** 5880 * Sets up the hardware to properly generate MSI-X interrupts 5881 * @hw 5882 * board private structure 5883 */ 5884 static void 5885 ixgbe_configure_msix(struct rte_eth_dev *dev) 5886 { 5887 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5888 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5889 struct ixgbe_hw *hw = 5890 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5891 uint32_t queue_id, base = IXGBE_MISC_VEC_ID; 5892 uint32_t vec = IXGBE_MISC_VEC_ID; 5893 uint32_t mask; 5894 uint32_t gpie; 5895 5896 /* won't configure msix register if no mapping is done 5897 * between intr vector and event fd 5898 * but if misx has been enabled already, need to configure 5899 * auto clean, auto mask and throttling. 5900 */ 5901 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 5902 if (!rte_intr_dp_is_en(intr_handle) && 5903 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT))) 5904 return; 5905 5906 if (rte_intr_allow_others(intr_handle)) 5907 vec = base = IXGBE_RX_VEC_START; 5908 5909 /* setup GPIE for MSI-x mode */ 5910 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 5911 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5912 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME; 5913 /* auto clearing and auto setting corresponding bits in EIMS 5914 * when MSI-X interrupt is triggered 5915 */ 5916 if (hw->mac.type == ixgbe_mac_82598EB) { 5917 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5918 } else { 5919 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5920 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5921 } 5922 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5923 5924 /* Populate the IVAR table and set the ITR values to the 5925 * corresponding register. 5926 */ 5927 if (rte_intr_dp_is_en(intr_handle)) { 5928 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; 5929 queue_id++) { 5930 /* by default, 1:1 mapping */ 5931 ixgbe_set_ivar_map(hw, 0, queue_id, vec); 5932 intr_handle->intr_vec[queue_id] = vec; 5933 if (vec < base + intr_handle->nb_efd - 1) 5934 vec++; 5935 } 5936 5937 switch (hw->mac.type) { 5938 case ixgbe_mac_82598EB: 5939 ixgbe_set_ivar_map(hw, -1, 5940 IXGBE_IVAR_OTHER_CAUSES_INDEX, 5941 IXGBE_MISC_VEC_ID); 5942 break; 5943 case ixgbe_mac_82599EB: 5944 case ixgbe_mac_X540: 5945 case ixgbe_mac_X550: 5946 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID); 5947 break; 5948 default: 5949 break; 5950 } 5951 } 5952 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID), 5953 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 5954 | IXGBE_EITR_CNT_WDIS); 5955 5956 /* set up to autoclear timer, and the vectors */ 5957 mask = IXGBE_EIMS_ENABLE_MASK; 5958 mask &= ~(IXGBE_EIMS_OTHER | 5959 IXGBE_EIMS_MAILBOX | 5960 IXGBE_EIMS_LSC); 5961 5962 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask); 5963 } 5964 5965 int 5966 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, 5967 uint16_t queue_idx, uint16_t tx_rate) 5968 { 5969 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5970 struct rte_eth_rxmode *rxmode; 5971 uint32_t rf_dec, rf_int; 5972 uint32_t bcnrc_val; 5973 uint16_t link_speed = dev->data->dev_link.link_speed; 5974 5975 if (queue_idx >= hw->mac.max_tx_queues) 5976 return -EINVAL; 5977 5978 if (tx_rate != 0) { 5979 /* Calculate the rate factor values to set */ 5980 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate; 5981 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate; 5982 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate; 5983 5984 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA; 5985 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) & 5986 IXGBE_RTTBCNRC_RF_INT_MASK_M); 5987 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK); 5988 } else { 5989 bcnrc_val = 0; 5990 } 5991 5992 rxmode = &dev->data->dev_conf.rxmode; 5993 /* 5994 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 5995 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise 5996 * set as 0x4. 5997 */ 5998 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) && 5999 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE)) 6000 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 6001 IXGBE_MMW_SIZE_JUMBO_FRAME); 6002 else 6003 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 6004 IXGBE_MMW_SIZE_DEFAULT); 6005 6006 /* Set RTTBCNRC of queue X */ 6007 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx); 6008 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 6009 IXGBE_WRITE_FLUSH(hw); 6010 6011 return 0; 6012 } 6013 6014 static int 6015 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr, 6016 __attribute__((unused)) uint32_t index, 6017 __attribute__((unused)) uint32_t pool) 6018 { 6019 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6020 int diag; 6021 6022 /* 6023 * On a 82599 VF, adding again the same MAC addr is not an idempotent 6024 * operation. Trap this case to avoid exhausting the [very limited] 6025 * set of PF resources used to store VF MAC addresses. 6026 */ 6027 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0) 6028 return -1; 6029 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6030 if (diag != 0) 6031 PMD_DRV_LOG(ERR, "Unable to add MAC address " 6032 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d", 6033 mac_addr->addr_bytes[0], 6034 mac_addr->addr_bytes[1], 6035 mac_addr->addr_bytes[2], 6036 mac_addr->addr_bytes[3], 6037 mac_addr->addr_bytes[4], 6038 mac_addr->addr_bytes[5], 6039 diag); 6040 return diag; 6041 } 6042 6043 static void 6044 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index) 6045 { 6046 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6047 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr; 6048 struct ether_addr *mac_addr; 6049 uint32_t i; 6050 int diag; 6051 6052 /* 6053 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does 6054 * not support the deletion of a given MAC address. 6055 * Instead, it imposes to delete all MAC addresses, then to add again 6056 * all MAC addresses with the exception of the one to be deleted. 6057 */ 6058 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL); 6059 6060 /* 6061 * Add again all MAC addresses, with the exception of the deleted one 6062 * and of the permanent MAC address. 6063 */ 6064 for (i = 0, mac_addr = dev->data->mac_addrs; 6065 i < hw->mac.num_rar_entries; i++, mac_addr++) { 6066 /* Skip the deleted MAC address */ 6067 if (i == index) 6068 continue; 6069 /* Skip NULL MAC addresses */ 6070 if (is_zero_ether_addr(mac_addr)) 6071 continue; 6072 /* Skip the permanent MAC address */ 6073 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0) 6074 continue; 6075 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6076 if (diag != 0) 6077 PMD_DRV_LOG(ERR, 6078 "Adding again MAC address " 6079 "%02x:%02x:%02x:%02x:%02x:%02x failed " 6080 "diag=%d", 6081 mac_addr->addr_bytes[0], 6082 mac_addr->addr_bytes[1], 6083 mac_addr->addr_bytes[2], 6084 mac_addr->addr_bytes[3], 6085 mac_addr->addr_bytes[4], 6086 mac_addr->addr_bytes[5], 6087 diag); 6088 } 6089 } 6090 6091 static int 6092 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr) 6093 { 6094 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6095 6096 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0); 6097 6098 return 0; 6099 } 6100 6101 int 6102 ixgbe_syn_filter_set(struct rte_eth_dev *dev, 6103 struct rte_eth_syn_filter *filter, 6104 bool add) 6105 { 6106 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6107 struct ixgbe_filter_info *filter_info = 6108 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6109 uint32_t syn_info; 6110 uint32_t synqf; 6111 6112 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6113 return -EINVAL; 6114 6115 syn_info = filter_info->syn_info; 6116 6117 if (add) { 6118 if (syn_info & IXGBE_SYN_FILTER_ENABLE) 6119 return -EINVAL; 6120 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) & 6121 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE); 6122 6123 if (filter->hig_pri) 6124 synqf |= IXGBE_SYN_FILTER_SYNQFP; 6125 else 6126 synqf &= ~IXGBE_SYN_FILTER_SYNQFP; 6127 } else { 6128 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6129 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE)) 6130 return -ENOENT; 6131 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE); 6132 } 6133 6134 filter_info->syn_info = synqf; 6135 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 6136 IXGBE_WRITE_FLUSH(hw); 6137 return 0; 6138 } 6139 6140 static int 6141 ixgbe_syn_filter_get(struct rte_eth_dev *dev, 6142 struct rte_eth_syn_filter *filter) 6143 { 6144 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6145 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6146 6147 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 6148 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0; 6149 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1); 6150 return 0; 6151 } 6152 return -ENOENT; 6153 } 6154 6155 static int 6156 ixgbe_syn_filter_handle(struct rte_eth_dev *dev, 6157 enum rte_filter_op filter_op, 6158 void *arg) 6159 { 6160 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6161 int ret; 6162 6163 MAC_TYPE_FILTER_SUP(hw->mac.type); 6164 6165 if (filter_op == RTE_ETH_FILTER_NOP) 6166 return 0; 6167 6168 if (arg == NULL) { 6169 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u", 6170 filter_op); 6171 return -EINVAL; 6172 } 6173 6174 switch (filter_op) { 6175 case RTE_ETH_FILTER_ADD: 6176 ret = ixgbe_syn_filter_set(dev, 6177 (struct rte_eth_syn_filter *)arg, 6178 TRUE); 6179 break; 6180 case RTE_ETH_FILTER_DELETE: 6181 ret = ixgbe_syn_filter_set(dev, 6182 (struct rte_eth_syn_filter *)arg, 6183 FALSE); 6184 break; 6185 case RTE_ETH_FILTER_GET: 6186 ret = ixgbe_syn_filter_get(dev, 6187 (struct rte_eth_syn_filter *)arg); 6188 break; 6189 default: 6190 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op); 6191 ret = -EINVAL; 6192 break; 6193 } 6194 6195 return ret; 6196 } 6197 6198 6199 static inline enum ixgbe_5tuple_protocol 6200 convert_protocol_type(uint8_t protocol_value) 6201 { 6202 if (protocol_value == IPPROTO_TCP) 6203 return IXGBE_FILTER_PROTOCOL_TCP; 6204 else if (protocol_value == IPPROTO_UDP) 6205 return IXGBE_FILTER_PROTOCOL_UDP; 6206 else if (protocol_value == IPPROTO_SCTP) 6207 return IXGBE_FILTER_PROTOCOL_SCTP; 6208 else 6209 return IXGBE_FILTER_PROTOCOL_NONE; 6210 } 6211 6212 /* inject a 5-tuple filter to HW */ 6213 static inline void 6214 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev, 6215 struct ixgbe_5tuple_filter *filter) 6216 { 6217 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6218 int i; 6219 uint32_t ftqf, sdpqf; 6220 uint32_t l34timir = 0; 6221 uint8_t mask = 0xff; 6222 6223 i = filter->index; 6224 6225 sdpqf = (uint32_t)(filter->filter_info.dst_port << 6226 IXGBE_SDPQF_DSTPORT_SHIFT); 6227 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT); 6228 6229 ftqf = (uint32_t)(filter->filter_info.proto & 6230 IXGBE_FTQF_PROTOCOL_MASK); 6231 ftqf |= (uint32_t)((filter->filter_info.priority & 6232 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT); 6233 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */ 6234 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK; 6235 if (filter->filter_info.dst_ip_mask == 0) 6236 mask &= IXGBE_FTQF_DEST_ADDR_MASK; 6237 if (filter->filter_info.src_port_mask == 0) 6238 mask &= IXGBE_FTQF_SOURCE_PORT_MASK; 6239 if (filter->filter_info.dst_port_mask == 0) 6240 mask &= IXGBE_FTQF_DEST_PORT_MASK; 6241 if (filter->filter_info.proto_mask == 0) 6242 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK; 6243 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT; 6244 ftqf |= IXGBE_FTQF_POOL_MASK_EN; 6245 ftqf |= IXGBE_FTQF_QUEUE_ENABLE; 6246 6247 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip); 6248 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip); 6249 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf); 6250 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf); 6251 6252 l34timir |= IXGBE_L34T_IMIR_RESERVE; 6253 l34timir |= (uint32_t)(filter->queue << 6254 IXGBE_L34T_IMIR_QUEUE_SHIFT); 6255 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir); 6256 } 6257 6258 /* 6259 * add a 5tuple filter 6260 * 6261 * @param 6262 * dev: Pointer to struct rte_eth_dev. 6263 * index: the index the filter allocates. 6264 * filter: ponter to the filter that will be added. 6265 * rx_queue: the queue id the filter assigned to. 6266 * 6267 * @return 6268 * - On success, zero. 6269 * - On failure, a negative value. 6270 */ 6271 static int 6272 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 6273 struct ixgbe_5tuple_filter *filter) 6274 { 6275 struct ixgbe_filter_info *filter_info = 6276 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6277 int i, idx, shift; 6278 6279 /* 6280 * look for an unused 5tuple filter index, 6281 * and insert the filter to list. 6282 */ 6283 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) { 6284 idx = i / (sizeof(uint32_t) * NBBY); 6285 shift = i % (sizeof(uint32_t) * NBBY); 6286 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) { 6287 filter_info->fivetuple_mask[idx] |= 1 << shift; 6288 filter->index = i; 6289 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list, 6290 filter, 6291 entries); 6292 break; 6293 } 6294 } 6295 if (i >= IXGBE_MAX_FTQF_FILTERS) { 6296 PMD_DRV_LOG(ERR, "5tuple filters are full."); 6297 return -ENOSYS; 6298 } 6299 6300 ixgbe_inject_5tuple_filter(dev, filter); 6301 6302 return 0; 6303 } 6304 6305 /* 6306 * remove a 5tuple filter 6307 * 6308 * @param 6309 * dev: Pointer to struct rte_eth_dev. 6310 * filter: the pointer of the filter will be removed. 6311 */ 6312 static void 6313 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 6314 struct ixgbe_5tuple_filter *filter) 6315 { 6316 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6317 struct ixgbe_filter_info *filter_info = 6318 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6319 uint16_t index = filter->index; 6320 6321 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &= 6322 ~(1 << (index % (sizeof(uint32_t) * NBBY))); 6323 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries); 6324 rte_free(filter); 6325 6326 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0); 6327 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0); 6328 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0); 6329 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0); 6330 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0); 6331 } 6332 6333 static int 6334 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 6335 { 6336 struct ixgbe_hw *hw; 6337 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 6338 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode; 6339 6340 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6341 6342 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN)) 6343 return -EINVAL; 6344 6345 /* refuse mtu that requires the support of scattered packets when this 6346 * feature has not been enabled before. 6347 */ 6348 if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) && 6349 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE > 6350 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) 6351 return -EINVAL; 6352 6353 /* 6354 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU 6355 * request of the version 2.0 of the mailbox API. 6356 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0 6357 * of the mailbox API. 6358 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers 6359 * prior to 3.11.33 which contains the following change: 6360 * "ixgbe: Enable jumbo frames support w/ SR-IOV" 6361 */ 6362 ixgbevf_rlpml_set_vf(hw, max_frame); 6363 6364 /* update max frame size */ 6365 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame; 6366 return 0; 6367 } 6368 6369 static inline struct ixgbe_5tuple_filter * 6370 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list, 6371 struct ixgbe_5tuple_filter_info *key) 6372 { 6373 struct ixgbe_5tuple_filter *it; 6374 6375 TAILQ_FOREACH(it, filter_list, entries) { 6376 if (memcmp(key, &it->filter_info, 6377 sizeof(struct ixgbe_5tuple_filter_info)) == 0) { 6378 return it; 6379 } 6380 } 6381 return NULL; 6382 } 6383 6384 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/ 6385 static inline int 6386 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter, 6387 struct ixgbe_5tuple_filter_info *filter_info) 6388 { 6389 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM || 6390 filter->priority > IXGBE_5TUPLE_MAX_PRI || 6391 filter->priority < IXGBE_5TUPLE_MIN_PRI) 6392 return -EINVAL; 6393 6394 switch (filter->dst_ip_mask) { 6395 case UINT32_MAX: 6396 filter_info->dst_ip_mask = 0; 6397 filter_info->dst_ip = filter->dst_ip; 6398 break; 6399 case 0: 6400 filter_info->dst_ip_mask = 1; 6401 break; 6402 default: 6403 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 6404 return -EINVAL; 6405 } 6406 6407 switch (filter->src_ip_mask) { 6408 case UINT32_MAX: 6409 filter_info->src_ip_mask = 0; 6410 filter_info->src_ip = filter->src_ip; 6411 break; 6412 case 0: 6413 filter_info->src_ip_mask = 1; 6414 break; 6415 default: 6416 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 6417 return -EINVAL; 6418 } 6419 6420 switch (filter->dst_port_mask) { 6421 case UINT16_MAX: 6422 filter_info->dst_port_mask = 0; 6423 filter_info->dst_port = filter->dst_port; 6424 break; 6425 case 0: 6426 filter_info->dst_port_mask = 1; 6427 break; 6428 default: 6429 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 6430 return -EINVAL; 6431 } 6432 6433 switch (filter->src_port_mask) { 6434 case UINT16_MAX: 6435 filter_info->src_port_mask = 0; 6436 filter_info->src_port = filter->src_port; 6437 break; 6438 case 0: 6439 filter_info->src_port_mask = 1; 6440 break; 6441 default: 6442 PMD_DRV_LOG(ERR, "invalid src_port mask."); 6443 return -EINVAL; 6444 } 6445 6446 switch (filter->proto_mask) { 6447 case UINT8_MAX: 6448 filter_info->proto_mask = 0; 6449 filter_info->proto = 6450 convert_protocol_type(filter->proto); 6451 break; 6452 case 0: 6453 filter_info->proto_mask = 1; 6454 break; 6455 default: 6456 PMD_DRV_LOG(ERR, "invalid protocol mask."); 6457 return -EINVAL; 6458 } 6459 6460 filter_info->priority = (uint8_t)filter->priority; 6461 return 0; 6462 } 6463 6464 /* 6465 * add or delete a ntuple filter 6466 * 6467 * @param 6468 * dev: Pointer to struct rte_eth_dev. 6469 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6470 * add: if true, add filter, if false, remove filter 6471 * 6472 * @return 6473 * - On success, zero. 6474 * - On failure, a negative value. 6475 */ 6476 int 6477 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 6478 struct rte_eth_ntuple_filter *ntuple_filter, 6479 bool add) 6480 { 6481 struct ixgbe_filter_info *filter_info = 6482 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6483 struct ixgbe_5tuple_filter_info filter_5tuple; 6484 struct ixgbe_5tuple_filter *filter; 6485 int ret; 6486 6487 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6488 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6489 return -EINVAL; 6490 } 6491 6492 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6493 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6494 if (ret < 0) 6495 return ret; 6496 6497 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6498 &filter_5tuple); 6499 if (filter != NULL && add) { 6500 PMD_DRV_LOG(ERR, "filter exists."); 6501 return -EEXIST; 6502 } 6503 if (filter == NULL && !add) { 6504 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6505 return -ENOENT; 6506 } 6507 6508 if (add) { 6509 filter = rte_zmalloc("ixgbe_5tuple_filter", 6510 sizeof(struct ixgbe_5tuple_filter), 0); 6511 if (filter == NULL) 6512 return -ENOMEM; 6513 rte_memcpy(&filter->filter_info, 6514 &filter_5tuple, 6515 sizeof(struct ixgbe_5tuple_filter_info)); 6516 filter->queue = ntuple_filter->queue; 6517 ret = ixgbe_add_5tuple_filter(dev, filter); 6518 if (ret < 0) { 6519 rte_free(filter); 6520 return ret; 6521 } 6522 } else 6523 ixgbe_remove_5tuple_filter(dev, filter); 6524 6525 return 0; 6526 } 6527 6528 /* 6529 * get a ntuple filter 6530 * 6531 * @param 6532 * dev: Pointer to struct rte_eth_dev. 6533 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6534 * 6535 * @return 6536 * - On success, zero. 6537 * - On failure, a negative value. 6538 */ 6539 static int 6540 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev, 6541 struct rte_eth_ntuple_filter *ntuple_filter) 6542 { 6543 struct ixgbe_filter_info *filter_info = 6544 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6545 struct ixgbe_5tuple_filter_info filter_5tuple; 6546 struct ixgbe_5tuple_filter *filter; 6547 int ret; 6548 6549 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6550 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6551 return -EINVAL; 6552 } 6553 6554 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6555 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6556 if (ret < 0) 6557 return ret; 6558 6559 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6560 &filter_5tuple); 6561 if (filter == NULL) { 6562 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6563 return -ENOENT; 6564 } 6565 ntuple_filter->queue = filter->queue; 6566 return 0; 6567 } 6568 6569 /* 6570 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter. 6571 * @dev: pointer to rte_eth_dev structure 6572 * @filter_op:operation will be taken. 6573 * @arg: a pointer to specific structure corresponding to the filter_op 6574 * 6575 * @return 6576 * - On success, zero. 6577 * - On failure, a negative value. 6578 */ 6579 static int 6580 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev, 6581 enum rte_filter_op filter_op, 6582 void *arg) 6583 { 6584 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6585 int ret; 6586 6587 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type); 6588 6589 if (filter_op == RTE_ETH_FILTER_NOP) 6590 return 0; 6591 6592 if (arg == NULL) { 6593 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 6594 filter_op); 6595 return -EINVAL; 6596 } 6597 6598 switch (filter_op) { 6599 case RTE_ETH_FILTER_ADD: 6600 ret = ixgbe_add_del_ntuple_filter(dev, 6601 (struct rte_eth_ntuple_filter *)arg, 6602 TRUE); 6603 break; 6604 case RTE_ETH_FILTER_DELETE: 6605 ret = ixgbe_add_del_ntuple_filter(dev, 6606 (struct rte_eth_ntuple_filter *)arg, 6607 FALSE); 6608 break; 6609 case RTE_ETH_FILTER_GET: 6610 ret = ixgbe_get_ntuple_filter(dev, 6611 (struct rte_eth_ntuple_filter *)arg); 6612 break; 6613 default: 6614 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 6615 ret = -EINVAL; 6616 break; 6617 } 6618 return ret; 6619 } 6620 6621 int 6622 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 6623 struct rte_eth_ethertype_filter *filter, 6624 bool add) 6625 { 6626 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6627 struct ixgbe_filter_info *filter_info = 6628 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6629 uint32_t etqf = 0; 6630 uint32_t etqs = 0; 6631 int ret; 6632 struct ixgbe_ethertype_filter ethertype_filter; 6633 6634 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6635 return -EINVAL; 6636 6637 if (filter->ether_type == ETHER_TYPE_IPv4 || 6638 filter->ether_type == ETHER_TYPE_IPv6) { 6639 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in" 6640 " ethertype filter.", filter->ether_type); 6641 return -EINVAL; 6642 } 6643 6644 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) { 6645 PMD_DRV_LOG(ERR, "mac compare is unsupported."); 6646 return -EINVAL; 6647 } 6648 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) { 6649 PMD_DRV_LOG(ERR, "drop option is unsupported."); 6650 return -EINVAL; 6651 } 6652 6653 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6654 if (ret >= 0 && add) { 6655 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.", 6656 filter->ether_type); 6657 return -EEXIST; 6658 } 6659 if (ret < 0 && !add) { 6660 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6661 filter->ether_type); 6662 return -ENOENT; 6663 } 6664 6665 if (add) { 6666 etqf = IXGBE_ETQF_FILTER_EN; 6667 etqf |= (uint32_t)filter->ether_type; 6668 etqs |= (uint32_t)((filter->queue << 6669 IXGBE_ETQS_RX_QUEUE_SHIFT) & 6670 IXGBE_ETQS_RX_QUEUE); 6671 etqs |= IXGBE_ETQS_QUEUE_EN; 6672 6673 ethertype_filter.ethertype = filter->ether_type; 6674 ethertype_filter.etqf = etqf; 6675 ethertype_filter.etqs = etqs; 6676 ethertype_filter.conf = FALSE; 6677 ret = ixgbe_ethertype_filter_insert(filter_info, 6678 ðertype_filter); 6679 if (ret < 0) { 6680 PMD_DRV_LOG(ERR, "ethertype filters are full."); 6681 return -ENOSPC; 6682 } 6683 } else { 6684 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret); 6685 if (ret < 0) 6686 return -ENOSYS; 6687 } 6688 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf); 6689 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs); 6690 IXGBE_WRITE_FLUSH(hw); 6691 6692 return 0; 6693 } 6694 6695 static int 6696 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, 6697 struct rte_eth_ethertype_filter *filter) 6698 { 6699 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6700 struct ixgbe_filter_info *filter_info = 6701 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6702 uint32_t etqf, etqs; 6703 int ret; 6704 6705 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6706 if (ret < 0) { 6707 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6708 filter->ether_type); 6709 return -ENOENT; 6710 } 6711 6712 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret)); 6713 if (etqf & IXGBE_ETQF_FILTER_EN) { 6714 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret)); 6715 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE; 6716 filter->flags = 0; 6717 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> 6718 IXGBE_ETQS_RX_QUEUE_SHIFT; 6719 return 0; 6720 } 6721 return -ENOENT; 6722 } 6723 6724 /* 6725 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter. 6726 * @dev: pointer to rte_eth_dev structure 6727 * @filter_op:operation will be taken. 6728 * @arg: a pointer to specific structure corresponding to the filter_op 6729 */ 6730 static int 6731 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev, 6732 enum rte_filter_op filter_op, 6733 void *arg) 6734 { 6735 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6736 int ret; 6737 6738 MAC_TYPE_FILTER_SUP(hw->mac.type); 6739 6740 if (filter_op == RTE_ETH_FILTER_NOP) 6741 return 0; 6742 6743 if (arg == NULL) { 6744 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 6745 filter_op); 6746 return -EINVAL; 6747 } 6748 6749 switch (filter_op) { 6750 case RTE_ETH_FILTER_ADD: 6751 ret = ixgbe_add_del_ethertype_filter(dev, 6752 (struct rte_eth_ethertype_filter *)arg, 6753 TRUE); 6754 break; 6755 case RTE_ETH_FILTER_DELETE: 6756 ret = ixgbe_add_del_ethertype_filter(dev, 6757 (struct rte_eth_ethertype_filter *)arg, 6758 FALSE); 6759 break; 6760 case RTE_ETH_FILTER_GET: 6761 ret = ixgbe_get_ethertype_filter(dev, 6762 (struct rte_eth_ethertype_filter *)arg); 6763 break; 6764 default: 6765 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 6766 ret = -EINVAL; 6767 break; 6768 } 6769 return ret; 6770 } 6771 6772 static int 6773 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 6774 enum rte_filter_type filter_type, 6775 enum rte_filter_op filter_op, 6776 void *arg) 6777 { 6778 int ret = 0; 6779 6780 switch (filter_type) { 6781 case RTE_ETH_FILTER_NTUPLE: 6782 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg); 6783 break; 6784 case RTE_ETH_FILTER_ETHERTYPE: 6785 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg); 6786 break; 6787 case RTE_ETH_FILTER_SYN: 6788 ret = ixgbe_syn_filter_handle(dev, filter_op, arg); 6789 break; 6790 case RTE_ETH_FILTER_FDIR: 6791 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg); 6792 break; 6793 case RTE_ETH_FILTER_L2_TUNNEL: 6794 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg); 6795 break; 6796 case RTE_ETH_FILTER_GENERIC: 6797 if (filter_op != RTE_ETH_FILTER_GET) 6798 return -EINVAL; 6799 *(const void **)arg = &ixgbe_flow_ops; 6800 break; 6801 default: 6802 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 6803 filter_type); 6804 ret = -EINVAL; 6805 break; 6806 } 6807 6808 return ret; 6809 } 6810 6811 static u8 * 6812 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw, 6813 u8 **mc_addr_ptr, u32 *vmdq) 6814 { 6815 u8 *mc_addr; 6816 6817 *vmdq = 0; 6818 mc_addr = *mc_addr_ptr; 6819 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr)); 6820 return mc_addr; 6821 } 6822 6823 static int 6824 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 6825 struct ether_addr *mc_addr_set, 6826 uint32_t nb_mc_addr) 6827 { 6828 struct ixgbe_hw *hw; 6829 u8 *mc_addr_list; 6830 6831 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6832 mc_addr_list = (u8 *)mc_addr_set; 6833 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr, 6834 ixgbe_dev_addr_list_itr, TRUE); 6835 } 6836 6837 static uint64_t 6838 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev) 6839 { 6840 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6841 uint64_t systime_cycles; 6842 6843 switch (hw->mac.type) { 6844 case ixgbe_mac_X550: 6845 case ixgbe_mac_X550EM_x: 6846 case ixgbe_mac_X550EM_a: 6847 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */ 6848 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 6849 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 6850 * NSEC_PER_SEC; 6851 break; 6852 default: 6853 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 6854 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 6855 << 32; 6856 } 6857 6858 return systime_cycles; 6859 } 6860 6861 static uint64_t 6862 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) 6863 { 6864 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6865 uint64_t rx_tstamp_cycles; 6866 6867 switch (hw->mac.type) { 6868 case ixgbe_mac_X550: 6869 case ixgbe_mac_X550EM_x: 6870 case ixgbe_mac_X550EM_a: 6871 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 6872 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 6873 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 6874 * NSEC_PER_SEC; 6875 break; 6876 default: 6877 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 6878 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 6879 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 6880 << 32; 6881 } 6882 6883 return rx_tstamp_cycles; 6884 } 6885 6886 static uint64_t 6887 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 6888 { 6889 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6890 uint64_t tx_tstamp_cycles; 6891 6892 switch (hw->mac.type) { 6893 case ixgbe_mac_X550: 6894 case ixgbe_mac_X550EM_x: 6895 case ixgbe_mac_X550EM_a: 6896 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 6897 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 6898 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 6899 * NSEC_PER_SEC; 6900 break; 6901 default: 6902 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 6903 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 6904 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 6905 << 32; 6906 } 6907 6908 return tx_tstamp_cycles; 6909 } 6910 6911 static void 6912 ixgbe_start_timecounters(struct rte_eth_dev *dev) 6913 { 6914 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6915 struct ixgbe_adapter *adapter = 6916 (struct ixgbe_adapter *)dev->data->dev_private; 6917 struct rte_eth_link link; 6918 uint32_t incval = 0; 6919 uint32_t shift = 0; 6920 6921 /* Get current link speed. */ 6922 ixgbe_dev_link_update(dev, 1); 6923 rte_eth_linkstatus_get(dev, &link); 6924 6925 switch (link.link_speed) { 6926 case ETH_SPEED_NUM_100M: 6927 incval = IXGBE_INCVAL_100; 6928 shift = IXGBE_INCVAL_SHIFT_100; 6929 break; 6930 case ETH_SPEED_NUM_1G: 6931 incval = IXGBE_INCVAL_1GB; 6932 shift = IXGBE_INCVAL_SHIFT_1GB; 6933 break; 6934 case ETH_SPEED_NUM_10G: 6935 default: 6936 incval = IXGBE_INCVAL_10GB; 6937 shift = IXGBE_INCVAL_SHIFT_10GB; 6938 break; 6939 } 6940 6941 switch (hw->mac.type) { 6942 case ixgbe_mac_X550: 6943 case ixgbe_mac_X550EM_x: 6944 case ixgbe_mac_X550EM_a: 6945 /* Independent of link speed. */ 6946 incval = 1; 6947 /* Cycles read will be interpreted as ns. */ 6948 shift = 0; 6949 /* Fall-through */ 6950 case ixgbe_mac_X540: 6951 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval); 6952 break; 6953 case ixgbe_mac_82599EB: 6954 incval >>= IXGBE_INCVAL_SHIFT_82599; 6955 shift -= IXGBE_INCVAL_SHIFT_82599; 6956 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 6957 (1 << IXGBE_INCPER_SHIFT_82599) | incval); 6958 break; 6959 default: 6960 /* Not supported. */ 6961 return; 6962 } 6963 6964 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 6965 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 6966 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 6967 6968 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6969 adapter->systime_tc.cc_shift = shift; 6970 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; 6971 6972 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6973 adapter->rx_tstamp_tc.cc_shift = shift; 6974 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 6975 6976 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6977 adapter->tx_tstamp_tc.cc_shift = shift; 6978 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 6979 } 6980 6981 static int 6982 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 6983 { 6984 struct ixgbe_adapter *adapter = 6985 (struct ixgbe_adapter *)dev->data->dev_private; 6986 6987 adapter->systime_tc.nsec += delta; 6988 adapter->rx_tstamp_tc.nsec += delta; 6989 adapter->tx_tstamp_tc.nsec += delta; 6990 6991 return 0; 6992 } 6993 6994 static int 6995 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 6996 { 6997 uint64_t ns; 6998 struct ixgbe_adapter *adapter = 6999 (struct ixgbe_adapter *)dev->data->dev_private; 7000 7001 ns = rte_timespec_to_ns(ts); 7002 /* Set the timecounters to a new value. */ 7003 adapter->systime_tc.nsec = ns; 7004 adapter->rx_tstamp_tc.nsec = ns; 7005 adapter->tx_tstamp_tc.nsec = ns; 7006 7007 return 0; 7008 } 7009 7010 static int 7011 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 7012 { 7013 uint64_t ns, systime_cycles; 7014 struct ixgbe_adapter *adapter = 7015 (struct ixgbe_adapter *)dev->data->dev_private; 7016 7017 systime_cycles = ixgbe_read_systime_cyclecounter(dev); 7018 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 7019 *ts = rte_ns_to_timespec(ns); 7020 7021 return 0; 7022 } 7023 7024 static int 7025 ixgbe_timesync_enable(struct rte_eth_dev *dev) 7026 { 7027 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7028 uint32_t tsync_ctl; 7029 uint32_t tsauxc; 7030 7031 /* Stop the timesync system time. */ 7032 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0); 7033 /* Reset the timesync system time value. */ 7034 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0); 7035 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0); 7036 7037 /* Enable system time for platforms where it isn't on by default. */ 7038 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC); 7039 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME; 7040 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc); 7041 7042 ixgbe_start_timecounters(dev); 7043 7044 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7045 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 7046 (ETHER_TYPE_1588 | 7047 IXGBE_ETQF_FILTER_EN | 7048 IXGBE_ETQF_1588)); 7049 7050 /* Enable timestamping of received PTP packets. */ 7051 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7052 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED; 7053 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7054 7055 /* Enable timestamping of transmitted PTP packets. */ 7056 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7057 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED; 7058 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7059 7060 IXGBE_WRITE_FLUSH(hw); 7061 7062 return 0; 7063 } 7064 7065 static int 7066 ixgbe_timesync_disable(struct rte_eth_dev *dev) 7067 { 7068 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7069 uint32_t tsync_ctl; 7070 7071 /* Disable timestamping of transmitted PTP packets. */ 7072 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7073 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED; 7074 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7075 7076 /* Disable timestamping of received PTP packets. */ 7077 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7078 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED; 7079 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7080 7081 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7082 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0); 7083 7084 /* Stop incrementating the System Time registers. */ 7085 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0); 7086 7087 return 0; 7088 } 7089 7090 static int 7091 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 7092 struct timespec *timestamp, 7093 uint32_t flags __rte_unused) 7094 { 7095 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7096 struct ixgbe_adapter *adapter = 7097 (struct ixgbe_adapter *)dev->data->dev_private; 7098 uint32_t tsync_rxctl; 7099 uint64_t rx_tstamp_cycles; 7100 uint64_t ns; 7101 7102 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7103 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0) 7104 return -EINVAL; 7105 7106 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev); 7107 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 7108 *timestamp = rte_ns_to_timespec(ns); 7109 7110 return 0; 7111 } 7112 7113 static int 7114 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 7115 struct timespec *timestamp) 7116 { 7117 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7118 struct ixgbe_adapter *adapter = 7119 (struct ixgbe_adapter *)dev->data->dev_private; 7120 uint32_t tsync_txctl; 7121 uint64_t tx_tstamp_cycles; 7122 uint64_t ns; 7123 7124 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7125 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0) 7126 return -EINVAL; 7127 7128 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev); 7129 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 7130 *timestamp = rte_ns_to_timespec(ns); 7131 7132 return 0; 7133 } 7134 7135 static int 7136 ixgbe_get_reg_length(struct rte_eth_dev *dev) 7137 { 7138 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7139 int count = 0; 7140 int g_ind = 0; 7141 const struct reg_info *reg_group; 7142 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7143 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7144 7145 while ((reg_group = reg_set[g_ind++])) 7146 count += ixgbe_regs_group_count(reg_group); 7147 7148 return count; 7149 } 7150 7151 static int 7152 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused) 7153 { 7154 int count = 0; 7155 int g_ind = 0; 7156 const struct reg_info *reg_group; 7157 7158 while ((reg_group = ixgbevf_regs[g_ind++])) 7159 count += ixgbe_regs_group_count(reg_group); 7160 7161 return count; 7162 } 7163 7164 static int 7165 ixgbe_get_regs(struct rte_eth_dev *dev, 7166 struct rte_dev_reg_info *regs) 7167 { 7168 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7169 uint32_t *data = regs->data; 7170 int g_ind = 0; 7171 int count = 0; 7172 const struct reg_info *reg_group; 7173 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7174 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7175 7176 if (data == NULL) { 7177 regs->length = ixgbe_get_reg_length(dev); 7178 regs->width = sizeof(uint32_t); 7179 return 0; 7180 } 7181 7182 /* Support only full register dump */ 7183 if ((regs->length == 0) || 7184 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) { 7185 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7186 hw->device_id; 7187 while ((reg_group = reg_set[g_ind++])) 7188 count += ixgbe_read_regs_group(dev, &data[count], 7189 reg_group); 7190 return 0; 7191 } 7192 7193 return -ENOTSUP; 7194 } 7195 7196 static int 7197 ixgbevf_get_regs(struct rte_eth_dev *dev, 7198 struct rte_dev_reg_info *regs) 7199 { 7200 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7201 uint32_t *data = regs->data; 7202 int g_ind = 0; 7203 int count = 0; 7204 const struct reg_info *reg_group; 7205 7206 if (data == NULL) { 7207 regs->length = ixgbevf_get_reg_length(dev); 7208 regs->width = sizeof(uint32_t); 7209 return 0; 7210 } 7211 7212 /* Support only full register dump */ 7213 if ((regs->length == 0) || 7214 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) { 7215 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7216 hw->device_id; 7217 while ((reg_group = ixgbevf_regs[g_ind++])) 7218 count += ixgbe_read_regs_group(dev, &data[count], 7219 reg_group); 7220 return 0; 7221 } 7222 7223 return -ENOTSUP; 7224 } 7225 7226 static int 7227 ixgbe_get_eeprom_length(struct rte_eth_dev *dev) 7228 { 7229 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7230 7231 /* Return unit is byte count */ 7232 return hw->eeprom.word_size * 2; 7233 } 7234 7235 static int 7236 ixgbe_get_eeprom(struct rte_eth_dev *dev, 7237 struct rte_dev_eeprom_info *in_eeprom) 7238 { 7239 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7240 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7241 uint16_t *data = in_eeprom->data; 7242 int first, length; 7243 7244 first = in_eeprom->offset >> 1; 7245 length = in_eeprom->length >> 1; 7246 if ((first > hw->eeprom.word_size) || 7247 ((first + length) > hw->eeprom.word_size)) 7248 return -EINVAL; 7249 7250 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7251 7252 return eeprom->ops.read_buffer(hw, first, length, data); 7253 } 7254 7255 static int 7256 ixgbe_set_eeprom(struct rte_eth_dev *dev, 7257 struct rte_dev_eeprom_info *in_eeprom) 7258 { 7259 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7260 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7261 uint16_t *data = in_eeprom->data; 7262 int first, length; 7263 7264 first = in_eeprom->offset >> 1; 7265 length = in_eeprom->length >> 1; 7266 if ((first > hw->eeprom.word_size) || 7267 ((first + length) > hw->eeprom.word_size)) 7268 return -EINVAL; 7269 7270 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7271 7272 return eeprom->ops.write_buffer(hw, first, length, data); 7273 } 7274 7275 static int 7276 ixgbe_get_module_info(struct rte_eth_dev *dev, 7277 struct rte_eth_dev_module_info *modinfo) 7278 { 7279 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7280 uint32_t status; 7281 uint8_t sff8472_rev, addr_mode; 7282 bool page_swap = false; 7283 7284 /* Check whether we support SFF-8472 or not */ 7285 status = hw->phy.ops.read_i2c_eeprom(hw, 7286 IXGBE_SFF_SFF_8472_COMP, 7287 &sff8472_rev); 7288 if (status != 0) 7289 return -EIO; 7290 7291 /* addressing mode is not supported */ 7292 status = hw->phy.ops.read_i2c_eeprom(hw, 7293 IXGBE_SFF_SFF_8472_SWAP, 7294 &addr_mode); 7295 if (status != 0) 7296 return -EIO; 7297 7298 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 7299 PMD_DRV_LOG(ERR, 7300 "Address change required to access page 0xA2, " 7301 "but not supported. Please report the module " 7302 "type to the driver maintainers."); 7303 page_swap = true; 7304 } 7305 7306 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) { 7307 /* We have a SFP, but it does not support SFF-8472 */ 7308 modinfo->type = RTE_ETH_MODULE_SFF_8079; 7309 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 7310 } else { 7311 /* We have a SFP which supports a revision of SFF-8472. */ 7312 modinfo->type = RTE_ETH_MODULE_SFF_8472; 7313 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 7314 } 7315 7316 return 0; 7317 } 7318 7319 static int 7320 ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 7321 struct rte_dev_eeprom_info *info) 7322 { 7323 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7324 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 7325 uint8_t databyte = 0xFF; 7326 uint8_t *data = info->data; 7327 uint32_t i = 0; 7328 7329 if (info->length == 0) 7330 return -EINVAL; 7331 7332 for (i = info->offset; i < info->offset + info->length; i++) { 7333 if (i < RTE_ETH_MODULE_SFF_8079_LEN) 7334 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 7335 else 7336 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 7337 7338 if (status != 0) 7339 return -EIO; 7340 7341 data[i - info->offset] = databyte; 7342 } 7343 7344 return 0; 7345 } 7346 7347 uint16_t 7348 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) { 7349 switch (mac_type) { 7350 case ixgbe_mac_X550: 7351 case ixgbe_mac_X550EM_x: 7352 case ixgbe_mac_X550EM_a: 7353 return ETH_RSS_RETA_SIZE_512; 7354 case ixgbe_mac_X550_vf: 7355 case ixgbe_mac_X550EM_x_vf: 7356 case ixgbe_mac_X550EM_a_vf: 7357 return ETH_RSS_RETA_SIZE_64; 7358 default: 7359 return ETH_RSS_RETA_SIZE_128; 7360 } 7361 } 7362 7363 uint32_t 7364 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) { 7365 switch (mac_type) { 7366 case ixgbe_mac_X550: 7367 case ixgbe_mac_X550EM_x: 7368 case ixgbe_mac_X550EM_a: 7369 if (reta_idx < ETH_RSS_RETA_SIZE_128) 7370 return IXGBE_RETA(reta_idx >> 2); 7371 else 7372 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2); 7373 case ixgbe_mac_X550_vf: 7374 case ixgbe_mac_X550EM_x_vf: 7375 case ixgbe_mac_X550EM_a_vf: 7376 return IXGBE_VFRETA(reta_idx >> 2); 7377 default: 7378 return IXGBE_RETA(reta_idx >> 2); 7379 } 7380 } 7381 7382 uint32_t 7383 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) { 7384 switch (mac_type) { 7385 case ixgbe_mac_X550_vf: 7386 case ixgbe_mac_X550EM_x_vf: 7387 case ixgbe_mac_X550EM_a_vf: 7388 return IXGBE_VFMRQC; 7389 default: 7390 return IXGBE_MRQC; 7391 } 7392 } 7393 7394 uint32_t 7395 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) { 7396 switch (mac_type) { 7397 case ixgbe_mac_X550_vf: 7398 case ixgbe_mac_X550EM_x_vf: 7399 case ixgbe_mac_X550EM_a_vf: 7400 return IXGBE_VFRSSRK(i); 7401 default: 7402 return IXGBE_RSSRK(i); 7403 } 7404 } 7405 7406 bool 7407 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) { 7408 switch (mac_type) { 7409 case ixgbe_mac_82599_vf: 7410 case ixgbe_mac_X540_vf: 7411 return 0; 7412 default: 7413 return 1; 7414 } 7415 } 7416 7417 static int 7418 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 7419 struct rte_eth_dcb_info *dcb_info) 7420 { 7421 struct ixgbe_dcb_config *dcb_config = 7422 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 7423 struct ixgbe_dcb_tc_config *tc; 7424 struct rte_eth_dcb_tc_queue_mapping *tc_queue; 7425 uint8_t nb_tcs; 7426 uint8_t i, j; 7427 7428 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG) 7429 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs; 7430 else 7431 dcb_info->nb_tcs = 1; 7432 7433 tc_queue = &dcb_info->tc_queue; 7434 nb_tcs = dcb_info->nb_tcs; 7435 7436 if (dcb_config->vt_mode) { /* vt is enabled*/ 7437 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf = 7438 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf; 7439 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7440 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i]; 7441 if (RTE_ETH_DEV_SRIOV(dev).active > 0) { 7442 for (j = 0; j < nb_tcs; j++) { 7443 tc_queue->tc_rxq[0][j].base = j; 7444 tc_queue->tc_rxq[0][j].nb_queue = 1; 7445 tc_queue->tc_txq[0][j].base = j; 7446 tc_queue->tc_txq[0][j].nb_queue = 1; 7447 } 7448 } else { 7449 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) { 7450 for (j = 0; j < nb_tcs; j++) { 7451 tc_queue->tc_rxq[i][j].base = 7452 i * nb_tcs + j; 7453 tc_queue->tc_rxq[i][j].nb_queue = 1; 7454 tc_queue->tc_txq[i][j].base = 7455 i * nb_tcs + j; 7456 tc_queue->tc_txq[i][j].nb_queue = 1; 7457 } 7458 } 7459 } 7460 } else { /* vt is disabled*/ 7461 struct rte_eth_dcb_rx_conf *rx_conf = 7462 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 7463 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7464 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i]; 7465 if (dcb_info->nb_tcs == ETH_4_TCS) { 7466 for (i = 0; i < dcb_info->nb_tcs; i++) { 7467 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32; 7468 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7469 } 7470 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7471 dcb_info->tc_queue.tc_txq[0][1].base = 64; 7472 dcb_info->tc_queue.tc_txq[0][2].base = 96; 7473 dcb_info->tc_queue.tc_txq[0][3].base = 112; 7474 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64; 7475 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7476 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7477 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7478 } else if (dcb_info->nb_tcs == ETH_8_TCS) { 7479 for (i = 0; i < dcb_info->nb_tcs; i++) { 7480 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16; 7481 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7482 } 7483 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7484 dcb_info->tc_queue.tc_txq[0][1].base = 32; 7485 dcb_info->tc_queue.tc_txq[0][2].base = 64; 7486 dcb_info->tc_queue.tc_txq[0][3].base = 80; 7487 dcb_info->tc_queue.tc_txq[0][4].base = 96; 7488 dcb_info->tc_queue.tc_txq[0][5].base = 104; 7489 dcb_info->tc_queue.tc_txq[0][6].base = 112; 7490 dcb_info->tc_queue.tc_txq[0][7].base = 120; 7491 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32; 7492 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7493 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7494 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7495 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8; 7496 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8; 7497 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8; 7498 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8; 7499 } 7500 } 7501 for (i = 0; i < dcb_info->nb_tcs; i++) { 7502 tc = &dcb_config->tc_config[i]; 7503 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent; 7504 } 7505 return 0; 7506 } 7507 7508 /* Update e-tag ether type */ 7509 static int 7510 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw, 7511 uint16_t ether_type) 7512 { 7513 uint32_t etag_etype; 7514 7515 if (hw->mac.type != ixgbe_mac_X550 && 7516 hw->mac.type != ixgbe_mac_X550EM_x && 7517 hw->mac.type != ixgbe_mac_X550EM_a) { 7518 return -ENOTSUP; 7519 } 7520 7521 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7522 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK; 7523 etag_etype |= ether_type; 7524 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7525 IXGBE_WRITE_FLUSH(hw); 7526 7527 return 0; 7528 } 7529 7530 /* Config l2 tunnel ether type */ 7531 static int 7532 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev, 7533 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7534 { 7535 int ret = 0; 7536 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7537 struct ixgbe_l2_tn_info *l2_tn_info = 7538 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7539 7540 if (l2_tunnel == NULL) 7541 return -EINVAL; 7542 7543 switch (l2_tunnel->l2_tunnel_type) { 7544 case RTE_L2_TUNNEL_TYPE_E_TAG: 7545 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type; 7546 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type); 7547 break; 7548 default: 7549 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7550 ret = -EINVAL; 7551 break; 7552 } 7553 7554 return ret; 7555 } 7556 7557 /* Enable e-tag tunnel */ 7558 static int 7559 ixgbe_e_tag_enable(struct ixgbe_hw *hw) 7560 { 7561 uint32_t etag_etype; 7562 7563 if (hw->mac.type != ixgbe_mac_X550 && 7564 hw->mac.type != ixgbe_mac_X550EM_x && 7565 hw->mac.type != ixgbe_mac_X550EM_a) { 7566 return -ENOTSUP; 7567 } 7568 7569 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7570 etag_etype |= IXGBE_ETAG_ETYPE_VALID; 7571 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7572 IXGBE_WRITE_FLUSH(hw); 7573 7574 return 0; 7575 } 7576 7577 /* Enable l2 tunnel */ 7578 static int 7579 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev, 7580 enum rte_eth_tunnel_type l2_tunnel_type) 7581 { 7582 int ret = 0; 7583 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7584 struct ixgbe_l2_tn_info *l2_tn_info = 7585 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7586 7587 switch (l2_tunnel_type) { 7588 case RTE_L2_TUNNEL_TYPE_E_TAG: 7589 l2_tn_info->e_tag_en = TRUE; 7590 ret = ixgbe_e_tag_enable(hw); 7591 break; 7592 default: 7593 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7594 ret = -EINVAL; 7595 break; 7596 } 7597 7598 return ret; 7599 } 7600 7601 /* Disable e-tag tunnel */ 7602 static int 7603 ixgbe_e_tag_disable(struct ixgbe_hw *hw) 7604 { 7605 uint32_t etag_etype; 7606 7607 if (hw->mac.type != ixgbe_mac_X550 && 7608 hw->mac.type != ixgbe_mac_X550EM_x && 7609 hw->mac.type != ixgbe_mac_X550EM_a) { 7610 return -ENOTSUP; 7611 } 7612 7613 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7614 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID; 7615 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7616 IXGBE_WRITE_FLUSH(hw); 7617 7618 return 0; 7619 } 7620 7621 /* Disable l2 tunnel */ 7622 static int 7623 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev, 7624 enum rte_eth_tunnel_type l2_tunnel_type) 7625 { 7626 int ret = 0; 7627 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7628 struct ixgbe_l2_tn_info *l2_tn_info = 7629 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7630 7631 switch (l2_tunnel_type) { 7632 case RTE_L2_TUNNEL_TYPE_E_TAG: 7633 l2_tn_info->e_tag_en = FALSE; 7634 ret = ixgbe_e_tag_disable(hw); 7635 break; 7636 default: 7637 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7638 ret = -EINVAL; 7639 break; 7640 } 7641 7642 return ret; 7643 } 7644 7645 static int 7646 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev, 7647 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7648 { 7649 int ret = 0; 7650 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7651 uint32_t i, rar_entries; 7652 uint32_t rar_low, rar_high; 7653 7654 if (hw->mac.type != ixgbe_mac_X550 && 7655 hw->mac.type != ixgbe_mac_X550EM_x && 7656 hw->mac.type != ixgbe_mac_X550EM_a) { 7657 return -ENOTSUP; 7658 } 7659 7660 rar_entries = ixgbe_get_num_rx_addrs(hw); 7661 7662 for (i = 1; i < rar_entries; i++) { 7663 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7664 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 7665 if ((rar_high & IXGBE_RAH_AV) && 7666 (rar_high & IXGBE_RAH_ADTYPE) && 7667 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) == 7668 l2_tunnel->tunnel_id)) { 7669 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 7670 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 7671 7672 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL); 7673 7674 return ret; 7675 } 7676 } 7677 7678 return ret; 7679 } 7680 7681 static int 7682 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev, 7683 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7684 { 7685 int ret = 0; 7686 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7687 uint32_t i, rar_entries; 7688 uint32_t rar_low, rar_high; 7689 7690 if (hw->mac.type != ixgbe_mac_X550 && 7691 hw->mac.type != ixgbe_mac_X550EM_x && 7692 hw->mac.type != ixgbe_mac_X550EM_a) { 7693 return -ENOTSUP; 7694 } 7695 7696 /* One entry for one tunnel. Try to remove potential existing entry. */ 7697 ixgbe_e_tag_filter_del(dev, l2_tunnel); 7698 7699 rar_entries = ixgbe_get_num_rx_addrs(hw); 7700 7701 for (i = 1; i < rar_entries; i++) { 7702 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7703 if (rar_high & IXGBE_RAH_AV) { 7704 continue; 7705 } else { 7706 ixgbe_set_vmdq(hw, i, l2_tunnel->pool); 7707 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE; 7708 rar_low = l2_tunnel->tunnel_id; 7709 7710 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low); 7711 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high); 7712 7713 return ret; 7714 } 7715 } 7716 7717 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full." 7718 " Please remove a rule before adding a new one."); 7719 return -EINVAL; 7720 } 7721 7722 static inline struct ixgbe_l2_tn_filter * 7723 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info, 7724 struct ixgbe_l2_tn_key *key) 7725 { 7726 int ret; 7727 7728 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key); 7729 if (ret < 0) 7730 return NULL; 7731 7732 return l2_tn_info->hash_map[ret]; 7733 } 7734 7735 static inline int 7736 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7737 struct ixgbe_l2_tn_filter *l2_tn_filter) 7738 { 7739 int ret; 7740 7741 ret = rte_hash_add_key(l2_tn_info->hash_handle, 7742 &l2_tn_filter->key); 7743 7744 if (ret < 0) { 7745 PMD_DRV_LOG(ERR, 7746 "Failed to insert L2 tunnel filter" 7747 " to hash table %d!", 7748 ret); 7749 return ret; 7750 } 7751 7752 l2_tn_info->hash_map[ret] = l2_tn_filter; 7753 7754 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 7755 7756 return 0; 7757 } 7758 7759 static inline int 7760 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7761 struct ixgbe_l2_tn_key *key) 7762 { 7763 int ret; 7764 struct ixgbe_l2_tn_filter *l2_tn_filter; 7765 7766 ret = rte_hash_del_key(l2_tn_info->hash_handle, key); 7767 7768 if (ret < 0) { 7769 PMD_DRV_LOG(ERR, 7770 "No such L2 tunnel filter to delete %d!", 7771 ret); 7772 return ret; 7773 } 7774 7775 l2_tn_filter = l2_tn_info->hash_map[ret]; 7776 l2_tn_info->hash_map[ret] = NULL; 7777 7778 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 7779 rte_free(l2_tn_filter); 7780 7781 return 0; 7782 } 7783 7784 /* Add l2 tunnel filter */ 7785 int 7786 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 7787 struct rte_eth_l2_tunnel_conf *l2_tunnel, 7788 bool restore) 7789 { 7790 int ret; 7791 struct ixgbe_l2_tn_info *l2_tn_info = 7792 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7793 struct ixgbe_l2_tn_key key; 7794 struct ixgbe_l2_tn_filter *node; 7795 7796 if (!restore) { 7797 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 7798 key.tn_id = l2_tunnel->tunnel_id; 7799 7800 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key); 7801 7802 if (node) { 7803 PMD_DRV_LOG(ERR, 7804 "The L2 tunnel filter already exists!"); 7805 return -EINVAL; 7806 } 7807 7808 node = rte_zmalloc("ixgbe_l2_tn", 7809 sizeof(struct ixgbe_l2_tn_filter), 7810 0); 7811 if (!node) 7812 return -ENOMEM; 7813 7814 rte_memcpy(&node->key, 7815 &key, 7816 sizeof(struct ixgbe_l2_tn_key)); 7817 node->pool = l2_tunnel->pool; 7818 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node); 7819 if (ret < 0) { 7820 rte_free(node); 7821 return ret; 7822 } 7823 } 7824 7825 switch (l2_tunnel->l2_tunnel_type) { 7826 case RTE_L2_TUNNEL_TYPE_E_TAG: 7827 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel); 7828 break; 7829 default: 7830 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7831 ret = -EINVAL; 7832 break; 7833 } 7834 7835 if ((!restore) && (ret < 0)) 7836 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 7837 7838 return ret; 7839 } 7840 7841 /* Delete l2 tunnel filter */ 7842 int 7843 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 7844 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7845 { 7846 int ret; 7847 struct ixgbe_l2_tn_info *l2_tn_info = 7848 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7849 struct ixgbe_l2_tn_key key; 7850 7851 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 7852 key.tn_id = l2_tunnel->tunnel_id; 7853 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 7854 if (ret < 0) 7855 return ret; 7856 7857 switch (l2_tunnel->l2_tunnel_type) { 7858 case RTE_L2_TUNNEL_TYPE_E_TAG: 7859 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel); 7860 break; 7861 default: 7862 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7863 ret = -EINVAL; 7864 break; 7865 } 7866 7867 return ret; 7868 } 7869 7870 /** 7871 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter. 7872 * @dev: pointer to rte_eth_dev structure 7873 * @filter_op:operation will be taken. 7874 * @arg: a pointer to specific structure corresponding to the filter_op 7875 */ 7876 static int 7877 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev, 7878 enum rte_filter_op filter_op, 7879 void *arg) 7880 { 7881 int ret; 7882 7883 if (filter_op == RTE_ETH_FILTER_NOP) 7884 return 0; 7885 7886 if (arg == NULL) { 7887 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 7888 filter_op); 7889 return -EINVAL; 7890 } 7891 7892 switch (filter_op) { 7893 case RTE_ETH_FILTER_ADD: 7894 ret = ixgbe_dev_l2_tunnel_filter_add 7895 (dev, 7896 (struct rte_eth_l2_tunnel_conf *)arg, 7897 FALSE); 7898 break; 7899 case RTE_ETH_FILTER_DELETE: 7900 ret = ixgbe_dev_l2_tunnel_filter_del 7901 (dev, 7902 (struct rte_eth_l2_tunnel_conf *)arg); 7903 break; 7904 default: 7905 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 7906 ret = -EINVAL; 7907 break; 7908 } 7909 return ret; 7910 } 7911 7912 static int 7913 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en) 7914 { 7915 int ret = 0; 7916 uint32_t ctrl; 7917 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7918 7919 if (hw->mac.type != ixgbe_mac_X550 && 7920 hw->mac.type != ixgbe_mac_X550EM_x && 7921 hw->mac.type != ixgbe_mac_X550EM_a) { 7922 return -ENOTSUP; 7923 } 7924 7925 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 7926 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 7927 if (en) 7928 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG; 7929 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 7930 7931 return ret; 7932 } 7933 7934 /* Enable l2 tunnel forwarding */ 7935 static int 7936 ixgbe_dev_l2_tunnel_forwarding_enable 7937 (struct rte_eth_dev *dev, 7938 enum rte_eth_tunnel_type l2_tunnel_type) 7939 { 7940 struct ixgbe_l2_tn_info *l2_tn_info = 7941 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7942 int ret = 0; 7943 7944 switch (l2_tunnel_type) { 7945 case RTE_L2_TUNNEL_TYPE_E_TAG: 7946 l2_tn_info->e_tag_fwd_en = TRUE; 7947 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1); 7948 break; 7949 default: 7950 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7951 ret = -EINVAL; 7952 break; 7953 } 7954 7955 return ret; 7956 } 7957 7958 /* Disable l2 tunnel forwarding */ 7959 static int 7960 ixgbe_dev_l2_tunnel_forwarding_disable 7961 (struct rte_eth_dev *dev, 7962 enum rte_eth_tunnel_type l2_tunnel_type) 7963 { 7964 struct ixgbe_l2_tn_info *l2_tn_info = 7965 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7966 int ret = 0; 7967 7968 switch (l2_tunnel_type) { 7969 case RTE_L2_TUNNEL_TYPE_E_TAG: 7970 l2_tn_info->e_tag_fwd_en = FALSE; 7971 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0); 7972 break; 7973 default: 7974 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7975 ret = -EINVAL; 7976 break; 7977 } 7978 7979 return ret; 7980 } 7981 7982 static int 7983 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev, 7984 struct rte_eth_l2_tunnel_conf *l2_tunnel, 7985 bool en) 7986 { 7987 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 7988 int ret = 0; 7989 uint32_t vmtir, vmvir; 7990 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7991 7992 if (l2_tunnel->vf_id >= pci_dev->max_vfs) { 7993 PMD_DRV_LOG(ERR, 7994 "VF id %u should be less than %u", 7995 l2_tunnel->vf_id, 7996 pci_dev->max_vfs); 7997 return -EINVAL; 7998 } 7999 8000 if (hw->mac.type != ixgbe_mac_X550 && 8001 hw->mac.type != ixgbe_mac_X550EM_x && 8002 hw->mac.type != ixgbe_mac_X550EM_a) { 8003 return -ENOTSUP; 8004 } 8005 8006 if (en) 8007 vmtir = l2_tunnel->tunnel_id; 8008 else 8009 vmtir = 0; 8010 8011 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir); 8012 8013 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id)); 8014 vmvir &= ~IXGBE_VMVIR_TAGA_MASK; 8015 if (en) 8016 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT; 8017 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir); 8018 8019 return ret; 8020 } 8021 8022 /* Enable l2 tunnel tag insertion */ 8023 static int 8024 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev, 8025 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8026 { 8027 int ret = 0; 8028 8029 switch (l2_tunnel->l2_tunnel_type) { 8030 case RTE_L2_TUNNEL_TYPE_E_TAG: 8031 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1); 8032 break; 8033 default: 8034 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8035 ret = -EINVAL; 8036 break; 8037 } 8038 8039 return ret; 8040 } 8041 8042 /* Disable l2 tunnel tag insertion */ 8043 static int 8044 ixgbe_dev_l2_tunnel_insertion_disable 8045 (struct rte_eth_dev *dev, 8046 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8047 { 8048 int ret = 0; 8049 8050 switch (l2_tunnel->l2_tunnel_type) { 8051 case RTE_L2_TUNNEL_TYPE_E_TAG: 8052 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0); 8053 break; 8054 default: 8055 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8056 ret = -EINVAL; 8057 break; 8058 } 8059 8060 return ret; 8061 } 8062 8063 static int 8064 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev, 8065 bool en) 8066 { 8067 int ret = 0; 8068 uint32_t qde; 8069 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8070 8071 if (hw->mac.type != ixgbe_mac_X550 && 8072 hw->mac.type != ixgbe_mac_X550EM_x && 8073 hw->mac.type != ixgbe_mac_X550EM_a) { 8074 return -ENOTSUP; 8075 } 8076 8077 qde = IXGBE_READ_REG(hw, IXGBE_QDE); 8078 if (en) 8079 qde |= IXGBE_QDE_STRIP_TAG; 8080 else 8081 qde &= ~IXGBE_QDE_STRIP_TAG; 8082 qde &= ~IXGBE_QDE_READ; 8083 qde |= IXGBE_QDE_WRITE; 8084 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde); 8085 8086 return ret; 8087 } 8088 8089 /* Enable l2 tunnel tag stripping */ 8090 static int 8091 ixgbe_dev_l2_tunnel_stripping_enable 8092 (struct rte_eth_dev *dev, 8093 enum rte_eth_tunnel_type l2_tunnel_type) 8094 { 8095 int ret = 0; 8096 8097 switch (l2_tunnel_type) { 8098 case RTE_L2_TUNNEL_TYPE_E_TAG: 8099 ret = ixgbe_e_tag_stripping_en_dis(dev, 1); 8100 break; 8101 default: 8102 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8103 ret = -EINVAL; 8104 break; 8105 } 8106 8107 return ret; 8108 } 8109 8110 /* Disable l2 tunnel tag stripping */ 8111 static int 8112 ixgbe_dev_l2_tunnel_stripping_disable 8113 (struct rte_eth_dev *dev, 8114 enum rte_eth_tunnel_type l2_tunnel_type) 8115 { 8116 int ret = 0; 8117 8118 switch (l2_tunnel_type) { 8119 case RTE_L2_TUNNEL_TYPE_E_TAG: 8120 ret = ixgbe_e_tag_stripping_en_dis(dev, 0); 8121 break; 8122 default: 8123 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8124 ret = -EINVAL; 8125 break; 8126 } 8127 8128 return ret; 8129 } 8130 8131 /* Enable/disable l2 tunnel offload functions */ 8132 static int 8133 ixgbe_dev_l2_tunnel_offload_set 8134 (struct rte_eth_dev *dev, 8135 struct rte_eth_l2_tunnel_conf *l2_tunnel, 8136 uint32_t mask, 8137 uint8_t en) 8138 { 8139 int ret = 0; 8140 8141 if (l2_tunnel == NULL) 8142 return -EINVAL; 8143 8144 ret = -EINVAL; 8145 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) { 8146 if (en) 8147 ret = ixgbe_dev_l2_tunnel_enable( 8148 dev, 8149 l2_tunnel->l2_tunnel_type); 8150 else 8151 ret = ixgbe_dev_l2_tunnel_disable( 8152 dev, 8153 l2_tunnel->l2_tunnel_type); 8154 } 8155 8156 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) { 8157 if (en) 8158 ret = ixgbe_dev_l2_tunnel_insertion_enable( 8159 dev, 8160 l2_tunnel); 8161 else 8162 ret = ixgbe_dev_l2_tunnel_insertion_disable( 8163 dev, 8164 l2_tunnel); 8165 } 8166 8167 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) { 8168 if (en) 8169 ret = ixgbe_dev_l2_tunnel_stripping_enable( 8170 dev, 8171 l2_tunnel->l2_tunnel_type); 8172 else 8173 ret = ixgbe_dev_l2_tunnel_stripping_disable( 8174 dev, 8175 l2_tunnel->l2_tunnel_type); 8176 } 8177 8178 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) { 8179 if (en) 8180 ret = ixgbe_dev_l2_tunnel_forwarding_enable( 8181 dev, 8182 l2_tunnel->l2_tunnel_type); 8183 else 8184 ret = ixgbe_dev_l2_tunnel_forwarding_disable( 8185 dev, 8186 l2_tunnel->l2_tunnel_type); 8187 } 8188 8189 return ret; 8190 } 8191 8192 static int 8193 ixgbe_update_vxlan_port(struct ixgbe_hw *hw, 8194 uint16_t port) 8195 { 8196 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port); 8197 IXGBE_WRITE_FLUSH(hw); 8198 8199 return 0; 8200 } 8201 8202 /* There's only one register for VxLAN UDP port. 8203 * So, we cannot add several ports. Will update it. 8204 */ 8205 static int 8206 ixgbe_add_vxlan_port(struct ixgbe_hw *hw, 8207 uint16_t port) 8208 { 8209 if (port == 0) { 8210 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 8211 return -EINVAL; 8212 } 8213 8214 return ixgbe_update_vxlan_port(hw, port); 8215 } 8216 8217 /* We cannot delete the VxLAN port. For there's a register for VxLAN 8218 * UDP port, it must have a value. 8219 * So, will reset it to the original value 0. 8220 */ 8221 static int 8222 ixgbe_del_vxlan_port(struct ixgbe_hw *hw, 8223 uint16_t port) 8224 { 8225 uint16_t cur_port; 8226 8227 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL); 8228 8229 if (cur_port != port) { 8230 PMD_DRV_LOG(ERR, "Port %u does not exist.", port); 8231 return -EINVAL; 8232 } 8233 8234 return ixgbe_update_vxlan_port(hw, 0); 8235 } 8236 8237 /* Add UDP tunneling port */ 8238 static int 8239 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 8240 struct rte_eth_udp_tunnel *udp_tunnel) 8241 { 8242 int ret = 0; 8243 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8244 8245 if (hw->mac.type != ixgbe_mac_X550 && 8246 hw->mac.type != ixgbe_mac_X550EM_x && 8247 hw->mac.type != ixgbe_mac_X550EM_a) { 8248 return -ENOTSUP; 8249 } 8250 8251 if (udp_tunnel == NULL) 8252 return -EINVAL; 8253 8254 switch (udp_tunnel->prot_type) { 8255 case RTE_TUNNEL_TYPE_VXLAN: 8256 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port); 8257 break; 8258 8259 case RTE_TUNNEL_TYPE_GENEVE: 8260 case RTE_TUNNEL_TYPE_TEREDO: 8261 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8262 ret = -EINVAL; 8263 break; 8264 8265 default: 8266 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8267 ret = -EINVAL; 8268 break; 8269 } 8270 8271 return ret; 8272 } 8273 8274 /* Remove UDP tunneling port */ 8275 static int 8276 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 8277 struct rte_eth_udp_tunnel *udp_tunnel) 8278 { 8279 int ret = 0; 8280 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8281 8282 if (hw->mac.type != ixgbe_mac_X550 && 8283 hw->mac.type != ixgbe_mac_X550EM_x && 8284 hw->mac.type != ixgbe_mac_X550EM_a) { 8285 return -ENOTSUP; 8286 } 8287 8288 if (udp_tunnel == NULL) 8289 return -EINVAL; 8290 8291 switch (udp_tunnel->prot_type) { 8292 case RTE_TUNNEL_TYPE_VXLAN: 8293 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port); 8294 break; 8295 case RTE_TUNNEL_TYPE_GENEVE: 8296 case RTE_TUNNEL_TYPE_TEREDO: 8297 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8298 ret = -EINVAL; 8299 break; 8300 default: 8301 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8302 ret = -EINVAL; 8303 break; 8304 } 8305 8306 return ret; 8307 } 8308 8309 static void 8310 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev) 8311 { 8312 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8313 8314 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI); 8315 } 8316 8317 static void 8318 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev) 8319 { 8320 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8321 8322 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI); 8323 } 8324 8325 static void ixgbevf_mbx_process(struct rte_eth_dev *dev) 8326 { 8327 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8328 u32 in_msg = 0; 8329 8330 /* peek the message first */ 8331 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM); 8332 8333 /* PF reset VF event */ 8334 if (in_msg == IXGBE_PF_CONTROL_MSG) { 8335 /* dummy mbx read to ack pf */ 8336 if (ixgbe_read_mbx(hw, &in_msg, 1, 0)) 8337 return; 8338 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 8339 NULL); 8340 } 8341 } 8342 8343 static int 8344 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev) 8345 { 8346 uint32_t eicr; 8347 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8348 struct ixgbe_interrupt *intr = 8349 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8350 ixgbevf_intr_disable(dev); 8351 8352 /* read-on-clear nic registers here */ 8353 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR); 8354 intr->flags = 0; 8355 8356 /* only one misc vector supported - mailbox */ 8357 eicr &= IXGBE_VTEICR_MASK; 8358 if (eicr == IXGBE_MISC_VEC_ID) 8359 intr->flags |= IXGBE_FLAG_MAILBOX; 8360 8361 return 0; 8362 } 8363 8364 static int 8365 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev) 8366 { 8367 struct ixgbe_interrupt *intr = 8368 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8369 8370 if (intr->flags & IXGBE_FLAG_MAILBOX) { 8371 ixgbevf_mbx_process(dev); 8372 intr->flags &= ~IXGBE_FLAG_MAILBOX; 8373 } 8374 8375 ixgbevf_intr_enable(dev); 8376 8377 return 0; 8378 } 8379 8380 static void 8381 ixgbevf_dev_interrupt_handler(void *param) 8382 { 8383 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 8384 8385 ixgbevf_dev_interrupt_get_status(dev); 8386 ixgbevf_dev_interrupt_action(dev); 8387 } 8388 8389 /** 8390 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path 8391 * @hw: pointer to hardware structure 8392 * 8393 * Stops the transmit data path and waits for the HW to internally empty 8394 * the Tx security block 8395 **/ 8396 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw) 8397 { 8398 #define IXGBE_MAX_SECTX_POLL 40 8399 8400 int i; 8401 int sectxreg; 8402 8403 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8404 sectxreg |= IXGBE_SECTXCTRL_TX_DIS; 8405 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8406 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) { 8407 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT); 8408 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY) 8409 break; 8410 /* Use interrupt-safe sleep just in case */ 8411 usec_delay(1000); 8412 } 8413 8414 /* For informational purposes only */ 8415 if (i >= IXGBE_MAX_SECTX_POLL) 8416 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security " 8417 "path fully disabled. Continuing with init."); 8418 8419 return IXGBE_SUCCESS; 8420 } 8421 8422 /** 8423 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path 8424 * @hw: pointer to hardware structure 8425 * 8426 * Enables the transmit data path. 8427 **/ 8428 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw) 8429 { 8430 uint32_t sectxreg; 8431 8432 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8433 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS; 8434 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8435 IXGBE_WRITE_FLUSH(hw); 8436 8437 return IXGBE_SUCCESS; 8438 } 8439 8440 /* restore n-tuple filter */ 8441 static inline void 8442 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev) 8443 { 8444 struct ixgbe_filter_info *filter_info = 8445 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8446 struct ixgbe_5tuple_filter *node; 8447 8448 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) { 8449 ixgbe_inject_5tuple_filter(dev, node); 8450 } 8451 } 8452 8453 /* restore ethernet type filter */ 8454 static inline void 8455 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev) 8456 { 8457 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8458 struct ixgbe_filter_info *filter_info = 8459 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8460 int i; 8461 8462 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8463 if (filter_info->ethertype_mask & (1 << i)) { 8464 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 8465 filter_info->ethertype_filters[i].etqf); 8466 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 8467 filter_info->ethertype_filters[i].etqs); 8468 IXGBE_WRITE_FLUSH(hw); 8469 } 8470 } 8471 } 8472 8473 /* restore SYN filter */ 8474 static inline void 8475 ixgbe_syn_filter_restore(struct rte_eth_dev *dev) 8476 { 8477 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8478 struct ixgbe_filter_info *filter_info = 8479 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8480 uint32_t synqf; 8481 8482 synqf = filter_info->syn_info; 8483 8484 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 8485 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 8486 IXGBE_WRITE_FLUSH(hw); 8487 } 8488 } 8489 8490 /* restore L2 tunnel filter */ 8491 static inline void 8492 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev) 8493 { 8494 struct ixgbe_l2_tn_info *l2_tn_info = 8495 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8496 struct ixgbe_l2_tn_filter *node; 8497 struct rte_eth_l2_tunnel_conf l2_tn_conf; 8498 8499 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) { 8500 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type; 8501 l2_tn_conf.tunnel_id = node->key.tn_id; 8502 l2_tn_conf.pool = node->pool; 8503 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE); 8504 } 8505 } 8506 8507 /* restore rss filter */ 8508 static inline void 8509 ixgbe_rss_filter_restore(struct rte_eth_dev *dev) 8510 { 8511 struct ixgbe_filter_info *filter_info = 8512 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8513 8514 if (filter_info->rss_info.conf.queue_num) 8515 ixgbe_config_rss_filter(dev, 8516 &filter_info->rss_info, TRUE); 8517 } 8518 8519 static int 8520 ixgbe_filter_restore(struct rte_eth_dev *dev) 8521 { 8522 ixgbe_ntuple_filter_restore(dev); 8523 ixgbe_ethertype_filter_restore(dev); 8524 ixgbe_syn_filter_restore(dev); 8525 ixgbe_fdir_filter_restore(dev); 8526 ixgbe_l2_tn_filter_restore(dev); 8527 ixgbe_rss_filter_restore(dev); 8528 8529 return 0; 8530 } 8531 8532 static void 8533 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev) 8534 { 8535 struct ixgbe_l2_tn_info *l2_tn_info = 8536 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8537 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8538 8539 if (l2_tn_info->e_tag_en) 8540 (void)ixgbe_e_tag_enable(hw); 8541 8542 if (l2_tn_info->e_tag_fwd_en) 8543 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1); 8544 8545 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type); 8546 } 8547 8548 /* remove all the n-tuple filters */ 8549 void 8550 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev) 8551 { 8552 struct ixgbe_filter_info *filter_info = 8553 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8554 struct ixgbe_5tuple_filter *p_5tuple; 8555 8556 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) 8557 ixgbe_remove_5tuple_filter(dev, p_5tuple); 8558 } 8559 8560 /* remove all the ether type filters */ 8561 void 8562 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev) 8563 { 8564 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8565 struct ixgbe_filter_info *filter_info = 8566 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8567 int i; 8568 8569 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8570 if (filter_info->ethertype_mask & (1 << i) && 8571 !filter_info->ethertype_filters[i].conf) { 8572 (void)ixgbe_ethertype_filter_remove(filter_info, 8573 (uint8_t)i); 8574 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0); 8575 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0); 8576 IXGBE_WRITE_FLUSH(hw); 8577 } 8578 } 8579 } 8580 8581 /* remove the SYN filter */ 8582 void 8583 ixgbe_clear_syn_filter(struct rte_eth_dev *dev) 8584 { 8585 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8586 struct ixgbe_filter_info *filter_info = 8587 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8588 8589 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) { 8590 filter_info->syn_info = 0; 8591 8592 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0); 8593 IXGBE_WRITE_FLUSH(hw); 8594 } 8595 } 8596 8597 /* remove all the L2 tunnel filters */ 8598 int 8599 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev) 8600 { 8601 struct ixgbe_l2_tn_info *l2_tn_info = 8602 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8603 struct ixgbe_l2_tn_filter *l2_tn_filter; 8604 struct rte_eth_l2_tunnel_conf l2_tn_conf; 8605 int ret = 0; 8606 8607 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 8608 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type; 8609 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id; 8610 l2_tn_conf.pool = l2_tn_filter->pool; 8611 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf); 8612 if (ret < 0) 8613 return ret; 8614 } 8615 8616 return 0; 8617 } 8618 8619 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd); 8620 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map); 8621 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 8622 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd); 8623 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map); 8624 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci"); 8625 8626 RTE_INIT(ixgbe_init_log) 8627 { 8628 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init"); 8629 if (ixgbe_logtype_init >= 0) 8630 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE); 8631 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver"); 8632 if (ixgbe_logtype_driver >= 0) 8633 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE); 8634 } 8635