1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <inttypes.h> 13 #include <netinet/in.h> 14 #include <rte_byteorder.h> 15 #include <rte_common.h> 16 #include <rte_cycles.h> 17 18 #include <rte_interrupts.h> 19 #include <rte_log.h> 20 #include <rte_debug.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_branch_prediction.h> 24 #include <rte_memory.h> 25 #include <rte_eal.h> 26 #include <rte_alarm.h> 27 #include <rte_ether.h> 28 #include <rte_ethdev_driver.h> 29 #include <rte_ethdev_pci.h> 30 #include <rte_malloc.h> 31 #include <rte_random.h> 32 #include <rte_dev.h> 33 #include <rte_hash_crc.h> 34 #ifdef RTE_LIBRTE_SECURITY 35 #include <rte_security_driver.h> 36 #endif 37 38 #include "ixgbe_logs.h" 39 #include "base/ixgbe_api.h" 40 #include "base/ixgbe_vf.h" 41 #include "base/ixgbe_common.h" 42 #include "ixgbe_ethdev.h" 43 #include "ixgbe_bypass.h" 44 #include "ixgbe_rxtx.h" 45 #include "base/ixgbe_type.h" 46 #include "base/ixgbe_phy.h" 47 #include "ixgbe_regs.h" 48 49 /* 50 * High threshold controlling when to start sending XOFF frames. Must be at 51 * least 8 bytes less than receive packet buffer size. This value is in units 52 * of 1024 bytes. 53 */ 54 #define IXGBE_FC_HI 0x80 55 56 /* 57 * Low threshold controlling when to start sending XON frames. This value is 58 * in units of 1024 bytes. 59 */ 60 #define IXGBE_FC_LO 0x40 61 62 /* Timer value included in XOFF frames. */ 63 #define IXGBE_FC_PAUSE 0x680 64 65 /*Default value of Max Rx Queue*/ 66 #define IXGBE_MAX_RX_QUEUE_NUM 128 67 68 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */ 69 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */ 70 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */ 71 72 #define IXGBE_MMW_SIZE_DEFAULT 0x4 73 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14 74 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */ 75 76 /* 77 * Default values for RX/TX configuration 78 */ 79 #define IXGBE_DEFAULT_RX_FREE_THRESH 32 80 #define IXGBE_DEFAULT_RX_PTHRESH 8 81 #define IXGBE_DEFAULT_RX_HTHRESH 8 82 #define IXGBE_DEFAULT_RX_WTHRESH 0 83 84 #define IXGBE_DEFAULT_TX_FREE_THRESH 32 85 #define IXGBE_DEFAULT_TX_PTHRESH 32 86 #define IXGBE_DEFAULT_TX_HTHRESH 0 87 #define IXGBE_DEFAULT_TX_WTHRESH 0 88 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32 89 90 /* Bit shift and mask */ 91 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2) 92 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t) 93 #define IXGBE_8_BIT_WIDTH CHAR_BIT 94 #define IXGBE_8_BIT_MASK UINT8_MAX 95 96 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */ 97 98 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0])) 99 100 /* Additional timesync values. */ 101 #define NSEC_PER_SEC 1000000000L 102 #define IXGBE_INCVAL_10GB 0x66666666 103 #define IXGBE_INCVAL_1GB 0x40000000 104 #define IXGBE_INCVAL_100 0x50000000 105 #define IXGBE_INCVAL_SHIFT_10GB 28 106 #define IXGBE_INCVAL_SHIFT_1GB 24 107 #define IXGBE_INCVAL_SHIFT_100 21 108 #define IXGBE_INCVAL_SHIFT_82599 7 109 #define IXGBE_INCPER_SHIFT_82599 24 110 111 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL 112 113 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000 114 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000 115 #define IXGBE_ETAG_ETYPE 0x00005084 116 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff 117 #define IXGBE_ETAG_ETYPE_VALID 0x80000000 118 #define IXGBE_RAH_ADTYPE 0x40000000 119 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff 120 #define IXGBE_VMVIR_TAGA_MASK 0x18000000 121 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000 122 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */ 123 #define IXGBE_QDE_STRIP_TAG 0x00000004 124 #define IXGBE_VTEICR_MASK 0x07 125 126 #define IXGBE_EXVET_VET_EXT_SHIFT 16 127 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000 128 129 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 130 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev); 131 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev); 132 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev); 133 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev); 134 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev); 135 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev); 136 static int ixgbe_dev_configure(struct rte_eth_dev *dev); 137 static int ixgbe_dev_start(struct rte_eth_dev *dev); 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev); 139 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev); 140 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev); 141 static void ixgbe_dev_close(struct rte_eth_dev *dev); 142 static int ixgbe_dev_reset(struct rte_eth_dev *dev); 143 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 144 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 145 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 146 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 147 static int ixgbe_dev_link_update(struct rte_eth_dev *dev, 148 int wait_to_complete); 149 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev, 150 struct rte_eth_stats *stats); 151 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev, 152 struct rte_eth_xstat *xstats, unsigned n); 153 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, 154 struct rte_eth_xstat *xstats, unsigned n); 155 static int 156 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 157 uint64_t *values, unsigned int n); 158 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev); 159 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev); 160 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 161 struct rte_eth_xstat_name *xstats_names, 162 unsigned int size); 163 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev, 164 struct rte_eth_xstat_name *xstats_names, unsigned limit); 165 static int ixgbe_dev_xstats_get_names_by_id( 166 struct rte_eth_dev *dev, 167 struct rte_eth_xstat_name *xstats_names, 168 const uint64_t *ids, 169 unsigned int limit); 170 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 171 uint16_t queue_id, 172 uint8_t stat_idx, 173 uint8_t is_rx); 174 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 175 size_t fw_size); 176 static void ixgbe_dev_info_get(struct rte_eth_dev *dev, 177 struct rte_eth_dev_info *dev_info); 178 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); 179 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev, 180 struct rte_eth_dev_info *dev_info); 181 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 182 183 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev, 184 uint16_t vlan_id, int on); 185 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 186 enum rte_vlan_type vlan_type, 187 uint16_t tpid_id); 188 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, 189 uint16_t queue, bool on); 190 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, 191 int on); 192 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, 193 int mask); 194 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask); 195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask); 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue); 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue); 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev); 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev); 200 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev); 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev); 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, 204 struct rte_eth_fc_conf *fc_conf); 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, 206 struct rte_eth_fc_conf *fc_conf); 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 208 struct rte_eth_pfc_conf *pfc_conf); 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 210 struct rte_eth_rss_reta_entry64 *reta_conf, 211 uint16_t reta_size); 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 213 struct rte_eth_rss_reta_entry64 *reta_conf, 214 uint16_t reta_size); 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev); 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); 217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev); 218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); 219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev); 220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev, 221 struct rte_intr_handle *handle); 222 static void ixgbe_dev_interrupt_handler(void *param); 223 static void ixgbe_dev_interrupt_delayed_handler(void *param); 224 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr, 225 uint32_t index, uint32_t pool); 226 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index); 227 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, 228 struct ether_addr *mac_addr); 229 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config); 230 static bool is_device_supported(struct rte_eth_dev *dev, 231 struct rte_pci_driver *drv); 232 233 /* For Virtual Function support */ 234 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev); 235 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev); 236 static int ixgbevf_dev_configure(struct rte_eth_dev *dev); 237 static int ixgbevf_dev_start(struct rte_eth_dev *dev); 238 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev, 239 int wait_to_complete); 240 static void ixgbevf_dev_stop(struct rte_eth_dev *dev); 241 static void ixgbevf_dev_close(struct rte_eth_dev *dev); 242 static int ixgbevf_dev_reset(struct rte_eth_dev *dev); 243 static void ixgbevf_intr_disable(struct rte_eth_dev *dev); 244 static void ixgbevf_intr_enable(struct rte_eth_dev *dev); 245 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev, 246 struct rte_eth_stats *stats); 247 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev); 248 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, 249 uint16_t vlan_id, int on); 250 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, 251 uint16_t queue, int on); 252 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask); 253 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask); 254 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on); 255 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 256 uint16_t queue_id); 257 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 258 uint16_t queue_id); 259 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 260 uint8_t queue, uint8_t msix_vector); 261 static void ixgbevf_configure_msix(struct rte_eth_dev *dev); 262 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev); 263 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev); 264 265 /* For Eth VMDQ APIs support */ 266 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct 267 ether_addr * mac_addr, uint8_t on); 268 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on); 269 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 270 struct rte_eth_mirror_conf *mirror_conf, 271 uint8_t rule_id, uint8_t on); 272 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, 273 uint8_t rule_id); 274 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 275 uint16_t queue_id); 276 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 277 uint16_t queue_id); 278 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 279 uint8_t queue, uint8_t msix_vector); 280 static void ixgbe_configure_msix(struct rte_eth_dev *dev); 281 282 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev, 283 struct ether_addr *mac_addr, 284 uint32_t index, uint32_t pool); 285 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index); 286 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 287 struct ether_addr *mac_addr); 288 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev, 289 struct rte_eth_syn_filter *filter); 290 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev, 291 enum rte_filter_op filter_op, 292 void *arg); 293 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 294 struct ixgbe_5tuple_filter *filter); 295 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 296 struct ixgbe_5tuple_filter *filter); 297 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev, 298 enum rte_filter_op filter_op, 299 void *arg); 300 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev, 301 struct rte_eth_ntuple_filter *filter); 302 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev, 303 enum rte_filter_op filter_op, 304 void *arg); 305 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, 306 struct rte_eth_ethertype_filter *filter); 307 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 308 enum rte_filter_type filter_type, 309 enum rte_filter_op filter_op, 310 void *arg); 311 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 312 313 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 314 struct ether_addr *mc_addr_set, 315 uint32_t nb_mc_addr); 316 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 317 struct rte_eth_dcb_info *dcb_info); 318 319 static int ixgbe_get_reg_length(struct rte_eth_dev *dev); 320 static int ixgbe_get_regs(struct rte_eth_dev *dev, 321 struct rte_dev_reg_info *regs); 322 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev); 323 static int ixgbe_get_eeprom(struct rte_eth_dev *dev, 324 struct rte_dev_eeprom_info *eeprom); 325 static int ixgbe_set_eeprom(struct rte_eth_dev *dev, 326 struct rte_dev_eeprom_info *eeprom); 327 328 static int ixgbe_get_module_info(struct rte_eth_dev *dev, 329 struct rte_eth_dev_module_info *modinfo); 330 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 331 struct rte_dev_eeprom_info *info); 332 333 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev); 334 static int ixgbevf_get_regs(struct rte_eth_dev *dev, 335 struct rte_dev_reg_info *regs); 336 337 static int ixgbe_timesync_enable(struct rte_eth_dev *dev); 338 static int ixgbe_timesync_disable(struct rte_eth_dev *dev); 339 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 340 struct timespec *timestamp, 341 uint32_t flags); 342 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 343 struct timespec *timestamp); 344 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 345 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev, 346 struct timespec *timestamp); 347 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev, 348 const struct timespec *timestamp); 349 static void ixgbevf_dev_interrupt_handler(void *param); 350 351 static int ixgbe_dev_l2_tunnel_eth_type_conf 352 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel); 353 static int ixgbe_dev_l2_tunnel_offload_set 354 (struct rte_eth_dev *dev, 355 struct rte_eth_l2_tunnel_conf *l2_tunnel, 356 uint32_t mask, 357 uint8_t en); 358 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev, 359 enum rte_filter_op filter_op, 360 void *arg); 361 362 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 363 struct rte_eth_udp_tunnel *udp_tunnel); 364 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 365 struct rte_eth_udp_tunnel *udp_tunnel); 366 static int ixgbe_filter_restore(struct rte_eth_dev *dev); 367 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev); 368 369 /* 370 * Define VF Stats MACRO for Non "cleared on read" register 371 */ 372 #define UPDATE_VF_STAT(reg, last, cur) \ 373 { \ 374 uint32_t latest = IXGBE_READ_REG(hw, reg); \ 375 cur += (latest - last) & UINT_MAX; \ 376 last = latest; \ 377 } 378 379 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \ 380 { \ 381 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \ 382 u64 new_msb = IXGBE_READ_REG(hw, msb); \ 383 u64 latest = ((new_msb << 32) | new_lsb); \ 384 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \ 385 last = latest; \ 386 } 387 388 #define IXGBE_SET_HWSTRIP(h, q) do {\ 389 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 390 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 391 (h)->bitmap[idx] |= 1 << bit;\ 392 } while (0) 393 394 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\ 395 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 396 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 397 (h)->bitmap[idx] &= ~(1 << bit);\ 398 } while (0) 399 400 #define IXGBE_GET_HWSTRIP(h, q, r) do {\ 401 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 402 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 403 (r) = (h)->bitmap[idx] >> bit & 1;\ 404 } while (0) 405 406 int ixgbe_logtype_init; 407 int ixgbe_logtype_driver; 408 409 /* 410 * The set of PCI devices this driver supports 411 */ 412 static const struct rte_pci_id pci_id_ixgbe_map[] = { 413 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) }, 414 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) }, 415 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) }, 416 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) }, 417 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) }, 418 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) }, 419 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) }, 420 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) }, 421 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) }, 422 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) }, 423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) }, 424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) }, 425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) }, 426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) }, 427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) }, 428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) }, 429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) }, 430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) }, 431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) }, 432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) }, 433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) }, 434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) }, 435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) }, 436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) }, 437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) }, 438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) }, 439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) }, 440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) }, 441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) }, 442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) }, 443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) }, 444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) }, 445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) }, 446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) }, 447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) }, 448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) }, 449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) }, 450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) }, 451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) }, 452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) }, 453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) }, 454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) }, 455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) }, 456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) }, 457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) }, 458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) }, 459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) }, 460 #ifdef RTE_LIBRTE_IXGBE_BYPASS 461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) }, 462 #endif 463 { .vendor_id = 0, /* sentinel */ }, 464 }; 465 466 /* 467 * The set of PCI devices this driver supports (for 82599 VF) 468 */ 469 static const struct rte_pci_id pci_id_ixgbevf_map[] = { 470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) }, 471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) }, 472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) }, 473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) }, 474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) }, 475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) }, 476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) }, 477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) }, 478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) }, 479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) }, 480 { .vendor_id = 0, /* sentinel */ }, 481 }; 482 483 static const struct rte_eth_desc_lim rx_desc_lim = { 484 .nb_max = IXGBE_MAX_RING_DESC, 485 .nb_min = IXGBE_MIN_RING_DESC, 486 .nb_align = IXGBE_RXD_ALIGN, 487 }; 488 489 static const struct rte_eth_desc_lim tx_desc_lim = { 490 .nb_max = IXGBE_MAX_RING_DESC, 491 .nb_min = IXGBE_MIN_RING_DESC, 492 .nb_align = IXGBE_TXD_ALIGN, 493 .nb_seg_max = IXGBE_TX_MAX_SEG, 494 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG, 495 }; 496 497 static const struct eth_dev_ops ixgbe_eth_dev_ops = { 498 .dev_configure = ixgbe_dev_configure, 499 .dev_start = ixgbe_dev_start, 500 .dev_stop = ixgbe_dev_stop, 501 .dev_set_link_up = ixgbe_dev_set_link_up, 502 .dev_set_link_down = ixgbe_dev_set_link_down, 503 .dev_close = ixgbe_dev_close, 504 .dev_reset = ixgbe_dev_reset, 505 .promiscuous_enable = ixgbe_dev_promiscuous_enable, 506 .promiscuous_disable = ixgbe_dev_promiscuous_disable, 507 .allmulticast_enable = ixgbe_dev_allmulticast_enable, 508 .allmulticast_disable = ixgbe_dev_allmulticast_disable, 509 .link_update = ixgbe_dev_link_update, 510 .stats_get = ixgbe_dev_stats_get, 511 .xstats_get = ixgbe_dev_xstats_get, 512 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id, 513 .stats_reset = ixgbe_dev_stats_reset, 514 .xstats_reset = ixgbe_dev_xstats_reset, 515 .xstats_get_names = ixgbe_dev_xstats_get_names, 516 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id, 517 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set, 518 .fw_version_get = ixgbe_fw_version_get, 519 .dev_infos_get = ixgbe_dev_info_get, 520 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 521 .mtu_set = ixgbe_dev_mtu_set, 522 .vlan_filter_set = ixgbe_vlan_filter_set, 523 .vlan_tpid_set = ixgbe_vlan_tpid_set, 524 .vlan_offload_set = ixgbe_vlan_offload_set, 525 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set, 526 .rx_queue_start = ixgbe_dev_rx_queue_start, 527 .rx_queue_stop = ixgbe_dev_rx_queue_stop, 528 .tx_queue_start = ixgbe_dev_tx_queue_start, 529 .tx_queue_stop = ixgbe_dev_tx_queue_stop, 530 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 531 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable, 532 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable, 533 .rx_queue_release = ixgbe_dev_rx_queue_release, 534 .rx_queue_count = ixgbe_dev_rx_queue_count, 535 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done, 536 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status, 537 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status, 538 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 539 .tx_queue_release = ixgbe_dev_tx_queue_release, 540 .dev_led_on = ixgbe_dev_led_on, 541 .dev_led_off = ixgbe_dev_led_off, 542 .flow_ctrl_get = ixgbe_flow_ctrl_get, 543 .flow_ctrl_set = ixgbe_flow_ctrl_set, 544 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set, 545 .mac_addr_add = ixgbe_add_rar, 546 .mac_addr_remove = ixgbe_remove_rar, 547 .mac_addr_set = ixgbe_set_default_mac_addr, 548 .uc_hash_table_set = ixgbe_uc_hash_table_set, 549 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set, 550 .mirror_rule_set = ixgbe_mirror_rule_set, 551 .mirror_rule_reset = ixgbe_mirror_rule_reset, 552 .set_queue_rate_limit = ixgbe_set_queue_rate_limit, 553 .reta_update = ixgbe_dev_rss_reta_update, 554 .reta_query = ixgbe_dev_rss_reta_query, 555 .rss_hash_update = ixgbe_dev_rss_hash_update, 556 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 557 .filter_ctrl = ixgbe_dev_filter_ctrl, 558 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 559 .rxq_info_get = ixgbe_rxq_info_get, 560 .txq_info_get = ixgbe_txq_info_get, 561 .timesync_enable = ixgbe_timesync_enable, 562 .timesync_disable = ixgbe_timesync_disable, 563 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp, 564 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp, 565 .get_reg = ixgbe_get_regs, 566 .get_eeprom_length = ixgbe_get_eeprom_length, 567 .get_eeprom = ixgbe_get_eeprom, 568 .set_eeprom = ixgbe_set_eeprom, 569 .get_module_info = ixgbe_get_module_info, 570 .get_module_eeprom = ixgbe_get_module_eeprom, 571 .get_dcb_info = ixgbe_dev_get_dcb_info, 572 .timesync_adjust_time = ixgbe_timesync_adjust_time, 573 .timesync_read_time = ixgbe_timesync_read_time, 574 .timesync_write_time = ixgbe_timesync_write_time, 575 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf, 576 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set, 577 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add, 578 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del, 579 .tm_ops_get = ixgbe_tm_ops_get, 580 }; 581 582 /* 583 * dev_ops for virtual function, bare necessities for basic vf 584 * operation have been implemented 585 */ 586 static const struct eth_dev_ops ixgbevf_eth_dev_ops = { 587 .dev_configure = ixgbevf_dev_configure, 588 .dev_start = ixgbevf_dev_start, 589 .dev_stop = ixgbevf_dev_stop, 590 .link_update = ixgbevf_dev_link_update, 591 .stats_get = ixgbevf_dev_stats_get, 592 .xstats_get = ixgbevf_dev_xstats_get, 593 .stats_reset = ixgbevf_dev_stats_reset, 594 .xstats_reset = ixgbevf_dev_stats_reset, 595 .xstats_get_names = ixgbevf_dev_xstats_get_names, 596 .dev_close = ixgbevf_dev_close, 597 .dev_reset = ixgbevf_dev_reset, 598 .allmulticast_enable = ixgbevf_dev_allmulticast_enable, 599 .allmulticast_disable = ixgbevf_dev_allmulticast_disable, 600 .dev_infos_get = ixgbevf_dev_info_get, 601 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 602 .mtu_set = ixgbevf_dev_set_mtu, 603 .vlan_filter_set = ixgbevf_vlan_filter_set, 604 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set, 605 .vlan_offload_set = ixgbevf_vlan_offload_set, 606 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 607 .rx_queue_release = ixgbe_dev_rx_queue_release, 608 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done, 609 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status, 610 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status, 611 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 612 .tx_queue_release = ixgbe_dev_tx_queue_release, 613 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable, 614 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable, 615 .mac_addr_add = ixgbevf_add_mac_addr, 616 .mac_addr_remove = ixgbevf_remove_mac_addr, 617 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 618 .rxq_info_get = ixgbe_rxq_info_get, 619 .txq_info_get = ixgbe_txq_info_get, 620 .mac_addr_set = ixgbevf_set_default_mac_addr, 621 .get_reg = ixgbevf_get_regs, 622 .reta_update = ixgbe_dev_rss_reta_update, 623 .reta_query = ixgbe_dev_rss_reta_query, 624 .rss_hash_update = ixgbe_dev_rss_hash_update, 625 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 626 }; 627 628 /* store statistics names and its offset in stats structure */ 629 struct rte_ixgbe_xstats_name_off { 630 char name[RTE_ETH_XSTATS_NAME_SIZE]; 631 unsigned offset; 632 }; 633 634 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = { 635 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)}, 636 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)}, 637 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)}, 638 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)}, 639 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)}, 640 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)}, 641 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)}, 642 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)}, 643 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)}, 644 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)}, 645 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)}, 646 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)}, 647 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)}, 648 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)}, 649 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 650 prc1023)}, 651 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 652 prc1522)}, 653 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)}, 654 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)}, 655 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)}, 656 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)}, 657 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)}, 658 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)}, 659 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)}, 660 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)}, 661 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)}, 662 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)}, 663 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)}, 664 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)}, 665 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)}, 666 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)}, 667 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)}, 668 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)}, 669 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 670 ptc1023)}, 671 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 672 ptc1522)}, 673 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)}, 674 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)}, 675 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)}, 676 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)}, 677 678 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats, 679 fdirustat_add)}, 680 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats, 681 fdirustat_remove)}, 682 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats, 683 fdirfstat_fadd)}, 684 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats, 685 fdirfstat_fremove)}, 686 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats, 687 fdirmatch)}, 688 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats, 689 fdirmiss)}, 690 691 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)}, 692 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)}, 693 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, 694 fclast)}, 695 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)}, 696 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)}, 697 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)}, 698 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)}, 699 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats, 700 fcoe_noddp)}, 701 {"rx_fcoe_no_direct_data_placement_ext_buff", 702 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)}, 703 704 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 705 lxontxc)}, 706 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 707 lxonrxc)}, 708 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 709 lxofftxc)}, 710 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 711 lxoffrxc)}, 712 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)}, 713 }; 714 715 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \ 716 sizeof(rte_ixgbe_stats_strings[0])) 717 718 /* MACsec statistics */ 719 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = { 720 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 721 out_pkts_untagged)}, 722 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats, 723 out_pkts_encrypted)}, 724 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats, 725 out_pkts_protected)}, 726 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats, 727 out_octets_encrypted)}, 728 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats, 729 out_octets_protected)}, 730 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 731 in_pkts_untagged)}, 732 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats, 733 in_pkts_badtag)}, 734 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats, 735 in_pkts_nosci)}, 736 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats, 737 in_pkts_unknownsci)}, 738 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats, 739 in_octets_decrypted)}, 740 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats, 741 in_octets_validated)}, 742 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats, 743 in_pkts_unchecked)}, 744 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats, 745 in_pkts_delayed)}, 746 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats, 747 in_pkts_late)}, 748 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats, 749 in_pkts_ok)}, 750 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats, 751 in_pkts_invalid)}, 752 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats, 753 in_pkts_notvalid)}, 754 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats, 755 in_pkts_unusedsa)}, 756 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats, 757 in_pkts_notusingsa)}, 758 }; 759 760 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \ 761 sizeof(rte_ixgbe_macsec_strings[0])) 762 763 /* Per-queue statistics */ 764 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = { 765 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)}, 766 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)}, 767 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)}, 768 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)}, 769 }; 770 771 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \ 772 sizeof(rte_ixgbe_rxq_strings[0])) 773 #define IXGBE_NB_RXQ_PRIO_VALUES 8 774 775 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = { 776 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)}, 777 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)}, 778 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats, 779 pxon2offc)}, 780 }; 781 782 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \ 783 sizeof(rte_ixgbe_txq_strings[0])) 784 #define IXGBE_NB_TXQ_PRIO_VALUES 8 785 786 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = { 787 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)}, 788 }; 789 790 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \ 791 sizeof(rte_ixgbevf_stats_strings[0])) 792 793 /* 794 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h. 795 */ 796 static inline int 797 ixgbe_is_sfp(struct ixgbe_hw *hw) 798 { 799 switch (hw->phy.type) { 800 case ixgbe_phy_sfp_avago: 801 case ixgbe_phy_sfp_ftl: 802 case ixgbe_phy_sfp_intel: 803 case ixgbe_phy_sfp_unknown: 804 case ixgbe_phy_sfp_passive_tyco: 805 case ixgbe_phy_sfp_passive_unknown: 806 return 1; 807 default: 808 return 0; 809 } 810 } 811 812 static inline int32_t 813 ixgbe_pf_reset_hw(struct ixgbe_hw *hw) 814 { 815 uint32_t ctrl_ext; 816 int32_t status; 817 818 status = ixgbe_reset_hw(hw); 819 820 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 821 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 822 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 823 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 824 IXGBE_WRITE_FLUSH(hw); 825 826 if (status == IXGBE_ERR_SFP_NOT_PRESENT) 827 status = IXGBE_SUCCESS; 828 return status; 829 } 830 831 static inline void 832 ixgbe_enable_intr(struct rte_eth_dev *dev) 833 { 834 struct ixgbe_interrupt *intr = 835 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 836 struct ixgbe_hw *hw = 837 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 838 839 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask); 840 IXGBE_WRITE_FLUSH(hw); 841 } 842 843 /* 844 * This function is based on ixgbe_disable_intr() in base/ixgbe.h. 845 */ 846 static void 847 ixgbe_disable_intr(struct ixgbe_hw *hw) 848 { 849 PMD_INIT_FUNC_TRACE(); 850 851 if (hw->mac.type == ixgbe_mac_82598EB) { 852 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0); 853 } else { 854 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000); 855 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0); 856 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0); 857 } 858 IXGBE_WRITE_FLUSH(hw); 859 } 860 861 /* 862 * This function resets queue statistics mapping registers. 863 * From Niantic datasheet, Initialization of Statistics section: 864 * "...if software requires the queue counters, the RQSMR and TQSM registers 865 * must be re-programmed following a device reset. 866 */ 867 static void 868 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw) 869 { 870 uint32_t i; 871 872 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) { 873 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0); 874 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0); 875 } 876 } 877 878 879 static int 880 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 881 uint16_t queue_id, 882 uint8_t stat_idx, 883 uint8_t is_rx) 884 { 885 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8 886 #define NB_QMAP_FIELDS_PER_QSM_REG 4 887 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f 888 889 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 890 struct ixgbe_stat_mapping_registers *stat_mappings = 891 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private); 892 uint32_t qsmr_mask = 0; 893 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK; 894 uint32_t q_map; 895 uint8_t n, offset; 896 897 if ((hw->mac.type != ixgbe_mac_82599EB) && 898 (hw->mac.type != ixgbe_mac_X540) && 899 (hw->mac.type != ixgbe_mac_X550) && 900 (hw->mac.type != ixgbe_mac_X550EM_x) && 901 (hw->mac.type != ixgbe_mac_X550EM_a)) 902 return -ENOSYS; 903 904 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d", 905 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 906 queue_id, stat_idx); 907 908 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG); 909 if (n >= IXGBE_NB_STAT_MAPPING_REGS) { 910 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded"); 911 return -EIO; 912 } 913 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG); 914 915 /* Now clear any previous stat_idx set */ 916 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 917 if (!is_rx) 918 stat_mappings->tqsm[n] &= ~clearing_mask; 919 else 920 stat_mappings->rqsmr[n] &= ~clearing_mask; 921 922 q_map = (uint32_t)stat_idx; 923 q_map &= QMAP_FIELD_RESERVED_BITS_MASK; 924 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 925 if (!is_rx) 926 stat_mappings->tqsm[n] |= qsmr_mask; 927 else 928 stat_mappings->rqsmr[n] |= qsmr_mask; 929 930 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d", 931 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 932 queue_id, stat_idx); 933 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n, 934 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]); 935 936 /* Now write the mapping in the appropriate register */ 937 if (is_rx) { 938 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d", 939 stat_mappings->rqsmr[n], n); 940 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]); 941 } else { 942 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d", 943 stat_mappings->tqsm[n], n); 944 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]); 945 } 946 return 0; 947 } 948 949 static void 950 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev) 951 { 952 struct ixgbe_stat_mapping_registers *stat_mappings = 953 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private); 954 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 955 int i; 956 957 /* write whatever was in stat mapping table to the NIC */ 958 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) { 959 /* rx */ 960 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]); 961 962 /* tx */ 963 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]); 964 } 965 } 966 967 static void 968 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config) 969 { 970 uint8_t i; 971 struct ixgbe_dcb_tc_config *tc; 972 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS; 973 974 dcb_config->num_tcs.pg_tcs = dcb_max_tc; 975 dcb_config->num_tcs.pfc_tcs = dcb_max_tc; 976 for (i = 0; i < dcb_max_tc; i++) { 977 tc = &dcb_config->tc_config[i]; 978 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i; 979 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 980 (uint8_t)(100/dcb_max_tc + (i & 1)); 981 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i; 982 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 983 (uint8_t)(100/dcb_max_tc + (i & 1)); 984 tc->pfc = ixgbe_dcb_pfc_disabled; 985 } 986 987 /* Initialize default user to priority mapping, UPx->TC0 */ 988 tc = &dcb_config->tc_config[0]; 989 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 990 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 991 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) { 992 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100; 993 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100; 994 } 995 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal; 996 dcb_config->pfc_mode_enable = false; 997 dcb_config->vt_mode = true; 998 dcb_config->round_robin_enable = false; 999 /* support all DCB capabilities in 82599 */ 1000 dcb_config->support.capabilities = 0xFF; 1001 1002 /*we only support 4 Tcs for X540, X550 */ 1003 if (hw->mac.type == ixgbe_mac_X540 || 1004 hw->mac.type == ixgbe_mac_X550 || 1005 hw->mac.type == ixgbe_mac_X550EM_x || 1006 hw->mac.type == ixgbe_mac_X550EM_a) { 1007 dcb_config->num_tcs.pg_tcs = 4; 1008 dcb_config->num_tcs.pfc_tcs = 4; 1009 } 1010 } 1011 1012 /* 1013 * Ensure that all locks are released before first NVM or PHY access 1014 */ 1015 static void 1016 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw) 1017 { 1018 uint16_t mask; 1019 1020 /* 1021 * Phy lock should not fail in this early stage. If this is the case, 1022 * it is due to an improper exit of the application. 1023 * So force the release of the faulty lock. Release of common lock 1024 * is done automatically by swfw_sync function. 1025 */ 1026 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func; 1027 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1028 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func); 1029 } 1030 ixgbe_release_swfw_semaphore(hw, mask); 1031 1032 /* 1033 * These ones are more tricky since they are common to all ports; but 1034 * swfw_sync retries last long enough (1s) to be almost sure that if 1035 * lock can not be taken it is due to an improper lock of the 1036 * semaphore. 1037 */ 1038 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM; 1039 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1040 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 1041 } 1042 ixgbe_release_swfw_semaphore(hw, mask); 1043 } 1044 1045 /* 1046 * This function is based on code in ixgbe_attach() in base/ixgbe.c. 1047 * It returns 0 on success. 1048 */ 1049 static int 1050 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) 1051 { 1052 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1053 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1054 struct ixgbe_hw *hw = 1055 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1056 struct ixgbe_vfta *shadow_vfta = 1057 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1058 struct ixgbe_hwstrip *hwstrip = 1059 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1060 struct ixgbe_dcb_config *dcb_config = 1061 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private); 1062 struct ixgbe_filter_info *filter_info = 1063 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1064 struct ixgbe_bw_conf *bw_conf = 1065 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private); 1066 uint32_t ctrl_ext; 1067 uint16_t csum; 1068 int diag, i; 1069 1070 PMD_INIT_FUNC_TRACE(); 1071 1072 eth_dev->dev_ops = &ixgbe_eth_dev_ops; 1073 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1074 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1075 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts; 1076 1077 /* 1078 * For secondary processes, we don't initialise any further as primary 1079 * has already done this work. Only check we don't need a different 1080 * RX and TX function. 1081 */ 1082 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1083 struct ixgbe_tx_queue *txq; 1084 /* TX queue function in primary, set by last queue initialized 1085 * Tx queue may not initialized by primary process 1086 */ 1087 if (eth_dev->data->tx_queues) { 1088 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1]; 1089 ixgbe_set_tx_function(eth_dev, txq); 1090 } else { 1091 /* Use default TX function if we get here */ 1092 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. " 1093 "Using default TX function."); 1094 } 1095 1096 ixgbe_set_rx_function(eth_dev); 1097 1098 return 0; 1099 } 1100 1101 rte_eth_copy_pci_info(eth_dev, pci_dev); 1102 1103 /* Vendor and Device ID need to be set before init of shared code */ 1104 hw->device_id = pci_dev->id.device_id; 1105 hw->vendor_id = pci_dev->id.vendor_id; 1106 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1107 hw->allow_unsupported_sfp = 1; 1108 1109 /* Initialize the shared code (base driver) */ 1110 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1111 diag = ixgbe_bypass_init_shared_code(hw); 1112 #else 1113 diag = ixgbe_init_shared_code(hw); 1114 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1115 1116 if (diag != IXGBE_SUCCESS) { 1117 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag); 1118 return -EIO; 1119 } 1120 1121 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 1122 PMD_INIT_LOG(ERR, "\nERROR: " 1123 "Firmware recovery mode detected. Limiting functionality.\n" 1124 "Refer to the Intel(R) Ethernet Adapters and Devices " 1125 "User Guide for details on firmware recovery mode."); 1126 return -EIO; 1127 } 1128 1129 /* pick up the PCI bus settings for reporting later */ 1130 ixgbe_get_bus_info(hw); 1131 1132 /* Unlock any pending hardware semaphore */ 1133 ixgbe_swfw_lock_reset(hw); 1134 1135 #ifdef RTE_LIBRTE_SECURITY 1136 /* Initialize security_ctx only for primary process*/ 1137 if (ixgbe_ipsec_ctx_create(eth_dev)) 1138 return -ENOMEM; 1139 #endif 1140 1141 /* Initialize DCB configuration*/ 1142 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config)); 1143 ixgbe_dcb_init(hw, dcb_config); 1144 /* Get Hardware Flow Control setting */ 1145 hw->fc.requested_mode = ixgbe_fc_full; 1146 hw->fc.current_mode = ixgbe_fc_full; 1147 hw->fc.pause_time = IXGBE_FC_PAUSE; 1148 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 1149 hw->fc.low_water[i] = IXGBE_FC_LO; 1150 hw->fc.high_water[i] = IXGBE_FC_HI; 1151 } 1152 hw->fc.send_xon = 1; 1153 1154 /* Make sure we have a good EEPROM before we read from it */ 1155 diag = ixgbe_validate_eeprom_checksum(hw, &csum); 1156 if (diag != IXGBE_SUCCESS) { 1157 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag); 1158 return -EIO; 1159 } 1160 1161 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1162 diag = ixgbe_bypass_init_hw(hw); 1163 #else 1164 diag = ixgbe_init_hw(hw); 1165 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1166 1167 /* 1168 * Devices with copper phys will fail to initialise if ixgbe_init_hw() 1169 * is called too soon after the kernel driver unbinding/binding occurs. 1170 * The failure occurs in ixgbe_identify_phy_generic() for all devices, 1171 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is 1172 * also called. See ixgbe_identify_phy_82599(). The reason for the 1173 * failure is not known, and only occuts when virtualisation features 1174 * are disabled in the bios. A delay of 100ms was found to be enough by 1175 * trial-and-error, and is doubled to be safe. 1176 */ 1177 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) { 1178 rte_delay_ms(200); 1179 diag = ixgbe_init_hw(hw); 1180 } 1181 1182 if (diag == IXGBE_ERR_SFP_NOT_PRESENT) 1183 diag = IXGBE_SUCCESS; 1184 1185 if (diag == IXGBE_ERR_EEPROM_VERSION) { 1186 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/" 1187 "LOM. Please be aware there may be issues associated " 1188 "with your hardware."); 1189 PMD_INIT_LOG(ERR, "If you are experiencing problems " 1190 "please contact your Intel or hardware representative " 1191 "who provided you with this hardware."); 1192 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED) 1193 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module"); 1194 if (diag) { 1195 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag); 1196 return -EIO; 1197 } 1198 1199 /* Reset the hw statistics */ 1200 ixgbe_dev_stats_reset(eth_dev); 1201 1202 /* disable interrupt */ 1203 ixgbe_disable_intr(hw); 1204 1205 /* reset mappings for queue statistics hw counters*/ 1206 ixgbe_reset_qstat_mappings(hw); 1207 1208 /* Allocate memory for storing MAC addresses */ 1209 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN * 1210 hw->mac.num_rar_entries, 0); 1211 if (eth_dev->data->mac_addrs == NULL) { 1212 PMD_INIT_LOG(ERR, 1213 "Failed to allocate %u bytes needed to store " 1214 "MAC addresses", 1215 ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1216 return -ENOMEM; 1217 } 1218 /* Copy the permanent MAC address */ 1219 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr, 1220 ð_dev->data->mac_addrs[0]); 1221 1222 /* Allocate memory for storing hash filter MAC addresses */ 1223 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN * 1224 IXGBE_VMDQ_NUM_UC_MAC, 0); 1225 if (eth_dev->data->hash_mac_addrs == NULL) { 1226 PMD_INIT_LOG(ERR, 1227 "Failed to allocate %d bytes needed to store MAC addresses", 1228 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC); 1229 return -ENOMEM; 1230 } 1231 1232 /* initialize the vfta */ 1233 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1234 1235 /* initialize the hw strip bitmap*/ 1236 memset(hwstrip, 0, sizeof(*hwstrip)); 1237 1238 /* initialize PF if max_vfs not zero */ 1239 ixgbe_pf_host_init(eth_dev); 1240 1241 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 1242 /* let hardware know driver is loaded */ 1243 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD; 1244 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 1245 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 1246 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 1247 IXGBE_WRITE_FLUSH(hw); 1248 1249 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 1250 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d", 1251 (int) hw->mac.type, (int) hw->phy.type, 1252 (int) hw->phy.sfp_type); 1253 else 1254 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d", 1255 (int) hw->mac.type, (int) hw->phy.type); 1256 1257 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 1258 eth_dev->data->port_id, pci_dev->id.vendor_id, 1259 pci_dev->id.device_id); 1260 1261 rte_intr_callback_register(intr_handle, 1262 ixgbe_dev_interrupt_handler, eth_dev); 1263 1264 /* enable uio/vfio intr/eventfd mapping */ 1265 rte_intr_enable(intr_handle); 1266 1267 /* enable support intr */ 1268 ixgbe_enable_intr(eth_dev); 1269 1270 /* initialize filter info */ 1271 memset(filter_info, 0, 1272 sizeof(struct ixgbe_filter_info)); 1273 1274 /* initialize 5tuple filter list */ 1275 TAILQ_INIT(&filter_info->fivetuple_list); 1276 1277 /* initialize flow director filter list & hash */ 1278 ixgbe_fdir_filter_init(eth_dev); 1279 1280 /* initialize l2 tunnel filter list & hash */ 1281 ixgbe_l2_tn_filter_init(eth_dev); 1282 1283 /* initialize flow filter lists */ 1284 ixgbe_filterlist_init(); 1285 1286 /* initialize bandwidth configuration info */ 1287 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf)); 1288 1289 /* initialize Traffic Manager configuration */ 1290 ixgbe_tm_conf_init(eth_dev); 1291 1292 return 0; 1293 } 1294 1295 static int 1296 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1297 { 1298 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1299 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1300 struct ixgbe_hw *hw; 1301 int retries = 0; 1302 int ret; 1303 1304 PMD_INIT_FUNC_TRACE(); 1305 1306 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1307 return -EPERM; 1308 1309 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1310 1311 if (hw->adapter_stopped == 0) 1312 ixgbe_dev_close(eth_dev); 1313 1314 eth_dev->dev_ops = NULL; 1315 eth_dev->rx_pkt_burst = NULL; 1316 eth_dev->tx_pkt_burst = NULL; 1317 1318 /* Unlock any pending hardware semaphore */ 1319 ixgbe_swfw_lock_reset(hw); 1320 1321 /* disable uio intr before callback unregister */ 1322 rte_intr_disable(intr_handle); 1323 1324 do { 1325 ret = rte_intr_callback_unregister(intr_handle, 1326 ixgbe_dev_interrupt_handler, eth_dev); 1327 if (ret >= 0) { 1328 break; 1329 } else if (ret != -EAGAIN) { 1330 PMD_INIT_LOG(ERR, 1331 "intr callback unregister failed: %d", 1332 ret); 1333 return ret; 1334 } 1335 rte_delay_ms(100); 1336 } while (retries++ < (10 + IXGBE_LINK_UP_TIME)); 1337 1338 /* uninitialize PF if max_vfs not zero */ 1339 ixgbe_pf_host_uninit(eth_dev); 1340 1341 rte_free(eth_dev->data->mac_addrs); 1342 eth_dev->data->mac_addrs = NULL; 1343 1344 rte_free(eth_dev->data->hash_mac_addrs); 1345 eth_dev->data->hash_mac_addrs = NULL; 1346 1347 /* remove all the fdir filters & hash */ 1348 ixgbe_fdir_filter_uninit(eth_dev); 1349 1350 /* remove all the L2 tunnel filters & hash */ 1351 ixgbe_l2_tn_filter_uninit(eth_dev); 1352 1353 /* Remove all ntuple filters of the device */ 1354 ixgbe_ntuple_filter_uninit(eth_dev); 1355 1356 /* clear all the filters list */ 1357 ixgbe_filterlist_flush(); 1358 1359 /* Remove all Traffic Manager configuration */ 1360 ixgbe_tm_conf_uninit(eth_dev); 1361 1362 #ifdef RTE_LIBRTE_SECURITY 1363 rte_free(eth_dev->security_ctx); 1364 #endif 1365 1366 return 0; 1367 } 1368 1369 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev) 1370 { 1371 struct ixgbe_filter_info *filter_info = 1372 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1373 struct ixgbe_5tuple_filter *p_5tuple; 1374 1375 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) { 1376 TAILQ_REMOVE(&filter_info->fivetuple_list, 1377 p_5tuple, 1378 entries); 1379 rte_free(p_5tuple); 1380 } 1381 memset(filter_info->fivetuple_mask, 0, 1382 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE); 1383 1384 return 0; 1385 } 1386 1387 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev) 1388 { 1389 struct ixgbe_hw_fdir_info *fdir_info = 1390 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1391 struct ixgbe_fdir_filter *fdir_filter; 1392 1393 if (fdir_info->hash_map) 1394 rte_free(fdir_info->hash_map); 1395 if (fdir_info->hash_handle) 1396 rte_hash_free(fdir_info->hash_handle); 1397 1398 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 1399 TAILQ_REMOVE(&fdir_info->fdir_list, 1400 fdir_filter, 1401 entries); 1402 rte_free(fdir_filter); 1403 } 1404 1405 return 0; 1406 } 1407 1408 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev) 1409 { 1410 struct ixgbe_l2_tn_info *l2_tn_info = 1411 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1412 struct ixgbe_l2_tn_filter *l2_tn_filter; 1413 1414 if (l2_tn_info->hash_map) 1415 rte_free(l2_tn_info->hash_map); 1416 if (l2_tn_info->hash_handle) 1417 rte_hash_free(l2_tn_info->hash_handle); 1418 1419 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 1420 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, 1421 l2_tn_filter, 1422 entries); 1423 rte_free(l2_tn_filter); 1424 } 1425 1426 return 0; 1427 } 1428 1429 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev) 1430 { 1431 struct ixgbe_hw_fdir_info *fdir_info = 1432 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1433 char fdir_hash_name[RTE_HASH_NAMESIZE]; 1434 struct rte_hash_parameters fdir_hash_params = { 1435 .name = fdir_hash_name, 1436 .entries = IXGBE_MAX_FDIR_FILTER_NUM, 1437 .key_len = sizeof(union ixgbe_atr_input), 1438 .hash_func = rte_hash_crc, 1439 .hash_func_init_val = 0, 1440 .socket_id = rte_socket_id(), 1441 }; 1442 1443 TAILQ_INIT(&fdir_info->fdir_list); 1444 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 1445 "fdir_%s", eth_dev->device->name); 1446 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params); 1447 if (!fdir_info->hash_handle) { 1448 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 1449 return -EINVAL; 1450 } 1451 fdir_info->hash_map = rte_zmalloc("ixgbe", 1452 sizeof(struct ixgbe_fdir_filter *) * 1453 IXGBE_MAX_FDIR_FILTER_NUM, 1454 0); 1455 if (!fdir_info->hash_map) { 1456 PMD_INIT_LOG(ERR, 1457 "Failed to allocate memory for fdir hash map!"); 1458 return -ENOMEM; 1459 } 1460 fdir_info->mask_added = FALSE; 1461 1462 return 0; 1463 } 1464 1465 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) 1466 { 1467 struct ixgbe_l2_tn_info *l2_tn_info = 1468 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1469 char l2_tn_hash_name[RTE_HASH_NAMESIZE]; 1470 struct rte_hash_parameters l2_tn_hash_params = { 1471 .name = l2_tn_hash_name, 1472 .entries = IXGBE_MAX_L2_TN_FILTER_NUM, 1473 .key_len = sizeof(struct ixgbe_l2_tn_key), 1474 .hash_func = rte_hash_crc, 1475 .hash_func_init_val = 0, 1476 .socket_id = rte_socket_id(), 1477 }; 1478 1479 TAILQ_INIT(&l2_tn_info->l2_tn_list); 1480 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE, 1481 "l2_tn_%s", eth_dev->device->name); 1482 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params); 1483 if (!l2_tn_info->hash_handle) { 1484 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!"); 1485 return -EINVAL; 1486 } 1487 l2_tn_info->hash_map = rte_zmalloc("ixgbe", 1488 sizeof(struct ixgbe_l2_tn_filter *) * 1489 IXGBE_MAX_L2_TN_FILTER_NUM, 1490 0); 1491 if (!l2_tn_info->hash_map) { 1492 PMD_INIT_LOG(ERR, 1493 "Failed to allocate memory for L2 TN hash map!"); 1494 return -ENOMEM; 1495 } 1496 l2_tn_info->e_tag_en = FALSE; 1497 l2_tn_info->e_tag_fwd_en = FALSE; 1498 l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG; 1499 1500 return 0; 1501 } 1502 /* 1503 * Negotiate mailbox API version with the PF. 1504 * After reset API version is always set to the basic one (ixgbe_mbox_api_10). 1505 * Then we try to negotiate starting with the most recent one. 1506 * If all negotiation attempts fail, then we will proceed with 1507 * the default one (ixgbe_mbox_api_10). 1508 */ 1509 static void 1510 ixgbevf_negotiate_api(struct ixgbe_hw *hw) 1511 { 1512 int32_t i; 1513 1514 /* start with highest supported, proceed down */ 1515 static const enum ixgbe_pfvf_api_rev sup_ver[] = { 1516 ixgbe_mbox_api_12, 1517 ixgbe_mbox_api_11, 1518 ixgbe_mbox_api_10, 1519 }; 1520 1521 for (i = 0; 1522 i != RTE_DIM(sup_ver) && 1523 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0; 1524 i++) 1525 ; 1526 } 1527 1528 static void 1529 generate_random_mac_addr(struct ether_addr *mac_addr) 1530 { 1531 uint64_t random; 1532 1533 /* Set Organizationally Unique Identifier (OUI) prefix. */ 1534 mac_addr->addr_bytes[0] = 0x00; 1535 mac_addr->addr_bytes[1] = 0x09; 1536 mac_addr->addr_bytes[2] = 0xC0; 1537 /* Force indication of locally assigned MAC address. */ 1538 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR; 1539 /* Generate the last 3 bytes of the MAC address with a random number. */ 1540 random = rte_rand(); 1541 memcpy(&mac_addr->addr_bytes[3], &random, 3); 1542 } 1543 1544 /* 1545 * Virtual Function device init 1546 */ 1547 static int 1548 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev) 1549 { 1550 int diag; 1551 uint32_t tc, tcs; 1552 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1553 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1554 struct ixgbe_hw *hw = 1555 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1556 struct ixgbe_vfta *shadow_vfta = 1557 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1558 struct ixgbe_hwstrip *hwstrip = 1559 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1560 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr; 1561 1562 PMD_INIT_FUNC_TRACE(); 1563 1564 eth_dev->dev_ops = &ixgbevf_eth_dev_ops; 1565 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1566 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1567 1568 /* for secondary processes, we don't initialise any further as primary 1569 * has already done this work. Only check we don't need a different 1570 * RX function 1571 */ 1572 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1573 struct ixgbe_tx_queue *txq; 1574 /* TX queue function in primary, set by last queue initialized 1575 * Tx queue may not initialized by primary process 1576 */ 1577 if (eth_dev->data->tx_queues) { 1578 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1]; 1579 ixgbe_set_tx_function(eth_dev, txq); 1580 } else { 1581 /* Use default TX function if we get here */ 1582 PMD_INIT_LOG(NOTICE, 1583 "No TX queues configured yet. Using default TX function."); 1584 } 1585 1586 ixgbe_set_rx_function(eth_dev); 1587 1588 return 0; 1589 } 1590 1591 rte_eth_copy_pci_info(eth_dev, pci_dev); 1592 1593 hw->device_id = pci_dev->id.device_id; 1594 hw->vendor_id = pci_dev->id.vendor_id; 1595 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1596 1597 /* initialize the vfta */ 1598 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1599 1600 /* initialize the hw strip bitmap*/ 1601 memset(hwstrip, 0, sizeof(*hwstrip)); 1602 1603 /* Initialize the shared code (base driver) */ 1604 diag = ixgbe_init_shared_code(hw); 1605 if (diag != IXGBE_SUCCESS) { 1606 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag); 1607 return -EIO; 1608 } 1609 1610 /* init_mailbox_params */ 1611 hw->mbx.ops.init_params(hw); 1612 1613 /* Reset the hw statistics */ 1614 ixgbevf_dev_stats_reset(eth_dev); 1615 1616 /* Disable the interrupts for VF */ 1617 ixgbevf_intr_disable(eth_dev); 1618 1619 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */ 1620 diag = hw->mac.ops.reset_hw(hw); 1621 1622 /* 1623 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when 1624 * the underlying PF driver has not assigned a MAC address to the VF. 1625 * In this case, assign a random MAC address. 1626 */ 1627 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) { 1628 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1629 /* 1630 * This error code will be propagated to the app by 1631 * rte_eth_dev_reset, so use a public error code rather than 1632 * the internal-only IXGBE_ERR_RESET_FAILED 1633 */ 1634 return -EAGAIN; 1635 } 1636 1637 /* negotiate mailbox API version to use with the PF. */ 1638 ixgbevf_negotiate_api(hw); 1639 1640 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */ 1641 ixgbevf_get_queues(hw, &tcs, &tc); 1642 1643 /* Allocate memory for storing MAC addresses */ 1644 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN * 1645 hw->mac.num_rar_entries, 0); 1646 if (eth_dev->data->mac_addrs == NULL) { 1647 PMD_INIT_LOG(ERR, 1648 "Failed to allocate %u bytes needed to store " 1649 "MAC addresses", 1650 ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1651 return -ENOMEM; 1652 } 1653 1654 /* Generate a random MAC address, if none was assigned by PF. */ 1655 if (is_zero_ether_addr(perm_addr)) { 1656 generate_random_mac_addr(perm_addr); 1657 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1); 1658 if (diag) { 1659 rte_free(eth_dev->data->mac_addrs); 1660 eth_dev->data->mac_addrs = NULL; 1661 return diag; 1662 } 1663 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF"); 1664 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address " 1665 "%02x:%02x:%02x:%02x:%02x:%02x", 1666 perm_addr->addr_bytes[0], 1667 perm_addr->addr_bytes[1], 1668 perm_addr->addr_bytes[2], 1669 perm_addr->addr_bytes[3], 1670 perm_addr->addr_bytes[4], 1671 perm_addr->addr_bytes[5]); 1672 } 1673 1674 /* Copy the permanent MAC address */ 1675 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]); 1676 1677 /* reset the hardware with the new settings */ 1678 diag = hw->mac.ops.start_hw(hw); 1679 switch (diag) { 1680 case 0: 1681 break; 1682 1683 default: 1684 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1685 return -EIO; 1686 } 1687 1688 rte_intr_callback_register(intr_handle, 1689 ixgbevf_dev_interrupt_handler, eth_dev); 1690 rte_intr_enable(intr_handle); 1691 ixgbevf_intr_enable(eth_dev); 1692 1693 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s", 1694 eth_dev->data->port_id, pci_dev->id.vendor_id, 1695 pci_dev->id.device_id, "ixgbe_mac_82599_vf"); 1696 1697 return 0; 1698 } 1699 1700 /* Virtual Function device uninit */ 1701 1702 static int 1703 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev) 1704 { 1705 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1706 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1707 struct ixgbe_hw *hw; 1708 1709 PMD_INIT_FUNC_TRACE(); 1710 1711 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1712 return -EPERM; 1713 1714 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1715 1716 if (hw->adapter_stopped == 0) 1717 ixgbevf_dev_close(eth_dev); 1718 1719 eth_dev->dev_ops = NULL; 1720 eth_dev->rx_pkt_burst = NULL; 1721 eth_dev->tx_pkt_burst = NULL; 1722 1723 /* Disable the interrupts for VF */ 1724 ixgbevf_intr_disable(eth_dev); 1725 1726 rte_free(eth_dev->data->mac_addrs); 1727 eth_dev->data->mac_addrs = NULL; 1728 1729 rte_intr_disable(intr_handle); 1730 rte_intr_callback_unregister(intr_handle, 1731 ixgbevf_dev_interrupt_handler, eth_dev); 1732 1733 return 0; 1734 } 1735 1736 static int 1737 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1738 struct rte_pci_device *pci_dev) 1739 { 1740 char name[RTE_ETH_NAME_MAX_LEN]; 1741 struct rte_eth_dev *pf_ethdev; 1742 struct rte_eth_devargs eth_da; 1743 int i, retval; 1744 1745 if (pci_dev->device.devargs) { 1746 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 1747 ð_da); 1748 if (retval) 1749 return retval; 1750 } else 1751 memset(ð_da, 0, sizeof(eth_da)); 1752 1753 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 1754 sizeof(struct ixgbe_adapter), 1755 eth_dev_pci_specific_init, pci_dev, 1756 eth_ixgbe_dev_init, NULL); 1757 1758 if (retval || eth_da.nb_representor_ports < 1) 1759 return retval; 1760 1761 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1762 if (pf_ethdev == NULL) 1763 return -ENODEV; 1764 1765 /* probe VF representor ports */ 1766 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1767 struct ixgbe_vf_info *vfinfo; 1768 struct ixgbe_vf_representor representor; 1769 1770 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA( 1771 pf_ethdev->data->dev_private); 1772 if (vfinfo == NULL) { 1773 PMD_DRV_LOG(ERR, 1774 "no virtual functions supported by PF"); 1775 break; 1776 } 1777 1778 representor.vf_id = eth_da.representor_ports[i]; 1779 representor.switch_domain_id = vfinfo->switch_domain_id; 1780 representor.pf_ethdev = pf_ethdev; 1781 1782 /* representor port net_bdf_port */ 1783 snprintf(name, sizeof(name), "net_%s_representor_%d", 1784 pci_dev->device.name, 1785 eth_da.representor_ports[i]); 1786 1787 retval = rte_eth_dev_create(&pci_dev->device, name, 1788 sizeof(struct ixgbe_vf_representor), NULL, NULL, 1789 ixgbe_vf_representor_init, &representor); 1790 1791 if (retval) 1792 PMD_DRV_LOG(ERR, "failed to create ixgbe vf " 1793 "representor %s.", name); 1794 } 1795 1796 return 0; 1797 } 1798 1799 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev) 1800 { 1801 struct rte_eth_dev *ethdev; 1802 1803 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1804 if (!ethdev) 1805 return -ENODEV; 1806 1807 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 1808 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit); 1809 else 1810 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit); 1811 } 1812 1813 static struct rte_pci_driver rte_ixgbe_pmd = { 1814 .id_table = pci_id_ixgbe_map, 1815 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 1816 RTE_PCI_DRV_IOVA_AS_VA, 1817 .probe = eth_ixgbe_pci_probe, 1818 .remove = eth_ixgbe_pci_remove, 1819 }; 1820 1821 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1822 struct rte_pci_device *pci_dev) 1823 { 1824 return rte_eth_dev_pci_generic_probe(pci_dev, 1825 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init); 1826 } 1827 1828 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev) 1829 { 1830 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit); 1831 } 1832 1833 /* 1834 * virtual function driver struct 1835 */ 1836 static struct rte_pci_driver rte_ixgbevf_pmd = { 1837 .id_table = pci_id_ixgbevf_map, 1838 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA, 1839 .probe = eth_ixgbevf_pci_probe, 1840 .remove = eth_ixgbevf_pci_remove, 1841 }; 1842 1843 static int 1844 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1845 { 1846 struct ixgbe_hw *hw = 1847 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1848 struct ixgbe_vfta *shadow_vfta = 1849 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1850 uint32_t vfta; 1851 uint32_t vid_idx; 1852 uint32_t vid_bit; 1853 1854 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 1855 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 1856 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx)); 1857 if (on) 1858 vfta |= vid_bit; 1859 else 1860 vfta &= ~vid_bit; 1861 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta); 1862 1863 /* update local VFTA copy */ 1864 shadow_vfta->vfta[vid_idx] = vfta; 1865 1866 return 0; 1867 } 1868 1869 static void 1870 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 1871 { 1872 if (on) 1873 ixgbe_vlan_hw_strip_enable(dev, queue); 1874 else 1875 ixgbe_vlan_hw_strip_disable(dev, queue); 1876 } 1877 1878 static int 1879 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1880 enum rte_vlan_type vlan_type, 1881 uint16_t tpid) 1882 { 1883 struct ixgbe_hw *hw = 1884 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1885 int ret = 0; 1886 uint32_t reg; 1887 uint32_t qinq; 1888 1889 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1890 qinq &= IXGBE_DMATXCTL_GDV; 1891 1892 switch (vlan_type) { 1893 case ETH_VLAN_TYPE_INNER: 1894 if (qinq) { 1895 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1896 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1897 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1898 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1899 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1900 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1901 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1902 } else { 1903 ret = -ENOTSUP; 1904 PMD_DRV_LOG(ERR, "Inner type is not supported" 1905 " by single VLAN"); 1906 } 1907 break; 1908 case ETH_VLAN_TYPE_OUTER: 1909 if (qinq) { 1910 /* Only the high 16-bits is valid */ 1911 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid << 1912 IXGBE_EXVET_VET_EXT_SHIFT); 1913 } else { 1914 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1915 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1916 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1917 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1918 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1919 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1920 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1921 } 1922 1923 break; 1924 default: 1925 ret = -EINVAL; 1926 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type); 1927 break; 1928 } 1929 1930 return ret; 1931 } 1932 1933 void 1934 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev) 1935 { 1936 struct ixgbe_hw *hw = 1937 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1938 uint32_t vlnctrl; 1939 1940 PMD_INIT_FUNC_TRACE(); 1941 1942 /* Filter Table Disable */ 1943 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1944 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 1945 1946 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1947 } 1948 1949 void 1950 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1951 { 1952 struct ixgbe_hw *hw = 1953 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1954 struct ixgbe_vfta *shadow_vfta = 1955 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1956 uint32_t vlnctrl; 1957 uint16_t i; 1958 1959 PMD_INIT_FUNC_TRACE(); 1960 1961 /* Filter Table Enable */ 1962 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1963 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; 1964 vlnctrl |= IXGBE_VLNCTRL_VFE; 1965 1966 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1967 1968 /* write whatever is in local vfta copy */ 1969 for (i = 0; i < IXGBE_VFTA_SIZE; i++) 1970 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]); 1971 } 1972 1973 static void 1974 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on) 1975 { 1976 struct ixgbe_hwstrip *hwstrip = 1977 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private); 1978 struct ixgbe_rx_queue *rxq; 1979 1980 if (queue >= IXGBE_MAX_RX_QUEUE_NUM) 1981 return; 1982 1983 if (on) 1984 IXGBE_SET_HWSTRIP(hwstrip, queue); 1985 else 1986 IXGBE_CLEAR_HWSTRIP(hwstrip, queue); 1987 1988 if (queue >= dev->data->nb_rx_queues) 1989 return; 1990 1991 rxq = dev->data->rx_queues[queue]; 1992 1993 if (on) { 1994 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; 1995 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 1996 } else { 1997 rxq->vlan_flags = PKT_RX_VLAN; 1998 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 1999 } 2000 } 2001 2002 static void 2003 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue) 2004 { 2005 struct ixgbe_hw *hw = 2006 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2007 uint32_t ctrl; 2008 2009 PMD_INIT_FUNC_TRACE(); 2010 2011 if (hw->mac.type == ixgbe_mac_82598EB) { 2012 /* No queue level support */ 2013 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2014 return; 2015 } 2016 2017 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2018 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2019 ctrl &= ~IXGBE_RXDCTL_VME; 2020 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2021 2022 /* record those setting for HW strip per queue */ 2023 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0); 2024 } 2025 2026 static void 2027 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue) 2028 { 2029 struct ixgbe_hw *hw = 2030 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2031 uint32_t ctrl; 2032 2033 PMD_INIT_FUNC_TRACE(); 2034 2035 if (hw->mac.type == ixgbe_mac_82598EB) { 2036 /* No queue level supported */ 2037 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2038 return; 2039 } 2040 2041 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2042 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2043 ctrl |= IXGBE_RXDCTL_VME; 2044 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2045 2046 /* record those setting for HW strip per queue */ 2047 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1); 2048 } 2049 2050 static void 2051 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev) 2052 { 2053 struct ixgbe_hw *hw = 2054 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2055 uint32_t ctrl; 2056 2057 PMD_INIT_FUNC_TRACE(); 2058 2059 /* DMATXCTRL: Geric Double VLAN Disable */ 2060 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2061 ctrl &= ~IXGBE_DMATXCTL_GDV; 2062 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2063 2064 /* CTRL_EXT: Global Double VLAN Disable */ 2065 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2066 ctrl &= ~IXGBE_EXTENDED_VLAN; 2067 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2068 2069 } 2070 2071 static void 2072 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) 2073 { 2074 struct ixgbe_hw *hw = 2075 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2076 uint32_t ctrl; 2077 2078 PMD_INIT_FUNC_TRACE(); 2079 2080 /* DMATXCTRL: Geric Double VLAN Enable */ 2081 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2082 ctrl |= IXGBE_DMATXCTL_GDV; 2083 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2084 2085 /* CTRL_EXT: Global Double VLAN Enable */ 2086 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2087 ctrl |= IXGBE_EXTENDED_VLAN; 2088 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2089 2090 /* Clear pooling mode of PFVTCTL. It's required by X550. */ 2091 if (hw->mac.type == ixgbe_mac_X550 || 2092 hw->mac.type == ixgbe_mac_X550EM_x || 2093 hw->mac.type == ixgbe_mac_X550EM_a) { 2094 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 2095 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 2096 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 2097 } 2098 2099 /* 2100 * VET EXT field in the EXVET register = 0x8100 by default 2101 * So no need to change. Same to VT field of DMATXCTL register 2102 */ 2103 } 2104 2105 void 2106 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev) 2107 { 2108 struct ixgbe_hw *hw = 2109 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2110 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 2111 uint32_t ctrl; 2112 uint16_t i; 2113 struct ixgbe_rx_queue *rxq; 2114 bool on; 2115 2116 PMD_INIT_FUNC_TRACE(); 2117 2118 if (hw->mac.type == ixgbe_mac_82598EB) { 2119 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2120 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2121 ctrl |= IXGBE_VLNCTRL_VME; 2122 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2123 } else { 2124 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2125 ctrl &= ~IXGBE_VLNCTRL_VME; 2126 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2127 } 2128 } else { 2129 /* 2130 * Other 10G NIC, the VLAN strip can be setup 2131 * per queue in RXDCTL 2132 */ 2133 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2134 rxq = dev->data->rx_queues[i]; 2135 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx)); 2136 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2137 ctrl |= IXGBE_RXDCTL_VME; 2138 on = TRUE; 2139 } else { 2140 ctrl &= ~IXGBE_RXDCTL_VME; 2141 on = FALSE; 2142 } 2143 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl); 2144 2145 /* record those setting for HW strip per queue */ 2146 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on); 2147 } 2148 } 2149 } 2150 2151 static void 2152 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask) 2153 { 2154 uint16_t i; 2155 struct rte_eth_rxmode *rxmode; 2156 struct ixgbe_rx_queue *rxq; 2157 2158 if (mask & ETH_VLAN_STRIP_MASK) { 2159 rxmode = &dev->data->dev_conf.rxmode; 2160 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 2161 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2162 rxq = dev->data->rx_queues[i]; 2163 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 2164 } 2165 else 2166 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2167 rxq = dev->data->rx_queues[i]; 2168 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 2169 } 2170 } 2171 } 2172 2173 static int 2174 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask) 2175 { 2176 struct rte_eth_rxmode *rxmode; 2177 rxmode = &dev->data->dev_conf.rxmode; 2178 2179 if (mask & ETH_VLAN_STRIP_MASK) { 2180 ixgbe_vlan_hw_strip_config(dev); 2181 } 2182 2183 if (mask & ETH_VLAN_FILTER_MASK) { 2184 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 2185 ixgbe_vlan_hw_filter_enable(dev); 2186 else 2187 ixgbe_vlan_hw_filter_disable(dev); 2188 } 2189 2190 if (mask & ETH_VLAN_EXTEND_MASK) { 2191 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2192 ixgbe_vlan_hw_extend_enable(dev); 2193 else 2194 ixgbe_vlan_hw_extend_disable(dev); 2195 } 2196 2197 return 0; 2198 } 2199 2200 static int 2201 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2202 { 2203 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 2204 2205 ixgbe_vlan_offload_config(dev, mask); 2206 2207 return 0; 2208 } 2209 2210 static void 2211 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev) 2212 { 2213 struct ixgbe_hw *hw = 2214 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2215 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */ 2216 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2217 2218 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */ 2219 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl); 2220 } 2221 2222 static int 2223 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q) 2224 { 2225 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2226 2227 switch (nb_rx_q) { 2228 case 1: 2229 case 2: 2230 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS; 2231 break; 2232 case 4: 2233 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS; 2234 break; 2235 default: 2236 return -EINVAL; 2237 } 2238 2239 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 2240 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2241 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 2242 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2243 return 0; 2244 } 2245 2246 static int 2247 ixgbe_check_mq_mode(struct rte_eth_dev *dev) 2248 { 2249 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 2250 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2251 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2252 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2253 2254 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 2255 /* check multi-queue mode */ 2256 switch (dev_conf->rxmode.mq_mode) { 2257 case ETH_MQ_RX_VMDQ_DCB: 2258 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV"); 2259 break; 2260 case ETH_MQ_RX_VMDQ_DCB_RSS: 2261 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */ 2262 PMD_INIT_LOG(ERR, "SRIOV active," 2263 " unsupported mq_mode rx %d.", 2264 dev_conf->rxmode.mq_mode); 2265 return -EINVAL; 2266 case ETH_MQ_RX_RSS: 2267 case ETH_MQ_RX_VMDQ_RSS: 2268 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS; 2269 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) 2270 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) { 2271 PMD_INIT_LOG(ERR, "SRIOV is active," 2272 " invalid queue number" 2273 " for VMDQ RSS, allowed" 2274 " value are 1, 2 or 4."); 2275 return -EINVAL; 2276 } 2277 break; 2278 case ETH_MQ_RX_VMDQ_ONLY: 2279 case ETH_MQ_RX_NONE: 2280 /* if nothing mq mode configure, use default scheme */ 2281 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY; 2282 break; 2283 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/ 2284 /* SRIOV only works in VMDq enable mode */ 2285 PMD_INIT_LOG(ERR, "SRIOV is active," 2286 " wrong mq_mode rx %d.", 2287 dev_conf->rxmode.mq_mode); 2288 return -EINVAL; 2289 } 2290 2291 switch (dev_conf->txmode.mq_mode) { 2292 case ETH_MQ_TX_VMDQ_DCB: 2293 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV"); 2294 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB; 2295 break; 2296 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */ 2297 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY; 2298 break; 2299 } 2300 2301 /* check valid queue number */ 2302 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) || 2303 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) { 2304 PMD_INIT_LOG(ERR, "SRIOV is active," 2305 " nb_rx_q=%d nb_tx_q=%d queue number" 2306 " must be less than or equal to %d.", 2307 nb_rx_q, nb_tx_q, 2308 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool); 2309 return -EINVAL; 2310 } 2311 } else { 2312 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) { 2313 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is" 2314 " not supported."); 2315 return -EINVAL; 2316 } 2317 /* check configuration for vmdb+dcb mode */ 2318 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) { 2319 const struct rte_eth_vmdq_dcb_conf *conf; 2320 2321 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2322 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.", 2323 IXGBE_VMDQ_DCB_NB_QUEUES); 2324 return -EINVAL; 2325 } 2326 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf; 2327 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2328 conf->nb_queue_pools == ETH_32_POOLS)) { 2329 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2330 " nb_queue_pools must be %d or %d.", 2331 ETH_16_POOLS, ETH_32_POOLS); 2332 return -EINVAL; 2333 } 2334 } 2335 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) { 2336 const struct rte_eth_vmdq_dcb_tx_conf *conf; 2337 2338 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2339 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d", 2340 IXGBE_VMDQ_DCB_NB_QUEUES); 2341 return -EINVAL; 2342 } 2343 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf; 2344 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2345 conf->nb_queue_pools == ETH_32_POOLS)) { 2346 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2347 " nb_queue_pools != %d and" 2348 " nb_queue_pools != %d.", 2349 ETH_16_POOLS, ETH_32_POOLS); 2350 return -EINVAL; 2351 } 2352 } 2353 2354 /* For DCB mode check our configuration before we go further */ 2355 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) { 2356 const struct rte_eth_dcb_rx_conf *conf; 2357 2358 conf = &dev_conf->rx_adv_conf.dcb_rx_conf; 2359 if (!(conf->nb_tcs == ETH_4_TCS || 2360 conf->nb_tcs == ETH_8_TCS)) { 2361 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2362 " and nb_tcs != %d.", 2363 ETH_4_TCS, ETH_8_TCS); 2364 return -EINVAL; 2365 } 2366 } 2367 2368 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) { 2369 const struct rte_eth_dcb_tx_conf *conf; 2370 2371 conf = &dev_conf->tx_adv_conf.dcb_tx_conf; 2372 if (!(conf->nb_tcs == ETH_4_TCS || 2373 conf->nb_tcs == ETH_8_TCS)) { 2374 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2375 " and nb_tcs != %d.", 2376 ETH_4_TCS, ETH_8_TCS); 2377 return -EINVAL; 2378 } 2379 } 2380 2381 /* 2382 * When DCB/VT is off, maximum number of queues changes, 2383 * except for 82598EB, which remains constant. 2384 */ 2385 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 2386 hw->mac.type != ixgbe_mac_82598EB) { 2387 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) { 2388 PMD_INIT_LOG(ERR, 2389 "Neither VT nor DCB are enabled, " 2390 "nb_tx_q > %d.", 2391 IXGBE_NONE_MODE_TX_NB_QUEUES); 2392 return -EINVAL; 2393 } 2394 } 2395 } 2396 return 0; 2397 } 2398 2399 static int 2400 ixgbe_dev_configure(struct rte_eth_dev *dev) 2401 { 2402 struct ixgbe_interrupt *intr = 2403 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2404 struct ixgbe_adapter *adapter = 2405 (struct ixgbe_adapter *)dev->data->dev_private; 2406 int ret; 2407 2408 PMD_INIT_FUNC_TRACE(); 2409 /* multipe queue mode checking */ 2410 ret = ixgbe_check_mq_mode(dev); 2411 if (ret != 0) { 2412 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.", 2413 ret); 2414 return ret; 2415 } 2416 2417 /* set flag to update link status after init */ 2418 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2419 2420 /* 2421 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 2422 * allocation or vector Rx preconditions we will reset it. 2423 */ 2424 adapter->rx_bulk_alloc_allowed = true; 2425 adapter->rx_vec_allowed = true; 2426 2427 return 0; 2428 } 2429 2430 static void 2431 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) 2432 { 2433 struct ixgbe_hw *hw = 2434 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2435 struct ixgbe_interrupt *intr = 2436 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2437 uint32_t gpie; 2438 2439 /* only set up it on X550EM_X */ 2440 if (hw->mac.type == ixgbe_mac_X550EM_x) { 2441 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 2442 gpie |= IXGBE_SDP0_GPIEN_X550EM_x; 2443 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 2444 if (hw->phy.type == ixgbe_phy_x550em_ext_t) 2445 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x; 2446 } 2447 } 2448 2449 int 2450 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 2451 uint16_t tx_rate, uint64_t q_msk) 2452 { 2453 struct ixgbe_hw *hw; 2454 struct ixgbe_vf_info *vfinfo; 2455 struct rte_eth_link link; 2456 uint8_t nb_q_per_pool; 2457 uint32_t queue_stride; 2458 uint32_t queue_idx, idx = 0, vf_idx; 2459 uint32_t queue_end; 2460 uint16_t total_rate = 0; 2461 struct rte_pci_device *pci_dev; 2462 2463 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2464 rte_eth_link_get_nowait(dev->data->port_id, &link); 2465 2466 if (vf >= pci_dev->max_vfs) 2467 return -EINVAL; 2468 2469 if (tx_rate > link.link_speed) 2470 return -EINVAL; 2471 2472 if (q_msk == 0) 2473 return 0; 2474 2475 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2476 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 2477 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2478 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2479 queue_idx = vf * queue_stride; 2480 queue_end = queue_idx + nb_q_per_pool - 1; 2481 if (queue_end >= hw->mac.max_tx_queues) 2482 return -EINVAL; 2483 2484 if (vfinfo) { 2485 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) { 2486 if (vf_idx == vf) 2487 continue; 2488 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate); 2489 idx++) 2490 total_rate += vfinfo[vf_idx].tx_rate[idx]; 2491 } 2492 } else { 2493 return -EINVAL; 2494 } 2495 2496 /* Store tx_rate for this vf. */ 2497 for (idx = 0; idx < nb_q_per_pool; idx++) { 2498 if (((uint64_t)0x1 << idx) & q_msk) { 2499 if (vfinfo[vf].tx_rate[idx] != tx_rate) 2500 vfinfo[vf].tx_rate[idx] = tx_rate; 2501 total_rate += tx_rate; 2502 } 2503 } 2504 2505 if (total_rate > dev->data->dev_link.link_speed) { 2506 /* Reset stored TX rate of the VF if it causes exceed 2507 * link speed. 2508 */ 2509 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate)); 2510 return -EINVAL; 2511 } 2512 2513 /* Set RTTBCNRC of each queue/pool for vf X */ 2514 for (; queue_idx <= queue_end; queue_idx++) { 2515 if (0x1 & q_msk) 2516 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate); 2517 q_msk = q_msk >> 1; 2518 } 2519 2520 return 0; 2521 } 2522 2523 /* 2524 * Configure device link speed and setup link. 2525 * It returns 0 on success. 2526 */ 2527 static int 2528 ixgbe_dev_start(struct rte_eth_dev *dev) 2529 { 2530 struct ixgbe_hw *hw = 2531 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2532 struct ixgbe_vf_info *vfinfo = 2533 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2534 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2535 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2536 uint32_t intr_vector = 0; 2537 int err, link_up = 0, negotiate = 0; 2538 uint32_t speed = 0; 2539 uint32_t allowed_speeds = 0; 2540 int mask = 0; 2541 int status; 2542 uint16_t vf, idx; 2543 uint32_t *link_speeds; 2544 struct ixgbe_tm_conf *tm_conf = 2545 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2546 2547 PMD_INIT_FUNC_TRACE(); 2548 2549 /* IXGBE devices don't support: 2550 * - half duplex (checked afterwards for valid speeds) 2551 * - fixed speed: TODO implement 2552 */ 2553 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) { 2554 PMD_INIT_LOG(ERR, 2555 "Invalid link_speeds for port %u, fix speed not supported", 2556 dev->data->port_id); 2557 return -EINVAL; 2558 } 2559 2560 /* disable uio/vfio intr/eventfd mapping */ 2561 rte_intr_disable(intr_handle); 2562 2563 /* stop adapter */ 2564 hw->adapter_stopped = 0; 2565 ixgbe_stop_adapter(hw); 2566 2567 /* reinitialize adapter 2568 * this calls reset and start 2569 */ 2570 status = ixgbe_pf_reset_hw(hw); 2571 if (status != 0) 2572 return -1; 2573 hw->mac.ops.start_hw(hw); 2574 hw->mac.get_link_status = true; 2575 2576 /* configure PF module if SRIOV enabled */ 2577 ixgbe_pf_host_configure(dev); 2578 2579 ixgbe_dev_phy_intr_setup(dev); 2580 2581 /* check and configure queue intr-vector mapping */ 2582 if ((rte_intr_cap_multiple(intr_handle) || 2583 !RTE_ETH_DEV_SRIOV(dev).active) && 2584 dev->data->dev_conf.intr_conf.rxq != 0) { 2585 intr_vector = dev->data->nb_rx_queues; 2586 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) { 2587 PMD_INIT_LOG(ERR, "At most %d intr queues supported", 2588 IXGBE_MAX_INTR_QUEUE_NUM); 2589 return -ENOTSUP; 2590 } 2591 if (rte_intr_efd_enable(intr_handle, intr_vector)) 2592 return -1; 2593 } 2594 2595 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 2596 intr_handle->intr_vec = 2597 rte_zmalloc("intr_vec", 2598 dev->data->nb_rx_queues * sizeof(int), 0); 2599 if (intr_handle->intr_vec == NULL) { 2600 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 2601 " intr_vec", dev->data->nb_rx_queues); 2602 return -ENOMEM; 2603 } 2604 } 2605 2606 /* confiugre msix for sleep until rx interrupt */ 2607 ixgbe_configure_msix(dev); 2608 2609 /* initialize transmission unit */ 2610 ixgbe_dev_tx_init(dev); 2611 2612 /* This can fail when allocating mbufs for descriptor rings */ 2613 err = ixgbe_dev_rx_init(dev); 2614 if (err) { 2615 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 2616 goto error; 2617 } 2618 2619 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 2620 ETH_VLAN_EXTEND_MASK; 2621 err = ixgbe_vlan_offload_config(dev, mask); 2622 if (err) { 2623 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 2624 goto error; 2625 } 2626 2627 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) { 2628 /* Enable vlan filtering for VMDq */ 2629 ixgbe_vmdq_vlan_hw_filter_enable(dev); 2630 } 2631 2632 /* Configure DCB hw */ 2633 ixgbe_configure_dcb(dev); 2634 2635 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) { 2636 err = ixgbe_fdir_configure(dev); 2637 if (err) 2638 goto error; 2639 } 2640 2641 /* Restore vf rate limit */ 2642 if (vfinfo != NULL) { 2643 for (vf = 0; vf < pci_dev->max_vfs; vf++) 2644 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++) 2645 if (vfinfo[vf].tx_rate[idx] != 0) 2646 ixgbe_set_vf_rate_limit( 2647 dev, vf, 2648 vfinfo[vf].tx_rate[idx], 2649 1 << idx); 2650 } 2651 2652 ixgbe_restore_statistics_mapping(dev); 2653 2654 err = ixgbe_dev_rxtx_start(dev); 2655 if (err < 0) { 2656 PMD_INIT_LOG(ERR, "Unable to start rxtx queues"); 2657 goto error; 2658 } 2659 2660 /* Skip link setup if loopback mode is enabled for 82599. */ 2661 if (hw->mac.type == ixgbe_mac_82599EB && 2662 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX) 2663 goto skip_link_setup; 2664 2665 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) { 2666 err = hw->mac.ops.setup_sfp(hw); 2667 if (err) 2668 goto error; 2669 } 2670 2671 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2672 /* Turn on the copper */ 2673 ixgbe_set_phy_power(hw, true); 2674 } else { 2675 /* Turn on the laser */ 2676 ixgbe_enable_tx_laser(hw); 2677 } 2678 2679 err = ixgbe_check_link(hw, &speed, &link_up, 0); 2680 if (err) 2681 goto error; 2682 dev->data->dev_link.link_status = link_up; 2683 2684 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate); 2685 if (err) 2686 goto error; 2687 2688 switch (hw->mac.type) { 2689 case ixgbe_mac_X550: 2690 case ixgbe_mac_X550EM_x: 2691 case ixgbe_mac_X550EM_a: 2692 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2693 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G | 2694 ETH_LINK_SPEED_10G; 2695 break; 2696 default: 2697 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2698 ETH_LINK_SPEED_10G; 2699 } 2700 2701 link_speeds = &dev->data->dev_conf.link_speeds; 2702 if (*link_speeds & ~allowed_speeds) { 2703 PMD_INIT_LOG(ERR, "Invalid link setting"); 2704 goto error; 2705 } 2706 2707 speed = 0x0; 2708 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) { 2709 switch (hw->mac.type) { 2710 case ixgbe_mac_82598EB: 2711 speed = IXGBE_LINK_SPEED_82598_AUTONEG; 2712 break; 2713 case ixgbe_mac_82599EB: 2714 case ixgbe_mac_X540: 2715 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2716 break; 2717 case ixgbe_mac_X550: 2718 case ixgbe_mac_X550EM_x: 2719 case ixgbe_mac_X550EM_a: 2720 speed = IXGBE_LINK_SPEED_X550_AUTONEG; 2721 break; 2722 default: 2723 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2724 } 2725 } else { 2726 if (*link_speeds & ETH_LINK_SPEED_10G) 2727 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2728 if (*link_speeds & ETH_LINK_SPEED_5G) 2729 speed |= IXGBE_LINK_SPEED_5GB_FULL; 2730 if (*link_speeds & ETH_LINK_SPEED_2_5G) 2731 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 2732 if (*link_speeds & ETH_LINK_SPEED_1G) 2733 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2734 if (*link_speeds & ETH_LINK_SPEED_100M) 2735 speed |= IXGBE_LINK_SPEED_100_FULL; 2736 } 2737 2738 err = ixgbe_setup_link(hw, speed, link_up); 2739 if (err) 2740 goto error; 2741 2742 ixgbe_dev_link_update(dev, 0); 2743 2744 skip_link_setup: 2745 2746 if (rte_intr_allow_others(intr_handle)) { 2747 /* check if lsc interrupt is enabled */ 2748 if (dev->data->dev_conf.intr_conf.lsc != 0) 2749 ixgbe_dev_lsc_interrupt_setup(dev, TRUE); 2750 else 2751 ixgbe_dev_lsc_interrupt_setup(dev, FALSE); 2752 ixgbe_dev_macsec_interrupt_setup(dev); 2753 } else { 2754 rte_intr_callback_unregister(intr_handle, 2755 ixgbe_dev_interrupt_handler, dev); 2756 if (dev->data->dev_conf.intr_conf.lsc != 0) 2757 PMD_INIT_LOG(INFO, "lsc won't enable because of" 2758 " no intr multiplex"); 2759 } 2760 2761 /* check if rxq interrupt is enabled */ 2762 if (dev->data->dev_conf.intr_conf.rxq != 0 && 2763 rte_intr_dp_is_en(intr_handle)) 2764 ixgbe_dev_rxq_interrupt_setup(dev); 2765 2766 /* enable uio/vfio intr/eventfd mapping */ 2767 rte_intr_enable(intr_handle); 2768 2769 /* resume enabled intr since hw reset */ 2770 ixgbe_enable_intr(dev); 2771 ixgbe_l2_tunnel_conf(dev); 2772 ixgbe_filter_restore(dev); 2773 2774 if (tm_conf->root && !tm_conf->committed) 2775 PMD_DRV_LOG(WARNING, 2776 "please call hierarchy_commit() " 2777 "before starting the port"); 2778 2779 return 0; 2780 2781 error: 2782 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err); 2783 ixgbe_dev_clear_queues(dev); 2784 return -EIO; 2785 } 2786 2787 /* 2788 * Stop device: disable rx and tx functions to allow for reconfiguring. 2789 */ 2790 static void 2791 ixgbe_dev_stop(struct rte_eth_dev *dev) 2792 { 2793 struct rte_eth_link link; 2794 struct ixgbe_hw *hw = 2795 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2796 struct ixgbe_vf_info *vfinfo = 2797 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2798 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2799 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2800 int vf; 2801 struct ixgbe_tm_conf *tm_conf = 2802 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2803 2804 PMD_INIT_FUNC_TRACE(); 2805 2806 /* disable interrupts */ 2807 ixgbe_disable_intr(hw); 2808 2809 /* reset the NIC */ 2810 ixgbe_pf_reset_hw(hw); 2811 hw->adapter_stopped = 0; 2812 2813 /* stop adapter */ 2814 ixgbe_stop_adapter(hw); 2815 2816 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++) 2817 vfinfo[vf].clear_to_send = false; 2818 2819 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2820 /* Turn off the copper */ 2821 ixgbe_set_phy_power(hw, false); 2822 } else { 2823 /* Turn off the laser */ 2824 ixgbe_disable_tx_laser(hw); 2825 } 2826 2827 ixgbe_dev_clear_queues(dev); 2828 2829 /* Clear stored conf */ 2830 dev->data->scattered_rx = 0; 2831 dev->data->lro = 0; 2832 2833 /* Clear recorded link status */ 2834 memset(&link, 0, sizeof(link)); 2835 rte_eth_linkstatus_set(dev, &link); 2836 2837 if (!rte_intr_allow_others(intr_handle)) 2838 /* resume to the default handler */ 2839 rte_intr_callback_register(intr_handle, 2840 ixgbe_dev_interrupt_handler, 2841 (void *)dev); 2842 2843 /* Clean datapath event and queue/vec mapping */ 2844 rte_intr_efd_disable(intr_handle); 2845 if (intr_handle->intr_vec != NULL) { 2846 rte_free(intr_handle->intr_vec); 2847 intr_handle->intr_vec = NULL; 2848 } 2849 2850 /* reset hierarchy commit */ 2851 tm_conf->committed = false; 2852 } 2853 2854 /* 2855 * Set device link up: enable tx. 2856 */ 2857 static int 2858 ixgbe_dev_set_link_up(struct rte_eth_dev *dev) 2859 { 2860 struct ixgbe_hw *hw = 2861 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2862 if (hw->mac.type == ixgbe_mac_82599EB) { 2863 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2864 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2865 /* Not suported in bypass mode */ 2866 PMD_INIT_LOG(ERR, "Set link up is not supported " 2867 "by device id 0x%x", hw->device_id); 2868 return -ENOTSUP; 2869 } 2870 #endif 2871 } 2872 2873 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2874 /* Turn on the copper */ 2875 ixgbe_set_phy_power(hw, true); 2876 } else { 2877 /* Turn on the laser */ 2878 ixgbe_enable_tx_laser(hw); 2879 } 2880 2881 return 0; 2882 } 2883 2884 /* 2885 * Set device link down: disable tx. 2886 */ 2887 static int 2888 ixgbe_dev_set_link_down(struct rte_eth_dev *dev) 2889 { 2890 struct ixgbe_hw *hw = 2891 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2892 if (hw->mac.type == ixgbe_mac_82599EB) { 2893 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2894 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2895 /* Not suported in bypass mode */ 2896 PMD_INIT_LOG(ERR, "Set link down is not supported " 2897 "by device id 0x%x", hw->device_id); 2898 return -ENOTSUP; 2899 } 2900 #endif 2901 } 2902 2903 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2904 /* Turn off the copper */ 2905 ixgbe_set_phy_power(hw, false); 2906 } else { 2907 /* Turn off the laser */ 2908 ixgbe_disable_tx_laser(hw); 2909 } 2910 2911 return 0; 2912 } 2913 2914 /* 2915 * Reset and stop device. 2916 */ 2917 static void 2918 ixgbe_dev_close(struct rte_eth_dev *dev) 2919 { 2920 struct ixgbe_hw *hw = 2921 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2922 2923 PMD_INIT_FUNC_TRACE(); 2924 2925 ixgbe_pf_reset_hw(hw); 2926 2927 ixgbe_dev_stop(dev); 2928 hw->adapter_stopped = 1; 2929 2930 ixgbe_dev_free_queues(dev); 2931 2932 ixgbe_disable_pcie_master(hw); 2933 2934 /* reprogram the RAR[0] in case user changed it. */ 2935 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2936 } 2937 2938 /* 2939 * Reset PF device. 2940 */ 2941 static int 2942 ixgbe_dev_reset(struct rte_eth_dev *dev) 2943 { 2944 int ret; 2945 2946 /* When a DPDK PMD PF begin to reset PF port, it should notify all 2947 * its VF to make them align with it. The detailed notification 2948 * mechanism is PMD specific. As to ixgbe PF, it is rather complex. 2949 * To avoid unexpected behavior in VF, currently reset of PF with 2950 * SR-IOV activation is not supported. It might be supported later. 2951 */ 2952 if (dev->data->sriov.active) 2953 return -ENOTSUP; 2954 2955 ret = eth_ixgbe_dev_uninit(dev); 2956 if (ret) 2957 return ret; 2958 2959 ret = eth_ixgbe_dev_init(dev, NULL); 2960 2961 return ret; 2962 } 2963 2964 static void 2965 ixgbe_read_stats_registers(struct ixgbe_hw *hw, 2966 struct ixgbe_hw_stats *hw_stats, 2967 struct ixgbe_macsec_stats *macsec_stats, 2968 uint64_t *total_missed_rx, uint64_t *total_qbrc, 2969 uint64_t *total_qprc, uint64_t *total_qprdc) 2970 { 2971 uint32_t bprc, lxon, lxoff, total; 2972 uint32_t delta_gprc = 0; 2973 unsigned i; 2974 /* Workaround for RX byte count not including CRC bytes when CRC 2975 * strip is enabled. CRC bytes are removed from counters when crc_strip 2976 * is disabled. 2977 */ 2978 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) & 2979 IXGBE_HLREG0_RXCRCSTRP); 2980 2981 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 2982 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC); 2983 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC); 2984 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC); 2985 2986 for (i = 0; i < 8; i++) { 2987 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 2988 2989 /* global total per queue */ 2990 hw_stats->mpc[i] += mp; 2991 /* Running comprehensive total for stats display */ 2992 *total_missed_rx += hw_stats->mpc[i]; 2993 if (hw->mac.type == ixgbe_mac_82598EB) { 2994 hw_stats->rnbc[i] += 2995 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 2996 hw_stats->pxonrxc[i] += 2997 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 2998 hw_stats->pxoffrxc[i] += 2999 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 3000 } else { 3001 hw_stats->pxonrxc[i] += 3002 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 3003 hw_stats->pxoffrxc[i] += 3004 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 3005 hw_stats->pxon2offc[i] += 3006 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 3007 } 3008 hw_stats->pxontxc[i] += 3009 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 3010 hw_stats->pxofftxc[i] += 3011 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 3012 } 3013 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3014 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 3015 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 3016 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 3017 3018 delta_gprc += delta_qprc; 3019 3020 hw_stats->qprc[i] += delta_qprc; 3021 hw_stats->qptc[i] += delta_qptc; 3022 3023 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 3024 hw_stats->qbrc[i] += 3025 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32); 3026 if (crc_strip == 0) 3027 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN; 3028 3029 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 3030 hw_stats->qbtc[i] += 3031 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32); 3032 3033 hw_stats->qprdc[i] += delta_qprdc; 3034 *total_qprdc += hw_stats->qprdc[i]; 3035 3036 *total_qprc += hw_stats->qprc[i]; 3037 *total_qbrc += hw_stats->qbrc[i]; 3038 } 3039 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC); 3040 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC); 3041 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 3042 3043 /* 3044 * An errata states that gprc actually counts good + missed packets: 3045 * Workaround to set gprc to summated queue packet receives 3046 */ 3047 hw_stats->gprc = *total_qprc; 3048 3049 if (hw->mac.type != ixgbe_mac_82598EB) { 3050 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 3051 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32); 3052 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 3053 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32); 3054 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 3055 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32); 3056 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 3057 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 3058 } else { 3059 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 3060 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 3061 /* 82598 only has a counter in the high register */ 3062 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 3063 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 3064 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 3065 } 3066 uint64_t old_tpr = hw_stats->tpr; 3067 3068 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 3069 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT); 3070 3071 if (crc_strip == 0) 3072 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN; 3073 3074 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC); 3075 hw_stats->gptc += delta_gptc; 3076 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN; 3077 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN; 3078 3079 /* 3080 * Workaround: mprc hardware is incorrectly counting 3081 * broadcasts, so for now we subtract those. 3082 */ 3083 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 3084 hw_stats->bprc += bprc; 3085 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 3086 if (hw->mac.type == ixgbe_mac_82598EB) 3087 hw_stats->mprc -= bprc; 3088 3089 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 3090 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 3091 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 3092 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 3093 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 3094 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 3095 3096 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 3097 hw_stats->lxontxc += lxon; 3098 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 3099 hw_stats->lxofftxc += lxoff; 3100 total = lxon + lxoff; 3101 3102 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 3103 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 3104 hw_stats->gptc -= total; 3105 hw_stats->mptc -= total; 3106 hw_stats->ptc64 -= total; 3107 hw_stats->gotc -= total * ETHER_MIN_LEN; 3108 3109 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 3110 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 3111 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 3112 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 3113 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC); 3114 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC); 3115 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC); 3116 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 3117 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 3118 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 3119 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 3120 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 3121 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 3122 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC); 3123 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 3124 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST); 3125 /* Only read FCOE on 82599 */ 3126 if (hw->mac.type != ixgbe_mac_82598EB) { 3127 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 3128 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 3129 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 3130 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 3131 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 3132 } 3133 3134 /* Flow Director Stats registers */ 3135 if (hw->mac.type != ixgbe_mac_82598EB) { 3136 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 3137 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 3138 hw_stats->fdirustat_add += IXGBE_READ_REG(hw, 3139 IXGBE_FDIRUSTAT) & 0xFFFF; 3140 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw, 3141 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF; 3142 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw, 3143 IXGBE_FDIRFSTAT) & 0xFFFF; 3144 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw, 3145 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF; 3146 } 3147 /* MACsec Stats registers */ 3148 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT); 3149 macsec_stats->out_pkts_encrypted += 3150 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE); 3151 macsec_stats->out_pkts_protected += 3152 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP); 3153 macsec_stats->out_octets_encrypted += 3154 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE); 3155 macsec_stats->out_octets_protected += 3156 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP); 3157 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT); 3158 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD); 3159 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI); 3160 macsec_stats->in_pkts_unknownsci += 3161 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI); 3162 macsec_stats->in_octets_decrypted += 3163 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD); 3164 macsec_stats->in_octets_validated += 3165 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV); 3166 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH); 3167 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY); 3168 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE); 3169 for (i = 0; i < 2; i++) { 3170 macsec_stats->in_pkts_ok += 3171 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i)); 3172 macsec_stats->in_pkts_invalid += 3173 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i)); 3174 macsec_stats->in_pkts_notvalid += 3175 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i)); 3176 } 3177 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA); 3178 macsec_stats->in_pkts_notusingsa += 3179 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA); 3180 } 3181 3182 /* 3183 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c 3184 */ 3185 static int 3186 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3187 { 3188 struct ixgbe_hw *hw = 3189 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3190 struct ixgbe_hw_stats *hw_stats = 3191 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3192 struct ixgbe_macsec_stats *macsec_stats = 3193 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3194 dev->data->dev_private); 3195 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3196 unsigned i; 3197 3198 total_missed_rx = 0; 3199 total_qbrc = 0; 3200 total_qprc = 0; 3201 total_qprdc = 0; 3202 3203 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3204 &total_qbrc, &total_qprc, &total_qprdc); 3205 3206 if (stats == NULL) 3207 return -EINVAL; 3208 3209 /* Fill out the rte_eth_stats statistics structure */ 3210 stats->ipackets = total_qprc; 3211 stats->ibytes = total_qbrc; 3212 stats->opackets = hw_stats->gptc; 3213 stats->obytes = hw_stats->gotc; 3214 3215 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3216 stats->q_ipackets[i] = hw_stats->qprc[i]; 3217 stats->q_opackets[i] = hw_stats->qptc[i]; 3218 stats->q_ibytes[i] = hw_stats->qbrc[i]; 3219 stats->q_obytes[i] = hw_stats->qbtc[i]; 3220 stats->q_errors[i] = hw_stats->qprdc[i]; 3221 } 3222 3223 /* Rx Errors */ 3224 stats->imissed = total_missed_rx; 3225 stats->ierrors = hw_stats->crcerrs + 3226 hw_stats->mspdc + 3227 hw_stats->rlec + 3228 hw_stats->ruc + 3229 hw_stats->roc + 3230 hw_stats->illerrc + 3231 hw_stats->errbc + 3232 hw_stats->rfc + 3233 hw_stats->fccrc + 3234 hw_stats->fclast; 3235 3236 /* Tx Errors */ 3237 stats->oerrors = 0; 3238 return 0; 3239 } 3240 3241 static void 3242 ixgbe_dev_stats_reset(struct rte_eth_dev *dev) 3243 { 3244 struct ixgbe_hw_stats *stats = 3245 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3246 3247 /* HW registers are cleared on read */ 3248 ixgbe_dev_stats_get(dev, NULL); 3249 3250 /* Reset software totals */ 3251 memset(stats, 0, sizeof(*stats)); 3252 } 3253 3254 /* This function calculates the number of xstats based on the current config */ 3255 static unsigned 3256 ixgbe_xstats_calc_num(void) { 3257 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS + 3258 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) + 3259 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES); 3260 } 3261 3262 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3263 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size) 3264 { 3265 const unsigned cnt_stats = ixgbe_xstats_calc_num(); 3266 unsigned stat, i, count; 3267 3268 if (xstats_names != NULL) { 3269 count = 0; 3270 3271 /* Note: limit >= cnt_stats checked upstream 3272 * in rte_eth_xstats_names() 3273 */ 3274 3275 /* Extended stats from ixgbe_hw_stats */ 3276 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3277 snprintf(xstats_names[count].name, 3278 sizeof(xstats_names[count].name), 3279 "%s", 3280 rte_ixgbe_stats_strings[i].name); 3281 count++; 3282 } 3283 3284 /* MACsec Stats */ 3285 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3286 snprintf(xstats_names[count].name, 3287 sizeof(xstats_names[count].name), 3288 "%s", 3289 rte_ixgbe_macsec_strings[i].name); 3290 count++; 3291 } 3292 3293 /* RX Priority Stats */ 3294 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3295 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3296 snprintf(xstats_names[count].name, 3297 sizeof(xstats_names[count].name), 3298 "rx_priority%u_%s", i, 3299 rte_ixgbe_rxq_strings[stat].name); 3300 count++; 3301 } 3302 } 3303 3304 /* TX Priority Stats */ 3305 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3306 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3307 snprintf(xstats_names[count].name, 3308 sizeof(xstats_names[count].name), 3309 "tx_priority%u_%s", i, 3310 rte_ixgbe_txq_strings[stat].name); 3311 count++; 3312 } 3313 } 3314 } 3315 return cnt_stats; 3316 } 3317 3318 static int ixgbe_dev_xstats_get_names_by_id( 3319 struct rte_eth_dev *dev, 3320 struct rte_eth_xstat_name *xstats_names, 3321 const uint64_t *ids, 3322 unsigned int limit) 3323 { 3324 if (!ids) { 3325 const unsigned int cnt_stats = ixgbe_xstats_calc_num(); 3326 unsigned int stat, i, count; 3327 3328 if (xstats_names != NULL) { 3329 count = 0; 3330 3331 /* Note: limit >= cnt_stats checked upstream 3332 * in rte_eth_xstats_names() 3333 */ 3334 3335 /* Extended stats from ixgbe_hw_stats */ 3336 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3337 snprintf(xstats_names[count].name, 3338 sizeof(xstats_names[count].name), 3339 "%s", 3340 rte_ixgbe_stats_strings[i].name); 3341 count++; 3342 } 3343 3344 /* MACsec Stats */ 3345 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3346 snprintf(xstats_names[count].name, 3347 sizeof(xstats_names[count].name), 3348 "%s", 3349 rte_ixgbe_macsec_strings[i].name); 3350 count++; 3351 } 3352 3353 /* RX Priority Stats */ 3354 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3355 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3356 snprintf(xstats_names[count].name, 3357 sizeof(xstats_names[count].name), 3358 "rx_priority%u_%s", i, 3359 rte_ixgbe_rxq_strings[stat].name); 3360 count++; 3361 } 3362 } 3363 3364 /* TX Priority Stats */ 3365 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3366 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3367 snprintf(xstats_names[count].name, 3368 sizeof(xstats_names[count].name), 3369 "tx_priority%u_%s", i, 3370 rte_ixgbe_txq_strings[stat].name); 3371 count++; 3372 } 3373 } 3374 } 3375 return cnt_stats; 3376 } 3377 3378 uint16_t i; 3379 uint16_t size = ixgbe_xstats_calc_num(); 3380 struct rte_eth_xstat_name xstats_names_copy[size]; 3381 3382 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL, 3383 size); 3384 3385 for (i = 0; i < limit; i++) { 3386 if (ids[i] >= size) { 3387 PMD_INIT_LOG(ERR, "id value isn't valid"); 3388 return -1; 3389 } 3390 strcpy(xstats_names[i].name, 3391 xstats_names_copy[ids[i]].name); 3392 } 3393 return limit; 3394 } 3395 3396 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3397 struct rte_eth_xstat_name *xstats_names, unsigned limit) 3398 { 3399 unsigned i; 3400 3401 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL) 3402 return -ENOMEM; 3403 3404 if (xstats_names != NULL) 3405 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) 3406 snprintf(xstats_names[i].name, 3407 sizeof(xstats_names[i].name), 3408 "%s", rte_ixgbevf_stats_strings[i].name); 3409 return IXGBEVF_NB_XSTATS; 3410 } 3411 3412 static int 3413 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3414 unsigned n) 3415 { 3416 struct ixgbe_hw *hw = 3417 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3418 struct ixgbe_hw_stats *hw_stats = 3419 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3420 struct ixgbe_macsec_stats *macsec_stats = 3421 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3422 dev->data->dev_private); 3423 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3424 unsigned i, stat, count = 0; 3425 3426 count = ixgbe_xstats_calc_num(); 3427 3428 if (n < count) 3429 return count; 3430 3431 total_missed_rx = 0; 3432 total_qbrc = 0; 3433 total_qprc = 0; 3434 total_qprdc = 0; 3435 3436 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3437 &total_qbrc, &total_qprc, &total_qprdc); 3438 3439 /* If this is a reset xstats is NULL, and we have cleared the 3440 * registers by reading them. 3441 */ 3442 if (!xstats) 3443 return 0; 3444 3445 /* Extended stats from ixgbe_hw_stats */ 3446 count = 0; 3447 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3448 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3449 rte_ixgbe_stats_strings[i].offset); 3450 xstats[count].id = count; 3451 count++; 3452 } 3453 3454 /* MACsec Stats */ 3455 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3456 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) + 3457 rte_ixgbe_macsec_strings[i].offset); 3458 xstats[count].id = count; 3459 count++; 3460 } 3461 3462 /* RX Priority Stats */ 3463 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3464 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3465 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3466 rte_ixgbe_rxq_strings[stat].offset + 3467 (sizeof(uint64_t) * i)); 3468 xstats[count].id = count; 3469 count++; 3470 } 3471 } 3472 3473 /* TX Priority Stats */ 3474 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3475 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3476 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3477 rte_ixgbe_txq_strings[stat].offset + 3478 (sizeof(uint64_t) * i)); 3479 xstats[count].id = count; 3480 count++; 3481 } 3482 } 3483 return count; 3484 } 3485 3486 static int 3487 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 3488 uint64_t *values, unsigned int n) 3489 { 3490 if (!ids) { 3491 struct ixgbe_hw *hw = 3492 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3493 struct ixgbe_hw_stats *hw_stats = 3494 IXGBE_DEV_PRIVATE_TO_STATS( 3495 dev->data->dev_private); 3496 struct ixgbe_macsec_stats *macsec_stats = 3497 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3498 dev->data->dev_private); 3499 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3500 unsigned int i, stat, count = 0; 3501 3502 count = ixgbe_xstats_calc_num(); 3503 3504 if (!ids && n < count) 3505 return count; 3506 3507 total_missed_rx = 0; 3508 total_qbrc = 0; 3509 total_qprc = 0; 3510 total_qprdc = 0; 3511 3512 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, 3513 &total_missed_rx, &total_qbrc, &total_qprc, 3514 &total_qprdc); 3515 3516 /* If this is a reset xstats is NULL, and we have cleared the 3517 * registers by reading them. 3518 */ 3519 if (!ids && !values) 3520 return 0; 3521 3522 /* Extended stats from ixgbe_hw_stats */ 3523 count = 0; 3524 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3525 values[count] = *(uint64_t *)(((char *)hw_stats) + 3526 rte_ixgbe_stats_strings[i].offset); 3527 count++; 3528 } 3529 3530 /* MACsec Stats */ 3531 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3532 values[count] = *(uint64_t *)(((char *)macsec_stats) + 3533 rte_ixgbe_macsec_strings[i].offset); 3534 count++; 3535 } 3536 3537 /* RX Priority Stats */ 3538 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3539 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3540 values[count] = 3541 *(uint64_t *)(((char *)hw_stats) + 3542 rte_ixgbe_rxq_strings[stat].offset + 3543 (sizeof(uint64_t) * i)); 3544 count++; 3545 } 3546 } 3547 3548 /* TX Priority Stats */ 3549 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3550 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3551 values[count] = 3552 *(uint64_t *)(((char *)hw_stats) + 3553 rte_ixgbe_txq_strings[stat].offset + 3554 (sizeof(uint64_t) * i)); 3555 count++; 3556 } 3557 } 3558 return count; 3559 } 3560 3561 uint16_t i; 3562 uint16_t size = ixgbe_xstats_calc_num(); 3563 uint64_t values_copy[size]; 3564 3565 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size); 3566 3567 for (i = 0; i < n; i++) { 3568 if (ids[i] >= size) { 3569 PMD_INIT_LOG(ERR, "id value isn't valid"); 3570 return -1; 3571 } 3572 values[i] = values_copy[ids[i]]; 3573 } 3574 return n; 3575 } 3576 3577 static void 3578 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev) 3579 { 3580 struct ixgbe_hw_stats *stats = 3581 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3582 struct ixgbe_macsec_stats *macsec_stats = 3583 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3584 dev->data->dev_private); 3585 3586 unsigned count = ixgbe_xstats_calc_num(); 3587 3588 /* HW registers are cleared on read */ 3589 ixgbe_dev_xstats_get(dev, NULL, count); 3590 3591 /* Reset software totals */ 3592 memset(stats, 0, sizeof(*stats)); 3593 memset(macsec_stats, 0, sizeof(*macsec_stats)); 3594 } 3595 3596 static void 3597 ixgbevf_update_stats(struct rte_eth_dev *dev) 3598 { 3599 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3600 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3601 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3602 3603 /* Good Rx packet, include VF loopback */ 3604 UPDATE_VF_STAT(IXGBE_VFGPRC, 3605 hw_stats->last_vfgprc, hw_stats->vfgprc); 3606 3607 /* Good Rx octets, include VF loopback */ 3608 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB, 3609 hw_stats->last_vfgorc, hw_stats->vfgorc); 3610 3611 /* Good Tx packet, include VF loopback */ 3612 UPDATE_VF_STAT(IXGBE_VFGPTC, 3613 hw_stats->last_vfgptc, hw_stats->vfgptc); 3614 3615 /* Good Tx octets, include VF loopback */ 3616 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB, 3617 hw_stats->last_vfgotc, hw_stats->vfgotc); 3618 3619 /* Rx Multicst Packet */ 3620 UPDATE_VF_STAT(IXGBE_VFMPRC, 3621 hw_stats->last_vfmprc, hw_stats->vfmprc); 3622 } 3623 3624 static int 3625 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3626 unsigned n) 3627 { 3628 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3629 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3630 unsigned i; 3631 3632 if (n < IXGBEVF_NB_XSTATS) 3633 return IXGBEVF_NB_XSTATS; 3634 3635 ixgbevf_update_stats(dev); 3636 3637 if (!xstats) 3638 return 0; 3639 3640 /* Extended stats */ 3641 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) { 3642 xstats[i].id = i; 3643 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + 3644 rte_ixgbevf_stats_strings[i].offset); 3645 } 3646 3647 return IXGBEVF_NB_XSTATS; 3648 } 3649 3650 static int 3651 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3652 { 3653 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3654 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3655 3656 ixgbevf_update_stats(dev); 3657 3658 if (stats == NULL) 3659 return -EINVAL; 3660 3661 stats->ipackets = hw_stats->vfgprc; 3662 stats->ibytes = hw_stats->vfgorc; 3663 stats->opackets = hw_stats->vfgptc; 3664 stats->obytes = hw_stats->vfgotc; 3665 return 0; 3666 } 3667 3668 static void 3669 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev) 3670 { 3671 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3672 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3673 3674 /* Sync HW register to the last stats */ 3675 ixgbevf_dev_stats_get(dev, NULL); 3676 3677 /* reset HW current stats*/ 3678 hw_stats->vfgprc = 0; 3679 hw_stats->vfgorc = 0; 3680 hw_stats->vfgptc = 0; 3681 hw_stats->vfgotc = 0; 3682 } 3683 3684 static int 3685 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 3686 { 3687 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3688 u16 eeprom_verh, eeprom_verl; 3689 u32 etrack_id; 3690 int ret; 3691 3692 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh); 3693 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl); 3694 3695 etrack_id = (eeprom_verh << 16) | eeprom_verl; 3696 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id); 3697 3698 ret += 1; /* add the size of '\0' */ 3699 if (fw_size < (u32)ret) 3700 return ret; 3701 else 3702 return 0; 3703 } 3704 3705 static void 3706 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3707 { 3708 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3709 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3710 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 3711 3712 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3713 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3714 if (RTE_ETH_DEV_SRIOV(dev).active == 0) { 3715 /* 3716 * When DCB/VT is off, maximum number of queues changes, 3717 * except for 82598EB, which remains constant. 3718 */ 3719 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 3720 hw->mac.type != ixgbe_mac_82598EB) 3721 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES; 3722 } 3723 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */ 3724 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */ 3725 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3726 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3727 dev_info->max_vfs = pci_dev->max_vfs; 3728 if (hw->mac.type == ixgbe_mac_82598EB) 3729 dev_info->max_vmdq_pools = ETH_16_POOLS; 3730 else 3731 dev_info->max_vmdq_pools = ETH_64_POOLS; 3732 dev_info->vmdq_queue_num = dev_info->max_rx_queues; 3733 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3734 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3735 dev_info->rx_queue_offload_capa); 3736 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3737 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3738 3739 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3740 .rx_thresh = { 3741 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3742 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3743 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3744 }, 3745 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3746 .rx_drop_en = 0, 3747 .offloads = 0, 3748 }; 3749 3750 dev_info->default_txconf = (struct rte_eth_txconf) { 3751 .tx_thresh = { 3752 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3753 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3754 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3755 }, 3756 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3757 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3758 .offloads = 0, 3759 }; 3760 3761 dev_info->rx_desc_lim = rx_desc_lim; 3762 dev_info->tx_desc_lim = tx_desc_lim; 3763 3764 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 3765 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 3766 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 3767 3768 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 3769 if (hw->mac.type == ixgbe_mac_X540 || 3770 hw->mac.type == ixgbe_mac_X540_vf || 3771 hw->mac.type == ixgbe_mac_X550 || 3772 hw->mac.type == ixgbe_mac_X550_vf) { 3773 dev_info->speed_capa |= ETH_LINK_SPEED_100M; 3774 } 3775 if (hw->mac.type == ixgbe_mac_X550) { 3776 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G; 3777 dev_info->speed_capa |= ETH_LINK_SPEED_5G; 3778 } 3779 3780 /* Driver-preferred Rx/Tx parameters */ 3781 dev_info->default_rxportconf.burst_size = 32; 3782 dev_info->default_txportconf.burst_size = 32; 3783 dev_info->default_rxportconf.nb_queues = 1; 3784 dev_info->default_txportconf.nb_queues = 1; 3785 dev_info->default_rxportconf.ring_size = 256; 3786 dev_info->default_txportconf.ring_size = 256; 3787 } 3788 3789 static const uint32_t * 3790 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 3791 { 3792 static const uint32_t ptypes[] = { 3793 /* For non-vec functions, 3794 * refers to ixgbe_rxd_pkt_info_to_pkt_type(); 3795 * for vec functions, 3796 * refers to _recv_raw_pkts_vec(). 3797 */ 3798 RTE_PTYPE_L2_ETHER, 3799 RTE_PTYPE_L3_IPV4, 3800 RTE_PTYPE_L3_IPV4_EXT, 3801 RTE_PTYPE_L3_IPV6, 3802 RTE_PTYPE_L3_IPV6_EXT, 3803 RTE_PTYPE_L4_SCTP, 3804 RTE_PTYPE_L4_TCP, 3805 RTE_PTYPE_L4_UDP, 3806 RTE_PTYPE_TUNNEL_IP, 3807 RTE_PTYPE_INNER_L3_IPV6, 3808 RTE_PTYPE_INNER_L3_IPV6_EXT, 3809 RTE_PTYPE_INNER_L4_TCP, 3810 RTE_PTYPE_INNER_L4_UDP, 3811 RTE_PTYPE_UNKNOWN 3812 }; 3813 3814 if (dev->rx_pkt_burst == ixgbe_recv_pkts || 3815 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc || 3816 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc || 3817 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc) 3818 return ptypes; 3819 3820 #if defined(RTE_ARCH_X86) 3821 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec || 3822 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec) 3823 return ptypes; 3824 #endif 3825 return NULL; 3826 } 3827 3828 static void 3829 ixgbevf_dev_info_get(struct rte_eth_dev *dev, 3830 struct rte_eth_dev_info *dev_info) 3831 { 3832 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3833 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3834 3835 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3836 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3837 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */ 3838 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */ 3839 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3840 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3841 dev_info->max_vfs = pci_dev->max_vfs; 3842 if (hw->mac.type == ixgbe_mac_82598EB) 3843 dev_info->max_vmdq_pools = ETH_16_POOLS; 3844 else 3845 dev_info->max_vmdq_pools = ETH_64_POOLS; 3846 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3847 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3848 dev_info->rx_queue_offload_capa); 3849 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3850 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3851 3852 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3853 .rx_thresh = { 3854 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3855 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3856 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3857 }, 3858 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3859 .rx_drop_en = 0, 3860 .offloads = 0, 3861 }; 3862 3863 dev_info->default_txconf = (struct rte_eth_txconf) { 3864 .tx_thresh = { 3865 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3866 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3867 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3868 }, 3869 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3870 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3871 .offloads = 0, 3872 }; 3873 3874 dev_info->rx_desc_lim = rx_desc_lim; 3875 dev_info->tx_desc_lim = tx_desc_lim; 3876 } 3877 3878 static int 3879 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3880 int *link_up, int wait_to_complete) 3881 { 3882 /** 3883 * for a quick link status checking, wait_to_compelet == 0, 3884 * skip PF link status checking 3885 */ 3886 bool no_pflink_check = wait_to_complete == 0; 3887 struct ixgbe_mbx_info *mbx = &hw->mbx; 3888 struct ixgbe_mac_info *mac = &hw->mac; 3889 uint32_t links_reg, in_msg; 3890 int ret_val = 0; 3891 3892 /* If we were hit with a reset drop the link */ 3893 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout) 3894 mac->get_link_status = true; 3895 3896 if (!mac->get_link_status) 3897 goto out; 3898 3899 /* if link status is down no point in checking to see if pf is up */ 3900 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 3901 if (!(links_reg & IXGBE_LINKS_UP)) 3902 goto out; 3903 3904 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs 3905 * before the link status is correct 3906 */ 3907 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) { 3908 int i; 3909 3910 for (i = 0; i < 5; i++) { 3911 rte_delay_us(100); 3912 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 3913 3914 if (!(links_reg & IXGBE_LINKS_UP)) 3915 goto out; 3916 } 3917 } 3918 3919 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 3920 case IXGBE_LINKS_SPEED_10G_82599: 3921 *speed = IXGBE_LINK_SPEED_10GB_FULL; 3922 if (hw->mac.type >= ixgbe_mac_X550) { 3923 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 3924 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 3925 } 3926 break; 3927 case IXGBE_LINKS_SPEED_1G_82599: 3928 *speed = IXGBE_LINK_SPEED_1GB_FULL; 3929 break; 3930 case IXGBE_LINKS_SPEED_100_82599: 3931 *speed = IXGBE_LINK_SPEED_100_FULL; 3932 if (hw->mac.type == ixgbe_mac_X550) { 3933 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 3934 *speed = IXGBE_LINK_SPEED_5GB_FULL; 3935 } 3936 break; 3937 case IXGBE_LINKS_SPEED_10_X550EM_A: 3938 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3939 /* Since Reserved in older MAC's */ 3940 if (hw->mac.type >= ixgbe_mac_X550) 3941 *speed = IXGBE_LINK_SPEED_10_FULL; 3942 break; 3943 default: 3944 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3945 } 3946 3947 if (no_pflink_check) { 3948 if (*speed == IXGBE_LINK_SPEED_UNKNOWN) 3949 mac->get_link_status = true; 3950 else 3951 mac->get_link_status = false; 3952 3953 goto out; 3954 } 3955 /* if the read failed it could just be a mailbox collision, best wait 3956 * until we are called again and don't report an error 3957 */ 3958 if (mbx->ops.read(hw, &in_msg, 1, 0)) 3959 goto out; 3960 3961 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) { 3962 /* msg is not CTS and is NACK we must have lost CTS status */ 3963 if (in_msg & IXGBE_VT_MSGTYPE_NACK) 3964 ret_val = -1; 3965 goto out; 3966 } 3967 3968 /* the pf is talking, if we timed out in the past we reinit */ 3969 if (!mbx->timeout) { 3970 ret_val = -1; 3971 goto out; 3972 } 3973 3974 /* if we passed all the tests above then the link is up and we no 3975 * longer need to check for link 3976 */ 3977 mac->get_link_status = false; 3978 3979 out: 3980 *link_up = !mac->get_link_status; 3981 return ret_val; 3982 } 3983 3984 /* return 0 means link status changed, -1 means not changed */ 3985 int 3986 ixgbe_dev_link_update_share(struct rte_eth_dev *dev, 3987 int wait_to_complete, int vf) 3988 { 3989 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3990 struct rte_eth_link link; 3991 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 3992 struct ixgbe_interrupt *intr = 3993 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 3994 int link_up; 3995 int diag; 3996 u32 speed = 0; 3997 int wait = 1; 3998 bool autoneg = false; 3999 4000 memset(&link, 0, sizeof(link)); 4001 link.link_status = ETH_LINK_DOWN; 4002 link.link_speed = ETH_SPEED_NUM_NONE; 4003 link.link_duplex = ETH_LINK_HALF_DUPLEX; 4004 link.link_autoneg = ETH_LINK_AUTONEG; 4005 4006 hw->mac.get_link_status = true; 4007 4008 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) && 4009 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) { 4010 speed = hw->phy.autoneg_advertised; 4011 if (!speed) 4012 ixgbe_get_link_capabilities(hw, &speed, &autoneg); 4013 ixgbe_setup_link(hw, speed, true); 4014 } 4015 4016 /* check if it needs to wait to complete, if lsc interrupt is enabled */ 4017 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0) 4018 wait = 0; 4019 4020 if (vf) 4021 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait); 4022 else 4023 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait); 4024 4025 if (diag != 0) { 4026 link.link_speed = ETH_SPEED_NUM_100M; 4027 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4028 return rte_eth_linkstatus_set(dev, &link); 4029 } 4030 4031 if (link_up == 0) { 4032 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 4033 return rte_eth_linkstatus_set(dev, &link); 4034 } 4035 4036 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 4037 link.link_status = ETH_LINK_UP; 4038 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4039 4040 switch (link_speed) { 4041 default: 4042 case IXGBE_LINK_SPEED_UNKNOWN: 4043 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4044 link.link_speed = ETH_SPEED_NUM_100M; 4045 break; 4046 4047 case IXGBE_LINK_SPEED_100_FULL: 4048 link.link_speed = ETH_SPEED_NUM_100M; 4049 break; 4050 4051 case IXGBE_LINK_SPEED_1GB_FULL: 4052 link.link_speed = ETH_SPEED_NUM_1G; 4053 break; 4054 4055 case IXGBE_LINK_SPEED_2_5GB_FULL: 4056 link.link_speed = ETH_SPEED_NUM_2_5G; 4057 break; 4058 4059 case IXGBE_LINK_SPEED_5GB_FULL: 4060 link.link_speed = ETH_SPEED_NUM_5G; 4061 break; 4062 4063 case IXGBE_LINK_SPEED_10GB_FULL: 4064 link.link_speed = ETH_SPEED_NUM_10G; 4065 break; 4066 } 4067 4068 return rte_eth_linkstatus_set(dev, &link); 4069 } 4070 4071 static int 4072 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4073 { 4074 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0); 4075 } 4076 4077 static int 4078 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4079 { 4080 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1); 4081 } 4082 4083 static void 4084 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 4085 { 4086 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4087 uint32_t fctrl; 4088 4089 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4090 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4091 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4092 } 4093 4094 static void 4095 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 4096 { 4097 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4098 uint32_t fctrl; 4099 4100 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4101 fctrl &= (~IXGBE_FCTRL_UPE); 4102 if (dev->data->all_multicast == 1) 4103 fctrl |= IXGBE_FCTRL_MPE; 4104 else 4105 fctrl &= (~IXGBE_FCTRL_MPE); 4106 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4107 } 4108 4109 static void 4110 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 4111 { 4112 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4113 uint32_t fctrl; 4114 4115 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4116 fctrl |= IXGBE_FCTRL_MPE; 4117 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4118 } 4119 4120 static void 4121 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 4122 { 4123 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4124 uint32_t fctrl; 4125 4126 if (dev->data->promiscuous == 1) 4127 return; /* must remain in all_multicast mode */ 4128 4129 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4130 fctrl &= (~IXGBE_FCTRL_MPE); 4131 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4132 } 4133 4134 /** 4135 * It clears the interrupt causes and enables the interrupt. 4136 * It will be called once only during nic initialized. 4137 * 4138 * @param dev 4139 * Pointer to struct rte_eth_dev. 4140 * @param on 4141 * Enable or Disable. 4142 * 4143 * @return 4144 * - On success, zero. 4145 * - On failure, a negative value. 4146 */ 4147 static int 4148 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 4149 { 4150 struct ixgbe_interrupt *intr = 4151 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4152 4153 ixgbe_dev_link_status_print(dev); 4154 if (on) 4155 intr->mask |= IXGBE_EICR_LSC; 4156 else 4157 intr->mask &= ~IXGBE_EICR_LSC; 4158 4159 return 0; 4160 } 4161 4162 /** 4163 * It clears the interrupt causes and enables the interrupt. 4164 * It will be called once only during nic initialized. 4165 * 4166 * @param dev 4167 * Pointer to struct rte_eth_dev. 4168 * 4169 * @return 4170 * - On success, zero. 4171 * - On failure, a negative value. 4172 */ 4173 static int 4174 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev) 4175 { 4176 struct ixgbe_interrupt *intr = 4177 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4178 4179 intr->mask |= IXGBE_EICR_RTX_QUEUE; 4180 4181 return 0; 4182 } 4183 4184 /** 4185 * It clears the interrupt causes and enables the interrupt. 4186 * It will be called once only during nic initialized. 4187 * 4188 * @param dev 4189 * Pointer to struct rte_eth_dev. 4190 * 4191 * @return 4192 * - On success, zero. 4193 * - On failure, a negative value. 4194 */ 4195 static int 4196 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev) 4197 { 4198 struct ixgbe_interrupt *intr = 4199 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4200 4201 intr->mask |= IXGBE_EICR_LINKSEC; 4202 4203 return 0; 4204 } 4205 4206 /* 4207 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update. 4208 * 4209 * @param dev 4210 * Pointer to struct rte_eth_dev. 4211 * 4212 * @return 4213 * - On success, zero. 4214 * - On failure, a negative value. 4215 */ 4216 static int 4217 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev) 4218 { 4219 uint32_t eicr; 4220 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4221 struct ixgbe_interrupt *intr = 4222 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4223 4224 /* clear all cause mask */ 4225 ixgbe_disable_intr(hw); 4226 4227 /* read-on-clear nic registers here */ 4228 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4229 PMD_DRV_LOG(DEBUG, "eicr %x", eicr); 4230 4231 intr->flags = 0; 4232 4233 /* set flag for async link update */ 4234 if (eicr & IXGBE_EICR_LSC) 4235 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 4236 4237 if (eicr & IXGBE_EICR_MAILBOX) 4238 intr->flags |= IXGBE_FLAG_MAILBOX; 4239 4240 if (eicr & IXGBE_EICR_LINKSEC) 4241 intr->flags |= IXGBE_FLAG_MACSEC; 4242 4243 if (hw->mac.type == ixgbe_mac_X550EM_x && 4244 hw->phy.type == ixgbe_phy_x550em_ext_t && 4245 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x)) 4246 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT; 4247 4248 return 0; 4249 } 4250 4251 /** 4252 * It gets and then prints the link status. 4253 * 4254 * @param dev 4255 * Pointer to struct rte_eth_dev. 4256 * 4257 * @return 4258 * - On success, zero. 4259 * - On failure, a negative value. 4260 */ 4261 static void 4262 ixgbe_dev_link_status_print(struct rte_eth_dev *dev) 4263 { 4264 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4265 struct rte_eth_link link; 4266 4267 rte_eth_linkstatus_get(dev, &link); 4268 4269 if (link.link_status) { 4270 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", 4271 (int)(dev->data->port_id), 4272 (unsigned)link.link_speed, 4273 link.link_duplex == ETH_LINK_FULL_DUPLEX ? 4274 "full-duplex" : "half-duplex"); 4275 } else { 4276 PMD_INIT_LOG(INFO, " Port %d: Link Down", 4277 (int)(dev->data->port_id)); 4278 } 4279 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 4280 pci_dev->addr.domain, 4281 pci_dev->addr.bus, 4282 pci_dev->addr.devid, 4283 pci_dev->addr.function); 4284 } 4285 4286 /* 4287 * It executes link_update after knowing an interrupt occurred. 4288 * 4289 * @param dev 4290 * Pointer to struct rte_eth_dev. 4291 * 4292 * @return 4293 * - On success, zero. 4294 * - On failure, a negative value. 4295 */ 4296 static int 4297 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev, 4298 struct rte_intr_handle *intr_handle) 4299 { 4300 struct ixgbe_interrupt *intr = 4301 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4302 int64_t timeout; 4303 struct ixgbe_hw *hw = 4304 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4305 4306 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags); 4307 4308 if (intr->flags & IXGBE_FLAG_MAILBOX) { 4309 ixgbe_pf_mbx_process(dev); 4310 intr->flags &= ~IXGBE_FLAG_MAILBOX; 4311 } 4312 4313 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4314 ixgbe_handle_lasi(hw); 4315 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4316 } 4317 4318 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4319 struct rte_eth_link link; 4320 4321 /* get the link status before link update, for predicting later */ 4322 rte_eth_linkstatus_get(dev, &link); 4323 4324 ixgbe_dev_link_update(dev, 0); 4325 4326 /* likely to up */ 4327 if (!link.link_status) 4328 /* handle it 1 sec later, wait it being stable */ 4329 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT; 4330 /* likely to down */ 4331 else 4332 /* handle it 4 sec later, wait it being stable */ 4333 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT; 4334 4335 ixgbe_dev_link_status_print(dev); 4336 if (rte_eal_alarm_set(timeout * 1000, 4337 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0) 4338 PMD_DRV_LOG(ERR, "Error setting alarm"); 4339 else { 4340 /* remember original mask */ 4341 intr->mask_original = intr->mask; 4342 /* only disable lsc interrupt */ 4343 intr->mask &= ~IXGBE_EIMS_LSC; 4344 } 4345 } 4346 4347 PMD_DRV_LOG(DEBUG, "enable intr immediately"); 4348 ixgbe_enable_intr(dev); 4349 rte_intr_enable(intr_handle); 4350 4351 return 0; 4352 } 4353 4354 /** 4355 * Interrupt handler which shall be registered for alarm callback for delayed 4356 * handling specific interrupt to wait for the stable nic state. As the 4357 * NIC interrupt state is not stable for ixgbe after link is just down, 4358 * it needs to wait 4 seconds to get the stable status. 4359 * 4360 * @param handle 4361 * Pointer to interrupt handle. 4362 * @param param 4363 * The address of parameter (struct rte_eth_dev *) regsitered before. 4364 * 4365 * @return 4366 * void 4367 */ 4368 static void 4369 ixgbe_dev_interrupt_delayed_handler(void *param) 4370 { 4371 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4372 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4373 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4374 struct ixgbe_interrupt *intr = 4375 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4376 struct ixgbe_hw *hw = 4377 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4378 uint32_t eicr; 4379 4380 ixgbe_disable_intr(hw); 4381 4382 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4383 if (eicr & IXGBE_EICR_MAILBOX) 4384 ixgbe_pf_mbx_process(dev); 4385 4386 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4387 ixgbe_handle_lasi(hw); 4388 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4389 } 4390 4391 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4392 ixgbe_dev_link_update(dev, 0); 4393 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 4394 ixgbe_dev_link_status_print(dev); 4395 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, 4396 NULL); 4397 } 4398 4399 if (intr->flags & IXGBE_FLAG_MACSEC) { 4400 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, 4401 NULL); 4402 intr->flags &= ~IXGBE_FLAG_MACSEC; 4403 } 4404 4405 /* restore original mask */ 4406 intr->mask = intr->mask_original; 4407 intr->mask_original = 0; 4408 4409 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr); 4410 ixgbe_enable_intr(dev); 4411 rte_intr_enable(intr_handle); 4412 } 4413 4414 /** 4415 * Interrupt handler triggered by NIC for handling 4416 * specific interrupt. 4417 * 4418 * @param handle 4419 * Pointer to interrupt handle. 4420 * @param param 4421 * The address of parameter (struct rte_eth_dev *) regsitered before. 4422 * 4423 * @return 4424 * void 4425 */ 4426 static void 4427 ixgbe_dev_interrupt_handler(void *param) 4428 { 4429 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4430 4431 ixgbe_dev_interrupt_get_status(dev); 4432 ixgbe_dev_interrupt_action(dev, dev->intr_handle); 4433 } 4434 4435 static int 4436 ixgbe_dev_led_on(struct rte_eth_dev *dev) 4437 { 4438 struct ixgbe_hw *hw; 4439 4440 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4441 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4442 } 4443 4444 static int 4445 ixgbe_dev_led_off(struct rte_eth_dev *dev) 4446 { 4447 struct ixgbe_hw *hw; 4448 4449 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4450 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4451 } 4452 4453 static int 4454 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4455 { 4456 struct ixgbe_hw *hw; 4457 uint32_t mflcn_reg; 4458 uint32_t fccfg_reg; 4459 int rx_pause; 4460 int tx_pause; 4461 4462 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4463 4464 fc_conf->pause_time = hw->fc.pause_time; 4465 fc_conf->high_water = hw->fc.high_water[0]; 4466 fc_conf->low_water = hw->fc.low_water[0]; 4467 fc_conf->send_xon = hw->fc.send_xon; 4468 fc_conf->autoneg = !hw->fc.disable_fc_autoneg; 4469 4470 /* 4471 * Return rx_pause status according to actual setting of 4472 * MFLCN register. 4473 */ 4474 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4475 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE)) 4476 rx_pause = 1; 4477 else 4478 rx_pause = 0; 4479 4480 /* 4481 * Return tx_pause status according to actual setting of 4482 * FCCFG register. 4483 */ 4484 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4485 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY)) 4486 tx_pause = 1; 4487 else 4488 tx_pause = 0; 4489 4490 if (rx_pause && tx_pause) 4491 fc_conf->mode = RTE_FC_FULL; 4492 else if (rx_pause) 4493 fc_conf->mode = RTE_FC_RX_PAUSE; 4494 else if (tx_pause) 4495 fc_conf->mode = RTE_FC_TX_PAUSE; 4496 else 4497 fc_conf->mode = RTE_FC_NONE; 4498 4499 return 0; 4500 } 4501 4502 static int 4503 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4504 { 4505 struct ixgbe_hw *hw; 4506 int err; 4507 uint32_t rx_buf_size; 4508 uint32_t max_high_water; 4509 uint32_t mflcn; 4510 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4511 ixgbe_fc_none, 4512 ixgbe_fc_rx_pause, 4513 ixgbe_fc_tx_pause, 4514 ixgbe_fc_full 4515 }; 4516 4517 PMD_INIT_FUNC_TRACE(); 4518 4519 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4520 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)); 4521 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4522 4523 /* 4524 * At least reserve one Ethernet frame for watermark 4525 * high_water/low_water in kilo bytes for ixgbe 4526 */ 4527 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4528 if ((fc_conf->high_water > max_high_water) || 4529 (fc_conf->high_water < fc_conf->low_water)) { 4530 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4531 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4532 return -EINVAL; 4533 } 4534 4535 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode]; 4536 hw->fc.pause_time = fc_conf->pause_time; 4537 hw->fc.high_water[0] = fc_conf->high_water; 4538 hw->fc.low_water[0] = fc_conf->low_water; 4539 hw->fc.send_xon = fc_conf->send_xon; 4540 hw->fc.disable_fc_autoneg = !fc_conf->autoneg; 4541 4542 err = ixgbe_fc_enable(hw); 4543 4544 /* Not negotiated is not an error case */ 4545 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) { 4546 4547 /* check if we want to forward MAC frames - driver doesn't have native 4548 * capability to do that, so we'll write the registers ourselves */ 4549 4550 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4551 4552 /* set or clear MFLCN.PMCF bit depending on configuration */ 4553 if (fc_conf->mac_ctrl_frame_fwd != 0) 4554 mflcn |= IXGBE_MFLCN_PMCF; 4555 else 4556 mflcn &= ~IXGBE_MFLCN_PMCF; 4557 4558 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn); 4559 IXGBE_WRITE_FLUSH(hw); 4560 4561 return 0; 4562 } 4563 4564 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err); 4565 return -EIO; 4566 } 4567 4568 /** 4569 * ixgbe_pfc_enable_generic - Enable flow control 4570 * @hw: pointer to hardware structure 4571 * @tc_num: traffic class number 4572 * Enable flow control according to the current settings. 4573 */ 4574 static int 4575 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num) 4576 { 4577 int ret_val = 0; 4578 uint32_t mflcn_reg, fccfg_reg; 4579 uint32_t reg; 4580 uint32_t fcrtl, fcrth; 4581 uint8_t i; 4582 uint8_t nb_rx_en; 4583 4584 /* Validate the water mark configuration */ 4585 if (!hw->fc.pause_time) { 4586 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4587 goto out; 4588 } 4589 4590 /* Low water mark of zero causes XOFF floods */ 4591 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 4592 /* High/Low water can not be 0 */ 4593 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) { 4594 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4595 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4596 goto out; 4597 } 4598 4599 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) { 4600 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4601 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4602 goto out; 4603 } 4604 } 4605 /* Negotiate the fc mode to use */ 4606 ixgbe_fc_autoneg(hw); 4607 4608 /* Disable any previous flow control settings */ 4609 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4610 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE); 4611 4612 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4613 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 4614 4615 switch (hw->fc.current_mode) { 4616 case ixgbe_fc_none: 4617 /* 4618 * If the count of enabled RX Priority Flow control >1, 4619 * and the TX pause can not be disabled 4620 */ 4621 nb_rx_en = 0; 4622 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4623 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4624 if (reg & IXGBE_FCRTH_FCEN) 4625 nb_rx_en++; 4626 } 4627 if (nb_rx_en > 1) 4628 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4629 break; 4630 case ixgbe_fc_rx_pause: 4631 /* 4632 * Rx Flow control is enabled and Tx Flow control is 4633 * disabled by software override. Since there really 4634 * isn't a way to advertise that we are capable of RX 4635 * Pause ONLY, we will advertise that we support both 4636 * symmetric and asymmetric Rx PAUSE. Later, we will 4637 * disable the adapter's ability to send PAUSE frames. 4638 */ 4639 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4640 /* 4641 * If the count of enabled RX Priority Flow control >1, 4642 * and the TX pause can not be disabled 4643 */ 4644 nb_rx_en = 0; 4645 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4646 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4647 if (reg & IXGBE_FCRTH_FCEN) 4648 nb_rx_en++; 4649 } 4650 if (nb_rx_en > 1) 4651 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4652 break; 4653 case ixgbe_fc_tx_pause: 4654 /* 4655 * Tx Flow control is enabled, and Rx Flow control is 4656 * disabled by software override. 4657 */ 4658 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4659 break; 4660 case ixgbe_fc_full: 4661 /* Flow control (both Rx and Tx) is enabled by SW override. */ 4662 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4663 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4664 break; 4665 default: 4666 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly"); 4667 ret_val = IXGBE_ERR_CONFIG; 4668 goto out; 4669 } 4670 4671 /* Set 802.3x based flow control settings. */ 4672 mflcn_reg |= IXGBE_MFLCN_DPF; 4673 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 4674 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 4675 4676 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 4677 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 4678 hw->fc.high_water[tc_num]) { 4679 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE; 4680 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl); 4681 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN; 4682 } else { 4683 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0); 4684 /* 4685 * In order to prevent Tx hangs when the internal Tx 4686 * switch is enabled we must set the high water mark 4687 * to the maximum FCRTH value. This allows the Tx 4688 * switch to function even under heavy Rx workloads. 4689 */ 4690 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32; 4691 } 4692 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth); 4693 4694 /* Configure pause time (2 TCs per register) */ 4695 reg = hw->fc.pause_time * 0x00010001; 4696 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 4697 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 4698 4699 /* Configure flow control refresh threshold value */ 4700 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 4701 4702 out: 4703 return ret_val; 4704 } 4705 4706 static int 4707 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num) 4708 { 4709 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4710 int32_t ret_val = IXGBE_NOT_IMPLEMENTED; 4711 4712 if (hw->mac.type != ixgbe_mac_82598EB) { 4713 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num); 4714 } 4715 return ret_val; 4716 } 4717 4718 static int 4719 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf) 4720 { 4721 int err; 4722 uint32_t rx_buf_size; 4723 uint32_t max_high_water; 4724 uint8_t tc_num; 4725 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 4726 struct ixgbe_hw *hw = 4727 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4728 struct ixgbe_dcb_config *dcb_config = 4729 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 4730 4731 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4732 ixgbe_fc_none, 4733 ixgbe_fc_rx_pause, 4734 ixgbe_fc_tx_pause, 4735 ixgbe_fc_full 4736 }; 4737 4738 PMD_INIT_FUNC_TRACE(); 4739 4740 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map); 4741 tc_num = map[pfc_conf->priority]; 4742 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)); 4743 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4744 /* 4745 * At least reserve one Ethernet frame for watermark 4746 * high_water/low_water in kilo bytes for ixgbe 4747 */ 4748 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4749 if ((pfc_conf->fc.high_water > max_high_water) || 4750 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) { 4751 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4752 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4753 return -EINVAL; 4754 } 4755 4756 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode]; 4757 hw->fc.pause_time = pfc_conf->fc.pause_time; 4758 hw->fc.send_xon = pfc_conf->fc.send_xon; 4759 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water; 4760 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; 4761 4762 err = ixgbe_dcb_pfc_enable(dev, tc_num); 4763 4764 /* Not negotiated is not an error case */ 4765 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) 4766 return 0; 4767 4768 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err); 4769 return -EIO; 4770 } 4771 4772 static int 4773 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 4774 struct rte_eth_rss_reta_entry64 *reta_conf, 4775 uint16_t reta_size) 4776 { 4777 uint16_t i, sp_reta_size; 4778 uint8_t j, mask; 4779 uint32_t reta, r; 4780 uint16_t idx, shift; 4781 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4782 uint32_t reta_reg; 4783 4784 PMD_INIT_FUNC_TRACE(); 4785 4786 if (!ixgbe_rss_update_sp(hw->mac.type)) { 4787 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " 4788 "NIC."); 4789 return -ENOTSUP; 4790 } 4791 4792 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 4793 if (reta_size != sp_reta_size) { 4794 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 4795 "(%d) doesn't match the number hardware can supported " 4796 "(%d)", reta_size, sp_reta_size); 4797 return -EINVAL; 4798 } 4799 4800 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 4801 idx = i / RTE_RETA_GROUP_SIZE; 4802 shift = i % RTE_RETA_GROUP_SIZE; 4803 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 4804 IXGBE_4_BIT_MASK); 4805 if (!mask) 4806 continue; 4807 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 4808 if (mask == IXGBE_4_BIT_MASK) 4809 r = 0; 4810 else 4811 r = IXGBE_READ_REG(hw, reta_reg); 4812 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) { 4813 if (mask & (0x1 << j)) 4814 reta |= reta_conf[idx].reta[shift + j] << 4815 (CHAR_BIT * j); 4816 else 4817 reta |= r & (IXGBE_8_BIT_MASK << 4818 (CHAR_BIT * j)); 4819 } 4820 IXGBE_WRITE_REG(hw, reta_reg, reta); 4821 } 4822 4823 return 0; 4824 } 4825 4826 static int 4827 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 4828 struct rte_eth_rss_reta_entry64 *reta_conf, 4829 uint16_t reta_size) 4830 { 4831 uint16_t i, sp_reta_size; 4832 uint8_t j, mask; 4833 uint32_t reta; 4834 uint16_t idx, shift; 4835 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4836 uint32_t reta_reg; 4837 4838 PMD_INIT_FUNC_TRACE(); 4839 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 4840 if (reta_size != sp_reta_size) { 4841 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 4842 "(%d) doesn't match the number hardware can supported " 4843 "(%d)", reta_size, sp_reta_size); 4844 return -EINVAL; 4845 } 4846 4847 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 4848 idx = i / RTE_RETA_GROUP_SIZE; 4849 shift = i % RTE_RETA_GROUP_SIZE; 4850 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 4851 IXGBE_4_BIT_MASK); 4852 if (!mask) 4853 continue; 4854 4855 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 4856 reta = IXGBE_READ_REG(hw, reta_reg); 4857 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) { 4858 if (mask & (0x1 << j)) 4859 reta_conf[idx].reta[shift + j] = 4860 ((reta >> (CHAR_BIT * j)) & 4861 IXGBE_8_BIT_MASK); 4862 } 4863 } 4864 4865 return 0; 4866 } 4867 4868 static int 4869 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr, 4870 uint32_t index, uint32_t pool) 4871 { 4872 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4873 uint32_t enable_addr = 1; 4874 4875 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes, 4876 pool, enable_addr); 4877 } 4878 4879 static void 4880 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) 4881 { 4882 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4883 4884 ixgbe_clear_rar(hw, index); 4885 } 4886 4887 static int 4888 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr) 4889 { 4890 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4891 4892 ixgbe_remove_rar(dev, 0); 4893 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs); 4894 4895 return 0; 4896 } 4897 4898 static bool 4899 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 4900 { 4901 if (strcmp(dev->device->driver->name, drv->driver.name)) 4902 return false; 4903 4904 return true; 4905 } 4906 4907 bool 4908 is_ixgbe_supported(struct rte_eth_dev *dev) 4909 { 4910 return is_device_supported(dev, &rte_ixgbe_pmd); 4911 } 4912 4913 static int 4914 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 4915 { 4916 uint32_t hlreg0; 4917 uint32_t maxfrs; 4918 struct ixgbe_hw *hw; 4919 struct rte_eth_dev_info dev_info; 4920 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 4921 struct rte_eth_dev_data *dev_data = dev->data; 4922 4923 ixgbe_dev_info_get(dev, &dev_info); 4924 4925 /* check that mtu is within the allowed range */ 4926 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) 4927 return -EINVAL; 4928 4929 /* If device is started, refuse mtu that requires the support of 4930 * scattered packets when this feature has not been enabled before. 4931 */ 4932 if (dev_data->dev_started && !dev_data->scattered_rx && 4933 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE > 4934 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 4935 PMD_INIT_LOG(ERR, "Stop port first."); 4936 return -EINVAL; 4937 } 4938 4939 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4940 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4941 4942 /* switch to jumbo mode if needed */ 4943 if (frame_size > ETHER_MAX_LEN) { 4944 dev->data->dev_conf.rxmode.offloads |= 4945 DEV_RX_OFFLOAD_JUMBO_FRAME; 4946 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4947 } else { 4948 dev->data->dev_conf.rxmode.offloads &= 4949 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 4950 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; 4951 } 4952 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4953 4954 /* update max frame size */ 4955 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 4956 4957 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS); 4958 maxfrs &= 0x0000FFFF; 4959 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16); 4960 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs); 4961 4962 return 0; 4963 } 4964 4965 /* 4966 * Virtual Function operations 4967 */ 4968 static void 4969 ixgbevf_intr_disable(struct rte_eth_dev *dev) 4970 { 4971 struct ixgbe_interrupt *intr = 4972 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4973 struct ixgbe_hw *hw = 4974 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4975 4976 PMD_INIT_FUNC_TRACE(); 4977 4978 /* Clear interrupt mask to stop from interrupts being generated */ 4979 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK); 4980 4981 IXGBE_WRITE_FLUSH(hw); 4982 4983 /* Clear mask value. */ 4984 intr->mask = 0; 4985 } 4986 4987 static void 4988 ixgbevf_intr_enable(struct rte_eth_dev *dev) 4989 { 4990 struct ixgbe_interrupt *intr = 4991 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4992 struct ixgbe_hw *hw = 4993 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4994 4995 PMD_INIT_FUNC_TRACE(); 4996 4997 /* VF enable interrupt autoclean */ 4998 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK); 4999 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK); 5000 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK); 5001 5002 IXGBE_WRITE_FLUSH(hw); 5003 5004 /* Save IXGBE_VTEIMS value to mask. */ 5005 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK; 5006 } 5007 5008 static int 5009 ixgbevf_dev_configure(struct rte_eth_dev *dev) 5010 { 5011 struct rte_eth_conf *conf = &dev->data->dev_conf; 5012 struct ixgbe_adapter *adapter = 5013 (struct ixgbe_adapter *)dev->data->dev_private; 5014 5015 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d", 5016 dev->data->port_id); 5017 5018 /* 5019 * VF has no ability to enable/disable HW CRC 5020 * Keep the persistent behavior the same as Host PF 5021 */ 5022 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC 5023 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) { 5024 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip"); 5025 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC; 5026 } 5027 #else 5028 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) { 5029 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip"); 5030 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC; 5031 } 5032 #endif 5033 5034 /* 5035 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 5036 * allocation or vector Rx preconditions we will reset it. 5037 */ 5038 adapter->rx_bulk_alloc_allowed = true; 5039 adapter->rx_vec_allowed = true; 5040 5041 return 0; 5042 } 5043 5044 static int 5045 ixgbevf_dev_start(struct rte_eth_dev *dev) 5046 { 5047 struct ixgbe_hw *hw = 5048 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5049 uint32_t intr_vector = 0; 5050 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5051 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5052 5053 int err, mask = 0; 5054 5055 PMD_INIT_FUNC_TRACE(); 5056 5057 err = hw->mac.ops.reset_hw(hw); 5058 if (err) { 5059 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err); 5060 return err; 5061 } 5062 hw->mac.get_link_status = true; 5063 5064 /* negotiate mailbox API version to use with the PF. */ 5065 ixgbevf_negotiate_api(hw); 5066 5067 ixgbevf_dev_tx_init(dev); 5068 5069 /* This can fail when allocating mbufs for descriptor rings */ 5070 err = ixgbevf_dev_rx_init(dev); 5071 if (err) { 5072 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err); 5073 ixgbe_dev_clear_queues(dev); 5074 return err; 5075 } 5076 5077 /* Set vfta */ 5078 ixgbevf_set_vfta_all(dev, 1); 5079 5080 /* Set HW strip */ 5081 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 5082 ETH_VLAN_EXTEND_MASK; 5083 err = ixgbevf_vlan_offload_config(dev, mask); 5084 if (err) { 5085 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err); 5086 ixgbe_dev_clear_queues(dev); 5087 return err; 5088 } 5089 5090 ixgbevf_dev_rxtx_start(dev); 5091 5092 ixgbevf_dev_link_update(dev, 0); 5093 5094 /* check and configure queue intr-vector mapping */ 5095 if (rte_intr_cap_multiple(intr_handle) && 5096 dev->data->dev_conf.intr_conf.rxq) { 5097 /* According to datasheet, only vector 0/1/2 can be used, 5098 * now only one vector is used for Rx queue 5099 */ 5100 intr_vector = 1; 5101 if (rte_intr_efd_enable(intr_handle, intr_vector)) 5102 return -1; 5103 } 5104 5105 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 5106 intr_handle->intr_vec = 5107 rte_zmalloc("intr_vec", 5108 dev->data->nb_rx_queues * sizeof(int), 0); 5109 if (intr_handle->intr_vec == NULL) { 5110 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 5111 " intr_vec", dev->data->nb_rx_queues); 5112 return -ENOMEM; 5113 } 5114 } 5115 ixgbevf_configure_msix(dev); 5116 5117 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt 5118 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ). 5119 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( ) 5120 * is not cleared, it will fail when following rte_intr_enable( ) tries 5121 * to map Rx queue interrupt to other VFIO vectors. 5122 * So clear uio/vfio intr/evevnfd first to avoid failure. 5123 */ 5124 rte_intr_disable(intr_handle); 5125 5126 rte_intr_enable(intr_handle); 5127 5128 /* Re-enable interrupt for VF */ 5129 ixgbevf_intr_enable(dev); 5130 5131 return 0; 5132 } 5133 5134 static void 5135 ixgbevf_dev_stop(struct rte_eth_dev *dev) 5136 { 5137 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5138 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5139 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5140 5141 PMD_INIT_FUNC_TRACE(); 5142 5143 ixgbevf_intr_disable(dev); 5144 5145 hw->adapter_stopped = 1; 5146 ixgbe_stop_adapter(hw); 5147 5148 /* 5149 * Clear what we set, but we still keep shadow_vfta to 5150 * restore after device starts 5151 */ 5152 ixgbevf_set_vfta_all(dev, 0); 5153 5154 /* Clear stored conf */ 5155 dev->data->scattered_rx = 0; 5156 5157 ixgbe_dev_clear_queues(dev); 5158 5159 /* Clean datapath event and queue/vec mapping */ 5160 rte_intr_efd_disable(intr_handle); 5161 if (intr_handle->intr_vec != NULL) { 5162 rte_free(intr_handle->intr_vec); 5163 intr_handle->intr_vec = NULL; 5164 } 5165 } 5166 5167 static void 5168 ixgbevf_dev_close(struct rte_eth_dev *dev) 5169 { 5170 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5171 5172 PMD_INIT_FUNC_TRACE(); 5173 5174 ixgbe_reset_hw(hw); 5175 5176 ixgbevf_dev_stop(dev); 5177 5178 ixgbe_dev_free_queues(dev); 5179 5180 /** 5181 * Remove the VF MAC address ro ensure 5182 * that the VF traffic goes to the PF 5183 * after stop, close and detach of the VF 5184 **/ 5185 ixgbevf_remove_mac_addr(dev, 0); 5186 } 5187 5188 /* 5189 * Reset VF device 5190 */ 5191 static int 5192 ixgbevf_dev_reset(struct rte_eth_dev *dev) 5193 { 5194 int ret; 5195 5196 ret = eth_ixgbevf_dev_uninit(dev); 5197 if (ret) 5198 return ret; 5199 5200 ret = eth_ixgbevf_dev_init(dev); 5201 5202 return ret; 5203 } 5204 5205 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) 5206 { 5207 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5208 struct ixgbe_vfta *shadow_vfta = 5209 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5210 int i = 0, j = 0, vfta = 0, mask = 1; 5211 5212 for (i = 0; i < IXGBE_VFTA_SIZE; i++) { 5213 vfta = shadow_vfta->vfta[i]; 5214 if (vfta) { 5215 mask = 1; 5216 for (j = 0; j < 32; j++) { 5217 if (vfta & mask) 5218 ixgbe_set_vfta(hw, (i<<5)+j, 0, 5219 on, false); 5220 mask <<= 1; 5221 } 5222 } 5223 } 5224 5225 } 5226 5227 static int 5228 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 5229 { 5230 struct ixgbe_hw *hw = 5231 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5232 struct ixgbe_vfta *shadow_vfta = 5233 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5234 uint32_t vid_idx = 0; 5235 uint32_t vid_bit = 0; 5236 int ret = 0; 5237 5238 PMD_INIT_FUNC_TRACE(); 5239 5240 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */ 5241 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false); 5242 if (ret) { 5243 PMD_INIT_LOG(ERR, "Unable to set VF vlan"); 5244 return ret; 5245 } 5246 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 5247 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 5248 5249 /* Save what we set and retore it after device reset */ 5250 if (on) 5251 shadow_vfta->vfta[vid_idx] |= vid_bit; 5252 else 5253 shadow_vfta->vfta[vid_idx] &= ~vid_bit; 5254 5255 return 0; 5256 } 5257 5258 static void 5259 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 5260 { 5261 struct ixgbe_hw *hw = 5262 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5263 uint32_t ctrl; 5264 5265 PMD_INIT_FUNC_TRACE(); 5266 5267 if (queue >= hw->mac.max_rx_queues) 5268 return; 5269 5270 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 5271 if (on) 5272 ctrl |= IXGBE_RXDCTL_VME; 5273 else 5274 ctrl &= ~IXGBE_RXDCTL_VME; 5275 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 5276 5277 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on); 5278 } 5279 5280 static int 5281 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask) 5282 { 5283 struct ixgbe_rx_queue *rxq; 5284 uint16_t i; 5285 int on = 0; 5286 5287 /* VF function only support hw strip feature, others are not support */ 5288 if (mask & ETH_VLAN_STRIP_MASK) { 5289 for (i = 0; i < dev->data->nb_rx_queues; i++) { 5290 rxq = dev->data->rx_queues[i]; 5291 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP); 5292 ixgbevf_vlan_strip_queue_set(dev, i, on); 5293 } 5294 } 5295 5296 return 0; 5297 } 5298 5299 static int 5300 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 5301 { 5302 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 5303 5304 ixgbevf_vlan_offload_config(dev, mask); 5305 5306 return 0; 5307 } 5308 5309 int 5310 ixgbe_vt_check(struct ixgbe_hw *hw) 5311 { 5312 uint32_t reg_val; 5313 5314 /* if Virtualization Technology is enabled */ 5315 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 5316 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) { 5317 PMD_INIT_LOG(ERR, "VT must be enabled for this setting"); 5318 return -1; 5319 } 5320 5321 return 0; 5322 } 5323 5324 static uint32_t 5325 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr) 5326 { 5327 uint32_t vector = 0; 5328 5329 switch (hw->mac.mc_filter_type) { 5330 case 0: /* use bits [47:36] of the address */ 5331 vector = ((uc_addr->addr_bytes[4] >> 4) | 5332 (((uint16_t)uc_addr->addr_bytes[5]) << 4)); 5333 break; 5334 case 1: /* use bits [46:35] of the address */ 5335 vector = ((uc_addr->addr_bytes[4] >> 3) | 5336 (((uint16_t)uc_addr->addr_bytes[5]) << 5)); 5337 break; 5338 case 2: /* use bits [45:34] of the address */ 5339 vector = ((uc_addr->addr_bytes[4] >> 2) | 5340 (((uint16_t)uc_addr->addr_bytes[5]) << 6)); 5341 break; 5342 case 3: /* use bits [43:32] of the address */ 5343 vector = ((uc_addr->addr_bytes[4]) | 5344 (((uint16_t)uc_addr->addr_bytes[5]) << 8)); 5345 break; 5346 default: /* Invalid mc_filter_type */ 5347 break; 5348 } 5349 5350 /* vector can only be 12-bits or boundary will be exceeded */ 5351 vector &= 0xFFF; 5352 return vector; 5353 } 5354 5355 static int 5356 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr, 5357 uint8_t on) 5358 { 5359 uint32_t vector; 5360 uint32_t uta_idx; 5361 uint32_t reg_val; 5362 uint32_t uta_shift; 5363 uint32_t rc; 5364 const uint32_t ixgbe_uta_idx_mask = 0x7F; 5365 const uint32_t ixgbe_uta_bit_shift = 5; 5366 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1; 5367 const uint32_t bit1 = 0x1; 5368 5369 struct ixgbe_hw *hw = 5370 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5371 struct ixgbe_uta_info *uta_info = 5372 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5373 5374 /* The UTA table only exists on 82599 hardware and newer */ 5375 if (hw->mac.type < ixgbe_mac_82599EB) 5376 return -ENOTSUP; 5377 5378 vector = ixgbe_uta_vector(hw, mac_addr); 5379 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask; 5380 uta_shift = vector & ixgbe_uta_bit_mask; 5381 5382 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0); 5383 if (rc == on) 5384 return 0; 5385 5386 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx)); 5387 if (on) { 5388 uta_info->uta_in_use++; 5389 reg_val |= (bit1 << uta_shift); 5390 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift); 5391 } else { 5392 uta_info->uta_in_use--; 5393 reg_val &= ~(bit1 << uta_shift); 5394 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift); 5395 } 5396 5397 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val); 5398 5399 if (uta_info->uta_in_use > 0) 5400 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 5401 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 5402 else 5403 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 5404 5405 return 0; 5406 } 5407 5408 static int 5409 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) 5410 { 5411 int i; 5412 struct ixgbe_hw *hw = 5413 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5414 struct ixgbe_uta_info *uta_info = 5415 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5416 5417 /* The UTA table only exists on 82599 hardware and newer */ 5418 if (hw->mac.type < ixgbe_mac_82599EB) 5419 return -ENOTSUP; 5420 5421 if (on) { 5422 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5423 uta_info->uta_shadow[i] = ~0; 5424 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); 5425 } 5426 } else { 5427 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5428 uta_info->uta_shadow[i] = 0; 5429 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 5430 } 5431 } 5432 return 0; 5433 5434 } 5435 5436 uint32_t 5437 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val) 5438 { 5439 uint32_t new_val = orig_val; 5440 5441 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG) 5442 new_val |= IXGBE_VMOLR_AUPE; 5443 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC) 5444 new_val |= IXGBE_VMOLR_ROMPE; 5445 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC) 5446 new_val |= IXGBE_VMOLR_ROPE; 5447 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST) 5448 new_val |= IXGBE_VMOLR_BAM; 5449 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST) 5450 new_val |= IXGBE_VMOLR_MPE; 5451 5452 return new_val; 5453 } 5454 5455 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */ 5456 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */ 5457 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */ 5458 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */ 5459 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \ 5460 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \ 5461 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN)) 5462 5463 static int 5464 ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 5465 struct rte_eth_mirror_conf *mirror_conf, 5466 uint8_t rule_id, uint8_t on) 5467 { 5468 uint32_t mr_ctl, vlvf; 5469 uint32_t mp_lsb = 0; 5470 uint32_t mv_msb = 0; 5471 uint32_t mv_lsb = 0; 5472 uint32_t mp_msb = 0; 5473 uint8_t i = 0; 5474 int reg_index = 0; 5475 uint64_t vlan_mask = 0; 5476 5477 const uint8_t pool_mask_offset = 32; 5478 const uint8_t vlan_mask_offset = 32; 5479 const uint8_t dst_pool_offset = 8; 5480 const uint8_t rule_mr_offset = 4; 5481 const uint8_t mirror_rule_mask = 0x0F; 5482 5483 struct ixgbe_mirror_info *mr_info = 5484 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5485 struct ixgbe_hw *hw = 5486 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5487 uint8_t mirror_type = 0; 5488 5489 if (ixgbe_vt_check(hw) < 0) 5490 return -ENOTSUP; 5491 5492 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5493 return -EINVAL; 5494 5495 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) { 5496 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.", 5497 mirror_conf->rule_type); 5498 return -EINVAL; 5499 } 5500 5501 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5502 mirror_type |= IXGBE_MRCTL_VLME; 5503 /* Check if vlan id is valid and find conresponding VLAN ID 5504 * index in VLVF 5505 */ 5506 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) { 5507 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) { 5508 /* search vlan id related pool vlan filter 5509 * index 5510 */ 5511 reg_index = ixgbe_find_vlvf_slot( 5512 hw, 5513 mirror_conf->vlan.vlan_id[i], 5514 false); 5515 if (reg_index < 0) 5516 return -EINVAL; 5517 vlvf = IXGBE_READ_REG(hw, 5518 IXGBE_VLVF(reg_index)); 5519 if ((vlvf & IXGBE_VLVF_VIEN) && 5520 ((vlvf & IXGBE_VLVF_VLANID_MASK) == 5521 mirror_conf->vlan.vlan_id[i])) 5522 vlan_mask |= (1ULL << reg_index); 5523 else 5524 return -EINVAL; 5525 } 5526 } 5527 5528 if (on) { 5529 mv_lsb = vlan_mask & 0xFFFFFFFF; 5530 mv_msb = vlan_mask >> vlan_mask_offset; 5531 5532 mr_info->mr_conf[rule_id].vlan.vlan_mask = 5533 mirror_conf->vlan.vlan_mask; 5534 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) { 5535 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) 5536 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 5537 mirror_conf->vlan.vlan_id[i]; 5538 } 5539 } else { 5540 mv_lsb = 0; 5541 mv_msb = 0; 5542 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0; 5543 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) 5544 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0; 5545 } 5546 } 5547 5548 /** 5549 * if enable pool mirror, write related pool mask register,if disable 5550 * pool mirror, clear PFMRVM register 5551 */ 5552 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5553 mirror_type |= IXGBE_MRCTL_VPME; 5554 if (on) { 5555 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF; 5556 mp_msb = mirror_conf->pool_mask >> pool_mask_offset; 5557 mr_info->mr_conf[rule_id].pool_mask = 5558 mirror_conf->pool_mask; 5559 5560 } else { 5561 mp_lsb = 0; 5562 mp_msb = 0; 5563 mr_info->mr_conf[rule_id].pool_mask = 0; 5564 } 5565 } 5566 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT) 5567 mirror_type |= IXGBE_MRCTL_UPME; 5568 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT) 5569 mirror_type |= IXGBE_MRCTL_DPME; 5570 5571 /* read mirror control register and recalculate it */ 5572 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id)); 5573 5574 if (on) { 5575 mr_ctl |= mirror_type; 5576 mr_ctl &= mirror_rule_mask; 5577 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset; 5578 } else { 5579 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask); 5580 } 5581 5582 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type; 5583 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool; 5584 5585 /* write mirrror control register */ 5586 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5587 5588 /* write pool mirrror control register */ 5589 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5590 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb); 5591 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), 5592 mp_msb); 5593 } 5594 /* write VLAN mirrror control register */ 5595 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5596 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb); 5597 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), 5598 mv_msb); 5599 } 5600 5601 return 0; 5602 } 5603 5604 static int 5605 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id) 5606 { 5607 int mr_ctl = 0; 5608 uint32_t lsb_val = 0; 5609 uint32_t msb_val = 0; 5610 const uint8_t rule_mr_offset = 4; 5611 5612 struct ixgbe_hw *hw = 5613 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5614 struct ixgbe_mirror_info *mr_info = 5615 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5616 5617 if (ixgbe_vt_check(hw) < 0) 5618 return -ENOTSUP; 5619 5620 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5621 return -EINVAL; 5622 5623 memset(&mr_info->mr_conf[rule_id], 0, 5624 sizeof(struct rte_eth_mirror_conf)); 5625 5626 /* clear PFVMCTL register */ 5627 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5628 5629 /* clear pool mask register */ 5630 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val); 5631 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val); 5632 5633 /* clear vlan mask register */ 5634 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val); 5635 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val); 5636 5637 return 0; 5638 } 5639 5640 static int 5641 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5642 { 5643 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5644 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5645 struct ixgbe_interrupt *intr = 5646 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5647 struct ixgbe_hw *hw = 5648 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5649 uint32_t vec = IXGBE_MISC_VEC_ID; 5650 5651 if (rte_intr_allow_others(intr_handle)) 5652 vec = IXGBE_RX_VEC_START; 5653 intr->mask |= (1 << vec); 5654 RTE_SET_USED(queue_id); 5655 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5656 5657 rte_intr_enable(intr_handle); 5658 5659 return 0; 5660 } 5661 5662 static int 5663 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5664 { 5665 struct ixgbe_interrupt *intr = 5666 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5667 struct ixgbe_hw *hw = 5668 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5669 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5670 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5671 uint32_t vec = IXGBE_MISC_VEC_ID; 5672 5673 if (rte_intr_allow_others(intr_handle)) 5674 vec = IXGBE_RX_VEC_START; 5675 intr->mask &= ~(1 << vec); 5676 RTE_SET_USED(queue_id); 5677 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5678 5679 return 0; 5680 } 5681 5682 static int 5683 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5684 { 5685 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5686 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5687 uint32_t mask; 5688 struct ixgbe_hw *hw = 5689 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5690 struct ixgbe_interrupt *intr = 5691 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5692 5693 if (queue_id < 16) { 5694 ixgbe_disable_intr(hw); 5695 intr->mask |= (1 << queue_id); 5696 ixgbe_enable_intr(dev); 5697 } else if (queue_id < 32) { 5698 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5699 mask &= (1 << queue_id); 5700 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5701 } else if (queue_id < 64) { 5702 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5703 mask &= (1 << (queue_id - 32)); 5704 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5705 } 5706 rte_intr_enable(intr_handle); 5707 5708 return 0; 5709 } 5710 5711 static int 5712 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5713 { 5714 uint32_t mask; 5715 struct ixgbe_hw *hw = 5716 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5717 struct ixgbe_interrupt *intr = 5718 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5719 5720 if (queue_id < 16) { 5721 ixgbe_disable_intr(hw); 5722 intr->mask &= ~(1 << queue_id); 5723 ixgbe_enable_intr(dev); 5724 } else if (queue_id < 32) { 5725 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5726 mask &= ~(1 << queue_id); 5727 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5728 } else if (queue_id < 64) { 5729 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5730 mask &= ~(1 << (queue_id - 32)); 5731 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5732 } 5733 5734 return 0; 5735 } 5736 5737 static void 5738 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 5739 uint8_t queue, uint8_t msix_vector) 5740 { 5741 uint32_t tmp, idx; 5742 5743 if (direction == -1) { 5744 /* other causes */ 5745 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5746 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC); 5747 tmp &= ~0xFF; 5748 tmp |= msix_vector; 5749 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp); 5750 } else { 5751 /* rx or tx cause */ 5752 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5753 idx = ((16 * (queue & 1)) + (8 * direction)); 5754 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1)); 5755 tmp &= ~(0xFF << idx); 5756 tmp |= (msix_vector << idx); 5757 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp); 5758 } 5759 } 5760 5761 /** 5762 * set the IVAR registers, mapping interrupt causes to vectors 5763 * @param hw 5764 * pointer to ixgbe_hw struct 5765 * @direction 5766 * 0 for Rx, 1 for Tx, -1 for other causes 5767 * @queue 5768 * queue to map the corresponding interrupt to 5769 * @msix_vector 5770 * the vector to map to the corresponding queue 5771 */ 5772 static void 5773 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 5774 uint8_t queue, uint8_t msix_vector) 5775 { 5776 uint32_t tmp, idx; 5777 5778 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5779 if (hw->mac.type == ixgbe_mac_82598EB) { 5780 if (direction == -1) 5781 direction = 0; 5782 idx = (((direction * 64) + queue) >> 2) & 0x1F; 5783 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx)); 5784 tmp &= ~(0xFF << (8 * (queue & 0x3))); 5785 tmp |= (msix_vector << (8 * (queue & 0x3))); 5786 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp); 5787 } else if ((hw->mac.type == ixgbe_mac_82599EB) || 5788 (hw->mac.type == ixgbe_mac_X540) || 5789 (hw->mac.type == ixgbe_mac_X550)) { 5790 if (direction == -1) { 5791 /* other causes */ 5792 idx = ((queue & 1) * 8); 5793 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC); 5794 tmp &= ~(0xFF << idx); 5795 tmp |= (msix_vector << idx); 5796 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp); 5797 } else { 5798 /* rx or tx causes */ 5799 idx = ((16 * (queue & 1)) + (8 * direction)); 5800 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 5801 tmp &= ~(0xFF << idx); 5802 tmp |= (msix_vector << idx); 5803 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp); 5804 } 5805 } 5806 } 5807 5808 static void 5809 ixgbevf_configure_msix(struct rte_eth_dev *dev) 5810 { 5811 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5812 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5813 struct ixgbe_hw *hw = 5814 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5815 uint32_t q_idx; 5816 uint32_t vector_idx = IXGBE_MISC_VEC_ID; 5817 uint32_t base = IXGBE_MISC_VEC_ID; 5818 5819 /* Configure VF other cause ivar */ 5820 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx); 5821 5822 /* won't configure msix register if no mapping is done 5823 * between intr vector and event fd. 5824 */ 5825 if (!rte_intr_dp_is_en(intr_handle)) 5826 return; 5827 5828 if (rte_intr_allow_others(intr_handle)) { 5829 base = IXGBE_RX_VEC_START; 5830 vector_idx = IXGBE_RX_VEC_START; 5831 } 5832 5833 /* Configure all RX queues of VF */ 5834 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) { 5835 /* Force all queue use vector 0, 5836 * as IXGBE_VF_MAXMSIVECOTR = 1 5837 */ 5838 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx); 5839 intr_handle->intr_vec[q_idx] = vector_idx; 5840 if (vector_idx < base + intr_handle->nb_efd - 1) 5841 vector_idx++; 5842 } 5843 5844 /* As RX queue setting above show, all queues use the vector 0. 5845 * Set only the ITR value of IXGBE_MISC_VEC_ID. 5846 */ 5847 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID), 5848 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 5849 | IXGBE_EITR_CNT_WDIS); 5850 } 5851 5852 /** 5853 * Sets up the hardware to properly generate MSI-X interrupts 5854 * @hw 5855 * board private structure 5856 */ 5857 static void 5858 ixgbe_configure_msix(struct rte_eth_dev *dev) 5859 { 5860 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5861 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5862 struct ixgbe_hw *hw = 5863 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5864 uint32_t queue_id, base = IXGBE_MISC_VEC_ID; 5865 uint32_t vec = IXGBE_MISC_VEC_ID; 5866 uint32_t mask; 5867 uint32_t gpie; 5868 5869 /* won't configure msix register if no mapping is done 5870 * between intr vector and event fd 5871 * but if misx has been enabled already, need to configure 5872 * auto clean, auto mask and throttling. 5873 */ 5874 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 5875 if (!rte_intr_dp_is_en(intr_handle) && 5876 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT))) 5877 return; 5878 5879 if (rte_intr_allow_others(intr_handle)) 5880 vec = base = IXGBE_RX_VEC_START; 5881 5882 /* setup GPIE for MSI-x mode */ 5883 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 5884 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5885 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME; 5886 /* auto clearing and auto setting corresponding bits in EIMS 5887 * when MSI-X interrupt is triggered 5888 */ 5889 if (hw->mac.type == ixgbe_mac_82598EB) { 5890 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5891 } else { 5892 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5893 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5894 } 5895 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5896 5897 /* Populate the IVAR table and set the ITR values to the 5898 * corresponding register. 5899 */ 5900 if (rte_intr_dp_is_en(intr_handle)) { 5901 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; 5902 queue_id++) { 5903 /* by default, 1:1 mapping */ 5904 ixgbe_set_ivar_map(hw, 0, queue_id, vec); 5905 intr_handle->intr_vec[queue_id] = vec; 5906 if (vec < base + intr_handle->nb_efd - 1) 5907 vec++; 5908 } 5909 5910 switch (hw->mac.type) { 5911 case ixgbe_mac_82598EB: 5912 ixgbe_set_ivar_map(hw, -1, 5913 IXGBE_IVAR_OTHER_CAUSES_INDEX, 5914 IXGBE_MISC_VEC_ID); 5915 break; 5916 case ixgbe_mac_82599EB: 5917 case ixgbe_mac_X540: 5918 case ixgbe_mac_X550: 5919 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID); 5920 break; 5921 default: 5922 break; 5923 } 5924 } 5925 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID), 5926 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 5927 | IXGBE_EITR_CNT_WDIS); 5928 5929 /* set up to autoclear timer, and the vectors */ 5930 mask = IXGBE_EIMS_ENABLE_MASK; 5931 mask &= ~(IXGBE_EIMS_OTHER | 5932 IXGBE_EIMS_MAILBOX | 5933 IXGBE_EIMS_LSC); 5934 5935 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask); 5936 } 5937 5938 int 5939 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, 5940 uint16_t queue_idx, uint16_t tx_rate) 5941 { 5942 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5943 struct rte_eth_rxmode *rxmode; 5944 uint32_t rf_dec, rf_int; 5945 uint32_t bcnrc_val; 5946 uint16_t link_speed = dev->data->dev_link.link_speed; 5947 5948 if (queue_idx >= hw->mac.max_tx_queues) 5949 return -EINVAL; 5950 5951 if (tx_rate != 0) { 5952 /* Calculate the rate factor values to set */ 5953 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate; 5954 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate; 5955 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate; 5956 5957 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA; 5958 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) & 5959 IXGBE_RTTBCNRC_RF_INT_MASK_M); 5960 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK); 5961 } else { 5962 bcnrc_val = 0; 5963 } 5964 5965 rxmode = &dev->data->dev_conf.rxmode; 5966 /* 5967 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 5968 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise 5969 * set as 0x4. 5970 */ 5971 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) && 5972 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE)) 5973 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 5974 IXGBE_MMW_SIZE_JUMBO_FRAME); 5975 else 5976 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 5977 IXGBE_MMW_SIZE_DEFAULT); 5978 5979 /* Set RTTBCNRC of queue X */ 5980 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx); 5981 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 5982 IXGBE_WRITE_FLUSH(hw); 5983 5984 return 0; 5985 } 5986 5987 static int 5988 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr, 5989 __attribute__((unused)) uint32_t index, 5990 __attribute__((unused)) uint32_t pool) 5991 { 5992 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5993 int diag; 5994 5995 /* 5996 * On a 82599 VF, adding again the same MAC addr is not an idempotent 5997 * operation. Trap this case to avoid exhausting the [very limited] 5998 * set of PF resources used to store VF MAC addresses. 5999 */ 6000 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0) 6001 return -1; 6002 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6003 if (diag != 0) 6004 PMD_DRV_LOG(ERR, "Unable to add MAC address " 6005 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d", 6006 mac_addr->addr_bytes[0], 6007 mac_addr->addr_bytes[1], 6008 mac_addr->addr_bytes[2], 6009 mac_addr->addr_bytes[3], 6010 mac_addr->addr_bytes[4], 6011 mac_addr->addr_bytes[5], 6012 diag); 6013 return diag; 6014 } 6015 6016 static void 6017 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index) 6018 { 6019 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6020 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr; 6021 struct ether_addr *mac_addr; 6022 uint32_t i; 6023 int diag; 6024 6025 /* 6026 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does 6027 * not support the deletion of a given MAC address. 6028 * Instead, it imposes to delete all MAC addresses, then to add again 6029 * all MAC addresses with the exception of the one to be deleted. 6030 */ 6031 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL); 6032 6033 /* 6034 * Add again all MAC addresses, with the exception of the deleted one 6035 * and of the permanent MAC address. 6036 */ 6037 for (i = 0, mac_addr = dev->data->mac_addrs; 6038 i < hw->mac.num_rar_entries; i++, mac_addr++) { 6039 /* Skip the deleted MAC address */ 6040 if (i == index) 6041 continue; 6042 /* Skip NULL MAC addresses */ 6043 if (is_zero_ether_addr(mac_addr)) 6044 continue; 6045 /* Skip the permanent MAC address */ 6046 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0) 6047 continue; 6048 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6049 if (diag != 0) 6050 PMD_DRV_LOG(ERR, 6051 "Adding again MAC address " 6052 "%02x:%02x:%02x:%02x:%02x:%02x failed " 6053 "diag=%d", 6054 mac_addr->addr_bytes[0], 6055 mac_addr->addr_bytes[1], 6056 mac_addr->addr_bytes[2], 6057 mac_addr->addr_bytes[3], 6058 mac_addr->addr_bytes[4], 6059 mac_addr->addr_bytes[5], 6060 diag); 6061 } 6062 } 6063 6064 static int 6065 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr) 6066 { 6067 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6068 6069 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0); 6070 6071 return 0; 6072 } 6073 6074 int 6075 ixgbe_syn_filter_set(struct rte_eth_dev *dev, 6076 struct rte_eth_syn_filter *filter, 6077 bool add) 6078 { 6079 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6080 struct ixgbe_filter_info *filter_info = 6081 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6082 uint32_t syn_info; 6083 uint32_t synqf; 6084 6085 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6086 return -EINVAL; 6087 6088 syn_info = filter_info->syn_info; 6089 6090 if (add) { 6091 if (syn_info & IXGBE_SYN_FILTER_ENABLE) 6092 return -EINVAL; 6093 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) & 6094 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE); 6095 6096 if (filter->hig_pri) 6097 synqf |= IXGBE_SYN_FILTER_SYNQFP; 6098 else 6099 synqf &= ~IXGBE_SYN_FILTER_SYNQFP; 6100 } else { 6101 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6102 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE)) 6103 return -ENOENT; 6104 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE); 6105 } 6106 6107 filter_info->syn_info = synqf; 6108 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 6109 IXGBE_WRITE_FLUSH(hw); 6110 return 0; 6111 } 6112 6113 static int 6114 ixgbe_syn_filter_get(struct rte_eth_dev *dev, 6115 struct rte_eth_syn_filter *filter) 6116 { 6117 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6118 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6119 6120 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 6121 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0; 6122 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1); 6123 return 0; 6124 } 6125 return -ENOENT; 6126 } 6127 6128 static int 6129 ixgbe_syn_filter_handle(struct rte_eth_dev *dev, 6130 enum rte_filter_op filter_op, 6131 void *arg) 6132 { 6133 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6134 int ret; 6135 6136 MAC_TYPE_FILTER_SUP(hw->mac.type); 6137 6138 if (filter_op == RTE_ETH_FILTER_NOP) 6139 return 0; 6140 6141 if (arg == NULL) { 6142 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u", 6143 filter_op); 6144 return -EINVAL; 6145 } 6146 6147 switch (filter_op) { 6148 case RTE_ETH_FILTER_ADD: 6149 ret = ixgbe_syn_filter_set(dev, 6150 (struct rte_eth_syn_filter *)arg, 6151 TRUE); 6152 break; 6153 case RTE_ETH_FILTER_DELETE: 6154 ret = ixgbe_syn_filter_set(dev, 6155 (struct rte_eth_syn_filter *)arg, 6156 FALSE); 6157 break; 6158 case RTE_ETH_FILTER_GET: 6159 ret = ixgbe_syn_filter_get(dev, 6160 (struct rte_eth_syn_filter *)arg); 6161 break; 6162 default: 6163 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op); 6164 ret = -EINVAL; 6165 break; 6166 } 6167 6168 return ret; 6169 } 6170 6171 6172 static inline enum ixgbe_5tuple_protocol 6173 convert_protocol_type(uint8_t protocol_value) 6174 { 6175 if (protocol_value == IPPROTO_TCP) 6176 return IXGBE_FILTER_PROTOCOL_TCP; 6177 else if (protocol_value == IPPROTO_UDP) 6178 return IXGBE_FILTER_PROTOCOL_UDP; 6179 else if (protocol_value == IPPROTO_SCTP) 6180 return IXGBE_FILTER_PROTOCOL_SCTP; 6181 else 6182 return IXGBE_FILTER_PROTOCOL_NONE; 6183 } 6184 6185 /* inject a 5-tuple filter to HW */ 6186 static inline void 6187 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev, 6188 struct ixgbe_5tuple_filter *filter) 6189 { 6190 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6191 int i; 6192 uint32_t ftqf, sdpqf; 6193 uint32_t l34timir = 0; 6194 uint8_t mask = 0xff; 6195 6196 i = filter->index; 6197 6198 sdpqf = (uint32_t)(filter->filter_info.dst_port << 6199 IXGBE_SDPQF_DSTPORT_SHIFT); 6200 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT); 6201 6202 ftqf = (uint32_t)(filter->filter_info.proto & 6203 IXGBE_FTQF_PROTOCOL_MASK); 6204 ftqf |= (uint32_t)((filter->filter_info.priority & 6205 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT); 6206 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */ 6207 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK; 6208 if (filter->filter_info.dst_ip_mask == 0) 6209 mask &= IXGBE_FTQF_DEST_ADDR_MASK; 6210 if (filter->filter_info.src_port_mask == 0) 6211 mask &= IXGBE_FTQF_SOURCE_PORT_MASK; 6212 if (filter->filter_info.dst_port_mask == 0) 6213 mask &= IXGBE_FTQF_DEST_PORT_MASK; 6214 if (filter->filter_info.proto_mask == 0) 6215 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK; 6216 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT; 6217 ftqf |= IXGBE_FTQF_POOL_MASK_EN; 6218 ftqf |= IXGBE_FTQF_QUEUE_ENABLE; 6219 6220 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip); 6221 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip); 6222 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf); 6223 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf); 6224 6225 l34timir |= IXGBE_L34T_IMIR_RESERVE; 6226 l34timir |= (uint32_t)(filter->queue << 6227 IXGBE_L34T_IMIR_QUEUE_SHIFT); 6228 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir); 6229 } 6230 6231 /* 6232 * add a 5tuple filter 6233 * 6234 * @param 6235 * dev: Pointer to struct rte_eth_dev. 6236 * index: the index the filter allocates. 6237 * filter: ponter to the filter that will be added. 6238 * rx_queue: the queue id the filter assigned to. 6239 * 6240 * @return 6241 * - On success, zero. 6242 * - On failure, a negative value. 6243 */ 6244 static int 6245 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 6246 struct ixgbe_5tuple_filter *filter) 6247 { 6248 struct ixgbe_filter_info *filter_info = 6249 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6250 int i, idx, shift; 6251 6252 /* 6253 * look for an unused 5tuple filter index, 6254 * and insert the filter to list. 6255 */ 6256 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) { 6257 idx = i / (sizeof(uint32_t) * NBBY); 6258 shift = i % (sizeof(uint32_t) * NBBY); 6259 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) { 6260 filter_info->fivetuple_mask[idx] |= 1 << shift; 6261 filter->index = i; 6262 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list, 6263 filter, 6264 entries); 6265 break; 6266 } 6267 } 6268 if (i >= IXGBE_MAX_FTQF_FILTERS) { 6269 PMD_DRV_LOG(ERR, "5tuple filters are full."); 6270 return -ENOSYS; 6271 } 6272 6273 ixgbe_inject_5tuple_filter(dev, filter); 6274 6275 return 0; 6276 } 6277 6278 /* 6279 * remove a 5tuple filter 6280 * 6281 * @param 6282 * dev: Pointer to struct rte_eth_dev. 6283 * filter: the pointer of the filter will be removed. 6284 */ 6285 static void 6286 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 6287 struct ixgbe_5tuple_filter *filter) 6288 { 6289 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6290 struct ixgbe_filter_info *filter_info = 6291 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6292 uint16_t index = filter->index; 6293 6294 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &= 6295 ~(1 << (index % (sizeof(uint32_t) * NBBY))); 6296 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries); 6297 rte_free(filter); 6298 6299 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0); 6300 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0); 6301 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0); 6302 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0); 6303 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0); 6304 } 6305 6306 static int 6307 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 6308 { 6309 struct ixgbe_hw *hw; 6310 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 6311 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode; 6312 6313 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6314 6315 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN)) 6316 return -EINVAL; 6317 6318 /* refuse mtu that requires the support of scattered packets when this 6319 * feature has not been enabled before. 6320 */ 6321 if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) && 6322 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE > 6323 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) 6324 return -EINVAL; 6325 6326 /* 6327 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU 6328 * request of the version 2.0 of the mailbox API. 6329 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0 6330 * of the mailbox API. 6331 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers 6332 * prior to 3.11.33 which contains the following change: 6333 * "ixgbe: Enable jumbo frames support w/ SR-IOV" 6334 */ 6335 ixgbevf_rlpml_set_vf(hw, max_frame); 6336 6337 /* update max frame size */ 6338 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame; 6339 return 0; 6340 } 6341 6342 static inline struct ixgbe_5tuple_filter * 6343 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list, 6344 struct ixgbe_5tuple_filter_info *key) 6345 { 6346 struct ixgbe_5tuple_filter *it; 6347 6348 TAILQ_FOREACH(it, filter_list, entries) { 6349 if (memcmp(key, &it->filter_info, 6350 sizeof(struct ixgbe_5tuple_filter_info)) == 0) { 6351 return it; 6352 } 6353 } 6354 return NULL; 6355 } 6356 6357 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/ 6358 static inline int 6359 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter, 6360 struct ixgbe_5tuple_filter_info *filter_info) 6361 { 6362 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM || 6363 filter->priority > IXGBE_5TUPLE_MAX_PRI || 6364 filter->priority < IXGBE_5TUPLE_MIN_PRI) 6365 return -EINVAL; 6366 6367 switch (filter->dst_ip_mask) { 6368 case UINT32_MAX: 6369 filter_info->dst_ip_mask = 0; 6370 filter_info->dst_ip = filter->dst_ip; 6371 break; 6372 case 0: 6373 filter_info->dst_ip_mask = 1; 6374 break; 6375 default: 6376 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 6377 return -EINVAL; 6378 } 6379 6380 switch (filter->src_ip_mask) { 6381 case UINT32_MAX: 6382 filter_info->src_ip_mask = 0; 6383 filter_info->src_ip = filter->src_ip; 6384 break; 6385 case 0: 6386 filter_info->src_ip_mask = 1; 6387 break; 6388 default: 6389 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 6390 return -EINVAL; 6391 } 6392 6393 switch (filter->dst_port_mask) { 6394 case UINT16_MAX: 6395 filter_info->dst_port_mask = 0; 6396 filter_info->dst_port = filter->dst_port; 6397 break; 6398 case 0: 6399 filter_info->dst_port_mask = 1; 6400 break; 6401 default: 6402 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 6403 return -EINVAL; 6404 } 6405 6406 switch (filter->src_port_mask) { 6407 case UINT16_MAX: 6408 filter_info->src_port_mask = 0; 6409 filter_info->src_port = filter->src_port; 6410 break; 6411 case 0: 6412 filter_info->src_port_mask = 1; 6413 break; 6414 default: 6415 PMD_DRV_LOG(ERR, "invalid src_port mask."); 6416 return -EINVAL; 6417 } 6418 6419 switch (filter->proto_mask) { 6420 case UINT8_MAX: 6421 filter_info->proto_mask = 0; 6422 filter_info->proto = 6423 convert_protocol_type(filter->proto); 6424 break; 6425 case 0: 6426 filter_info->proto_mask = 1; 6427 break; 6428 default: 6429 PMD_DRV_LOG(ERR, "invalid protocol mask."); 6430 return -EINVAL; 6431 } 6432 6433 filter_info->priority = (uint8_t)filter->priority; 6434 return 0; 6435 } 6436 6437 /* 6438 * add or delete a ntuple filter 6439 * 6440 * @param 6441 * dev: Pointer to struct rte_eth_dev. 6442 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6443 * add: if true, add filter, if false, remove filter 6444 * 6445 * @return 6446 * - On success, zero. 6447 * - On failure, a negative value. 6448 */ 6449 int 6450 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 6451 struct rte_eth_ntuple_filter *ntuple_filter, 6452 bool add) 6453 { 6454 struct ixgbe_filter_info *filter_info = 6455 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6456 struct ixgbe_5tuple_filter_info filter_5tuple; 6457 struct ixgbe_5tuple_filter *filter; 6458 int ret; 6459 6460 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6461 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6462 return -EINVAL; 6463 } 6464 6465 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6466 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6467 if (ret < 0) 6468 return ret; 6469 6470 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6471 &filter_5tuple); 6472 if (filter != NULL && add) { 6473 PMD_DRV_LOG(ERR, "filter exists."); 6474 return -EEXIST; 6475 } 6476 if (filter == NULL && !add) { 6477 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6478 return -ENOENT; 6479 } 6480 6481 if (add) { 6482 filter = rte_zmalloc("ixgbe_5tuple_filter", 6483 sizeof(struct ixgbe_5tuple_filter), 0); 6484 if (filter == NULL) 6485 return -ENOMEM; 6486 rte_memcpy(&filter->filter_info, 6487 &filter_5tuple, 6488 sizeof(struct ixgbe_5tuple_filter_info)); 6489 filter->queue = ntuple_filter->queue; 6490 ret = ixgbe_add_5tuple_filter(dev, filter); 6491 if (ret < 0) { 6492 rte_free(filter); 6493 return ret; 6494 } 6495 } else 6496 ixgbe_remove_5tuple_filter(dev, filter); 6497 6498 return 0; 6499 } 6500 6501 /* 6502 * get a ntuple filter 6503 * 6504 * @param 6505 * dev: Pointer to struct rte_eth_dev. 6506 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6507 * 6508 * @return 6509 * - On success, zero. 6510 * - On failure, a negative value. 6511 */ 6512 static int 6513 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev, 6514 struct rte_eth_ntuple_filter *ntuple_filter) 6515 { 6516 struct ixgbe_filter_info *filter_info = 6517 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6518 struct ixgbe_5tuple_filter_info filter_5tuple; 6519 struct ixgbe_5tuple_filter *filter; 6520 int ret; 6521 6522 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6523 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6524 return -EINVAL; 6525 } 6526 6527 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6528 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6529 if (ret < 0) 6530 return ret; 6531 6532 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6533 &filter_5tuple); 6534 if (filter == NULL) { 6535 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6536 return -ENOENT; 6537 } 6538 ntuple_filter->queue = filter->queue; 6539 return 0; 6540 } 6541 6542 /* 6543 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter. 6544 * @dev: pointer to rte_eth_dev structure 6545 * @filter_op:operation will be taken. 6546 * @arg: a pointer to specific structure corresponding to the filter_op 6547 * 6548 * @return 6549 * - On success, zero. 6550 * - On failure, a negative value. 6551 */ 6552 static int 6553 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev, 6554 enum rte_filter_op filter_op, 6555 void *arg) 6556 { 6557 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6558 int ret; 6559 6560 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type); 6561 6562 if (filter_op == RTE_ETH_FILTER_NOP) 6563 return 0; 6564 6565 if (arg == NULL) { 6566 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 6567 filter_op); 6568 return -EINVAL; 6569 } 6570 6571 switch (filter_op) { 6572 case RTE_ETH_FILTER_ADD: 6573 ret = ixgbe_add_del_ntuple_filter(dev, 6574 (struct rte_eth_ntuple_filter *)arg, 6575 TRUE); 6576 break; 6577 case RTE_ETH_FILTER_DELETE: 6578 ret = ixgbe_add_del_ntuple_filter(dev, 6579 (struct rte_eth_ntuple_filter *)arg, 6580 FALSE); 6581 break; 6582 case RTE_ETH_FILTER_GET: 6583 ret = ixgbe_get_ntuple_filter(dev, 6584 (struct rte_eth_ntuple_filter *)arg); 6585 break; 6586 default: 6587 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 6588 ret = -EINVAL; 6589 break; 6590 } 6591 return ret; 6592 } 6593 6594 int 6595 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 6596 struct rte_eth_ethertype_filter *filter, 6597 bool add) 6598 { 6599 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6600 struct ixgbe_filter_info *filter_info = 6601 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6602 uint32_t etqf = 0; 6603 uint32_t etqs = 0; 6604 int ret; 6605 struct ixgbe_ethertype_filter ethertype_filter; 6606 6607 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6608 return -EINVAL; 6609 6610 if (filter->ether_type == ETHER_TYPE_IPv4 || 6611 filter->ether_type == ETHER_TYPE_IPv6) { 6612 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in" 6613 " ethertype filter.", filter->ether_type); 6614 return -EINVAL; 6615 } 6616 6617 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) { 6618 PMD_DRV_LOG(ERR, "mac compare is unsupported."); 6619 return -EINVAL; 6620 } 6621 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) { 6622 PMD_DRV_LOG(ERR, "drop option is unsupported."); 6623 return -EINVAL; 6624 } 6625 6626 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6627 if (ret >= 0 && add) { 6628 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.", 6629 filter->ether_type); 6630 return -EEXIST; 6631 } 6632 if (ret < 0 && !add) { 6633 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6634 filter->ether_type); 6635 return -ENOENT; 6636 } 6637 6638 if (add) { 6639 etqf = IXGBE_ETQF_FILTER_EN; 6640 etqf |= (uint32_t)filter->ether_type; 6641 etqs |= (uint32_t)((filter->queue << 6642 IXGBE_ETQS_RX_QUEUE_SHIFT) & 6643 IXGBE_ETQS_RX_QUEUE); 6644 etqs |= IXGBE_ETQS_QUEUE_EN; 6645 6646 ethertype_filter.ethertype = filter->ether_type; 6647 ethertype_filter.etqf = etqf; 6648 ethertype_filter.etqs = etqs; 6649 ethertype_filter.conf = FALSE; 6650 ret = ixgbe_ethertype_filter_insert(filter_info, 6651 ðertype_filter); 6652 if (ret < 0) { 6653 PMD_DRV_LOG(ERR, "ethertype filters are full."); 6654 return -ENOSPC; 6655 } 6656 } else { 6657 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret); 6658 if (ret < 0) 6659 return -ENOSYS; 6660 } 6661 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf); 6662 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs); 6663 IXGBE_WRITE_FLUSH(hw); 6664 6665 return 0; 6666 } 6667 6668 static int 6669 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, 6670 struct rte_eth_ethertype_filter *filter) 6671 { 6672 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6673 struct ixgbe_filter_info *filter_info = 6674 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6675 uint32_t etqf, etqs; 6676 int ret; 6677 6678 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6679 if (ret < 0) { 6680 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6681 filter->ether_type); 6682 return -ENOENT; 6683 } 6684 6685 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret)); 6686 if (etqf & IXGBE_ETQF_FILTER_EN) { 6687 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret)); 6688 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE; 6689 filter->flags = 0; 6690 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> 6691 IXGBE_ETQS_RX_QUEUE_SHIFT; 6692 return 0; 6693 } 6694 return -ENOENT; 6695 } 6696 6697 /* 6698 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter. 6699 * @dev: pointer to rte_eth_dev structure 6700 * @filter_op:operation will be taken. 6701 * @arg: a pointer to specific structure corresponding to the filter_op 6702 */ 6703 static int 6704 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev, 6705 enum rte_filter_op filter_op, 6706 void *arg) 6707 { 6708 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6709 int ret; 6710 6711 MAC_TYPE_FILTER_SUP(hw->mac.type); 6712 6713 if (filter_op == RTE_ETH_FILTER_NOP) 6714 return 0; 6715 6716 if (arg == NULL) { 6717 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 6718 filter_op); 6719 return -EINVAL; 6720 } 6721 6722 switch (filter_op) { 6723 case RTE_ETH_FILTER_ADD: 6724 ret = ixgbe_add_del_ethertype_filter(dev, 6725 (struct rte_eth_ethertype_filter *)arg, 6726 TRUE); 6727 break; 6728 case RTE_ETH_FILTER_DELETE: 6729 ret = ixgbe_add_del_ethertype_filter(dev, 6730 (struct rte_eth_ethertype_filter *)arg, 6731 FALSE); 6732 break; 6733 case RTE_ETH_FILTER_GET: 6734 ret = ixgbe_get_ethertype_filter(dev, 6735 (struct rte_eth_ethertype_filter *)arg); 6736 break; 6737 default: 6738 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 6739 ret = -EINVAL; 6740 break; 6741 } 6742 return ret; 6743 } 6744 6745 static int 6746 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 6747 enum rte_filter_type filter_type, 6748 enum rte_filter_op filter_op, 6749 void *arg) 6750 { 6751 int ret = 0; 6752 6753 switch (filter_type) { 6754 case RTE_ETH_FILTER_NTUPLE: 6755 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg); 6756 break; 6757 case RTE_ETH_FILTER_ETHERTYPE: 6758 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg); 6759 break; 6760 case RTE_ETH_FILTER_SYN: 6761 ret = ixgbe_syn_filter_handle(dev, filter_op, arg); 6762 break; 6763 case RTE_ETH_FILTER_FDIR: 6764 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg); 6765 break; 6766 case RTE_ETH_FILTER_L2_TUNNEL: 6767 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg); 6768 break; 6769 case RTE_ETH_FILTER_GENERIC: 6770 if (filter_op != RTE_ETH_FILTER_GET) 6771 return -EINVAL; 6772 *(const void **)arg = &ixgbe_flow_ops; 6773 break; 6774 default: 6775 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 6776 filter_type); 6777 ret = -EINVAL; 6778 break; 6779 } 6780 6781 return ret; 6782 } 6783 6784 static u8 * 6785 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw, 6786 u8 **mc_addr_ptr, u32 *vmdq) 6787 { 6788 u8 *mc_addr; 6789 6790 *vmdq = 0; 6791 mc_addr = *mc_addr_ptr; 6792 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr)); 6793 return mc_addr; 6794 } 6795 6796 static int 6797 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 6798 struct ether_addr *mc_addr_set, 6799 uint32_t nb_mc_addr) 6800 { 6801 struct ixgbe_hw *hw; 6802 u8 *mc_addr_list; 6803 6804 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6805 mc_addr_list = (u8 *)mc_addr_set; 6806 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr, 6807 ixgbe_dev_addr_list_itr, TRUE); 6808 } 6809 6810 static uint64_t 6811 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev) 6812 { 6813 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6814 uint64_t systime_cycles; 6815 6816 switch (hw->mac.type) { 6817 case ixgbe_mac_X550: 6818 case ixgbe_mac_X550EM_x: 6819 case ixgbe_mac_X550EM_a: 6820 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */ 6821 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 6822 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 6823 * NSEC_PER_SEC; 6824 break; 6825 default: 6826 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 6827 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 6828 << 32; 6829 } 6830 6831 return systime_cycles; 6832 } 6833 6834 static uint64_t 6835 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) 6836 { 6837 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6838 uint64_t rx_tstamp_cycles; 6839 6840 switch (hw->mac.type) { 6841 case ixgbe_mac_X550: 6842 case ixgbe_mac_X550EM_x: 6843 case ixgbe_mac_X550EM_a: 6844 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 6845 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 6846 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 6847 * NSEC_PER_SEC; 6848 break; 6849 default: 6850 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 6851 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 6852 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 6853 << 32; 6854 } 6855 6856 return rx_tstamp_cycles; 6857 } 6858 6859 static uint64_t 6860 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 6861 { 6862 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6863 uint64_t tx_tstamp_cycles; 6864 6865 switch (hw->mac.type) { 6866 case ixgbe_mac_X550: 6867 case ixgbe_mac_X550EM_x: 6868 case ixgbe_mac_X550EM_a: 6869 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 6870 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 6871 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 6872 * NSEC_PER_SEC; 6873 break; 6874 default: 6875 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 6876 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 6877 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 6878 << 32; 6879 } 6880 6881 return tx_tstamp_cycles; 6882 } 6883 6884 static void 6885 ixgbe_start_timecounters(struct rte_eth_dev *dev) 6886 { 6887 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6888 struct ixgbe_adapter *adapter = 6889 (struct ixgbe_adapter *)dev->data->dev_private; 6890 struct rte_eth_link link; 6891 uint32_t incval = 0; 6892 uint32_t shift = 0; 6893 6894 /* Get current link speed. */ 6895 ixgbe_dev_link_update(dev, 1); 6896 rte_eth_linkstatus_get(dev, &link); 6897 6898 switch (link.link_speed) { 6899 case ETH_SPEED_NUM_100M: 6900 incval = IXGBE_INCVAL_100; 6901 shift = IXGBE_INCVAL_SHIFT_100; 6902 break; 6903 case ETH_SPEED_NUM_1G: 6904 incval = IXGBE_INCVAL_1GB; 6905 shift = IXGBE_INCVAL_SHIFT_1GB; 6906 break; 6907 case ETH_SPEED_NUM_10G: 6908 default: 6909 incval = IXGBE_INCVAL_10GB; 6910 shift = IXGBE_INCVAL_SHIFT_10GB; 6911 break; 6912 } 6913 6914 switch (hw->mac.type) { 6915 case ixgbe_mac_X550: 6916 case ixgbe_mac_X550EM_x: 6917 case ixgbe_mac_X550EM_a: 6918 /* Independent of link speed. */ 6919 incval = 1; 6920 /* Cycles read will be interpreted as ns. */ 6921 shift = 0; 6922 /* Fall-through */ 6923 case ixgbe_mac_X540: 6924 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval); 6925 break; 6926 case ixgbe_mac_82599EB: 6927 incval >>= IXGBE_INCVAL_SHIFT_82599; 6928 shift -= IXGBE_INCVAL_SHIFT_82599; 6929 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 6930 (1 << IXGBE_INCPER_SHIFT_82599) | incval); 6931 break; 6932 default: 6933 /* Not supported. */ 6934 return; 6935 } 6936 6937 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 6938 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 6939 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 6940 6941 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6942 adapter->systime_tc.cc_shift = shift; 6943 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; 6944 6945 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6946 adapter->rx_tstamp_tc.cc_shift = shift; 6947 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 6948 6949 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6950 adapter->tx_tstamp_tc.cc_shift = shift; 6951 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 6952 } 6953 6954 static int 6955 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 6956 { 6957 struct ixgbe_adapter *adapter = 6958 (struct ixgbe_adapter *)dev->data->dev_private; 6959 6960 adapter->systime_tc.nsec += delta; 6961 adapter->rx_tstamp_tc.nsec += delta; 6962 adapter->tx_tstamp_tc.nsec += delta; 6963 6964 return 0; 6965 } 6966 6967 static int 6968 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 6969 { 6970 uint64_t ns; 6971 struct ixgbe_adapter *adapter = 6972 (struct ixgbe_adapter *)dev->data->dev_private; 6973 6974 ns = rte_timespec_to_ns(ts); 6975 /* Set the timecounters to a new value. */ 6976 adapter->systime_tc.nsec = ns; 6977 adapter->rx_tstamp_tc.nsec = ns; 6978 adapter->tx_tstamp_tc.nsec = ns; 6979 6980 return 0; 6981 } 6982 6983 static int 6984 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 6985 { 6986 uint64_t ns, systime_cycles; 6987 struct ixgbe_adapter *adapter = 6988 (struct ixgbe_adapter *)dev->data->dev_private; 6989 6990 systime_cycles = ixgbe_read_systime_cyclecounter(dev); 6991 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 6992 *ts = rte_ns_to_timespec(ns); 6993 6994 return 0; 6995 } 6996 6997 static int 6998 ixgbe_timesync_enable(struct rte_eth_dev *dev) 6999 { 7000 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7001 uint32_t tsync_ctl; 7002 uint32_t tsauxc; 7003 7004 /* Stop the timesync system time. */ 7005 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0); 7006 /* Reset the timesync system time value. */ 7007 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0); 7008 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0); 7009 7010 /* Enable system time for platforms where it isn't on by default. */ 7011 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC); 7012 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME; 7013 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc); 7014 7015 ixgbe_start_timecounters(dev); 7016 7017 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7018 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 7019 (ETHER_TYPE_1588 | 7020 IXGBE_ETQF_FILTER_EN | 7021 IXGBE_ETQF_1588)); 7022 7023 /* Enable timestamping of received PTP packets. */ 7024 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7025 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED; 7026 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7027 7028 /* Enable timestamping of transmitted PTP packets. */ 7029 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7030 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED; 7031 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7032 7033 IXGBE_WRITE_FLUSH(hw); 7034 7035 return 0; 7036 } 7037 7038 static int 7039 ixgbe_timesync_disable(struct rte_eth_dev *dev) 7040 { 7041 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7042 uint32_t tsync_ctl; 7043 7044 /* Disable timestamping of transmitted PTP packets. */ 7045 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7046 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED; 7047 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7048 7049 /* Disable timestamping of received PTP packets. */ 7050 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7051 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED; 7052 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7053 7054 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7055 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0); 7056 7057 /* Stop incrementating the System Time registers. */ 7058 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0); 7059 7060 return 0; 7061 } 7062 7063 static int 7064 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 7065 struct timespec *timestamp, 7066 uint32_t flags __rte_unused) 7067 { 7068 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7069 struct ixgbe_adapter *adapter = 7070 (struct ixgbe_adapter *)dev->data->dev_private; 7071 uint32_t tsync_rxctl; 7072 uint64_t rx_tstamp_cycles; 7073 uint64_t ns; 7074 7075 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7076 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0) 7077 return -EINVAL; 7078 7079 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev); 7080 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 7081 *timestamp = rte_ns_to_timespec(ns); 7082 7083 return 0; 7084 } 7085 7086 static int 7087 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 7088 struct timespec *timestamp) 7089 { 7090 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7091 struct ixgbe_adapter *adapter = 7092 (struct ixgbe_adapter *)dev->data->dev_private; 7093 uint32_t tsync_txctl; 7094 uint64_t tx_tstamp_cycles; 7095 uint64_t ns; 7096 7097 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7098 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0) 7099 return -EINVAL; 7100 7101 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev); 7102 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 7103 *timestamp = rte_ns_to_timespec(ns); 7104 7105 return 0; 7106 } 7107 7108 static int 7109 ixgbe_get_reg_length(struct rte_eth_dev *dev) 7110 { 7111 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7112 int count = 0; 7113 int g_ind = 0; 7114 const struct reg_info *reg_group; 7115 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7116 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7117 7118 while ((reg_group = reg_set[g_ind++])) 7119 count += ixgbe_regs_group_count(reg_group); 7120 7121 return count; 7122 } 7123 7124 static int 7125 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused) 7126 { 7127 int count = 0; 7128 int g_ind = 0; 7129 const struct reg_info *reg_group; 7130 7131 while ((reg_group = ixgbevf_regs[g_ind++])) 7132 count += ixgbe_regs_group_count(reg_group); 7133 7134 return count; 7135 } 7136 7137 static int 7138 ixgbe_get_regs(struct rte_eth_dev *dev, 7139 struct rte_dev_reg_info *regs) 7140 { 7141 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7142 uint32_t *data = regs->data; 7143 int g_ind = 0; 7144 int count = 0; 7145 const struct reg_info *reg_group; 7146 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7147 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7148 7149 if (data == NULL) { 7150 regs->length = ixgbe_get_reg_length(dev); 7151 regs->width = sizeof(uint32_t); 7152 return 0; 7153 } 7154 7155 /* Support only full register dump */ 7156 if ((regs->length == 0) || 7157 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) { 7158 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7159 hw->device_id; 7160 while ((reg_group = reg_set[g_ind++])) 7161 count += ixgbe_read_regs_group(dev, &data[count], 7162 reg_group); 7163 return 0; 7164 } 7165 7166 return -ENOTSUP; 7167 } 7168 7169 static int 7170 ixgbevf_get_regs(struct rte_eth_dev *dev, 7171 struct rte_dev_reg_info *regs) 7172 { 7173 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7174 uint32_t *data = regs->data; 7175 int g_ind = 0; 7176 int count = 0; 7177 const struct reg_info *reg_group; 7178 7179 if (data == NULL) { 7180 regs->length = ixgbevf_get_reg_length(dev); 7181 regs->width = sizeof(uint32_t); 7182 return 0; 7183 } 7184 7185 /* Support only full register dump */ 7186 if ((regs->length == 0) || 7187 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) { 7188 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7189 hw->device_id; 7190 while ((reg_group = ixgbevf_regs[g_ind++])) 7191 count += ixgbe_read_regs_group(dev, &data[count], 7192 reg_group); 7193 return 0; 7194 } 7195 7196 return -ENOTSUP; 7197 } 7198 7199 static int 7200 ixgbe_get_eeprom_length(struct rte_eth_dev *dev) 7201 { 7202 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7203 7204 /* Return unit is byte count */ 7205 return hw->eeprom.word_size * 2; 7206 } 7207 7208 static int 7209 ixgbe_get_eeprom(struct rte_eth_dev *dev, 7210 struct rte_dev_eeprom_info *in_eeprom) 7211 { 7212 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7213 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7214 uint16_t *data = in_eeprom->data; 7215 int first, length; 7216 7217 first = in_eeprom->offset >> 1; 7218 length = in_eeprom->length >> 1; 7219 if ((first > hw->eeprom.word_size) || 7220 ((first + length) > hw->eeprom.word_size)) 7221 return -EINVAL; 7222 7223 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7224 7225 return eeprom->ops.read_buffer(hw, first, length, data); 7226 } 7227 7228 static int 7229 ixgbe_set_eeprom(struct rte_eth_dev *dev, 7230 struct rte_dev_eeprom_info *in_eeprom) 7231 { 7232 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7233 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7234 uint16_t *data = in_eeprom->data; 7235 int first, length; 7236 7237 first = in_eeprom->offset >> 1; 7238 length = in_eeprom->length >> 1; 7239 if ((first > hw->eeprom.word_size) || 7240 ((first + length) > hw->eeprom.word_size)) 7241 return -EINVAL; 7242 7243 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7244 7245 return eeprom->ops.write_buffer(hw, first, length, data); 7246 } 7247 7248 static int 7249 ixgbe_get_module_info(struct rte_eth_dev *dev, 7250 struct rte_eth_dev_module_info *modinfo) 7251 { 7252 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7253 uint32_t status; 7254 uint8_t sff8472_rev, addr_mode; 7255 bool page_swap = false; 7256 7257 /* Check whether we support SFF-8472 or not */ 7258 status = hw->phy.ops.read_i2c_eeprom(hw, 7259 IXGBE_SFF_SFF_8472_COMP, 7260 &sff8472_rev); 7261 if (status != 0) 7262 return -EIO; 7263 7264 /* addressing mode is not supported */ 7265 status = hw->phy.ops.read_i2c_eeprom(hw, 7266 IXGBE_SFF_SFF_8472_SWAP, 7267 &addr_mode); 7268 if (status != 0) 7269 return -EIO; 7270 7271 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 7272 PMD_DRV_LOG(ERR, 7273 "Address change required to access page 0xA2, " 7274 "but not supported. Please report the module " 7275 "type to the driver maintainers."); 7276 page_swap = true; 7277 } 7278 7279 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) { 7280 /* We have a SFP, but it does not support SFF-8472 */ 7281 modinfo->type = RTE_ETH_MODULE_SFF_8079; 7282 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 7283 } else { 7284 /* We have a SFP which supports a revision of SFF-8472. */ 7285 modinfo->type = RTE_ETH_MODULE_SFF_8472; 7286 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 7287 } 7288 7289 return 0; 7290 } 7291 7292 static int 7293 ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 7294 struct rte_dev_eeprom_info *info) 7295 { 7296 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7297 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 7298 uint8_t databyte = 0xFF; 7299 uint8_t *data = info->data; 7300 uint32_t i = 0; 7301 7302 if (info->length == 0) 7303 return -EINVAL; 7304 7305 for (i = info->offset; i < info->offset + info->length; i++) { 7306 if (i < RTE_ETH_MODULE_SFF_8079_LEN) 7307 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 7308 else 7309 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 7310 7311 if (status != 0) 7312 return -EIO; 7313 7314 data[i - info->offset] = databyte; 7315 } 7316 7317 return 0; 7318 } 7319 7320 uint16_t 7321 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) { 7322 switch (mac_type) { 7323 case ixgbe_mac_X550: 7324 case ixgbe_mac_X550EM_x: 7325 case ixgbe_mac_X550EM_a: 7326 return ETH_RSS_RETA_SIZE_512; 7327 case ixgbe_mac_X550_vf: 7328 case ixgbe_mac_X550EM_x_vf: 7329 case ixgbe_mac_X550EM_a_vf: 7330 return ETH_RSS_RETA_SIZE_64; 7331 default: 7332 return ETH_RSS_RETA_SIZE_128; 7333 } 7334 } 7335 7336 uint32_t 7337 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) { 7338 switch (mac_type) { 7339 case ixgbe_mac_X550: 7340 case ixgbe_mac_X550EM_x: 7341 case ixgbe_mac_X550EM_a: 7342 if (reta_idx < ETH_RSS_RETA_SIZE_128) 7343 return IXGBE_RETA(reta_idx >> 2); 7344 else 7345 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2); 7346 case ixgbe_mac_X550_vf: 7347 case ixgbe_mac_X550EM_x_vf: 7348 case ixgbe_mac_X550EM_a_vf: 7349 return IXGBE_VFRETA(reta_idx >> 2); 7350 default: 7351 return IXGBE_RETA(reta_idx >> 2); 7352 } 7353 } 7354 7355 uint32_t 7356 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) { 7357 switch (mac_type) { 7358 case ixgbe_mac_X550_vf: 7359 case ixgbe_mac_X550EM_x_vf: 7360 case ixgbe_mac_X550EM_a_vf: 7361 return IXGBE_VFMRQC; 7362 default: 7363 return IXGBE_MRQC; 7364 } 7365 } 7366 7367 uint32_t 7368 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) { 7369 switch (mac_type) { 7370 case ixgbe_mac_X550_vf: 7371 case ixgbe_mac_X550EM_x_vf: 7372 case ixgbe_mac_X550EM_a_vf: 7373 return IXGBE_VFRSSRK(i); 7374 default: 7375 return IXGBE_RSSRK(i); 7376 } 7377 } 7378 7379 bool 7380 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) { 7381 switch (mac_type) { 7382 case ixgbe_mac_82599_vf: 7383 case ixgbe_mac_X540_vf: 7384 return 0; 7385 default: 7386 return 1; 7387 } 7388 } 7389 7390 static int 7391 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 7392 struct rte_eth_dcb_info *dcb_info) 7393 { 7394 struct ixgbe_dcb_config *dcb_config = 7395 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 7396 struct ixgbe_dcb_tc_config *tc; 7397 struct rte_eth_dcb_tc_queue_mapping *tc_queue; 7398 uint8_t nb_tcs; 7399 uint8_t i, j; 7400 7401 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG) 7402 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs; 7403 else 7404 dcb_info->nb_tcs = 1; 7405 7406 tc_queue = &dcb_info->tc_queue; 7407 nb_tcs = dcb_info->nb_tcs; 7408 7409 if (dcb_config->vt_mode) { /* vt is enabled*/ 7410 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf = 7411 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf; 7412 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7413 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i]; 7414 if (RTE_ETH_DEV_SRIOV(dev).active > 0) { 7415 for (j = 0; j < nb_tcs; j++) { 7416 tc_queue->tc_rxq[0][j].base = j; 7417 tc_queue->tc_rxq[0][j].nb_queue = 1; 7418 tc_queue->tc_txq[0][j].base = j; 7419 tc_queue->tc_txq[0][j].nb_queue = 1; 7420 } 7421 } else { 7422 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) { 7423 for (j = 0; j < nb_tcs; j++) { 7424 tc_queue->tc_rxq[i][j].base = 7425 i * nb_tcs + j; 7426 tc_queue->tc_rxq[i][j].nb_queue = 1; 7427 tc_queue->tc_txq[i][j].base = 7428 i * nb_tcs + j; 7429 tc_queue->tc_txq[i][j].nb_queue = 1; 7430 } 7431 } 7432 } 7433 } else { /* vt is disabled*/ 7434 struct rte_eth_dcb_rx_conf *rx_conf = 7435 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 7436 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7437 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i]; 7438 if (dcb_info->nb_tcs == ETH_4_TCS) { 7439 for (i = 0; i < dcb_info->nb_tcs; i++) { 7440 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32; 7441 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7442 } 7443 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7444 dcb_info->tc_queue.tc_txq[0][1].base = 64; 7445 dcb_info->tc_queue.tc_txq[0][2].base = 96; 7446 dcb_info->tc_queue.tc_txq[0][3].base = 112; 7447 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64; 7448 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7449 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7450 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7451 } else if (dcb_info->nb_tcs == ETH_8_TCS) { 7452 for (i = 0; i < dcb_info->nb_tcs; i++) { 7453 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16; 7454 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7455 } 7456 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7457 dcb_info->tc_queue.tc_txq[0][1].base = 32; 7458 dcb_info->tc_queue.tc_txq[0][2].base = 64; 7459 dcb_info->tc_queue.tc_txq[0][3].base = 80; 7460 dcb_info->tc_queue.tc_txq[0][4].base = 96; 7461 dcb_info->tc_queue.tc_txq[0][5].base = 104; 7462 dcb_info->tc_queue.tc_txq[0][6].base = 112; 7463 dcb_info->tc_queue.tc_txq[0][7].base = 120; 7464 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32; 7465 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7466 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7467 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7468 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8; 7469 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8; 7470 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8; 7471 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8; 7472 } 7473 } 7474 for (i = 0; i < dcb_info->nb_tcs; i++) { 7475 tc = &dcb_config->tc_config[i]; 7476 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent; 7477 } 7478 return 0; 7479 } 7480 7481 /* Update e-tag ether type */ 7482 static int 7483 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw, 7484 uint16_t ether_type) 7485 { 7486 uint32_t etag_etype; 7487 7488 if (hw->mac.type != ixgbe_mac_X550 && 7489 hw->mac.type != ixgbe_mac_X550EM_x && 7490 hw->mac.type != ixgbe_mac_X550EM_a) { 7491 return -ENOTSUP; 7492 } 7493 7494 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7495 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK; 7496 etag_etype |= ether_type; 7497 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7498 IXGBE_WRITE_FLUSH(hw); 7499 7500 return 0; 7501 } 7502 7503 /* Config l2 tunnel ether type */ 7504 static int 7505 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev, 7506 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7507 { 7508 int ret = 0; 7509 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7510 struct ixgbe_l2_tn_info *l2_tn_info = 7511 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7512 7513 if (l2_tunnel == NULL) 7514 return -EINVAL; 7515 7516 switch (l2_tunnel->l2_tunnel_type) { 7517 case RTE_L2_TUNNEL_TYPE_E_TAG: 7518 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type; 7519 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type); 7520 break; 7521 default: 7522 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7523 ret = -EINVAL; 7524 break; 7525 } 7526 7527 return ret; 7528 } 7529 7530 /* Enable e-tag tunnel */ 7531 static int 7532 ixgbe_e_tag_enable(struct ixgbe_hw *hw) 7533 { 7534 uint32_t etag_etype; 7535 7536 if (hw->mac.type != ixgbe_mac_X550 && 7537 hw->mac.type != ixgbe_mac_X550EM_x && 7538 hw->mac.type != ixgbe_mac_X550EM_a) { 7539 return -ENOTSUP; 7540 } 7541 7542 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7543 etag_etype |= IXGBE_ETAG_ETYPE_VALID; 7544 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7545 IXGBE_WRITE_FLUSH(hw); 7546 7547 return 0; 7548 } 7549 7550 /* Enable l2 tunnel */ 7551 static int 7552 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev, 7553 enum rte_eth_tunnel_type l2_tunnel_type) 7554 { 7555 int ret = 0; 7556 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7557 struct ixgbe_l2_tn_info *l2_tn_info = 7558 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7559 7560 switch (l2_tunnel_type) { 7561 case RTE_L2_TUNNEL_TYPE_E_TAG: 7562 l2_tn_info->e_tag_en = TRUE; 7563 ret = ixgbe_e_tag_enable(hw); 7564 break; 7565 default: 7566 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7567 ret = -EINVAL; 7568 break; 7569 } 7570 7571 return ret; 7572 } 7573 7574 /* Disable e-tag tunnel */ 7575 static int 7576 ixgbe_e_tag_disable(struct ixgbe_hw *hw) 7577 { 7578 uint32_t etag_etype; 7579 7580 if (hw->mac.type != ixgbe_mac_X550 && 7581 hw->mac.type != ixgbe_mac_X550EM_x && 7582 hw->mac.type != ixgbe_mac_X550EM_a) { 7583 return -ENOTSUP; 7584 } 7585 7586 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7587 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID; 7588 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7589 IXGBE_WRITE_FLUSH(hw); 7590 7591 return 0; 7592 } 7593 7594 /* Disable l2 tunnel */ 7595 static int 7596 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev, 7597 enum rte_eth_tunnel_type l2_tunnel_type) 7598 { 7599 int ret = 0; 7600 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7601 struct ixgbe_l2_tn_info *l2_tn_info = 7602 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7603 7604 switch (l2_tunnel_type) { 7605 case RTE_L2_TUNNEL_TYPE_E_TAG: 7606 l2_tn_info->e_tag_en = FALSE; 7607 ret = ixgbe_e_tag_disable(hw); 7608 break; 7609 default: 7610 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7611 ret = -EINVAL; 7612 break; 7613 } 7614 7615 return ret; 7616 } 7617 7618 static int 7619 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev, 7620 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7621 { 7622 int ret = 0; 7623 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7624 uint32_t i, rar_entries; 7625 uint32_t rar_low, rar_high; 7626 7627 if (hw->mac.type != ixgbe_mac_X550 && 7628 hw->mac.type != ixgbe_mac_X550EM_x && 7629 hw->mac.type != ixgbe_mac_X550EM_a) { 7630 return -ENOTSUP; 7631 } 7632 7633 rar_entries = ixgbe_get_num_rx_addrs(hw); 7634 7635 for (i = 1; i < rar_entries; i++) { 7636 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7637 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 7638 if ((rar_high & IXGBE_RAH_AV) && 7639 (rar_high & IXGBE_RAH_ADTYPE) && 7640 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) == 7641 l2_tunnel->tunnel_id)) { 7642 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 7643 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 7644 7645 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL); 7646 7647 return ret; 7648 } 7649 } 7650 7651 return ret; 7652 } 7653 7654 static int 7655 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev, 7656 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7657 { 7658 int ret = 0; 7659 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7660 uint32_t i, rar_entries; 7661 uint32_t rar_low, rar_high; 7662 7663 if (hw->mac.type != ixgbe_mac_X550 && 7664 hw->mac.type != ixgbe_mac_X550EM_x && 7665 hw->mac.type != ixgbe_mac_X550EM_a) { 7666 return -ENOTSUP; 7667 } 7668 7669 /* One entry for one tunnel. Try to remove potential existing entry. */ 7670 ixgbe_e_tag_filter_del(dev, l2_tunnel); 7671 7672 rar_entries = ixgbe_get_num_rx_addrs(hw); 7673 7674 for (i = 1; i < rar_entries; i++) { 7675 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7676 if (rar_high & IXGBE_RAH_AV) { 7677 continue; 7678 } else { 7679 ixgbe_set_vmdq(hw, i, l2_tunnel->pool); 7680 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE; 7681 rar_low = l2_tunnel->tunnel_id; 7682 7683 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low); 7684 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high); 7685 7686 return ret; 7687 } 7688 } 7689 7690 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full." 7691 " Please remove a rule before adding a new one."); 7692 return -EINVAL; 7693 } 7694 7695 static inline struct ixgbe_l2_tn_filter * 7696 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info, 7697 struct ixgbe_l2_tn_key *key) 7698 { 7699 int ret; 7700 7701 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key); 7702 if (ret < 0) 7703 return NULL; 7704 7705 return l2_tn_info->hash_map[ret]; 7706 } 7707 7708 static inline int 7709 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7710 struct ixgbe_l2_tn_filter *l2_tn_filter) 7711 { 7712 int ret; 7713 7714 ret = rte_hash_add_key(l2_tn_info->hash_handle, 7715 &l2_tn_filter->key); 7716 7717 if (ret < 0) { 7718 PMD_DRV_LOG(ERR, 7719 "Failed to insert L2 tunnel filter" 7720 " to hash table %d!", 7721 ret); 7722 return ret; 7723 } 7724 7725 l2_tn_info->hash_map[ret] = l2_tn_filter; 7726 7727 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 7728 7729 return 0; 7730 } 7731 7732 static inline int 7733 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7734 struct ixgbe_l2_tn_key *key) 7735 { 7736 int ret; 7737 struct ixgbe_l2_tn_filter *l2_tn_filter; 7738 7739 ret = rte_hash_del_key(l2_tn_info->hash_handle, key); 7740 7741 if (ret < 0) { 7742 PMD_DRV_LOG(ERR, 7743 "No such L2 tunnel filter to delete %d!", 7744 ret); 7745 return ret; 7746 } 7747 7748 l2_tn_filter = l2_tn_info->hash_map[ret]; 7749 l2_tn_info->hash_map[ret] = NULL; 7750 7751 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 7752 rte_free(l2_tn_filter); 7753 7754 return 0; 7755 } 7756 7757 /* Add l2 tunnel filter */ 7758 int 7759 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 7760 struct rte_eth_l2_tunnel_conf *l2_tunnel, 7761 bool restore) 7762 { 7763 int ret; 7764 struct ixgbe_l2_tn_info *l2_tn_info = 7765 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7766 struct ixgbe_l2_tn_key key; 7767 struct ixgbe_l2_tn_filter *node; 7768 7769 if (!restore) { 7770 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 7771 key.tn_id = l2_tunnel->tunnel_id; 7772 7773 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key); 7774 7775 if (node) { 7776 PMD_DRV_LOG(ERR, 7777 "The L2 tunnel filter already exists!"); 7778 return -EINVAL; 7779 } 7780 7781 node = rte_zmalloc("ixgbe_l2_tn", 7782 sizeof(struct ixgbe_l2_tn_filter), 7783 0); 7784 if (!node) 7785 return -ENOMEM; 7786 7787 rte_memcpy(&node->key, 7788 &key, 7789 sizeof(struct ixgbe_l2_tn_key)); 7790 node->pool = l2_tunnel->pool; 7791 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node); 7792 if (ret < 0) { 7793 rte_free(node); 7794 return ret; 7795 } 7796 } 7797 7798 switch (l2_tunnel->l2_tunnel_type) { 7799 case RTE_L2_TUNNEL_TYPE_E_TAG: 7800 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel); 7801 break; 7802 default: 7803 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7804 ret = -EINVAL; 7805 break; 7806 } 7807 7808 if ((!restore) && (ret < 0)) 7809 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 7810 7811 return ret; 7812 } 7813 7814 /* Delete l2 tunnel filter */ 7815 int 7816 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 7817 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7818 { 7819 int ret; 7820 struct ixgbe_l2_tn_info *l2_tn_info = 7821 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7822 struct ixgbe_l2_tn_key key; 7823 7824 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 7825 key.tn_id = l2_tunnel->tunnel_id; 7826 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 7827 if (ret < 0) 7828 return ret; 7829 7830 switch (l2_tunnel->l2_tunnel_type) { 7831 case RTE_L2_TUNNEL_TYPE_E_TAG: 7832 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel); 7833 break; 7834 default: 7835 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7836 ret = -EINVAL; 7837 break; 7838 } 7839 7840 return ret; 7841 } 7842 7843 /** 7844 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter. 7845 * @dev: pointer to rte_eth_dev structure 7846 * @filter_op:operation will be taken. 7847 * @arg: a pointer to specific structure corresponding to the filter_op 7848 */ 7849 static int 7850 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev, 7851 enum rte_filter_op filter_op, 7852 void *arg) 7853 { 7854 int ret; 7855 7856 if (filter_op == RTE_ETH_FILTER_NOP) 7857 return 0; 7858 7859 if (arg == NULL) { 7860 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 7861 filter_op); 7862 return -EINVAL; 7863 } 7864 7865 switch (filter_op) { 7866 case RTE_ETH_FILTER_ADD: 7867 ret = ixgbe_dev_l2_tunnel_filter_add 7868 (dev, 7869 (struct rte_eth_l2_tunnel_conf *)arg, 7870 FALSE); 7871 break; 7872 case RTE_ETH_FILTER_DELETE: 7873 ret = ixgbe_dev_l2_tunnel_filter_del 7874 (dev, 7875 (struct rte_eth_l2_tunnel_conf *)arg); 7876 break; 7877 default: 7878 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 7879 ret = -EINVAL; 7880 break; 7881 } 7882 return ret; 7883 } 7884 7885 static int 7886 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en) 7887 { 7888 int ret = 0; 7889 uint32_t ctrl; 7890 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7891 7892 if (hw->mac.type != ixgbe_mac_X550 && 7893 hw->mac.type != ixgbe_mac_X550EM_x && 7894 hw->mac.type != ixgbe_mac_X550EM_a) { 7895 return -ENOTSUP; 7896 } 7897 7898 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 7899 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 7900 if (en) 7901 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG; 7902 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 7903 7904 return ret; 7905 } 7906 7907 /* Enable l2 tunnel forwarding */ 7908 static int 7909 ixgbe_dev_l2_tunnel_forwarding_enable 7910 (struct rte_eth_dev *dev, 7911 enum rte_eth_tunnel_type l2_tunnel_type) 7912 { 7913 struct ixgbe_l2_tn_info *l2_tn_info = 7914 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7915 int ret = 0; 7916 7917 switch (l2_tunnel_type) { 7918 case RTE_L2_TUNNEL_TYPE_E_TAG: 7919 l2_tn_info->e_tag_fwd_en = TRUE; 7920 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1); 7921 break; 7922 default: 7923 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7924 ret = -EINVAL; 7925 break; 7926 } 7927 7928 return ret; 7929 } 7930 7931 /* Disable l2 tunnel forwarding */ 7932 static int 7933 ixgbe_dev_l2_tunnel_forwarding_disable 7934 (struct rte_eth_dev *dev, 7935 enum rte_eth_tunnel_type l2_tunnel_type) 7936 { 7937 struct ixgbe_l2_tn_info *l2_tn_info = 7938 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7939 int ret = 0; 7940 7941 switch (l2_tunnel_type) { 7942 case RTE_L2_TUNNEL_TYPE_E_TAG: 7943 l2_tn_info->e_tag_fwd_en = FALSE; 7944 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0); 7945 break; 7946 default: 7947 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7948 ret = -EINVAL; 7949 break; 7950 } 7951 7952 return ret; 7953 } 7954 7955 static int 7956 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev, 7957 struct rte_eth_l2_tunnel_conf *l2_tunnel, 7958 bool en) 7959 { 7960 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 7961 int ret = 0; 7962 uint32_t vmtir, vmvir; 7963 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7964 7965 if (l2_tunnel->vf_id >= pci_dev->max_vfs) { 7966 PMD_DRV_LOG(ERR, 7967 "VF id %u should be less than %u", 7968 l2_tunnel->vf_id, 7969 pci_dev->max_vfs); 7970 return -EINVAL; 7971 } 7972 7973 if (hw->mac.type != ixgbe_mac_X550 && 7974 hw->mac.type != ixgbe_mac_X550EM_x && 7975 hw->mac.type != ixgbe_mac_X550EM_a) { 7976 return -ENOTSUP; 7977 } 7978 7979 if (en) 7980 vmtir = l2_tunnel->tunnel_id; 7981 else 7982 vmtir = 0; 7983 7984 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir); 7985 7986 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id)); 7987 vmvir &= ~IXGBE_VMVIR_TAGA_MASK; 7988 if (en) 7989 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT; 7990 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir); 7991 7992 return ret; 7993 } 7994 7995 /* Enable l2 tunnel tag insertion */ 7996 static int 7997 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev, 7998 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7999 { 8000 int ret = 0; 8001 8002 switch (l2_tunnel->l2_tunnel_type) { 8003 case RTE_L2_TUNNEL_TYPE_E_TAG: 8004 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1); 8005 break; 8006 default: 8007 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8008 ret = -EINVAL; 8009 break; 8010 } 8011 8012 return ret; 8013 } 8014 8015 /* Disable l2 tunnel tag insertion */ 8016 static int 8017 ixgbe_dev_l2_tunnel_insertion_disable 8018 (struct rte_eth_dev *dev, 8019 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8020 { 8021 int ret = 0; 8022 8023 switch (l2_tunnel->l2_tunnel_type) { 8024 case RTE_L2_TUNNEL_TYPE_E_TAG: 8025 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0); 8026 break; 8027 default: 8028 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8029 ret = -EINVAL; 8030 break; 8031 } 8032 8033 return ret; 8034 } 8035 8036 static int 8037 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev, 8038 bool en) 8039 { 8040 int ret = 0; 8041 uint32_t qde; 8042 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8043 8044 if (hw->mac.type != ixgbe_mac_X550 && 8045 hw->mac.type != ixgbe_mac_X550EM_x && 8046 hw->mac.type != ixgbe_mac_X550EM_a) { 8047 return -ENOTSUP; 8048 } 8049 8050 qde = IXGBE_READ_REG(hw, IXGBE_QDE); 8051 if (en) 8052 qde |= IXGBE_QDE_STRIP_TAG; 8053 else 8054 qde &= ~IXGBE_QDE_STRIP_TAG; 8055 qde &= ~IXGBE_QDE_READ; 8056 qde |= IXGBE_QDE_WRITE; 8057 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde); 8058 8059 return ret; 8060 } 8061 8062 /* Enable l2 tunnel tag stripping */ 8063 static int 8064 ixgbe_dev_l2_tunnel_stripping_enable 8065 (struct rte_eth_dev *dev, 8066 enum rte_eth_tunnel_type l2_tunnel_type) 8067 { 8068 int ret = 0; 8069 8070 switch (l2_tunnel_type) { 8071 case RTE_L2_TUNNEL_TYPE_E_TAG: 8072 ret = ixgbe_e_tag_stripping_en_dis(dev, 1); 8073 break; 8074 default: 8075 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8076 ret = -EINVAL; 8077 break; 8078 } 8079 8080 return ret; 8081 } 8082 8083 /* Disable l2 tunnel tag stripping */ 8084 static int 8085 ixgbe_dev_l2_tunnel_stripping_disable 8086 (struct rte_eth_dev *dev, 8087 enum rte_eth_tunnel_type l2_tunnel_type) 8088 { 8089 int ret = 0; 8090 8091 switch (l2_tunnel_type) { 8092 case RTE_L2_TUNNEL_TYPE_E_TAG: 8093 ret = ixgbe_e_tag_stripping_en_dis(dev, 0); 8094 break; 8095 default: 8096 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8097 ret = -EINVAL; 8098 break; 8099 } 8100 8101 return ret; 8102 } 8103 8104 /* Enable/disable l2 tunnel offload functions */ 8105 static int 8106 ixgbe_dev_l2_tunnel_offload_set 8107 (struct rte_eth_dev *dev, 8108 struct rte_eth_l2_tunnel_conf *l2_tunnel, 8109 uint32_t mask, 8110 uint8_t en) 8111 { 8112 int ret = 0; 8113 8114 if (l2_tunnel == NULL) 8115 return -EINVAL; 8116 8117 ret = -EINVAL; 8118 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) { 8119 if (en) 8120 ret = ixgbe_dev_l2_tunnel_enable( 8121 dev, 8122 l2_tunnel->l2_tunnel_type); 8123 else 8124 ret = ixgbe_dev_l2_tunnel_disable( 8125 dev, 8126 l2_tunnel->l2_tunnel_type); 8127 } 8128 8129 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) { 8130 if (en) 8131 ret = ixgbe_dev_l2_tunnel_insertion_enable( 8132 dev, 8133 l2_tunnel); 8134 else 8135 ret = ixgbe_dev_l2_tunnel_insertion_disable( 8136 dev, 8137 l2_tunnel); 8138 } 8139 8140 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) { 8141 if (en) 8142 ret = ixgbe_dev_l2_tunnel_stripping_enable( 8143 dev, 8144 l2_tunnel->l2_tunnel_type); 8145 else 8146 ret = ixgbe_dev_l2_tunnel_stripping_disable( 8147 dev, 8148 l2_tunnel->l2_tunnel_type); 8149 } 8150 8151 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) { 8152 if (en) 8153 ret = ixgbe_dev_l2_tunnel_forwarding_enable( 8154 dev, 8155 l2_tunnel->l2_tunnel_type); 8156 else 8157 ret = ixgbe_dev_l2_tunnel_forwarding_disable( 8158 dev, 8159 l2_tunnel->l2_tunnel_type); 8160 } 8161 8162 return ret; 8163 } 8164 8165 static int 8166 ixgbe_update_vxlan_port(struct ixgbe_hw *hw, 8167 uint16_t port) 8168 { 8169 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port); 8170 IXGBE_WRITE_FLUSH(hw); 8171 8172 return 0; 8173 } 8174 8175 /* There's only one register for VxLAN UDP port. 8176 * So, we cannot add several ports. Will update it. 8177 */ 8178 static int 8179 ixgbe_add_vxlan_port(struct ixgbe_hw *hw, 8180 uint16_t port) 8181 { 8182 if (port == 0) { 8183 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 8184 return -EINVAL; 8185 } 8186 8187 return ixgbe_update_vxlan_port(hw, port); 8188 } 8189 8190 /* We cannot delete the VxLAN port. For there's a register for VxLAN 8191 * UDP port, it must have a value. 8192 * So, will reset it to the original value 0. 8193 */ 8194 static int 8195 ixgbe_del_vxlan_port(struct ixgbe_hw *hw, 8196 uint16_t port) 8197 { 8198 uint16_t cur_port; 8199 8200 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL); 8201 8202 if (cur_port != port) { 8203 PMD_DRV_LOG(ERR, "Port %u does not exist.", port); 8204 return -EINVAL; 8205 } 8206 8207 return ixgbe_update_vxlan_port(hw, 0); 8208 } 8209 8210 /* Add UDP tunneling port */ 8211 static int 8212 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 8213 struct rte_eth_udp_tunnel *udp_tunnel) 8214 { 8215 int ret = 0; 8216 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8217 8218 if (hw->mac.type != ixgbe_mac_X550 && 8219 hw->mac.type != ixgbe_mac_X550EM_x && 8220 hw->mac.type != ixgbe_mac_X550EM_a) { 8221 return -ENOTSUP; 8222 } 8223 8224 if (udp_tunnel == NULL) 8225 return -EINVAL; 8226 8227 switch (udp_tunnel->prot_type) { 8228 case RTE_TUNNEL_TYPE_VXLAN: 8229 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port); 8230 break; 8231 8232 case RTE_TUNNEL_TYPE_GENEVE: 8233 case RTE_TUNNEL_TYPE_TEREDO: 8234 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8235 ret = -EINVAL; 8236 break; 8237 8238 default: 8239 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8240 ret = -EINVAL; 8241 break; 8242 } 8243 8244 return ret; 8245 } 8246 8247 /* Remove UDP tunneling port */ 8248 static int 8249 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 8250 struct rte_eth_udp_tunnel *udp_tunnel) 8251 { 8252 int ret = 0; 8253 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8254 8255 if (hw->mac.type != ixgbe_mac_X550 && 8256 hw->mac.type != ixgbe_mac_X550EM_x && 8257 hw->mac.type != ixgbe_mac_X550EM_a) { 8258 return -ENOTSUP; 8259 } 8260 8261 if (udp_tunnel == NULL) 8262 return -EINVAL; 8263 8264 switch (udp_tunnel->prot_type) { 8265 case RTE_TUNNEL_TYPE_VXLAN: 8266 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port); 8267 break; 8268 case RTE_TUNNEL_TYPE_GENEVE: 8269 case RTE_TUNNEL_TYPE_TEREDO: 8270 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8271 ret = -EINVAL; 8272 break; 8273 default: 8274 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8275 ret = -EINVAL; 8276 break; 8277 } 8278 8279 return ret; 8280 } 8281 8282 static void 8283 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev) 8284 { 8285 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8286 8287 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI); 8288 } 8289 8290 static void 8291 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev) 8292 { 8293 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8294 8295 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI); 8296 } 8297 8298 static void ixgbevf_mbx_process(struct rte_eth_dev *dev) 8299 { 8300 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8301 u32 in_msg = 0; 8302 8303 /* peek the message first */ 8304 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM); 8305 8306 /* PF reset VF event */ 8307 if (in_msg == IXGBE_PF_CONTROL_MSG) { 8308 /* dummy mbx read to ack pf */ 8309 if (ixgbe_read_mbx(hw, &in_msg, 1, 0)) 8310 return; 8311 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 8312 NULL); 8313 } 8314 } 8315 8316 static int 8317 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev) 8318 { 8319 uint32_t eicr; 8320 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8321 struct ixgbe_interrupt *intr = 8322 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8323 ixgbevf_intr_disable(dev); 8324 8325 /* read-on-clear nic registers here */ 8326 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR); 8327 intr->flags = 0; 8328 8329 /* only one misc vector supported - mailbox */ 8330 eicr &= IXGBE_VTEICR_MASK; 8331 if (eicr == IXGBE_MISC_VEC_ID) 8332 intr->flags |= IXGBE_FLAG_MAILBOX; 8333 8334 return 0; 8335 } 8336 8337 static int 8338 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev) 8339 { 8340 struct ixgbe_interrupt *intr = 8341 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8342 8343 if (intr->flags & IXGBE_FLAG_MAILBOX) { 8344 ixgbevf_mbx_process(dev); 8345 intr->flags &= ~IXGBE_FLAG_MAILBOX; 8346 } 8347 8348 ixgbevf_intr_enable(dev); 8349 8350 return 0; 8351 } 8352 8353 static void 8354 ixgbevf_dev_interrupt_handler(void *param) 8355 { 8356 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 8357 8358 ixgbevf_dev_interrupt_get_status(dev); 8359 ixgbevf_dev_interrupt_action(dev); 8360 } 8361 8362 /** 8363 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path 8364 * @hw: pointer to hardware structure 8365 * 8366 * Stops the transmit data path and waits for the HW to internally empty 8367 * the Tx security block 8368 **/ 8369 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw) 8370 { 8371 #define IXGBE_MAX_SECTX_POLL 40 8372 8373 int i; 8374 int sectxreg; 8375 8376 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8377 sectxreg |= IXGBE_SECTXCTRL_TX_DIS; 8378 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8379 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) { 8380 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT); 8381 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY) 8382 break; 8383 /* Use interrupt-safe sleep just in case */ 8384 usec_delay(1000); 8385 } 8386 8387 /* For informational purposes only */ 8388 if (i >= IXGBE_MAX_SECTX_POLL) 8389 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security " 8390 "path fully disabled. Continuing with init."); 8391 8392 return IXGBE_SUCCESS; 8393 } 8394 8395 /** 8396 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path 8397 * @hw: pointer to hardware structure 8398 * 8399 * Enables the transmit data path. 8400 **/ 8401 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw) 8402 { 8403 uint32_t sectxreg; 8404 8405 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8406 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS; 8407 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8408 IXGBE_WRITE_FLUSH(hw); 8409 8410 return IXGBE_SUCCESS; 8411 } 8412 8413 /* restore n-tuple filter */ 8414 static inline void 8415 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev) 8416 { 8417 struct ixgbe_filter_info *filter_info = 8418 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8419 struct ixgbe_5tuple_filter *node; 8420 8421 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) { 8422 ixgbe_inject_5tuple_filter(dev, node); 8423 } 8424 } 8425 8426 /* restore ethernet type filter */ 8427 static inline void 8428 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev) 8429 { 8430 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8431 struct ixgbe_filter_info *filter_info = 8432 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8433 int i; 8434 8435 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8436 if (filter_info->ethertype_mask & (1 << i)) { 8437 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 8438 filter_info->ethertype_filters[i].etqf); 8439 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 8440 filter_info->ethertype_filters[i].etqs); 8441 IXGBE_WRITE_FLUSH(hw); 8442 } 8443 } 8444 } 8445 8446 /* restore SYN filter */ 8447 static inline void 8448 ixgbe_syn_filter_restore(struct rte_eth_dev *dev) 8449 { 8450 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8451 struct ixgbe_filter_info *filter_info = 8452 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8453 uint32_t synqf; 8454 8455 synqf = filter_info->syn_info; 8456 8457 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 8458 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 8459 IXGBE_WRITE_FLUSH(hw); 8460 } 8461 } 8462 8463 /* restore L2 tunnel filter */ 8464 static inline void 8465 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev) 8466 { 8467 struct ixgbe_l2_tn_info *l2_tn_info = 8468 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8469 struct ixgbe_l2_tn_filter *node; 8470 struct rte_eth_l2_tunnel_conf l2_tn_conf; 8471 8472 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) { 8473 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type; 8474 l2_tn_conf.tunnel_id = node->key.tn_id; 8475 l2_tn_conf.pool = node->pool; 8476 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE); 8477 } 8478 } 8479 8480 /* restore rss filter */ 8481 static inline void 8482 ixgbe_rss_filter_restore(struct rte_eth_dev *dev) 8483 { 8484 struct ixgbe_filter_info *filter_info = 8485 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8486 8487 if (filter_info->rss_info.conf.queue_num) 8488 ixgbe_config_rss_filter(dev, 8489 &filter_info->rss_info, TRUE); 8490 } 8491 8492 static int 8493 ixgbe_filter_restore(struct rte_eth_dev *dev) 8494 { 8495 ixgbe_ntuple_filter_restore(dev); 8496 ixgbe_ethertype_filter_restore(dev); 8497 ixgbe_syn_filter_restore(dev); 8498 ixgbe_fdir_filter_restore(dev); 8499 ixgbe_l2_tn_filter_restore(dev); 8500 ixgbe_rss_filter_restore(dev); 8501 8502 return 0; 8503 } 8504 8505 static void 8506 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev) 8507 { 8508 struct ixgbe_l2_tn_info *l2_tn_info = 8509 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8510 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8511 8512 if (l2_tn_info->e_tag_en) 8513 (void)ixgbe_e_tag_enable(hw); 8514 8515 if (l2_tn_info->e_tag_fwd_en) 8516 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1); 8517 8518 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type); 8519 } 8520 8521 /* remove all the n-tuple filters */ 8522 void 8523 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev) 8524 { 8525 struct ixgbe_filter_info *filter_info = 8526 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8527 struct ixgbe_5tuple_filter *p_5tuple; 8528 8529 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) 8530 ixgbe_remove_5tuple_filter(dev, p_5tuple); 8531 } 8532 8533 /* remove all the ether type filters */ 8534 void 8535 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev) 8536 { 8537 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8538 struct ixgbe_filter_info *filter_info = 8539 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8540 int i; 8541 8542 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8543 if (filter_info->ethertype_mask & (1 << i) && 8544 !filter_info->ethertype_filters[i].conf) { 8545 (void)ixgbe_ethertype_filter_remove(filter_info, 8546 (uint8_t)i); 8547 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0); 8548 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0); 8549 IXGBE_WRITE_FLUSH(hw); 8550 } 8551 } 8552 } 8553 8554 /* remove the SYN filter */ 8555 void 8556 ixgbe_clear_syn_filter(struct rte_eth_dev *dev) 8557 { 8558 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8559 struct ixgbe_filter_info *filter_info = 8560 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8561 8562 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) { 8563 filter_info->syn_info = 0; 8564 8565 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0); 8566 IXGBE_WRITE_FLUSH(hw); 8567 } 8568 } 8569 8570 /* remove all the L2 tunnel filters */ 8571 int 8572 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev) 8573 { 8574 struct ixgbe_l2_tn_info *l2_tn_info = 8575 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8576 struct ixgbe_l2_tn_filter *l2_tn_filter; 8577 struct rte_eth_l2_tunnel_conf l2_tn_conf; 8578 int ret = 0; 8579 8580 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 8581 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type; 8582 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id; 8583 l2_tn_conf.pool = l2_tn_filter->pool; 8584 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf); 8585 if (ret < 0) 8586 return ret; 8587 } 8588 8589 return 0; 8590 } 8591 8592 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd); 8593 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map); 8594 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 8595 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd); 8596 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map); 8597 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci"); 8598 8599 RTE_INIT(ixgbe_init_log) 8600 { 8601 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init"); 8602 if (ixgbe_logtype_init >= 0) 8603 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE); 8604 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver"); 8605 if (ixgbe_logtype_driver >= 0) 8606 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE); 8607 } 8608