1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <inttypes.h> 13 #include <netinet/in.h> 14 #include <rte_string_fns.h> 15 #include <rte_byteorder.h> 16 #include <rte_common.h> 17 #include <rte_cycles.h> 18 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_bus_pci.h> 24 #include <rte_branch_prediction.h> 25 #include <rte_memory.h> 26 #include <rte_kvargs.h> 27 #include <rte_eal.h> 28 #include <rte_alarm.h> 29 #include <rte_ether.h> 30 #include <rte_ethdev_driver.h> 31 #include <rte_ethdev_pci.h> 32 #include <rte_malloc.h> 33 #include <rte_random.h> 34 #include <rte_dev.h> 35 #include <rte_hash_crc.h> 36 #ifdef RTE_LIBRTE_SECURITY 37 #include <rte_security_driver.h> 38 #endif 39 40 #include "ixgbe_logs.h" 41 #include "base/ixgbe_api.h" 42 #include "base/ixgbe_vf.h" 43 #include "base/ixgbe_common.h" 44 #include "ixgbe_ethdev.h" 45 #include "ixgbe_bypass.h" 46 #include "ixgbe_rxtx.h" 47 #include "base/ixgbe_type.h" 48 #include "base/ixgbe_phy.h" 49 #include "ixgbe_regs.h" 50 51 /* 52 * High threshold controlling when to start sending XOFF frames. Must be at 53 * least 8 bytes less than receive packet buffer size. This value is in units 54 * of 1024 bytes. 55 */ 56 #define IXGBE_FC_HI 0x80 57 58 /* 59 * Low threshold controlling when to start sending XON frames. This value is 60 * in units of 1024 bytes. 61 */ 62 #define IXGBE_FC_LO 0x40 63 64 /* Timer value included in XOFF frames. */ 65 #define IXGBE_FC_PAUSE 0x680 66 67 /*Default value of Max Rx Queue*/ 68 #define IXGBE_MAX_RX_QUEUE_NUM 128 69 70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */ 71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */ 72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */ 73 74 #define IXGBE_MMW_SIZE_DEFAULT 0x4 75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14 76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */ 77 78 /* 79 * Default values for RX/TX configuration 80 */ 81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32 82 #define IXGBE_DEFAULT_RX_PTHRESH 8 83 #define IXGBE_DEFAULT_RX_HTHRESH 8 84 #define IXGBE_DEFAULT_RX_WTHRESH 0 85 86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32 87 #define IXGBE_DEFAULT_TX_PTHRESH 32 88 #define IXGBE_DEFAULT_TX_HTHRESH 0 89 #define IXGBE_DEFAULT_TX_WTHRESH 0 90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32 91 92 /* Bit shift and mask */ 93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2) 94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t) 95 #define IXGBE_8_BIT_WIDTH CHAR_BIT 96 #define IXGBE_8_BIT_MASK UINT8_MAX 97 98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */ 99 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0])) 101 102 /* Additional timesync values. */ 103 #define NSEC_PER_SEC 1000000000L 104 #define IXGBE_INCVAL_10GB 0x66666666 105 #define IXGBE_INCVAL_1GB 0x40000000 106 #define IXGBE_INCVAL_100 0x50000000 107 #define IXGBE_INCVAL_SHIFT_10GB 28 108 #define IXGBE_INCVAL_SHIFT_1GB 24 109 #define IXGBE_INCVAL_SHIFT_100 21 110 #define IXGBE_INCVAL_SHIFT_82599 7 111 #define IXGBE_INCPER_SHIFT_82599 24 112 113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL 114 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000 117 #define IXGBE_ETAG_ETYPE 0x00005084 118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff 119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000 120 #define IXGBE_RAH_ADTYPE 0x40000000 121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff 122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */ 125 #define IXGBE_QDE_STRIP_TAG 0x00000004 126 #define IXGBE_VTEICR_MASK 0x07 127 128 #define IXGBE_EXVET_VET_EXT_SHIFT 16 129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000 130 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk" 132 133 static const char * const ixgbevf_valid_arguments[] = { 134 IXGBEVF_DEVARG_PFLINK_FULLCHK, 135 NULL 136 }; 137 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev); 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev); 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev); 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev); 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev); 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev); 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev); 146 static int ixgbe_dev_start(struct rte_eth_dev *dev); 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev); 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev); 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev); 150 static void ixgbe_dev_close(struct rte_eth_dev *dev); 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev); 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev, 157 int wait_to_complete); 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev, 159 struct rte_eth_stats *stats); 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev, 161 struct rte_eth_xstat *xstats, unsigned n); 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, 163 struct rte_eth_xstat *xstats, unsigned n); 164 static int 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 166 uint64_t *values, unsigned int n); 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev); 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev); 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 170 struct rte_eth_xstat_name *xstats_names, 171 unsigned int size); 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev, 173 struct rte_eth_xstat_name *xstats_names, unsigned limit); 174 static int ixgbe_dev_xstats_get_names_by_id( 175 struct rte_eth_dev *dev, 176 struct rte_eth_xstat_name *xstats_names, 177 const uint64_t *ids, 178 unsigned int limit); 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 180 uint16_t queue_id, 181 uint8_t stat_idx, 182 uint8_t is_rx); 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 184 size_t fw_size); 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev, 186 struct rte_eth_dev_info *dev_info); 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev, 189 struct rte_eth_dev_info *dev_info); 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 191 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev, 193 uint16_t vlan_id, int on); 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 195 enum rte_vlan_type vlan_type, 196 uint16_t tpid_id); 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, 198 uint16_t queue, bool on); 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, 200 int on); 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, 202 int mask); 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask); 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask); 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue); 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue); 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev); 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev); 209 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev); 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev); 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, 213 struct rte_eth_fc_conf *fc_conf); 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, 215 struct rte_eth_fc_conf *fc_conf); 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 217 struct rte_eth_pfc_conf *pfc_conf); 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 219 struct rte_eth_rss_reta_entry64 *reta_conf, 220 uint16_t reta_size); 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 222 struct rte_eth_rss_reta_entry64 *reta_conf, 223 uint16_t reta_size); 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev); 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev); 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev); 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev); 230 static void ixgbe_dev_interrupt_handler(void *param); 231 static void ixgbe_dev_interrupt_delayed_handler(void *param); 232 static void ixgbe_dev_setup_link_alarm_handler(void *param); 233 234 static int ixgbe_add_rar(struct rte_eth_dev *dev, 235 struct rte_ether_addr *mac_addr, 236 uint32_t index, uint32_t pool); 237 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index); 238 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, 239 struct rte_ether_addr *mac_addr); 240 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config); 241 static bool is_device_supported(struct rte_eth_dev *dev, 242 struct rte_pci_driver *drv); 243 244 /* For Virtual Function support */ 245 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev); 246 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev); 247 static int ixgbevf_dev_configure(struct rte_eth_dev *dev); 248 static int ixgbevf_dev_start(struct rte_eth_dev *dev); 249 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev, 250 int wait_to_complete); 251 static void ixgbevf_dev_stop(struct rte_eth_dev *dev); 252 static void ixgbevf_dev_close(struct rte_eth_dev *dev); 253 static int ixgbevf_dev_reset(struct rte_eth_dev *dev); 254 static void ixgbevf_intr_disable(struct rte_eth_dev *dev); 255 static void ixgbevf_intr_enable(struct rte_eth_dev *dev); 256 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev, 257 struct rte_eth_stats *stats); 258 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev); 259 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, 260 uint16_t vlan_id, int on); 261 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, 262 uint16_t queue, int on); 263 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask); 264 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask); 265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on); 266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 267 uint16_t queue_id); 268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 269 uint16_t queue_id); 270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 271 uint8_t queue, uint8_t msix_vector); 272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev); 273 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev); 274 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev); 275 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev); 276 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev); 277 278 /* For Eth VMDQ APIs support */ 279 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct 280 rte_ether_addr * mac_addr, uint8_t on); 281 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on); 282 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 283 struct rte_eth_mirror_conf *mirror_conf, 284 uint8_t rule_id, uint8_t on); 285 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, 286 uint8_t rule_id); 287 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 288 uint16_t queue_id); 289 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 290 uint16_t queue_id); 291 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 292 uint8_t queue, uint8_t msix_vector); 293 static void ixgbe_configure_msix(struct rte_eth_dev *dev); 294 295 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev, 296 struct rte_ether_addr *mac_addr, 297 uint32_t index, uint32_t pool); 298 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index); 299 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 300 struct rte_ether_addr *mac_addr); 301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev, 302 struct rte_eth_syn_filter *filter); 303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev, 304 enum rte_filter_op filter_op, 305 void *arg); 306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 307 struct ixgbe_5tuple_filter *filter); 308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 309 struct ixgbe_5tuple_filter *filter); 310 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev, 311 enum rte_filter_op filter_op, 312 void *arg); 313 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev, 314 struct rte_eth_ntuple_filter *filter); 315 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev, 316 enum rte_filter_op filter_op, 317 void *arg); 318 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, 319 struct rte_eth_ethertype_filter *filter); 320 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 321 enum rte_filter_type filter_type, 322 enum rte_filter_op filter_op, 323 void *arg); 324 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 325 326 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 327 struct rte_ether_addr *mc_addr_set, 328 uint32_t nb_mc_addr); 329 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 330 struct rte_eth_dcb_info *dcb_info); 331 332 static int ixgbe_get_reg_length(struct rte_eth_dev *dev); 333 static int ixgbe_get_regs(struct rte_eth_dev *dev, 334 struct rte_dev_reg_info *regs); 335 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev); 336 static int ixgbe_get_eeprom(struct rte_eth_dev *dev, 337 struct rte_dev_eeprom_info *eeprom); 338 static int ixgbe_set_eeprom(struct rte_eth_dev *dev, 339 struct rte_dev_eeprom_info *eeprom); 340 341 static int ixgbe_get_module_info(struct rte_eth_dev *dev, 342 struct rte_eth_dev_module_info *modinfo); 343 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 344 struct rte_dev_eeprom_info *info); 345 346 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev); 347 static int ixgbevf_get_regs(struct rte_eth_dev *dev, 348 struct rte_dev_reg_info *regs); 349 350 static int ixgbe_timesync_enable(struct rte_eth_dev *dev); 351 static int ixgbe_timesync_disable(struct rte_eth_dev *dev); 352 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 353 struct timespec *timestamp, 354 uint32_t flags); 355 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 356 struct timespec *timestamp); 357 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 358 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev, 359 struct timespec *timestamp); 360 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev, 361 const struct timespec *timestamp); 362 static void ixgbevf_dev_interrupt_handler(void *param); 363 364 static int ixgbe_dev_l2_tunnel_eth_type_conf 365 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel); 366 static int ixgbe_dev_l2_tunnel_offload_set 367 (struct rte_eth_dev *dev, 368 struct rte_eth_l2_tunnel_conf *l2_tunnel, 369 uint32_t mask, 370 uint8_t en); 371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev, 372 enum rte_filter_op filter_op, 373 void *arg); 374 375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 376 struct rte_eth_udp_tunnel *udp_tunnel); 377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 378 struct rte_eth_udp_tunnel *udp_tunnel); 379 static int ixgbe_filter_restore(struct rte_eth_dev *dev); 380 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev); 381 382 /* 383 * Define VF Stats MACRO for Non "cleared on read" register 384 */ 385 #define UPDATE_VF_STAT(reg, last, cur) \ 386 { \ 387 uint32_t latest = IXGBE_READ_REG(hw, reg); \ 388 cur += (latest - last) & UINT_MAX; \ 389 last = latest; \ 390 } 391 392 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \ 393 { \ 394 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \ 395 u64 new_msb = IXGBE_READ_REG(hw, msb); \ 396 u64 latest = ((new_msb << 32) | new_lsb); \ 397 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \ 398 last = latest; \ 399 } 400 401 #define IXGBE_SET_HWSTRIP(h, q) do {\ 402 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 403 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 404 (h)->bitmap[idx] |= 1 << bit;\ 405 } while (0) 406 407 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\ 408 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 409 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 410 (h)->bitmap[idx] &= ~(1 << bit);\ 411 } while (0) 412 413 #define IXGBE_GET_HWSTRIP(h, q, r) do {\ 414 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 415 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 416 (r) = (h)->bitmap[idx] >> bit & 1;\ 417 } while (0) 418 419 int ixgbe_logtype_init; 420 int ixgbe_logtype_driver; 421 422 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX 423 int ixgbe_logtype_rx; 424 #endif 425 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX 426 int ixgbe_logtype_tx; 427 #endif 428 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE 429 int ixgbe_logtype_tx_free; 430 #endif 431 432 /* 433 * The set of PCI devices this driver supports 434 */ 435 static const struct rte_pci_id pci_id_ixgbe_map[] = { 436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) }, 437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) }, 438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) }, 439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) }, 440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) }, 441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) }, 442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) }, 443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) }, 444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) }, 445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) }, 446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) }, 447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) }, 448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) }, 449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) }, 450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) }, 451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) }, 452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) }, 453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) }, 454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) }, 455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) }, 456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) }, 457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) }, 458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) }, 459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) }, 460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) }, 461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) }, 462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) }, 463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) }, 464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) }, 465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) }, 466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) }, 467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) }, 468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) }, 469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) }, 470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) }, 471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) }, 472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) }, 473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) }, 474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) }, 475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) }, 476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) }, 477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) }, 478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) }, 479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) }, 480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) }, 481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) }, 482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) }, 483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) }, 484 #ifdef RTE_LIBRTE_IXGBE_BYPASS 485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) }, 486 #endif 487 { .vendor_id = 0, /* sentinel */ }, 488 }; 489 490 /* 491 * The set of PCI devices this driver supports (for 82599 VF) 492 */ 493 static const struct rte_pci_id pci_id_ixgbevf_map[] = { 494 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) }, 495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) }, 496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) }, 497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) }, 498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) }, 499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) }, 500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) }, 501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) }, 502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) }, 503 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) }, 504 { .vendor_id = 0, /* sentinel */ }, 505 }; 506 507 static const struct rte_eth_desc_lim rx_desc_lim = { 508 .nb_max = IXGBE_MAX_RING_DESC, 509 .nb_min = IXGBE_MIN_RING_DESC, 510 .nb_align = IXGBE_RXD_ALIGN, 511 }; 512 513 static const struct rte_eth_desc_lim tx_desc_lim = { 514 .nb_max = IXGBE_MAX_RING_DESC, 515 .nb_min = IXGBE_MIN_RING_DESC, 516 .nb_align = IXGBE_TXD_ALIGN, 517 .nb_seg_max = IXGBE_TX_MAX_SEG, 518 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG, 519 }; 520 521 static const struct eth_dev_ops ixgbe_eth_dev_ops = { 522 .dev_configure = ixgbe_dev_configure, 523 .dev_start = ixgbe_dev_start, 524 .dev_stop = ixgbe_dev_stop, 525 .dev_set_link_up = ixgbe_dev_set_link_up, 526 .dev_set_link_down = ixgbe_dev_set_link_down, 527 .dev_close = ixgbe_dev_close, 528 .dev_reset = ixgbe_dev_reset, 529 .promiscuous_enable = ixgbe_dev_promiscuous_enable, 530 .promiscuous_disable = ixgbe_dev_promiscuous_disable, 531 .allmulticast_enable = ixgbe_dev_allmulticast_enable, 532 .allmulticast_disable = ixgbe_dev_allmulticast_disable, 533 .link_update = ixgbe_dev_link_update, 534 .stats_get = ixgbe_dev_stats_get, 535 .xstats_get = ixgbe_dev_xstats_get, 536 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id, 537 .stats_reset = ixgbe_dev_stats_reset, 538 .xstats_reset = ixgbe_dev_xstats_reset, 539 .xstats_get_names = ixgbe_dev_xstats_get_names, 540 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id, 541 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set, 542 .fw_version_get = ixgbe_fw_version_get, 543 .dev_infos_get = ixgbe_dev_info_get, 544 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 545 .mtu_set = ixgbe_dev_mtu_set, 546 .vlan_filter_set = ixgbe_vlan_filter_set, 547 .vlan_tpid_set = ixgbe_vlan_tpid_set, 548 .vlan_offload_set = ixgbe_vlan_offload_set, 549 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set, 550 .rx_queue_start = ixgbe_dev_rx_queue_start, 551 .rx_queue_stop = ixgbe_dev_rx_queue_stop, 552 .tx_queue_start = ixgbe_dev_tx_queue_start, 553 .tx_queue_stop = ixgbe_dev_tx_queue_stop, 554 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 555 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable, 556 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable, 557 .rx_queue_release = ixgbe_dev_rx_queue_release, 558 .rx_queue_count = ixgbe_dev_rx_queue_count, 559 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done, 560 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status, 561 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status, 562 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 563 .tx_queue_release = ixgbe_dev_tx_queue_release, 564 .dev_led_on = ixgbe_dev_led_on, 565 .dev_led_off = ixgbe_dev_led_off, 566 .flow_ctrl_get = ixgbe_flow_ctrl_get, 567 .flow_ctrl_set = ixgbe_flow_ctrl_set, 568 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set, 569 .mac_addr_add = ixgbe_add_rar, 570 .mac_addr_remove = ixgbe_remove_rar, 571 .mac_addr_set = ixgbe_set_default_mac_addr, 572 .uc_hash_table_set = ixgbe_uc_hash_table_set, 573 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set, 574 .mirror_rule_set = ixgbe_mirror_rule_set, 575 .mirror_rule_reset = ixgbe_mirror_rule_reset, 576 .set_queue_rate_limit = ixgbe_set_queue_rate_limit, 577 .reta_update = ixgbe_dev_rss_reta_update, 578 .reta_query = ixgbe_dev_rss_reta_query, 579 .rss_hash_update = ixgbe_dev_rss_hash_update, 580 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 581 .filter_ctrl = ixgbe_dev_filter_ctrl, 582 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 583 .rxq_info_get = ixgbe_rxq_info_get, 584 .txq_info_get = ixgbe_txq_info_get, 585 .timesync_enable = ixgbe_timesync_enable, 586 .timesync_disable = ixgbe_timesync_disable, 587 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp, 588 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp, 589 .get_reg = ixgbe_get_regs, 590 .get_eeprom_length = ixgbe_get_eeprom_length, 591 .get_eeprom = ixgbe_get_eeprom, 592 .set_eeprom = ixgbe_set_eeprom, 593 .get_module_info = ixgbe_get_module_info, 594 .get_module_eeprom = ixgbe_get_module_eeprom, 595 .get_dcb_info = ixgbe_dev_get_dcb_info, 596 .timesync_adjust_time = ixgbe_timesync_adjust_time, 597 .timesync_read_time = ixgbe_timesync_read_time, 598 .timesync_write_time = ixgbe_timesync_write_time, 599 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf, 600 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set, 601 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add, 602 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del, 603 .tm_ops_get = ixgbe_tm_ops_get, 604 }; 605 606 /* 607 * dev_ops for virtual function, bare necessities for basic vf 608 * operation have been implemented 609 */ 610 static const struct eth_dev_ops ixgbevf_eth_dev_ops = { 611 .dev_configure = ixgbevf_dev_configure, 612 .dev_start = ixgbevf_dev_start, 613 .dev_stop = ixgbevf_dev_stop, 614 .link_update = ixgbevf_dev_link_update, 615 .stats_get = ixgbevf_dev_stats_get, 616 .xstats_get = ixgbevf_dev_xstats_get, 617 .stats_reset = ixgbevf_dev_stats_reset, 618 .xstats_reset = ixgbevf_dev_stats_reset, 619 .xstats_get_names = ixgbevf_dev_xstats_get_names, 620 .dev_close = ixgbevf_dev_close, 621 .dev_reset = ixgbevf_dev_reset, 622 .promiscuous_enable = ixgbevf_dev_promiscuous_enable, 623 .promiscuous_disable = ixgbevf_dev_promiscuous_disable, 624 .allmulticast_enable = ixgbevf_dev_allmulticast_enable, 625 .allmulticast_disable = ixgbevf_dev_allmulticast_disable, 626 .dev_infos_get = ixgbevf_dev_info_get, 627 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 628 .mtu_set = ixgbevf_dev_set_mtu, 629 .vlan_filter_set = ixgbevf_vlan_filter_set, 630 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set, 631 .vlan_offload_set = ixgbevf_vlan_offload_set, 632 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 633 .rx_queue_release = ixgbe_dev_rx_queue_release, 634 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done, 635 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status, 636 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status, 637 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 638 .tx_queue_release = ixgbe_dev_tx_queue_release, 639 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable, 640 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable, 641 .mac_addr_add = ixgbevf_add_mac_addr, 642 .mac_addr_remove = ixgbevf_remove_mac_addr, 643 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 644 .rxq_info_get = ixgbe_rxq_info_get, 645 .txq_info_get = ixgbe_txq_info_get, 646 .mac_addr_set = ixgbevf_set_default_mac_addr, 647 .get_reg = ixgbevf_get_regs, 648 .reta_update = ixgbe_dev_rss_reta_update, 649 .reta_query = ixgbe_dev_rss_reta_query, 650 .rss_hash_update = ixgbe_dev_rss_hash_update, 651 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 652 }; 653 654 /* store statistics names and its offset in stats structure */ 655 struct rte_ixgbe_xstats_name_off { 656 char name[RTE_ETH_XSTATS_NAME_SIZE]; 657 unsigned offset; 658 }; 659 660 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = { 661 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)}, 662 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)}, 663 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)}, 664 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)}, 665 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)}, 666 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)}, 667 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)}, 668 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)}, 669 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)}, 670 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)}, 671 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)}, 672 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)}, 673 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)}, 674 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)}, 675 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 676 prc1023)}, 677 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 678 prc1522)}, 679 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)}, 680 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)}, 681 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)}, 682 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)}, 683 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)}, 684 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)}, 685 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)}, 686 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)}, 687 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)}, 688 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)}, 689 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)}, 690 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)}, 691 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)}, 692 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)}, 693 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)}, 694 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)}, 695 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 696 ptc1023)}, 697 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 698 ptc1522)}, 699 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)}, 700 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)}, 701 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)}, 702 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)}, 703 704 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats, 705 fdirustat_add)}, 706 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats, 707 fdirustat_remove)}, 708 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats, 709 fdirfstat_fadd)}, 710 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats, 711 fdirfstat_fremove)}, 712 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats, 713 fdirmatch)}, 714 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats, 715 fdirmiss)}, 716 717 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)}, 718 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)}, 719 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, 720 fclast)}, 721 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)}, 722 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)}, 723 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)}, 724 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)}, 725 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats, 726 fcoe_noddp)}, 727 {"rx_fcoe_no_direct_data_placement_ext_buff", 728 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)}, 729 730 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 731 lxontxc)}, 732 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 733 lxonrxc)}, 734 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 735 lxofftxc)}, 736 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 737 lxoffrxc)}, 738 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)}, 739 }; 740 741 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \ 742 sizeof(rte_ixgbe_stats_strings[0])) 743 744 /* MACsec statistics */ 745 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = { 746 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 747 out_pkts_untagged)}, 748 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats, 749 out_pkts_encrypted)}, 750 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats, 751 out_pkts_protected)}, 752 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats, 753 out_octets_encrypted)}, 754 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats, 755 out_octets_protected)}, 756 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 757 in_pkts_untagged)}, 758 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats, 759 in_pkts_badtag)}, 760 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats, 761 in_pkts_nosci)}, 762 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats, 763 in_pkts_unknownsci)}, 764 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats, 765 in_octets_decrypted)}, 766 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats, 767 in_octets_validated)}, 768 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats, 769 in_pkts_unchecked)}, 770 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats, 771 in_pkts_delayed)}, 772 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats, 773 in_pkts_late)}, 774 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats, 775 in_pkts_ok)}, 776 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats, 777 in_pkts_invalid)}, 778 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats, 779 in_pkts_notvalid)}, 780 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats, 781 in_pkts_unusedsa)}, 782 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats, 783 in_pkts_notusingsa)}, 784 }; 785 786 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \ 787 sizeof(rte_ixgbe_macsec_strings[0])) 788 789 /* Per-queue statistics */ 790 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = { 791 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)}, 792 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)}, 793 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)}, 794 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)}, 795 }; 796 797 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \ 798 sizeof(rte_ixgbe_rxq_strings[0])) 799 #define IXGBE_NB_RXQ_PRIO_VALUES 8 800 801 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = { 802 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)}, 803 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)}, 804 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats, 805 pxon2offc)}, 806 }; 807 808 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \ 809 sizeof(rte_ixgbe_txq_strings[0])) 810 #define IXGBE_NB_TXQ_PRIO_VALUES 8 811 812 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = { 813 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)}, 814 }; 815 816 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \ 817 sizeof(rte_ixgbevf_stats_strings[0])) 818 819 /* 820 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h. 821 */ 822 static inline int 823 ixgbe_is_sfp(struct ixgbe_hw *hw) 824 { 825 switch (hw->phy.type) { 826 case ixgbe_phy_sfp_avago: 827 case ixgbe_phy_sfp_ftl: 828 case ixgbe_phy_sfp_intel: 829 case ixgbe_phy_sfp_unknown: 830 case ixgbe_phy_sfp_passive_tyco: 831 case ixgbe_phy_sfp_passive_unknown: 832 return 1; 833 default: 834 return 0; 835 } 836 } 837 838 static inline int32_t 839 ixgbe_pf_reset_hw(struct ixgbe_hw *hw) 840 { 841 uint32_t ctrl_ext; 842 int32_t status; 843 844 status = ixgbe_reset_hw(hw); 845 846 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 847 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 848 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 849 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 850 IXGBE_WRITE_FLUSH(hw); 851 852 if (status == IXGBE_ERR_SFP_NOT_PRESENT) 853 status = IXGBE_SUCCESS; 854 return status; 855 } 856 857 static inline void 858 ixgbe_enable_intr(struct rte_eth_dev *dev) 859 { 860 struct ixgbe_interrupt *intr = 861 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 862 struct ixgbe_hw *hw = 863 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 864 865 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask); 866 IXGBE_WRITE_FLUSH(hw); 867 } 868 869 /* 870 * This function is based on ixgbe_disable_intr() in base/ixgbe.h. 871 */ 872 static void 873 ixgbe_disable_intr(struct ixgbe_hw *hw) 874 { 875 PMD_INIT_FUNC_TRACE(); 876 877 if (hw->mac.type == ixgbe_mac_82598EB) { 878 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0); 879 } else { 880 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000); 881 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0); 882 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0); 883 } 884 IXGBE_WRITE_FLUSH(hw); 885 } 886 887 /* 888 * This function resets queue statistics mapping registers. 889 * From Niantic datasheet, Initialization of Statistics section: 890 * "...if software requires the queue counters, the RQSMR and TQSM registers 891 * must be re-programmed following a device reset. 892 */ 893 static void 894 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw) 895 { 896 uint32_t i; 897 898 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) { 899 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0); 900 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0); 901 } 902 } 903 904 905 static int 906 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 907 uint16_t queue_id, 908 uint8_t stat_idx, 909 uint8_t is_rx) 910 { 911 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8 912 #define NB_QMAP_FIELDS_PER_QSM_REG 4 913 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f 914 915 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 916 struct ixgbe_stat_mapping_registers *stat_mappings = 917 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private); 918 uint32_t qsmr_mask = 0; 919 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK; 920 uint32_t q_map; 921 uint8_t n, offset; 922 923 if ((hw->mac.type != ixgbe_mac_82599EB) && 924 (hw->mac.type != ixgbe_mac_X540) && 925 (hw->mac.type != ixgbe_mac_X550) && 926 (hw->mac.type != ixgbe_mac_X550EM_x) && 927 (hw->mac.type != ixgbe_mac_X550EM_a)) 928 return -ENOSYS; 929 930 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d", 931 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 932 queue_id, stat_idx); 933 934 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG); 935 if (n >= IXGBE_NB_STAT_MAPPING_REGS) { 936 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded"); 937 return -EIO; 938 } 939 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG); 940 941 /* Now clear any previous stat_idx set */ 942 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 943 if (!is_rx) 944 stat_mappings->tqsm[n] &= ~clearing_mask; 945 else 946 stat_mappings->rqsmr[n] &= ~clearing_mask; 947 948 q_map = (uint32_t)stat_idx; 949 q_map &= QMAP_FIELD_RESERVED_BITS_MASK; 950 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 951 if (!is_rx) 952 stat_mappings->tqsm[n] |= qsmr_mask; 953 else 954 stat_mappings->rqsmr[n] |= qsmr_mask; 955 956 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d", 957 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 958 queue_id, stat_idx); 959 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n, 960 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]); 961 962 /* Now write the mapping in the appropriate register */ 963 if (is_rx) { 964 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d", 965 stat_mappings->rqsmr[n], n); 966 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]); 967 } else { 968 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d", 969 stat_mappings->tqsm[n], n); 970 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]); 971 } 972 return 0; 973 } 974 975 static void 976 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev) 977 { 978 struct ixgbe_stat_mapping_registers *stat_mappings = 979 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private); 980 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 981 int i; 982 983 /* write whatever was in stat mapping table to the NIC */ 984 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) { 985 /* rx */ 986 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]); 987 988 /* tx */ 989 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]); 990 } 991 } 992 993 static void 994 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config) 995 { 996 uint8_t i; 997 struct ixgbe_dcb_tc_config *tc; 998 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS; 999 1000 dcb_config->num_tcs.pg_tcs = dcb_max_tc; 1001 dcb_config->num_tcs.pfc_tcs = dcb_max_tc; 1002 for (i = 0; i < dcb_max_tc; i++) { 1003 tc = &dcb_config->tc_config[i]; 1004 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i; 1005 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 1006 (uint8_t)(100/dcb_max_tc + (i & 1)); 1007 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i; 1008 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 1009 (uint8_t)(100/dcb_max_tc + (i & 1)); 1010 tc->pfc = ixgbe_dcb_pfc_disabled; 1011 } 1012 1013 /* Initialize default user to priority mapping, UPx->TC0 */ 1014 tc = &dcb_config->tc_config[0]; 1015 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 1016 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 1017 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) { 1018 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100; 1019 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100; 1020 } 1021 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal; 1022 dcb_config->pfc_mode_enable = false; 1023 dcb_config->vt_mode = true; 1024 dcb_config->round_robin_enable = false; 1025 /* support all DCB capabilities in 82599 */ 1026 dcb_config->support.capabilities = 0xFF; 1027 1028 /*we only support 4 Tcs for X540, X550 */ 1029 if (hw->mac.type == ixgbe_mac_X540 || 1030 hw->mac.type == ixgbe_mac_X550 || 1031 hw->mac.type == ixgbe_mac_X550EM_x || 1032 hw->mac.type == ixgbe_mac_X550EM_a) { 1033 dcb_config->num_tcs.pg_tcs = 4; 1034 dcb_config->num_tcs.pfc_tcs = 4; 1035 } 1036 } 1037 1038 /* 1039 * Ensure that all locks are released before first NVM or PHY access 1040 */ 1041 static void 1042 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw) 1043 { 1044 uint16_t mask; 1045 1046 /* 1047 * Phy lock should not fail in this early stage. If this is the case, 1048 * it is due to an improper exit of the application. 1049 * So force the release of the faulty lock. Release of common lock 1050 * is done automatically by swfw_sync function. 1051 */ 1052 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func; 1053 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1054 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func); 1055 } 1056 ixgbe_release_swfw_semaphore(hw, mask); 1057 1058 /* 1059 * These ones are more tricky since they are common to all ports; but 1060 * swfw_sync retries last long enough (1s) to be almost sure that if 1061 * lock can not be taken it is due to an improper lock of the 1062 * semaphore. 1063 */ 1064 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM; 1065 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1066 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 1067 } 1068 ixgbe_release_swfw_semaphore(hw, mask); 1069 } 1070 1071 /* 1072 * This function is based on code in ixgbe_attach() in base/ixgbe.c. 1073 * It returns 0 on success. 1074 */ 1075 static int 1076 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) 1077 { 1078 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1079 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1080 struct ixgbe_hw *hw = 1081 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1082 struct ixgbe_vfta *shadow_vfta = 1083 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1084 struct ixgbe_hwstrip *hwstrip = 1085 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1086 struct ixgbe_dcb_config *dcb_config = 1087 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private); 1088 struct ixgbe_filter_info *filter_info = 1089 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1090 struct ixgbe_bw_conf *bw_conf = 1091 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private); 1092 uint32_t ctrl_ext; 1093 uint16_t csum; 1094 int diag, i; 1095 1096 PMD_INIT_FUNC_TRACE(); 1097 1098 ixgbe_dev_macsec_setting_reset(eth_dev); 1099 1100 eth_dev->dev_ops = &ixgbe_eth_dev_ops; 1101 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1102 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1103 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts; 1104 1105 /* 1106 * For secondary processes, we don't initialise any further as primary 1107 * has already done this work. Only check we don't need a different 1108 * RX and TX function. 1109 */ 1110 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1111 struct ixgbe_tx_queue *txq; 1112 /* TX queue function in primary, set by last queue initialized 1113 * Tx queue may not initialized by primary process 1114 */ 1115 if (eth_dev->data->tx_queues) { 1116 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1]; 1117 ixgbe_set_tx_function(eth_dev, txq); 1118 } else { 1119 /* Use default TX function if we get here */ 1120 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. " 1121 "Using default TX function."); 1122 } 1123 1124 ixgbe_set_rx_function(eth_dev); 1125 1126 return 0; 1127 } 1128 1129 rte_eth_copy_pci_info(eth_dev, pci_dev); 1130 1131 /* Vendor and Device ID need to be set before init of shared code */ 1132 hw->device_id = pci_dev->id.device_id; 1133 hw->vendor_id = pci_dev->id.vendor_id; 1134 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1135 hw->allow_unsupported_sfp = 1; 1136 1137 /* Initialize the shared code (base driver) */ 1138 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1139 diag = ixgbe_bypass_init_shared_code(hw); 1140 #else 1141 diag = ixgbe_init_shared_code(hw); 1142 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1143 1144 if (diag != IXGBE_SUCCESS) { 1145 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag); 1146 return -EIO; 1147 } 1148 1149 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 1150 PMD_INIT_LOG(ERR, "\nERROR: " 1151 "Firmware recovery mode detected. Limiting functionality.\n" 1152 "Refer to the Intel(R) Ethernet Adapters and Devices " 1153 "User Guide for details on firmware recovery mode."); 1154 return -EIO; 1155 } 1156 1157 /* pick up the PCI bus settings for reporting later */ 1158 ixgbe_get_bus_info(hw); 1159 1160 /* Unlock any pending hardware semaphore */ 1161 ixgbe_swfw_lock_reset(hw); 1162 1163 #ifdef RTE_LIBRTE_SECURITY 1164 /* Initialize security_ctx only for primary process*/ 1165 if (ixgbe_ipsec_ctx_create(eth_dev)) 1166 return -ENOMEM; 1167 #endif 1168 1169 /* Initialize DCB configuration*/ 1170 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config)); 1171 ixgbe_dcb_init(hw, dcb_config); 1172 /* Get Hardware Flow Control setting */ 1173 hw->fc.requested_mode = ixgbe_fc_full; 1174 hw->fc.current_mode = ixgbe_fc_full; 1175 hw->fc.pause_time = IXGBE_FC_PAUSE; 1176 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 1177 hw->fc.low_water[i] = IXGBE_FC_LO; 1178 hw->fc.high_water[i] = IXGBE_FC_HI; 1179 } 1180 hw->fc.send_xon = 1; 1181 1182 /* Make sure we have a good EEPROM before we read from it */ 1183 diag = ixgbe_validate_eeprom_checksum(hw, &csum); 1184 if (diag != IXGBE_SUCCESS) { 1185 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag); 1186 return -EIO; 1187 } 1188 1189 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1190 diag = ixgbe_bypass_init_hw(hw); 1191 #else 1192 diag = ixgbe_init_hw(hw); 1193 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1194 1195 /* 1196 * Devices with copper phys will fail to initialise if ixgbe_init_hw() 1197 * is called too soon after the kernel driver unbinding/binding occurs. 1198 * The failure occurs in ixgbe_identify_phy_generic() for all devices, 1199 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is 1200 * also called. See ixgbe_identify_phy_82599(). The reason for the 1201 * failure is not known, and only occuts when virtualisation features 1202 * are disabled in the bios. A delay of 100ms was found to be enough by 1203 * trial-and-error, and is doubled to be safe. 1204 */ 1205 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) { 1206 rte_delay_ms(200); 1207 diag = ixgbe_init_hw(hw); 1208 } 1209 1210 if (diag == IXGBE_ERR_SFP_NOT_PRESENT) 1211 diag = IXGBE_SUCCESS; 1212 1213 if (diag == IXGBE_ERR_EEPROM_VERSION) { 1214 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/" 1215 "LOM. Please be aware there may be issues associated " 1216 "with your hardware."); 1217 PMD_INIT_LOG(ERR, "If you are experiencing problems " 1218 "please contact your Intel or hardware representative " 1219 "who provided you with this hardware."); 1220 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED) 1221 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module"); 1222 if (diag) { 1223 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag); 1224 return -EIO; 1225 } 1226 1227 /* Reset the hw statistics */ 1228 ixgbe_dev_stats_reset(eth_dev); 1229 1230 /* disable interrupt */ 1231 ixgbe_disable_intr(hw); 1232 1233 /* reset mappings for queue statistics hw counters*/ 1234 ixgbe_reset_qstat_mappings(hw); 1235 1236 /* Allocate memory for storing MAC addresses */ 1237 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN * 1238 hw->mac.num_rar_entries, 0); 1239 if (eth_dev->data->mac_addrs == NULL) { 1240 PMD_INIT_LOG(ERR, 1241 "Failed to allocate %u bytes needed to store " 1242 "MAC addresses", 1243 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1244 return -ENOMEM; 1245 } 1246 /* Copy the permanent MAC address */ 1247 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr, 1248 ð_dev->data->mac_addrs[0]); 1249 1250 /* Allocate memory for storing hash filter MAC addresses */ 1251 eth_dev->data->hash_mac_addrs = rte_zmalloc( 1252 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0); 1253 if (eth_dev->data->hash_mac_addrs == NULL) { 1254 PMD_INIT_LOG(ERR, 1255 "Failed to allocate %d bytes needed to store MAC addresses", 1256 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC); 1257 return -ENOMEM; 1258 } 1259 1260 /* Pass the information to the rte_eth_dev_close() that it should also 1261 * release the private port resources. 1262 */ 1263 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1264 1265 /* initialize the vfta */ 1266 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1267 1268 /* initialize the hw strip bitmap*/ 1269 memset(hwstrip, 0, sizeof(*hwstrip)); 1270 1271 /* initialize PF if max_vfs not zero */ 1272 ixgbe_pf_host_init(eth_dev); 1273 1274 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 1275 /* let hardware know driver is loaded */ 1276 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD; 1277 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 1278 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 1279 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 1280 IXGBE_WRITE_FLUSH(hw); 1281 1282 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 1283 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d", 1284 (int) hw->mac.type, (int) hw->phy.type, 1285 (int) hw->phy.sfp_type); 1286 else 1287 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d", 1288 (int) hw->mac.type, (int) hw->phy.type); 1289 1290 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 1291 eth_dev->data->port_id, pci_dev->id.vendor_id, 1292 pci_dev->id.device_id); 1293 1294 rte_intr_callback_register(intr_handle, 1295 ixgbe_dev_interrupt_handler, eth_dev); 1296 1297 /* enable uio/vfio intr/eventfd mapping */ 1298 rte_intr_enable(intr_handle); 1299 1300 /* enable support intr */ 1301 ixgbe_enable_intr(eth_dev); 1302 1303 /* initialize filter info */ 1304 memset(filter_info, 0, 1305 sizeof(struct ixgbe_filter_info)); 1306 1307 /* initialize 5tuple filter list */ 1308 TAILQ_INIT(&filter_info->fivetuple_list); 1309 1310 /* initialize flow director filter list & hash */ 1311 ixgbe_fdir_filter_init(eth_dev); 1312 1313 /* initialize l2 tunnel filter list & hash */ 1314 ixgbe_l2_tn_filter_init(eth_dev); 1315 1316 /* initialize flow filter lists */ 1317 ixgbe_filterlist_init(); 1318 1319 /* initialize bandwidth configuration info */ 1320 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf)); 1321 1322 /* initialize Traffic Manager configuration */ 1323 ixgbe_tm_conf_init(eth_dev); 1324 1325 return 0; 1326 } 1327 1328 static int 1329 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1330 { 1331 PMD_INIT_FUNC_TRACE(); 1332 1333 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1334 return 0; 1335 1336 ixgbe_dev_close(eth_dev); 1337 1338 return 0; 1339 } 1340 1341 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev) 1342 { 1343 struct ixgbe_filter_info *filter_info = 1344 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1345 struct ixgbe_5tuple_filter *p_5tuple; 1346 1347 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) { 1348 TAILQ_REMOVE(&filter_info->fivetuple_list, 1349 p_5tuple, 1350 entries); 1351 rte_free(p_5tuple); 1352 } 1353 memset(filter_info->fivetuple_mask, 0, 1354 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE); 1355 1356 return 0; 1357 } 1358 1359 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev) 1360 { 1361 struct ixgbe_hw_fdir_info *fdir_info = 1362 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1363 struct ixgbe_fdir_filter *fdir_filter; 1364 1365 if (fdir_info->hash_map) 1366 rte_free(fdir_info->hash_map); 1367 if (fdir_info->hash_handle) 1368 rte_hash_free(fdir_info->hash_handle); 1369 1370 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 1371 TAILQ_REMOVE(&fdir_info->fdir_list, 1372 fdir_filter, 1373 entries); 1374 rte_free(fdir_filter); 1375 } 1376 1377 return 0; 1378 } 1379 1380 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev) 1381 { 1382 struct ixgbe_l2_tn_info *l2_tn_info = 1383 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1384 struct ixgbe_l2_tn_filter *l2_tn_filter; 1385 1386 if (l2_tn_info->hash_map) 1387 rte_free(l2_tn_info->hash_map); 1388 if (l2_tn_info->hash_handle) 1389 rte_hash_free(l2_tn_info->hash_handle); 1390 1391 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 1392 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, 1393 l2_tn_filter, 1394 entries); 1395 rte_free(l2_tn_filter); 1396 } 1397 1398 return 0; 1399 } 1400 1401 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev) 1402 { 1403 struct ixgbe_hw_fdir_info *fdir_info = 1404 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1405 char fdir_hash_name[RTE_HASH_NAMESIZE]; 1406 struct rte_hash_parameters fdir_hash_params = { 1407 .name = fdir_hash_name, 1408 .entries = IXGBE_MAX_FDIR_FILTER_NUM, 1409 .key_len = sizeof(union ixgbe_atr_input), 1410 .hash_func = rte_hash_crc, 1411 .hash_func_init_val = 0, 1412 .socket_id = rte_socket_id(), 1413 }; 1414 1415 TAILQ_INIT(&fdir_info->fdir_list); 1416 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 1417 "fdir_%s", eth_dev->device->name); 1418 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params); 1419 if (!fdir_info->hash_handle) { 1420 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 1421 return -EINVAL; 1422 } 1423 fdir_info->hash_map = rte_zmalloc("ixgbe", 1424 sizeof(struct ixgbe_fdir_filter *) * 1425 IXGBE_MAX_FDIR_FILTER_NUM, 1426 0); 1427 if (!fdir_info->hash_map) { 1428 PMD_INIT_LOG(ERR, 1429 "Failed to allocate memory for fdir hash map!"); 1430 return -ENOMEM; 1431 } 1432 fdir_info->mask_added = FALSE; 1433 1434 return 0; 1435 } 1436 1437 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) 1438 { 1439 struct ixgbe_l2_tn_info *l2_tn_info = 1440 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1441 char l2_tn_hash_name[RTE_HASH_NAMESIZE]; 1442 struct rte_hash_parameters l2_tn_hash_params = { 1443 .name = l2_tn_hash_name, 1444 .entries = IXGBE_MAX_L2_TN_FILTER_NUM, 1445 .key_len = sizeof(struct ixgbe_l2_tn_key), 1446 .hash_func = rte_hash_crc, 1447 .hash_func_init_val = 0, 1448 .socket_id = rte_socket_id(), 1449 }; 1450 1451 TAILQ_INIT(&l2_tn_info->l2_tn_list); 1452 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE, 1453 "l2_tn_%s", eth_dev->device->name); 1454 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params); 1455 if (!l2_tn_info->hash_handle) { 1456 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!"); 1457 return -EINVAL; 1458 } 1459 l2_tn_info->hash_map = rte_zmalloc("ixgbe", 1460 sizeof(struct ixgbe_l2_tn_filter *) * 1461 IXGBE_MAX_L2_TN_FILTER_NUM, 1462 0); 1463 if (!l2_tn_info->hash_map) { 1464 PMD_INIT_LOG(ERR, 1465 "Failed to allocate memory for L2 TN hash map!"); 1466 return -ENOMEM; 1467 } 1468 l2_tn_info->e_tag_en = FALSE; 1469 l2_tn_info->e_tag_fwd_en = FALSE; 1470 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG; 1471 1472 return 0; 1473 } 1474 /* 1475 * Negotiate mailbox API version with the PF. 1476 * After reset API version is always set to the basic one (ixgbe_mbox_api_10). 1477 * Then we try to negotiate starting with the most recent one. 1478 * If all negotiation attempts fail, then we will proceed with 1479 * the default one (ixgbe_mbox_api_10). 1480 */ 1481 static void 1482 ixgbevf_negotiate_api(struct ixgbe_hw *hw) 1483 { 1484 int32_t i; 1485 1486 /* start with highest supported, proceed down */ 1487 static const enum ixgbe_pfvf_api_rev sup_ver[] = { 1488 ixgbe_mbox_api_13, 1489 ixgbe_mbox_api_12, 1490 ixgbe_mbox_api_11, 1491 ixgbe_mbox_api_10, 1492 }; 1493 1494 for (i = 0; 1495 i != RTE_DIM(sup_ver) && 1496 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0; 1497 i++) 1498 ; 1499 } 1500 1501 static void 1502 generate_random_mac_addr(struct rte_ether_addr *mac_addr) 1503 { 1504 uint64_t random; 1505 1506 /* Set Organizationally Unique Identifier (OUI) prefix. */ 1507 mac_addr->addr_bytes[0] = 0x00; 1508 mac_addr->addr_bytes[1] = 0x09; 1509 mac_addr->addr_bytes[2] = 0xC0; 1510 /* Force indication of locally assigned MAC address. */ 1511 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR; 1512 /* Generate the last 3 bytes of the MAC address with a random number. */ 1513 random = rte_rand(); 1514 memcpy(&mac_addr->addr_bytes[3], &random, 3); 1515 } 1516 1517 static int 1518 devarg_handle_int(__rte_unused const char *key, const char *value, 1519 void *extra_args) 1520 { 1521 uint16_t *n = extra_args; 1522 1523 if (value == NULL || extra_args == NULL) 1524 return -EINVAL; 1525 1526 *n = (uint16_t)strtoul(value, NULL, 0); 1527 if (*n == USHRT_MAX && errno == ERANGE) 1528 return -1; 1529 1530 return 0; 1531 } 1532 1533 static void 1534 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter, 1535 struct rte_devargs *devargs) 1536 { 1537 struct rte_kvargs *kvlist; 1538 uint16_t pflink_fullchk; 1539 1540 if (devargs == NULL) 1541 return; 1542 1543 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments); 1544 if (kvlist == NULL) 1545 return; 1546 1547 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 && 1548 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK, 1549 devarg_handle_int, &pflink_fullchk) == 0 && 1550 pflink_fullchk == 1) 1551 adapter->pflink_fullchk = 1; 1552 1553 rte_kvargs_free(kvlist); 1554 } 1555 1556 /* 1557 * Virtual Function device init 1558 */ 1559 static int 1560 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev) 1561 { 1562 int diag; 1563 uint32_t tc, tcs; 1564 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1565 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1566 struct ixgbe_hw *hw = 1567 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1568 struct ixgbe_vfta *shadow_vfta = 1569 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1570 struct ixgbe_hwstrip *hwstrip = 1571 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1572 struct rte_ether_addr *perm_addr = 1573 (struct rte_ether_addr *)hw->mac.perm_addr; 1574 1575 PMD_INIT_FUNC_TRACE(); 1576 1577 eth_dev->dev_ops = &ixgbevf_eth_dev_ops; 1578 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1579 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1580 1581 /* for secondary processes, we don't initialise any further as primary 1582 * has already done this work. Only check we don't need a different 1583 * RX function 1584 */ 1585 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1586 struct ixgbe_tx_queue *txq; 1587 /* TX queue function in primary, set by last queue initialized 1588 * Tx queue may not initialized by primary process 1589 */ 1590 if (eth_dev->data->tx_queues) { 1591 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1]; 1592 ixgbe_set_tx_function(eth_dev, txq); 1593 } else { 1594 /* Use default TX function if we get here */ 1595 PMD_INIT_LOG(NOTICE, 1596 "No TX queues configured yet. Using default TX function."); 1597 } 1598 1599 ixgbe_set_rx_function(eth_dev); 1600 1601 return 0; 1602 } 1603 1604 ixgbevf_parse_devargs(eth_dev->data->dev_private, 1605 pci_dev->device.devargs); 1606 1607 rte_eth_copy_pci_info(eth_dev, pci_dev); 1608 1609 hw->device_id = pci_dev->id.device_id; 1610 hw->vendor_id = pci_dev->id.vendor_id; 1611 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1612 1613 /* initialize the vfta */ 1614 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1615 1616 /* initialize the hw strip bitmap*/ 1617 memset(hwstrip, 0, sizeof(*hwstrip)); 1618 1619 /* Initialize the shared code (base driver) */ 1620 diag = ixgbe_init_shared_code(hw); 1621 if (diag != IXGBE_SUCCESS) { 1622 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag); 1623 return -EIO; 1624 } 1625 1626 /* init_mailbox_params */ 1627 hw->mbx.ops.init_params(hw); 1628 1629 /* Reset the hw statistics */ 1630 ixgbevf_dev_stats_reset(eth_dev); 1631 1632 /* Disable the interrupts for VF */ 1633 ixgbevf_intr_disable(eth_dev); 1634 1635 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */ 1636 diag = hw->mac.ops.reset_hw(hw); 1637 1638 /* 1639 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when 1640 * the underlying PF driver has not assigned a MAC address to the VF. 1641 * In this case, assign a random MAC address. 1642 */ 1643 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) { 1644 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1645 /* 1646 * This error code will be propagated to the app by 1647 * rte_eth_dev_reset, so use a public error code rather than 1648 * the internal-only IXGBE_ERR_RESET_FAILED 1649 */ 1650 return -EAGAIN; 1651 } 1652 1653 /* negotiate mailbox API version to use with the PF. */ 1654 ixgbevf_negotiate_api(hw); 1655 1656 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */ 1657 ixgbevf_get_queues(hw, &tcs, &tc); 1658 1659 /* Allocate memory for storing MAC addresses */ 1660 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN * 1661 hw->mac.num_rar_entries, 0); 1662 if (eth_dev->data->mac_addrs == NULL) { 1663 PMD_INIT_LOG(ERR, 1664 "Failed to allocate %u bytes needed to store " 1665 "MAC addresses", 1666 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1667 return -ENOMEM; 1668 } 1669 1670 /* Pass the information to the rte_eth_dev_close() that it should also 1671 * release the private port resources. 1672 */ 1673 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1674 1675 /* Generate a random MAC address, if none was assigned by PF. */ 1676 if (rte_is_zero_ether_addr(perm_addr)) { 1677 generate_random_mac_addr(perm_addr); 1678 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1); 1679 if (diag) { 1680 rte_free(eth_dev->data->mac_addrs); 1681 eth_dev->data->mac_addrs = NULL; 1682 return diag; 1683 } 1684 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF"); 1685 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address " 1686 "%02x:%02x:%02x:%02x:%02x:%02x", 1687 perm_addr->addr_bytes[0], 1688 perm_addr->addr_bytes[1], 1689 perm_addr->addr_bytes[2], 1690 perm_addr->addr_bytes[3], 1691 perm_addr->addr_bytes[4], 1692 perm_addr->addr_bytes[5]); 1693 } 1694 1695 /* Copy the permanent MAC address */ 1696 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]); 1697 1698 /* reset the hardware with the new settings */ 1699 diag = hw->mac.ops.start_hw(hw); 1700 switch (diag) { 1701 case 0: 1702 break; 1703 1704 default: 1705 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1706 return -EIO; 1707 } 1708 1709 rte_intr_callback_register(intr_handle, 1710 ixgbevf_dev_interrupt_handler, eth_dev); 1711 rte_intr_enable(intr_handle); 1712 ixgbevf_intr_enable(eth_dev); 1713 1714 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s", 1715 eth_dev->data->port_id, pci_dev->id.vendor_id, 1716 pci_dev->id.device_id, "ixgbe_mac_82599_vf"); 1717 1718 return 0; 1719 } 1720 1721 /* Virtual Function device uninit */ 1722 1723 static int 1724 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev) 1725 { 1726 PMD_INIT_FUNC_TRACE(); 1727 1728 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1729 return 0; 1730 1731 ixgbevf_dev_close(eth_dev); 1732 1733 return 0; 1734 } 1735 1736 static int 1737 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1738 struct rte_pci_device *pci_dev) 1739 { 1740 char name[RTE_ETH_NAME_MAX_LEN]; 1741 struct rte_eth_dev *pf_ethdev; 1742 struct rte_eth_devargs eth_da; 1743 int i, retval; 1744 1745 if (pci_dev->device.devargs) { 1746 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 1747 ð_da); 1748 if (retval) 1749 return retval; 1750 } else 1751 memset(ð_da, 0, sizeof(eth_da)); 1752 1753 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 1754 sizeof(struct ixgbe_adapter), 1755 eth_dev_pci_specific_init, pci_dev, 1756 eth_ixgbe_dev_init, NULL); 1757 1758 if (retval || eth_da.nb_representor_ports < 1) 1759 return retval; 1760 1761 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1762 if (pf_ethdev == NULL) 1763 return -ENODEV; 1764 1765 /* probe VF representor ports */ 1766 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1767 struct ixgbe_vf_info *vfinfo; 1768 struct ixgbe_vf_representor representor; 1769 1770 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA( 1771 pf_ethdev->data->dev_private); 1772 if (vfinfo == NULL) { 1773 PMD_DRV_LOG(ERR, 1774 "no virtual functions supported by PF"); 1775 break; 1776 } 1777 1778 representor.vf_id = eth_da.representor_ports[i]; 1779 representor.switch_domain_id = vfinfo->switch_domain_id; 1780 representor.pf_ethdev = pf_ethdev; 1781 1782 /* representor port net_bdf_port */ 1783 snprintf(name, sizeof(name), "net_%s_representor_%d", 1784 pci_dev->device.name, 1785 eth_da.representor_ports[i]); 1786 1787 retval = rte_eth_dev_create(&pci_dev->device, name, 1788 sizeof(struct ixgbe_vf_representor), NULL, NULL, 1789 ixgbe_vf_representor_init, &representor); 1790 1791 if (retval) 1792 PMD_DRV_LOG(ERR, "failed to create ixgbe vf " 1793 "representor %s.", name); 1794 } 1795 1796 return 0; 1797 } 1798 1799 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev) 1800 { 1801 struct rte_eth_dev *ethdev; 1802 1803 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1804 if (!ethdev) 1805 return 0; 1806 1807 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 1808 return rte_eth_dev_pci_generic_remove(pci_dev, 1809 ixgbe_vf_representor_uninit); 1810 else 1811 return rte_eth_dev_pci_generic_remove(pci_dev, 1812 eth_ixgbe_dev_uninit); 1813 } 1814 1815 static struct rte_pci_driver rte_ixgbe_pmd = { 1816 .id_table = pci_id_ixgbe_map, 1817 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1818 .probe = eth_ixgbe_pci_probe, 1819 .remove = eth_ixgbe_pci_remove, 1820 }; 1821 1822 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1823 struct rte_pci_device *pci_dev) 1824 { 1825 return rte_eth_dev_pci_generic_probe(pci_dev, 1826 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init); 1827 } 1828 1829 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev) 1830 { 1831 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit); 1832 } 1833 1834 /* 1835 * virtual function driver struct 1836 */ 1837 static struct rte_pci_driver rte_ixgbevf_pmd = { 1838 .id_table = pci_id_ixgbevf_map, 1839 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1840 .probe = eth_ixgbevf_pci_probe, 1841 .remove = eth_ixgbevf_pci_remove, 1842 }; 1843 1844 static int 1845 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1846 { 1847 struct ixgbe_hw *hw = 1848 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1849 struct ixgbe_vfta *shadow_vfta = 1850 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1851 uint32_t vfta; 1852 uint32_t vid_idx; 1853 uint32_t vid_bit; 1854 1855 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 1856 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 1857 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx)); 1858 if (on) 1859 vfta |= vid_bit; 1860 else 1861 vfta &= ~vid_bit; 1862 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta); 1863 1864 /* update local VFTA copy */ 1865 shadow_vfta->vfta[vid_idx] = vfta; 1866 1867 return 0; 1868 } 1869 1870 static void 1871 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 1872 { 1873 if (on) 1874 ixgbe_vlan_hw_strip_enable(dev, queue); 1875 else 1876 ixgbe_vlan_hw_strip_disable(dev, queue); 1877 } 1878 1879 static int 1880 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1881 enum rte_vlan_type vlan_type, 1882 uint16_t tpid) 1883 { 1884 struct ixgbe_hw *hw = 1885 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1886 int ret = 0; 1887 uint32_t reg; 1888 uint32_t qinq; 1889 1890 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1891 qinq &= IXGBE_DMATXCTL_GDV; 1892 1893 switch (vlan_type) { 1894 case ETH_VLAN_TYPE_INNER: 1895 if (qinq) { 1896 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1897 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1898 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1899 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1900 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1901 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1902 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1903 } else { 1904 ret = -ENOTSUP; 1905 PMD_DRV_LOG(ERR, "Inner type is not supported" 1906 " by single VLAN"); 1907 } 1908 break; 1909 case ETH_VLAN_TYPE_OUTER: 1910 if (qinq) { 1911 /* Only the high 16-bits is valid */ 1912 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid << 1913 IXGBE_EXVET_VET_EXT_SHIFT); 1914 } else { 1915 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1916 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1917 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1918 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1919 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1920 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1921 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1922 } 1923 1924 break; 1925 default: 1926 ret = -EINVAL; 1927 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type); 1928 break; 1929 } 1930 1931 return ret; 1932 } 1933 1934 void 1935 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev) 1936 { 1937 struct ixgbe_hw *hw = 1938 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1939 uint32_t vlnctrl; 1940 1941 PMD_INIT_FUNC_TRACE(); 1942 1943 /* Filter Table Disable */ 1944 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1945 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 1946 1947 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1948 } 1949 1950 void 1951 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1952 { 1953 struct ixgbe_hw *hw = 1954 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1955 struct ixgbe_vfta *shadow_vfta = 1956 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1957 uint32_t vlnctrl; 1958 uint16_t i; 1959 1960 PMD_INIT_FUNC_TRACE(); 1961 1962 /* Filter Table Enable */ 1963 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1964 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; 1965 vlnctrl |= IXGBE_VLNCTRL_VFE; 1966 1967 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1968 1969 /* write whatever is in local vfta copy */ 1970 for (i = 0; i < IXGBE_VFTA_SIZE; i++) 1971 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]); 1972 } 1973 1974 static void 1975 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on) 1976 { 1977 struct ixgbe_hwstrip *hwstrip = 1978 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private); 1979 struct ixgbe_rx_queue *rxq; 1980 1981 if (queue >= IXGBE_MAX_RX_QUEUE_NUM) 1982 return; 1983 1984 if (on) 1985 IXGBE_SET_HWSTRIP(hwstrip, queue); 1986 else 1987 IXGBE_CLEAR_HWSTRIP(hwstrip, queue); 1988 1989 if (queue >= dev->data->nb_rx_queues) 1990 return; 1991 1992 rxq = dev->data->rx_queues[queue]; 1993 1994 if (on) { 1995 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; 1996 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 1997 } else { 1998 rxq->vlan_flags = PKT_RX_VLAN; 1999 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 2000 } 2001 } 2002 2003 static void 2004 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue) 2005 { 2006 struct ixgbe_hw *hw = 2007 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2008 uint32_t ctrl; 2009 2010 PMD_INIT_FUNC_TRACE(); 2011 2012 if (hw->mac.type == ixgbe_mac_82598EB) { 2013 /* No queue level support */ 2014 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2015 return; 2016 } 2017 2018 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2019 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2020 ctrl &= ~IXGBE_RXDCTL_VME; 2021 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2022 2023 /* record those setting for HW strip per queue */ 2024 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0); 2025 } 2026 2027 static void 2028 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue) 2029 { 2030 struct ixgbe_hw *hw = 2031 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2032 uint32_t ctrl; 2033 2034 PMD_INIT_FUNC_TRACE(); 2035 2036 if (hw->mac.type == ixgbe_mac_82598EB) { 2037 /* No queue level supported */ 2038 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2039 return; 2040 } 2041 2042 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2043 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2044 ctrl |= IXGBE_RXDCTL_VME; 2045 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2046 2047 /* record those setting for HW strip per queue */ 2048 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1); 2049 } 2050 2051 static void 2052 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev) 2053 { 2054 struct ixgbe_hw *hw = 2055 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2056 uint32_t ctrl; 2057 2058 PMD_INIT_FUNC_TRACE(); 2059 2060 /* DMATXCTRL: Geric Double VLAN Disable */ 2061 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2062 ctrl &= ~IXGBE_DMATXCTL_GDV; 2063 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2064 2065 /* CTRL_EXT: Global Double VLAN Disable */ 2066 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2067 ctrl &= ~IXGBE_EXTENDED_VLAN; 2068 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2069 2070 } 2071 2072 static void 2073 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) 2074 { 2075 struct ixgbe_hw *hw = 2076 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2077 uint32_t ctrl; 2078 2079 PMD_INIT_FUNC_TRACE(); 2080 2081 /* DMATXCTRL: Geric Double VLAN Enable */ 2082 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2083 ctrl |= IXGBE_DMATXCTL_GDV; 2084 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2085 2086 /* CTRL_EXT: Global Double VLAN Enable */ 2087 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2088 ctrl |= IXGBE_EXTENDED_VLAN; 2089 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2090 2091 /* Clear pooling mode of PFVTCTL. It's required by X550. */ 2092 if (hw->mac.type == ixgbe_mac_X550 || 2093 hw->mac.type == ixgbe_mac_X550EM_x || 2094 hw->mac.type == ixgbe_mac_X550EM_a) { 2095 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 2096 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 2097 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 2098 } 2099 2100 /* 2101 * VET EXT field in the EXVET register = 0x8100 by default 2102 * So no need to change. Same to VT field of DMATXCTL register 2103 */ 2104 } 2105 2106 void 2107 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev) 2108 { 2109 struct ixgbe_hw *hw = 2110 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2111 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 2112 uint32_t ctrl; 2113 uint16_t i; 2114 struct ixgbe_rx_queue *rxq; 2115 bool on; 2116 2117 PMD_INIT_FUNC_TRACE(); 2118 2119 if (hw->mac.type == ixgbe_mac_82598EB) { 2120 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2121 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2122 ctrl |= IXGBE_VLNCTRL_VME; 2123 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2124 } else { 2125 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2126 ctrl &= ~IXGBE_VLNCTRL_VME; 2127 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2128 } 2129 } else { 2130 /* 2131 * Other 10G NIC, the VLAN strip can be setup 2132 * per queue in RXDCTL 2133 */ 2134 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2135 rxq = dev->data->rx_queues[i]; 2136 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx)); 2137 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2138 ctrl |= IXGBE_RXDCTL_VME; 2139 on = TRUE; 2140 } else { 2141 ctrl &= ~IXGBE_RXDCTL_VME; 2142 on = FALSE; 2143 } 2144 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl); 2145 2146 /* record those setting for HW strip per queue */ 2147 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on); 2148 } 2149 } 2150 } 2151 2152 static void 2153 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask) 2154 { 2155 uint16_t i; 2156 struct rte_eth_rxmode *rxmode; 2157 struct ixgbe_rx_queue *rxq; 2158 2159 if (mask & ETH_VLAN_STRIP_MASK) { 2160 rxmode = &dev->data->dev_conf.rxmode; 2161 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 2162 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2163 rxq = dev->data->rx_queues[i]; 2164 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 2165 } 2166 else 2167 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2168 rxq = dev->data->rx_queues[i]; 2169 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 2170 } 2171 } 2172 } 2173 2174 static int 2175 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask) 2176 { 2177 struct rte_eth_rxmode *rxmode; 2178 rxmode = &dev->data->dev_conf.rxmode; 2179 2180 if (mask & ETH_VLAN_STRIP_MASK) { 2181 ixgbe_vlan_hw_strip_config(dev); 2182 } 2183 2184 if (mask & ETH_VLAN_FILTER_MASK) { 2185 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 2186 ixgbe_vlan_hw_filter_enable(dev); 2187 else 2188 ixgbe_vlan_hw_filter_disable(dev); 2189 } 2190 2191 if (mask & ETH_VLAN_EXTEND_MASK) { 2192 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2193 ixgbe_vlan_hw_extend_enable(dev); 2194 else 2195 ixgbe_vlan_hw_extend_disable(dev); 2196 } 2197 2198 return 0; 2199 } 2200 2201 static int 2202 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2203 { 2204 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 2205 2206 ixgbe_vlan_offload_config(dev, mask); 2207 2208 return 0; 2209 } 2210 2211 static void 2212 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev) 2213 { 2214 struct ixgbe_hw *hw = 2215 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2216 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */ 2217 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2218 2219 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */ 2220 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl); 2221 } 2222 2223 static int 2224 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q) 2225 { 2226 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2227 2228 switch (nb_rx_q) { 2229 case 1: 2230 case 2: 2231 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS; 2232 break; 2233 case 4: 2234 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS; 2235 break; 2236 default: 2237 return -EINVAL; 2238 } 2239 2240 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 2241 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2242 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 2243 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2244 return 0; 2245 } 2246 2247 static int 2248 ixgbe_check_mq_mode(struct rte_eth_dev *dev) 2249 { 2250 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 2251 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2252 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2253 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2254 2255 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 2256 /* check multi-queue mode */ 2257 switch (dev_conf->rxmode.mq_mode) { 2258 case ETH_MQ_RX_VMDQ_DCB: 2259 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV"); 2260 break; 2261 case ETH_MQ_RX_VMDQ_DCB_RSS: 2262 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */ 2263 PMD_INIT_LOG(ERR, "SRIOV active," 2264 " unsupported mq_mode rx %d.", 2265 dev_conf->rxmode.mq_mode); 2266 return -EINVAL; 2267 case ETH_MQ_RX_RSS: 2268 case ETH_MQ_RX_VMDQ_RSS: 2269 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS; 2270 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) 2271 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) { 2272 PMD_INIT_LOG(ERR, "SRIOV is active," 2273 " invalid queue number" 2274 " for VMDQ RSS, allowed" 2275 " value are 1, 2 or 4."); 2276 return -EINVAL; 2277 } 2278 break; 2279 case ETH_MQ_RX_VMDQ_ONLY: 2280 case ETH_MQ_RX_NONE: 2281 /* if nothing mq mode configure, use default scheme */ 2282 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY; 2283 break; 2284 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/ 2285 /* SRIOV only works in VMDq enable mode */ 2286 PMD_INIT_LOG(ERR, "SRIOV is active," 2287 " wrong mq_mode rx %d.", 2288 dev_conf->rxmode.mq_mode); 2289 return -EINVAL; 2290 } 2291 2292 switch (dev_conf->txmode.mq_mode) { 2293 case ETH_MQ_TX_VMDQ_DCB: 2294 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV"); 2295 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB; 2296 break; 2297 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */ 2298 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY; 2299 break; 2300 } 2301 2302 /* check valid queue number */ 2303 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) || 2304 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) { 2305 PMD_INIT_LOG(ERR, "SRIOV is active," 2306 " nb_rx_q=%d nb_tx_q=%d queue number" 2307 " must be less than or equal to %d.", 2308 nb_rx_q, nb_tx_q, 2309 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool); 2310 return -EINVAL; 2311 } 2312 } else { 2313 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) { 2314 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is" 2315 " not supported."); 2316 return -EINVAL; 2317 } 2318 /* check configuration for vmdb+dcb mode */ 2319 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) { 2320 const struct rte_eth_vmdq_dcb_conf *conf; 2321 2322 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2323 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.", 2324 IXGBE_VMDQ_DCB_NB_QUEUES); 2325 return -EINVAL; 2326 } 2327 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf; 2328 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2329 conf->nb_queue_pools == ETH_32_POOLS)) { 2330 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2331 " nb_queue_pools must be %d or %d.", 2332 ETH_16_POOLS, ETH_32_POOLS); 2333 return -EINVAL; 2334 } 2335 } 2336 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) { 2337 const struct rte_eth_vmdq_dcb_tx_conf *conf; 2338 2339 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2340 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d", 2341 IXGBE_VMDQ_DCB_NB_QUEUES); 2342 return -EINVAL; 2343 } 2344 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf; 2345 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2346 conf->nb_queue_pools == ETH_32_POOLS)) { 2347 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2348 " nb_queue_pools != %d and" 2349 " nb_queue_pools != %d.", 2350 ETH_16_POOLS, ETH_32_POOLS); 2351 return -EINVAL; 2352 } 2353 } 2354 2355 /* For DCB mode check our configuration before we go further */ 2356 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) { 2357 const struct rte_eth_dcb_rx_conf *conf; 2358 2359 conf = &dev_conf->rx_adv_conf.dcb_rx_conf; 2360 if (!(conf->nb_tcs == ETH_4_TCS || 2361 conf->nb_tcs == ETH_8_TCS)) { 2362 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2363 " and nb_tcs != %d.", 2364 ETH_4_TCS, ETH_8_TCS); 2365 return -EINVAL; 2366 } 2367 } 2368 2369 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) { 2370 const struct rte_eth_dcb_tx_conf *conf; 2371 2372 conf = &dev_conf->tx_adv_conf.dcb_tx_conf; 2373 if (!(conf->nb_tcs == ETH_4_TCS || 2374 conf->nb_tcs == ETH_8_TCS)) { 2375 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2376 " and nb_tcs != %d.", 2377 ETH_4_TCS, ETH_8_TCS); 2378 return -EINVAL; 2379 } 2380 } 2381 2382 /* 2383 * When DCB/VT is off, maximum number of queues changes, 2384 * except for 82598EB, which remains constant. 2385 */ 2386 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 2387 hw->mac.type != ixgbe_mac_82598EB) { 2388 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) { 2389 PMD_INIT_LOG(ERR, 2390 "Neither VT nor DCB are enabled, " 2391 "nb_tx_q > %d.", 2392 IXGBE_NONE_MODE_TX_NB_QUEUES); 2393 return -EINVAL; 2394 } 2395 } 2396 } 2397 return 0; 2398 } 2399 2400 static int 2401 ixgbe_dev_configure(struct rte_eth_dev *dev) 2402 { 2403 struct ixgbe_interrupt *intr = 2404 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2405 struct ixgbe_adapter *adapter = dev->data->dev_private; 2406 int ret; 2407 2408 PMD_INIT_FUNC_TRACE(); 2409 2410 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 2411 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 2412 2413 /* multipe queue mode checking */ 2414 ret = ixgbe_check_mq_mode(dev); 2415 if (ret != 0) { 2416 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.", 2417 ret); 2418 return ret; 2419 } 2420 2421 /* set flag to update link status after init */ 2422 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2423 2424 /* 2425 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 2426 * allocation or vector Rx preconditions we will reset it. 2427 */ 2428 adapter->rx_bulk_alloc_allowed = true; 2429 adapter->rx_vec_allowed = true; 2430 2431 return 0; 2432 } 2433 2434 static void 2435 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) 2436 { 2437 struct ixgbe_hw *hw = 2438 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2439 struct ixgbe_interrupt *intr = 2440 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2441 uint32_t gpie; 2442 2443 /* only set up it on X550EM_X */ 2444 if (hw->mac.type == ixgbe_mac_X550EM_x) { 2445 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 2446 gpie |= IXGBE_SDP0_GPIEN_X550EM_x; 2447 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 2448 if (hw->phy.type == ixgbe_phy_x550em_ext_t) 2449 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x; 2450 } 2451 } 2452 2453 int 2454 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 2455 uint16_t tx_rate, uint64_t q_msk) 2456 { 2457 struct ixgbe_hw *hw; 2458 struct ixgbe_vf_info *vfinfo; 2459 struct rte_eth_link link; 2460 uint8_t nb_q_per_pool; 2461 uint32_t queue_stride; 2462 uint32_t queue_idx, idx = 0, vf_idx; 2463 uint32_t queue_end; 2464 uint16_t total_rate = 0; 2465 struct rte_pci_device *pci_dev; 2466 int ret; 2467 2468 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2469 ret = rte_eth_link_get_nowait(dev->data->port_id, &link); 2470 if (ret < 0) 2471 return ret; 2472 2473 if (vf >= pci_dev->max_vfs) 2474 return -EINVAL; 2475 2476 if (tx_rate > link.link_speed) 2477 return -EINVAL; 2478 2479 if (q_msk == 0) 2480 return 0; 2481 2482 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2483 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 2484 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2485 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2486 queue_idx = vf * queue_stride; 2487 queue_end = queue_idx + nb_q_per_pool - 1; 2488 if (queue_end >= hw->mac.max_tx_queues) 2489 return -EINVAL; 2490 2491 if (vfinfo) { 2492 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) { 2493 if (vf_idx == vf) 2494 continue; 2495 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate); 2496 idx++) 2497 total_rate += vfinfo[vf_idx].tx_rate[idx]; 2498 } 2499 } else { 2500 return -EINVAL; 2501 } 2502 2503 /* Store tx_rate for this vf. */ 2504 for (idx = 0; idx < nb_q_per_pool; idx++) { 2505 if (((uint64_t)0x1 << idx) & q_msk) { 2506 if (vfinfo[vf].tx_rate[idx] != tx_rate) 2507 vfinfo[vf].tx_rate[idx] = tx_rate; 2508 total_rate += tx_rate; 2509 } 2510 } 2511 2512 if (total_rate > dev->data->dev_link.link_speed) { 2513 /* Reset stored TX rate of the VF if it causes exceed 2514 * link speed. 2515 */ 2516 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate)); 2517 return -EINVAL; 2518 } 2519 2520 /* Set RTTBCNRC of each queue/pool for vf X */ 2521 for (; queue_idx <= queue_end; queue_idx++) { 2522 if (0x1 & q_msk) 2523 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate); 2524 q_msk = q_msk >> 1; 2525 } 2526 2527 return 0; 2528 } 2529 2530 /* 2531 * Configure device link speed and setup link. 2532 * It returns 0 on success. 2533 */ 2534 static int 2535 ixgbe_dev_start(struct rte_eth_dev *dev) 2536 { 2537 struct ixgbe_hw *hw = 2538 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2539 struct ixgbe_vf_info *vfinfo = 2540 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2541 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2542 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2543 uint32_t intr_vector = 0; 2544 int err, link_up = 0, negotiate = 0; 2545 uint32_t speed = 0; 2546 uint32_t allowed_speeds = 0; 2547 int mask = 0; 2548 int status; 2549 uint16_t vf, idx; 2550 uint32_t *link_speeds; 2551 struct ixgbe_tm_conf *tm_conf = 2552 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2553 struct ixgbe_macsec_setting *macsec_setting = 2554 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 2555 2556 PMD_INIT_FUNC_TRACE(); 2557 2558 /* IXGBE devices don't support: 2559 * - half duplex (checked afterwards for valid speeds) 2560 * - fixed speed: TODO implement 2561 */ 2562 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) { 2563 PMD_INIT_LOG(ERR, 2564 "Invalid link_speeds for port %u, fix speed not supported", 2565 dev->data->port_id); 2566 return -EINVAL; 2567 } 2568 2569 /* Stop the link setup handler before resetting the HW. */ 2570 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 2571 2572 /* disable uio/vfio intr/eventfd mapping */ 2573 rte_intr_disable(intr_handle); 2574 2575 /* stop adapter */ 2576 hw->adapter_stopped = 0; 2577 ixgbe_stop_adapter(hw); 2578 2579 /* reinitialize adapter 2580 * this calls reset and start 2581 */ 2582 status = ixgbe_pf_reset_hw(hw); 2583 if (status != 0) 2584 return -1; 2585 hw->mac.ops.start_hw(hw); 2586 hw->mac.get_link_status = true; 2587 2588 /* configure PF module if SRIOV enabled */ 2589 ixgbe_pf_host_configure(dev); 2590 2591 ixgbe_dev_phy_intr_setup(dev); 2592 2593 /* check and configure queue intr-vector mapping */ 2594 if ((rte_intr_cap_multiple(intr_handle) || 2595 !RTE_ETH_DEV_SRIOV(dev).active) && 2596 dev->data->dev_conf.intr_conf.rxq != 0) { 2597 intr_vector = dev->data->nb_rx_queues; 2598 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) { 2599 PMD_INIT_LOG(ERR, "At most %d intr queues supported", 2600 IXGBE_MAX_INTR_QUEUE_NUM); 2601 return -ENOTSUP; 2602 } 2603 if (rte_intr_efd_enable(intr_handle, intr_vector)) 2604 return -1; 2605 } 2606 2607 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 2608 intr_handle->intr_vec = 2609 rte_zmalloc("intr_vec", 2610 dev->data->nb_rx_queues * sizeof(int), 0); 2611 if (intr_handle->intr_vec == NULL) { 2612 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 2613 " intr_vec", dev->data->nb_rx_queues); 2614 return -ENOMEM; 2615 } 2616 } 2617 2618 /* confiugre msix for sleep until rx interrupt */ 2619 ixgbe_configure_msix(dev); 2620 2621 /* initialize transmission unit */ 2622 ixgbe_dev_tx_init(dev); 2623 2624 /* This can fail when allocating mbufs for descriptor rings */ 2625 err = ixgbe_dev_rx_init(dev); 2626 if (err) { 2627 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 2628 goto error; 2629 } 2630 2631 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 2632 ETH_VLAN_EXTEND_MASK; 2633 err = ixgbe_vlan_offload_config(dev, mask); 2634 if (err) { 2635 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 2636 goto error; 2637 } 2638 2639 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) { 2640 /* Enable vlan filtering for VMDq */ 2641 ixgbe_vmdq_vlan_hw_filter_enable(dev); 2642 } 2643 2644 /* Configure DCB hw */ 2645 ixgbe_configure_dcb(dev); 2646 2647 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) { 2648 err = ixgbe_fdir_configure(dev); 2649 if (err) 2650 goto error; 2651 } 2652 2653 /* Restore vf rate limit */ 2654 if (vfinfo != NULL) { 2655 for (vf = 0; vf < pci_dev->max_vfs; vf++) 2656 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++) 2657 if (vfinfo[vf].tx_rate[idx] != 0) 2658 ixgbe_set_vf_rate_limit( 2659 dev, vf, 2660 vfinfo[vf].tx_rate[idx], 2661 1 << idx); 2662 } 2663 2664 ixgbe_restore_statistics_mapping(dev); 2665 2666 err = ixgbe_dev_rxtx_start(dev); 2667 if (err < 0) { 2668 PMD_INIT_LOG(ERR, "Unable to start rxtx queues"); 2669 goto error; 2670 } 2671 2672 /* Skip link setup if loopback mode is enabled. */ 2673 if (dev->data->dev_conf.lpbk_mode != 0) { 2674 err = ixgbe_check_supported_loopback_mode(dev); 2675 if (err < 0) { 2676 PMD_INIT_LOG(ERR, "Unsupported loopback mode"); 2677 goto error; 2678 } else { 2679 goto skip_link_setup; 2680 } 2681 } 2682 2683 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) { 2684 err = hw->mac.ops.setup_sfp(hw); 2685 if (err) 2686 goto error; 2687 } 2688 2689 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2690 /* Turn on the copper */ 2691 ixgbe_set_phy_power(hw, true); 2692 } else { 2693 /* Turn on the laser */ 2694 ixgbe_enable_tx_laser(hw); 2695 } 2696 2697 err = ixgbe_check_link(hw, &speed, &link_up, 0); 2698 if (err) 2699 goto error; 2700 dev->data->dev_link.link_status = link_up; 2701 2702 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate); 2703 if (err) 2704 goto error; 2705 2706 switch (hw->mac.type) { 2707 case ixgbe_mac_X550: 2708 case ixgbe_mac_X550EM_x: 2709 case ixgbe_mac_X550EM_a: 2710 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2711 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G | 2712 ETH_LINK_SPEED_10G; 2713 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 2714 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 2715 allowed_speeds = ETH_LINK_SPEED_10M | 2716 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G; 2717 break; 2718 default: 2719 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2720 ETH_LINK_SPEED_10G; 2721 } 2722 2723 link_speeds = &dev->data->dev_conf.link_speeds; 2724 if (*link_speeds & ~allowed_speeds) { 2725 PMD_INIT_LOG(ERR, "Invalid link setting"); 2726 goto error; 2727 } 2728 2729 speed = 0x0; 2730 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) { 2731 switch (hw->mac.type) { 2732 case ixgbe_mac_82598EB: 2733 speed = IXGBE_LINK_SPEED_82598_AUTONEG; 2734 break; 2735 case ixgbe_mac_82599EB: 2736 case ixgbe_mac_X540: 2737 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2738 break; 2739 case ixgbe_mac_X550: 2740 case ixgbe_mac_X550EM_x: 2741 case ixgbe_mac_X550EM_a: 2742 speed = IXGBE_LINK_SPEED_X550_AUTONEG; 2743 break; 2744 default: 2745 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2746 } 2747 } else { 2748 if (*link_speeds & ETH_LINK_SPEED_10G) 2749 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2750 if (*link_speeds & ETH_LINK_SPEED_5G) 2751 speed |= IXGBE_LINK_SPEED_5GB_FULL; 2752 if (*link_speeds & ETH_LINK_SPEED_2_5G) 2753 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 2754 if (*link_speeds & ETH_LINK_SPEED_1G) 2755 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2756 if (*link_speeds & ETH_LINK_SPEED_100M) 2757 speed |= IXGBE_LINK_SPEED_100_FULL; 2758 if (*link_speeds & ETH_LINK_SPEED_10M) 2759 speed |= IXGBE_LINK_SPEED_10_FULL; 2760 } 2761 2762 err = ixgbe_setup_link(hw, speed, link_up); 2763 if (err) 2764 goto error; 2765 2766 skip_link_setup: 2767 2768 if (rte_intr_allow_others(intr_handle)) { 2769 /* check if lsc interrupt is enabled */ 2770 if (dev->data->dev_conf.intr_conf.lsc != 0) 2771 ixgbe_dev_lsc_interrupt_setup(dev, TRUE); 2772 else 2773 ixgbe_dev_lsc_interrupt_setup(dev, FALSE); 2774 ixgbe_dev_macsec_interrupt_setup(dev); 2775 } else { 2776 rte_intr_callback_unregister(intr_handle, 2777 ixgbe_dev_interrupt_handler, dev); 2778 if (dev->data->dev_conf.intr_conf.lsc != 0) 2779 PMD_INIT_LOG(INFO, "lsc won't enable because of" 2780 " no intr multiplex"); 2781 } 2782 2783 /* check if rxq interrupt is enabled */ 2784 if (dev->data->dev_conf.intr_conf.rxq != 0 && 2785 rte_intr_dp_is_en(intr_handle)) 2786 ixgbe_dev_rxq_interrupt_setup(dev); 2787 2788 /* enable uio/vfio intr/eventfd mapping */ 2789 rte_intr_enable(intr_handle); 2790 2791 /* resume enabled intr since hw reset */ 2792 ixgbe_enable_intr(dev); 2793 ixgbe_l2_tunnel_conf(dev); 2794 ixgbe_filter_restore(dev); 2795 2796 if (tm_conf->root && !tm_conf->committed) 2797 PMD_DRV_LOG(WARNING, 2798 "please call hierarchy_commit() " 2799 "before starting the port"); 2800 2801 /* 2802 * Update link status right before return, because it may 2803 * start link configuration process in a separate thread. 2804 */ 2805 ixgbe_dev_link_update(dev, 0); 2806 2807 /* setup the macsec setting register */ 2808 if (macsec_setting->offload_en) 2809 ixgbe_dev_macsec_register_enable(dev, macsec_setting); 2810 2811 return 0; 2812 2813 error: 2814 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err); 2815 ixgbe_dev_clear_queues(dev); 2816 return -EIO; 2817 } 2818 2819 /* 2820 * Stop device: disable rx and tx functions to allow for reconfiguring. 2821 */ 2822 static void 2823 ixgbe_dev_stop(struct rte_eth_dev *dev) 2824 { 2825 struct rte_eth_link link; 2826 struct ixgbe_adapter *adapter = dev->data->dev_private; 2827 struct ixgbe_hw *hw = 2828 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2829 struct ixgbe_vf_info *vfinfo = 2830 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2831 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2832 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2833 int vf; 2834 struct ixgbe_tm_conf *tm_conf = 2835 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2836 2837 if (hw->adapter_stopped) 2838 return; 2839 2840 PMD_INIT_FUNC_TRACE(); 2841 2842 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 2843 2844 /* disable interrupts */ 2845 ixgbe_disable_intr(hw); 2846 2847 /* reset the NIC */ 2848 ixgbe_pf_reset_hw(hw); 2849 hw->adapter_stopped = 0; 2850 2851 /* stop adapter */ 2852 ixgbe_stop_adapter(hw); 2853 2854 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++) 2855 vfinfo[vf].clear_to_send = false; 2856 2857 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2858 /* Turn off the copper */ 2859 ixgbe_set_phy_power(hw, false); 2860 } else { 2861 /* Turn off the laser */ 2862 ixgbe_disable_tx_laser(hw); 2863 } 2864 2865 ixgbe_dev_clear_queues(dev); 2866 2867 /* Clear stored conf */ 2868 dev->data->scattered_rx = 0; 2869 dev->data->lro = 0; 2870 2871 /* Clear recorded link status */ 2872 memset(&link, 0, sizeof(link)); 2873 rte_eth_linkstatus_set(dev, &link); 2874 2875 if (!rte_intr_allow_others(intr_handle)) 2876 /* resume to the default handler */ 2877 rte_intr_callback_register(intr_handle, 2878 ixgbe_dev_interrupt_handler, 2879 (void *)dev); 2880 2881 /* Clean datapath event and queue/vec mapping */ 2882 rte_intr_efd_disable(intr_handle); 2883 if (intr_handle->intr_vec != NULL) { 2884 rte_free(intr_handle->intr_vec); 2885 intr_handle->intr_vec = NULL; 2886 } 2887 2888 /* reset hierarchy commit */ 2889 tm_conf->committed = false; 2890 2891 adapter->rss_reta_updated = 0; 2892 2893 hw->adapter_stopped = true; 2894 } 2895 2896 /* 2897 * Set device link up: enable tx. 2898 */ 2899 static int 2900 ixgbe_dev_set_link_up(struct rte_eth_dev *dev) 2901 { 2902 struct ixgbe_hw *hw = 2903 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2904 if (hw->mac.type == ixgbe_mac_82599EB) { 2905 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2906 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2907 /* Not suported in bypass mode */ 2908 PMD_INIT_LOG(ERR, "Set link up is not supported " 2909 "by device id 0x%x", hw->device_id); 2910 return -ENOTSUP; 2911 } 2912 #endif 2913 } 2914 2915 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2916 /* Turn on the copper */ 2917 ixgbe_set_phy_power(hw, true); 2918 } else { 2919 /* Turn on the laser */ 2920 ixgbe_enable_tx_laser(hw); 2921 ixgbe_dev_link_update(dev, 0); 2922 } 2923 2924 return 0; 2925 } 2926 2927 /* 2928 * Set device link down: disable tx. 2929 */ 2930 static int 2931 ixgbe_dev_set_link_down(struct rte_eth_dev *dev) 2932 { 2933 struct ixgbe_hw *hw = 2934 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2935 if (hw->mac.type == ixgbe_mac_82599EB) { 2936 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2937 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2938 /* Not suported in bypass mode */ 2939 PMD_INIT_LOG(ERR, "Set link down is not supported " 2940 "by device id 0x%x", hw->device_id); 2941 return -ENOTSUP; 2942 } 2943 #endif 2944 } 2945 2946 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2947 /* Turn off the copper */ 2948 ixgbe_set_phy_power(hw, false); 2949 } else { 2950 /* Turn off the laser */ 2951 ixgbe_disable_tx_laser(hw); 2952 ixgbe_dev_link_update(dev, 0); 2953 } 2954 2955 return 0; 2956 } 2957 2958 /* 2959 * Reset and stop device. 2960 */ 2961 static void 2962 ixgbe_dev_close(struct rte_eth_dev *dev) 2963 { 2964 struct ixgbe_hw *hw = 2965 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2966 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2967 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2968 int retries = 0; 2969 int ret; 2970 2971 PMD_INIT_FUNC_TRACE(); 2972 2973 ixgbe_pf_reset_hw(hw); 2974 2975 ixgbe_dev_stop(dev); 2976 2977 ixgbe_dev_free_queues(dev); 2978 2979 ixgbe_disable_pcie_master(hw); 2980 2981 /* reprogram the RAR[0] in case user changed it. */ 2982 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2983 2984 dev->dev_ops = NULL; 2985 dev->rx_pkt_burst = NULL; 2986 dev->tx_pkt_burst = NULL; 2987 2988 /* Unlock any pending hardware semaphore */ 2989 ixgbe_swfw_lock_reset(hw); 2990 2991 /* disable uio intr before callback unregister */ 2992 rte_intr_disable(intr_handle); 2993 2994 do { 2995 ret = rte_intr_callback_unregister(intr_handle, 2996 ixgbe_dev_interrupt_handler, dev); 2997 if (ret >= 0 || ret == -ENOENT) { 2998 break; 2999 } else if (ret != -EAGAIN) { 3000 PMD_INIT_LOG(ERR, 3001 "intr callback unregister failed: %d", 3002 ret); 3003 } 3004 rte_delay_ms(100); 3005 } while (retries++ < (10 + IXGBE_LINK_UP_TIME)); 3006 3007 /* cancel the delay handler before remove dev */ 3008 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev); 3009 3010 /* uninitialize PF if max_vfs not zero */ 3011 ixgbe_pf_host_uninit(dev); 3012 3013 /* remove all the fdir filters & hash */ 3014 ixgbe_fdir_filter_uninit(dev); 3015 3016 /* remove all the L2 tunnel filters & hash */ 3017 ixgbe_l2_tn_filter_uninit(dev); 3018 3019 /* Remove all ntuple filters of the device */ 3020 ixgbe_ntuple_filter_uninit(dev); 3021 3022 /* clear all the filters list */ 3023 ixgbe_filterlist_flush(); 3024 3025 /* Remove all Traffic Manager configuration */ 3026 ixgbe_tm_conf_uninit(dev); 3027 3028 #ifdef RTE_LIBRTE_SECURITY 3029 rte_free(dev->security_ctx); 3030 #endif 3031 3032 } 3033 3034 /* 3035 * Reset PF device. 3036 */ 3037 static int 3038 ixgbe_dev_reset(struct rte_eth_dev *dev) 3039 { 3040 int ret; 3041 3042 /* When a DPDK PMD PF begin to reset PF port, it should notify all 3043 * its VF to make them align with it. The detailed notification 3044 * mechanism is PMD specific. As to ixgbe PF, it is rather complex. 3045 * To avoid unexpected behavior in VF, currently reset of PF with 3046 * SR-IOV activation is not supported. It might be supported later. 3047 */ 3048 if (dev->data->sriov.active) 3049 return -ENOTSUP; 3050 3051 ret = eth_ixgbe_dev_uninit(dev); 3052 if (ret) 3053 return ret; 3054 3055 ret = eth_ixgbe_dev_init(dev, NULL); 3056 3057 return ret; 3058 } 3059 3060 static void 3061 ixgbe_read_stats_registers(struct ixgbe_hw *hw, 3062 struct ixgbe_hw_stats *hw_stats, 3063 struct ixgbe_macsec_stats *macsec_stats, 3064 uint64_t *total_missed_rx, uint64_t *total_qbrc, 3065 uint64_t *total_qprc, uint64_t *total_qprdc) 3066 { 3067 uint32_t bprc, lxon, lxoff, total; 3068 uint32_t delta_gprc = 0; 3069 unsigned i; 3070 /* Workaround for RX byte count not including CRC bytes when CRC 3071 * strip is enabled. CRC bytes are removed from counters when crc_strip 3072 * is disabled. 3073 */ 3074 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) & 3075 IXGBE_HLREG0_RXCRCSTRP); 3076 3077 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 3078 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC); 3079 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC); 3080 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC); 3081 3082 for (i = 0; i < 8; i++) { 3083 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 3084 3085 /* global total per queue */ 3086 hw_stats->mpc[i] += mp; 3087 /* Running comprehensive total for stats display */ 3088 *total_missed_rx += hw_stats->mpc[i]; 3089 if (hw->mac.type == ixgbe_mac_82598EB) { 3090 hw_stats->rnbc[i] += 3091 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 3092 hw_stats->pxonrxc[i] += 3093 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 3094 hw_stats->pxoffrxc[i] += 3095 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 3096 } else { 3097 hw_stats->pxonrxc[i] += 3098 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 3099 hw_stats->pxoffrxc[i] += 3100 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 3101 hw_stats->pxon2offc[i] += 3102 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 3103 } 3104 hw_stats->pxontxc[i] += 3105 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 3106 hw_stats->pxofftxc[i] += 3107 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 3108 } 3109 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3110 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 3111 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 3112 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 3113 3114 delta_gprc += delta_qprc; 3115 3116 hw_stats->qprc[i] += delta_qprc; 3117 hw_stats->qptc[i] += delta_qptc; 3118 3119 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 3120 hw_stats->qbrc[i] += 3121 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32); 3122 if (crc_strip == 0) 3123 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN; 3124 3125 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 3126 hw_stats->qbtc[i] += 3127 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32); 3128 3129 hw_stats->qprdc[i] += delta_qprdc; 3130 *total_qprdc += hw_stats->qprdc[i]; 3131 3132 *total_qprc += hw_stats->qprc[i]; 3133 *total_qbrc += hw_stats->qbrc[i]; 3134 } 3135 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC); 3136 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC); 3137 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 3138 3139 /* 3140 * An errata states that gprc actually counts good + missed packets: 3141 * Workaround to set gprc to summated queue packet receives 3142 */ 3143 hw_stats->gprc = *total_qprc; 3144 3145 if (hw->mac.type != ixgbe_mac_82598EB) { 3146 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 3147 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32); 3148 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 3149 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32); 3150 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 3151 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32); 3152 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 3153 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 3154 } else { 3155 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 3156 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 3157 /* 82598 only has a counter in the high register */ 3158 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 3159 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 3160 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 3161 } 3162 uint64_t old_tpr = hw_stats->tpr; 3163 3164 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 3165 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT); 3166 3167 if (crc_strip == 0) 3168 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN; 3169 3170 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC); 3171 hw_stats->gptc += delta_gptc; 3172 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN; 3173 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN; 3174 3175 /* 3176 * Workaround: mprc hardware is incorrectly counting 3177 * broadcasts, so for now we subtract those. 3178 */ 3179 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 3180 hw_stats->bprc += bprc; 3181 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 3182 if (hw->mac.type == ixgbe_mac_82598EB) 3183 hw_stats->mprc -= bprc; 3184 3185 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 3186 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 3187 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 3188 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 3189 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 3190 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 3191 3192 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 3193 hw_stats->lxontxc += lxon; 3194 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 3195 hw_stats->lxofftxc += lxoff; 3196 total = lxon + lxoff; 3197 3198 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 3199 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 3200 hw_stats->gptc -= total; 3201 hw_stats->mptc -= total; 3202 hw_stats->ptc64 -= total; 3203 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN; 3204 3205 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 3206 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 3207 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 3208 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 3209 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC); 3210 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC); 3211 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC); 3212 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 3213 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 3214 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 3215 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 3216 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 3217 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 3218 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC); 3219 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 3220 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST); 3221 /* Only read FCOE on 82599 */ 3222 if (hw->mac.type != ixgbe_mac_82598EB) { 3223 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 3224 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 3225 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 3226 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 3227 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 3228 } 3229 3230 /* Flow Director Stats registers */ 3231 if (hw->mac.type != ixgbe_mac_82598EB) { 3232 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 3233 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 3234 hw_stats->fdirustat_add += IXGBE_READ_REG(hw, 3235 IXGBE_FDIRUSTAT) & 0xFFFF; 3236 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw, 3237 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF; 3238 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw, 3239 IXGBE_FDIRFSTAT) & 0xFFFF; 3240 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw, 3241 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF; 3242 } 3243 /* MACsec Stats registers */ 3244 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT); 3245 macsec_stats->out_pkts_encrypted += 3246 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE); 3247 macsec_stats->out_pkts_protected += 3248 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP); 3249 macsec_stats->out_octets_encrypted += 3250 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE); 3251 macsec_stats->out_octets_protected += 3252 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP); 3253 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT); 3254 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD); 3255 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI); 3256 macsec_stats->in_pkts_unknownsci += 3257 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI); 3258 macsec_stats->in_octets_decrypted += 3259 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD); 3260 macsec_stats->in_octets_validated += 3261 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV); 3262 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH); 3263 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY); 3264 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE); 3265 for (i = 0; i < 2; i++) { 3266 macsec_stats->in_pkts_ok += 3267 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i)); 3268 macsec_stats->in_pkts_invalid += 3269 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i)); 3270 macsec_stats->in_pkts_notvalid += 3271 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i)); 3272 } 3273 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA); 3274 macsec_stats->in_pkts_notusingsa += 3275 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA); 3276 } 3277 3278 /* 3279 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c 3280 */ 3281 static int 3282 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3283 { 3284 struct ixgbe_hw *hw = 3285 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3286 struct ixgbe_hw_stats *hw_stats = 3287 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3288 struct ixgbe_macsec_stats *macsec_stats = 3289 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3290 dev->data->dev_private); 3291 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3292 unsigned i; 3293 3294 total_missed_rx = 0; 3295 total_qbrc = 0; 3296 total_qprc = 0; 3297 total_qprdc = 0; 3298 3299 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3300 &total_qbrc, &total_qprc, &total_qprdc); 3301 3302 if (stats == NULL) 3303 return -EINVAL; 3304 3305 /* Fill out the rte_eth_stats statistics structure */ 3306 stats->ipackets = total_qprc; 3307 stats->ibytes = total_qbrc; 3308 stats->opackets = hw_stats->gptc; 3309 stats->obytes = hw_stats->gotc; 3310 3311 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3312 stats->q_ipackets[i] = hw_stats->qprc[i]; 3313 stats->q_opackets[i] = hw_stats->qptc[i]; 3314 stats->q_ibytes[i] = hw_stats->qbrc[i]; 3315 stats->q_obytes[i] = hw_stats->qbtc[i]; 3316 stats->q_errors[i] = hw_stats->qprdc[i]; 3317 } 3318 3319 /* Rx Errors */ 3320 stats->imissed = total_missed_rx; 3321 stats->ierrors = hw_stats->crcerrs + 3322 hw_stats->mspdc + 3323 hw_stats->rlec + 3324 hw_stats->ruc + 3325 hw_stats->roc + 3326 hw_stats->illerrc + 3327 hw_stats->errbc + 3328 hw_stats->rfc + 3329 hw_stats->fccrc + 3330 hw_stats->fclast; 3331 3332 /* Tx Errors */ 3333 stats->oerrors = 0; 3334 return 0; 3335 } 3336 3337 static int 3338 ixgbe_dev_stats_reset(struct rte_eth_dev *dev) 3339 { 3340 struct ixgbe_hw_stats *stats = 3341 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3342 3343 /* HW registers are cleared on read */ 3344 ixgbe_dev_stats_get(dev, NULL); 3345 3346 /* Reset software totals */ 3347 memset(stats, 0, sizeof(*stats)); 3348 3349 return 0; 3350 } 3351 3352 /* This function calculates the number of xstats based on the current config */ 3353 static unsigned 3354 ixgbe_xstats_calc_num(void) { 3355 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS + 3356 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) + 3357 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES); 3358 } 3359 3360 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3361 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size) 3362 { 3363 const unsigned cnt_stats = ixgbe_xstats_calc_num(); 3364 unsigned stat, i, count; 3365 3366 if (xstats_names != NULL) { 3367 count = 0; 3368 3369 /* Note: limit >= cnt_stats checked upstream 3370 * in rte_eth_xstats_names() 3371 */ 3372 3373 /* Extended stats from ixgbe_hw_stats */ 3374 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3375 strlcpy(xstats_names[count].name, 3376 rte_ixgbe_stats_strings[i].name, 3377 sizeof(xstats_names[count].name)); 3378 count++; 3379 } 3380 3381 /* MACsec Stats */ 3382 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3383 strlcpy(xstats_names[count].name, 3384 rte_ixgbe_macsec_strings[i].name, 3385 sizeof(xstats_names[count].name)); 3386 count++; 3387 } 3388 3389 /* RX Priority Stats */ 3390 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3391 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3392 snprintf(xstats_names[count].name, 3393 sizeof(xstats_names[count].name), 3394 "rx_priority%u_%s", i, 3395 rte_ixgbe_rxq_strings[stat].name); 3396 count++; 3397 } 3398 } 3399 3400 /* TX Priority Stats */ 3401 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3402 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3403 snprintf(xstats_names[count].name, 3404 sizeof(xstats_names[count].name), 3405 "tx_priority%u_%s", i, 3406 rte_ixgbe_txq_strings[stat].name); 3407 count++; 3408 } 3409 } 3410 } 3411 return cnt_stats; 3412 } 3413 3414 static int ixgbe_dev_xstats_get_names_by_id( 3415 struct rte_eth_dev *dev, 3416 struct rte_eth_xstat_name *xstats_names, 3417 const uint64_t *ids, 3418 unsigned int limit) 3419 { 3420 if (!ids) { 3421 const unsigned int cnt_stats = ixgbe_xstats_calc_num(); 3422 unsigned int stat, i, count; 3423 3424 if (xstats_names != NULL) { 3425 count = 0; 3426 3427 /* Note: limit >= cnt_stats checked upstream 3428 * in rte_eth_xstats_names() 3429 */ 3430 3431 /* Extended stats from ixgbe_hw_stats */ 3432 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3433 strlcpy(xstats_names[count].name, 3434 rte_ixgbe_stats_strings[i].name, 3435 sizeof(xstats_names[count].name)); 3436 count++; 3437 } 3438 3439 /* MACsec Stats */ 3440 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3441 strlcpy(xstats_names[count].name, 3442 rte_ixgbe_macsec_strings[i].name, 3443 sizeof(xstats_names[count].name)); 3444 count++; 3445 } 3446 3447 /* RX Priority Stats */ 3448 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3449 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3450 snprintf(xstats_names[count].name, 3451 sizeof(xstats_names[count].name), 3452 "rx_priority%u_%s", i, 3453 rte_ixgbe_rxq_strings[stat].name); 3454 count++; 3455 } 3456 } 3457 3458 /* TX Priority Stats */ 3459 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3460 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3461 snprintf(xstats_names[count].name, 3462 sizeof(xstats_names[count].name), 3463 "tx_priority%u_%s", i, 3464 rte_ixgbe_txq_strings[stat].name); 3465 count++; 3466 } 3467 } 3468 } 3469 return cnt_stats; 3470 } 3471 3472 uint16_t i; 3473 uint16_t size = ixgbe_xstats_calc_num(); 3474 struct rte_eth_xstat_name xstats_names_copy[size]; 3475 3476 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL, 3477 size); 3478 3479 for (i = 0; i < limit; i++) { 3480 if (ids[i] >= size) { 3481 PMD_INIT_LOG(ERR, "id value isn't valid"); 3482 return -1; 3483 } 3484 strcpy(xstats_names[i].name, 3485 xstats_names_copy[ids[i]].name); 3486 } 3487 return limit; 3488 } 3489 3490 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3491 struct rte_eth_xstat_name *xstats_names, unsigned limit) 3492 { 3493 unsigned i; 3494 3495 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL) 3496 return -ENOMEM; 3497 3498 if (xstats_names != NULL) 3499 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) 3500 strlcpy(xstats_names[i].name, 3501 rte_ixgbevf_stats_strings[i].name, 3502 sizeof(xstats_names[i].name)); 3503 return IXGBEVF_NB_XSTATS; 3504 } 3505 3506 static int 3507 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3508 unsigned n) 3509 { 3510 struct ixgbe_hw *hw = 3511 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3512 struct ixgbe_hw_stats *hw_stats = 3513 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3514 struct ixgbe_macsec_stats *macsec_stats = 3515 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3516 dev->data->dev_private); 3517 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3518 unsigned i, stat, count = 0; 3519 3520 count = ixgbe_xstats_calc_num(); 3521 3522 if (n < count) 3523 return count; 3524 3525 total_missed_rx = 0; 3526 total_qbrc = 0; 3527 total_qprc = 0; 3528 total_qprdc = 0; 3529 3530 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3531 &total_qbrc, &total_qprc, &total_qprdc); 3532 3533 /* If this is a reset xstats is NULL, and we have cleared the 3534 * registers by reading them. 3535 */ 3536 if (!xstats) 3537 return 0; 3538 3539 /* Extended stats from ixgbe_hw_stats */ 3540 count = 0; 3541 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3542 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3543 rte_ixgbe_stats_strings[i].offset); 3544 xstats[count].id = count; 3545 count++; 3546 } 3547 3548 /* MACsec Stats */ 3549 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3550 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) + 3551 rte_ixgbe_macsec_strings[i].offset); 3552 xstats[count].id = count; 3553 count++; 3554 } 3555 3556 /* RX Priority Stats */ 3557 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3558 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3559 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3560 rte_ixgbe_rxq_strings[stat].offset + 3561 (sizeof(uint64_t) * i)); 3562 xstats[count].id = count; 3563 count++; 3564 } 3565 } 3566 3567 /* TX Priority Stats */ 3568 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3569 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3570 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3571 rte_ixgbe_txq_strings[stat].offset + 3572 (sizeof(uint64_t) * i)); 3573 xstats[count].id = count; 3574 count++; 3575 } 3576 } 3577 return count; 3578 } 3579 3580 static int 3581 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 3582 uint64_t *values, unsigned int n) 3583 { 3584 if (!ids) { 3585 struct ixgbe_hw *hw = 3586 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3587 struct ixgbe_hw_stats *hw_stats = 3588 IXGBE_DEV_PRIVATE_TO_STATS( 3589 dev->data->dev_private); 3590 struct ixgbe_macsec_stats *macsec_stats = 3591 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3592 dev->data->dev_private); 3593 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3594 unsigned int i, stat, count = 0; 3595 3596 count = ixgbe_xstats_calc_num(); 3597 3598 if (!ids && n < count) 3599 return count; 3600 3601 total_missed_rx = 0; 3602 total_qbrc = 0; 3603 total_qprc = 0; 3604 total_qprdc = 0; 3605 3606 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, 3607 &total_missed_rx, &total_qbrc, &total_qprc, 3608 &total_qprdc); 3609 3610 /* If this is a reset xstats is NULL, and we have cleared the 3611 * registers by reading them. 3612 */ 3613 if (!ids && !values) 3614 return 0; 3615 3616 /* Extended stats from ixgbe_hw_stats */ 3617 count = 0; 3618 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3619 values[count] = *(uint64_t *)(((char *)hw_stats) + 3620 rte_ixgbe_stats_strings[i].offset); 3621 count++; 3622 } 3623 3624 /* MACsec Stats */ 3625 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3626 values[count] = *(uint64_t *)(((char *)macsec_stats) + 3627 rte_ixgbe_macsec_strings[i].offset); 3628 count++; 3629 } 3630 3631 /* RX Priority Stats */ 3632 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3633 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3634 values[count] = 3635 *(uint64_t *)(((char *)hw_stats) + 3636 rte_ixgbe_rxq_strings[stat].offset + 3637 (sizeof(uint64_t) * i)); 3638 count++; 3639 } 3640 } 3641 3642 /* TX Priority Stats */ 3643 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3644 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3645 values[count] = 3646 *(uint64_t *)(((char *)hw_stats) + 3647 rte_ixgbe_txq_strings[stat].offset + 3648 (sizeof(uint64_t) * i)); 3649 count++; 3650 } 3651 } 3652 return count; 3653 } 3654 3655 uint16_t i; 3656 uint16_t size = ixgbe_xstats_calc_num(); 3657 uint64_t values_copy[size]; 3658 3659 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size); 3660 3661 for (i = 0; i < n; i++) { 3662 if (ids[i] >= size) { 3663 PMD_INIT_LOG(ERR, "id value isn't valid"); 3664 return -1; 3665 } 3666 values[i] = values_copy[ids[i]]; 3667 } 3668 return n; 3669 } 3670 3671 static int 3672 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev) 3673 { 3674 struct ixgbe_hw_stats *stats = 3675 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3676 struct ixgbe_macsec_stats *macsec_stats = 3677 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3678 dev->data->dev_private); 3679 3680 unsigned count = ixgbe_xstats_calc_num(); 3681 3682 /* HW registers are cleared on read */ 3683 ixgbe_dev_xstats_get(dev, NULL, count); 3684 3685 /* Reset software totals */ 3686 memset(stats, 0, sizeof(*stats)); 3687 memset(macsec_stats, 0, sizeof(*macsec_stats)); 3688 3689 return 0; 3690 } 3691 3692 static void 3693 ixgbevf_update_stats(struct rte_eth_dev *dev) 3694 { 3695 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3696 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3697 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3698 3699 /* Good Rx packet, include VF loopback */ 3700 UPDATE_VF_STAT(IXGBE_VFGPRC, 3701 hw_stats->last_vfgprc, hw_stats->vfgprc); 3702 3703 /* Good Rx octets, include VF loopback */ 3704 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB, 3705 hw_stats->last_vfgorc, hw_stats->vfgorc); 3706 3707 /* Good Tx packet, include VF loopback */ 3708 UPDATE_VF_STAT(IXGBE_VFGPTC, 3709 hw_stats->last_vfgptc, hw_stats->vfgptc); 3710 3711 /* Good Tx octets, include VF loopback */ 3712 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB, 3713 hw_stats->last_vfgotc, hw_stats->vfgotc); 3714 3715 /* Rx Multicst Packet */ 3716 UPDATE_VF_STAT(IXGBE_VFMPRC, 3717 hw_stats->last_vfmprc, hw_stats->vfmprc); 3718 } 3719 3720 static int 3721 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3722 unsigned n) 3723 { 3724 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3725 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3726 unsigned i; 3727 3728 if (n < IXGBEVF_NB_XSTATS) 3729 return IXGBEVF_NB_XSTATS; 3730 3731 ixgbevf_update_stats(dev); 3732 3733 if (!xstats) 3734 return 0; 3735 3736 /* Extended stats */ 3737 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) { 3738 xstats[i].id = i; 3739 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + 3740 rte_ixgbevf_stats_strings[i].offset); 3741 } 3742 3743 return IXGBEVF_NB_XSTATS; 3744 } 3745 3746 static int 3747 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3748 { 3749 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3750 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3751 3752 ixgbevf_update_stats(dev); 3753 3754 if (stats == NULL) 3755 return -EINVAL; 3756 3757 stats->ipackets = hw_stats->vfgprc; 3758 stats->ibytes = hw_stats->vfgorc; 3759 stats->opackets = hw_stats->vfgptc; 3760 stats->obytes = hw_stats->vfgotc; 3761 return 0; 3762 } 3763 3764 static int 3765 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev) 3766 { 3767 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3768 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3769 3770 /* Sync HW register to the last stats */ 3771 ixgbevf_dev_stats_get(dev, NULL); 3772 3773 /* reset HW current stats*/ 3774 hw_stats->vfgprc = 0; 3775 hw_stats->vfgorc = 0; 3776 hw_stats->vfgptc = 0; 3777 hw_stats->vfgotc = 0; 3778 3779 return 0; 3780 } 3781 3782 static int 3783 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 3784 { 3785 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3786 u16 eeprom_verh, eeprom_verl; 3787 u32 etrack_id; 3788 int ret; 3789 3790 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh); 3791 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl); 3792 3793 etrack_id = (eeprom_verh << 16) | eeprom_verl; 3794 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id); 3795 3796 ret += 1; /* add the size of '\0' */ 3797 if (fw_size < (u32)ret) 3798 return ret; 3799 else 3800 return 0; 3801 } 3802 3803 static int 3804 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3805 { 3806 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3807 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3808 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 3809 3810 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3811 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3812 if (RTE_ETH_DEV_SRIOV(dev).active == 0) { 3813 /* 3814 * When DCB/VT is off, maximum number of queues changes, 3815 * except for 82598EB, which remains constant. 3816 */ 3817 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 3818 hw->mac.type != ixgbe_mac_82598EB) 3819 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES; 3820 } 3821 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */ 3822 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */ 3823 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3824 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3825 dev_info->max_vfs = pci_dev->max_vfs; 3826 if (hw->mac.type == ixgbe_mac_82598EB) 3827 dev_info->max_vmdq_pools = ETH_16_POOLS; 3828 else 3829 dev_info->max_vmdq_pools = ETH_64_POOLS; 3830 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD; 3831 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 3832 dev_info->vmdq_queue_num = dev_info->max_rx_queues; 3833 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3834 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3835 dev_info->rx_queue_offload_capa); 3836 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3837 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3838 3839 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3840 .rx_thresh = { 3841 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3842 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3843 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3844 }, 3845 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3846 .rx_drop_en = 0, 3847 .offloads = 0, 3848 }; 3849 3850 dev_info->default_txconf = (struct rte_eth_txconf) { 3851 .tx_thresh = { 3852 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3853 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3854 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3855 }, 3856 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3857 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3858 .offloads = 0, 3859 }; 3860 3861 dev_info->rx_desc_lim = rx_desc_lim; 3862 dev_info->tx_desc_lim = tx_desc_lim; 3863 3864 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 3865 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 3866 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 3867 3868 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 3869 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 3870 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 3871 dev_info->speed_capa = ETH_LINK_SPEED_10M | 3872 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G; 3873 3874 if (hw->mac.type == ixgbe_mac_X540 || 3875 hw->mac.type == ixgbe_mac_X540_vf || 3876 hw->mac.type == ixgbe_mac_X550 || 3877 hw->mac.type == ixgbe_mac_X550_vf) { 3878 dev_info->speed_capa |= ETH_LINK_SPEED_100M; 3879 } 3880 if (hw->mac.type == ixgbe_mac_X550) { 3881 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G; 3882 dev_info->speed_capa |= ETH_LINK_SPEED_5G; 3883 } 3884 3885 /* Driver-preferred Rx/Tx parameters */ 3886 dev_info->default_rxportconf.burst_size = 32; 3887 dev_info->default_txportconf.burst_size = 32; 3888 dev_info->default_rxportconf.nb_queues = 1; 3889 dev_info->default_txportconf.nb_queues = 1; 3890 dev_info->default_rxportconf.ring_size = 256; 3891 dev_info->default_txportconf.ring_size = 256; 3892 3893 return 0; 3894 } 3895 3896 static const uint32_t * 3897 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 3898 { 3899 static const uint32_t ptypes[] = { 3900 /* For non-vec functions, 3901 * refers to ixgbe_rxd_pkt_info_to_pkt_type(); 3902 * for vec functions, 3903 * refers to _recv_raw_pkts_vec(). 3904 */ 3905 RTE_PTYPE_L2_ETHER, 3906 RTE_PTYPE_L3_IPV4, 3907 RTE_PTYPE_L3_IPV4_EXT, 3908 RTE_PTYPE_L3_IPV6, 3909 RTE_PTYPE_L3_IPV6_EXT, 3910 RTE_PTYPE_L4_SCTP, 3911 RTE_PTYPE_L4_TCP, 3912 RTE_PTYPE_L4_UDP, 3913 RTE_PTYPE_TUNNEL_IP, 3914 RTE_PTYPE_INNER_L3_IPV6, 3915 RTE_PTYPE_INNER_L3_IPV6_EXT, 3916 RTE_PTYPE_INNER_L4_TCP, 3917 RTE_PTYPE_INNER_L4_UDP, 3918 RTE_PTYPE_UNKNOWN 3919 }; 3920 3921 if (dev->rx_pkt_burst == ixgbe_recv_pkts || 3922 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc || 3923 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc || 3924 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc) 3925 return ptypes; 3926 3927 #if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_NEON) 3928 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec || 3929 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec) 3930 return ptypes; 3931 #endif 3932 return NULL; 3933 } 3934 3935 static int 3936 ixgbevf_dev_info_get(struct rte_eth_dev *dev, 3937 struct rte_eth_dev_info *dev_info) 3938 { 3939 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3940 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3941 3942 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3943 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3944 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */ 3945 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */ 3946 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD; 3947 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3948 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3949 dev_info->max_vfs = pci_dev->max_vfs; 3950 if (hw->mac.type == ixgbe_mac_82598EB) 3951 dev_info->max_vmdq_pools = ETH_16_POOLS; 3952 else 3953 dev_info->max_vmdq_pools = ETH_64_POOLS; 3954 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3955 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3956 dev_info->rx_queue_offload_capa); 3957 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3958 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3959 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 3960 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 3961 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 3962 3963 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3964 .rx_thresh = { 3965 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3966 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3967 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3968 }, 3969 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3970 .rx_drop_en = 0, 3971 .offloads = 0, 3972 }; 3973 3974 dev_info->default_txconf = (struct rte_eth_txconf) { 3975 .tx_thresh = { 3976 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3977 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3978 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3979 }, 3980 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3981 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3982 .offloads = 0, 3983 }; 3984 3985 dev_info->rx_desc_lim = rx_desc_lim; 3986 dev_info->tx_desc_lim = tx_desc_lim; 3987 3988 return 0; 3989 } 3990 3991 static int 3992 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3993 int *link_up, int wait_to_complete) 3994 { 3995 struct ixgbe_adapter *adapter = container_of(hw, 3996 struct ixgbe_adapter, hw); 3997 struct ixgbe_mbx_info *mbx = &hw->mbx; 3998 struct ixgbe_mac_info *mac = &hw->mac; 3999 uint32_t links_reg, in_msg; 4000 int ret_val = 0; 4001 4002 /* If we were hit with a reset drop the link */ 4003 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout) 4004 mac->get_link_status = true; 4005 4006 if (!mac->get_link_status) 4007 goto out; 4008 4009 /* if link status is down no point in checking to see if pf is up */ 4010 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 4011 if (!(links_reg & IXGBE_LINKS_UP)) 4012 goto out; 4013 4014 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs 4015 * before the link status is correct 4016 */ 4017 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) { 4018 int i; 4019 4020 for (i = 0; i < 5; i++) { 4021 rte_delay_us(100); 4022 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 4023 4024 if (!(links_reg & IXGBE_LINKS_UP)) 4025 goto out; 4026 } 4027 } 4028 4029 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 4030 case IXGBE_LINKS_SPEED_10G_82599: 4031 *speed = IXGBE_LINK_SPEED_10GB_FULL; 4032 if (hw->mac.type >= ixgbe_mac_X550) { 4033 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4034 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4035 } 4036 break; 4037 case IXGBE_LINKS_SPEED_1G_82599: 4038 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4039 break; 4040 case IXGBE_LINKS_SPEED_100_82599: 4041 *speed = IXGBE_LINK_SPEED_100_FULL; 4042 if (hw->mac.type == ixgbe_mac_X550) { 4043 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4044 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4045 } 4046 break; 4047 case IXGBE_LINKS_SPEED_10_X550EM_A: 4048 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4049 /* Since Reserved in older MAC's */ 4050 if (hw->mac.type >= ixgbe_mac_X550) 4051 *speed = IXGBE_LINK_SPEED_10_FULL; 4052 break; 4053 default: 4054 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4055 } 4056 4057 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) { 4058 if (*speed == IXGBE_LINK_SPEED_UNKNOWN) 4059 mac->get_link_status = true; 4060 else 4061 mac->get_link_status = false; 4062 4063 goto out; 4064 } 4065 4066 /* if the read failed it could just be a mailbox collision, best wait 4067 * until we are called again and don't report an error 4068 */ 4069 if (mbx->ops.read(hw, &in_msg, 1, 0)) 4070 goto out; 4071 4072 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) { 4073 /* msg is not CTS and is NACK we must have lost CTS status */ 4074 if (in_msg & IXGBE_VT_MSGTYPE_NACK) 4075 mac->get_link_status = false; 4076 goto out; 4077 } 4078 4079 /* the pf is talking, if we timed out in the past we reinit */ 4080 if (!mbx->timeout) { 4081 ret_val = -1; 4082 goto out; 4083 } 4084 4085 /* if we passed all the tests above then the link is up and we no 4086 * longer need to check for link 4087 */ 4088 mac->get_link_status = false; 4089 4090 out: 4091 *link_up = !mac->get_link_status; 4092 return ret_val; 4093 } 4094 4095 static void 4096 ixgbe_dev_setup_link_alarm_handler(void *param) 4097 { 4098 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4099 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4100 struct ixgbe_interrupt *intr = 4101 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4102 u32 speed; 4103 bool autoneg = false; 4104 4105 speed = hw->phy.autoneg_advertised; 4106 if (!speed) 4107 ixgbe_get_link_capabilities(hw, &speed, &autoneg); 4108 4109 ixgbe_setup_link(hw, speed, true); 4110 4111 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 4112 } 4113 4114 /* return 0 means link status changed, -1 means not changed */ 4115 int 4116 ixgbe_dev_link_update_share(struct rte_eth_dev *dev, 4117 int wait_to_complete, int vf) 4118 { 4119 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4120 struct rte_eth_link link; 4121 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4122 struct ixgbe_interrupt *intr = 4123 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4124 int link_up; 4125 int diag; 4126 int wait = 1; 4127 u32 esdp_reg; 4128 4129 memset(&link, 0, sizeof(link)); 4130 link.link_status = ETH_LINK_DOWN; 4131 link.link_speed = ETH_SPEED_NUM_NONE; 4132 link.link_duplex = ETH_LINK_HALF_DUPLEX; 4133 link.link_autoneg = ETH_LINK_AUTONEG; 4134 4135 hw->mac.get_link_status = true; 4136 4137 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) 4138 return rte_eth_linkstatus_set(dev, &link); 4139 4140 /* check if it needs to wait to complete, if lsc interrupt is enabled */ 4141 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0) 4142 wait = 0; 4143 4144 if (vf) 4145 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait); 4146 else 4147 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait); 4148 4149 if (diag != 0) { 4150 link.link_speed = ETH_SPEED_NUM_100M; 4151 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4152 return rte_eth_linkstatus_set(dev, &link); 4153 } 4154 4155 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 4156 if ((esdp_reg & IXGBE_ESDP_SDP3)) 4157 link_up = 0; 4158 4159 if (link_up == 0) { 4160 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) { 4161 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 4162 rte_eal_alarm_set(10, 4163 ixgbe_dev_setup_link_alarm_handler, dev); 4164 } 4165 return rte_eth_linkstatus_set(dev, &link); 4166 } 4167 4168 link.link_status = ETH_LINK_UP; 4169 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4170 4171 switch (link_speed) { 4172 default: 4173 case IXGBE_LINK_SPEED_UNKNOWN: 4174 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 4175 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 4176 link.link_speed = ETH_SPEED_NUM_10M; 4177 else 4178 link.link_speed = ETH_SPEED_NUM_100M; 4179 break; 4180 4181 case IXGBE_LINK_SPEED_100_FULL: 4182 link.link_speed = ETH_SPEED_NUM_100M; 4183 break; 4184 4185 case IXGBE_LINK_SPEED_1GB_FULL: 4186 link.link_speed = ETH_SPEED_NUM_1G; 4187 break; 4188 4189 case IXGBE_LINK_SPEED_2_5GB_FULL: 4190 link.link_speed = ETH_SPEED_NUM_2_5G; 4191 break; 4192 4193 case IXGBE_LINK_SPEED_5GB_FULL: 4194 link.link_speed = ETH_SPEED_NUM_5G; 4195 break; 4196 4197 case IXGBE_LINK_SPEED_10GB_FULL: 4198 link.link_speed = ETH_SPEED_NUM_10G; 4199 break; 4200 } 4201 4202 return rte_eth_linkstatus_set(dev, &link); 4203 } 4204 4205 static int 4206 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4207 { 4208 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0); 4209 } 4210 4211 static int 4212 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4213 { 4214 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1); 4215 } 4216 4217 static int 4218 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 4219 { 4220 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4221 uint32_t fctrl; 4222 4223 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4224 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4225 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4226 4227 return 0; 4228 } 4229 4230 static int 4231 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 4232 { 4233 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4234 uint32_t fctrl; 4235 4236 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4237 fctrl &= (~IXGBE_FCTRL_UPE); 4238 if (dev->data->all_multicast == 1) 4239 fctrl |= IXGBE_FCTRL_MPE; 4240 else 4241 fctrl &= (~IXGBE_FCTRL_MPE); 4242 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4243 4244 return 0; 4245 } 4246 4247 static int 4248 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 4249 { 4250 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4251 uint32_t fctrl; 4252 4253 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4254 fctrl |= IXGBE_FCTRL_MPE; 4255 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4256 4257 return 0; 4258 } 4259 4260 static int 4261 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 4262 { 4263 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4264 uint32_t fctrl; 4265 4266 if (dev->data->promiscuous == 1) 4267 return 0; /* must remain in all_multicast mode */ 4268 4269 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4270 fctrl &= (~IXGBE_FCTRL_MPE); 4271 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4272 4273 return 0; 4274 } 4275 4276 /** 4277 * It clears the interrupt causes and enables the interrupt. 4278 * It will be called once only during nic initialized. 4279 * 4280 * @param dev 4281 * Pointer to struct rte_eth_dev. 4282 * @param on 4283 * Enable or Disable. 4284 * 4285 * @return 4286 * - On success, zero. 4287 * - On failure, a negative value. 4288 */ 4289 static int 4290 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 4291 { 4292 struct ixgbe_interrupt *intr = 4293 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4294 4295 ixgbe_dev_link_status_print(dev); 4296 if (on) 4297 intr->mask |= IXGBE_EICR_LSC; 4298 else 4299 intr->mask &= ~IXGBE_EICR_LSC; 4300 4301 return 0; 4302 } 4303 4304 /** 4305 * It clears the interrupt causes and enables the interrupt. 4306 * It will be called once only during nic initialized. 4307 * 4308 * @param dev 4309 * Pointer to struct rte_eth_dev. 4310 * 4311 * @return 4312 * - On success, zero. 4313 * - On failure, a negative value. 4314 */ 4315 static int 4316 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev) 4317 { 4318 struct ixgbe_interrupt *intr = 4319 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4320 4321 intr->mask |= IXGBE_EICR_RTX_QUEUE; 4322 4323 return 0; 4324 } 4325 4326 /** 4327 * It clears the interrupt causes and enables the interrupt. 4328 * It will be called once only during nic initialized. 4329 * 4330 * @param dev 4331 * Pointer to struct rte_eth_dev. 4332 * 4333 * @return 4334 * - On success, zero. 4335 * - On failure, a negative value. 4336 */ 4337 static int 4338 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev) 4339 { 4340 struct ixgbe_interrupt *intr = 4341 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4342 4343 intr->mask |= IXGBE_EICR_LINKSEC; 4344 4345 return 0; 4346 } 4347 4348 /* 4349 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update. 4350 * 4351 * @param dev 4352 * Pointer to struct rte_eth_dev. 4353 * 4354 * @return 4355 * - On success, zero. 4356 * - On failure, a negative value. 4357 */ 4358 static int 4359 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev) 4360 { 4361 uint32_t eicr; 4362 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4363 struct ixgbe_interrupt *intr = 4364 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4365 4366 /* clear all cause mask */ 4367 ixgbe_disable_intr(hw); 4368 4369 /* read-on-clear nic registers here */ 4370 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4371 PMD_DRV_LOG(DEBUG, "eicr %x", eicr); 4372 4373 intr->flags = 0; 4374 4375 /* set flag for async link update */ 4376 if (eicr & IXGBE_EICR_LSC) 4377 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 4378 4379 if (eicr & IXGBE_EICR_MAILBOX) 4380 intr->flags |= IXGBE_FLAG_MAILBOX; 4381 4382 if (eicr & IXGBE_EICR_LINKSEC) 4383 intr->flags |= IXGBE_FLAG_MACSEC; 4384 4385 if (hw->mac.type == ixgbe_mac_X550EM_x && 4386 hw->phy.type == ixgbe_phy_x550em_ext_t && 4387 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x)) 4388 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT; 4389 4390 return 0; 4391 } 4392 4393 /** 4394 * It gets and then prints the link status. 4395 * 4396 * @param dev 4397 * Pointer to struct rte_eth_dev. 4398 * 4399 * @return 4400 * - On success, zero. 4401 * - On failure, a negative value. 4402 */ 4403 static void 4404 ixgbe_dev_link_status_print(struct rte_eth_dev *dev) 4405 { 4406 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4407 struct rte_eth_link link; 4408 4409 rte_eth_linkstatus_get(dev, &link); 4410 4411 if (link.link_status) { 4412 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", 4413 (int)(dev->data->port_id), 4414 (unsigned)link.link_speed, 4415 link.link_duplex == ETH_LINK_FULL_DUPLEX ? 4416 "full-duplex" : "half-duplex"); 4417 } else { 4418 PMD_INIT_LOG(INFO, " Port %d: Link Down", 4419 (int)(dev->data->port_id)); 4420 } 4421 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 4422 pci_dev->addr.domain, 4423 pci_dev->addr.bus, 4424 pci_dev->addr.devid, 4425 pci_dev->addr.function); 4426 } 4427 4428 /* 4429 * It executes link_update after knowing an interrupt occurred. 4430 * 4431 * @param dev 4432 * Pointer to struct rte_eth_dev. 4433 * 4434 * @return 4435 * - On success, zero. 4436 * - On failure, a negative value. 4437 */ 4438 static int 4439 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev) 4440 { 4441 struct ixgbe_interrupt *intr = 4442 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4443 int64_t timeout; 4444 struct ixgbe_hw *hw = 4445 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4446 4447 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags); 4448 4449 if (intr->flags & IXGBE_FLAG_MAILBOX) { 4450 ixgbe_pf_mbx_process(dev); 4451 intr->flags &= ~IXGBE_FLAG_MAILBOX; 4452 } 4453 4454 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4455 ixgbe_handle_lasi(hw); 4456 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4457 } 4458 4459 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4460 struct rte_eth_link link; 4461 4462 /* get the link status before link update, for predicting later */ 4463 rte_eth_linkstatus_get(dev, &link); 4464 4465 ixgbe_dev_link_update(dev, 0); 4466 4467 /* likely to up */ 4468 if (!link.link_status) 4469 /* handle it 1 sec later, wait it being stable */ 4470 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT; 4471 /* likely to down */ 4472 else 4473 /* handle it 4 sec later, wait it being stable */ 4474 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT; 4475 4476 ixgbe_dev_link_status_print(dev); 4477 if (rte_eal_alarm_set(timeout * 1000, 4478 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0) 4479 PMD_DRV_LOG(ERR, "Error setting alarm"); 4480 else { 4481 /* remember original mask */ 4482 intr->mask_original = intr->mask; 4483 /* only disable lsc interrupt */ 4484 intr->mask &= ~IXGBE_EIMS_LSC; 4485 } 4486 } 4487 4488 PMD_DRV_LOG(DEBUG, "enable intr immediately"); 4489 ixgbe_enable_intr(dev); 4490 4491 return 0; 4492 } 4493 4494 /** 4495 * Interrupt handler which shall be registered for alarm callback for delayed 4496 * handling specific interrupt to wait for the stable nic state. As the 4497 * NIC interrupt state is not stable for ixgbe after link is just down, 4498 * it needs to wait 4 seconds to get the stable status. 4499 * 4500 * @param handle 4501 * Pointer to interrupt handle. 4502 * @param param 4503 * The address of parameter (struct rte_eth_dev *) regsitered before. 4504 * 4505 * @return 4506 * void 4507 */ 4508 static void 4509 ixgbe_dev_interrupt_delayed_handler(void *param) 4510 { 4511 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4512 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4513 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4514 struct ixgbe_interrupt *intr = 4515 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4516 struct ixgbe_hw *hw = 4517 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4518 uint32_t eicr; 4519 4520 ixgbe_disable_intr(hw); 4521 4522 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4523 if (eicr & IXGBE_EICR_MAILBOX) 4524 ixgbe_pf_mbx_process(dev); 4525 4526 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4527 ixgbe_handle_lasi(hw); 4528 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4529 } 4530 4531 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4532 ixgbe_dev_link_update(dev, 0); 4533 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 4534 ixgbe_dev_link_status_print(dev); 4535 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, 4536 NULL); 4537 } 4538 4539 if (intr->flags & IXGBE_FLAG_MACSEC) { 4540 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, 4541 NULL); 4542 intr->flags &= ~IXGBE_FLAG_MACSEC; 4543 } 4544 4545 /* restore original mask */ 4546 intr->mask = intr->mask_original; 4547 intr->mask_original = 0; 4548 4549 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr); 4550 ixgbe_enable_intr(dev); 4551 rte_intr_ack(intr_handle); 4552 } 4553 4554 /** 4555 * Interrupt handler triggered by NIC for handling 4556 * specific interrupt. 4557 * 4558 * @param handle 4559 * Pointer to interrupt handle. 4560 * @param param 4561 * The address of parameter (struct rte_eth_dev *) regsitered before. 4562 * 4563 * @return 4564 * void 4565 */ 4566 static void 4567 ixgbe_dev_interrupt_handler(void *param) 4568 { 4569 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4570 4571 ixgbe_dev_interrupt_get_status(dev); 4572 ixgbe_dev_interrupt_action(dev); 4573 } 4574 4575 static int 4576 ixgbe_dev_led_on(struct rte_eth_dev *dev) 4577 { 4578 struct ixgbe_hw *hw; 4579 4580 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4581 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4582 } 4583 4584 static int 4585 ixgbe_dev_led_off(struct rte_eth_dev *dev) 4586 { 4587 struct ixgbe_hw *hw; 4588 4589 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4590 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4591 } 4592 4593 static int 4594 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4595 { 4596 struct ixgbe_hw *hw; 4597 uint32_t mflcn_reg; 4598 uint32_t fccfg_reg; 4599 int rx_pause; 4600 int tx_pause; 4601 4602 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4603 4604 fc_conf->pause_time = hw->fc.pause_time; 4605 fc_conf->high_water = hw->fc.high_water[0]; 4606 fc_conf->low_water = hw->fc.low_water[0]; 4607 fc_conf->send_xon = hw->fc.send_xon; 4608 fc_conf->autoneg = !hw->fc.disable_fc_autoneg; 4609 4610 /* 4611 * Return rx_pause status according to actual setting of 4612 * MFLCN register. 4613 */ 4614 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4615 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE)) 4616 rx_pause = 1; 4617 else 4618 rx_pause = 0; 4619 4620 /* 4621 * Return tx_pause status according to actual setting of 4622 * FCCFG register. 4623 */ 4624 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4625 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY)) 4626 tx_pause = 1; 4627 else 4628 tx_pause = 0; 4629 4630 if (rx_pause && tx_pause) 4631 fc_conf->mode = RTE_FC_FULL; 4632 else if (rx_pause) 4633 fc_conf->mode = RTE_FC_RX_PAUSE; 4634 else if (tx_pause) 4635 fc_conf->mode = RTE_FC_TX_PAUSE; 4636 else 4637 fc_conf->mode = RTE_FC_NONE; 4638 4639 return 0; 4640 } 4641 4642 static int 4643 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4644 { 4645 struct ixgbe_hw *hw; 4646 int err; 4647 uint32_t rx_buf_size; 4648 uint32_t max_high_water; 4649 uint32_t mflcn; 4650 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4651 ixgbe_fc_none, 4652 ixgbe_fc_rx_pause, 4653 ixgbe_fc_tx_pause, 4654 ixgbe_fc_full 4655 }; 4656 4657 PMD_INIT_FUNC_TRACE(); 4658 4659 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4660 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)); 4661 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4662 4663 /* 4664 * At least reserve one Ethernet frame for watermark 4665 * high_water/low_water in kilo bytes for ixgbe 4666 */ 4667 max_high_water = (rx_buf_size - 4668 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4669 if ((fc_conf->high_water > max_high_water) || 4670 (fc_conf->high_water < fc_conf->low_water)) { 4671 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4672 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4673 return -EINVAL; 4674 } 4675 4676 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode]; 4677 hw->fc.pause_time = fc_conf->pause_time; 4678 hw->fc.high_water[0] = fc_conf->high_water; 4679 hw->fc.low_water[0] = fc_conf->low_water; 4680 hw->fc.send_xon = fc_conf->send_xon; 4681 hw->fc.disable_fc_autoneg = !fc_conf->autoneg; 4682 4683 err = ixgbe_fc_enable(hw); 4684 4685 /* Not negotiated is not an error case */ 4686 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) { 4687 4688 /* check if we want to forward MAC frames - driver doesn't have native 4689 * capability to do that, so we'll write the registers ourselves */ 4690 4691 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4692 4693 /* set or clear MFLCN.PMCF bit depending on configuration */ 4694 if (fc_conf->mac_ctrl_frame_fwd != 0) 4695 mflcn |= IXGBE_MFLCN_PMCF; 4696 else 4697 mflcn &= ~IXGBE_MFLCN_PMCF; 4698 4699 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn); 4700 IXGBE_WRITE_FLUSH(hw); 4701 4702 return 0; 4703 } 4704 4705 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err); 4706 return -EIO; 4707 } 4708 4709 /** 4710 * ixgbe_pfc_enable_generic - Enable flow control 4711 * @hw: pointer to hardware structure 4712 * @tc_num: traffic class number 4713 * Enable flow control according to the current settings. 4714 */ 4715 static int 4716 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num) 4717 { 4718 int ret_val = 0; 4719 uint32_t mflcn_reg, fccfg_reg; 4720 uint32_t reg; 4721 uint32_t fcrtl, fcrth; 4722 uint8_t i; 4723 uint8_t nb_rx_en; 4724 4725 /* Validate the water mark configuration */ 4726 if (!hw->fc.pause_time) { 4727 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4728 goto out; 4729 } 4730 4731 /* Low water mark of zero causes XOFF floods */ 4732 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 4733 /* High/Low water can not be 0 */ 4734 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) { 4735 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4736 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4737 goto out; 4738 } 4739 4740 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) { 4741 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4742 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4743 goto out; 4744 } 4745 } 4746 /* Negotiate the fc mode to use */ 4747 ixgbe_fc_autoneg(hw); 4748 4749 /* Disable any previous flow control settings */ 4750 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4751 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE); 4752 4753 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4754 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 4755 4756 switch (hw->fc.current_mode) { 4757 case ixgbe_fc_none: 4758 /* 4759 * If the count of enabled RX Priority Flow control >1, 4760 * and the TX pause can not be disabled 4761 */ 4762 nb_rx_en = 0; 4763 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4764 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4765 if (reg & IXGBE_FCRTH_FCEN) 4766 nb_rx_en++; 4767 } 4768 if (nb_rx_en > 1) 4769 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4770 break; 4771 case ixgbe_fc_rx_pause: 4772 /* 4773 * Rx Flow control is enabled and Tx Flow control is 4774 * disabled by software override. Since there really 4775 * isn't a way to advertise that we are capable of RX 4776 * Pause ONLY, we will advertise that we support both 4777 * symmetric and asymmetric Rx PAUSE. Later, we will 4778 * disable the adapter's ability to send PAUSE frames. 4779 */ 4780 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4781 /* 4782 * If the count of enabled RX Priority Flow control >1, 4783 * and the TX pause can not be disabled 4784 */ 4785 nb_rx_en = 0; 4786 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4787 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4788 if (reg & IXGBE_FCRTH_FCEN) 4789 nb_rx_en++; 4790 } 4791 if (nb_rx_en > 1) 4792 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4793 break; 4794 case ixgbe_fc_tx_pause: 4795 /* 4796 * Tx Flow control is enabled, and Rx Flow control is 4797 * disabled by software override. 4798 */ 4799 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4800 break; 4801 case ixgbe_fc_full: 4802 /* Flow control (both Rx and Tx) is enabled by SW override. */ 4803 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4804 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4805 break; 4806 default: 4807 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly"); 4808 ret_val = IXGBE_ERR_CONFIG; 4809 goto out; 4810 } 4811 4812 /* Set 802.3x based flow control settings. */ 4813 mflcn_reg |= IXGBE_MFLCN_DPF; 4814 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 4815 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 4816 4817 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 4818 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 4819 hw->fc.high_water[tc_num]) { 4820 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE; 4821 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl); 4822 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN; 4823 } else { 4824 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0); 4825 /* 4826 * In order to prevent Tx hangs when the internal Tx 4827 * switch is enabled we must set the high water mark 4828 * to the maximum FCRTH value. This allows the Tx 4829 * switch to function even under heavy Rx workloads. 4830 */ 4831 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32; 4832 } 4833 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth); 4834 4835 /* Configure pause time (2 TCs per register) */ 4836 reg = hw->fc.pause_time * 0x00010001; 4837 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 4838 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 4839 4840 /* Configure flow control refresh threshold value */ 4841 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 4842 4843 out: 4844 return ret_val; 4845 } 4846 4847 static int 4848 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num) 4849 { 4850 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4851 int32_t ret_val = IXGBE_NOT_IMPLEMENTED; 4852 4853 if (hw->mac.type != ixgbe_mac_82598EB) { 4854 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num); 4855 } 4856 return ret_val; 4857 } 4858 4859 static int 4860 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf) 4861 { 4862 int err; 4863 uint32_t rx_buf_size; 4864 uint32_t max_high_water; 4865 uint8_t tc_num; 4866 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 4867 struct ixgbe_hw *hw = 4868 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4869 struct ixgbe_dcb_config *dcb_config = 4870 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 4871 4872 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4873 ixgbe_fc_none, 4874 ixgbe_fc_rx_pause, 4875 ixgbe_fc_tx_pause, 4876 ixgbe_fc_full 4877 }; 4878 4879 PMD_INIT_FUNC_TRACE(); 4880 4881 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map); 4882 tc_num = map[pfc_conf->priority]; 4883 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)); 4884 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4885 /* 4886 * At least reserve one Ethernet frame for watermark 4887 * high_water/low_water in kilo bytes for ixgbe 4888 */ 4889 max_high_water = (rx_buf_size - 4890 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4891 if ((pfc_conf->fc.high_water > max_high_water) || 4892 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) { 4893 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4894 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4895 return -EINVAL; 4896 } 4897 4898 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode]; 4899 hw->fc.pause_time = pfc_conf->fc.pause_time; 4900 hw->fc.send_xon = pfc_conf->fc.send_xon; 4901 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water; 4902 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; 4903 4904 err = ixgbe_dcb_pfc_enable(dev, tc_num); 4905 4906 /* Not negotiated is not an error case */ 4907 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) 4908 return 0; 4909 4910 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err); 4911 return -EIO; 4912 } 4913 4914 static int 4915 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 4916 struct rte_eth_rss_reta_entry64 *reta_conf, 4917 uint16_t reta_size) 4918 { 4919 uint16_t i, sp_reta_size; 4920 uint8_t j, mask; 4921 uint32_t reta, r; 4922 uint16_t idx, shift; 4923 struct ixgbe_adapter *adapter = dev->data->dev_private; 4924 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4925 uint32_t reta_reg; 4926 4927 PMD_INIT_FUNC_TRACE(); 4928 4929 if (!ixgbe_rss_update_sp(hw->mac.type)) { 4930 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " 4931 "NIC."); 4932 return -ENOTSUP; 4933 } 4934 4935 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 4936 if (reta_size != sp_reta_size) { 4937 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 4938 "(%d) doesn't match the number hardware can supported " 4939 "(%d)", reta_size, sp_reta_size); 4940 return -EINVAL; 4941 } 4942 4943 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 4944 idx = i / RTE_RETA_GROUP_SIZE; 4945 shift = i % RTE_RETA_GROUP_SIZE; 4946 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 4947 IXGBE_4_BIT_MASK); 4948 if (!mask) 4949 continue; 4950 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 4951 if (mask == IXGBE_4_BIT_MASK) 4952 r = 0; 4953 else 4954 r = IXGBE_READ_REG(hw, reta_reg); 4955 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) { 4956 if (mask & (0x1 << j)) 4957 reta |= reta_conf[idx].reta[shift + j] << 4958 (CHAR_BIT * j); 4959 else 4960 reta |= r & (IXGBE_8_BIT_MASK << 4961 (CHAR_BIT * j)); 4962 } 4963 IXGBE_WRITE_REG(hw, reta_reg, reta); 4964 } 4965 adapter->rss_reta_updated = 1; 4966 4967 return 0; 4968 } 4969 4970 static int 4971 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 4972 struct rte_eth_rss_reta_entry64 *reta_conf, 4973 uint16_t reta_size) 4974 { 4975 uint16_t i, sp_reta_size; 4976 uint8_t j, mask; 4977 uint32_t reta; 4978 uint16_t idx, shift; 4979 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4980 uint32_t reta_reg; 4981 4982 PMD_INIT_FUNC_TRACE(); 4983 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 4984 if (reta_size != sp_reta_size) { 4985 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 4986 "(%d) doesn't match the number hardware can supported " 4987 "(%d)", reta_size, sp_reta_size); 4988 return -EINVAL; 4989 } 4990 4991 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 4992 idx = i / RTE_RETA_GROUP_SIZE; 4993 shift = i % RTE_RETA_GROUP_SIZE; 4994 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 4995 IXGBE_4_BIT_MASK); 4996 if (!mask) 4997 continue; 4998 4999 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 5000 reta = IXGBE_READ_REG(hw, reta_reg); 5001 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) { 5002 if (mask & (0x1 << j)) 5003 reta_conf[idx].reta[shift + j] = 5004 ((reta >> (CHAR_BIT * j)) & 5005 IXGBE_8_BIT_MASK); 5006 } 5007 } 5008 5009 return 0; 5010 } 5011 5012 static int 5013 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 5014 uint32_t index, uint32_t pool) 5015 { 5016 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5017 uint32_t enable_addr = 1; 5018 5019 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes, 5020 pool, enable_addr); 5021 } 5022 5023 static void 5024 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) 5025 { 5026 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5027 5028 ixgbe_clear_rar(hw, index); 5029 } 5030 5031 static int 5032 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 5033 { 5034 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5035 5036 ixgbe_remove_rar(dev, 0); 5037 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs); 5038 5039 return 0; 5040 } 5041 5042 static bool 5043 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 5044 { 5045 if (strcmp(dev->device->driver->name, drv->driver.name)) 5046 return false; 5047 5048 return true; 5049 } 5050 5051 bool 5052 is_ixgbe_supported(struct rte_eth_dev *dev) 5053 { 5054 return is_device_supported(dev, &rte_ixgbe_pmd); 5055 } 5056 5057 static int 5058 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 5059 { 5060 uint32_t hlreg0; 5061 uint32_t maxfrs; 5062 struct ixgbe_hw *hw; 5063 struct rte_eth_dev_info dev_info; 5064 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD; 5065 struct rte_eth_dev_data *dev_data = dev->data; 5066 int ret; 5067 5068 ret = ixgbe_dev_info_get(dev, &dev_info); 5069 if (ret != 0) 5070 return ret; 5071 5072 /* check that mtu is within the allowed range */ 5073 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) 5074 return -EINVAL; 5075 5076 /* If device is started, refuse mtu that requires the support of 5077 * scattered packets when this feature has not been enabled before. 5078 */ 5079 if (dev_data->dev_started && !dev_data->scattered_rx && 5080 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE > 5081 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 5082 PMD_INIT_LOG(ERR, "Stop port first."); 5083 return -EINVAL; 5084 } 5085 5086 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5087 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 5088 5089 /* switch to jumbo mode if needed */ 5090 if (frame_size > RTE_ETHER_MAX_LEN) { 5091 dev->data->dev_conf.rxmode.offloads |= 5092 DEV_RX_OFFLOAD_JUMBO_FRAME; 5093 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 5094 } else { 5095 dev->data->dev_conf.rxmode.offloads &= 5096 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 5097 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; 5098 } 5099 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 5100 5101 /* update max frame size */ 5102 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 5103 5104 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS); 5105 maxfrs &= 0x0000FFFF; 5106 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16); 5107 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs); 5108 5109 return 0; 5110 } 5111 5112 /* 5113 * Virtual Function operations 5114 */ 5115 static void 5116 ixgbevf_intr_disable(struct rte_eth_dev *dev) 5117 { 5118 struct ixgbe_interrupt *intr = 5119 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5120 struct ixgbe_hw *hw = 5121 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5122 5123 PMD_INIT_FUNC_TRACE(); 5124 5125 /* Clear interrupt mask to stop from interrupts being generated */ 5126 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK); 5127 5128 IXGBE_WRITE_FLUSH(hw); 5129 5130 /* Clear mask value. */ 5131 intr->mask = 0; 5132 } 5133 5134 static void 5135 ixgbevf_intr_enable(struct rte_eth_dev *dev) 5136 { 5137 struct ixgbe_interrupt *intr = 5138 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5139 struct ixgbe_hw *hw = 5140 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5141 5142 PMD_INIT_FUNC_TRACE(); 5143 5144 /* VF enable interrupt autoclean */ 5145 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK); 5146 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK); 5147 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK); 5148 5149 IXGBE_WRITE_FLUSH(hw); 5150 5151 /* Save IXGBE_VTEIMS value to mask. */ 5152 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK; 5153 } 5154 5155 static int 5156 ixgbevf_dev_configure(struct rte_eth_dev *dev) 5157 { 5158 struct rte_eth_conf *conf = &dev->data->dev_conf; 5159 struct ixgbe_adapter *adapter = dev->data->dev_private; 5160 5161 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d", 5162 dev->data->port_id); 5163 5164 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 5165 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 5166 5167 /* 5168 * VF has no ability to enable/disable HW CRC 5169 * Keep the persistent behavior the same as Host PF 5170 */ 5171 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC 5172 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) { 5173 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip"); 5174 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC; 5175 } 5176 #else 5177 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) { 5178 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip"); 5179 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC; 5180 } 5181 #endif 5182 5183 /* 5184 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 5185 * allocation or vector Rx preconditions we will reset it. 5186 */ 5187 adapter->rx_bulk_alloc_allowed = true; 5188 adapter->rx_vec_allowed = true; 5189 5190 return 0; 5191 } 5192 5193 static int 5194 ixgbevf_dev_start(struct rte_eth_dev *dev) 5195 { 5196 struct ixgbe_hw *hw = 5197 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5198 uint32_t intr_vector = 0; 5199 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5200 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5201 5202 int err, mask = 0; 5203 5204 PMD_INIT_FUNC_TRACE(); 5205 5206 /* Stop the link setup handler before resetting the HW. */ 5207 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 5208 5209 err = hw->mac.ops.reset_hw(hw); 5210 if (err) { 5211 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err); 5212 return err; 5213 } 5214 hw->mac.get_link_status = true; 5215 5216 /* negotiate mailbox API version to use with the PF. */ 5217 ixgbevf_negotiate_api(hw); 5218 5219 ixgbevf_dev_tx_init(dev); 5220 5221 /* This can fail when allocating mbufs for descriptor rings */ 5222 err = ixgbevf_dev_rx_init(dev); 5223 if (err) { 5224 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err); 5225 ixgbe_dev_clear_queues(dev); 5226 return err; 5227 } 5228 5229 /* Set vfta */ 5230 ixgbevf_set_vfta_all(dev, 1); 5231 5232 /* Set HW strip */ 5233 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 5234 ETH_VLAN_EXTEND_MASK; 5235 err = ixgbevf_vlan_offload_config(dev, mask); 5236 if (err) { 5237 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err); 5238 ixgbe_dev_clear_queues(dev); 5239 return err; 5240 } 5241 5242 ixgbevf_dev_rxtx_start(dev); 5243 5244 /* check and configure queue intr-vector mapping */ 5245 if (rte_intr_cap_multiple(intr_handle) && 5246 dev->data->dev_conf.intr_conf.rxq) { 5247 /* According to datasheet, only vector 0/1/2 can be used, 5248 * now only one vector is used for Rx queue 5249 */ 5250 intr_vector = 1; 5251 if (rte_intr_efd_enable(intr_handle, intr_vector)) 5252 return -1; 5253 } 5254 5255 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 5256 intr_handle->intr_vec = 5257 rte_zmalloc("intr_vec", 5258 dev->data->nb_rx_queues * sizeof(int), 0); 5259 if (intr_handle->intr_vec == NULL) { 5260 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 5261 " intr_vec", dev->data->nb_rx_queues); 5262 return -ENOMEM; 5263 } 5264 } 5265 ixgbevf_configure_msix(dev); 5266 5267 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt 5268 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ). 5269 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( ) 5270 * is not cleared, it will fail when following rte_intr_enable( ) tries 5271 * to map Rx queue interrupt to other VFIO vectors. 5272 * So clear uio/vfio intr/evevnfd first to avoid failure. 5273 */ 5274 rte_intr_disable(intr_handle); 5275 5276 rte_intr_enable(intr_handle); 5277 5278 /* Re-enable interrupt for VF */ 5279 ixgbevf_intr_enable(dev); 5280 5281 /* 5282 * Update link status right before return, because it may 5283 * start link configuration process in a separate thread. 5284 */ 5285 ixgbevf_dev_link_update(dev, 0); 5286 5287 hw->adapter_stopped = false; 5288 5289 return 0; 5290 } 5291 5292 static void 5293 ixgbevf_dev_stop(struct rte_eth_dev *dev) 5294 { 5295 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5296 struct ixgbe_adapter *adapter = dev->data->dev_private; 5297 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5298 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5299 5300 if (hw->adapter_stopped) 5301 return; 5302 5303 PMD_INIT_FUNC_TRACE(); 5304 5305 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 5306 5307 ixgbevf_intr_disable(dev); 5308 5309 hw->adapter_stopped = 1; 5310 ixgbe_stop_adapter(hw); 5311 5312 /* 5313 * Clear what we set, but we still keep shadow_vfta to 5314 * restore after device starts 5315 */ 5316 ixgbevf_set_vfta_all(dev, 0); 5317 5318 /* Clear stored conf */ 5319 dev->data->scattered_rx = 0; 5320 5321 ixgbe_dev_clear_queues(dev); 5322 5323 /* Clean datapath event and queue/vec mapping */ 5324 rte_intr_efd_disable(intr_handle); 5325 if (intr_handle->intr_vec != NULL) { 5326 rte_free(intr_handle->intr_vec); 5327 intr_handle->intr_vec = NULL; 5328 } 5329 5330 adapter->rss_reta_updated = 0; 5331 } 5332 5333 static void 5334 ixgbevf_dev_close(struct rte_eth_dev *dev) 5335 { 5336 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5337 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5338 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5339 5340 PMD_INIT_FUNC_TRACE(); 5341 5342 ixgbe_reset_hw(hw); 5343 5344 ixgbevf_dev_stop(dev); 5345 5346 ixgbe_dev_free_queues(dev); 5347 5348 /** 5349 * Remove the VF MAC address ro ensure 5350 * that the VF traffic goes to the PF 5351 * after stop, close and detach of the VF 5352 **/ 5353 ixgbevf_remove_mac_addr(dev, 0); 5354 5355 dev->dev_ops = NULL; 5356 dev->rx_pkt_burst = NULL; 5357 dev->tx_pkt_burst = NULL; 5358 5359 rte_intr_disable(intr_handle); 5360 rte_intr_callback_unregister(intr_handle, 5361 ixgbevf_dev_interrupt_handler, dev); 5362 } 5363 5364 /* 5365 * Reset VF device 5366 */ 5367 static int 5368 ixgbevf_dev_reset(struct rte_eth_dev *dev) 5369 { 5370 int ret; 5371 5372 ret = eth_ixgbevf_dev_uninit(dev); 5373 if (ret) 5374 return ret; 5375 5376 ret = eth_ixgbevf_dev_init(dev); 5377 5378 return ret; 5379 } 5380 5381 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) 5382 { 5383 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5384 struct ixgbe_vfta *shadow_vfta = 5385 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5386 int i = 0, j = 0, vfta = 0, mask = 1; 5387 5388 for (i = 0; i < IXGBE_VFTA_SIZE; i++) { 5389 vfta = shadow_vfta->vfta[i]; 5390 if (vfta) { 5391 mask = 1; 5392 for (j = 0; j < 32; j++) { 5393 if (vfta & mask) 5394 ixgbe_set_vfta(hw, (i<<5)+j, 0, 5395 on, false); 5396 mask <<= 1; 5397 } 5398 } 5399 } 5400 5401 } 5402 5403 static int 5404 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 5405 { 5406 struct ixgbe_hw *hw = 5407 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5408 struct ixgbe_vfta *shadow_vfta = 5409 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5410 uint32_t vid_idx = 0; 5411 uint32_t vid_bit = 0; 5412 int ret = 0; 5413 5414 PMD_INIT_FUNC_TRACE(); 5415 5416 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */ 5417 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false); 5418 if (ret) { 5419 PMD_INIT_LOG(ERR, "Unable to set VF vlan"); 5420 return ret; 5421 } 5422 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 5423 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 5424 5425 /* Save what we set and retore it after device reset */ 5426 if (on) 5427 shadow_vfta->vfta[vid_idx] |= vid_bit; 5428 else 5429 shadow_vfta->vfta[vid_idx] &= ~vid_bit; 5430 5431 return 0; 5432 } 5433 5434 static void 5435 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 5436 { 5437 struct ixgbe_hw *hw = 5438 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5439 uint32_t ctrl; 5440 5441 PMD_INIT_FUNC_TRACE(); 5442 5443 if (queue >= hw->mac.max_rx_queues) 5444 return; 5445 5446 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 5447 if (on) 5448 ctrl |= IXGBE_RXDCTL_VME; 5449 else 5450 ctrl &= ~IXGBE_RXDCTL_VME; 5451 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 5452 5453 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on); 5454 } 5455 5456 static int 5457 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask) 5458 { 5459 struct ixgbe_rx_queue *rxq; 5460 uint16_t i; 5461 int on = 0; 5462 5463 /* VF function only support hw strip feature, others are not support */ 5464 if (mask & ETH_VLAN_STRIP_MASK) { 5465 for (i = 0; i < dev->data->nb_rx_queues; i++) { 5466 rxq = dev->data->rx_queues[i]; 5467 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP); 5468 ixgbevf_vlan_strip_queue_set(dev, i, on); 5469 } 5470 } 5471 5472 return 0; 5473 } 5474 5475 static int 5476 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 5477 { 5478 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 5479 5480 ixgbevf_vlan_offload_config(dev, mask); 5481 5482 return 0; 5483 } 5484 5485 int 5486 ixgbe_vt_check(struct ixgbe_hw *hw) 5487 { 5488 uint32_t reg_val; 5489 5490 /* if Virtualization Technology is enabled */ 5491 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 5492 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) { 5493 PMD_INIT_LOG(ERR, "VT must be enabled for this setting"); 5494 return -1; 5495 } 5496 5497 return 0; 5498 } 5499 5500 static uint32_t 5501 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr) 5502 { 5503 uint32_t vector = 0; 5504 5505 switch (hw->mac.mc_filter_type) { 5506 case 0: /* use bits [47:36] of the address */ 5507 vector = ((uc_addr->addr_bytes[4] >> 4) | 5508 (((uint16_t)uc_addr->addr_bytes[5]) << 4)); 5509 break; 5510 case 1: /* use bits [46:35] of the address */ 5511 vector = ((uc_addr->addr_bytes[4] >> 3) | 5512 (((uint16_t)uc_addr->addr_bytes[5]) << 5)); 5513 break; 5514 case 2: /* use bits [45:34] of the address */ 5515 vector = ((uc_addr->addr_bytes[4] >> 2) | 5516 (((uint16_t)uc_addr->addr_bytes[5]) << 6)); 5517 break; 5518 case 3: /* use bits [43:32] of the address */ 5519 vector = ((uc_addr->addr_bytes[4]) | 5520 (((uint16_t)uc_addr->addr_bytes[5]) << 8)); 5521 break; 5522 default: /* Invalid mc_filter_type */ 5523 break; 5524 } 5525 5526 /* vector can only be 12-bits or boundary will be exceeded */ 5527 vector &= 0xFFF; 5528 return vector; 5529 } 5530 5531 static int 5532 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, 5533 struct rte_ether_addr *mac_addr, uint8_t on) 5534 { 5535 uint32_t vector; 5536 uint32_t uta_idx; 5537 uint32_t reg_val; 5538 uint32_t uta_shift; 5539 uint32_t rc; 5540 const uint32_t ixgbe_uta_idx_mask = 0x7F; 5541 const uint32_t ixgbe_uta_bit_shift = 5; 5542 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1; 5543 const uint32_t bit1 = 0x1; 5544 5545 struct ixgbe_hw *hw = 5546 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5547 struct ixgbe_uta_info *uta_info = 5548 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5549 5550 /* The UTA table only exists on 82599 hardware and newer */ 5551 if (hw->mac.type < ixgbe_mac_82599EB) 5552 return -ENOTSUP; 5553 5554 vector = ixgbe_uta_vector(hw, mac_addr); 5555 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask; 5556 uta_shift = vector & ixgbe_uta_bit_mask; 5557 5558 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0); 5559 if (rc == on) 5560 return 0; 5561 5562 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx)); 5563 if (on) { 5564 uta_info->uta_in_use++; 5565 reg_val |= (bit1 << uta_shift); 5566 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift); 5567 } else { 5568 uta_info->uta_in_use--; 5569 reg_val &= ~(bit1 << uta_shift); 5570 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift); 5571 } 5572 5573 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val); 5574 5575 if (uta_info->uta_in_use > 0) 5576 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 5577 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 5578 else 5579 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 5580 5581 return 0; 5582 } 5583 5584 static int 5585 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) 5586 { 5587 int i; 5588 struct ixgbe_hw *hw = 5589 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5590 struct ixgbe_uta_info *uta_info = 5591 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5592 5593 /* The UTA table only exists on 82599 hardware and newer */ 5594 if (hw->mac.type < ixgbe_mac_82599EB) 5595 return -ENOTSUP; 5596 5597 if (on) { 5598 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5599 uta_info->uta_shadow[i] = ~0; 5600 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); 5601 } 5602 } else { 5603 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5604 uta_info->uta_shadow[i] = 0; 5605 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 5606 } 5607 } 5608 return 0; 5609 5610 } 5611 5612 uint32_t 5613 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val) 5614 { 5615 uint32_t new_val = orig_val; 5616 5617 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG) 5618 new_val |= IXGBE_VMOLR_AUPE; 5619 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC) 5620 new_val |= IXGBE_VMOLR_ROMPE; 5621 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC) 5622 new_val |= IXGBE_VMOLR_ROPE; 5623 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST) 5624 new_val |= IXGBE_VMOLR_BAM; 5625 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST) 5626 new_val |= IXGBE_VMOLR_MPE; 5627 5628 return new_val; 5629 } 5630 5631 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */ 5632 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */ 5633 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */ 5634 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */ 5635 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \ 5636 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \ 5637 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN)) 5638 5639 static int 5640 ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 5641 struct rte_eth_mirror_conf *mirror_conf, 5642 uint8_t rule_id, uint8_t on) 5643 { 5644 uint32_t mr_ctl, vlvf; 5645 uint32_t mp_lsb = 0; 5646 uint32_t mv_msb = 0; 5647 uint32_t mv_lsb = 0; 5648 uint32_t mp_msb = 0; 5649 uint8_t i = 0; 5650 int reg_index = 0; 5651 uint64_t vlan_mask = 0; 5652 5653 const uint8_t pool_mask_offset = 32; 5654 const uint8_t vlan_mask_offset = 32; 5655 const uint8_t dst_pool_offset = 8; 5656 const uint8_t rule_mr_offset = 4; 5657 const uint8_t mirror_rule_mask = 0x0F; 5658 5659 struct ixgbe_mirror_info *mr_info = 5660 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5661 struct ixgbe_hw *hw = 5662 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5663 uint8_t mirror_type = 0; 5664 5665 if (ixgbe_vt_check(hw) < 0) 5666 return -ENOTSUP; 5667 5668 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5669 return -EINVAL; 5670 5671 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) { 5672 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.", 5673 mirror_conf->rule_type); 5674 return -EINVAL; 5675 } 5676 5677 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5678 mirror_type |= IXGBE_MRCTL_VLME; 5679 /* Check if vlan id is valid and find conresponding VLAN ID 5680 * index in VLVF 5681 */ 5682 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) { 5683 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) { 5684 /* search vlan id related pool vlan filter 5685 * index 5686 */ 5687 reg_index = ixgbe_find_vlvf_slot( 5688 hw, 5689 mirror_conf->vlan.vlan_id[i], 5690 false); 5691 if (reg_index < 0) 5692 return -EINVAL; 5693 vlvf = IXGBE_READ_REG(hw, 5694 IXGBE_VLVF(reg_index)); 5695 if ((vlvf & IXGBE_VLVF_VIEN) && 5696 ((vlvf & IXGBE_VLVF_VLANID_MASK) == 5697 mirror_conf->vlan.vlan_id[i])) 5698 vlan_mask |= (1ULL << reg_index); 5699 else 5700 return -EINVAL; 5701 } 5702 } 5703 5704 if (on) { 5705 mv_lsb = vlan_mask & 0xFFFFFFFF; 5706 mv_msb = vlan_mask >> vlan_mask_offset; 5707 5708 mr_info->mr_conf[rule_id].vlan.vlan_mask = 5709 mirror_conf->vlan.vlan_mask; 5710 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) { 5711 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) 5712 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 5713 mirror_conf->vlan.vlan_id[i]; 5714 } 5715 } else { 5716 mv_lsb = 0; 5717 mv_msb = 0; 5718 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0; 5719 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) 5720 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0; 5721 } 5722 } 5723 5724 /** 5725 * if enable pool mirror, write related pool mask register,if disable 5726 * pool mirror, clear PFMRVM register 5727 */ 5728 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5729 mirror_type |= IXGBE_MRCTL_VPME; 5730 if (on) { 5731 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF; 5732 mp_msb = mirror_conf->pool_mask >> pool_mask_offset; 5733 mr_info->mr_conf[rule_id].pool_mask = 5734 mirror_conf->pool_mask; 5735 5736 } else { 5737 mp_lsb = 0; 5738 mp_msb = 0; 5739 mr_info->mr_conf[rule_id].pool_mask = 0; 5740 } 5741 } 5742 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT) 5743 mirror_type |= IXGBE_MRCTL_UPME; 5744 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT) 5745 mirror_type |= IXGBE_MRCTL_DPME; 5746 5747 /* read mirror control register and recalculate it */ 5748 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id)); 5749 5750 if (on) { 5751 mr_ctl |= mirror_type; 5752 mr_ctl &= mirror_rule_mask; 5753 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset; 5754 } else { 5755 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask); 5756 } 5757 5758 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type; 5759 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool; 5760 5761 /* write mirrror control register */ 5762 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5763 5764 /* write pool mirrror control register */ 5765 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5766 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb); 5767 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), 5768 mp_msb); 5769 } 5770 /* write VLAN mirrror control register */ 5771 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5772 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb); 5773 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), 5774 mv_msb); 5775 } 5776 5777 return 0; 5778 } 5779 5780 static int 5781 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id) 5782 { 5783 int mr_ctl = 0; 5784 uint32_t lsb_val = 0; 5785 uint32_t msb_val = 0; 5786 const uint8_t rule_mr_offset = 4; 5787 5788 struct ixgbe_hw *hw = 5789 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5790 struct ixgbe_mirror_info *mr_info = 5791 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5792 5793 if (ixgbe_vt_check(hw) < 0) 5794 return -ENOTSUP; 5795 5796 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5797 return -EINVAL; 5798 5799 memset(&mr_info->mr_conf[rule_id], 0, 5800 sizeof(struct rte_eth_mirror_conf)); 5801 5802 /* clear PFVMCTL register */ 5803 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5804 5805 /* clear pool mask register */ 5806 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val); 5807 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val); 5808 5809 /* clear vlan mask register */ 5810 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val); 5811 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val); 5812 5813 return 0; 5814 } 5815 5816 static int 5817 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5818 { 5819 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5820 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5821 struct ixgbe_interrupt *intr = 5822 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5823 struct ixgbe_hw *hw = 5824 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5825 uint32_t vec = IXGBE_MISC_VEC_ID; 5826 5827 if (rte_intr_allow_others(intr_handle)) 5828 vec = IXGBE_RX_VEC_START; 5829 intr->mask |= (1 << vec); 5830 RTE_SET_USED(queue_id); 5831 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5832 5833 rte_intr_ack(intr_handle); 5834 5835 return 0; 5836 } 5837 5838 static int 5839 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5840 { 5841 struct ixgbe_interrupt *intr = 5842 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5843 struct ixgbe_hw *hw = 5844 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5845 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5846 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5847 uint32_t vec = IXGBE_MISC_VEC_ID; 5848 5849 if (rte_intr_allow_others(intr_handle)) 5850 vec = IXGBE_RX_VEC_START; 5851 intr->mask &= ~(1 << vec); 5852 RTE_SET_USED(queue_id); 5853 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5854 5855 return 0; 5856 } 5857 5858 static int 5859 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5860 { 5861 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5862 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5863 uint32_t mask; 5864 struct ixgbe_hw *hw = 5865 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5866 struct ixgbe_interrupt *intr = 5867 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5868 5869 if (queue_id < 16) { 5870 ixgbe_disable_intr(hw); 5871 intr->mask |= (1 << queue_id); 5872 ixgbe_enable_intr(dev); 5873 } else if (queue_id < 32) { 5874 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5875 mask &= (1 << queue_id); 5876 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5877 } else if (queue_id < 64) { 5878 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5879 mask &= (1 << (queue_id - 32)); 5880 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5881 } 5882 rte_intr_ack(intr_handle); 5883 5884 return 0; 5885 } 5886 5887 static int 5888 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5889 { 5890 uint32_t mask; 5891 struct ixgbe_hw *hw = 5892 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5893 struct ixgbe_interrupt *intr = 5894 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5895 5896 if (queue_id < 16) { 5897 ixgbe_disable_intr(hw); 5898 intr->mask &= ~(1 << queue_id); 5899 ixgbe_enable_intr(dev); 5900 } else if (queue_id < 32) { 5901 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5902 mask &= ~(1 << queue_id); 5903 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5904 } else if (queue_id < 64) { 5905 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5906 mask &= ~(1 << (queue_id - 32)); 5907 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5908 } 5909 5910 return 0; 5911 } 5912 5913 static void 5914 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 5915 uint8_t queue, uint8_t msix_vector) 5916 { 5917 uint32_t tmp, idx; 5918 5919 if (direction == -1) { 5920 /* other causes */ 5921 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5922 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC); 5923 tmp &= ~0xFF; 5924 tmp |= msix_vector; 5925 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp); 5926 } else { 5927 /* rx or tx cause */ 5928 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5929 idx = ((16 * (queue & 1)) + (8 * direction)); 5930 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1)); 5931 tmp &= ~(0xFF << idx); 5932 tmp |= (msix_vector << idx); 5933 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp); 5934 } 5935 } 5936 5937 /** 5938 * set the IVAR registers, mapping interrupt causes to vectors 5939 * @param hw 5940 * pointer to ixgbe_hw struct 5941 * @direction 5942 * 0 for Rx, 1 for Tx, -1 for other causes 5943 * @queue 5944 * queue to map the corresponding interrupt to 5945 * @msix_vector 5946 * the vector to map to the corresponding queue 5947 */ 5948 static void 5949 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 5950 uint8_t queue, uint8_t msix_vector) 5951 { 5952 uint32_t tmp, idx; 5953 5954 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5955 if (hw->mac.type == ixgbe_mac_82598EB) { 5956 if (direction == -1) 5957 direction = 0; 5958 idx = (((direction * 64) + queue) >> 2) & 0x1F; 5959 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx)); 5960 tmp &= ~(0xFF << (8 * (queue & 0x3))); 5961 tmp |= (msix_vector << (8 * (queue & 0x3))); 5962 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp); 5963 } else if ((hw->mac.type == ixgbe_mac_82599EB) || 5964 (hw->mac.type == ixgbe_mac_X540) || 5965 (hw->mac.type == ixgbe_mac_X550) || 5966 (hw->mac.type == ixgbe_mac_X550EM_x)) { 5967 if (direction == -1) { 5968 /* other causes */ 5969 idx = ((queue & 1) * 8); 5970 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC); 5971 tmp &= ~(0xFF << idx); 5972 tmp |= (msix_vector << idx); 5973 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp); 5974 } else { 5975 /* rx or tx causes */ 5976 idx = ((16 * (queue & 1)) + (8 * direction)); 5977 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 5978 tmp &= ~(0xFF << idx); 5979 tmp |= (msix_vector << idx); 5980 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp); 5981 } 5982 } 5983 } 5984 5985 static void 5986 ixgbevf_configure_msix(struct rte_eth_dev *dev) 5987 { 5988 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5989 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5990 struct ixgbe_hw *hw = 5991 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5992 uint32_t q_idx; 5993 uint32_t vector_idx = IXGBE_MISC_VEC_ID; 5994 uint32_t base = IXGBE_MISC_VEC_ID; 5995 5996 /* Configure VF other cause ivar */ 5997 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx); 5998 5999 /* won't configure msix register if no mapping is done 6000 * between intr vector and event fd. 6001 */ 6002 if (!rte_intr_dp_is_en(intr_handle)) 6003 return; 6004 6005 if (rte_intr_allow_others(intr_handle)) { 6006 base = IXGBE_RX_VEC_START; 6007 vector_idx = IXGBE_RX_VEC_START; 6008 } 6009 6010 /* Configure all RX queues of VF */ 6011 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) { 6012 /* Force all queue use vector 0, 6013 * as IXGBE_VF_MAXMSIVECOTR = 1 6014 */ 6015 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx); 6016 intr_handle->intr_vec[q_idx] = vector_idx; 6017 if (vector_idx < base + intr_handle->nb_efd - 1) 6018 vector_idx++; 6019 } 6020 6021 /* As RX queue setting above show, all queues use the vector 0. 6022 * Set only the ITR value of IXGBE_MISC_VEC_ID. 6023 */ 6024 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID), 6025 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 6026 | IXGBE_EITR_CNT_WDIS); 6027 } 6028 6029 /** 6030 * Sets up the hardware to properly generate MSI-X interrupts 6031 * @hw 6032 * board private structure 6033 */ 6034 static void 6035 ixgbe_configure_msix(struct rte_eth_dev *dev) 6036 { 6037 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 6038 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 6039 struct ixgbe_hw *hw = 6040 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6041 uint32_t queue_id, base = IXGBE_MISC_VEC_ID; 6042 uint32_t vec = IXGBE_MISC_VEC_ID; 6043 uint32_t mask; 6044 uint32_t gpie; 6045 6046 /* won't configure msix register if no mapping is done 6047 * between intr vector and event fd 6048 * but if misx has been enabled already, need to configure 6049 * auto clean, auto mask and throttling. 6050 */ 6051 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 6052 if (!rte_intr_dp_is_en(intr_handle) && 6053 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT))) 6054 return; 6055 6056 if (rte_intr_allow_others(intr_handle)) 6057 vec = base = IXGBE_RX_VEC_START; 6058 6059 /* setup GPIE for MSI-x mode */ 6060 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 6061 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 6062 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME; 6063 /* auto clearing and auto setting corresponding bits in EIMS 6064 * when MSI-X interrupt is triggered 6065 */ 6066 if (hw->mac.type == ixgbe_mac_82598EB) { 6067 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 6068 } else { 6069 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 6070 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 6071 } 6072 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 6073 6074 /* Populate the IVAR table and set the ITR values to the 6075 * corresponding register. 6076 */ 6077 if (rte_intr_dp_is_en(intr_handle)) { 6078 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; 6079 queue_id++) { 6080 /* by default, 1:1 mapping */ 6081 ixgbe_set_ivar_map(hw, 0, queue_id, vec); 6082 intr_handle->intr_vec[queue_id] = vec; 6083 if (vec < base + intr_handle->nb_efd - 1) 6084 vec++; 6085 } 6086 6087 switch (hw->mac.type) { 6088 case ixgbe_mac_82598EB: 6089 ixgbe_set_ivar_map(hw, -1, 6090 IXGBE_IVAR_OTHER_CAUSES_INDEX, 6091 IXGBE_MISC_VEC_ID); 6092 break; 6093 case ixgbe_mac_82599EB: 6094 case ixgbe_mac_X540: 6095 case ixgbe_mac_X550: 6096 case ixgbe_mac_X550EM_x: 6097 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID); 6098 break; 6099 default: 6100 break; 6101 } 6102 } 6103 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID), 6104 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 6105 | IXGBE_EITR_CNT_WDIS); 6106 6107 /* set up to autoclear timer, and the vectors */ 6108 mask = IXGBE_EIMS_ENABLE_MASK; 6109 mask &= ~(IXGBE_EIMS_OTHER | 6110 IXGBE_EIMS_MAILBOX | 6111 IXGBE_EIMS_LSC); 6112 6113 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask); 6114 } 6115 6116 int 6117 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, 6118 uint16_t queue_idx, uint16_t tx_rate) 6119 { 6120 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6121 struct rte_eth_rxmode *rxmode; 6122 uint32_t rf_dec, rf_int; 6123 uint32_t bcnrc_val; 6124 uint16_t link_speed = dev->data->dev_link.link_speed; 6125 6126 if (queue_idx >= hw->mac.max_tx_queues) 6127 return -EINVAL; 6128 6129 if (tx_rate != 0) { 6130 /* Calculate the rate factor values to set */ 6131 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate; 6132 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate; 6133 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate; 6134 6135 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA; 6136 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) & 6137 IXGBE_RTTBCNRC_RF_INT_MASK_M); 6138 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK); 6139 } else { 6140 bcnrc_val = 0; 6141 } 6142 6143 rxmode = &dev->data->dev_conf.rxmode; 6144 /* 6145 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 6146 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise 6147 * set as 0x4. 6148 */ 6149 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) && 6150 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE)) 6151 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 6152 IXGBE_MMW_SIZE_JUMBO_FRAME); 6153 else 6154 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 6155 IXGBE_MMW_SIZE_DEFAULT); 6156 6157 /* Set RTTBCNRC of queue X */ 6158 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx); 6159 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 6160 IXGBE_WRITE_FLUSH(hw); 6161 6162 return 0; 6163 } 6164 6165 static int 6166 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 6167 __attribute__((unused)) uint32_t index, 6168 __attribute__((unused)) uint32_t pool) 6169 { 6170 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6171 int diag; 6172 6173 /* 6174 * On a 82599 VF, adding again the same MAC addr is not an idempotent 6175 * operation. Trap this case to avoid exhausting the [very limited] 6176 * set of PF resources used to store VF MAC addresses. 6177 */ 6178 if (memcmp(hw->mac.perm_addr, mac_addr, 6179 sizeof(struct rte_ether_addr)) == 0) 6180 return -1; 6181 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6182 if (diag != 0) 6183 PMD_DRV_LOG(ERR, "Unable to add MAC address " 6184 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d", 6185 mac_addr->addr_bytes[0], 6186 mac_addr->addr_bytes[1], 6187 mac_addr->addr_bytes[2], 6188 mac_addr->addr_bytes[3], 6189 mac_addr->addr_bytes[4], 6190 mac_addr->addr_bytes[5], 6191 diag); 6192 return diag; 6193 } 6194 6195 static void 6196 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index) 6197 { 6198 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6199 struct rte_ether_addr *perm_addr = 6200 (struct rte_ether_addr *)hw->mac.perm_addr; 6201 struct rte_ether_addr *mac_addr; 6202 uint32_t i; 6203 int diag; 6204 6205 /* 6206 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does 6207 * not support the deletion of a given MAC address. 6208 * Instead, it imposes to delete all MAC addresses, then to add again 6209 * all MAC addresses with the exception of the one to be deleted. 6210 */ 6211 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL); 6212 6213 /* 6214 * Add again all MAC addresses, with the exception of the deleted one 6215 * and of the permanent MAC address. 6216 */ 6217 for (i = 0, mac_addr = dev->data->mac_addrs; 6218 i < hw->mac.num_rar_entries; i++, mac_addr++) { 6219 /* Skip the deleted MAC address */ 6220 if (i == index) 6221 continue; 6222 /* Skip NULL MAC addresses */ 6223 if (rte_is_zero_ether_addr(mac_addr)) 6224 continue; 6225 /* Skip the permanent MAC address */ 6226 if (memcmp(perm_addr, mac_addr, 6227 sizeof(struct rte_ether_addr)) == 0) 6228 continue; 6229 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6230 if (diag != 0) 6231 PMD_DRV_LOG(ERR, 6232 "Adding again MAC address " 6233 "%02x:%02x:%02x:%02x:%02x:%02x failed " 6234 "diag=%d", 6235 mac_addr->addr_bytes[0], 6236 mac_addr->addr_bytes[1], 6237 mac_addr->addr_bytes[2], 6238 mac_addr->addr_bytes[3], 6239 mac_addr->addr_bytes[4], 6240 mac_addr->addr_bytes[5], 6241 diag); 6242 } 6243 } 6244 6245 static int 6246 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 6247 struct rte_ether_addr *addr) 6248 { 6249 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6250 6251 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0); 6252 6253 return 0; 6254 } 6255 6256 int 6257 ixgbe_syn_filter_set(struct rte_eth_dev *dev, 6258 struct rte_eth_syn_filter *filter, 6259 bool add) 6260 { 6261 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6262 struct ixgbe_filter_info *filter_info = 6263 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6264 uint32_t syn_info; 6265 uint32_t synqf; 6266 6267 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6268 return -EINVAL; 6269 6270 syn_info = filter_info->syn_info; 6271 6272 if (add) { 6273 if (syn_info & IXGBE_SYN_FILTER_ENABLE) 6274 return -EINVAL; 6275 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) & 6276 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE); 6277 6278 if (filter->hig_pri) 6279 synqf |= IXGBE_SYN_FILTER_SYNQFP; 6280 else 6281 synqf &= ~IXGBE_SYN_FILTER_SYNQFP; 6282 } else { 6283 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6284 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE)) 6285 return -ENOENT; 6286 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE); 6287 } 6288 6289 filter_info->syn_info = synqf; 6290 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 6291 IXGBE_WRITE_FLUSH(hw); 6292 return 0; 6293 } 6294 6295 static int 6296 ixgbe_syn_filter_get(struct rte_eth_dev *dev, 6297 struct rte_eth_syn_filter *filter) 6298 { 6299 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6300 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6301 6302 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 6303 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0; 6304 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1); 6305 return 0; 6306 } 6307 return -ENOENT; 6308 } 6309 6310 static int 6311 ixgbe_syn_filter_handle(struct rte_eth_dev *dev, 6312 enum rte_filter_op filter_op, 6313 void *arg) 6314 { 6315 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6316 int ret; 6317 6318 MAC_TYPE_FILTER_SUP(hw->mac.type); 6319 6320 if (filter_op == RTE_ETH_FILTER_NOP) 6321 return 0; 6322 6323 if (arg == NULL) { 6324 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u", 6325 filter_op); 6326 return -EINVAL; 6327 } 6328 6329 switch (filter_op) { 6330 case RTE_ETH_FILTER_ADD: 6331 ret = ixgbe_syn_filter_set(dev, 6332 (struct rte_eth_syn_filter *)arg, 6333 TRUE); 6334 break; 6335 case RTE_ETH_FILTER_DELETE: 6336 ret = ixgbe_syn_filter_set(dev, 6337 (struct rte_eth_syn_filter *)arg, 6338 FALSE); 6339 break; 6340 case RTE_ETH_FILTER_GET: 6341 ret = ixgbe_syn_filter_get(dev, 6342 (struct rte_eth_syn_filter *)arg); 6343 break; 6344 default: 6345 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op); 6346 ret = -EINVAL; 6347 break; 6348 } 6349 6350 return ret; 6351 } 6352 6353 6354 static inline enum ixgbe_5tuple_protocol 6355 convert_protocol_type(uint8_t protocol_value) 6356 { 6357 if (protocol_value == IPPROTO_TCP) 6358 return IXGBE_FILTER_PROTOCOL_TCP; 6359 else if (protocol_value == IPPROTO_UDP) 6360 return IXGBE_FILTER_PROTOCOL_UDP; 6361 else if (protocol_value == IPPROTO_SCTP) 6362 return IXGBE_FILTER_PROTOCOL_SCTP; 6363 else 6364 return IXGBE_FILTER_PROTOCOL_NONE; 6365 } 6366 6367 /* inject a 5-tuple filter to HW */ 6368 static inline void 6369 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev, 6370 struct ixgbe_5tuple_filter *filter) 6371 { 6372 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6373 int i; 6374 uint32_t ftqf, sdpqf; 6375 uint32_t l34timir = 0; 6376 uint8_t mask = 0xff; 6377 6378 i = filter->index; 6379 6380 sdpqf = (uint32_t)(filter->filter_info.dst_port << 6381 IXGBE_SDPQF_DSTPORT_SHIFT); 6382 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT); 6383 6384 ftqf = (uint32_t)(filter->filter_info.proto & 6385 IXGBE_FTQF_PROTOCOL_MASK); 6386 ftqf |= (uint32_t)((filter->filter_info.priority & 6387 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT); 6388 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */ 6389 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK; 6390 if (filter->filter_info.dst_ip_mask == 0) 6391 mask &= IXGBE_FTQF_DEST_ADDR_MASK; 6392 if (filter->filter_info.src_port_mask == 0) 6393 mask &= IXGBE_FTQF_SOURCE_PORT_MASK; 6394 if (filter->filter_info.dst_port_mask == 0) 6395 mask &= IXGBE_FTQF_DEST_PORT_MASK; 6396 if (filter->filter_info.proto_mask == 0) 6397 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK; 6398 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT; 6399 ftqf |= IXGBE_FTQF_POOL_MASK_EN; 6400 ftqf |= IXGBE_FTQF_QUEUE_ENABLE; 6401 6402 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip); 6403 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip); 6404 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf); 6405 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf); 6406 6407 l34timir |= IXGBE_L34T_IMIR_RESERVE; 6408 l34timir |= (uint32_t)(filter->queue << 6409 IXGBE_L34T_IMIR_QUEUE_SHIFT); 6410 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir); 6411 } 6412 6413 /* 6414 * add a 5tuple filter 6415 * 6416 * @param 6417 * dev: Pointer to struct rte_eth_dev. 6418 * index: the index the filter allocates. 6419 * filter: ponter to the filter that will be added. 6420 * rx_queue: the queue id the filter assigned to. 6421 * 6422 * @return 6423 * - On success, zero. 6424 * - On failure, a negative value. 6425 */ 6426 static int 6427 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 6428 struct ixgbe_5tuple_filter *filter) 6429 { 6430 struct ixgbe_filter_info *filter_info = 6431 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6432 int i, idx, shift; 6433 6434 /* 6435 * look for an unused 5tuple filter index, 6436 * and insert the filter to list. 6437 */ 6438 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) { 6439 idx = i / (sizeof(uint32_t) * NBBY); 6440 shift = i % (sizeof(uint32_t) * NBBY); 6441 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) { 6442 filter_info->fivetuple_mask[idx] |= 1 << shift; 6443 filter->index = i; 6444 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list, 6445 filter, 6446 entries); 6447 break; 6448 } 6449 } 6450 if (i >= IXGBE_MAX_FTQF_FILTERS) { 6451 PMD_DRV_LOG(ERR, "5tuple filters are full."); 6452 return -ENOSYS; 6453 } 6454 6455 ixgbe_inject_5tuple_filter(dev, filter); 6456 6457 return 0; 6458 } 6459 6460 /* 6461 * remove a 5tuple filter 6462 * 6463 * @param 6464 * dev: Pointer to struct rte_eth_dev. 6465 * filter: the pointer of the filter will be removed. 6466 */ 6467 static void 6468 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 6469 struct ixgbe_5tuple_filter *filter) 6470 { 6471 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6472 struct ixgbe_filter_info *filter_info = 6473 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6474 uint16_t index = filter->index; 6475 6476 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &= 6477 ~(1 << (index % (sizeof(uint32_t) * NBBY))); 6478 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries); 6479 rte_free(filter); 6480 6481 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0); 6482 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0); 6483 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0); 6484 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0); 6485 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0); 6486 } 6487 6488 static int 6489 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 6490 { 6491 struct ixgbe_hw *hw; 6492 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD; 6493 struct rte_eth_dev_data *dev_data = dev->data; 6494 6495 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6496 6497 if (mtu < RTE_ETHER_MIN_MTU || 6498 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN) 6499 return -EINVAL; 6500 6501 /* If device is started, refuse mtu that requires the support of 6502 * scattered packets when this feature has not been enabled before. 6503 */ 6504 if (dev_data->dev_started && !dev_data->scattered_rx && 6505 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE > 6506 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 6507 PMD_INIT_LOG(ERR, "Stop port first."); 6508 return -EINVAL; 6509 } 6510 6511 /* 6512 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU 6513 * request of the version 2.0 of the mailbox API. 6514 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0 6515 * of the mailbox API. 6516 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers 6517 * prior to 3.11.33 which contains the following change: 6518 * "ixgbe: Enable jumbo frames support w/ SR-IOV" 6519 */ 6520 ixgbevf_rlpml_set_vf(hw, max_frame); 6521 6522 /* update max frame size */ 6523 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame; 6524 return 0; 6525 } 6526 6527 static inline struct ixgbe_5tuple_filter * 6528 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list, 6529 struct ixgbe_5tuple_filter_info *key) 6530 { 6531 struct ixgbe_5tuple_filter *it; 6532 6533 TAILQ_FOREACH(it, filter_list, entries) { 6534 if (memcmp(key, &it->filter_info, 6535 sizeof(struct ixgbe_5tuple_filter_info)) == 0) { 6536 return it; 6537 } 6538 } 6539 return NULL; 6540 } 6541 6542 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/ 6543 static inline int 6544 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter, 6545 struct ixgbe_5tuple_filter_info *filter_info) 6546 { 6547 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM || 6548 filter->priority > IXGBE_5TUPLE_MAX_PRI || 6549 filter->priority < IXGBE_5TUPLE_MIN_PRI) 6550 return -EINVAL; 6551 6552 switch (filter->dst_ip_mask) { 6553 case UINT32_MAX: 6554 filter_info->dst_ip_mask = 0; 6555 filter_info->dst_ip = filter->dst_ip; 6556 break; 6557 case 0: 6558 filter_info->dst_ip_mask = 1; 6559 break; 6560 default: 6561 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 6562 return -EINVAL; 6563 } 6564 6565 switch (filter->src_ip_mask) { 6566 case UINT32_MAX: 6567 filter_info->src_ip_mask = 0; 6568 filter_info->src_ip = filter->src_ip; 6569 break; 6570 case 0: 6571 filter_info->src_ip_mask = 1; 6572 break; 6573 default: 6574 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 6575 return -EINVAL; 6576 } 6577 6578 switch (filter->dst_port_mask) { 6579 case UINT16_MAX: 6580 filter_info->dst_port_mask = 0; 6581 filter_info->dst_port = filter->dst_port; 6582 break; 6583 case 0: 6584 filter_info->dst_port_mask = 1; 6585 break; 6586 default: 6587 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 6588 return -EINVAL; 6589 } 6590 6591 switch (filter->src_port_mask) { 6592 case UINT16_MAX: 6593 filter_info->src_port_mask = 0; 6594 filter_info->src_port = filter->src_port; 6595 break; 6596 case 0: 6597 filter_info->src_port_mask = 1; 6598 break; 6599 default: 6600 PMD_DRV_LOG(ERR, "invalid src_port mask."); 6601 return -EINVAL; 6602 } 6603 6604 switch (filter->proto_mask) { 6605 case UINT8_MAX: 6606 filter_info->proto_mask = 0; 6607 filter_info->proto = 6608 convert_protocol_type(filter->proto); 6609 break; 6610 case 0: 6611 filter_info->proto_mask = 1; 6612 break; 6613 default: 6614 PMD_DRV_LOG(ERR, "invalid protocol mask."); 6615 return -EINVAL; 6616 } 6617 6618 filter_info->priority = (uint8_t)filter->priority; 6619 return 0; 6620 } 6621 6622 /* 6623 * add or delete a ntuple filter 6624 * 6625 * @param 6626 * dev: Pointer to struct rte_eth_dev. 6627 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6628 * add: if true, add filter, if false, remove filter 6629 * 6630 * @return 6631 * - On success, zero. 6632 * - On failure, a negative value. 6633 */ 6634 int 6635 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 6636 struct rte_eth_ntuple_filter *ntuple_filter, 6637 bool add) 6638 { 6639 struct ixgbe_filter_info *filter_info = 6640 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6641 struct ixgbe_5tuple_filter_info filter_5tuple; 6642 struct ixgbe_5tuple_filter *filter; 6643 int ret; 6644 6645 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6646 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6647 return -EINVAL; 6648 } 6649 6650 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6651 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6652 if (ret < 0) 6653 return ret; 6654 6655 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6656 &filter_5tuple); 6657 if (filter != NULL && add) { 6658 PMD_DRV_LOG(ERR, "filter exists."); 6659 return -EEXIST; 6660 } 6661 if (filter == NULL && !add) { 6662 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6663 return -ENOENT; 6664 } 6665 6666 if (add) { 6667 filter = rte_zmalloc("ixgbe_5tuple_filter", 6668 sizeof(struct ixgbe_5tuple_filter), 0); 6669 if (filter == NULL) 6670 return -ENOMEM; 6671 rte_memcpy(&filter->filter_info, 6672 &filter_5tuple, 6673 sizeof(struct ixgbe_5tuple_filter_info)); 6674 filter->queue = ntuple_filter->queue; 6675 ret = ixgbe_add_5tuple_filter(dev, filter); 6676 if (ret < 0) { 6677 rte_free(filter); 6678 return ret; 6679 } 6680 } else 6681 ixgbe_remove_5tuple_filter(dev, filter); 6682 6683 return 0; 6684 } 6685 6686 /* 6687 * get a ntuple filter 6688 * 6689 * @param 6690 * dev: Pointer to struct rte_eth_dev. 6691 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6692 * 6693 * @return 6694 * - On success, zero. 6695 * - On failure, a negative value. 6696 */ 6697 static int 6698 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev, 6699 struct rte_eth_ntuple_filter *ntuple_filter) 6700 { 6701 struct ixgbe_filter_info *filter_info = 6702 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6703 struct ixgbe_5tuple_filter_info filter_5tuple; 6704 struct ixgbe_5tuple_filter *filter; 6705 int ret; 6706 6707 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6708 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6709 return -EINVAL; 6710 } 6711 6712 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6713 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6714 if (ret < 0) 6715 return ret; 6716 6717 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6718 &filter_5tuple); 6719 if (filter == NULL) { 6720 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6721 return -ENOENT; 6722 } 6723 ntuple_filter->queue = filter->queue; 6724 return 0; 6725 } 6726 6727 /* 6728 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter. 6729 * @dev: pointer to rte_eth_dev structure 6730 * @filter_op:operation will be taken. 6731 * @arg: a pointer to specific structure corresponding to the filter_op 6732 * 6733 * @return 6734 * - On success, zero. 6735 * - On failure, a negative value. 6736 */ 6737 static int 6738 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev, 6739 enum rte_filter_op filter_op, 6740 void *arg) 6741 { 6742 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6743 int ret; 6744 6745 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type); 6746 6747 if (filter_op == RTE_ETH_FILTER_NOP) 6748 return 0; 6749 6750 if (arg == NULL) { 6751 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 6752 filter_op); 6753 return -EINVAL; 6754 } 6755 6756 switch (filter_op) { 6757 case RTE_ETH_FILTER_ADD: 6758 ret = ixgbe_add_del_ntuple_filter(dev, 6759 (struct rte_eth_ntuple_filter *)arg, 6760 TRUE); 6761 break; 6762 case RTE_ETH_FILTER_DELETE: 6763 ret = ixgbe_add_del_ntuple_filter(dev, 6764 (struct rte_eth_ntuple_filter *)arg, 6765 FALSE); 6766 break; 6767 case RTE_ETH_FILTER_GET: 6768 ret = ixgbe_get_ntuple_filter(dev, 6769 (struct rte_eth_ntuple_filter *)arg); 6770 break; 6771 default: 6772 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 6773 ret = -EINVAL; 6774 break; 6775 } 6776 return ret; 6777 } 6778 6779 int 6780 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 6781 struct rte_eth_ethertype_filter *filter, 6782 bool add) 6783 { 6784 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6785 struct ixgbe_filter_info *filter_info = 6786 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6787 uint32_t etqf = 0; 6788 uint32_t etqs = 0; 6789 int ret; 6790 struct ixgbe_ethertype_filter ethertype_filter; 6791 6792 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6793 return -EINVAL; 6794 6795 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 || 6796 filter->ether_type == RTE_ETHER_TYPE_IPV6) { 6797 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in" 6798 " ethertype filter.", filter->ether_type); 6799 return -EINVAL; 6800 } 6801 6802 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) { 6803 PMD_DRV_LOG(ERR, "mac compare is unsupported."); 6804 return -EINVAL; 6805 } 6806 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) { 6807 PMD_DRV_LOG(ERR, "drop option is unsupported."); 6808 return -EINVAL; 6809 } 6810 6811 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6812 if (ret >= 0 && add) { 6813 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.", 6814 filter->ether_type); 6815 return -EEXIST; 6816 } 6817 if (ret < 0 && !add) { 6818 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6819 filter->ether_type); 6820 return -ENOENT; 6821 } 6822 6823 if (add) { 6824 etqf = IXGBE_ETQF_FILTER_EN; 6825 etqf |= (uint32_t)filter->ether_type; 6826 etqs |= (uint32_t)((filter->queue << 6827 IXGBE_ETQS_RX_QUEUE_SHIFT) & 6828 IXGBE_ETQS_RX_QUEUE); 6829 etqs |= IXGBE_ETQS_QUEUE_EN; 6830 6831 ethertype_filter.ethertype = filter->ether_type; 6832 ethertype_filter.etqf = etqf; 6833 ethertype_filter.etqs = etqs; 6834 ethertype_filter.conf = FALSE; 6835 ret = ixgbe_ethertype_filter_insert(filter_info, 6836 ðertype_filter); 6837 if (ret < 0) { 6838 PMD_DRV_LOG(ERR, "ethertype filters are full."); 6839 return -ENOSPC; 6840 } 6841 } else { 6842 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret); 6843 if (ret < 0) 6844 return -ENOSYS; 6845 } 6846 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf); 6847 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs); 6848 IXGBE_WRITE_FLUSH(hw); 6849 6850 return 0; 6851 } 6852 6853 static int 6854 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, 6855 struct rte_eth_ethertype_filter *filter) 6856 { 6857 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6858 struct ixgbe_filter_info *filter_info = 6859 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6860 uint32_t etqf, etqs; 6861 int ret; 6862 6863 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6864 if (ret < 0) { 6865 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6866 filter->ether_type); 6867 return -ENOENT; 6868 } 6869 6870 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret)); 6871 if (etqf & IXGBE_ETQF_FILTER_EN) { 6872 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret)); 6873 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE; 6874 filter->flags = 0; 6875 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> 6876 IXGBE_ETQS_RX_QUEUE_SHIFT; 6877 return 0; 6878 } 6879 return -ENOENT; 6880 } 6881 6882 /* 6883 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter. 6884 * @dev: pointer to rte_eth_dev structure 6885 * @filter_op:operation will be taken. 6886 * @arg: a pointer to specific structure corresponding to the filter_op 6887 */ 6888 static int 6889 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev, 6890 enum rte_filter_op filter_op, 6891 void *arg) 6892 { 6893 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6894 int ret; 6895 6896 MAC_TYPE_FILTER_SUP(hw->mac.type); 6897 6898 if (filter_op == RTE_ETH_FILTER_NOP) 6899 return 0; 6900 6901 if (arg == NULL) { 6902 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 6903 filter_op); 6904 return -EINVAL; 6905 } 6906 6907 switch (filter_op) { 6908 case RTE_ETH_FILTER_ADD: 6909 ret = ixgbe_add_del_ethertype_filter(dev, 6910 (struct rte_eth_ethertype_filter *)arg, 6911 TRUE); 6912 break; 6913 case RTE_ETH_FILTER_DELETE: 6914 ret = ixgbe_add_del_ethertype_filter(dev, 6915 (struct rte_eth_ethertype_filter *)arg, 6916 FALSE); 6917 break; 6918 case RTE_ETH_FILTER_GET: 6919 ret = ixgbe_get_ethertype_filter(dev, 6920 (struct rte_eth_ethertype_filter *)arg); 6921 break; 6922 default: 6923 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 6924 ret = -EINVAL; 6925 break; 6926 } 6927 return ret; 6928 } 6929 6930 static int 6931 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 6932 enum rte_filter_type filter_type, 6933 enum rte_filter_op filter_op, 6934 void *arg) 6935 { 6936 int ret = 0; 6937 6938 switch (filter_type) { 6939 case RTE_ETH_FILTER_NTUPLE: 6940 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg); 6941 break; 6942 case RTE_ETH_FILTER_ETHERTYPE: 6943 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg); 6944 break; 6945 case RTE_ETH_FILTER_SYN: 6946 ret = ixgbe_syn_filter_handle(dev, filter_op, arg); 6947 break; 6948 case RTE_ETH_FILTER_FDIR: 6949 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg); 6950 break; 6951 case RTE_ETH_FILTER_L2_TUNNEL: 6952 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg); 6953 break; 6954 case RTE_ETH_FILTER_GENERIC: 6955 if (filter_op != RTE_ETH_FILTER_GET) 6956 return -EINVAL; 6957 *(const void **)arg = &ixgbe_flow_ops; 6958 break; 6959 default: 6960 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 6961 filter_type); 6962 ret = -EINVAL; 6963 break; 6964 } 6965 6966 return ret; 6967 } 6968 6969 static u8 * 6970 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw, 6971 u8 **mc_addr_ptr, u32 *vmdq) 6972 { 6973 u8 *mc_addr; 6974 6975 *vmdq = 0; 6976 mc_addr = *mc_addr_ptr; 6977 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr)); 6978 return mc_addr; 6979 } 6980 6981 static int 6982 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 6983 struct rte_ether_addr *mc_addr_set, 6984 uint32_t nb_mc_addr) 6985 { 6986 struct ixgbe_hw *hw; 6987 u8 *mc_addr_list; 6988 6989 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6990 mc_addr_list = (u8 *)mc_addr_set; 6991 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr, 6992 ixgbe_dev_addr_list_itr, TRUE); 6993 } 6994 6995 static uint64_t 6996 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev) 6997 { 6998 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6999 uint64_t systime_cycles; 7000 7001 switch (hw->mac.type) { 7002 case ixgbe_mac_X550: 7003 case ixgbe_mac_X550EM_x: 7004 case ixgbe_mac_X550EM_a: 7005 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */ 7006 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 7007 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 7008 * NSEC_PER_SEC; 7009 break; 7010 default: 7011 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 7012 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 7013 << 32; 7014 } 7015 7016 return systime_cycles; 7017 } 7018 7019 static uint64_t 7020 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) 7021 { 7022 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7023 uint64_t rx_tstamp_cycles; 7024 7025 switch (hw->mac.type) { 7026 case ixgbe_mac_X550: 7027 case ixgbe_mac_X550EM_x: 7028 case ixgbe_mac_X550EM_a: 7029 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 7030 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 7031 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 7032 * NSEC_PER_SEC; 7033 break; 7034 default: 7035 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 7036 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 7037 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 7038 << 32; 7039 } 7040 7041 return rx_tstamp_cycles; 7042 } 7043 7044 static uint64_t 7045 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 7046 { 7047 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7048 uint64_t tx_tstamp_cycles; 7049 7050 switch (hw->mac.type) { 7051 case ixgbe_mac_X550: 7052 case ixgbe_mac_X550EM_x: 7053 case ixgbe_mac_X550EM_a: 7054 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 7055 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 7056 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 7057 * NSEC_PER_SEC; 7058 break; 7059 default: 7060 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 7061 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 7062 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 7063 << 32; 7064 } 7065 7066 return tx_tstamp_cycles; 7067 } 7068 7069 static void 7070 ixgbe_start_timecounters(struct rte_eth_dev *dev) 7071 { 7072 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7073 struct ixgbe_adapter *adapter = dev->data->dev_private; 7074 struct rte_eth_link link; 7075 uint32_t incval = 0; 7076 uint32_t shift = 0; 7077 7078 /* Get current link speed. */ 7079 ixgbe_dev_link_update(dev, 1); 7080 rte_eth_linkstatus_get(dev, &link); 7081 7082 switch (link.link_speed) { 7083 case ETH_SPEED_NUM_100M: 7084 incval = IXGBE_INCVAL_100; 7085 shift = IXGBE_INCVAL_SHIFT_100; 7086 break; 7087 case ETH_SPEED_NUM_1G: 7088 incval = IXGBE_INCVAL_1GB; 7089 shift = IXGBE_INCVAL_SHIFT_1GB; 7090 break; 7091 case ETH_SPEED_NUM_10G: 7092 default: 7093 incval = IXGBE_INCVAL_10GB; 7094 shift = IXGBE_INCVAL_SHIFT_10GB; 7095 break; 7096 } 7097 7098 switch (hw->mac.type) { 7099 case ixgbe_mac_X550: 7100 case ixgbe_mac_X550EM_x: 7101 case ixgbe_mac_X550EM_a: 7102 /* Independent of link speed. */ 7103 incval = 1; 7104 /* Cycles read will be interpreted as ns. */ 7105 shift = 0; 7106 /* Fall-through */ 7107 case ixgbe_mac_X540: 7108 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval); 7109 break; 7110 case ixgbe_mac_82599EB: 7111 incval >>= IXGBE_INCVAL_SHIFT_82599; 7112 shift -= IXGBE_INCVAL_SHIFT_82599; 7113 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 7114 (1 << IXGBE_INCPER_SHIFT_82599) | incval); 7115 break; 7116 default: 7117 /* Not supported. */ 7118 return; 7119 } 7120 7121 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 7122 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 7123 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 7124 7125 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 7126 adapter->systime_tc.cc_shift = shift; 7127 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; 7128 7129 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 7130 adapter->rx_tstamp_tc.cc_shift = shift; 7131 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 7132 7133 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 7134 adapter->tx_tstamp_tc.cc_shift = shift; 7135 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 7136 } 7137 7138 static int 7139 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 7140 { 7141 struct ixgbe_adapter *adapter = dev->data->dev_private; 7142 7143 adapter->systime_tc.nsec += delta; 7144 adapter->rx_tstamp_tc.nsec += delta; 7145 adapter->tx_tstamp_tc.nsec += delta; 7146 7147 return 0; 7148 } 7149 7150 static int 7151 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 7152 { 7153 uint64_t ns; 7154 struct ixgbe_adapter *adapter = dev->data->dev_private; 7155 7156 ns = rte_timespec_to_ns(ts); 7157 /* Set the timecounters to a new value. */ 7158 adapter->systime_tc.nsec = ns; 7159 adapter->rx_tstamp_tc.nsec = ns; 7160 adapter->tx_tstamp_tc.nsec = ns; 7161 7162 return 0; 7163 } 7164 7165 static int 7166 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 7167 { 7168 uint64_t ns, systime_cycles; 7169 struct ixgbe_adapter *adapter = dev->data->dev_private; 7170 7171 systime_cycles = ixgbe_read_systime_cyclecounter(dev); 7172 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 7173 *ts = rte_ns_to_timespec(ns); 7174 7175 return 0; 7176 } 7177 7178 static int 7179 ixgbe_timesync_enable(struct rte_eth_dev *dev) 7180 { 7181 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7182 uint32_t tsync_ctl; 7183 uint32_t tsauxc; 7184 7185 /* Stop the timesync system time. */ 7186 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0); 7187 /* Reset the timesync system time value. */ 7188 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0); 7189 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0); 7190 7191 /* Enable system time for platforms where it isn't on by default. */ 7192 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC); 7193 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME; 7194 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc); 7195 7196 ixgbe_start_timecounters(dev); 7197 7198 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7199 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 7200 (RTE_ETHER_TYPE_1588 | 7201 IXGBE_ETQF_FILTER_EN | 7202 IXGBE_ETQF_1588)); 7203 7204 /* Enable timestamping of received PTP packets. */ 7205 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7206 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED; 7207 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7208 7209 /* Enable timestamping of transmitted PTP packets. */ 7210 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7211 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED; 7212 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7213 7214 IXGBE_WRITE_FLUSH(hw); 7215 7216 return 0; 7217 } 7218 7219 static int 7220 ixgbe_timesync_disable(struct rte_eth_dev *dev) 7221 { 7222 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7223 uint32_t tsync_ctl; 7224 7225 /* Disable timestamping of transmitted PTP packets. */ 7226 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7227 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED; 7228 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7229 7230 /* Disable timestamping of received PTP packets. */ 7231 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7232 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED; 7233 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7234 7235 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7236 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0); 7237 7238 /* Stop incrementating the System Time registers. */ 7239 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0); 7240 7241 return 0; 7242 } 7243 7244 static int 7245 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 7246 struct timespec *timestamp, 7247 uint32_t flags __rte_unused) 7248 { 7249 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7250 struct ixgbe_adapter *adapter = dev->data->dev_private; 7251 uint32_t tsync_rxctl; 7252 uint64_t rx_tstamp_cycles; 7253 uint64_t ns; 7254 7255 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7256 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0) 7257 return -EINVAL; 7258 7259 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev); 7260 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 7261 *timestamp = rte_ns_to_timespec(ns); 7262 7263 return 0; 7264 } 7265 7266 static int 7267 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 7268 struct timespec *timestamp) 7269 { 7270 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7271 struct ixgbe_adapter *adapter = dev->data->dev_private; 7272 uint32_t tsync_txctl; 7273 uint64_t tx_tstamp_cycles; 7274 uint64_t ns; 7275 7276 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7277 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0) 7278 return -EINVAL; 7279 7280 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev); 7281 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 7282 *timestamp = rte_ns_to_timespec(ns); 7283 7284 return 0; 7285 } 7286 7287 static int 7288 ixgbe_get_reg_length(struct rte_eth_dev *dev) 7289 { 7290 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7291 int count = 0; 7292 int g_ind = 0; 7293 const struct reg_info *reg_group; 7294 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7295 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7296 7297 while ((reg_group = reg_set[g_ind++])) 7298 count += ixgbe_regs_group_count(reg_group); 7299 7300 return count; 7301 } 7302 7303 static int 7304 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused) 7305 { 7306 int count = 0; 7307 int g_ind = 0; 7308 const struct reg_info *reg_group; 7309 7310 while ((reg_group = ixgbevf_regs[g_ind++])) 7311 count += ixgbe_regs_group_count(reg_group); 7312 7313 return count; 7314 } 7315 7316 static int 7317 ixgbe_get_regs(struct rte_eth_dev *dev, 7318 struct rte_dev_reg_info *regs) 7319 { 7320 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7321 uint32_t *data = regs->data; 7322 int g_ind = 0; 7323 int count = 0; 7324 const struct reg_info *reg_group; 7325 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7326 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7327 7328 if (data == NULL) { 7329 regs->length = ixgbe_get_reg_length(dev); 7330 regs->width = sizeof(uint32_t); 7331 return 0; 7332 } 7333 7334 /* Support only full register dump */ 7335 if ((regs->length == 0) || 7336 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) { 7337 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7338 hw->device_id; 7339 while ((reg_group = reg_set[g_ind++])) 7340 count += ixgbe_read_regs_group(dev, &data[count], 7341 reg_group); 7342 return 0; 7343 } 7344 7345 return -ENOTSUP; 7346 } 7347 7348 static int 7349 ixgbevf_get_regs(struct rte_eth_dev *dev, 7350 struct rte_dev_reg_info *regs) 7351 { 7352 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7353 uint32_t *data = regs->data; 7354 int g_ind = 0; 7355 int count = 0; 7356 const struct reg_info *reg_group; 7357 7358 if (data == NULL) { 7359 regs->length = ixgbevf_get_reg_length(dev); 7360 regs->width = sizeof(uint32_t); 7361 return 0; 7362 } 7363 7364 /* Support only full register dump */ 7365 if ((regs->length == 0) || 7366 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) { 7367 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7368 hw->device_id; 7369 while ((reg_group = ixgbevf_regs[g_ind++])) 7370 count += ixgbe_read_regs_group(dev, &data[count], 7371 reg_group); 7372 return 0; 7373 } 7374 7375 return -ENOTSUP; 7376 } 7377 7378 static int 7379 ixgbe_get_eeprom_length(struct rte_eth_dev *dev) 7380 { 7381 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7382 7383 /* Return unit is byte count */ 7384 return hw->eeprom.word_size * 2; 7385 } 7386 7387 static int 7388 ixgbe_get_eeprom(struct rte_eth_dev *dev, 7389 struct rte_dev_eeprom_info *in_eeprom) 7390 { 7391 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7392 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7393 uint16_t *data = in_eeprom->data; 7394 int first, length; 7395 7396 first = in_eeprom->offset >> 1; 7397 length = in_eeprom->length >> 1; 7398 if ((first > hw->eeprom.word_size) || 7399 ((first + length) > hw->eeprom.word_size)) 7400 return -EINVAL; 7401 7402 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7403 7404 return eeprom->ops.read_buffer(hw, first, length, data); 7405 } 7406 7407 static int 7408 ixgbe_set_eeprom(struct rte_eth_dev *dev, 7409 struct rte_dev_eeprom_info *in_eeprom) 7410 { 7411 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7412 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7413 uint16_t *data = in_eeprom->data; 7414 int first, length; 7415 7416 first = in_eeprom->offset >> 1; 7417 length = in_eeprom->length >> 1; 7418 if ((first > hw->eeprom.word_size) || 7419 ((first + length) > hw->eeprom.word_size)) 7420 return -EINVAL; 7421 7422 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7423 7424 return eeprom->ops.write_buffer(hw, first, length, data); 7425 } 7426 7427 static int 7428 ixgbe_get_module_info(struct rte_eth_dev *dev, 7429 struct rte_eth_dev_module_info *modinfo) 7430 { 7431 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7432 uint32_t status; 7433 uint8_t sff8472_rev, addr_mode; 7434 bool page_swap = false; 7435 7436 /* Check whether we support SFF-8472 or not */ 7437 status = hw->phy.ops.read_i2c_eeprom(hw, 7438 IXGBE_SFF_SFF_8472_COMP, 7439 &sff8472_rev); 7440 if (status != 0) 7441 return -EIO; 7442 7443 /* addressing mode is not supported */ 7444 status = hw->phy.ops.read_i2c_eeprom(hw, 7445 IXGBE_SFF_SFF_8472_SWAP, 7446 &addr_mode); 7447 if (status != 0) 7448 return -EIO; 7449 7450 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 7451 PMD_DRV_LOG(ERR, 7452 "Address change required to access page 0xA2, " 7453 "but not supported. Please report the module " 7454 "type to the driver maintainers."); 7455 page_swap = true; 7456 } 7457 7458 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) { 7459 /* We have a SFP, but it does not support SFF-8472 */ 7460 modinfo->type = RTE_ETH_MODULE_SFF_8079; 7461 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 7462 } else { 7463 /* We have a SFP which supports a revision of SFF-8472. */ 7464 modinfo->type = RTE_ETH_MODULE_SFF_8472; 7465 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 7466 } 7467 7468 return 0; 7469 } 7470 7471 static int 7472 ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 7473 struct rte_dev_eeprom_info *info) 7474 { 7475 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7476 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 7477 uint8_t databyte = 0xFF; 7478 uint8_t *data = info->data; 7479 uint32_t i = 0; 7480 7481 if (info->length == 0) 7482 return -EINVAL; 7483 7484 for (i = info->offset; i < info->offset + info->length; i++) { 7485 if (i < RTE_ETH_MODULE_SFF_8079_LEN) 7486 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 7487 else 7488 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 7489 7490 if (status != 0) 7491 return -EIO; 7492 7493 data[i - info->offset] = databyte; 7494 } 7495 7496 return 0; 7497 } 7498 7499 uint16_t 7500 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) { 7501 switch (mac_type) { 7502 case ixgbe_mac_X550: 7503 case ixgbe_mac_X550EM_x: 7504 case ixgbe_mac_X550EM_a: 7505 return ETH_RSS_RETA_SIZE_512; 7506 case ixgbe_mac_X550_vf: 7507 case ixgbe_mac_X550EM_x_vf: 7508 case ixgbe_mac_X550EM_a_vf: 7509 return ETH_RSS_RETA_SIZE_64; 7510 case ixgbe_mac_X540_vf: 7511 case ixgbe_mac_82599_vf: 7512 return 0; 7513 default: 7514 return ETH_RSS_RETA_SIZE_128; 7515 } 7516 } 7517 7518 uint32_t 7519 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) { 7520 switch (mac_type) { 7521 case ixgbe_mac_X550: 7522 case ixgbe_mac_X550EM_x: 7523 case ixgbe_mac_X550EM_a: 7524 if (reta_idx < ETH_RSS_RETA_SIZE_128) 7525 return IXGBE_RETA(reta_idx >> 2); 7526 else 7527 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2); 7528 case ixgbe_mac_X550_vf: 7529 case ixgbe_mac_X550EM_x_vf: 7530 case ixgbe_mac_X550EM_a_vf: 7531 return IXGBE_VFRETA(reta_idx >> 2); 7532 default: 7533 return IXGBE_RETA(reta_idx >> 2); 7534 } 7535 } 7536 7537 uint32_t 7538 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) { 7539 switch (mac_type) { 7540 case ixgbe_mac_X550_vf: 7541 case ixgbe_mac_X550EM_x_vf: 7542 case ixgbe_mac_X550EM_a_vf: 7543 return IXGBE_VFMRQC; 7544 default: 7545 return IXGBE_MRQC; 7546 } 7547 } 7548 7549 uint32_t 7550 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) { 7551 switch (mac_type) { 7552 case ixgbe_mac_X550_vf: 7553 case ixgbe_mac_X550EM_x_vf: 7554 case ixgbe_mac_X550EM_a_vf: 7555 return IXGBE_VFRSSRK(i); 7556 default: 7557 return IXGBE_RSSRK(i); 7558 } 7559 } 7560 7561 bool 7562 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) { 7563 switch (mac_type) { 7564 case ixgbe_mac_82599_vf: 7565 case ixgbe_mac_X540_vf: 7566 return 0; 7567 default: 7568 return 1; 7569 } 7570 } 7571 7572 static int 7573 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 7574 struct rte_eth_dcb_info *dcb_info) 7575 { 7576 struct ixgbe_dcb_config *dcb_config = 7577 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 7578 struct ixgbe_dcb_tc_config *tc; 7579 struct rte_eth_dcb_tc_queue_mapping *tc_queue; 7580 uint8_t nb_tcs; 7581 uint8_t i, j; 7582 7583 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG) 7584 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs; 7585 else 7586 dcb_info->nb_tcs = 1; 7587 7588 tc_queue = &dcb_info->tc_queue; 7589 nb_tcs = dcb_info->nb_tcs; 7590 7591 if (dcb_config->vt_mode) { /* vt is enabled*/ 7592 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf = 7593 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf; 7594 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7595 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i]; 7596 if (RTE_ETH_DEV_SRIOV(dev).active > 0) { 7597 for (j = 0; j < nb_tcs; j++) { 7598 tc_queue->tc_rxq[0][j].base = j; 7599 tc_queue->tc_rxq[0][j].nb_queue = 1; 7600 tc_queue->tc_txq[0][j].base = j; 7601 tc_queue->tc_txq[0][j].nb_queue = 1; 7602 } 7603 } else { 7604 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) { 7605 for (j = 0; j < nb_tcs; j++) { 7606 tc_queue->tc_rxq[i][j].base = 7607 i * nb_tcs + j; 7608 tc_queue->tc_rxq[i][j].nb_queue = 1; 7609 tc_queue->tc_txq[i][j].base = 7610 i * nb_tcs + j; 7611 tc_queue->tc_txq[i][j].nb_queue = 1; 7612 } 7613 } 7614 } 7615 } else { /* vt is disabled*/ 7616 struct rte_eth_dcb_rx_conf *rx_conf = 7617 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 7618 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7619 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i]; 7620 if (dcb_info->nb_tcs == ETH_4_TCS) { 7621 for (i = 0; i < dcb_info->nb_tcs; i++) { 7622 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32; 7623 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7624 } 7625 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7626 dcb_info->tc_queue.tc_txq[0][1].base = 64; 7627 dcb_info->tc_queue.tc_txq[0][2].base = 96; 7628 dcb_info->tc_queue.tc_txq[0][3].base = 112; 7629 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64; 7630 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7631 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7632 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7633 } else if (dcb_info->nb_tcs == ETH_8_TCS) { 7634 for (i = 0; i < dcb_info->nb_tcs; i++) { 7635 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16; 7636 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7637 } 7638 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7639 dcb_info->tc_queue.tc_txq[0][1].base = 32; 7640 dcb_info->tc_queue.tc_txq[0][2].base = 64; 7641 dcb_info->tc_queue.tc_txq[0][3].base = 80; 7642 dcb_info->tc_queue.tc_txq[0][4].base = 96; 7643 dcb_info->tc_queue.tc_txq[0][5].base = 104; 7644 dcb_info->tc_queue.tc_txq[0][6].base = 112; 7645 dcb_info->tc_queue.tc_txq[0][7].base = 120; 7646 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32; 7647 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7648 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7649 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7650 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8; 7651 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8; 7652 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8; 7653 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8; 7654 } 7655 } 7656 for (i = 0; i < dcb_info->nb_tcs; i++) { 7657 tc = &dcb_config->tc_config[i]; 7658 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent; 7659 } 7660 return 0; 7661 } 7662 7663 /* Update e-tag ether type */ 7664 static int 7665 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw, 7666 uint16_t ether_type) 7667 { 7668 uint32_t etag_etype; 7669 7670 if (hw->mac.type != ixgbe_mac_X550 && 7671 hw->mac.type != ixgbe_mac_X550EM_x && 7672 hw->mac.type != ixgbe_mac_X550EM_a) { 7673 return -ENOTSUP; 7674 } 7675 7676 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7677 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK; 7678 etag_etype |= ether_type; 7679 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7680 IXGBE_WRITE_FLUSH(hw); 7681 7682 return 0; 7683 } 7684 7685 /* Config l2 tunnel ether type */ 7686 static int 7687 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev, 7688 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7689 { 7690 int ret = 0; 7691 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7692 struct ixgbe_l2_tn_info *l2_tn_info = 7693 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7694 7695 if (l2_tunnel == NULL) 7696 return -EINVAL; 7697 7698 switch (l2_tunnel->l2_tunnel_type) { 7699 case RTE_L2_TUNNEL_TYPE_E_TAG: 7700 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type; 7701 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type); 7702 break; 7703 default: 7704 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7705 ret = -EINVAL; 7706 break; 7707 } 7708 7709 return ret; 7710 } 7711 7712 /* Enable e-tag tunnel */ 7713 static int 7714 ixgbe_e_tag_enable(struct ixgbe_hw *hw) 7715 { 7716 uint32_t etag_etype; 7717 7718 if (hw->mac.type != ixgbe_mac_X550 && 7719 hw->mac.type != ixgbe_mac_X550EM_x && 7720 hw->mac.type != ixgbe_mac_X550EM_a) { 7721 return -ENOTSUP; 7722 } 7723 7724 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7725 etag_etype |= IXGBE_ETAG_ETYPE_VALID; 7726 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7727 IXGBE_WRITE_FLUSH(hw); 7728 7729 return 0; 7730 } 7731 7732 /* Enable l2 tunnel */ 7733 static int 7734 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev, 7735 enum rte_eth_tunnel_type l2_tunnel_type) 7736 { 7737 int ret = 0; 7738 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7739 struct ixgbe_l2_tn_info *l2_tn_info = 7740 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7741 7742 switch (l2_tunnel_type) { 7743 case RTE_L2_TUNNEL_TYPE_E_TAG: 7744 l2_tn_info->e_tag_en = TRUE; 7745 ret = ixgbe_e_tag_enable(hw); 7746 break; 7747 default: 7748 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7749 ret = -EINVAL; 7750 break; 7751 } 7752 7753 return ret; 7754 } 7755 7756 /* Disable e-tag tunnel */ 7757 static int 7758 ixgbe_e_tag_disable(struct ixgbe_hw *hw) 7759 { 7760 uint32_t etag_etype; 7761 7762 if (hw->mac.type != ixgbe_mac_X550 && 7763 hw->mac.type != ixgbe_mac_X550EM_x && 7764 hw->mac.type != ixgbe_mac_X550EM_a) { 7765 return -ENOTSUP; 7766 } 7767 7768 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7769 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID; 7770 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7771 IXGBE_WRITE_FLUSH(hw); 7772 7773 return 0; 7774 } 7775 7776 /* Disable l2 tunnel */ 7777 static int 7778 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev, 7779 enum rte_eth_tunnel_type l2_tunnel_type) 7780 { 7781 int ret = 0; 7782 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7783 struct ixgbe_l2_tn_info *l2_tn_info = 7784 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7785 7786 switch (l2_tunnel_type) { 7787 case RTE_L2_TUNNEL_TYPE_E_TAG: 7788 l2_tn_info->e_tag_en = FALSE; 7789 ret = ixgbe_e_tag_disable(hw); 7790 break; 7791 default: 7792 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7793 ret = -EINVAL; 7794 break; 7795 } 7796 7797 return ret; 7798 } 7799 7800 static int 7801 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev, 7802 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7803 { 7804 int ret = 0; 7805 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7806 uint32_t i, rar_entries; 7807 uint32_t rar_low, rar_high; 7808 7809 if (hw->mac.type != ixgbe_mac_X550 && 7810 hw->mac.type != ixgbe_mac_X550EM_x && 7811 hw->mac.type != ixgbe_mac_X550EM_a) { 7812 return -ENOTSUP; 7813 } 7814 7815 rar_entries = ixgbe_get_num_rx_addrs(hw); 7816 7817 for (i = 1; i < rar_entries; i++) { 7818 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7819 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 7820 if ((rar_high & IXGBE_RAH_AV) && 7821 (rar_high & IXGBE_RAH_ADTYPE) && 7822 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) == 7823 l2_tunnel->tunnel_id)) { 7824 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 7825 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 7826 7827 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL); 7828 7829 return ret; 7830 } 7831 } 7832 7833 return ret; 7834 } 7835 7836 static int 7837 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev, 7838 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7839 { 7840 int ret = 0; 7841 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7842 uint32_t i, rar_entries; 7843 uint32_t rar_low, rar_high; 7844 7845 if (hw->mac.type != ixgbe_mac_X550 && 7846 hw->mac.type != ixgbe_mac_X550EM_x && 7847 hw->mac.type != ixgbe_mac_X550EM_a) { 7848 return -ENOTSUP; 7849 } 7850 7851 /* One entry for one tunnel. Try to remove potential existing entry. */ 7852 ixgbe_e_tag_filter_del(dev, l2_tunnel); 7853 7854 rar_entries = ixgbe_get_num_rx_addrs(hw); 7855 7856 for (i = 1; i < rar_entries; i++) { 7857 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7858 if (rar_high & IXGBE_RAH_AV) { 7859 continue; 7860 } else { 7861 ixgbe_set_vmdq(hw, i, l2_tunnel->pool); 7862 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE; 7863 rar_low = l2_tunnel->tunnel_id; 7864 7865 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low); 7866 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high); 7867 7868 return ret; 7869 } 7870 } 7871 7872 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full." 7873 " Please remove a rule before adding a new one."); 7874 return -EINVAL; 7875 } 7876 7877 static inline struct ixgbe_l2_tn_filter * 7878 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info, 7879 struct ixgbe_l2_tn_key *key) 7880 { 7881 int ret; 7882 7883 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key); 7884 if (ret < 0) 7885 return NULL; 7886 7887 return l2_tn_info->hash_map[ret]; 7888 } 7889 7890 static inline int 7891 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7892 struct ixgbe_l2_tn_filter *l2_tn_filter) 7893 { 7894 int ret; 7895 7896 ret = rte_hash_add_key(l2_tn_info->hash_handle, 7897 &l2_tn_filter->key); 7898 7899 if (ret < 0) { 7900 PMD_DRV_LOG(ERR, 7901 "Failed to insert L2 tunnel filter" 7902 " to hash table %d!", 7903 ret); 7904 return ret; 7905 } 7906 7907 l2_tn_info->hash_map[ret] = l2_tn_filter; 7908 7909 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 7910 7911 return 0; 7912 } 7913 7914 static inline int 7915 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7916 struct ixgbe_l2_tn_key *key) 7917 { 7918 int ret; 7919 struct ixgbe_l2_tn_filter *l2_tn_filter; 7920 7921 ret = rte_hash_del_key(l2_tn_info->hash_handle, key); 7922 7923 if (ret < 0) { 7924 PMD_DRV_LOG(ERR, 7925 "No such L2 tunnel filter to delete %d!", 7926 ret); 7927 return ret; 7928 } 7929 7930 l2_tn_filter = l2_tn_info->hash_map[ret]; 7931 l2_tn_info->hash_map[ret] = NULL; 7932 7933 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 7934 rte_free(l2_tn_filter); 7935 7936 return 0; 7937 } 7938 7939 /* Add l2 tunnel filter */ 7940 int 7941 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 7942 struct rte_eth_l2_tunnel_conf *l2_tunnel, 7943 bool restore) 7944 { 7945 int ret; 7946 struct ixgbe_l2_tn_info *l2_tn_info = 7947 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7948 struct ixgbe_l2_tn_key key; 7949 struct ixgbe_l2_tn_filter *node; 7950 7951 if (!restore) { 7952 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 7953 key.tn_id = l2_tunnel->tunnel_id; 7954 7955 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key); 7956 7957 if (node) { 7958 PMD_DRV_LOG(ERR, 7959 "The L2 tunnel filter already exists!"); 7960 return -EINVAL; 7961 } 7962 7963 node = rte_zmalloc("ixgbe_l2_tn", 7964 sizeof(struct ixgbe_l2_tn_filter), 7965 0); 7966 if (!node) 7967 return -ENOMEM; 7968 7969 rte_memcpy(&node->key, 7970 &key, 7971 sizeof(struct ixgbe_l2_tn_key)); 7972 node->pool = l2_tunnel->pool; 7973 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node); 7974 if (ret < 0) { 7975 rte_free(node); 7976 return ret; 7977 } 7978 } 7979 7980 switch (l2_tunnel->l2_tunnel_type) { 7981 case RTE_L2_TUNNEL_TYPE_E_TAG: 7982 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel); 7983 break; 7984 default: 7985 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7986 ret = -EINVAL; 7987 break; 7988 } 7989 7990 if ((!restore) && (ret < 0)) 7991 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 7992 7993 return ret; 7994 } 7995 7996 /* Delete l2 tunnel filter */ 7997 int 7998 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 7999 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8000 { 8001 int ret; 8002 struct ixgbe_l2_tn_info *l2_tn_info = 8003 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8004 struct ixgbe_l2_tn_key key; 8005 8006 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 8007 key.tn_id = l2_tunnel->tunnel_id; 8008 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 8009 if (ret < 0) 8010 return ret; 8011 8012 switch (l2_tunnel->l2_tunnel_type) { 8013 case RTE_L2_TUNNEL_TYPE_E_TAG: 8014 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel); 8015 break; 8016 default: 8017 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8018 ret = -EINVAL; 8019 break; 8020 } 8021 8022 return ret; 8023 } 8024 8025 /** 8026 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter. 8027 * @dev: pointer to rte_eth_dev structure 8028 * @filter_op:operation will be taken. 8029 * @arg: a pointer to specific structure corresponding to the filter_op 8030 */ 8031 static int 8032 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev, 8033 enum rte_filter_op filter_op, 8034 void *arg) 8035 { 8036 int ret; 8037 8038 if (filter_op == RTE_ETH_FILTER_NOP) 8039 return 0; 8040 8041 if (arg == NULL) { 8042 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 8043 filter_op); 8044 return -EINVAL; 8045 } 8046 8047 switch (filter_op) { 8048 case RTE_ETH_FILTER_ADD: 8049 ret = ixgbe_dev_l2_tunnel_filter_add 8050 (dev, 8051 (struct rte_eth_l2_tunnel_conf *)arg, 8052 FALSE); 8053 break; 8054 case RTE_ETH_FILTER_DELETE: 8055 ret = ixgbe_dev_l2_tunnel_filter_del 8056 (dev, 8057 (struct rte_eth_l2_tunnel_conf *)arg); 8058 break; 8059 default: 8060 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 8061 ret = -EINVAL; 8062 break; 8063 } 8064 return ret; 8065 } 8066 8067 static int 8068 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en) 8069 { 8070 int ret = 0; 8071 uint32_t ctrl; 8072 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8073 8074 if (hw->mac.type != ixgbe_mac_X550 && 8075 hw->mac.type != ixgbe_mac_X550EM_x && 8076 hw->mac.type != ixgbe_mac_X550EM_a) { 8077 return -ENOTSUP; 8078 } 8079 8080 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 8081 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 8082 if (en) 8083 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG; 8084 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 8085 8086 return ret; 8087 } 8088 8089 /* Enable l2 tunnel forwarding */ 8090 static int 8091 ixgbe_dev_l2_tunnel_forwarding_enable 8092 (struct rte_eth_dev *dev, 8093 enum rte_eth_tunnel_type l2_tunnel_type) 8094 { 8095 struct ixgbe_l2_tn_info *l2_tn_info = 8096 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8097 int ret = 0; 8098 8099 switch (l2_tunnel_type) { 8100 case RTE_L2_TUNNEL_TYPE_E_TAG: 8101 l2_tn_info->e_tag_fwd_en = TRUE; 8102 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1); 8103 break; 8104 default: 8105 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8106 ret = -EINVAL; 8107 break; 8108 } 8109 8110 return ret; 8111 } 8112 8113 /* Disable l2 tunnel forwarding */ 8114 static int 8115 ixgbe_dev_l2_tunnel_forwarding_disable 8116 (struct rte_eth_dev *dev, 8117 enum rte_eth_tunnel_type l2_tunnel_type) 8118 { 8119 struct ixgbe_l2_tn_info *l2_tn_info = 8120 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8121 int ret = 0; 8122 8123 switch (l2_tunnel_type) { 8124 case RTE_L2_TUNNEL_TYPE_E_TAG: 8125 l2_tn_info->e_tag_fwd_en = FALSE; 8126 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0); 8127 break; 8128 default: 8129 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8130 ret = -EINVAL; 8131 break; 8132 } 8133 8134 return ret; 8135 } 8136 8137 static int 8138 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev, 8139 struct rte_eth_l2_tunnel_conf *l2_tunnel, 8140 bool en) 8141 { 8142 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 8143 int ret = 0; 8144 uint32_t vmtir, vmvir; 8145 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8146 8147 if (l2_tunnel->vf_id >= pci_dev->max_vfs) { 8148 PMD_DRV_LOG(ERR, 8149 "VF id %u should be less than %u", 8150 l2_tunnel->vf_id, 8151 pci_dev->max_vfs); 8152 return -EINVAL; 8153 } 8154 8155 if (hw->mac.type != ixgbe_mac_X550 && 8156 hw->mac.type != ixgbe_mac_X550EM_x && 8157 hw->mac.type != ixgbe_mac_X550EM_a) { 8158 return -ENOTSUP; 8159 } 8160 8161 if (en) 8162 vmtir = l2_tunnel->tunnel_id; 8163 else 8164 vmtir = 0; 8165 8166 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir); 8167 8168 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id)); 8169 vmvir &= ~IXGBE_VMVIR_TAGA_MASK; 8170 if (en) 8171 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT; 8172 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir); 8173 8174 return ret; 8175 } 8176 8177 /* Enable l2 tunnel tag insertion */ 8178 static int 8179 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev, 8180 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8181 { 8182 int ret = 0; 8183 8184 switch (l2_tunnel->l2_tunnel_type) { 8185 case RTE_L2_TUNNEL_TYPE_E_TAG: 8186 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1); 8187 break; 8188 default: 8189 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8190 ret = -EINVAL; 8191 break; 8192 } 8193 8194 return ret; 8195 } 8196 8197 /* Disable l2 tunnel tag insertion */ 8198 static int 8199 ixgbe_dev_l2_tunnel_insertion_disable 8200 (struct rte_eth_dev *dev, 8201 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8202 { 8203 int ret = 0; 8204 8205 switch (l2_tunnel->l2_tunnel_type) { 8206 case RTE_L2_TUNNEL_TYPE_E_TAG: 8207 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0); 8208 break; 8209 default: 8210 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8211 ret = -EINVAL; 8212 break; 8213 } 8214 8215 return ret; 8216 } 8217 8218 static int 8219 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev, 8220 bool en) 8221 { 8222 int ret = 0; 8223 uint32_t qde; 8224 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8225 8226 if (hw->mac.type != ixgbe_mac_X550 && 8227 hw->mac.type != ixgbe_mac_X550EM_x && 8228 hw->mac.type != ixgbe_mac_X550EM_a) { 8229 return -ENOTSUP; 8230 } 8231 8232 qde = IXGBE_READ_REG(hw, IXGBE_QDE); 8233 if (en) 8234 qde |= IXGBE_QDE_STRIP_TAG; 8235 else 8236 qde &= ~IXGBE_QDE_STRIP_TAG; 8237 qde &= ~IXGBE_QDE_READ; 8238 qde |= IXGBE_QDE_WRITE; 8239 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde); 8240 8241 return ret; 8242 } 8243 8244 /* Enable l2 tunnel tag stripping */ 8245 static int 8246 ixgbe_dev_l2_tunnel_stripping_enable 8247 (struct rte_eth_dev *dev, 8248 enum rte_eth_tunnel_type l2_tunnel_type) 8249 { 8250 int ret = 0; 8251 8252 switch (l2_tunnel_type) { 8253 case RTE_L2_TUNNEL_TYPE_E_TAG: 8254 ret = ixgbe_e_tag_stripping_en_dis(dev, 1); 8255 break; 8256 default: 8257 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8258 ret = -EINVAL; 8259 break; 8260 } 8261 8262 return ret; 8263 } 8264 8265 /* Disable l2 tunnel tag stripping */ 8266 static int 8267 ixgbe_dev_l2_tunnel_stripping_disable 8268 (struct rte_eth_dev *dev, 8269 enum rte_eth_tunnel_type l2_tunnel_type) 8270 { 8271 int ret = 0; 8272 8273 switch (l2_tunnel_type) { 8274 case RTE_L2_TUNNEL_TYPE_E_TAG: 8275 ret = ixgbe_e_tag_stripping_en_dis(dev, 0); 8276 break; 8277 default: 8278 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8279 ret = -EINVAL; 8280 break; 8281 } 8282 8283 return ret; 8284 } 8285 8286 /* Enable/disable l2 tunnel offload functions */ 8287 static int 8288 ixgbe_dev_l2_tunnel_offload_set 8289 (struct rte_eth_dev *dev, 8290 struct rte_eth_l2_tunnel_conf *l2_tunnel, 8291 uint32_t mask, 8292 uint8_t en) 8293 { 8294 int ret = 0; 8295 8296 if (l2_tunnel == NULL) 8297 return -EINVAL; 8298 8299 ret = -EINVAL; 8300 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) { 8301 if (en) 8302 ret = ixgbe_dev_l2_tunnel_enable( 8303 dev, 8304 l2_tunnel->l2_tunnel_type); 8305 else 8306 ret = ixgbe_dev_l2_tunnel_disable( 8307 dev, 8308 l2_tunnel->l2_tunnel_type); 8309 } 8310 8311 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) { 8312 if (en) 8313 ret = ixgbe_dev_l2_tunnel_insertion_enable( 8314 dev, 8315 l2_tunnel); 8316 else 8317 ret = ixgbe_dev_l2_tunnel_insertion_disable( 8318 dev, 8319 l2_tunnel); 8320 } 8321 8322 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) { 8323 if (en) 8324 ret = ixgbe_dev_l2_tunnel_stripping_enable( 8325 dev, 8326 l2_tunnel->l2_tunnel_type); 8327 else 8328 ret = ixgbe_dev_l2_tunnel_stripping_disable( 8329 dev, 8330 l2_tunnel->l2_tunnel_type); 8331 } 8332 8333 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) { 8334 if (en) 8335 ret = ixgbe_dev_l2_tunnel_forwarding_enable( 8336 dev, 8337 l2_tunnel->l2_tunnel_type); 8338 else 8339 ret = ixgbe_dev_l2_tunnel_forwarding_disable( 8340 dev, 8341 l2_tunnel->l2_tunnel_type); 8342 } 8343 8344 return ret; 8345 } 8346 8347 static int 8348 ixgbe_update_vxlan_port(struct ixgbe_hw *hw, 8349 uint16_t port) 8350 { 8351 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port); 8352 IXGBE_WRITE_FLUSH(hw); 8353 8354 return 0; 8355 } 8356 8357 /* There's only one register for VxLAN UDP port. 8358 * So, we cannot add several ports. Will update it. 8359 */ 8360 static int 8361 ixgbe_add_vxlan_port(struct ixgbe_hw *hw, 8362 uint16_t port) 8363 { 8364 if (port == 0) { 8365 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 8366 return -EINVAL; 8367 } 8368 8369 return ixgbe_update_vxlan_port(hw, port); 8370 } 8371 8372 /* We cannot delete the VxLAN port. For there's a register for VxLAN 8373 * UDP port, it must have a value. 8374 * So, will reset it to the original value 0. 8375 */ 8376 static int 8377 ixgbe_del_vxlan_port(struct ixgbe_hw *hw, 8378 uint16_t port) 8379 { 8380 uint16_t cur_port; 8381 8382 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL); 8383 8384 if (cur_port != port) { 8385 PMD_DRV_LOG(ERR, "Port %u does not exist.", port); 8386 return -EINVAL; 8387 } 8388 8389 return ixgbe_update_vxlan_port(hw, 0); 8390 } 8391 8392 /* Add UDP tunneling port */ 8393 static int 8394 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 8395 struct rte_eth_udp_tunnel *udp_tunnel) 8396 { 8397 int ret = 0; 8398 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8399 8400 if (hw->mac.type != ixgbe_mac_X550 && 8401 hw->mac.type != ixgbe_mac_X550EM_x && 8402 hw->mac.type != ixgbe_mac_X550EM_a) { 8403 return -ENOTSUP; 8404 } 8405 8406 if (udp_tunnel == NULL) 8407 return -EINVAL; 8408 8409 switch (udp_tunnel->prot_type) { 8410 case RTE_TUNNEL_TYPE_VXLAN: 8411 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port); 8412 break; 8413 8414 case RTE_TUNNEL_TYPE_GENEVE: 8415 case RTE_TUNNEL_TYPE_TEREDO: 8416 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8417 ret = -EINVAL; 8418 break; 8419 8420 default: 8421 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8422 ret = -EINVAL; 8423 break; 8424 } 8425 8426 return ret; 8427 } 8428 8429 /* Remove UDP tunneling port */ 8430 static int 8431 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 8432 struct rte_eth_udp_tunnel *udp_tunnel) 8433 { 8434 int ret = 0; 8435 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8436 8437 if (hw->mac.type != ixgbe_mac_X550 && 8438 hw->mac.type != ixgbe_mac_X550EM_x && 8439 hw->mac.type != ixgbe_mac_X550EM_a) { 8440 return -ENOTSUP; 8441 } 8442 8443 if (udp_tunnel == NULL) 8444 return -EINVAL; 8445 8446 switch (udp_tunnel->prot_type) { 8447 case RTE_TUNNEL_TYPE_VXLAN: 8448 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port); 8449 break; 8450 case RTE_TUNNEL_TYPE_GENEVE: 8451 case RTE_TUNNEL_TYPE_TEREDO: 8452 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8453 ret = -EINVAL; 8454 break; 8455 default: 8456 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8457 ret = -EINVAL; 8458 break; 8459 } 8460 8461 return ret; 8462 } 8463 8464 static int 8465 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev) 8466 { 8467 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8468 int ret; 8469 8470 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) { 8471 case IXGBE_SUCCESS: 8472 ret = 0; 8473 break; 8474 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 8475 ret = -ENOTSUP; 8476 break; 8477 default: 8478 ret = -EAGAIN; 8479 break; 8480 } 8481 8482 return ret; 8483 } 8484 8485 static int 8486 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev) 8487 { 8488 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8489 int ret; 8490 8491 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) { 8492 case IXGBE_SUCCESS: 8493 ret = 0; 8494 break; 8495 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 8496 ret = -ENOTSUP; 8497 break; 8498 default: 8499 ret = -EAGAIN; 8500 break; 8501 } 8502 8503 return ret; 8504 } 8505 8506 static int 8507 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev) 8508 { 8509 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8510 int ret; 8511 int mode = IXGBEVF_XCAST_MODE_ALLMULTI; 8512 8513 switch (hw->mac.ops.update_xcast_mode(hw, mode)) { 8514 case IXGBE_SUCCESS: 8515 ret = 0; 8516 break; 8517 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 8518 ret = -ENOTSUP; 8519 break; 8520 default: 8521 ret = -EAGAIN; 8522 break; 8523 } 8524 8525 return ret; 8526 } 8527 8528 static int 8529 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev) 8530 { 8531 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8532 int ret; 8533 8534 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) { 8535 case IXGBE_SUCCESS: 8536 ret = 0; 8537 break; 8538 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 8539 ret = -ENOTSUP; 8540 break; 8541 default: 8542 ret = -EAGAIN; 8543 break; 8544 } 8545 8546 return ret; 8547 } 8548 8549 static void ixgbevf_mbx_process(struct rte_eth_dev *dev) 8550 { 8551 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8552 u32 in_msg = 0; 8553 8554 /* peek the message first */ 8555 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM); 8556 8557 /* PF reset VF event */ 8558 if (in_msg == IXGBE_PF_CONTROL_MSG) { 8559 /* dummy mbx read to ack pf */ 8560 if (ixgbe_read_mbx(hw, &in_msg, 1, 0)) 8561 return; 8562 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 8563 NULL); 8564 } 8565 } 8566 8567 static int 8568 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev) 8569 { 8570 uint32_t eicr; 8571 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8572 struct ixgbe_interrupt *intr = 8573 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8574 ixgbevf_intr_disable(dev); 8575 8576 /* read-on-clear nic registers here */ 8577 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR); 8578 intr->flags = 0; 8579 8580 /* only one misc vector supported - mailbox */ 8581 eicr &= IXGBE_VTEICR_MASK; 8582 if (eicr == IXGBE_MISC_VEC_ID) 8583 intr->flags |= IXGBE_FLAG_MAILBOX; 8584 8585 return 0; 8586 } 8587 8588 static int 8589 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev) 8590 { 8591 struct ixgbe_interrupt *intr = 8592 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8593 8594 if (intr->flags & IXGBE_FLAG_MAILBOX) { 8595 ixgbevf_mbx_process(dev); 8596 intr->flags &= ~IXGBE_FLAG_MAILBOX; 8597 } 8598 8599 ixgbevf_intr_enable(dev); 8600 8601 return 0; 8602 } 8603 8604 static void 8605 ixgbevf_dev_interrupt_handler(void *param) 8606 { 8607 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 8608 8609 ixgbevf_dev_interrupt_get_status(dev); 8610 ixgbevf_dev_interrupt_action(dev); 8611 } 8612 8613 /** 8614 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path 8615 * @hw: pointer to hardware structure 8616 * 8617 * Stops the transmit data path and waits for the HW to internally empty 8618 * the Tx security block 8619 **/ 8620 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw) 8621 { 8622 #define IXGBE_MAX_SECTX_POLL 40 8623 8624 int i; 8625 int sectxreg; 8626 8627 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8628 sectxreg |= IXGBE_SECTXCTRL_TX_DIS; 8629 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8630 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) { 8631 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT); 8632 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY) 8633 break; 8634 /* Use interrupt-safe sleep just in case */ 8635 usec_delay(1000); 8636 } 8637 8638 /* For informational purposes only */ 8639 if (i >= IXGBE_MAX_SECTX_POLL) 8640 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security " 8641 "path fully disabled. Continuing with init."); 8642 8643 return IXGBE_SUCCESS; 8644 } 8645 8646 /** 8647 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path 8648 * @hw: pointer to hardware structure 8649 * 8650 * Enables the transmit data path. 8651 **/ 8652 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw) 8653 { 8654 uint32_t sectxreg; 8655 8656 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8657 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS; 8658 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8659 IXGBE_WRITE_FLUSH(hw); 8660 8661 return IXGBE_SUCCESS; 8662 } 8663 8664 /* restore n-tuple filter */ 8665 static inline void 8666 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev) 8667 { 8668 struct ixgbe_filter_info *filter_info = 8669 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8670 struct ixgbe_5tuple_filter *node; 8671 8672 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) { 8673 ixgbe_inject_5tuple_filter(dev, node); 8674 } 8675 } 8676 8677 /* restore ethernet type filter */ 8678 static inline void 8679 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev) 8680 { 8681 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8682 struct ixgbe_filter_info *filter_info = 8683 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8684 int i; 8685 8686 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8687 if (filter_info->ethertype_mask & (1 << i)) { 8688 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 8689 filter_info->ethertype_filters[i].etqf); 8690 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 8691 filter_info->ethertype_filters[i].etqs); 8692 IXGBE_WRITE_FLUSH(hw); 8693 } 8694 } 8695 } 8696 8697 /* restore SYN filter */ 8698 static inline void 8699 ixgbe_syn_filter_restore(struct rte_eth_dev *dev) 8700 { 8701 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8702 struct ixgbe_filter_info *filter_info = 8703 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8704 uint32_t synqf; 8705 8706 synqf = filter_info->syn_info; 8707 8708 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 8709 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 8710 IXGBE_WRITE_FLUSH(hw); 8711 } 8712 } 8713 8714 /* restore L2 tunnel filter */ 8715 static inline void 8716 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev) 8717 { 8718 struct ixgbe_l2_tn_info *l2_tn_info = 8719 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8720 struct ixgbe_l2_tn_filter *node; 8721 struct rte_eth_l2_tunnel_conf l2_tn_conf; 8722 8723 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) { 8724 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type; 8725 l2_tn_conf.tunnel_id = node->key.tn_id; 8726 l2_tn_conf.pool = node->pool; 8727 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE); 8728 } 8729 } 8730 8731 /* restore rss filter */ 8732 static inline void 8733 ixgbe_rss_filter_restore(struct rte_eth_dev *dev) 8734 { 8735 struct ixgbe_filter_info *filter_info = 8736 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8737 8738 if (filter_info->rss_info.conf.queue_num) 8739 ixgbe_config_rss_filter(dev, 8740 &filter_info->rss_info, TRUE); 8741 } 8742 8743 static int 8744 ixgbe_filter_restore(struct rte_eth_dev *dev) 8745 { 8746 ixgbe_ntuple_filter_restore(dev); 8747 ixgbe_ethertype_filter_restore(dev); 8748 ixgbe_syn_filter_restore(dev); 8749 ixgbe_fdir_filter_restore(dev); 8750 ixgbe_l2_tn_filter_restore(dev); 8751 ixgbe_rss_filter_restore(dev); 8752 8753 return 0; 8754 } 8755 8756 static void 8757 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev) 8758 { 8759 struct ixgbe_l2_tn_info *l2_tn_info = 8760 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8761 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8762 8763 if (l2_tn_info->e_tag_en) 8764 (void)ixgbe_e_tag_enable(hw); 8765 8766 if (l2_tn_info->e_tag_fwd_en) 8767 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1); 8768 8769 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type); 8770 } 8771 8772 /* remove all the n-tuple filters */ 8773 void 8774 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev) 8775 { 8776 struct ixgbe_filter_info *filter_info = 8777 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8778 struct ixgbe_5tuple_filter *p_5tuple; 8779 8780 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) 8781 ixgbe_remove_5tuple_filter(dev, p_5tuple); 8782 } 8783 8784 /* remove all the ether type filters */ 8785 void 8786 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev) 8787 { 8788 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8789 struct ixgbe_filter_info *filter_info = 8790 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8791 int i; 8792 8793 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8794 if (filter_info->ethertype_mask & (1 << i) && 8795 !filter_info->ethertype_filters[i].conf) { 8796 (void)ixgbe_ethertype_filter_remove(filter_info, 8797 (uint8_t)i); 8798 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0); 8799 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0); 8800 IXGBE_WRITE_FLUSH(hw); 8801 } 8802 } 8803 } 8804 8805 /* remove the SYN filter */ 8806 void 8807 ixgbe_clear_syn_filter(struct rte_eth_dev *dev) 8808 { 8809 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8810 struct ixgbe_filter_info *filter_info = 8811 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8812 8813 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) { 8814 filter_info->syn_info = 0; 8815 8816 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0); 8817 IXGBE_WRITE_FLUSH(hw); 8818 } 8819 } 8820 8821 /* remove all the L2 tunnel filters */ 8822 int 8823 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev) 8824 { 8825 struct ixgbe_l2_tn_info *l2_tn_info = 8826 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8827 struct ixgbe_l2_tn_filter *l2_tn_filter; 8828 struct rte_eth_l2_tunnel_conf l2_tn_conf; 8829 int ret = 0; 8830 8831 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 8832 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type; 8833 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id; 8834 l2_tn_conf.pool = l2_tn_filter->pool; 8835 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf); 8836 if (ret < 0) 8837 return ret; 8838 } 8839 8840 return 0; 8841 } 8842 8843 void 8844 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev, 8845 struct ixgbe_macsec_setting *macsec_setting) 8846 { 8847 struct ixgbe_macsec_setting *macsec = 8848 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 8849 8850 macsec->offload_en = macsec_setting->offload_en; 8851 macsec->encrypt_en = macsec_setting->encrypt_en; 8852 macsec->replayprotect_en = macsec_setting->replayprotect_en; 8853 } 8854 8855 void 8856 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev) 8857 { 8858 struct ixgbe_macsec_setting *macsec = 8859 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 8860 8861 macsec->offload_en = 0; 8862 macsec->encrypt_en = 0; 8863 macsec->replayprotect_en = 0; 8864 } 8865 8866 void 8867 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev, 8868 struct ixgbe_macsec_setting *macsec_setting) 8869 { 8870 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8871 uint32_t ctrl; 8872 uint8_t en = macsec_setting->encrypt_en; 8873 uint8_t rp = macsec_setting->replayprotect_en; 8874 8875 /** 8876 * Workaround: 8877 * As no ixgbe_disable_sec_rx_path equivalent is 8878 * implemented for tx in the base code, and we are 8879 * not allowed to modify the base code in DPDK, so 8880 * just call the hand-written one directly for now. 8881 * The hardware support has been checked by 8882 * ixgbe_disable_sec_rx_path(). 8883 */ 8884 ixgbe_disable_sec_tx_path_generic(hw); 8885 8886 /* Enable Ethernet CRC (required by MACsec offload) */ 8887 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0); 8888 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP; 8889 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl); 8890 8891 /* Enable the TX and RX crypto engines */ 8892 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8893 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS; 8894 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl); 8895 8896 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 8897 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS; 8898 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl); 8899 8900 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 8901 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK; 8902 ctrl |= 0x3; 8903 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl); 8904 8905 /* Enable SA lookup */ 8906 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL); 8907 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK; 8908 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT : 8909 IXGBE_LSECTXCTRL_AUTH; 8910 ctrl |= IXGBE_LSECTXCTRL_AISCI; 8911 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK; 8912 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK; 8913 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl); 8914 8915 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL); 8916 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK; 8917 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT; 8918 ctrl &= ~IXGBE_LSECRXCTRL_PLSH; 8919 if (rp) 8920 ctrl |= IXGBE_LSECRXCTRL_RP; 8921 else 8922 ctrl &= ~IXGBE_LSECRXCTRL_RP; 8923 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl); 8924 8925 /* Start the data paths */ 8926 ixgbe_enable_sec_rx_path(hw); 8927 /** 8928 * Workaround: 8929 * As no ixgbe_enable_sec_rx_path equivalent is 8930 * implemented for tx in the base code, and we are 8931 * not allowed to modify the base code in DPDK, so 8932 * just call the hand-written one directly for now. 8933 */ 8934 ixgbe_enable_sec_tx_path_generic(hw); 8935 } 8936 8937 void 8938 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev) 8939 { 8940 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8941 uint32_t ctrl; 8942 8943 /** 8944 * Workaround: 8945 * As no ixgbe_disable_sec_rx_path equivalent is 8946 * implemented for tx in the base code, and we are 8947 * not allowed to modify the base code in DPDK, so 8948 * just call the hand-written one directly for now. 8949 * The hardware support has been checked by 8950 * ixgbe_disable_sec_rx_path(). 8951 */ 8952 ixgbe_disable_sec_tx_path_generic(hw); 8953 8954 /* Disable the TX and RX crypto engines */ 8955 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8956 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS; 8957 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl); 8958 8959 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 8960 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS; 8961 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl); 8962 8963 /* Disable SA lookup */ 8964 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL); 8965 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK; 8966 ctrl |= IXGBE_LSECTXCTRL_DISABLE; 8967 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl); 8968 8969 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL); 8970 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK; 8971 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT; 8972 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl); 8973 8974 /* Start the data paths */ 8975 ixgbe_enable_sec_rx_path(hw); 8976 /** 8977 * Workaround: 8978 * As no ixgbe_enable_sec_rx_path equivalent is 8979 * implemented for tx in the base code, and we are 8980 * not allowed to modify the base code in DPDK, so 8981 * just call the hand-written one directly for now. 8982 */ 8983 ixgbe_enable_sec_tx_path_generic(hw); 8984 } 8985 8986 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd); 8987 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map); 8988 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 8989 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd); 8990 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map); 8991 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci"); 8992 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf, 8993 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>"); 8994 8995 RTE_INIT(ixgbe_init_log) 8996 { 8997 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init"); 8998 if (ixgbe_logtype_init >= 0) 8999 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE); 9000 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver"); 9001 if (ixgbe_logtype_driver >= 0) 9002 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE); 9003 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX 9004 ixgbe_logtype_rx = rte_log_register("pmd.net.ixgbe.rx"); 9005 if (ixgbe_logtype_rx >= 0) 9006 rte_log_set_level(ixgbe_logtype_rx, RTE_LOG_DEBUG); 9007 #endif 9008 9009 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX 9010 ixgbe_logtype_tx = rte_log_register("pmd.net.ixgbe.tx"); 9011 if (ixgbe_logtype_tx >= 0) 9012 rte_log_set_level(ixgbe_logtype_tx, RTE_LOG_DEBUG); 9013 #endif 9014 9015 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE 9016 ixgbe_logtype_tx_free = rte_log_register("pmd.net.ixgbe.tx_free"); 9017 if (ixgbe_logtype_tx_free >= 0) 9018 rte_log_set_level(ixgbe_logtype_tx_free, RTE_LOG_DEBUG); 9019 #endif 9020 } 9021