1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <inttypes.h> 13 #include <netinet/in.h> 14 #include <rte_string_fns.h> 15 #include <rte_byteorder.h> 16 #include <rte_common.h> 17 #include <rte_cycles.h> 18 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_bus_pci.h> 24 #include <rte_branch_prediction.h> 25 #include <rte_memory.h> 26 #include <rte_kvargs.h> 27 #include <rte_eal.h> 28 #include <rte_alarm.h> 29 #include <rte_ether.h> 30 #include <rte_ethdev_driver.h> 31 #include <rte_ethdev_pci.h> 32 #include <rte_malloc.h> 33 #include <rte_random.h> 34 #include <rte_dev.h> 35 #include <rte_hash_crc.h> 36 #ifdef RTE_LIBRTE_SECURITY 37 #include <rte_security_driver.h> 38 #endif 39 40 #include "ixgbe_logs.h" 41 #include "base/ixgbe_api.h" 42 #include "base/ixgbe_vf.h" 43 #include "base/ixgbe_common.h" 44 #include "ixgbe_ethdev.h" 45 #include "ixgbe_bypass.h" 46 #include "ixgbe_rxtx.h" 47 #include "base/ixgbe_type.h" 48 #include "base/ixgbe_phy.h" 49 #include "ixgbe_regs.h" 50 51 /* 52 * High threshold controlling when to start sending XOFF frames. Must be at 53 * least 8 bytes less than receive packet buffer size. This value is in units 54 * of 1024 bytes. 55 */ 56 #define IXGBE_FC_HI 0x80 57 58 /* 59 * Low threshold controlling when to start sending XON frames. This value is 60 * in units of 1024 bytes. 61 */ 62 #define IXGBE_FC_LO 0x40 63 64 /* Timer value included in XOFF frames. */ 65 #define IXGBE_FC_PAUSE 0x680 66 67 /*Default value of Max Rx Queue*/ 68 #define IXGBE_MAX_RX_QUEUE_NUM 128 69 70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */ 71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */ 72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */ 73 74 #define IXGBE_MMW_SIZE_DEFAULT 0x4 75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14 76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */ 77 78 /* 79 * Default values for RX/TX configuration 80 */ 81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32 82 #define IXGBE_DEFAULT_RX_PTHRESH 8 83 #define IXGBE_DEFAULT_RX_HTHRESH 8 84 #define IXGBE_DEFAULT_RX_WTHRESH 0 85 86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32 87 #define IXGBE_DEFAULT_TX_PTHRESH 32 88 #define IXGBE_DEFAULT_TX_HTHRESH 0 89 #define IXGBE_DEFAULT_TX_WTHRESH 0 90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32 91 92 /* Bit shift and mask */ 93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2) 94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t) 95 #define IXGBE_8_BIT_WIDTH CHAR_BIT 96 #define IXGBE_8_BIT_MASK UINT8_MAX 97 98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */ 99 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0])) 101 102 /* Additional timesync values. */ 103 #define NSEC_PER_SEC 1000000000L 104 #define IXGBE_INCVAL_10GB 0x66666666 105 #define IXGBE_INCVAL_1GB 0x40000000 106 #define IXGBE_INCVAL_100 0x50000000 107 #define IXGBE_INCVAL_SHIFT_10GB 28 108 #define IXGBE_INCVAL_SHIFT_1GB 24 109 #define IXGBE_INCVAL_SHIFT_100 21 110 #define IXGBE_INCVAL_SHIFT_82599 7 111 #define IXGBE_INCPER_SHIFT_82599 24 112 113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL 114 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000 117 #define IXGBE_ETAG_ETYPE 0x00005084 118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff 119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000 120 #define IXGBE_RAH_ADTYPE 0x40000000 121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff 122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */ 125 #define IXGBE_QDE_STRIP_TAG 0x00000004 126 #define IXGBE_VTEICR_MASK 0x07 127 128 #define IXGBE_EXVET_VET_EXT_SHIFT 16 129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000 130 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk" 132 133 static const char * const ixgbevf_valid_arguments[] = { 134 IXGBEVF_DEVARG_PFLINK_FULLCHK, 135 NULL 136 }; 137 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev); 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev); 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev); 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev); 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev); 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev); 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev); 146 static int ixgbe_dev_start(struct rte_eth_dev *dev); 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev); 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev); 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev); 150 static int ixgbe_dev_close(struct rte_eth_dev *dev); 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev); 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev, 157 int wait_to_complete); 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev, 159 struct rte_eth_stats *stats); 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev, 161 struct rte_eth_xstat *xstats, unsigned n); 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, 163 struct rte_eth_xstat *xstats, unsigned n); 164 static int 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 166 uint64_t *values, unsigned int n); 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev); 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev); 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 170 struct rte_eth_xstat_name *xstats_names, 171 unsigned int size); 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev, 173 struct rte_eth_xstat_name *xstats_names, unsigned limit); 174 static int ixgbe_dev_xstats_get_names_by_id( 175 struct rte_eth_dev *dev, 176 struct rte_eth_xstat_name *xstats_names, 177 const uint64_t *ids, 178 unsigned int limit); 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 180 uint16_t queue_id, 181 uint8_t stat_idx, 182 uint8_t is_rx); 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 184 size_t fw_size); 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev, 186 struct rte_eth_dev_info *dev_info); 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev, 189 struct rte_eth_dev_info *dev_info); 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 191 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev, 193 uint16_t vlan_id, int on); 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 195 enum rte_vlan_type vlan_type, 196 uint16_t tpid_id); 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, 198 uint16_t queue, bool on); 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, 200 int on); 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, 202 int mask); 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask); 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask); 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue); 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue); 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev); 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev); 209 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev); 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev); 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, 213 struct rte_eth_fc_conf *fc_conf); 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, 215 struct rte_eth_fc_conf *fc_conf); 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 217 struct rte_eth_pfc_conf *pfc_conf); 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 219 struct rte_eth_rss_reta_entry64 *reta_conf, 220 uint16_t reta_size); 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 222 struct rte_eth_rss_reta_entry64 *reta_conf, 223 uint16_t reta_size); 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev); 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev); 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev); 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev); 230 static void ixgbe_dev_interrupt_handler(void *param); 231 static void ixgbe_dev_interrupt_delayed_handler(void *param); 232 static void *ixgbe_dev_setup_link_thread_handler(void *param); 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, 234 uint32_t timeout_ms); 235 236 static int ixgbe_add_rar(struct rte_eth_dev *dev, 237 struct rte_ether_addr *mac_addr, 238 uint32_t index, uint32_t pool); 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index); 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, 241 struct rte_ether_addr *mac_addr); 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config); 243 static bool is_device_supported(struct rte_eth_dev *dev, 244 struct rte_pci_driver *drv); 245 246 /* For Virtual Function support */ 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev); 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev); 249 static int ixgbevf_dev_configure(struct rte_eth_dev *dev); 250 static int ixgbevf_dev_start(struct rte_eth_dev *dev); 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev, 252 int wait_to_complete); 253 static void ixgbevf_dev_stop(struct rte_eth_dev *dev); 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev); 255 static int ixgbevf_dev_reset(struct rte_eth_dev *dev); 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev); 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev); 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev, 259 struct rte_eth_stats *stats); 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev); 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, 262 uint16_t vlan_id, int on); 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, 264 uint16_t queue, int on); 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask); 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask); 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on); 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 269 uint16_t queue_id); 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 271 uint16_t queue_id); 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 273 uint8_t queue, uint8_t msix_vector); 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev); 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev); 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev); 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev); 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev); 279 280 /* For Eth VMDQ APIs support */ 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct 282 rte_ether_addr * mac_addr, uint8_t on); 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on); 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 285 struct rte_eth_mirror_conf *mirror_conf, 286 uint8_t rule_id, uint8_t on); 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, 288 uint8_t rule_id); 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 290 uint16_t queue_id); 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 292 uint16_t queue_id); 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 294 uint8_t queue, uint8_t msix_vector); 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev); 296 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev, 298 struct rte_ether_addr *mac_addr, 299 uint32_t index, uint32_t pool); 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index); 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 302 struct rte_ether_addr *mac_addr); 303 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev, 304 struct rte_eth_syn_filter *filter); 305 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev, 306 enum rte_filter_op filter_op, 307 void *arg); 308 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 309 struct ixgbe_5tuple_filter *filter); 310 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 311 struct ixgbe_5tuple_filter *filter); 312 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev, 313 enum rte_filter_op filter_op, 314 void *arg); 315 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev, 316 struct rte_eth_ntuple_filter *filter); 317 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev, 318 enum rte_filter_op filter_op, 319 void *arg); 320 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, 321 struct rte_eth_ethertype_filter *filter); 322 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 323 enum rte_filter_type filter_type, 324 enum rte_filter_op filter_op, 325 void *arg); 326 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 327 328 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 329 struct rte_ether_addr *mc_addr_set, 330 uint32_t nb_mc_addr); 331 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 332 struct rte_eth_dcb_info *dcb_info); 333 334 static int ixgbe_get_reg_length(struct rte_eth_dev *dev); 335 static int ixgbe_get_regs(struct rte_eth_dev *dev, 336 struct rte_dev_reg_info *regs); 337 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev); 338 static int ixgbe_get_eeprom(struct rte_eth_dev *dev, 339 struct rte_dev_eeprom_info *eeprom); 340 static int ixgbe_set_eeprom(struct rte_eth_dev *dev, 341 struct rte_dev_eeprom_info *eeprom); 342 343 static int ixgbe_get_module_info(struct rte_eth_dev *dev, 344 struct rte_eth_dev_module_info *modinfo); 345 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 346 struct rte_dev_eeprom_info *info); 347 348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev); 349 static int ixgbevf_get_regs(struct rte_eth_dev *dev, 350 struct rte_dev_reg_info *regs); 351 352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev); 353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev); 354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 355 struct timespec *timestamp, 356 uint32_t flags); 357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 358 struct timespec *timestamp); 359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev, 361 struct timespec *timestamp); 362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev, 363 const struct timespec *timestamp); 364 static void ixgbevf_dev_interrupt_handler(void *param); 365 366 static int ixgbe_dev_l2_tunnel_eth_type_conf 367 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel); 368 static int ixgbe_dev_l2_tunnel_offload_set 369 (struct rte_eth_dev *dev, 370 struct rte_eth_l2_tunnel_conf *l2_tunnel, 371 uint32_t mask, 372 uint8_t en); 373 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev, 374 enum rte_filter_op filter_op, 375 void *arg); 376 377 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 378 struct rte_eth_udp_tunnel *udp_tunnel); 379 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 380 struct rte_eth_udp_tunnel *udp_tunnel); 381 static int ixgbe_filter_restore(struct rte_eth_dev *dev); 382 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev); 383 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw); 384 385 /* 386 * Define VF Stats MACRO for Non "cleared on read" register 387 */ 388 #define UPDATE_VF_STAT(reg, last, cur) \ 389 { \ 390 uint32_t latest = IXGBE_READ_REG(hw, reg); \ 391 cur += (latest - last) & UINT_MAX; \ 392 last = latest; \ 393 } 394 395 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \ 396 { \ 397 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \ 398 u64 new_msb = IXGBE_READ_REG(hw, msb); \ 399 u64 latest = ((new_msb << 32) | new_lsb); \ 400 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \ 401 last = latest; \ 402 } 403 404 #define IXGBE_SET_HWSTRIP(h, q) do {\ 405 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 406 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 407 (h)->bitmap[idx] |= 1 << bit;\ 408 } while (0) 409 410 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\ 411 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 412 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 413 (h)->bitmap[idx] &= ~(1 << bit);\ 414 } while (0) 415 416 #define IXGBE_GET_HWSTRIP(h, q, r) do {\ 417 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 418 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 419 (r) = (h)->bitmap[idx] >> bit & 1;\ 420 } while (0) 421 422 /* 423 * The set of PCI devices this driver supports 424 */ 425 static const struct rte_pci_id pci_id_ixgbe_map[] = { 426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) }, 427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) }, 428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) }, 429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) }, 430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) }, 431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) }, 432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) }, 433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) }, 434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) }, 435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) }, 436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) }, 437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) }, 438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) }, 439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) }, 440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) }, 441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) }, 442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) }, 443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) }, 444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) }, 445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) }, 446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) }, 447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) }, 448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) }, 449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) }, 450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) }, 451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) }, 452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) }, 453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) }, 454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) }, 455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) }, 456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) }, 457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) }, 458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) }, 459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) }, 460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) }, 461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) }, 462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) }, 463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) }, 464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) }, 465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) }, 466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) }, 467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) }, 468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) }, 469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) }, 470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) }, 471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) }, 472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) }, 473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) }, 474 #ifdef RTE_LIBRTE_IXGBE_BYPASS 475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) }, 476 #endif 477 { .vendor_id = 0, /* sentinel */ }, 478 }; 479 480 /* 481 * The set of PCI devices this driver supports (for 82599 VF) 482 */ 483 static const struct rte_pci_id pci_id_ixgbevf_map[] = { 484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) }, 485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) }, 486 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) }, 487 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) }, 488 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) }, 489 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) }, 490 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) }, 491 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) }, 492 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) }, 493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) }, 494 { .vendor_id = 0, /* sentinel */ }, 495 }; 496 497 static const struct rte_eth_desc_lim rx_desc_lim = { 498 .nb_max = IXGBE_MAX_RING_DESC, 499 .nb_min = IXGBE_MIN_RING_DESC, 500 .nb_align = IXGBE_RXD_ALIGN, 501 }; 502 503 static const struct rte_eth_desc_lim tx_desc_lim = { 504 .nb_max = IXGBE_MAX_RING_DESC, 505 .nb_min = IXGBE_MIN_RING_DESC, 506 .nb_align = IXGBE_TXD_ALIGN, 507 .nb_seg_max = IXGBE_TX_MAX_SEG, 508 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG, 509 }; 510 511 static const struct eth_dev_ops ixgbe_eth_dev_ops = { 512 .dev_configure = ixgbe_dev_configure, 513 .dev_start = ixgbe_dev_start, 514 .dev_stop = ixgbe_dev_stop, 515 .dev_set_link_up = ixgbe_dev_set_link_up, 516 .dev_set_link_down = ixgbe_dev_set_link_down, 517 .dev_close = ixgbe_dev_close, 518 .dev_reset = ixgbe_dev_reset, 519 .promiscuous_enable = ixgbe_dev_promiscuous_enable, 520 .promiscuous_disable = ixgbe_dev_promiscuous_disable, 521 .allmulticast_enable = ixgbe_dev_allmulticast_enable, 522 .allmulticast_disable = ixgbe_dev_allmulticast_disable, 523 .link_update = ixgbe_dev_link_update, 524 .stats_get = ixgbe_dev_stats_get, 525 .xstats_get = ixgbe_dev_xstats_get, 526 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id, 527 .stats_reset = ixgbe_dev_stats_reset, 528 .xstats_reset = ixgbe_dev_xstats_reset, 529 .xstats_get_names = ixgbe_dev_xstats_get_names, 530 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id, 531 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set, 532 .fw_version_get = ixgbe_fw_version_get, 533 .dev_infos_get = ixgbe_dev_info_get, 534 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 535 .mtu_set = ixgbe_dev_mtu_set, 536 .vlan_filter_set = ixgbe_vlan_filter_set, 537 .vlan_tpid_set = ixgbe_vlan_tpid_set, 538 .vlan_offload_set = ixgbe_vlan_offload_set, 539 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set, 540 .rx_queue_start = ixgbe_dev_rx_queue_start, 541 .rx_queue_stop = ixgbe_dev_rx_queue_stop, 542 .tx_queue_start = ixgbe_dev_tx_queue_start, 543 .tx_queue_stop = ixgbe_dev_tx_queue_stop, 544 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 545 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable, 546 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable, 547 .rx_queue_release = ixgbe_dev_rx_queue_release, 548 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 549 .tx_queue_release = ixgbe_dev_tx_queue_release, 550 .dev_led_on = ixgbe_dev_led_on, 551 .dev_led_off = ixgbe_dev_led_off, 552 .flow_ctrl_get = ixgbe_flow_ctrl_get, 553 .flow_ctrl_set = ixgbe_flow_ctrl_set, 554 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set, 555 .mac_addr_add = ixgbe_add_rar, 556 .mac_addr_remove = ixgbe_remove_rar, 557 .mac_addr_set = ixgbe_set_default_mac_addr, 558 .uc_hash_table_set = ixgbe_uc_hash_table_set, 559 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set, 560 .mirror_rule_set = ixgbe_mirror_rule_set, 561 .mirror_rule_reset = ixgbe_mirror_rule_reset, 562 .set_queue_rate_limit = ixgbe_set_queue_rate_limit, 563 .reta_update = ixgbe_dev_rss_reta_update, 564 .reta_query = ixgbe_dev_rss_reta_query, 565 .rss_hash_update = ixgbe_dev_rss_hash_update, 566 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 567 .filter_ctrl = ixgbe_dev_filter_ctrl, 568 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 569 .rxq_info_get = ixgbe_rxq_info_get, 570 .txq_info_get = ixgbe_txq_info_get, 571 .timesync_enable = ixgbe_timesync_enable, 572 .timesync_disable = ixgbe_timesync_disable, 573 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp, 574 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp, 575 .get_reg = ixgbe_get_regs, 576 .get_eeprom_length = ixgbe_get_eeprom_length, 577 .get_eeprom = ixgbe_get_eeprom, 578 .set_eeprom = ixgbe_set_eeprom, 579 .get_module_info = ixgbe_get_module_info, 580 .get_module_eeprom = ixgbe_get_module_eeprom, 581 .get_dcb_info = ixgbe_dev_get_dcb_info, 582 .timesync_adjust_time = ixgbe_timesync_adjust_time, 583 .timesync_read_time = ixgbe_timesync_read_time, 584 .timesync_write_time = ixgbe_timesync_write_time, 585 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf, 586 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set, 587 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add, 588 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del, 589 .tm_ops_get = ixgbe_tm_ops_get, 590 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup, 591 }; 592 593 /* 594 * dev_ops for virtual function, bare necessities for basic vf 595 * operation have been implemented 596 */ 597 static const struct eth_dev_ops ixgbevf_eth_dev_ops = { 598 .dev_configure = ixgbevf_dev_configure, 599 .dev_start = ixgbevf_dev_start, 600 .dev_stop = ixgbevf_dev_stop, 601 .link_update = ixgbevf_dev_link_update, 602 .stats_get = ixgbevf_dev_stats_get, 603 .xstats_get = ixgbevf_dev_xstats_get, 604 .stats_reset = ixgbevf_dev_stats_reset, 605 .xstats_reset = ixgbevf_dev_stats_reset, 606 .xstats_get_names = ixgbevf_dev_xstats_get_names, 607 .dev_close = ixgbevf_dev_close, 608 .dev_reset = ixgbevf_dev_reset, 609 .promiscuous_enable = ixgbevf_dev_promiscuous_enable, 610 .promiscuous_disable = ixgbevf_dev_promiscuous_disable, 611 .allmulticast_enable = ixgbevf_dev_allmulticast_enable, 612 .allmulticast_disable = ixgbevf_dev_allmulticast_disable, 613 .dev_infos_get = ixgbevf_dev_info_get, 614 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 615 .mtu_set = ixgbevf_dev_set_mtu, 616 .vlan_filter_set = ixgbevf_vlan_filter_set, 617 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set, 618 .vlan_offload_set = ixgbevf_vlan_offload_set, 619 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 620 .rx_queue_release = ixgbe_dev_rx_queue_release, 621 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 622 .tx_queue_release = ixgbe_dev_tx_queue_release, 623 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable, 624 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable, 625 .mac_addr_add = ixgbevf_add_mac_addr, 626 .mac_addr_remove = ixgbevf_remove_mac_addr, 627 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 628 .rxq_info_get = ixgbe_rxq_info_get, 629 .txq_info_get = ixgbe_txq_info_get, 630 .mac_addr_set = ixgbevf_set_default_mac_addr, 631 .get_reg = ixgbevf_get_regs, 632 .reta_update = ixgbe_dev_rss_reta_update, 633 .reta_query = ixgbe_dev_rss_reta_query, 634 .rss_hash_update = ixgbe_dev_rss_hash_update, 635 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 636 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup, 637 }; 638 639 /* store statistics names and its offset in stats structure */ 640 struct rte_ixgbe_xstats_name_off { 641 char name[RTE_ETH_XSTATS_NAME_SIZE]; 642 unsigned offset; 643 }; 644 645 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = { 646 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)}, 647 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)}, 648 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)}, 649 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)}, 650 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)}, 651 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)}, 652 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)}, 653 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)}, 654 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)}, 655 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)}, 656 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)}, 657 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)}, 658 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)}, 659 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)}, 660 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 661 prc1023)}, 662 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 663 prc1522)}, 664 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)}, 665 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)}, 666 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)}, 667 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)}, 668 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)}, 669 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)}, 670 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)}, 671 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)}, 672 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)}, 673 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)}, 674 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)}, 675 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)}, 676 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)}, 677 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)}, 678 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)}, 679 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)}, 680 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 681 ptc1023)}, 682 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 683 ptc1522)}, 684 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)}, 685 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)}, 686 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)}, 687 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)}, 688 689 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats, 690 fdirustat_add)}, 691 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats, 692 fdirustat_remove)}, 693 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats, 694 fdirfstat_fadd)}, 695 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats, 696 fdirfstat_fremove)}, 697 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats, 698 fdirmatch)}, 699 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats, 700 fdirmiss)}, 701 702 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)}, 703 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)}, 704 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, 705 fclast)}, 706 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)}, 707 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)}, 708 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)}, 709 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)}, 710 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats, 711 fcoe_noddp)}, 712 {"rx_fcoe_no_direct_data_placement_ext_buff", 713 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)}, 714 715 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 716 lxontxc)}, 717 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 718 lxonrxc)}, 719 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 720 lxofftxc)}, 721 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 722 lxoffrxc)}, 723 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)}, 724 }; 725 726 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \ 727 sizeof(rte_ixgbe_stats_strings[0])) 728 729 /* MACsec statistics */ 730 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = { 731 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 732 out_pkts_untagged)}, 733 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats, 734 out_pkts_encrypted)}, 735 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats, 736 out_pkts_protected)}, 737 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats, 738 out_octets_encrypted)}, 739 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats, 740 out_octets_protected)}, 741 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 742 in_pkts_untagged)}, 743 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats, 744 in_pkts_badtag)}, 745 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats, 746 in_pkts_nosci)}, 747 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats, 748 in_pkts_unknownsci)}, 749 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats, 750 in_octets_decrypted)}, 751 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats, 752 in_octets_validated)}, 753 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats, 754 in_pkts_unchecked)}, 755 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats, 756 in_pkts_delayed)}, 757 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats, 758 in_pkts_late)}, 759 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats, 760 in_pkts_ok)}, 761 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats, 762 in_pkts_invalid)}, 763 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats, 764 in_pkts_notvalid)}, 765 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats, 766 in_pkts_unusedsa)}, 767 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats, 768 in_pkts_notusingsa)}, 769 }; 770 771 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \ 772 sizeof(rte_ixgbe_macsec_strings[0])) 773 774 /* Per-queue statistics */ 775 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = { 776 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)}, 777 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)}, 778 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)}, 779 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)}, 780 }; 781 782 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \ 783 sizeof(rte_ixgbe_rxq_strings[0])) 784 #define IXGBE_NB_RXQ_PRIO_VALUES 8 785 786 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = { 787 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)}, 788 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)}, 789 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats, 790 pxon2offc)}, 791 }; 792 793 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \ 794 sizeof(rte_ixgbe_txq_strings[0])) 795 #define IXGBE_NB_TXQ_PRIO_VALUES 8 796 797 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = { 798 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)}, 799 }; 800 801 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \ 802 sizeof(rte_ixgbevf_stats_strings[0])) 803 804 /* 805 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h. 806 */ 807 static inline int 808 ixgbe_is_sfp(struct ixgbe_hw *hw) 809 { 810 switch (hw->phy.type) { 811 case ixgbe_phy_sfp_avago: 812 case ixgbe_phy_sfp_ftl: 813 case ixgbe_phy_sfp_intel: 814 case ixgbe_phy_sfp_unknown: 815 case ixgbe_phy_sfp_passive_tyco: 816 case ixgbe_phy_sfp_passive_unknown: 817 return 1; 818 default: 819 return 0; 820 } 821 } 822 823 static inline int32_t 824 ixgbe_pf_reset_hw(struct ixgbe_hw *hw) 825 { 826 uint32_t ctrl_ext; 827 int32_t status; 828 829 status = ixgbe_reset_hw(hw); 830 831 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 832 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 833 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 834 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 835 IXGBE_WRITE_FLUSH(hw); 836 837 if (status == IXGBE_ERR_SFP_NOT_PRESENT) 838 status = IXGBE_SUCCESS; 839 return status; 840 } 841 842 static inline void 843 ixgbe_enable_intr(struct rte_eth_dev *dev) 844 { 845 struct ixgbe_interrupt *intr = 846 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 847 struct ixgbe_hw *hw = 848 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 849 850 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask); 851 IXGBE_WRITE_FLUSH(hw); 852 } 853 854 /* 855 * This function is based on ixgbe_disable_intr() in base/ixgbe.h. 856 */ 857 static void 858 ixgbe_disable_intr(struct ixgbe_hw *hw) 859 { 860 PMD_INIT_FUNC_TRACE(); 861 862 if (hw->mac.type == ixgbe_mac_82598EB) { 863 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0); 864 } else { 865 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000); 866 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0); 867 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0); 868 } 869 IXGBE_WRITE_FLUSH(hw); 870 } 871 872 /* 873 * This function resets queue statistics mapping registers. 874 * From Niantic datasheet, Initialization of Statistics section: 875 * "...if software requires the queue counters, the RQSMR and TQSM registers 876 * must be re-programmed following a device reset. 877 */ 878 static void 879 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw) 880 { 881 uint32_t i; 882 883 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) { 884 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0); 885 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0); 886 } 887 } 888 889 890 static int 891 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 892 uint16_t queue_id, 893 uint8_t stat_idx, 894 uint8_t is_rx) 895 { 896 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8 897 #define NB_QMAP_FIELDS_PER_QSM_REG 4 898 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f 899 900 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 901 struct ixgbe_stat_mapping_registers *stat_mappings = 902 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private); 903 uint32_t qsmr_mask = 0; 904 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK; 905 uint32_t q_map; 906 uint8_t n, offset; 907 908 if ((hw->mac.type != ixgbe_mac_82599EB) && 909 (hw->mac.type != ixgbe_mac_X540) && 910 (hw->mac.type != ixgbe_mac_X550) && 911 (hw->mac.type != ixgbe_mac_X550EM_x) && 912 (hw->mac.type != ixgbe_mac_X550EM_a)) 913 return -ENOSYS; 914 915 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d", 916 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 917 queue_id, stat_idx); 918 919 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG); 920 if (n >= IXGBE_NB_STAT_MAPPING_REGS) { 921 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded"); 922 return -EIO; 923 } 924 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG); 925 926 /* Now clear any previous stat_idx set */ 927 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 928 if (!is_rx) 929 stat_mappings->tqsm[n] &= ~clearing_mask; 930 else 931 stat_mappings->rqsmr[n] &= ~clearing_mask; 932 933 q_map = (uint32_t)stat_idx; 934 q_map &= QMAP_FIELD_RESERVED_BITS_MASK; 935 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 936 if (!is_rx) 937 stat_mappings->tqsm[n] |= qsmr_mask; 938 else 939 stat_mappings->rqsmr[n] |= qsmr_mask; 940 941 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d", 942 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 943 queue_id, stat_idx); 944 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n, 945 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]); 946 947 /* Now write the mapping in the appropriate register */ 948 if (is_rx) { 949 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d", 950 stat_mappings->rqsmr[n], n); 951 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]); 952 } else { 953 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d", 954 stat_mappings->tqsm[n], n); 955 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]); 956 } 957 return 0; 958 } 959 960 static void 961 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev) 962 { 963 struct ixgbe_stat_mapping_registers *stat_mappings = 964 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private); 965 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 966 int i; 967 968 /* write whatever was in stat mapping table to the NIC */ 969 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) { 970 /* rx */ 971 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]); 972 973 /* tx */ 974 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]); 975 } 976 } 977 978 static void 979 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config) 980 { 981 uint8_t i; 982 struct ixgbe_dcb_tc_config *tc; 983 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS; 984 985 dcb_config->num_tcs.pg_tcs = dcb_max_tc; 986 dcb_config->num_tcs.pfc_tcs = dcb_max_tc; 987 for (i = 0; i < dcb_max_tc; i++) { 988 tc = &dcb_config->tc_config[i]; 989 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i; 990 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 991 (uint8_t)(100/dcb_max_tc + (i & 1)); 992 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i; 993 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 994 (uint8_t)(100/dcb_max_tc + (i & 1)); 995 tc->pfc = ixgbe_dcb_pfc_disabled; 996 } 997 998 /* Initialize default user to priority mapping, UPx->TC0 */ 999 tc = &dcb_config->tc_config[0]; 1000 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 1001 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 1002 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) { 1003 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100; 1004 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100; 1005 } 1006 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal; 1007 dcb_config->pfc_mode_enable = false; 1008 dcb_config->vt_mode = true; 1009 dcb_config->round_robin_enable = false; 1010 /* support all DCB capabilities in 82599 */ 1011 dcb_config->support.capabilities = 0xFF; 1012 1013 /*we only support 4 Tcs for X540, X550 */ 1014 if (hw->mac.type == ixgbe_mac_X540 || 1015 hw->mac.type == ixgbe_mac_X550 || 1016 hw->mac.type == ixgbe_mac_X550EM_x || 1017 hw->mac.type == ixgbe_mac_X550EM_a) { 1018 dcb_config->num_tcs.pg_tcs = 4; 1019 dcb_config->num_tcs.pfc_tcs = 4; 1020 } 1021 } 1022 1023 /* 1024 * Ensure that all locks are released before first NVM or PHY access 1025 */ 1026 static void 1027 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw) 1028 { 1029 uint16_t mask; 1030 1031 /* 1032 * Phy lock should not fail in this early stage. If this is the case, 1033 * it is due to an improper exit of the application. 1034 * So force the release of the faulty lock. Release of common lock 1035 * is done automatically by swfw_sync function. 1036 */ 1037 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func; 1038 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1039 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func); 1040 } 1041 ixgbe_release_swfw_semaphore(hw, mask); 1042 1043 /* 1044 * These ones are more tricky since they are common to all ports; but 1045 * swfw_sync retries last long enough (1s) to be almost sure that if 1046 * lock can not be taken it is due to an improper lock of the 1047 * semaphore. 1048 */ 1049 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM; 1050 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1051 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 1052 } 1053 ixgbe_release_swfw_semaphore(hw, mask); 1054 } 1055 1056 /* 1057 * This function is based on code in ixgbe_attach() in base/ixgbe.c. 1058 * It returns 0 on success. 1059 */ 1060 static int 1061 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) 1062 { 1063 struct ixgbe_adapter *ad = eth_dev->data->dev_private; 1064 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1065 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1066 struct ixgbe_hw *hw = 1067 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1068 struct ixgbe_vfta *shadow_vfta = 1069 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1070 struct ixgbe_hwstrip *hwstrip = 1071 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1072 struct ixgbe_dcb_config *dcb_config = 1073 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private); 1074 struct ixgbe_filter_info *filter_info = 1075 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1076 struct ixgbe_bw_conf *bw_conf = 1077 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private); 1078 uint32_t ctrl_ext; 1079 uint16_t csum; 1080 int diag, i; 1081 1082 PMD_INIT_FUNC_TRACE(); 1083 1084 ixgbe_dev_macsec_setting_reset(eth_dev); 1085 1086 eth_dev->dev_ops = &ixgbe_eth_dev_ops; 1087 eth_dev->rx_queue_count = ixgbe_dev_rx_queue_count; 1088 eth_dev->rx_descriptor_done = ixgbe_dev_rx_descriptor_done; 1089 eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status; 1090 eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status; 1091 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1092 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1093 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts; 1094 1095 /* 1096 * For secondary processes, we don't initialise any further as primary 1097 * has already done this work. Only check we don't need a different 1098 * RX and TX function. 1099 */ 1100 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1101 struct ixgbe_tx_queue *txq; 1102 /* TX queue function in primary, set by last queue initialized 1103 * Tx queue may not initialized by primary process 1104 */ 1105 if (eth_dev->data->tx_queues) { 1106 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1]; 1107 ixgbe_set_tx_function(eth_dev, txq); 1108 } else { 1109 /* Use default TX function if we get here */ 1110 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. " 1111 "Using default TX function."); 1112 } 1113 1114 ixgbe_set_rx_function(eth_dev); 1115 1116 return 0; 1117 } 1118 1119 rte_atomic32_clear(&ad->link_thread_running); 1120 rte_eth_copy_pci_info(eth_dev, pci_dev); 1121 1122 /* Vendor and Device ID need to be set before init of shared code */ 1123 hw->device_id = pci_dev->id.device_id; 1124 hw->vendor_id = pci_dev->id.vendor_id; 1125 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1126 hw->allow_unsupported_sfp = 1; 1127 1128 /* Initialize the shared code (base driver) */ 1129 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1130 diag = ixgbe_bypass_init_shared_code(hw); 1131 #else 1132 diag = ixgbe_init_shared_code(hw); 1133 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1134 1135 if (diag != IXGBE_SUCCESS) { 1136 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag); 1137 return -EIO; 1138 } 1139 1140 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 1141 PMD_INIT_LOG(ERR, "\nERROR: " 1142 "Firmware recovery mode detected. Limiting functionality.\n" 1143 "Refer to the Intel(R) Ethernet Adapters and Devices " 1144 "User Guide for details on firmware recovery mode."); 1145 return -EIO; 1146 } 1147 1148 /* pick up the PCI bus settings for reporting later */ 1149 ixgbe_get_bus_info(hw); 1150 1151 /* Unlock any pending hardware semaphore */ 1152 ixgbe_swfw_lock_reset(hw); 1153 1154 #ifdef RTE_LIBRTE_SECURITY 1155 /* Initialize security_ctx only for primary process*/ 1156 if (ixgbe_ipsec_ctx_create(eth_dev)) 1157 return -ENOMEM; 1158 #endif 1159 1160 /* Initialize DCB configuration*/ 1161 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config)); 1162 ixgbe_dcb_init(hw, dcb_config); 1163 /* Get Hardware Flow Control setting */ 1164 hw->fc.requested_mode = ixgbe_fc_none; 1165 hw->fc.current_mode = ixgbe_fc_none; 1166 hw->fc.pause_time = IXGBE_FC_PAUSE; 1167 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 1168 hw->fc.low_water[i] = IXGBE_FC_LO; 1169 hw->fc.high_water[i] = IXGBE_FC_HI; 1170 } 1171 hw->fc.send_xon = 1; 1172 1173 /* Make sure we have a good EEPROM before we read from it */ 1174 diag = ixgbe_validate_eeprom_checksum(hw, &csum); 1175 if (diag != IXGBE_SUCCESS) { 1176 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag); 1177 return -EIO; 1178 } 1179 1180 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1181 diag = ixgbe_bypass_init_hw(hw); 1182 #else 1183 diag = ixgbe_init_hw(hw); 1184 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1185 1186 /* 1187 * Devices with copper phys will fail to initialise if ixgbe_init_hw() 1188 * is called too soon after the kernel driver unbinding/binding occurs. 1189 * The failure occurs in ixgbe_identify_phy_generic() for all devices, 1190 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is 1191 * also called. See ixgbe_identify_phy_82599(). The reason for the 1192 * failure is not known, and only occuts when virtualisation features 1193 * are disabled in the bios. A delay of 100ms was found to be enough by 1194 * trial-and-error, and is doubled to be safe. 1195 */ 1196 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) { 1197 rte_delay_ms(200); 1198 diag = ixgbe_init_hw(hw); 1199 } 1200 1201 if (diag == IXGBE_ERR_SFP_NOT_PRESENT) 1202 diag = IXGBE_SUCCESS; 1203 1204 if (diag == IXGBE_ERR_EEPROM_VERSION) { 1205 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/" 1206 "LOM. Please be aware there may be issues associated " 1207 "with your hardware."); 1208 PMD_INIT_LOG(ERR, "If you are experiencing problems " 1209 "please contact your Intel or hardware representative " 1210 "who provided you with this hardware."); 1211 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED) 1212 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module"); 1213 if (diag) { 1214 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag); 1215 return -EIO; 1216 } 1217 1218 /* Reset the hw statistics */ 1219 ixgbe_dev_stats_reset(eth_dev); 1220 1221 /* disable interrupt */ 1222 ixgbe_disable_intr(hw); 1223 1224 /* reset mappings for queue statistics hw counters*/ 1225 ixgbe_reset_qstat_mappings(hw); 1226 1227 /* Allocate memory for storing MAC addresses */ 1228 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN * 1229 hw->mac.num_rar_entries, 0); 1230 if (eth_dev->data->mac_addrs == NULL) { 1231 PMD_INIT_LOG(ERR, 1232 "Failed to allocate %u bytes needed to store " 1233 "MAC addresses", 1234 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1235 return -ENOMEM; 1236 } 1237 /* Copy the permanent MAC address */ 1238 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr, 1239 ð_dev->data->mac_addrs[0]); 1240 1241 /* Allocate memory for storing hash filter MAC addresses */ 1242 eth_dev->data->hash_mac_addrs = rte_zmalloc( 1243 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0); 1244 if (eth_dev->data->hash_mac_addrs == NULL) { 1245 PMD_INIT_LOG(ERR, 1246 "Failed to allocate %d bytes needed to store MAC addresses", 1247 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC); 1248 return -ENOMEM; 1249 } 1250 1251 /* initialize the vfta */ 1252 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1253 1254 /* initialize the hw strip bitmap*/ 1255 memset(hwstrip, 0, sizeof(*hwstrip)); 1256 1257 /* initialize PF if max_vfs not zero */ 1258 ixgbe_pf_host_init(eth_dev); 1259 1260 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 1261 /* let hardware know driver is loaded */ 1262 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD; 1263 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 1264 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 1265 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 1266 IXGBE_WRITE_FLUSH(hw); 1267 1268 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 1269 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d", 1270 (int) hw->mac.type, (int) hw->phy.type, 1271 (int) hw->phy.sfp_type); 1272 else 1273 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d", 1274 (int) hw->mac.type, (int) hw->phy.type); 1275 1276 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 1277 eth_dev->data->port_id, pci_dev->id.vendor_id, 1278 pci_dev->id.device_id); 1279 1280 rte_intr_callback_register(intr_handle, 1281 ixgbe_dev_interrupt_handler, eth_dev); 1282 1283 /* enable uio/vfio intr/eventfd mapping */ 1284 rte_intr_enable(intr_handle); 1285 1286 /* enable support intr */ 1287 ixgbe_enable_intr(eth_dev); 1288 1289 /* initialize filter info */ 1290 memset(filter_info, 0, 1291 sizeof(struct ixgbe_filter_info)); 1292 1293 /* initialize 5tuple filter list */ 1294 TAILQ_INIT(&filter_info->fivetuple_list); 1295 1296 /* initialize flow director filter list & hash */ 1297 ixgbe_fdir_filter_init(eth_dev); 1298 1299 /* initialize l2 tunnel filter list & hash */ 1300 ixgbe_l2_tn_filter_init(eth_dev); 1301 1302 /* initialize flow filter lists */ 1303 ixgbe_filterlist_init(); 1304 1305 /* initialize bandwidth configuration info */ 1306 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf)); 1307 1308 /* initialize Traffic Manager configuration */ 1309 ixgbe_tm_conf_init(eth_dev); 1310 1311 return 0; 1312 } 1313 1314 static int 1315 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1316 { 1317 PMD_INIT_FUNC_TRACE(); 1318 1319 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1320 return 0; 1321 1322 ixgbe_dev_close(eth_dev); 1323 1324 return 0; 1325 } 1326 1327 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev) 1328 { 1329 struct ixgbe_filter_info *filter_info = 1330 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1331 struct ixgbe_5tuple_filter *p_5tuple; 1332 1333 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) { 1334 TAILQ_REMOVE(&filter_info->fivetuple_list, 1335 p_5tuple, 1336 entries); 1337 rte_free(p_5tuple); 1338 } 1339 memset(filter_info->fivetuple_mask, 0, 1340 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE); 1341 1342 return 0; 1343 } 1344 1345 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev) 1346 { 1347 struct ixgbe_hw_fdir_info *fdir_info = 1348 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1349 struct ixgbe_fdir_filter *fdir_filter; 1350 1351 if (fdir_info->hash_map) 1352 rte_free(fdir_info->hash_map); 1353 if (fdir_info->hash_handle) 1354 rte_hash_free(fdir_info->hash_handle); 1355 1356 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 1357 TAILQ_REMOVE(&fdir_info->fdir_list, 1358 fdir_filter, 1359 entries); 1360 rte_free(fdir_filter); 1361 } 1362 1363 return 0; 1364 } 1365 1366 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev) 1367 { 1368 struct ixgbe_l2_tn_info *l2_tn_info = 1369 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1370 struct ixgbe_l2_tn_filter *l2_tn_filter; 1371 1372 if (l2_tn_info->hash_map) 1373 rte_free(l2_tn_info->hash_map); 1374 if (l2_tn_info->hash_handle) 1375 rte_hash_free(l2_tn_info->hash_handle); 1376 1377 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 1378 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, 1379 l2_tn_filter, 1380 entries); 1381 rte_free(l2_tn_filter); 1382 } 1383 1384 return 0; 1385 } 1386 1387 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev) 1388 { 1389 struct ixgbe_hw_fdir_info *fdir_info = 1390 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1391 char fdir_hash_name[RTE_HASH_NAMESIZE]; 1392 struct rte_hash_parameters fdir_hash_params = { 1393 .name = fdir_hash_name, 1394 .entries = IXGBE_MAX_FDIR_FILTER_NUM, 1395 .key_len = sizeof(union ixgbe_atr_input), 1396 .hash_func = rte_hash_crc, 1397 .hash_func_init_val = 0, 1398 .socket_id = rte_socket_id(), 1399 }; 1400 1401 TAILQ_INIT(&fdir_info->fdir_list); 1402 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 1403 "fdir_%s", eth_dev->device->name); 1404 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params); 1405 if (!fdir_info->hash_handle) { 1406 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 1407 return -EINVAL; 1408 } 1409 fdir_info->hash_map = rte_zmalloc("ixgbe", 1410 sizeof(struct ixgbe_fdir_filter *) * 1411 IXGBE_MAX_FDIR_FILTER_NUM, 1412 0); 1413 if (!fdir_info->hash_map) { 1414 PMD_INIT_LOG(ERR, 1415 "Failed to allocate memory for fdir hash map!"); 1416 return -ENOMEM; 1417 } 1418 fdir_info->mask_added = FALSE; 1419 1420 return 0; 1421 } 1422 1423 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) 1424 { 1425 struct ixgbe_l2_tn_info *l2_tn_info = 1426 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1427 char l2_tn_hash_name[RTE_HASH_NAMESIZE]; 1428 struct rte_hash_parameters l2_tn_hash_params = { 1429 .name = l2_tn_hash_name, 1430 .entries = IXGBE_MAX_L2_TN_FILTER_NUM, 1431 .key_len = sizeof(struct ixgbe_l2_tn_key), 1432 .hash_func = rte_hash_crc, 1433 .hash_func_init_val = 0, 1434 .socket_id = rte_socket_id(), 1435 }; 1436 1437 TAILQ_INIT(&l2_tn_info->l2_tn_list); 1438 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE, 1439 "l2_tn_%s", eth_dev->device->name); 1440 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params); 1441 if (!l2_tn_info->hash_handle) { 1442 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!"); 1443 return -EINVAL; 1444 } 1445 l2_tn_info->hash_map = rte_zmalloc("ixgbe", 1446 sizeof(struct ixgbe_l2_tn_filter *) * 1447 IXGBE_MAX_L2_TN_FILTER_NUM, 1448 0); 1449 if (!l2_tn_info->hash_map) { 1450 PMD_INIT_LOG(ERR, 1451 "Failed to allocate memory for L2 TN hash map!"); 1452 return -ENOMEM; 1453 } 1454 l2_tn_info->e_tag_en = FALSE; 1455 l2_tn_info->e_tag_fwd_en = FALSE; 1456 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG; 1457 1458 return 0; 1459 } 1460 /* 1461 * Negotiate mailbox API version with the PF. 1462 * After reset API version is always set to the basic one (ixgbe_mbox_api_10). 1463 * Then we try to negotiate starting with the most recent one. 1464 * If all negotiation attempts fail, then we will proceed with 1465 * the default one (ixgbe_mbox_api_10). 1466 */ 1467 static void 1468 ixgbevf_negotiate_api(struct ixgbe_hw *hw) 1469 { 1470 int32_t i; 1471 1472 /* start with highest supported, proceed down */ 1473 static const enum ixgbe_pfvf_api_rev sup_ver[] = { 1474 ixgbe_mbox_api_13, 1475 ixgbe_mbox_api_12, 1476 ixgbe_mbox_api_11, 1477 ixgbe_mbox_api_10, 1478 }; 1479 1480 for (i = 0; 1481 i != RTE_DIM(sup_ver) && 1482 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0; 1483 i++) 1484 ; 1485 } 1486 1487 static void 1488 generate_random_mac_addr(struct rte_ether_addr *mac_addr) 1489 { 1490 uint64_t random; 1491 1492 /* Set Organizationally Unique Identifier (OUI) prefix. */ 1493 mac_addr->addr_bytes[0] = 0x00; 1494 mac_addr->addr_bytes[1] = 0x09; 1495 mac_addr->addr_bytes[2] = 0xC0; 1496 /* Force indication of locally assigned MAC address. */ 1497 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR; 1498 /* Generate the last 3 bytes of the MAC address with a random number. */ 1499 random = rte_rand(); 1500 memcpy(&mac_addr->addr_bytes[3], &random, 3); 1501 } 1502 1503 static int 1504 devarg_handle_int(__rte_unused const char *key, const char *value, 1505 void *extra_args) 1506 { 1507 uint16_t *n = extra_args; 1508 1509 if (value == NULL || extra_args == NULL) 1510 return -EINVAL; 1511 1512 *n = (uint16_t)strtoul(value, NULL, 0); 1513 if (*n == USHRT_MAX && errno == ERANGE) 1514 return -1; 1515 1516 return 0; 1517 } 1518 1519 static void 1520 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter, 1521 struct rte_devargs *devargs) 1522 { 1523 struct rte_kvargs *kvlist; 1524 uint16_t pflink_fullchk; 1525 1526 if (devargs == NULL) 1527 return; 1528 1529 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments); 1530 if (kvlist == NULL) 1531 return; 1532 1533 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 && 1534 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK, 1535 devarg_handle_int, &pflink_fullchk) == 0 && 1536 pflink_fullchk == 1) 1537 adapter->pflink_fullchk = 1; 1538 1539 rte_kvargs_free(kvlist); 1540 } 1541 1542 /* 1543 * Virtual Function device init 1544 */ 1545 static int 1546 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev) 1547 { 1548 int diag; 1549 uint32_t tc, tcs; 1550 struct ixgbe_adapter *ad = eth_dev->data->dev_private; 1551 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1552 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1553 struct ixgbe_hw *hw = 1554 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1555 struct ixgbe_vfta *shadow_vfta = 1556 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1557 struct ixgbe_hwstrip *hwstrip = 1558 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1559 struct rte_ether_addr *perm_addr = 1560 (struct rte_ether_addr *)hw->mac.perm_addr; 1561 1562 PMD_INIT_FUNC_TRACE(); 1563 1564 eth_dev->dev_ops = &ixgbevf_eth_dev_ops; 1565 eth_dev->rx_descriptor_done = ixgbe_dev_rx_descriptor_done; 1566 eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status; 1567 eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status; 1568 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1569 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1570 1571 /* for secondary processes, we don't initialise any further as primary 1572 * has already done this work. Only check we don't need a different 1573 * RX function 1574 */ 1575 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1576 struct ixgbe_tx_queue *txq; 1577 /* TX queue function in primary, set by last queue initialized 1578 * Tx queue may not initialized by primary process 1579 */ 1580 if (eth_dev->data->tx_queues) { 1581 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1]; 1582 ixgbe_set_tx_function(eth_dev, txq); 1583 } else { 1584 /* Use default TX function if we get here */ 1585 PMD_INIT_LOG(NOTICE, 1586 "No TX queues configured yet. Using default TX function."); 1587 } 1588 1589 ixgbe_set_rx_function(eth_dev); 1590 1591 return 0; 1592 } 1593 1594 rte_atomic32_clear(&ad->link_thread_running); 1595 ixgbevf_parse_devargs(eth_dev->data->dev_private, 1596 pci_dev->device.devargs); 1597 1598 rte_eth_copy_pci_info(eth_dev, pci_dev); 1599 1600 hw->device_id = pci_dev->id.device_id; 1601 hw->vendor_id = pci_dev->id.vendor_id; 1602 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1603 1604 /* initialize the vfta */ 1605 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1606 1607 /* initialize the hw strip bitmap*/ 1608 memset(hwstrip, 0, sizeof(*hwstrip)); 1609 1610 /* Initialize the shared code (base driver) */ 1611 diag = ixgbe_init_shared_code(hw); 1612 if (diag != IXGBE_SUCCESS) { 1613 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag); 1614 return -EIO; 1615 } 1616 1617 /* init_mailbox_params */ 1618 hw->mbx.ops.init_params(hw); 1619 1620 /* Reset the hw statistics */ 1621 ixgbevf_dev_stats_reset(eth_dev); 1622 1623 /* Disable the interrupts for VF */ 1624 ixgbevf_intr_disable(eth_dev); 1625 1626 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */ 1627 diag = hw->mac.ops.reset_hw(hw); 1628 1629 /* 1630 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when 1631 * the underlying PF driver has not assigned a MAC address to the VF. 1632 * In this case, assign a random MAC address. 1633 */ 1634 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) { 1635 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1636 /* 1637 * This error code will be propagated to the app by 1638 * rte_eth_dev_reset, so use a public error code rather than 1639 * the internal-only IXGBE_ERR_RESET_FAILED 1640 */ 1641 return -EAGAIN; 1642 } 1643 1644 /* negotiate mailbox API version to use with the PF. */ 1645 ixgbevf_negotiate_api(hw); 1646 1647 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */ 1648 ixgbevf_get_queues(hw, &tcs, &tc); 1649 1650 /* Allocate memory for storing MAC addresses */ 1651 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN * 1652 hw->mac.num_rar_entries, 0); 1653 if (eth_dev->data->mac_addrs == NULL) { 1654 PMD_INIT_LOG(ERR, 1655 "Failed to allocate %u bytes needed to store " 1656 "MAC addresses", 1657 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1658 return -ENOMEM; 1659 } 1660 1661 /* Generate a random MAC address, if none was assigned by PF. */ 1662 if (rte_is_zero_ether_addr(perm_addr)) { 1663 generate_random_mac_addr(perm_addr); 1664 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1); 1665 if (diag) { 1666 rte_free(eth_dev->data->mac_addrs); 1667 eth_dev->data->mac_addrs = NULL; 1668 return diag; 1669 } 1670 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF"); 1671 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address " 1672 "%02x:%02x:%02x:%02x:%02x:%02x", 1673 perm_addr->addr_bytes[0], 1674 perm_addr->addr_bytes[1], 1675 perm_addr->addr_bytes[2], 1676 perm_addr->addr_bytes[3], 1677 perm_addr->addr_bytes[4], 1678 perm_addr->addr_bytes[5]); 1679 } 1680 1681 /* Copy the permanent MAC address */ 1682 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]); 1683 1684 /* reset the hardware with the new settings */ 1685 diag = hw->mac.ops.start_hw(hw); 1686 switch (diag) { 1687 case 0: 1688 break; 1689 1690 default: 1691 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1692 return -EIO; 1693 } 1694 1695 rte_intr_callback_register(intr_handle, 1696 ixgbevf_dev_interrupt_handler, eth_dev); 1697 rte_intr_enable(intr_handle); 1698 ixgbevf_intr_enable(eth_dev); 1699 1700 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s", 1701 eth_dev->data->port_id, pci_dev->id.vendor_id, 1702 pci_dev->id.device_id, "ixgbe_mac_82599_vf"); 1703 1704 return 0; 1705 } 1706 1707 /* Virtual Function device uninit */ 1708 1709 static int 1710 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev) 1711 { 1712 PMD_INIT_FUNC_TRACE(); 1713 1714 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1715 return 0; 1716 1717 ixgbevf_dev_close(eth_dev); 1718 1719 return 0; 1720 } 1721 1722 static int 1723 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1724 struct rte_pci_device *pci_dev) 1725 { 1726 char name[RTE_ETH_NAME_MAX_LEN]; 1727 struct rte_eth_dev *pf_ethdev; 1728 struct rte_eth_devargs eth_da; 1729 int i, retval; 1730 1731 if (pci_dev->device.devargs) { 1732 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 1733 ð_da); 1734 if (retval) 1735 return retval; 1736 } else 1737 memset(ð_da, 0, sizeof(eth_da)); 1738 1739 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 1740 sizeof(struct ixgbe_adapter), 1741 eth_dev_pci_specific_init, pci_dev, 1742 eth_ixgbe_dev_init, NULL); 1743 1744 if (retval || eth_da.nb_representor_ports < 1) 1745 return retval; 1746 1747 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1748 if (pf_ethdev == NULL) 1749 return -ENODEV; 1750 1751 /* probe VF representor ports */ 1752 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1753 struct ixgbe_vf_info *vfinfo; 1754 struct ixgbe_vf_representor representor; 1755 1756 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA( 1757 pf_ethdev->data->dev_private); 1758 if (vfinfo == NULL) { 1759 PMD_DRV_LOG(ERR, 1760 "no virtual functions supported by PF"); 1761 break; 1762 } 1763 1764 representor.vf_id = eth_da.representor_ports[i]; 1765 representor.switch_domain_id = vfinfo->switch_domain_id; 1766 representor.pf_ethdev = pf_ethdev; 1767 1768 /* representor port net_bdf_port */ 1769 snprintf(name, sizeof(name), "net_%s_representor_%d", 1770 pci_dev->device.name, 1771 eth_da.representor_ports[i]); 1772 1773 retval = rte_eth_dev_create(&pci_dev->device, name, 1774 sizeof(struct ixgbe_vf_representor), NULL, NULL, 1775 ixgbe_vf_representor_init, &representor); 1776 1777 if (retval) 1778 PMD_DRV_LOG(ERR, "failed to create ixgbe vf " 1779 "representor %s.", name); 1780 } 1781 1782 return 0; 1783 } 1784 1785 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev) 1786 { 1787 struct rte_eth_dev *ethdev; 1788 1789 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1790 if (!ethdev) 1791 return 0; 1792 1793 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 1794 return rte_eth_dev_pci_generic_remove(pci_dev, 1795 ixgbe_vf_representor_uninit); 1796 else 1797 return rte_eth_dev_pci_generic_remove(pci_dev, 1798 eth_ixgbe_dev_uninit); 1799 } 1800 1801 static struct rte_pci_driver rte_ixgbe_pmd = { 1802 .id_table = pci_id_ixgbe_map, 1803 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1804 .probe = eth_ixgbe_pci_probe, 1805 .remove = eth_ixgbe_pci_remove, 1806 }; 1807 1808 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1809 struct rte_pci_device *pci_dev) 1810 { 1811 return rte_eth_dev_pci_generic_probe(pci_dev, 1812 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init); 1813 } 1814 1815 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev) 1816 { 1817 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit); 1818 } 1819 1820 /* 1821 * virtual function driver struct 1822 */ 1823 static struct rte_pci_driver rte_ixgbevf_pmd = { 1824 .id_table = pci_id_ixgbevf_map, 1825 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1826 .probe = eth_ixgbevf_pci_probe, 1827 .remove = eth_ixgbevf_pci_remove, 1828 }; 1829 1830 static int 1831 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1832 { 1833 struct ixgbe_hw *hw = 1834 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1835 struct ixgbe_vfta *shadow_vfta = 1836 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1837 uint32_t vfta; 1838 uint32_t vid_idx; 1839 uint32_t vid_bit; 1840 1841 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 1842 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 1843 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx)); 1844 if (on) 1845 vfta |= vid_bit; 1846 else 1847 vfta &= ~vid_bit; 1848 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta); 1849 1850 /* update local VFTA copy */ 1851 shadow_vfta->vfta[vid_idx] = vfta; 1852 1853 return 0; 1854 } 1855 1856 static void 1857 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 1858 { 1859 if (on) 1860 ixgbe_vlan_hw_strip_enable(dev, queue); 1861 else 1862 ixgbe_vlan_hw_strip_disable(dev, queue); 1863 } 1864 1865 static int 1866 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1867 enum rte_vlan_type vlan_type, 1868 uint16_t tpid) 1869 { 1870 struct ixgbe_hw *hw = 1871 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1872 int ret = 0; 1873 uint32_t reg; 1874 uint32_t qinq; 1875 1876 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1877 qinq &= IXGBE_DMATXCTL_GDV; 1878 1879 switch (vlan_type) { 1880 case ETH_VLAN_TYPE_INNER: 1881 if (qinq) { 1882 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1883 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1884 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1885 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1886 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1887 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1888 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1889 } else { 1890 ret = -ENOTSUP; 1891 PMD_DRV_LOG(ERR, "Inner type is not supported" 1892 " by single VLAN"); 1893 } 1894 break; 1895 case ETH_VLAN_TYPE_OUTER: 1896 if (qinq) { 1897 /* Only the high 16-bits is valid */ 1898 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid << 1899 IXGBE_EXVET_VET_EXT_SHIFT); 1900 } else { 1901 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1902 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1903 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1904 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1905 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1906 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1907 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1908 } 1909 1910 break; 1911 default: 1912 ret = -EINVAL; 1913 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type); 1914 break; 1915 } 1916 1917 return ret; 1918 } 1919 1920 void 1921 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev) 1922 { 1923 struct ixgbe_hw *hw = 1924 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1925 uint32_t vlnctrl; 1926 1927 PMD_INIT_FUNC_TRACE(); 1928 1929 /* Filter Table Disable */ 1930 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1931 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 1932 1933 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1934 } 1935 1936 void 1937 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1938 { 1939 struct ixgbe_hw *hw = 1940 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1941 struct ixgbe_vfta *shadow_vfta = 1942 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1943 uint32_t vlnctrl; 1944 uint16_t i; 1945 1946 PMD_INIT_FUNC_TRACE(); 1947 1948 /* Filter Table Enable */ 1949 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1950 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; 1951 vlnctrl |= IXGBE_VLNCTRL_VFE; 1952 1953 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1954 1955 /* write whatever is in local vfta copy */ 1956 for (i = 0; i < IXGBE_VFTA_SIZE; i++) 1957 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]); 1958 } 1959 1960 static void 1961 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on) 1962 { 1963 struct ixgbe_hwstrip *hwstrip = 1964 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private); 1965 struct ixgbe_rx_queue *rxq; 1966 1967 if (queue >= IXGBE_MAX_RX_QUEUE_NUM) 1968 return; 1969 1970 if (on) 1971 IXGBE_SET_HWSTRIP(hwstrip, queue); 1972 else 1973 IXGBE_CLEAR_HWSTRIP(hwstrip, queue); 1974 1975 if (queue >= dev->data->nb_rx_queues) 1976 return; 1977 1978 rxq = dev->data->rx_queues[queue]; 1979 1980 if (on) { 1981 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; 1982 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 1983 } else { 1984 rxq->vlan_flags = PKT_RX_VLAN; 1985 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 1986 } 1987 } 1988 1989 static void 1990 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue) 1991 { 1992 struct ixgbe_hw *hw = 1993 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1994 uint32_t ctrl; 1995 1996 PMD_INIT_FUNC_TRACE(); 1997 1998 if (hw->mac.type == ixgbe_mac_82598EB) { 1999 /* No queue level support */ 2000 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2001 return; 2002 } 2003 2004 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2005 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2006 ctrl &= ~IXGBE_RXDCTL_VME; 2007 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2008 2009 /* record those setting for HW strip per queue */ 2010 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0); 2011 } 2012 2013 static void 2014 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue) 2015 { 2016 struct ixgbe_hw *hw = 2017 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2018 uint32_t ctrl; 2019 2020 PMD_INIT_FUNC_TRACE(); 2021 2022 if (hw->mac.type == ixgbe_mac_82598EB) { 2023 /* No queue level supported */ 2024 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2025 return; 2026 } 2027 2028 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2029 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2030 ctrl |= IXGBE_RXDCTL_VME; 2031 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2032 2033 /* record those setting for HW strip per queue */ 2034 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1); 2035 } 2036 2037 static void 2038 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev) 2039 { 2040 struct ixgbe_hw *hw = 2041 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2042 uint32_t ctrl; 2043 2044 PMD_INIT_FUNC_TRACE(); 2045 2046 /* DMATXCTRL: Geric Double VLAN Disable */ 2047 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2048 ctrl &= ~IXGBE_DMATXCTL_GDV; 2049 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2050 2051 /* CTRL_EXT: Global Double VLAN Disable */ 2052 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2053 ctrl &= ~IXGBE_EXTENDED_VLAN; 2054 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2055 2056 } 2057 2058 static void 2059 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) 2060 { 2061 struct ixgbe_hw *hw = 2062 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2063 uint32_t ctrl; 2064 2065 PMD_INIT_FUNC_TRACE(); 2066 2067 /* DMATXCTRL: Geric Double VLAN Enable */ 2068 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2069 ctrl |= IXGBE_DMATXCTL_GDV; 2070 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2071 2072 /* CTRL_EXT: Global Double VLAN Enable */ 2073 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2074 ctrl |= IXGBE_EXTENDED_VLAN; 2075 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2076 2077 /* Clear pooling mode of PFVTCTL. It's required by X550. */ 2078 if (hw->mac.type == ixgbe_mac_X550 || 2079 hw->mac.type == ixgbe_mac_X550EM_x || 2080 hw->mac.type == ixgbe_mac_X550EM_a) { 2081 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 2082 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 2083 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 2084 } 2085 2086 /* 2087 * VET EXT field in the EXVET register = 0x8100 by default 2088 * So no need to change. Same to VT field of DMATXCTL register 2089 */ 2090 } 2091 2092 void 2093 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev) 2094 { 2095 struct ixgbe_hw *hw = 2096 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2097 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 2098 uint32_t ctrl; 2099 uint16_t i; 2100 struct ixgbe_rx_queue *rxq; 2101 bool on; 2102 2103 PMD_INIT_FUNC_TRACE(); 2104 2105 if (hw->mac.type == ixgbe_mac_82598EB) { 2106 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2107 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2108 ctrl |= IXGBE_VLNCTRL_VME; 2109 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2110 } else { 2111 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2112 ctrl &= ~IXGBE_VLNCTRL_VME; 2113 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2114 } 2115 } else { 2116 /* 2117 * Other 10G NIC, the VLAN strip can be setup 2118 * per queue in RXDCTL 2119 */ 2120 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2121 rxq = dev->data->rx_queues[i]; 2122 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx)); 2123 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2124 ctrl |= IXGBE_RXDCTL_VME; 2125 on = TRUE; 2126 } else { 2127 ctrl &= ~IXGBE_RXDCTL_VME; 2128 on = FALSE; 2129 } 2130 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl); 2131 2132 /* record those setting for HW strip per queue */ 2133 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on); 2134 } 2135 } 2136 } 2137 2138 static void 2139 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask) 2140 { 2141 uint16_t i; 2142 struct rte_eth_rxmode *rxmode; 2143 struct ixgbe_rx_queue *rxq; 2144 2145 if (mask & ETH_VLAN_STRIP_MASK) { 2146 rxmode = &dev->data->dev_conf.rxmode; 2147 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 2148 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2149 rxq = dev->data->rx_queues[i]; 2150 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 2151 } 2152 else 2153 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2154 rxq = dev->data->rx_queues[i]; 2155 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 2156 } 2157 } 2158 } 2159 2160 static int 2161 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask) 2162 { 2163 struct rte_eth_rxmode *rxmode; 2164 rxmode = &dev->data->dev_conf.rxmode; 2165 2166 if (mask & ETH_VLAN_STRIP_MASK) { 2167 ixgbe_vlan_hw_strip_config(dev); 2168 } 2169 2170 if (mask & ETH_VLAN_FILTER_MASK) { 2171 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 2172 ixgbe_vlan_hw_filter_enable(dev); 2173 else 2174 ixgbe_vlan_hw_filter_disable(dev); 2175 } 2176 2177 if (mask & ETH_VLAN_EXTEND_MASK) { 2178 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2179 ixgbe_vlan_hw_extend_enable(dev); 2180 else 2181 ixgbe_vlan_hw_extend_disable(dev); 2182 } 2183 2184 return 0; 2185 } 2186 2187 static int 2188 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2189 { 2190 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 2191 2192 ixgbe_vlan_offload_config(dev, mask); 2193 2194 return 0; 2195 } 2196 2197 static void 2198 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev) 2199 { 2200 struct ixgbe_hw *hw = 2201 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2202 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */ 2203 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2204 2205 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */ 2206 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl); 2207 } 2208 2209 static int 2210 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q) 2211 { 2212 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2213 2214 switch (nb_rx_q) { 2215 case 1: 2216 case 2: 2217 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS; 2218 break; 2219 case 4: 2220 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS; 2221 break; 2222 default: 2223 return -EINVAL; 2224 } 2225 2226 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 2227 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2228 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 2229 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2230 return 0; 2231 } 2232 2233 static int 2234 ixgbe_check_mq_mode(struct rte_eth_dev *dev) 2235 { 2236 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 2237 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2238 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2239 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2240 2241 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 2242 /* check multi-queue mode */ 2243 switch (dev_conf->rxmode.mq_mode) { 2244 case ETH_MQ_RX_VMDQ_DCB: 2245 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV"); 2246 break; 2247 case ETH_MQ_RX_VMDQ_DCB_RSS: 2248 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */ 2249 PMD_INIT_LOG(ERR, "SRIOV active," 2250 " unsupported mq_mode rx %d.", 2251 dev_conf->rxmode.mq_mode); 2252 return -EINVAL; 2253 case ETH_MQ_RX_RSS: 2254 case ETH_MQ_RX_VMDQ_RSS: 2255 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS; 2256 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) 2257 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) { 2258 PMD_INIT_LOG(ERR, "SRIOV is active," 2259 " invalid queue number" 2260 " for VMDQ RSS, allowed" 2261 " value are 1, 2 or 4."); 2262 return -EINVAL; 2263 } 2264 break; 2265 case ETH_MQ_RX_VMDQ_ONLY: 2266 case ETH_MQ_RX_NONE: 2267 /* if nothing mq mode configure, use default scheme */ 2268 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY; 2269 break; 2270 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/ 2271 /* SRIOV only works in VMDq enable mode */ 2272 PMD_INIT_LOG(ERR, "SRIOV is active," 2273 " wrong mq_mode rx %d.", 2274 dev_conf->rxmode.mq_mode); 2275 return -EINVAL; 2276 } 2277 2278 switch (dev_conf->txmode.mq_mode) { 2279 case ETH_MQ_TX_VMDQ_DCB: 2280 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV"); 2281 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB; 2282 break; 2283 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */ 2284 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY; 2285 break; 2286 } 2287 2288 /* check valid queue number */ 2289 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) || 2290 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) { 2291 PMD_INIT_LOG(ERR, "SRIOV is active," 2292 " nb_rx_q=%d nb_tx_q=%d queue number" 2293 " must be less than or equal to %d.", 2294 nb_rx_q, nb_tx_q, 2295 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool); 2296 return -EINVAL; 2297 } 2298 } else { 2299 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) { 2300 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is" 2301 " not supported."); 2302 return -EINVAL; 2303 } 2304 /* check configuration for vmdb+dcb mode */ 2305 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) { 2306 const struct rte_eth_vmdq_dcb_conf *conf; 2307 2308 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2309 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.", 2310 IXGBE_VMDQ_DCB_NB_QUEUES); 2311 return -EINVAL; 2312 } 2313 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf; 2314 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2315 conf->nb_queue_pools == ETH_32_POOLS)) { 2316 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2317 " nb_queue_pools must be %d or %d.", 2318 ETH_16_POOLS, ETH_32_POOLS); 2319 return -EINVAL; 2320 } 2321 } 2322 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) { 2323 const struct rte_eth_vmdq_dcb_tx_conf *conf; 2324 2325 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2326 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d", 2327 IXGBE_VMDQ_DCB_NB_QUEUES); 2328 return -EINVAL; 2329 } 2330 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf; 2331 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2332 conf->nb_queue_pools == ETH_32_POOLS)) { 2333 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2334 " nb_queue_pools != %d and" 2335 " nb_queue_pools != %d.", 2336 ETH_16_POOLS, ETH_32_POOLS); 2337 return -EINVAL; 2338 } 2339 } 2340 2341 /* For DCB mode check our configuration before we go further */ 2342 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) { 2343 const struct rte_eth_dcb_rx_conf *conf; 2344 2345 conf = &dev_conf->rx_adv_conf.dcb_rx_conf; 2346 if (!(conf->nb_tcs == ETH_4_TCS || 2347 conf->nb_tcs == ETH_8_TCS)) { 2348 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2349 " and nb_tcs != %d.", 2350 ETH_4_TCS, ETH_8_TCS); 2351 return -EINVAL; 2352 } 2353 } 2354 2355 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) { 2356 const struct rte_eth_dcb_tx_conf *conf; 2357 2358 conf = &dev_conf->tx_adv_conf.dcb_tx_conf; 2359 if (!(conf->nb_tcs == ETH_4_TCS || 2360 conf->nb_tcs == ETH_8_TCS)) { 2361 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2362 " and nb_tcs != %d.", 2363 ETH_4_TCS, ETH_8_TCS); 2364 return -EINVAL; 2365 } 2366 } 2367 2368 /* 2369 * When DCB/VT is off, maximum number of queues changes, 2370 * except for 82598EB, which remains constant. 2371 */ 2372 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 2373 hw->mac.type != ixgbe_mac_82598EB) { 2374 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) { 2375 PMD_INIT_LOG(ERR, 2376 "Neither VT nor DCB are enabled, " 2377 "nb_tx_q > %d.", 2378 IXGBE_NONE_MODE_TX_NB_QUEUES); 2379 return -EINVAL; 2380 } 2381 } 2382 } 2383 return 0; 2384 } 2385 2386 static int 2387 ixgbe_dev_configure(struct rte_eth_dev *dev) 2388 { 2389 struct ixgbe_interrupt *intr = 2390 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2391 struct ixgbe_adapter *adapter = dev->data->dev_private; 2392 int ret; 2393 2394 PMD_INIT_FUNC_TRACE(); 2395 2396 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 2397 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 2398 2399 /* multipe queue mode checking */ 2400 ret = ixgbe_check_mq_mode(dev); 2401 if (ret != 0) { 2402 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.", 2403 ret); 2404 return ret; 2405 } 2406 2407 /* set flag to update link status after init */ 2408 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2409 2410 /* 2411 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 2412 * allocation or vector Rx preconditions we will reset it. 2413 */ 2414 adapter->rx_bulk_alloc_allowed = true; 2415 adapter->rx_vec_allowed = true; 2416 2417 return 0; 2418 } 2419 2420 static void 2421 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) 2422 { 2423 struct ixgbe_hw *hw = 2424 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2425 struct ixgbe_interrupt *intr = 2426 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2427 uint32_t gpie; 2428 2429 /* only set up it on X550EM_X */ 2430 if (hw->mac.type == ixgbe_mac_X550EM_x) { 2431 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 2432 gpie |= IXGBE_SDP0_GPIEN_X550EM_x; 2433 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 2434 if (hw->phy.type == ixgbe_phy_x550em_ext_t) 2435 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x; 2436 } 2437 } 2438 2439 int 2440 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 2441 uint16_t tx_rate, uint64_t q_msk) 2442 { 2443 struct ixgbe_hw *hw; 2444 struct ixgbe_vf_info *vfinfo; 2445 struct rte_eth_link link; 2446 uint8_t nb_q_per_pool; 2447 uint32_t queue_stride; 2448 uint32_t queue_idx, idx = 0, vf_idx; 2449 uint32_t queue_end; 2450 uint16_t total_rate = 0; 2451 struct rte_pci_device *pci_dev; 2452 int ret; 2453 2454 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2455 ret = rte_eth_link_get_nowait(dev->data->port_id, &link); 2456 if (ret < 0) 2457 return ret; 2458 2459 if (vf >= pci_dev->max_vfs) 2460 return -EINVAL; 2461 2462 if (tx_rate > link.link_speed) 2463 return -EINVAL; 2464 2465 if (q_msk == 0) 2466 return 0; 2467 2468 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2469 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 2470 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2471 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2472 queue_idx = vf * queue_stride; 2473 queue_end = queue_idx + nb_q_per_pool - 1; 2474 if (queue_end >= hw->mac.max_tx_queues) 2475 return -EINVAL; 2476 2477 if (vfinfo) { 2478 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) { 2479 if (vf_idx == vf) 2480 continue; 2481 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate); 2482 idx++) 2483 total_rate += vfinfo[vf_idx].tx_rate[idx]; 2484 } 2485 } else { 2486 return -EINVAL; 2487 } 2488 2489 /* Store tx_rate for this vf. */ 2490 for (idx = 0; idx < nb_q_per_pool; idx++) { 2491 if (((uint64_t)0x1 << idx) & q_msk) { 2492 if (vfinfo[vf].tx_rate[idx] != tx_rate) 2493 vfinfo[vf].tx_rate[idx] = tx_rate; 2494 total_rate += tx_rate; 2495 } 2496 } 2497 2498 if (total_rate > dev->data->dev_link.link_speed) { 2499 /* Reset stored TX rate of the VF if it causes exceed 2500 * link speed. 2501 */ 2502 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate)); 2503 return -EINVAL; 2504 } 2505 2506 /* Set RTTBCNRC of each queue/pool for vf X */ 2507 for (; queue_idx <= queue_end; queue_idx++) { 2508 if (0x1 & q_msk) 2509 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate); 2510 q_msk = q_msk >> 1; 2511 } 2512 2513 return 0; 2514 } 2515 2516 static int 2517 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw) 2518 { 2519 struct ixgbe_adapter *adapter = dev->data->dev_private; 2520 int err; 2521 uint32_t mflcn; 2522 2523 ixgbe_setup_fc(hw); 2524 2525 err = ixgbe_fc_enable(hw); 2526 2527 /* Not negotiated is not an error case */ 2528 if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) { 2529 /* 2530 *check if we want to forward MAC frames - driver doesn't 2531 *have native capability to do that, 2532 *so we'll write the registers ourselves 2533 */ 2534 2535 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2536 2537 /* set or clear MFLCN.PMCF bit depending on configuration */ 2538 if (adapter->mac_ctrl_frame_fwd != 0) 2539 mflcn |= IXGBE_MFLCN_PMCF; 2540 else 2541 mflcn &= ~IXGBE_MFLCN_PMCF; 2542 2543 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn); 2544 IXGBE_WRITE_FLUSH(hw); 2545 2546 return 0; 2547 } 2548 return err; 2549 } 2550 2551 /* 2552 * Configure device link speed and setup link. 2553 * It returns 0 on success. 2554 */ 2555 static int 2556 ixgbe_dev_start(struct rte_eth_dev *dev) 2557 { 2558 struct ixgbe_hw *hw = 2559 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2560 struct ixgbe_vf_info *vfinfo = 2561 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2562 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2563 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2564 uint32_t intr_vector = 0; 2565 int err; 2566 bool link_up = false, negotiate = 0; 2567 uint32_t speed = 0; 2568 uint32_t allowed_speeds = 0; 2569 int mask = 0; 2570 int status; 2571 uint16_t vf, idx; 2572 uint32_t *link_speeds; 2573 struct ixgbe_tm_conf *tm_conf = 2574 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2575 struct ixgbe_macsec_setting *macsec_setting = 2576 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 2577 2578 PMD_INIT_FUNC_TRACE(); 2579 2580 /* Stop the link setup handler before resetting the HW. */ 2581 ixgbe_dev_wait_setup_link_complete(dev, 0); 2582 2583 /* disable uio/vfio intr/eventfd mapping */ 2584 rte_intr_disable(intr_handle); 2585 2586 /* stop adapter */ 2587 hw->adapter_stopped = 0; 2588 ixgbe_stop_adapter(hw); 2589 2590 /* reinitialize adapter 2591 * this calls reset and start 2592 */ 2593 status = ixgbe_pf_reset_hw(hw); 2594 if (status != 0) 2595 return -1; 2596 hw->mac.ops.start_hw(hw); 2597 hw->mac.get_link_status = true; 2598 2599 /* configure PF module if SRIOV enabled */ 2600 ixgbe_pf_host_configure(dev); 2601 2602 ixgbe_dev_phy_intr_setup(dev); 2603 2604 /* check and configure queue intr-vector mapping */ 2605 if ((rte_intr_cap_multiple(intr_handle) || 2606 !RTE_ETH_DEV_SRIOV(dev).active) && 2607 dev->data->dev_conf.intr_conf.rxq != 0) { 2608 intr_vector = dev->data->nb_rx_queues; 2609 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) { 2610 PMD_INIT_LOG(ERR, "At most %d intr queues supported", 2611 IXGBE_MAX_INTR_QUEUE_NUM); 2612 return -ENOTSUP; 2613 } 2614 if (rte_intr_efd_enable(intr_handle, intr_vector)) 2615 return -1; 2616 } 2617 2618 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 2619 intr_handle->intr_vec = 2620 rte_zmalloc("intr_vec", 2621 dev->data->nb_rx_queues * sizeof(int), 0); 2622 if (intr_handle->intr_vec == NULL) { 2623 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 2624 " intr_vec", dev->data->nb_rx_queues); 2625 return -ENOMEM; 2626 } 2627 } 2628 2629 /* confiugre msix for sleep until rx interrupt */ 2630 ixgbe_configure_msix(dev); 2631 2632 /* initialize transmission unit */ 2633 ixgbe_dev_tx_init(dev); 2634 2635 /* This can fail when allocating mbufs for descriptor rings */ 2636 err = ixgbe_dev_rx_init(dev); 2637 if (err) { 2638 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 2639 goto error; 2640 } 2641 2642 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 2643 ETH_VLAN_EXTEND_MASK; 2644 err = ixgbe_vlan_offload_config(dev, mask); 2645 if (err) { 2646 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 2647 goto error; 2648 } 2649 2650 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) { 2651 /* Enable vlan filtering for VMDq */ 2652 ixgbe_vmdq_vlan_hw_filter_enable(dev); 2653 } 2654 2655 /* Configure DCB hw */ 2656 ixgbe_configure_dcb(dev); 2657 2658 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) { 2659 err = ixgbe_fdir_configure(dev); 2660 if (err) 2661 goto error; 2662 } 2663 2664 /* Restore vf rate limit */ 2665 if (vfinfo != NULL) { 2666 for (vf = 0; vf < pci_dev->max_vfs; vf++) 2667 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++) 2668 if (vfinfo[vf].tx_rate[idx] != 0) 2669 ixgbe_set_vf_rate_limit( 2670 dev, vf, 2671 vfinfo[vf].tx_rate[idx], 2672 1 << idx); 2673 } 2674 2675 ixgbe_restore_statistics_mapping(dev); 2676 2677 err = ixgbe_flow_ctrl_enable(dev, hw); 2678 if (err < 0) { 2679 PMD_INIT_LOG(ERR, "enable flow ctrl err"); 2680 goto error; 2681 } 2682 2683 err = ixgbe_dev_rxtx_start(dev); 2684 if (err < 0) { 2685 PMD_INIT_LOG(ERR, "Unable to start rxtx queues"); 2686 goto error; 2687 } 2688 2689 /* Skip link setup if loopback mode is enabled. */ 2690 if (dev->data->dev_conf.lpbk_mode != 0) { 2691 err = ixgbe_check_supported_loopback_mode(dev); 2692 if (err < 0) { 2693 PMD_INIT_LOG(ERR, "Unsupported loopback mode"); 2694 goto error; 2695 } else { 2696 goto skip_link_setup; 2697 } 2698 } 2699 2700 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) { 2701 err = hw->mac.ops.setup_sfp(hw); 2702 if (err) 2703 goto error; 2704 } 2705 2706 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2707 /* Turn on the copper */ 2708 ixgbe_set_phy_power(hw, true); 2709 } else { 2710 /* Turn on the laser */ 2711 ixgbe_enable_tx_laser(hw); 2712 } 2713 2714 err = ixgbe_check_link(hw, &speed, &link_up, 0); 2715 if (err) 2716 goto error; 2717 dev->data->dev_link.link_status = link_up; 2718 2719 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate); 2720 if (err) 2721 goto error; 2722 2723 switch (hw->mac.type) { 2724 case ixgbe_mac_X550: 2725 case ixgbe_mac_X550EM_x: 2726 case ixgbe_mac_X550EM_a: 2727 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2728 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G | 2729 ETH_LINK_SPEED_10G; 2730 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 2731 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 2732 allowed_speeds = ETH_LINK_SPEED_10M | 2733 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G; 2734 break; 2735 default: 2736 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2737 ETH_LINK_SPEED_10G; 2738 } 2739 2740 link_speeds = &dev->data->dev_conf.link_speeds; 2741 2742 /* Ignore autoneg flag bit and check the validity of 2743 * link_speed 2744 */ 2745 if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) { 2746 PMD_INIT_LOG(ERR, "Invalid link setting"); 2747 goto error; 2748 } 2749 2750 speed = 0x0; 2751 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) { 2752 switch (hw->mac.type) { 2753 case ixgbe_mac_82598EB: 2754 speed = IXGBE_LINK_SPEED_82598_AUTONEG; 2755 break; 2756 case ixgbe_mac_82599EB: 2757 case ixgbe_mac_X540: 2758 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2759 break; 2760 case ixgbe_mac_X550: 2761 case ixgbe_mac_X550EM_x: 2762 case ixgbe_mac_X550EM_a: 2763 speed = IXGBE_LINK_SPEED_X550_AUTONEG; 2764 break; 2765 default: 2766 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2767 } 2768 } else { 2769 if (*link_speeds & ETH_LINK_SPEED_10G) 2770 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2771 if (*link_speeds & ETH_LINK_SPEED_5G) 2772 speed |= IXGBE_LINK_SPEED_5GB_FULL; 2773 if (*link_speeds & ETH_LINK_SPEED_2_5G) 2774 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 2775 if (*link_speeds & ETH_LINK_SPEED_1G) 2776 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2777 if (*link_speeds & ETH_LINK_SPEED_100M) 2778 speed |= IXGBE_LINK_SPEED_100_FULL; 2779 if (*link_speeds & ETH_LINK_SPEED_10M) 2780 speed |= IXGBE_LINK_SPEED_10_FULL; 2781 } 2782 2783 err = ixgbe_setup_link(hw, speed, link_up); 2784 if (err) 2785 goto error; 2786 2787 skip_link_setup: 2788 2789 if (rte_intr_allow_others(intr_handle)) { 2790 /* check if lsc interrupt is enabled */ 2791 if (dev->data->dev_conf.intr_conf.lsc != 0) 2792 ixgbe_dev_lsc_interrupt_setup(dev, TRUE); 2793 else 2794 ixgbe_dev_lsc_interrupt_setup(dev, FALSE); 2795 ixgbe_dev_macsec_interrupt_setup(dev); 2796 } else { 2797 rte_intr_callback_unregister(intr_handle, 2798 ixgbe_dev_interrupt_handler, dev); 2799 if (dev->data->dev_conf.intr_conf.lsc != 0) 2800 PMD_INIT_LOG(INFO, "lsc won't enable because of" 2801 " no intr multiplex"); 2802 } 2803 2804 /* check if rxq interrupt is enabled */ 2805 if (dev->data->dev_conf.intr_conf.rxq != 0 && 2806 rte_intr_dp_is_en(intr_handle)) 2807 ixgbe_dev_rxq_interrupt_setup(dev); 2808 2809 /* enable uio/vfio intr/eventfd mapping */ 2810 rte_intr_enable(intr_handle); 2811 2812 /* resume enabled intr since hw reset */ 2813 ixgbe_enable_intr(dev); 2814 ixgbe_l2_tunnel_conf(dev); 2815 ixgbe_filter_restore(dev); 2816 2817 if (tm_conf->root && !tm_conf->committed) 2818 PMD_DRV_LOG(WARNING, 2819 "please call hierarchy_commit() " 2820 "before starting the port"); 2821 2822 /* wait for the controller to acquire link */ 2823 err = ixgbe_wait_for_link_up(hw); 2824 if (err) 2825 goto error; 2826 2827 /* 2828 * Update link status right before return, because it may 2829 * start link configuration process in a separate thread. 2830 */ 2831 ixgbe_dev_link_update(dev, 0); 2832 2833 /* setup the macsec setting register */ 2834 if (macsec_setting->offload_en) 2835 ixgbe_dev_macsec_register_enable(dev, macsec_setting); 2836 2837 return 0; 2838 2839 error: 2840 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err); 2841 ixgbe_dev_clear_queues(dev); 2842 return -EIO; 2843 } 2844 2845 /* 2846 * Stop device: disable rx and tx functions to allow for reconfiguring. 2847 */ 2848 static void 2849 ixgbe_dev_stop(struct rte_eth_dev *dev) 2850 { 2851 struct rte_eth_link link; 2852 struct ixgbe_adapter *adapter = dev->data->dev_private; 2853 struct ixgbe_hw *hw = 2854 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2855 struct ixgbe_vf_info *vfinfo = 2856 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2857 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2858 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2859 int vf; 2860 struct ixgbe_tm_conf *tm_conf = 2861 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2862 2863 if (hw->adapter_stopped) 2864 return; 2865 2866 PMD_INIT_FUNC_TRACE(); 2867 2868 ixgbe_dev_wait_setup_link_complete(dev, 0); 2869 2870 /* disable interrupts */ 2871 ixgbe_disable_intr(hw); 2872 2873 /* reset the NIC */ 2874 ixgbe_pf_reset_hw(hw); 2875 hw->adapter_stopped = 0; 2876 2877 /* stop adapter */ 2878 ixgbe_stop_adapter(hw); 2879 2880 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++) 2881 vfinfo[vf].clear_to_send = false; 2882 2883 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2884 /* Turn off the copper */ 2885 ixgbe_set_phy_power(hw, false); 2886 } else { 2887 /* Turn off the laser */ 2888 ixgbe_disable_tx_laser(hw); 2889 } 2890 2891 ixgbe_dev_clear_queues(dev); 2892 2893 /* Clear stored conf */ 2894 dev->data->scattered_rx = 0; 2895 dev->data->lro = 0; 2896 2897 /* Clear recorded link status */ 2898 memset(&link, 0, sizeof(link)); 2899 rte_eth_linkstatus_set(dev, &link); 2900 2901 if (!rte_intr_allow_others(intr_handle)) 2902 /* resume to the default handler */ 2903 rte_intr_callback_register(intr_handle, 2904 ixgbe_dev_interrupt_handler, 2905 (void *)dev); 2906 2907 /* Clean datapath event and queue/vec mapping */ 2908 rte_intr_efd_disable(intr_handle); 2909 if (intr_handle->intr_vec != NULL) { 2910 rte_free(intr_handle->intr_vec); 2911 intr_handle->intr_vec = NULL; 2912 } 2913 2914 /* reset hierarchy commit */ 2915 tm_conf->committed = false; 2916 2917 adapter->rss_reta_updated = 0; 2918 2919 hw->adapter_stopped = true; 2920 } 2921 2922 /* 2923 * Set device link up: enable tx. 2924 */ 2925 static int 2926 ixgbe_dev_set_link_up(struct rte_eth_dev *dev) 2927 { 2928 struct ixgbe_hw *hw = 2929 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2930 if (hw->mac.type == ixgbe_mac_82599EB) { 2931 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2932 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2933 /* Not suported in bypass mode */ 2934 PMD_INIT_LOG(ERR, "Set link up is not supported " 2935 "by device id 0x%x", hw->device_id); 2936 return -ENOTSUP; 2937 } 2938 #endif 2939 } 2940 2941 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2942 /* Turn on the copper */ 2943 ixgbe_set_phy_power(hw, true); 2944 } else { 2945 /* Turn on the laser */ 2946 ixgbe_enable_tx_laser(hw); 2947 ixgbe_dev_link_update(dev, 0); 2948 } 2949 2950 return 0; 2951 } 2952 2953 /* 2954 * Set device link down: disable tx. 2955 */ 2956 static int 2957 ixgbe_dev_set_link_down(struct rte_eth_dev *dev) 2958 { 2959 struct ixgbe_hw *hw = 2960 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2961 if (hw->mac.type == ixgbe_mac_82599EB) { 2962 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2963 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2964 /* Not suported in bypass mode */ 2965 PMD_INIT_LOG(ERR, "Set link down is not supported " 2966 "by device id 0x%x", hw->device_id); 2967 return -ENOTSUP; 2968 } 2969 #endif 2970 } 2971 2972 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2973 /* Turn off the copper */ 2974 ixgbe_set_phy_power(hw, false); 2975 } else { 2976 /* Turn off the laser */ 2977 ixgbe_disable_tx_laser(hw); 2978 ixgbe_dev_link_update(dev, 0); 2979 } 2980 2981 return 0; 2982 } 2983 2984 /* 2985 * Reset and stop device. 2986 */ 2987 static int 2988 ixgbe_dev_close(struct rte_eth_dev *dev) 2989 { 2990 struct ixgbe_hw *hw = 2991 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2992 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2993 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2994 int retries = 0; 2995 int ret; 2996 2997 PMD_INIT_FUNC_TRACE(); 2998 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2999 return 0; 3000 3001 ixgbe_pf_reset_hw(hw); 3002 3003 ixgbe_dev_stop(dev); 3004 3005 ixgbe_dev_free_queues(dev); 3006 3007 ixgbe_disable_pcie_master(hw); 3008 3009 /* reprogram the RAR[0] in case user changed it. */ 3010 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 3011 3012 dev->dev_ops = NULL; 3013 dev->rx_pkt_burst = NULL; 3014 dev->tx_pkt_burst = NULL; 3015 3016 /* Unlock any pending hardware semaphore */ 3017 ixgbe_swfw_lock_reset(hw); 3018 3019 /* disable uio intr before callback unregister */ 3020 rte_intr_disable(intr_handle); 3021 3022 do { 3023 ret = rte_intr_callback_unregister(intr_handle, 3024 ixgbe_dev_interrupt_handler, dev); 3025 if (ret >= 0 || ret == -ENOENT) { 3026 break; 3027 } else if (ret != -EAGAIN) { 3028 PMD_INIT_LOG(ERR, 3029 "intr callback unregister failed: %d", 3030 ret); 3031 } 3032 rte_delay_ms(100); 3033 } while (retries++ < (10 + IXGBE_LINK_UP_TIME)); 3034 3035 /* cancel the delay handler before remove dev */ 3036 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev); 3037 3038 /* uninitialize PF if max_vfs not zero */ 3039 ixgbe_pf_host_uninit(dev); 3040 3041 /* remove all the fdir filters & hash */ 3042 ixgbe_fdir_filter_uninit(dev); 3043 3044 /* remove all the L2 tunnel filters & hash */ 3045 ixgbe_l2_tn_filter_uninit(dev); 3046 3047 /* Remove all ntuple filters of the device */ 3048 ixgbe_ntuple_filter_uninit(dev); 3049 3050 /* clear all the filters list */ 3051 ixgbe_filterlist_flush(); 3052 3053 /* Remove all Traffic Manager configuration */ 3054 ixgbe_tm_conf_uninit(dev); 3055 3056 #ifdef RTE_LIBRTE_SECURITY 3057 rte_free(dev->security_ctx); 3058 #endif 3059 3060 return 0; 3061 } 3062 3063 /* 3064 * Reset PF device. 3065 */ 3066 static int 3067 ixgbe_dev_reset(struct rte_eth_dev *dev) 3068 { 3069 int ret; 3070 3071 /* When a DPDK PMD PF begin to reset PF port, it should notify all 3072 * its VF to make them align with it. The detailed notification 3073 * mechanism is PMD specific. As to ixgbe PF, it is rather complex. 3074 * To avoid unexpected behavior in VF, currently reset of PF with 3075 * SR-IOV activation is not supported. It might be supported later. 3076 */ 3077 if (dev->data->sriov.active) 3078 return -ENOTSUP; 3079 3080 ret = eth_ixgbe_dev_uninit(dev); 3081 if (ret) 3082 return ret; 3083 3084 ret = eth_ixgbe_dev_init(dev, NULL); 3085 3086 return ret; 3087 } 3088 3089 static void 3090 ixgbe_read_stats_registers(struct ixgbe_hw *hw, 3091 struct ixgbe_hw_stats *hw_stats, 3092 struct ixgbe_macsec_stats *macsec_stats, 3093 uint64_t *total_missed_rx, uint64_t *total_qbrc, 3094 uint64_t *total_qprc, uint64_t *total_qprdc) 3095 { 3096 uint32_t bprc, lxon, lxoff, total; 3097 uint32_t delta_gprc = 0; 3098 unsigned i; 3099 /* Workaround for RX byte count not including CRC bytes when CRC 3100 * strip is enabled. CRC bytes are removed from counters when crc_strip 3101 * is disabled. 3102 */ 3103 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) & 3104 IXGBE_HLREG0_RXCRCSTRP); 3105 3106 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 3107 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC); 3108 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC); 3109 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC); 3110 3111 for (i = 0; i < 8; i++) { 3112 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 3113 3114 /* global total per queue */ 3115 hw_stats->mpc[i] += mp; 3116 /* Running comprehensive total for stats display */ 3117 *total_missed_rx += hw_stats->mpc[i]; 3118 if (hw->mac.type == ixgbe_mac_82598EB) { 3119 hw_stats->rnbc[i] += 3120 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 3121 hw_stats->pxonrxc[i] += 3122 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 3123 hw_stats->pxoffrxc[i] += 3124 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 3125 } else { 3126 hw_stats->pxonrxc[i] += 3127 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 3128 hw_stats->pxoffrxc[i] += 3129 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 3130 hw_stats->pxon2offc[i] += 3131 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 3132 } 3133 hw_stats->pxontxc[i] += 3134 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 3135 hw_stats->pxofftxc[i] += 3136 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 3137 } 3138 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3139 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 3140 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 3141 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 3142 3143 delta_gprc += delta_qprc; 3144 3145 hw_stats->qprc[i] += delta_qprc; 3146 hw_stats->qptc[i] += delta_qptc; 3147 3148 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 3149 hw_stats->qbrc[i] += 3150 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32); 3151 if (crc_strip == 0) 3152 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN; 3153 3154 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 3155 hw_stats->qbtc[i] += 3156 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32); 3157 3158 hw_stats->qprdc[i] += delta_qprdc; 3159 *total_qprdc += hw_stats->qprdc[i]; 3160 3161 *total_qprc += hw_stats->qprc[i]; 3162 *total_qbrc += hw_stats->qbrc[i]; 3163 } 3164 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC); 3165 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC); 3166 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 3167 3168 /* 3169 * An errata states that gprc actually counts good + missed packets: 3170 * Workaround to set gprc to summated queue packet receives 3171 */ 3172 hw_stats->gprc = *total_qprc; 3173 3174 if (hw->mac.type != ixgbe_mac_82598EB) { 3175 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 3176 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32); 3177 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 3178 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32); 3179 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 3180 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32); 3181 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 3182 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 3183 } else { 3184 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 3185 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 3186 /* 82598 only has a counter in the high register */ 3187 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 3188 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 3189 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 3190 } 3191 uint64_t old_tpr = hw_stats->tpr; 3192 3193 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 3194 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT); 3195 3196 if (crc_strip == 0) 3197 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN; 3198 3199 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC); 3200 hw_stats->gptc += delta_gptc; 3201 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN; 3202 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN; 3203 3204 /* 3205 * Workaround: mprc hardware is incorrectly counting 3206 * broadcasts, so for now we subtract those. 3207 */ 3208 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 3209 hw_stats->bprc += bprc; 3210 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 3211 if (hw->mac.type == ixgbe_mac_82598EB) 3212 hw_stats->mprc -= bprc; 3213 3214 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 3215 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 3216 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 3217 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 3218 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 3219 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 3220 3221 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 3222 hw_stats->lxontxc += lxon; 3223 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 3224 hw_stats->lxofftxc += lxoff; 3225 total = lxon + lxoff; 3226 3227 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 3228 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 3229 hw_stats->gptc -= total; 3230 hw_stats->mptc -= total; 3231 hw_stats->ptc64 -= total; 3232 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN; 3233 3234 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 3235 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 3236 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 3237 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 3238 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC); 3239 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC); 3240 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC); 3241 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 3242 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 3243 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 3244 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 3245 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 3246 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 3247 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC); 3248 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 3249 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST); 3250 /* Only read FCOE on 82599 */ 3251 if (hw->mac.type != ixgbe_mac_82598EB) { 3252 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 3253 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 3254 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 3255 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 3256 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 3257 } 3258 3259 /* Flow Director Stats registers */ 3260 if (hw->mac.type != ixgbe_mac_82598EB) { 3261 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 3262 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 3263 hw_stats->fdirustat_add += IXGBE_READ_REG(hw, 3264 IXGBE_FDIRUSTAT) & 0xFFFF; 3265 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw, 3266 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF; 3267 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw, 3268 IXGBE_FDIRFSTAT) & 0xFFFF; 3269 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw, 3270 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF; 3271 } 3272 /* MACsec Stats registers */ 3273 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT); 3274 macsec_stats->out_pkts_encrypted += 3275 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE); 3276 macsec_stats->out_pkts_protected += 3277 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP); 3278 macsec_stats->out_octets_encrypted += 3279 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE); 3280 macsec_stats->out_octets_protected += 3281 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP); 3282 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT); 3283 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD); 3284 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI); 3285 macsec_stats->in_pkts_unknownsci += 3286 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI); 3287 macsec_stats->in_octets_decrypted += 3288 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD); 3289 macsec_stats->in_octets_validated += 3290 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV); 3291 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH); 3292 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY); 3293 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE); 3294 for (i = 0; i < 2; i++) { 3295 macsec_stats->in_pkts_ok += 3296 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i)); 3297 macsec_stats->in_pkts_invalid += 3298 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i)); 3299 macsec_stats->in_pkts_notvalid += 3300 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i)); 3301 } 3302 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA); 3303 macsec_stats->in_pkts_notusingsa += 3304 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA); 3305 } 3306 3307 /* 3308 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c 3309 */ 3310 static int 3311 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3312 { 3313 struct ixgbe_hw *hw = 3314 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3315 struct ixgbe_hw_stats *hw_stats = 3316 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3317 struct ixgbe_macsec_stats *macsec_stats = 3318 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3319 dev->data->dev_private); 3320 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3321 unsigned i; 3322 3323 total_missed_rx = 0; 3324 total_qbrc = 0; 3325 total_qprc = 0; 3326 total_qprdc = 0; 3327 3328 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3329 &total_qbrc, &total_qprc, &total_qprdc); 3330 3331 if (stats == NULL) 3332 return -EINVAL; 3333 3334 /* Fill out the rte_eth_stats statistics structure */ 3335 stats->ipackets = total_qprc; 3336 stats->ibytes = total_qbrc; 3337 stats->opackets = hw_stats->gptc; 3338 stats->obytes = hw_stats->gotc; 3339 3340 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3341 stats->q_ipackets[i] = hw_stats->qprc[i]; 3342 stats->q_opackets[i] = hw_stats->qptc[i]; 3343 stats->q_ibytes[i] = hw_stats->qbrc[i]; 3344 stats->q_obytes[i] = hw_stats->qbtc[i]; 3345 stats->q_errors[i] = hw_stats->qprdc[i]; 3346 } 3347 3348 /* Rx Errors */ 3349 stats->imissed = total_missed_rx; 3350 stats->ierrors = hw_stats->crcerrs + 3351 hw_stats->mspdc + 3352 hw_stats->rlec + 3353 hw_stats->ruc + 3354 hw_stats->roc + 3355 hw_stats->illerrc + 3356 hw_stats->errbc + 3357 hw_stats->rfc + 3358 hw_stats->fccrc + 3359 hw_stats->fclast; 3360 3361 /* Tx Errors */ 3362 stats->oerrors = 0; 3363 return 0; 3364 } 3365 3366 static int 3367 ixgbe_dev_stats_reset(struct rte_eth_dev *dev) 3368 { 3369 struct ixgbe_hw_stats *stats = 3370 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3371 3372 /* HW registers are cleared on read */ 3373 ixgbe_dev_stats_get(dev, NULL); 3374 3375 /* Reset software totals */ 3376 memset(stats, 0, sizeof(*stats)); 3377 3378 return 0; 3379 } 3380 3381 /* This function calculates the number of xstats based on the current config */ 3382 static unsigned 3383 ixgbe_xstats_calc_num(void) { 3384 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS + 3385 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) + 3386 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES); 3387 } 3388 3389 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3390 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size) 3391 { 3392 const unsigned cnt_stats = ixgbe_xstats_calc_num(); 3393 unsigned stat, i, count; 3394 3395 if (xstats_names != NULL) { 3396 count = 0; 3397 3398 /* Note: limit >= cnt_stats checked upstream 3399 * in rte_eth_xstats_names() 3400 */ 3401 3402 /* Extended stats from ixgbe_hw_stats */ 3403 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3404 strlcpy(xstats_names[count].name, 3405 rte_ixgbe_stats_strings[i].name, 3406 sizeof(xstats_names[count].name)); 3407 count++; 3408 } 3409 3410 /* MACsec Stats */ 3411 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3412 strlcpy(xstats_names[count].name, 3413 rte_ixgbe_macsec_strings[i].name, 3414 sizeof(xstats_names[count].name)); 3415 count++; 3416 } 3417 3418 /* RX Priority Stats */ 3419 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3420 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3421 snprintf(xstats_names[count].name, 3422 sizeof(xstats_names[count].name), 3423 "rx_priority%u_%s", i, 3424 rte_ixgbe_rxq_strings[stat].name); 3425 count++; 3426 } 3427 } 3428 3429 /* TX Priority Stats */ 3430 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3431 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3432 snprintf(xstats_names[count].name, 3433 sizeof(xstats_names[count].name), 3434 "tx_priority%u_%s", i, 3435 rte_ixgbe_txq_strings[stat].name); 3436 count++; 3437 } 3438 } 3439 } 3440 return cnt_stats; 3441 } 3442 3443 static int ixgbe_dev_xstats_get_names_by_id( 3444 struct rte_eth_dev *dev, 3445 struct rte_eth_xstat_name *xstats_names, 3446 const uint64_t *ids, 3447 unsigned int limit) 3448 { 3449 if (!ids) { 3450 const unsigned int cnt_stats = ixgbe_xstats_calc_num(); 3451 unsigned int stat, i, count; 3452 3453 if (xstats_names != NULL) { 3454 count = 0; 3455 3456 /* Note: limit >= cnt_stats checked upstream 3457 * in rte_eth_xstats_names() 3458 */ 3459 3460 /* Extended stats from ixgbe_hw_stats */ 3461 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3462 strlcpy(xstats_names[count].name, 3463 rte_ixgbe_stats_strings[i].name, 3464 sizeof(xstats_names[count].name)); 3465 count++; 3466 } 3467 3468 /* MACsec Stats */ 3469 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3470 strlcpy(xstats_names[count].name, 3471 rte_ixgbe_macsec_strings[i].name, 3472 sizeof(xstats_names[count].name)); 3473 count++; 3474 } 3475 3476 /* RX Priority Stats */ 3477 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3478 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3479 snprintf(xstats_names[count].name, 3480 sizeof(xstats_names[count].name), 3481 "rx_priority%u_%s", i, 3482 rte_ixgbe_rxq_strings[stat].name); 3483 count++; 3484 } 3485 } 3486 3487 /* TX Priority Stats */ 3488 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3489 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3490 snprintf(xstats_names[count].name, 3491 sizeof(xstats_names[count].name), 3492 "tx_priority%u_%s", i, 3493 rte_ixgbe_txq_strings[stat].name); 3494 count++; 3495 } 3496 } 3497 } 3498 return cnt_stats; 3499 } 3500 3501 uint16_t i; 3502 uint16_t size = ixgbe_xstats_calc_num(); 3503 struct rte_eth_xstat_name xstats_names_copy[size]; 3504 3505 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL, 3506 size); 3507 3508 for (i = 0; i < limit; i++) { 3509 if (ids[i] >= size) { 3510 PMD_INIT_LOG(ERR, "id value isn't valid"); 3511 return -1; 3512 } 3513 strcpy(xstats_names[i].name, 3514 xstats_names_copy[ids[i]].name); 3515 } 3516 return limit; 3517 } 3518 3519 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3520 struct rte_eth_xstat_name *xstats_names, unsigned limit) 3521 { 3522 unsigned i; 3523 3524 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL) 3525 return -ENOMEM; 3526 3527 if (xstats_names != NULL) 3528 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) 3529 strlcpy(xstats_names[i].name, 3530 rte_ixgbevf_stats_strings[i].name, 3531 sizeof(xstats_names[i].name)); 3532 return IXGBEVF_NB_XSTATS; 3533 } 3534 3535 static int 3536 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3537 unsigned n) 3538 { 3539 struct ixgbe_hw *hw = 3540 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3541 struct ixgbe_hw_stats *hw_stats = 3542 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3543 struct ixgbe_macsec_stats *macsec_stats = 3544 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3545 dev->data->dev_private); 3546 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3547 unsigned i, stat, count = 0; 3548 3549 count = ixgbe_xstats_calc_num(); 3550 3551 if (n < count) 3552 return count; 3553 3554 total_missed_rx = 0; 3555 total_qbrc = 0; 3556 total_qprc = 0; 3557 total_qprdc = 0; 3558 3559 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3560 &total_qbrc, &total_qprc, &total_qprdc); 3561 3562 /* If this is a reset xstats is NULL, and we have cleared the 3563 * registers by reading them. 3564 */ 3565 if (!xstats) 3566 return 0; 3567 3568 /* Extended stats from ixgbe_hw_stats */ 3569 count = 0; 3570 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3571 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3572 rte_ixgbe_stats_strings[i].offset); 3573 xstats[count].id = count; 3574 count++; 3575 } 3576 3577 /* MACsec Stats */ 3578 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3579 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) + 3580 rte_ixgbe_macsec_strings[i].offset); 3581 xstats[count].id = count; 3582 count++; 3583 } 3584 3585 /* RX Priority Stats */ 3586 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3587 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3588 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3589 rte_ixgbe_rxq_strings[stat].offset + 3590 (sizeof(uint64_t) * i)); 3591 xstats[count].id = count; 3592 count++; 3593 } 3594 } 3595 3596 /* TX Priority Stats */ 3597 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3598 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3599 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3600 rte_ixgbe_txq_strings[stat].offset + 3601 (sizeof(uint64_t) * i)); 3602 xstats[count].id = count; 3603 count++; 3604 } 3605 } 3606 return count; 3607 } 3608 3609 static int 3610 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 3611 uint64_t *values, unsigned int n) 3612 { 3613 if (!ids) { 3614 struct ixgbe_hw *hw = 3615 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3616 struct ixgbe_hw_stats *hw_stats = 3617 IXGBE_DEV_PRIVATE_TO_STATS( 3618 dev->data->dev_private); 3619 struct ixgbe_macsec_stats *macsec_stats = 3620 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3621 dev->data->dev_private); 3622 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3623 unsigned int i, stat, count = 0; 3624 3625 count = ixgbe_xstats_calc_num(); 3626 3627 if (!ids && n < count) 3628 return count; 3629 3630 total_missed_rx = 0; 3631 total_qbrc = 0; 3632 total_qprc = 0; 3633 total_qprdc = 0; 3634 3635 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, 3636 &total_missed_rx, &total_qbrc, &total_qprc, 3637 &total_qprdc); 3638 3639 /* If this is a reset xstats is NULL, and we have cleared the 3640 * registers by reading them. 3641 */ 3642 if (!ids && !values) 3643 return 0; 3644 3645 /* Extended stats from ixgbe_hw_stats */ 3646 count = 0; 3647 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3648 values[count] = *(uint64_t *)(((char *)hw_stats) + 3649 rte_ixgbe_stats_strings[i].offset); 3650 count++; 3651 } 3652 3653 /* MACsec Stats */ 3654 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3655 values[count] = *(uint64_t *)(((char *)macsec_stats) + 3656 rte_ixgbe_macsec_strings[i].offset); 3657 count++; 3658 } 3659 3660 /* RX Priority Stats */ 3661 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3662 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3663 values[count] = 3664 *(uint64_t *)(((char *)hw_stats) + 3665 rte_ixgbe_rxq_strings[stat].offset + 3666 (sizeof(uint64_t) * i)); 3667 count++; 3668 } 3669 } 3670 3671 /* TX Priority Stats */ 3672 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3673 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3674 values[count] = 3675 *(uint64_t *)(((char *)hw_stats) + 3676 rte_ixgbe_txq_strings[stat].offset + 3677 (sizeof(uint64_t) * i)); 3678 count++; 3679 } 3680 } 3681 return count; 3682 } 3683 3684 uint16_t i; 3685 uint16_t size = ixgbe_xstats_calc_num(); 3686 uint64_t values_copy[size]; 3687 3688 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size); 3689 3690 for (i = 0; i < n; i++) { 3691 if (ids[i] >= size) { 3692 PMD_INIT_LOG(ERR, "id value isn't valid"); 3693 return -1; 3694 } 3695 values[i] = values_copy[ids[i]]; 3696 } 3697 return n; 3698 } 3699 3700 static int 3701 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev) 3702 { 3703 struct ixgbe_hw_stats *stats = 3704 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3705 struct ixgbe_macsec_stats *macsec_stats = 3706 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3707 dev->data->dev_private); 3708 3709 unsigned count = ixgbe_xstats_calc_num(); 3710 3711 /* HW registers are cleared on read */ 3712 ixgbe_dev_xstats_get(dev, NULL, count); 3713 3714 /* Reset software totals */ 3715 memset(stats, 0, sizeof(*stats)); 3716 memset(macsec_stats, 0, sizeof(*macsec_stats)); 3717 3718 return 0; 3719 } 3720 3721 static void 3722 ixgbevf_update_stats(struct rte_eth_dev *dev) 3723 { 3724 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3725 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3726 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3727 3728 /* Good Rx packet, include VF loopback */ 3729 UPDATE_VF_STAT(IXGBE_VFGPRC, 3730 hw_stats->last_vfgprc, hw_stats->vfgprc); 3731 3732 /* Good Rx octets, include VF loopback */ 3733 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB, 3734 hw_stats->last_vfgorc, hw_stats->vfgorc); 3735 3736 /* Good Tx packet, include VF loopback */ 3737 UPDATE_VF_STAT(IXGBE_VFGPTC, 3738 hw_stats->last_vfgptc, hw_stats->vfgptc); 3739 3740 /* Good Tx octets, include VF loopback */ 3741 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB, 3742 hw_stats->last_vfgotc, hw_stats->vfgotc); 3743 3744 /* Rx Multicst Packet */ 3745 UPDATE_VF_STAT(IXGBE_VFMPRC, 3746 hw_stats->last_vfmprc, hw_stats->vfmprc); 3747 } 3748 3749 static int 3750 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3751 unsigned n) 3752 { 3753 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3754 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3755 unsigned i; 3756 3757 if (n < IXGBEVF_NB_XSTATS) 3758 return IXGBEVF_NB_XSTATS; 3759 3760 ixgbevf_update_stats(dev); 3761 3762 if (!xstats) 3763 return 0; 3764 3765 /* Extended stats */ 3766 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) { 3767 xstats[i].id = i; 3768 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + 3769 rte_ixgbevf_stats_strings[i].offset); 3770 } 3771 3772 return IXGBEVF_NB_XSTATS; 3773 } 3774 3775 static int 3776 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3777 { 3778 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3779 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3780 3781 ixgbevf_update_stats(dev); 3782 3783 if (stats == NULL) 3784 return -EINVAL; 3785 3786 stats->ipackets = hw_stats->vfgprc; 3787 stats->ibytes = hw_stats->vfgorc; 3788 stats->opackets = hw_stats->vfgptc; 3789 stats->obytes = hw_stats->vfgotc; 3790 return 0; 3791 } 3792 3793 static int 3794 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev) 3795 { 3796 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3797 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3798 3799 /* Sync HW register to the last stats */ 3800 ixgbevf_dev_stats_get(dev, NULL); 3801 3802 /* reset HW current stats*/ 3803 hw_stats->vfgprc = 0; 3804 hw_stats->vfgorc = 0; 3805 hw_stats->vfgptc = 0; 3806 hw_stats->vfgotc = 0; 3807 3808 return 0; 3809 } 3810 3811 static int 3812 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 3813 { 3814 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3815 u16 eeprom_verh, eeprom_verl; 3816 u32 etrack_id; 3817 int ret; 3818 3819 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh); 3820 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl); 3821 3822 etrack_id = (eeprom_verh << 16) | eeprom_verl; 3823 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id); 3824 3825 ret += 1; /* add the size of '\0' */ 3826 if (fw_size < (u32)ret) 3827 return ret; 3828 else 3829 return 0; 3830 } 3831 3832 static int 3833 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3834 { 3835 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3836 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3837 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 3838 3839 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3840 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3841 if (RTE_ETH_DEV_SRIOV(dev).active == 0) { 3842 /* 3843 * When DCB/VT is off, maximum number of queues changes, 3844 * except for 82598EB, which remains constant. 3845 */ 3846 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 3847 hw->mac.type != ixgbe_mac_82598EB) 3848 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES; 3849 } 3850 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */ 3851 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */ 3852 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3853 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3854 dev_info->max_vfs = pci_dev->max_vfs; 3855 if (hw->mac.type == ixgbe_mac_82598EB) 3856 dev_info->max_vmdq_pools = ETH_16_POOLS; 3857 else 3858 dev_info->max_vmdq_pools = ETH_64_POOLS; 3859 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD; 3860 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 3861 dev_info->vmdq_queue_num = dev_info->max_rx_queues; 3862 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3863 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3864 dev_info->rx_queue_offload_capa); 3865 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3866 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3867 3868 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3869 .rx_thresh = { 3870 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3871 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3872 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3873 }, 3874 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3875 .rx_drop_en = 0, 3876 .offloads = 0, 3877 }; 3878 3879 dev_info->default_txconf = (struct rte_eth_txconf) { 3880 .tx_thresh = { 3881 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3882 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3883 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3884 }, 3885 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3886 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3887 .offloads = 0, 3888 }; 3889 3890 dev_info->rx_desc_lim = rx_desc_lim; 3891 dev_info->tx_desc_lim = tx_desc_lim; 3892 3893 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 3894 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 3895 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 3896 3897 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 3898 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 3899 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 3900 dev_info->speed_capa = ETH_LINK_SPEED_10M | 3901 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G; 3902 3903 if (hw->mac.type == ixgbe_mac_X540 || 3904 hw->mac.type == ixgbe_mac_X540_vf || 3905 hw->mac.type == ixgbe_mac_X550 || 3906 hw->mac.type == ixgbe_mac_X550_vf) { 3907 dev_info->speed_capa |= ETH_LINK_SPEED_100M; 3908 } 3909 if (hw->mac.type == ixgbe_mac_X550) { 3910 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G; 3911 dev_info->speed_capa |= ETH_LINK_SPEED_5G; 3912 } 3913 3914 /* Driver-preferred Rx/Tx parameters */ 3915 dev_info->default_rxportconf.burst_size = 32; 3916 dev_info->default_txportconf.burst_size = 32; 3917 dev_info->default_rxportconf.nb_queues = 1; 3918 dev_info->default_txportconf.nb_queues = 1; 3919 dev_info->default_rxportconf.ring_size = 256; 3920 dev_info->default_txportconf.ring_size = 256; 3921 3922 return 0; 3923 } 3924 3925 static const uint32_t * 3926 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 3927 { 3928 static const uint32_t ptypes[] = { 3929 /* For non-vec functions, 3930 * refers to ixgbe_rxd_pkt_info_to_pkt_type(); 3931 * for vec functions, 3932 * refers to _recv_raw_pkts_vec(). 3933 */ 3934 RTE_PTYPE_L2_ETHER, 3935 RTE_PTYPE_L3_IPV4, 3936 RTE_PTYPE_L3_IPV4_EXT, 3937 RTE_PTYPE_L3_IPV6, 3938 RTE_PTYPE_L3_IPV6_EXT, 3939 RTE_PTYPE_L4_SCTP, 3940 RTE_PTYPE_L4_TCP, 3941 RTE_PTYPE_L4_UDP, 3942 RTE_PTYPE_TUNNEL_IP, 3943 RTE_PTYPE_INNER_L3_IPV6, 3944 RTE_PTYPE_INNER_L3_IPV6_EXT, 3945 RTE_PTYPE_INNER_L4_TCP, 3946 RTE_PTYPE_INNER_L4_UDP, 3947 RTE_PTYPE_UNKNOWN 3948 }; 3949 3950 if (dev->rx_pkt_burst == ixgbe_recv_pkts || 3951 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc || 3952 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc || 3953 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc) 3954 return ptypes; 3955 3956 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON) 3957 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec || 3958 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec) 3959 return ptypes; 3960 #endif 3961 return NULL; 3962 } 3963 3964 static int 3965 ixgbevf_dev_info_get(struct rte_eth_dev *dev, 3966 struct rte_eth_dev_info *dev_info) 3967 { 3968 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3969 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3970 3971 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3972 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3973 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */ 3974 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */ 3975 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD; 3976 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3977 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3978 dev_info->max_vfs = pci_dev->max_vfs; 3979 if (hw->mac.type == ixgbe_mac_82598EB) 3980 dev_info->max_vmdq_pools = ETH_16_POOLS; 3981 else 3982 dev_info->max_vmdq_pools = ETH_64_POOLS; 3983 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3984 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3985 dev_info->rx_queue_offload_capa); 3986 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3987 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3988 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 3989 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 3990 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 3991 3992 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3993 .rx_thresh = { 3994 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3995 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3996 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3997 }, 3998 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3999 .rx_drop_en = 0, 4000 .offloads = 0, 4001 }; 4002 4003 dev_info->default_txconf = (struct rte_eth_txconf) { 4004 .tx_thresh = { 4005 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 4006 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 4007 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 4008 }, 4009 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 4010 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 4011 .offloads = 0, 4012 }; 4013 4014 dev_info->rx_desc_lim = rx_desc_lim; 4015 dev_info->tx_desc_lim = tx_desc_lim; 4016 4017 return 0; 4018 } 4019 4020 static int 4021 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4022 bool *link_up, int wait_to_complete) 4023 { 4024 struct ixgbe_adapter *adapter = container_of(hw, 4025 struct ixgbe_adapter, hw); 4026 struct ixgbe_mbx_info *mbx = &hw->mbx; 4027 struct ixgbe_mac_info *mac = &hw->mac; 4028 uint32_t links_reg, in_msg; 4029 int ret_val = 0; 4030 4031 /* If we were hit with a reset drop the link */ 4032 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout) 4033 mac->get_link_status = true; 4034 4035 if (!mac->get_link_status) 4036 goto out; 4037 4038 /* if link status is down no point in checking to see if pf is up */ 4039 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 4040 if (!(links_reg & IXGBE_LINKS_UP)) 4041 goto out; 4042 4043 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs 4044 * before the link status is correct 4045 */ 4046 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) { 4047 int i; 4048 4049 for (i = 0; i < 5; i++) { 4050 rte_delay_us(100); 4051 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 4052 4053 if (!(links_reg & IXGBE_LINKS_UP)) 4054 goto out; 4055 } 4056 } 4057 4058 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 4059 case IXGBE_LINKS_SPEED_10G_82599: 4060 *speed = IXGBE_LINK_SPEED_10GB_FULL; 4061 if (hw->mac.type >= ixgbe_mac_X550) { 4062 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4063 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4064 } 4065 break; 4066 case IXGBE_LINKS_SPEED_1G_82599: 4067 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4068 break; 4069 case IXGBE_LINKS_SPEED_100_82599: 4070 *speed = IXGBE_LINK_SPEED_100_FULL; 4071 if (hw->mac.type == ixgbe_mac_X550) { 4072 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4073 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4074 } 4075 break; 4076 case IXGBE_LINKS_SPEED_10_X550EM_A: 4077 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4078 /* Since Reserved in older MAC's */ 4079 if (hw->mac.type >= ixgbe_mac_X550) 4080 *speed = IXGBE_LINK_SPEED_10_FULL; 4081 break; 4082 default: 4083 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4084 } 4085 4086 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) { 4087 if (*speed == IXGBE_LINK_SPEED_UNKNOWN) 4088 mac->get_link_status = true; 4089 else 4090 mac->get_link_status = false; 4091 4092 goto out; 4093 } 4094 4095 /* if the read failed it could just be a mailbox collision, best wait 4096 * until we are called again and don't report an error 4097 */ 4098 if (mbx->ops.read(hw, &in_msg, 1, 0)) 4099 goto out; 4100 4101 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) { 4102 /* msg is not CTS and is NACK we must have lost CTS status */ 4103 if (in_msg & IXGBE_VT_MSGTYPE_NACK) 4104 mac->get_link_status = false; 4105 goto out; 4106 } 4107 4108 /* the pf is talking, if we timed out in the past we reinit */ 4109 if (!mbx->timeout) { 4110 ret_val = -1; 4111 goto out; 4112 } 4113 4114 /* if we passed all the tests above then the link is up and we no 4115 * longer need to check for link 4116 */ 4117 mac->get_link_status = false; 4118 4119 out: 4120 *link_up = !mac->get_link_status; 4121 return ret_val; 4122 } 4123 4124 /* 4125 * If @timeout_ms was 0, it means that it will not return until link complete. 4126 * It returns 1 on complete, return 0 on timeout. 4127 */ 4128 static int 4129 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms) 4130 { 4131 #define WARNING_TIMEOUT 9000 /* 9s in total */ 4132 struct ixgbe_adapter *ad = dev->data->dev_private; 4133 uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT; 4134 4135 while (rte_atomic32_read(&ad->link_thread_running)) { 4136 msec_delay(1); 4137 timeout--; 4138 4139 if (timeout_ms) { 4140 if (!timeout) 4141 return 0; 4142 } else if (!timeout) { 4143 /* It will not return until link complete */ 4144 timeout = WARNING_TIMEOUT; 4145 PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!"); 4146 } 4147 } 4148 4149 return 1; 4150 } 4151 4152 static void * 4153 ixgbe_dev_setup_link_thread_handler(void *param) 4154 { 4155 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4156 struct ixgbe_adapter *ad = dev->data->dev_private; 4157 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4158 struct ixgbe_interrupt *intr = 4159 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4160 u32 speed; 4161 bool autoneg = false; 4162 4163 pthread_detach(pthread_self()); 4164 speed = hw->phy.autoneg_advertised; 4165 if (!speed) 4166 ixgbe_get_link_capabilities(hw, &speed, &autoneg); 4167 4168 ixgbe_setup_link(hw, speed, true); 4169 4170 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 4171 rte_atomic32_clear(&ad->link_thread_running); 4172 return NULL; 4173 } 4174 4175 /* 4176 * In freebsd environment, nic_uio drivers do not support interrupts, 4177 * rte_intr_callback_register() will fail to register interrupts. 4178 * We can not make link status to change from down to up by interrupt 4179 * callback. So we need to wait for the controller to acquire link 4180 * when ports start. 4181 * It returns 0 on link up. 4182 */ 4183 static int 4184 ixgbe_wait_for_link_up(struct ixgbe_hw *hw) 4185 { 4186 #ifdef RTE_EXEC_ENV_FREEBSD 4187 int err, i; 4188 bool link_up = false; 4189 uint32_t speed = 0; 4190 const int nb_iter = 25; 4191 4192 for (i = 0; i < nb_iter; i++) { 4193 err = ixgbe_check_link(hw, &speed, &link_up, 0); 4194 if (err) 4195 return err; 4196 if (link_up) 4197 return 0; 4198 msec_delay(200); 4199 } 4200 4201 return 0; 4202 #else 4203 RTE_SET_USED(hw); 4204 return 0; 4205 #endif 4206 } 4207 4208 /* return 0 means link status changed, -1 means not changed */ 4209 int 4210 ixgbe_dev_link_update_share(struct rte_eth_dev *dev, 4211 int wait_to_complete, int vf) 4212 { 4213 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4214 struct ixgbe_adapter *ad = dev->data->dev_private; 4215 struct rte_eth_link link; 4216 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4217 struct ixgbe_interrupt *intr = 4218 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4219 bool link_up; 4220 int diag; 4221 int wait = 1; 4222 u32 esdp_reg; 4223 4224 memset(&link, 0, sizeof(link)); 4225 link.link_status = ETH_LINK_DOWN; 4226 link.link_speed = ETH_SPEED_NUM_NONE; 4227 link.link_duplex = ETH_LINK_HALF_DUPLEX; 4228 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 4229 ETH_LINK_SPEED_FIXED); 4230 4231 hw->mac.get_link_status = true; 4232 4233 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) 4234 return rte_eth_linkstatus_set(dev, &link); 4235 4236 /* check if it needs to wait to complete, if lsc interrupt is enabled */ 4237 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0) 4238 wait = 0; 4239 4240 /* BSD has no interrupt mechanism, so force NIC status synchronization. */ 4241 #ifdef RTE_EXEC_ENV_FREEBSD 4242 wait = 1; 4243 #endif 4244 4245 if (vf) 4246 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait); 4247 else 4248 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait); 4249 4250 if (diag != 0) { 4251 link.link_speed = ETH_SPEED_NUM_100M; 4252 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4253 return rte_eth_linkstatus_set(dev, &link); 4254 } 4255 4256 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) { 4257 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 4258 if ((esdp_reg & IXGBE_ESDP_SDP3)) 4259 link_up = 0; 4260 } 4261 4262 if (link_up == 0) { 4263 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) { 4264 ixgbe_dev_wait_setup_link_complete(dev, 0); 4265 if (rte_atomic32_test_and_set(&ad->link_thread_running)) { 4266 /* To avoid race condition between threads, set 4267 * the IXGBE_FLAG_NEED_LINK_CONFIG flag only 4268 * when there is no link thread running. 4269 */ 4270 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 4271 if (rte_ctrl_thread_create(&ad->link_thread_tid, 4272 "ixgbe-link-handler", 4273 NULL, 4274 ixgbe_dev_setup_link_thread_handler, 4275 dev) < 0) { 4276 PMD_DRV_LOG(ERR, 4277 "Create link thread failed!"); 4278 rte_atomic32_clear(&ad->link_thread_running); 4279 } 4280 } else { 4281 PMD_DRV_LOG(ERR, 4282 "Other link thread is running now!"); 4283 } 4284 } 4285 return rte_eth_linkstatus_set(dev, &link); 4286 } 4287 4288 link.link_status = ETH_LINK_UP; 4289 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4290 4291 switch (link_speed) { 4292 default: 4293 case IXGBE_LINK_SPEED_UNKNOWN: 4294 link.link_speed = ETH_SPEED_NUM_UNKNOWN; 4295 break; 4296 4297 case IXGBE_LINK_SPEED_10_FULL: 4298 link.link_speed = ETH_SPEED_NUM_10M; 4299 break; 4300 4301 case IXGBE_LINK_SPEED_100_FULL: 4302 link.link_speed = ETH_SPEED_NUM_100M; 4303 break; 4304 4305 case IXGBE_LINK_SPEED_1GB_FULL: 4306 link.link_speed = ETH_SPEED_NUM_1G; 4307 break; 4308 4309 case IXGBE_LINK_SPEED_2_5GB_FULL: 4310 link.link_speed = ETH_SPEED_NUM_2_5G; 4311 break; 4312 4313 case IXGBE_LINK_SPEED_5GB_FULL: 4314 link.link_speed = ETH_SPEED_NUM_5G; 4315 break; 4316 4317 case IXGBE_LINK_SPEED_10GB_FULL: 4318 link.link_speed = ETH_SPEED_NUM_10G; 4319 break; 4320 } 4321 4322 return rte_eth_linkstatus_set(dev, &link); 4323 } 4324 4325 static int 4326 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4327 { 4328 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0); 4329 } 4330 4331 static int 4332 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4333 { 4334 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1); 4335 } 4336 4337 static int 4338 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 4339 { 4340 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4341 uint32_t fctrl; 4342 4343 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4344 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4345 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4346 4347 return 0; 4348 } 4349 4350 static int 4351 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 4352 { 4353 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4354 uint32_t fctrl; 4355 4356 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4357 fctrl &= (~IXGBE_FCTRL_UPE); 4358 if (dev->data->all_multicast == 1) 4359 fctrl |= IXGBE_FCTRL_MPE; 4360 else 4361 fctrl &= (~IXGBE_FCTRL_MPE); 4362 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4363 4364 return 0; 4365 } 4366 4367 static int 4368 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 4369 { 4370 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4371 uint32_t fctrl; 4372 4373 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4374 fctrl |= IXGBE_FCTRL_MPE; 4375 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4376 4377 return 0; 4378 } 4379 4380 static int 4381 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 4382 { 4383 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4384 uint32_t fctrl; 4385 4386 if (dev->data->promiscuous == 1) 4387 return 0; /* must remain in all_multicast mode */ 4388 4389 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4390 fctrl &= (~IXGBE_FCTRL_MPE); 4391 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4392 4393 return 0; 4394 } 4395 4396 /** 4397 * It clears the interrupt causes and enables the interrupt. 4398 * It will be called once only during nic initialized. 4399 * 4400 * @param dev 4401 * Pointer to struct rte_eth_dev. 4402 * @param on 4403 * Enable or Disable. 4404 * 4405 * @return 4406 * - On success, zero. 4407 * - On failure, a negative value. 4408 */ 4409 static int 4410 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 4411 { 4412 struct ixgbe_interrupt *intr = 4413 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4414 4415 ixgbe_dev_link_status_print(dev); 4416 if (on) 4417 intr->mask |= IXGBE_EICR_LSC; 4418 else 4419 intr->mask &= ~IXGBE_EICR_LSC; 4420 4421 return 0; 4422 } 4423 4424 /** 4425 * It clears the interrupt causes and enables the interrupt. 4426 * It will be called once only during nic initialized. 4427 * 4428 * @param dev 4429 * Pointer to struct rte_eth_dev. 4430 * 4431 * @return 4432 * - On success, zero. 4433 * - On failure, a negative value. 4434 */ 4435 static int 4436 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev) 4437 { 4438 struct ixgbe_interrupt *intr = 4439 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4440 4441 intr->mask |= IXGBE_EICR_RTX_QUEUE; 4442 4443 return 0; 4444 } 4445 4446 /** 4447 * It clears the interrupt causes and enables the interrupt. 4448 * It will be called once only during nic initialized. 4449 * 4450 * @param dev 4451 * Pointer to struct rte_eth_dev. 4452 * 4453 * @return 4454 * - On success, zero. 4455 * - On failure, a negative value. 4456 */ 4457 static int 4458 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev) 4459 { 4460 struct ixgbe_interrupt *intr = 4461 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4462 4463 intr->mask |= IXGBE_EICR_LINKSEC; 4464 4465 return 0; 4466 } 4467 4468 /* 4469 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update. 4470 * 4471 * @param dev 4472 * Pointer to struct rte_eth_dev. 4473 * 4474 * @return 4475 * - On success, zero. 4476 * - On failure, a negative value. 4477 */ 4478 static int 4479 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev) 4480 { 4481 uint32_t eicr; 4482 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4483 struct ixgbe_interrupt *intr = 4484 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4485 4486 /* clear all cause mask */ 4487 ixgbe_disable_intr(hw); 4488 4489 /* read-on-clear nic registers here */ 4490 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4491 PMD_DRV_LOG(DEBUG, "eicr %x", eicr); 4492 4493 intr->flags = 0; 4494 4495 /* set flag for async link update */ 4496 if (eicr & IXGBE_EICR_LSC) 4497 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 4498 4499 if (eicr & IXGBE_EICR_MAILBOX) 4500 intr->flags |= IXGBE_FLAG_MAILBOX; 4501 4502 if (eicr & IXGBE_EICR_LINKSEC) 4503 intr->flags |= IXGBE_FLAG_MACSEC; 4504 4505 if (hw->mac.type == ixgbe_mac_X550EM_x && 4506 hw->phy.type == ixgbe_phy_x550em_ext_t && 4507 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x)) 4508 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT; 4509 4510 return 0; 4511 } 4512 4513 /** 4514 * It gets and then prints the link status. 4515 * 4516 * @param dev 4517 * Pointer to struct rte_eth_dev. 4518 * 4519 * @return 4520 * - On success, zero. 4521 * - On failure, a negative value. 4522 */ 4523 static void 4524 ixgbe_dev_link_status_print(struct rte_eth_dev *dev) 4525 { 4526 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4527 struct rte_eth_link link; 4528 4529 rte_eth_linkstatus_get(dev, &link); 4530 4531 if (link.link_status) { 4532 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", 4533 (int)(dev->data->port_id), 4534 (unsigned)link.link_speed, 4535 link.link_duplex == ETH_LINK_FULL_DUPLEX ? 4536 "full-duplex" : "half-duplex"); 4537 } else { 4538 PMD_INIT_LOG(INFO, " Port %d: Link Down", 4539 (int)(dev->data->port_id)); 4540 } 4541 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 4542 pci_dev->addr.domain, 4543 pci_dev->addr.bus, 4544 pci_dev->addr.devid, 4545 pci_dev->addr.function); 4546 } 4547 4548 /* 4549 * It executes link_update after knowing an interrupt occurred. 4550 * 4551 * @param dev 4552 * Pointer to struct rte_eth_dev. 4553 * 4554 * @return 4555 * - On success, zero. 4556 * - On failure, a negative value. 4557 */ 4558 static int 4559 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev) 4560 { 4561 struct ixgbe_interrupt *intr = 4562 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4563 int64_t timeout; 4564 struct ixgbe_hw *hw = 4565 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4566 4567 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags); 4568 4569 if (intr->flags & IXGBE_FLAG_MAILBOX) { 4570 ixgbe_pf_mbx_process(dev); 4571 intr->flags &= ~IXGBE_FLAG_MAILBOX; 4572 } 4573 4574 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4575 ixgbe_handle_lasi(hw); 4576 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4577 } 4578 4579 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4580 struct rte_eth_link link; 4581 4582 /* get the link status before link update, for predicting later */ 4583 rte_eth_linkstatus_get(dev, &link); 4584 4585 ixgbe_dev_link_update(dev, 0); 4586 4587 /* likely to up */ 4588 if (!link.link_status) 4589 /* handle it 1 sec later, wait it being stable */ 4590 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT; 4591 /* likely to down */ 4592 else 4593 /* handle it 4 sec later, wait it being stable */ 4594 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT; 4595 4596 ixgbe_dev_link_status_print(dev); 4597 if (rte_eal_alarm_set(timeout * 1000, 4598 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0) 4599 PMD_DRV_LOG(ERR, "Error setting alarm"); 4600 else { 4601 /* remember original mask */ 4602 intr->mask_original = intr->mask; 4603 /* only disable lsc interrupt */ 4604 intr->mask &= ~IXGBE_EIMS_LSC; 4605 } 4606 } 4607 4608 PMD_DRV_LOG(DEBUG, "enable intr immediately"); 4609 ixgbe_enable_intr(dev); 4610 4611 return 0; 4612 } 4613 4614 /** 4615 * Interrupt handler which shall be registered for alarm callback for delayed 4616 * handling specific interrupt to wait for the stable nic state. As the 4617 * NIC interrupt state is not stable for ixgbe after link is just down, 4618 * it needs to wait 4 seconds to get the stable status. 4619 * 4620 * @param handle 4621 * Pointer to interrupt handle. 4622 * @param param 4623 * The address of parameter (struct rte_eth_dev *) regsitered before. 4624 * 4625 * @return 4626 * void 4627 */ 4628 static void 4629 ixgbe_dev_interrupt_delayed_handler(void *param) 4630 { 4631 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4632 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4633 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4634 struct ixgbe_interrupt *intr = 4635 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4636 struct ixgbe_hw *hw = 4637 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4638 uint32_t eicr; 4639 4640 ixgbe_disable_intr(hw); 4641 4642 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4643 if (eicr & IXGBE_EICR_MAILBOX) 4644 ixgbe_pf_mbx_process(dev); 4645 4646 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4647 ixgbe_handle_lasi(hw); 4648 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4649 } 4650 4651 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4652 ixgbe_dev_link_update(dev, 0); 4653 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 4654 ixgbe_dev_link_status_print(dev); 4655 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 4656 } 4657 4658 if (intr->flags & IXGBE_FLAG_MACSEC) { 4659 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL); 4660 intr->flags &= ~IXGBE_FLAG_MACSEC; 4661 } 4662 4663 /* restore original mask */ 4664 intr->mask = intr->mask_original; 4665 intr->mask_original = 0; 4666 4667 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr); 4668 ixgbe_enable_intr(dev); 4669 rte_intr_ack(intr_handle); 4670 } 4671 4672 /** 4673 * Interrupt handler triggered by NIC for handling 4674 * specific interrupt. 4675 * 4676 * @param handle 4677 * Pointer to interrupt handle. 4678 * @param param 4679 * The address of parameter (struct rte_eth_dev *) regsitered before. 4680 * 4681 * @return 4682 * void 4683 */ 4684 static void 4685 ixgbe_dev_interrupt_handler(void *param) 4686 { 4687 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4688 4689 ixgbe_dev_interrupt_get_status(dev); 4690 ixgbe_dev_interrupt_action(dev); 4691 } 4692 4693 static int 4694 ixgbe_dev_led_on(struct rte_eth_dev *dev) 4695 { 4696 struct ixgbe_hw *hw; 4697 4698 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4699 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4700 } 4701 4702 static int 4703 ixgbe_dev_led_off(struct rte_eth_dev *dev) 4704 { 4705 struct ixgbe_hw *hw; 4706 4707 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4708 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4709 } 4710 4711 static int 4712 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4713 { 4714 struct ixgbe_hw *hw; 4715 uint32_t mflcn_reg; 4716 uint32_t fccfg_reg; 4717 int rx_pause; 4718 int tx_pause; 4719 4720 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4721 4722 fc_conf->pause_time = hw->fc.pause_time; 4723 fc_conf->high_water = hw->fc.high_water[0]; 4724 fc_conf->low_water = hw->fc.low_water[0]; 4725 fc_conf->send_xon = hw->fc.send_xon; 4726 fc_conf->autoneg = !hw->fc.disable_fc_autoneg; 4727 4728 /* 4729 * Return rx_pause status according to actual setting of 4730 * MFLCN register. 4731 */ 4732 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4733 if (mflcn_reg & IXGBE_MFLCN_PMCF) 4734 fc_conf->mac_ctrl_frame_fwd = 1; 4735 else 4736 fc_conf->mac_ctrl_frame_fwd = 0; 4737 4738 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE)) 4739 rx_pause = 1; 4740 else 4741 rx_pause = 0; 4742 4743 /* 4744 * Return tx_pause status according to actual setting of 4745 * FCCFG register. 4746 */ 4747 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4748 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY)) 4749 tx_pause = 1; 4750 else 4751 tx_pause = 0; 4752 4753 if (rx_pause && tx_pause) 4754 fc_conf->mode = RTE_FC_FULL; 4755 else if (rx_pause) 4756 fc_conf->mode = RTE_FC_RX_PAUSE; 4757 else if (tx_pause) 4758 fc_conf->mode = RTE_FC_TX_PAUSE; 4759 else 4760 fc_conf->mode = RTE_FC_NONE; 4761 4762 return 0; 4763 } 4764 4765 static int 4766 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4767 { 4768 struct ixgbe_hw *hw; 4769 struct ixgbe_adapter *adapter = dev->data->dev_private; 4770 int err; 4771 uint32_t rx_buf_size; 4772 uint32_t max_high_water; 4773 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4774 ixgbe_fc_none, 4775 ixgbe_fc_rx_pause, 4776 ixgbe_fc_tx_pause, 4777 ixgbe_fc_full 4778 }; 4779 4780 PMD_INIT_FUNC_TRACE(); 4781 4782 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4783 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)); 4784 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4785 4786 /* 4787 * At least reserve one Ethernet frame for watermark 4788 * high_water/low_water in kilo bytes for ixgbe 4789 */ 4790 max_high_water = (rx_buf_size - 4791 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4792 if ((fc_conf->high_water > max_high_water) || 4793 (fc_conf->high_water < fc_conf->low_water)) { 4794 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4795 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4796 return -EINVAL; 4797 } 4798 4799 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode]; 4800 hw->fc.pause_time = fc_conf->pause_time; 4801 hw->fc.high_water[0] = fc_conf->high_water; 4802 hw->fc.low_water[0] = fc_conf->low_water; 4803 hw->fc.send_xon = fc_conf->send_xon; 4804 hw->fc.disable_fc_autoneg = !fc_conf->autoneg; 4805 adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; 4806 4807 err = ixgbe_flow_ctrl_enable(dev, hw); 4808 if (err < 0) { 4809 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err); 4810 return -EIO; 4811 } 4812 return err; 4813 } 4814 4815 /** 4816 * ixgbe_pfc_enable_generic - Enable flow control 4817 * @hw: pointer to hardware structure 4818 * @tc_num: traffic class number 4819 * Enable flow control according to the current settings. 4820 */ 4821 static int 4822 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num) 4823 { 4824 int ret_val = 0; 4825 uint32_t mflcn_reg, fccfg_reg; 4826 uint32_t reg; 4827 uint32_t fcrtl, fcrth; 4828 uint8_t i; 4829 uint8_t nb_rx_en; 4830 4831 /* Validate the water mark configuration */ 4832 if (!hw->fc.pause_time) { 4833 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4834 goto out; 4835 } 4836 4837 /* Low water mark of zero causes XOFF floods */ 4838 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 4839 /* High/Low water can not be 0 */ 4840 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) { 4841 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4842 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4843 goto out; 4844 } 4845 4846 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) { 4847 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4848 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4849 goto out; 4850 } 4851 } 4852 /* Negotiate the fc mode to use */ 4853 ixgbe_fc_autoneg(hw); 4854 4855 /* Disable any previous flow control settings */ 4856 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4857 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE); 4858 4859 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4860 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 4861 4862 switch (hw->fc.current_mode) { 4863 case ixgbe_fc_none: 4864 /* 4865 * If the count of enabled RX Priority Flow control >1, 4866 * and the TX pause can not be disabled 4867 */ 4868 nb_rx_en = 0; 4869 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4870 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4871 if (reg & IXGBE_FCRTH_FCEN) 4872 nb_rx_en++; 4873 } 4874 if (nb_rx_en > 1) 4875 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4876 break; 4877 case ixgbe_fc_rx_pause: 4878 /* 4879 * Rx Flow control is enabled and Tx Flow control is 4880 * disabled by software override. Since there really 4881 * isn't a way to advertise that we are capable of RX 4882 * Pause ONLY, we will advertise that we support both 4883 * symmetric and asymmetric Rx PAUSE. Later, we will 4884 * disable the adapter's ability to send PAUSE frames. 4885 */ 4886 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4887 /* 4888 * If the count of enabled RX Priority Flow control >1, 4889 * and the TX pause can not be disabled 4890 */ 4891 nb_rx_en = 0; 4892 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4893 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4894 if (reg & IXGBE_FCRTH_FCEN) 4895 nb_rx_en++; 4896 } 4897 if (nb_rx_en > 1) 4898 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4899 break; 4900 case ixgbe_fc_tx_pause: 4901 /* 4902 * Tx Flow control is enabled, and Rx Flow control is 4903 * disabled by software override. 4904 */ 4905 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4906 break; 4907 case ixgbe_fc_full: 4908 /* Flow control (both Rx and Tx) is enabled by SW override. */ 4909 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4910 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4911 break; 4912 default: 4913 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly"); 4914 ret_val = IXGBE_ERR_CONFIG; 4915 goto out; 4916 } 4917 4918 /* Set 802.3x based flow control settings. */ 4919 mflcn_reg |= IXGBE_MFLCN_DPF; 4920 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 4921 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 4922 4923 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 4924 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 4925 hw->fc.high_water[tc_num]) { 4926 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE; 4927 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl); 4928 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN; 4929 } else { 4930 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0); 4931 /* 4932 * In order to prevent Tx hangs when the internal Tx 4933 * switch is enabled we must set the high water mark 4934 * to the maximum FCRTH value. This allows the Tx 4935 * switch to function even under heavy Rx workloads. 4936 */ 4937 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32; 4938 } 4939 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth); 4940 4941 /* Configure pause time (2 TCs per register) */ 4942 reg = hw->fc.pause_time * 0x00010001; 4943 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 4944 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 4945 4946 /* Configure flow control refresh threshold value */ 4947 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 4948 4949 out: 4950 return ret_val; 4951 } 4952 4953 static int 4954 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num) 4955 { 4956 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4957 int32_t ret_val = IXGBE_NOT_IMPLEMENTED; 4958 4959 if (hw->mac.type != ixgbe_mac_82598EB) { 4960 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num); 4961 } 4962 return ret_val; 4963 } 4964 4965 static int 4966 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf) 4967 { 4968 int err; 4969 uint32_t rx_buf_size; 4970 uint32_t max_high_water; 4971 uint8_t tc_num; 4972 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 4973 struct ixgbe_hw *hw = 4974 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4975 struct ixgbe_dcb_config *dcb_config = 4976 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 4977 4978 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4979 ixgbe_fc_none, 4980 ixgbe_fc_rx_pause, 4981 ixgbe_fc_tx_pause, 4982 ixgbe_fc_full 4983 }; 4984 4985 PMD_INIT_FUNC_TRACE(); 4986 4987 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map); 4988 tc_num = map[pfc_conf->priority]; 4989 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)); 4990 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4991 /* 4992 * At least reserve one Ethernet frame for watermark 4993 * high_water/low_water in kilo bytes for ixgbe 4994 */ 4995 max_high_water = (rx_buf_size - 4996 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4997 if ((pfc_conf->fc.high_water > max_high_water) || 4998 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) { 4999 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 5000 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 5001 return -EINVAL; 5002 } 5003 5004 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode]; 5005 hw->fc.pause_time = pfc_conf->fc.pause_time; 5006 hw->fc.send_xon = pfc_conf->fc.send_xon; 5007 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water; 5008 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; 5009 5010 err = ixgbe_dcb_pfc_enable(dev, tc_num); 5011 5012 /* Not negotiated is not an error case */ 5013 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) 5014 return 0; 5015 5016 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err); 5017 return -EIO; 5018 } 5019 5020 static int 5021 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 5022 struct rte_eth_rss_reta_entry64 *reta_conf, 5023 uint16_t reta_size) 5024 { 5025 uint16_t i, sp_reta_size; 5026 uint8_t j, mask; 5027 uint32_t reta, r; 5028 uint16_t idx, shift; 5029 struct ixgbe_adapter *adapter = dev->data->dev_private; 5030 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5031 uint32_t reta_reg; 5032 5033 PMD_INIT_FUNC_TRACE(); 5034 5035 if (!ixgbe_rss_update_sp(hw->mac.type)) { 5036 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " 5037 "NIC."); 5038 return -ENOTSUP; 5039 } 5040 5041 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 5042 if (reta_size != sp_reta_size) { 5043 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 5044 "(%d) doesn't match the number hardware can supported " 5045 "(%d)", reta_size, sp_reta_size); 5046 return -EINVAL; 5047 } 5048 5049 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 5050 idx = i / RTE_RETA_GROUP_SIZE; 5051 shift = i % RTE_RETA_GROUP_SIZE; 5052 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 5053 IXGBE_4_BIT_MASK); 5054 if (!mask) 5055 continue; 5056 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 5057 if (mask == IXGBE_4_BIT_MASK) 5058 r = 0; 5059 else 5060 r = IXGBE_READ_REG(hw, reta_reg); 5061 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) { 5062 if (mask & (0x1 << j)) 5063 reta |= reta_conf[idx].reta[shift + j] << 5064 (CHAR_BIT * j); 5065 else 5066 reta |= r & (IXGBE_8_BIT_MASK << 5067 (CHAR_BIT * j)); 5068 } 5069 IXGBE_WRITE_REG(hw, reta_reg, reta); 5070 } 5071 adapter->rss_reta_updated = 1; 5072 5073 return 0; 5074 } 5075 5076 static int 5077 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 5078 struct rte_eth_rss_reta_entry64 *reta_conf, 5079 uint16_t reta_size) 5080 { 5081 uint16_t i, sp_reta_size; 5082 uint8_t j, mask; 5083 uint32_t reta; 5084 uint16_t idx, shift; 5085 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5086 uint32_t reta_reg; 5087 5088 PMD_INIT_FUNC_TRACE(); 5089 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 5090 if (reta_size != sp_reta_size) { 5091 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 5092 "(%d) doesn't match the number hardware can supported " 5093 "(%d)", reta_size, sp_reta_size); 5094 return -EINVAL; 5095 } 5096 5097 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 5098 idx = i / RTE_RETA_GROUP_SIZE; 5099 shift = i % RTE_RETA_GROUP_SIZE; 5100 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 5101 IXGBE_4_BIT_MASK); 5102 if (!mask) 5103 continue; 5104 5105 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 5106 reta = IXGBE_READ_REG(hw, reta_reg); 5107 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) { 5108 if (mask & (0x1 << j)) 5109 reta_conf[idx].reta[shift + j] = 5110 ((reta >> (CHAR_BIT * j)) & 5111 IXGBE_8_BIT_MASK); 5112 } 5113 } 5114 5115 return 0; 5116 } 5117 5118 static int 5119 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 5120 uint32_t index, uint32_t pool) 5121 { 5122 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5123 uint32_t enable_addr = 1; 5124 5125 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes, 5126 pool, enable_addr); 5127 } 5128 5129 static void 5130 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) 5131 { 5132 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5133 5134 ixgbe_clear_rar(hw, index); 5135 } 5136 5137 static int 5138 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 5139 { 5140 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5141 5142 ixgbe_remove_rar(dev, 0); 5143 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs); 5144 5145 return 0; 5146 } 5147 5148 static bool 5149 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 5150 { 5151 if (strcmp(dev->device->driver->name, drv->driver.name)) 5152 return false; 5153 5154 return true; 5155 } 5156 5157 bool 5158 is_ixgbe_supported(struct rte_eth_dev *dev) 5159 { 5160 return is_device_supported(dev, &rte_ixgbe_pmd); 5161 } 5162 5163 static int 5164 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 5165 { 5166 uint32_t hlreg0; 5167 uint32_t maxfrs; 5168 struct ixgbe_hw *hw; 5169 struct rte_eth_dev_info dev_info; 5170 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD; 5171 struct rte_eth_dev_data *dev_data = dev->data; 5172 int ret; 5173 5174 ret = ixgbe_dev_info_get(dev, &dev_info); 5175 if (ret != 0) 5176 return ret; 5177 5178 /* check that mtu is within the allowed range */ 5179 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) 5180 return -EINVAL; 5181 5182 /* If device is started, refuse mtu that requires the support of 5183 * scattered packets when this feature has not been enabled before. 5184 */ 5185 if (dev_data->dev_started && !dev_data->scattered_rx && 5186 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE > 5187 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 5188 PMD_INIT_LOG(ERR, "Stop port first."); 5189 return -EINVAL; 5190 } 5191 5192 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5193 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 5194 5195 /* switch to jumbo mode if needed */ 5196 if (frame_size > RTE_ETHER_MAX_LEN) { 5197 dev->data->dev_conf.rxmode.offloads |= 5198 DEV_RX_OFFLOAD_JUMBO_FRAME; 5199 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 5200 } else { 5201 dev->data->dev_conf.rxmode.offloads &= 5202 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 5203 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; 5204 } 5205 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 5206 5207 /* update max frame size */ 5208 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 5209 5210 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS); 5211 maxfrs &= 0x0000FFFF; 5212 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16); 5213 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs); 5214 5215 return 0; 5216 } 5217 5218 /* 5219 * Virtual Function operations 5220 */ 5221 static void 5222 ixgbevf_intr_disable(struct rte_eth_dev *dev) 5223 { 5224 struct ixgbe_interrupt *intr = 5225 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5226 struct ixgbe_hw *hw = 5227 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5228 5229 PMD_INIT_FUNC_TRACE(); 5230 5231 /* Clear interrupt mask to stop from interrupts being generated */ 5232 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK); 5233 5234 IXGBE_WRITE_FLUSH(hw); 5235 5236 /* Clear mask value. */ 5237 intr->mask = 0; 5238 } 5239 5240 static void 5241 ixgbevf_intr_enable(struct rte_eth_dev *dev) 5242 { 5243 struct ixgbe_interrupt *intr = 5244 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5245 struct ixgbe_hw *hw = 5246 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5247 5248 PMD_INIT_FUNC_TRACE(); 5249 5250 /* VF enable interrupt autoclean */ 5251 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK); 5252 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK); 5253 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK); 5254 5255 IXGBE_WRITE_FLUSH(hw); 5256 5257 /* Save IXGBE_VTEIMS value to mask. */ 5258 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK; 5259 } 5260 5261 static int 5262 ixgbevf_dev_configure(struct rte_eth_dev *dev) 5263 { 5264 struct rte_eth_conf *conf = &dev->data->dev_conf; 5265 struct ixgbe_adapter *adapter = dev->data->dev_private; 5266 5267 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d", 5268 dev->data->port_id); 5269 5270 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 5271 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 5272 5273 /* 5274 * VF has no ability to enable/disable HW CRC 5275 * Keep the persistent behavior the same as Host PF 5276 */ 5277 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC 5278 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) { 5279 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip"); 5280 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC; 5281 } 5282 #else 5283 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) { 5284 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip"); 5285 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC; 5286 } 5287 #endif 5288 5289 /* 5290 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 5291 * allocation or vector Rx preconditions we will reset it. 5292 */ 5293 adapter->rx_bulk_alloc_allowed = true; 5294 adapter->rx_vec_allowed = true; 5295 5296 return 0; 5297 } 5298 5299 static int 5300 ixgbevf_dev_start(struct rte_eth_dev *dev) 5301 { 5302 struct ixgbe_hw *hw = 5303 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5304 uint32_t intr_vector = 0; 5305 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5306 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5307 5308 int err, mask = 0; 5309 5310 PMD_INIT_FUNC_TRACE(); 5311 5312 /* Stop the link setup handler before resetting the HW. */ 5313 ixgbe_dev_wait_setup_link_complete(dev, 0); 5314 5315 err = hw->mac.ops.reset_hw(hw); 5316 5317 /** 5318 * In this case, reuses the MAC address assigned by VF 5319 * initialization. 5320 */ 5321 if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) { 5322 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err); 5323 return err; 5324 } 5325 5326 hw->mac.get_link_status = true; 5327 5328 /* negotiate mailbox API version to use with the PF. */ 5329 ixgbevf_negotiate_api(hw); 5330 5331 ixgbevf_dev_tx_init(dev); 5332 5333 /* This can fail when allocating mbufs for descriptor rings */ 5334 err = ixgbevf_dev_rx_init(dev); 5335 if (err) { 5336 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err); 5337 ixgbe_dev_clear_queues(dev); 5338 return err; 5339 } 5340 5341 /* Set vfta */ 5342 ixgbevf_set_vfta_all(dev, 1); 5343 5344 /* Set HW strip */ 5345 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 5346 ETH_VLAN_EXTEND_MASK; 5347 err = ixgbevf_vlan_offload_config(dev, mask); 5348 if (err) { 5349 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err); 5350 ixgbe_dev_clear_queues(dev); 5351 return err; 5352 } 5353 5354 ixgbevf_dev_rxtx_start(dev); 5355 5356 /* check and configure queue intr-vector mapping */ 5357 if (rte_intr_cap_multiple(intr_handle) && 5358 dev->data->dev_conf.intr_conf.rxq) { 5359 /* According to datasheet, only vector 0/1/2 can be used, 5360 * now only one vector is used for Rx queue 5361 */ 5362 intr_vector = 1; 5363 if (rte_intr_efd_enable(intr_handle, intr_vector)) 5364 return -1; 5365 } 5366 5367 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 5368 intr_handle->intr_vec = 5369 rte_zmalloc("intr_vec", 5370 dev->data->nb_rx_queues * sizeof(int), 0); 5371 if (intr_handle->intr_vec == NULL) { 5372 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 5373 " intr_vec", dev->data->nb_rx_queues); 5374 return -ENOMEM; 5375 } 5376 } 5377 ixgbevf_configure_msix(dev); 5378 5379 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt 5380 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ). 5381 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( ) 5382 * is not cleared, it will fail when following rte_intr_enable( ) tries 5383 * to map Rx queue interrupt to other VFIO vectors. 5384 * So clear uio/vfio intr/evevnfd first to avoid failure. 5385 */ 5386 rte_intr_disable(intr_handle); 5387 5388 rte_intr_enable(intr_handle); 5389 5390 /* Re-enable interrupt for VF */ 5391 ixgbevf_intr_enable(dev); 5392 5393 /* 5394 * Update link status right before return, because it may 5395 * start link configuration process in a separate thread. 5396 */ 5397 ixgbevf_dev_link_update(dev, 0); 5398 5399 hw->adapter_stopped = false; 5400 5401 return 0; 5402 } 5403 5404 static void 5405 ixgbevf_dev_stop(struct rte_eth_dev *dev) 5406 { 5407 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5408 struct ixgbe_adapter *adapter = dev->data->dev_private; 5409 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5410 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5411 5412 if (hw->adapter_stopped) 5413 return; 5414 5415 PMD_INIT_FUNC_TRACE(); 5416 5417 ixgbe_dev_wait_setup_link_complete(dev, 0); 5418 5419 ixgbevf_intr_disable(dev); 5420 5421 hw->adapter_stopped = 1; 5422 ixgbe_stop_adapter(hw); 5423 5424 /* 5425 * Clear what we set, but we still keep shadow_vfta to 5426 * restore after device starts 5427 */ 5428 ixgbevf_set_vfta_all(dev, 0); 5429 5430 /* Clear stored conf */ 5431 dev->data->scattered_rx = 0; 5432 5433 ixgbe_dev_clear_queues(dev); 5434 5435 /* Clean datapath event and queue/vec mapping */ 5436 rte_intr_efd_disable(intr_handle); 5437 if (intr_handle->intr_vec != NULL) { 5438 rte_free(intr_handle->intr_vec); 5439 intr_handle->intr_vec = NULL; 5440 } 5441 5442 adapter->rss_reta_updated = 0; 5443 } 5444 5445 static int 5446 ixgbevf_dev_close(struct rte_eth_dev *dev) 5447 { 5448 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5449 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5450 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5451 5452 PMD_INIT_FUNC_TRACE(); 5453 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5454 return 0; 5455 5456 ixgbe_reset_hw(hw); 5457 5458 ixgbevf_dev_stop(dev); 5459 5460 ixgbe_dev_free_queues(dev); 5461 5462 /** 5463 * Remove the VF MAC address ro ensure 5464 * that the VF traffic goes to the PF 5465 * after stop, close and detach of the VF 5466 **/ 5467 ixgbevf_remove_mac_addr(dev, 0); 5468 5469 dev->dev_ops = NULL; 5470 dev->rx_pkt_burst = NULL; 5471 dev->tx_pkt_burst = NULL; 5472 5473 rte_intr_disable(intr_handle); 5474 rte_intr_callback_unregister(intr_handle, 5475 ixgbevf_dev_interrupt_handler, dev); 5476 5477 return 0; 5478 } 5479 5480 /* 5481 * Reset VF device 5482 */ 5483 static int 5484 ixgbevf_dev_reset(struct rte_eth_dev *dev) 5485 { 5486 int ret; 5487 5488 ret = eth_ixgbevf_dev_uninit(dev); 5489 if (ret) 5490 return ret; 5491 5492 ret = eth_ixgbevf_dev_init(dev); 5493 5494 return ret; 5495 } 5496 5497 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) 5498 { 5499 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5500 struct ixgbe_vfta *shadow_vfta = 5501 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5502 int i = 0, j = 0, vfta = 0, mask = 1; 5503 5504 for (i = 0; i < IXGBE_VFTA_SIZE; i++) { 5505 vfta = shadow_vfta->vfta[i]; 5506 if (vfta) { 5507 mask = 1; 5508 for (j = 0; j < 32; j++) { 5509 if (vfta & mask) 5510 ixgbe_set_vfta(hw, (i<<5)+j, 0, 5511 on, false); 5512 mask <<= 1; 5513 } 5514 } 5515 } 5516 5517 } 5518 5519 static int 5520 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 5521 { 5522 struct ixgbe_hw *hw = 5523 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5524 struct ixgbe_vfta *shadow_vfta = 5525 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5526 uint32_t vid_idx = 0; 5527 uint32_t vid_bit = 0; 5528 int ret = 0; 5529 5530 PMD_INIT_FUNC_TRACE(); 5531 5532 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */ 5533 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false); 5534 if (ret) { 5535 PMD_INIT_LOG(ERR, "Unable to set VF vlan"); 5536 return ret; 5537 } 5538 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 5539 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 5540 5541 /* Save what we set and retore it after device reset */ 5542 if (on) 5543 shadow_vfta->vfta[vid_idx] |= vid_bit; 5544 else 5545 shadow_vfta->vfta[vid_idx] &= ~vid_bit; 5546 5547 return 0; 5548 } 5549 5550 static void 5551 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 5552 { 5553 struct ixgbe_hw *hw = 5554 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5555 uint32_t ctrl; 5556 5557 PMD_INIT_FUNC_TRACE(); 5558 5559 if (queue >= hw->mac.max_rx_queues) 5560 return; 5561 5562 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 5563 if (on) 5564 ctrl |= IXGBE_RXDCTL_VME; 5565 else 5566 ctrl &= ~IXGBE_RXDCTL_VME; 5567 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 5568 5569 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on); 5570 } 5571 5572 static int 5573 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask) 5574 { 5575 struct ixgbe_rx_queue *rxq; 5576 uint16_t i; 5577 int on = 0; 5578 5579 /* VF function only support hw strip feature, others are not support */ 5580 if (mask & ETH_VLAN_STRIP_MASK) { 5581 for (i = 0; i < dev->data->nb_rx_queues; i++) { 5582 rxq = dev->data->rx_queues[i]; 5583 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP); 5584 ixgbevf_vlan_strip_queue_set(dev, i, on); 5585 } 5586 } 5587 5588 return 0; 5589 } 5590 5591 static int 5592 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 5593 { 5594 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 5595 5596 ixgbevf_vlan_offload_config(dev, mask); 5597 5598 return 0; 5599 } 5600 5601 int 5602 ixgbe_vt_check(struct ixgbe_hw *hw) 5603 { 5604 uint32_t reg_val; 5605 5606 /* if Virtualization Technology is enabled */ 5607 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 5608 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) { 5609 PMD_INIT_LOG(ERR, "VT must be enabled for this setting"); 5610 return -1; 5611 } 5612 5613 return 0; 5614 } 5615 5616 static uint32_t 5617 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr) 5618 { 5619 uint32_t vector = 0; 5620 5621 switch (hw->mac.mc_filter_type) { 5622 case 0: /* use bits [47:36] of the address */ 5623 vector = ((uc_addr->addr_bytes[4] >> 4) | 5624 (((uint16_t)uc_addr->addr_bytes[5]) << 4)); 5625 break; 5626 case 1: /* use bits [46:35] of the address */ 5627 vector = ((uc_addr->addr_bytes[4] >> 3) | 5628 (((uint16_t)uc_addr->addr_bytes[5]) << 5)); 5629 break; 5630 case 2: /* use bits [45:34] of the address */ 5631 vector = ((uc_addr->addr_bytes[4] >> 2) | 5632 (((uint16_t)uc_addr->addr_bytes[5]) << 6)); 5633 break; 5634 case 3: /* use bits [43:32] of the address */ 5635 vector = ((uc_addr->addr_bytes[4]) | 5636 (((uint16_t)uc_addr->addr_bytes[5]) << 8)); 5637 break; 5638 default: /* Invalid mc_filter_type */ 5639 break; 5640 } 5641 5642 /* vector can only be 12-bits or boundary will be exceeded */ 5643 vector &= 0xFFF; 5644 return vector; 5645 } 5646 5647 static int 5648 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, 5649 struct rte_ether_addr *mac_addr, uint8_t on) 5650 { 5651 uint32_t vector; 5652 uint32_t uta_idx; 5653 uint32_t reg_val; 5654 uint32_t uta_shift; 5655 uint32_t rc; 5656 const uint32_t ixgbe_uta_idx_mask = 0x7F; 5657 const uint32_t ixgbe_uta_bit_shift = 5; 5658 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1; 5659 const uint32_t bit1 = 0x1; 5660 5661 struct ixgbe_hw *hw = 5662 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5663 struct ixgbe_uta_info *uta_info = 5664 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5665 5666 /* The UTA table only exists on 82599 hardware and newer */ 5667 if (hw->mac.type < ixgbe_mac_82599EB) 5668 return -ENOTSUP; 5669 5670 vector = ixgbe_uta_vector(hw, mac_addr); 5671 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask; 5672 uta_shift = vector & ixgbe_uta_bit_mask; 5673 5674 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0); 5675 if (rc == on) 5676 return 0; 5677 5678 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx)); 5679 if (on) { 5680 uta_info->uta_in_use++; 5681 reg_val |= (bit1 << uta_shift); 5682 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift); 5683 } else { 5684 uta_info->uta_in_use--; 5685 reg_val &= ~(bit1 << uta_shift); 5686 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift); 5687 } 5688 5689 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val); 5690 5691 if (uta_info->uta_in_use > 0) 5692 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 5693 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 5694 else 5695 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 5696 5697 return 0; 5698 } 5699 5700 static int 5701 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) 5702 { 5703 int i; 5704 struct ixgbe_hw *hw = 5705 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5706 struct ixgbe_uta_info *uta_info = 5707 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5708 5709 /* The UTA table only exists on 82599 hardware and newer */ 5710 if (hw->mac.type < ixgbe_mac_82599EB) 5711 return -ENOTSUP; 5712 5713 if (on) { 5714 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5715 uta_info->uta_shadow[i] = ~0; 5716 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); 5717 } 5718 } else { 5719 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5720 uta_info->uta_shadow[i] = 0; 5721 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 5722 } 5723 } 5724 return 0; 5725 5726 } 5727 5728 uint32_t 5729 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val) 5730 { 5731 uint32_t new_val = orig_val; 5732 5733 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG) 5734 new_val |= IXGBE_VMOLR_AUPE; 5735 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC) 5736 new_val |= IXGBE_VMOLR_ROMPE; 5737 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC) 5738 new_val |= IXGBE_VMOLR_ROPE; 5739 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST) 5740 new_val |= IXGBE_VMOLR_BAM; 5741 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST) 5742 new_val |= IXGBE_VMOLR_MPE; 5743 5744 return new_val; 5745 } 5746 5747 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */ 5748 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */ 5749 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */ 5750 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */ 5751 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \ 5752 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \ 5753 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN)) 5754 5755 static int 5756 ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 5757 struct rte_eth_mirror_conf *mirror_conf, 5758 uint8_t rule_id, uint8_t on) 5759 { 5760 uint32_t mr_ctl, vlvf; 5761 uint32_t mp_lsb = 0; 5762 uint32_t mv_msb = 0; 5763 uint32_t mv_lsb = 0; 5764 uint32_t mp_msb = 0; 5765 uint8_t i = 0; 5766 int reg_index = 0; 5767 uint64_t vlan_mask = 0; 5768 5769 const uint8_t pool_mask_offset = 32; 5770 const uint8_t vlan_mask_offset = 32; 5771 const uint8_t dst_pool_offset = 8; 5772 const uint8_t rule_mr_offset = 4; 5773 const uint8_t mirror_rule_mask = 0x0F; 5774 5775 struct ixgbe_mirror_info *mr_info = 5776 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5777 struct ixgbe_hw *hw = 5778 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5779 uint8_t mirror_type = 0; 5780 5781 if (ixgbe_vt_check(hw) < 0) 5782 return -ENOTSUP; 5783 5784 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5785 return -EINVAL; 5786 5787 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) { 5788 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.", 5789 mirror_conf->rule_type); 5790 return -EINVAL; 5791 } 5792 5793 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5794 mirror_type |= IXGBE_MRCTL_VLME; 5795 /* Check if vlan id is valid and find conresponding VLAN ID 5796 * index in VLVF 5797 */ 5798 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) { 5799 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) { 5800 /* search vlan id related pool vlan filter 5801 * index 5802 */ 5803 reg_index = ixgbe_find_vlvf_slot( 5804 hw, 5805 mirror_conf->vlan.vlan_id[i], 5806 false); 5807 if (reg_index < 0) 5808 return -EINVAL; 5809 vlvf = IXGBE_READ_REG(hw, 5810 IXGBE_VLVF(reg_index)); 5811 if ((vlvf & IXGBE_VLVF_VIEN) && 5812 ((vlvf & IXGBE_VLVF_VLANID_MASK) == 5813 mirror_conf->vlan.vlan_id[i])) 5814 vlan_mask |= (1ULL << reg_index); 5815 else 5816 return -EINVAL; 5817 } 5818 } 5819 5820 if (on) { 5821 mv_lsb = vlan_mask & 0xFFFFFFFF; 5822 mv_msb = vlan_mask >> vlan_mask_offset; 5823 5824 mr_info->mr_conf[rule_id].vlan.vlan_mask = 5825 mirror_conf->vlan.vlan_mask; 5826 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) { 5827 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) 5828 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 5829 mirror_conf->vlan.vlan_id[i]; 5830 } 5831 } else { 5832 mv_lsb = 0; 5833 mv_msb = 0; 5834 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0; 5835 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) 5836 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0; 5837 } 5838 } 5839 5840 /** 5841 * if enable pool mirror, write related pool mask register,if disable 5842 * pool mirror, clear PFMRVM register 5843 */ 5844 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5845 mirror_type |= IXGBE_MRCTL_VPME; 5846 if (on) { 5847 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF; 5848 mp_msb = mirror_conf->pool_mask >> pool_mask_offset; 5849 mr_info->mr_conf[rule_id].pool_mask = 5850 mirror_conf->pool_mask; 5851 5852 } else { 5853 mp_lsb = 0; 5854 mp_msb = 0; 5855 mr_info->mr_conf[rule_id].pool_mask = 0; 5856 } 5857 } 5858 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT) 5859 mirror_type |= IXGBE_MRCTL_UPME; 5860 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT) 5861 mirror_type |= IXGBE_MRCTL_DPME; 5862 5863 /* read mirror control register and recalculate it */ 5864 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id)); 5865 5866 if (on) { 5867 mr_ctl |= mirror_type; 5868 mr_ctl &= mirror_rule_mask; 5869 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset; 5870 } else { 5871 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask); 5872 } 5873 5874 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type; 5875 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool; 5876 5877 /* write mirrror control register */ 5878 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5879 5880 /* write pool mirrror control register */ 5881 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5882 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb); 5883 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), 5884 mp_msb); 5885 } 5886 /* write VLAN mirrror control register */ 5887 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5888 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb); 5889 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), 5890 mv_msb); 5891 } 5892 5893 return 0; 5894 } 5895 5896 static int 5897 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id) 5898 { 5899 int mr_ctl = 0; 5900 uint32_t lsb_val = 0; 5901 uint32_t msb_val = 0; 5902 const uint8_t rule_mr_offset = 4; 5903 5904 struct ixgbe_hw *hw = 5905 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5906 struct ixgbe_mirror_info *mr_info = 5907 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5908 5909 if (ixgbe_vt_check(hw) < 0) 5910 return -ENOTSUP; 5911 5912 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5913 return -EINVAL; 5914 5915 memset(&mr_info->mr_conf[rule_id], 0, 5916 sizeof(struct rte_eth_mirror_conf)); 5917 5918 /* clear PFVMCTL register */ 5919 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5920 5921 /* clear pool mask register */ 5922 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val); 5923 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val); 5924 5925 /* clear vlan mask register */ 5926 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val); 5927 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val); 5928 5929 return 0; 5930 } 5931 5932 static int 5933 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5934 { 5935 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5936 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5937 struct ixgbe_interrupt *intr = 5938 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5939 struct ixgbe_hw *hw = 5940 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5941 uint32_t vec = IXGBE_MISC_VEC_ID; 5942 5943 if (rte_intr_allow_others(intr_handle)) 5944 vec = IXGBE_RX_VEC_START; 5945 intr->mask |= (1 << vec); 5946 RTE_SET_USED(queue_id); 5947 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5948 5949 rte_intr_ack(intr_handle); 5950 5951 return 0; 5952 } 5953 5954 static int 5955 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5956 { 5957 struct ixgbe_interrupt *intr = 5958 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5959 struct ixgbe_hw *hw = 5960 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5961 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5962 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5963 uint32_t vec = IXGBE_MISC_VEC_ID; 5964 5965 if (rte_intr_allow_others(intr_handle)) 5966 vec = IXGBE_RX_VEC_START; 5967 intr->mask &= ~(1 << vec); 5968 RTE_SET_USED(queue_id); 5969 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5970 5971 return 0; 5972 } 5973 5974 static int 5975 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5976 { 5977 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5978 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5979 uint32_t mask; 5980 struct ixgbe_hw *hw = 5981 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5982 struct ixgbe_interrupt *intr = 5983 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5984 5985 if (queue_id < 16) { 5986 ixgbe_disable_intr(hw); 5987 intr->mask |= (1 << queue_id); 5988 ixgbe_enable_intr(dev); 5989 } else if (queue_id < 32) { 5990 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5991 mask &= (1 << queue_id); 5992 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5993 } else if (queue_id < 64) { 5994 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5995 mask &= (1 << (queue_id - 32)); 5996 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5997 } 5998 rte_intr_ack(intr_handle); 5999 6000 return 0; 6001 } 6002 6003 static int 6004 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 6005 { 6006 uint32_t mask; 6007 struct ixgbe_hw *hw = 6008 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6009 struct ixgbe_interrupt *intr = 6010 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 6011 6012 if (queue_id < 16) { 6013 ixgbe_disable_intr(hw); 6014 intr->mask &= ~(1 << queue_id); 6015 ixgbe_enable_intr(dev); 6016 } else if (queue_id < 32) { 6017 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 6018 mask &= ~(1 << queue_id); 6019 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 6020 } else if (queue_id < 64) { 6021 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 6022 mask &= ~(1 << (queue_id - 32)); 6023 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 6024 } 6025 6026 return 0; 6027 } 6028 6029 static void 6030 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 6031 uint8_t queue, uint8_t msix_vector) 6032 { 6033 uint32_t tmp, idx; 6034 6035 if (direction == -1) { 6036 /* other causes */ 6037 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 6038 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC); 6039 tmp &= ~0xFF; 6040 tmp |= msix_vector; 6041 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp); 6042 } else { 6043 /* rx or tx cause */ 6044 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 6045 idx = ((16 * (queue & 1)) + (8 * direction)); 6046 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1)); 6047 tmp &= ~(0xFF << idx); 6048 tmp |= (msix_vector << idx); 6049 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp); 6050 } 6051 } 6052 6053 /** 6054 * set the IVAR registers, mapping interrupt causes to vectors 6055 * @param hw 6056 * pointer to ixgbe_hw struct 6057 * @direction 6058 * 0 for Rx, 1 for Tx, -1 for other causes 6059 * @queue 6060 * queue to map the corresponding interrupt to 6061 * @msix_vector 6062 * the vector to map to the corresponding queue 6063 */ 6064 static void 6065 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 6066 uint8_t queue, uint8_t msix_vector) 6067 { 6068 uint32_t tmp, idx; 6069 6070 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 6071 if (hw->mac.type == ixgbe_mac_82598EB) { 6072 if (direction == -1) 6073 direction = 0; 6074 idx = (((direction * 64) + queue) >> 2) & 0x1F; 6075 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx)); 6076 tmp &= ~(0xFF << (8 * (queue & 0x3))); 6077 tmp |= (msix_vector << (8 * (queue & 0x3))); 6078 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp); 6079 } else if ((hw->mac.type == ixgbe_mac_82599EB) || 6080 (hw->mac.type == ixgbe_mac_X540) || 6081 (hw->mac.type == ixgbe_mac_X550) || 6082 (hw->mac.type == ixgbe_mac_X550EM_x)) { 6083 if (direction == -1) { 6084 /* other causes */ 6085 idx = ((queue & 1) * 8); 6086 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC); 6087 tmp &= ~(0xFF << idx); 6088 tmp |= (msix_vector << idx); 6089 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp); 6090 } else { 6091 /* rx or tx causes */ 6092 idx = ((16 * (queue & 1)) + (8 * direction)); 6093 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 6094 tmp &= ~(0xFF << idx); 6095 tmp |= (msix_vector << idx); 6096 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp); 6097 } 6098 } 6099 } 6100 6101 static void 6102 ixgbevf_configure_msix(struct rte_eth_dev *dev) 6103 { 6104 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 6105 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 6106 struct ixgbe_hw *hw = 6107 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6108 uint32_t q_idx; 6109 uint32_t vector_idx = IXGBE_MISC_VEC_ID; 6110 uint32_t base = IXGBE_MISC_VEC_ID; 6111 6112 /* Configure VF other cause ivar */ 6113 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx); 6114 6115 /* won't configure msix register if no mapping is done 6116 * between intr vector and event fd. 6117 */ 6118 if (!rte_intr_dp_is_en(intr_handle)) 6119 return; 6120 6121 if (rte_intr_allow_others(intr_handle)) { 6122 base = IXGBE_RX_VEC_START; 6123 vector_idx = IXGBE_RX_VEC_START; 6124 } 6125 6126 /* Configure all RX queues of VF */ 6127 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) { 6128 /* Force all queue use vector 0, 6129 * as IXGBE_VF_MAXMSIVECOTR = 1 6130 */ 6131 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx); 6132 intr_handle->intr_vec[q_idx] = vector_idx; 6133 if (vector_idx < base + intr_handle->nb_efd - 1) 6134 vector_idx++; 6135 } 6136 6137 /* As RX queue setting above show, all queues use the vector 0. 6138 * Set only the ITR value of IXGBE_MISC_VEC_ID. 6139 */ 6140 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID), 6141 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 6142 | IXGBE_EITR_CNT_WDIS); 6143 } 6144 6145 /** 6146 * Sets up the hardware to properly generate MSI-X interrupts 6147 * @hw 6148 * board private structure 6149 */ 6150 static void 6151 ixgbe_configure_msix(struct rte_eth_dev *dev) 6152 { 6153 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 6154 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 6155 struct ixgbe_hw *hw = 6156 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6157 uint32_t queue_id, base = IXGBE_MISC_VEC_ID; 6158 uint32_t vec = IXGBE_MISC_VEC_ID; 6159 uint32_t mask; 6160 uint32_t gpie; 6161 6162 /* won't configure msix register if no mapping is done 6163 * between intr vector and event fd 6164 * but if misx has been enabled already, need to configure 6165 * auto clean, auto mask and throttling. 6166 */ 6167 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 6168 if (!rte_intr_dp_is_en(intr_handle) && 6169 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT))) 6170 return; 6171 6172 if (rte_intr_allow_others(intr_handle)) 6173 vec = base = IXGBE_RX_VEC_START; 6174 6175 /* setup GPIE for MSI-x mode */ 6176 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 6177 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 6178 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME; 6179 /* auto clearing and auto setting corresponding bits in EIMS 6180 * when MSI-X interrupt is triggered 6181 */ 6182 if (hw->mac.type == ixgbe_mac_82598EB) { 6183 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 6184 } else { 6185 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 6186 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 6187 } 6188 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 6189 6190 /* Populate the IVAR table and set the ITR values to the 6191 * corresponding register. 6192 */ 6193 if (rte_intr_dp_is_en(intr_handle)) { 6194 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; 6195 queue_id++) { 6196 /* by default, 1:1 mapping */ 6197 ixgbe_set_ivar_map(hw, 0, queue_id, vec); 6198 intr_handle->intr_vec[queue_id] = vec; 6199 if (vec < base + intr_handle->nb_efd - 1) 6200 vec++; 6201 } 6202 6203 switch (hw->mac.type) { 6204 case ixgbe_mac_82598EB: 6205 ixgbe_set_ivar_map(hw, -1, 6206 IXGBE_IVAR_OTHER_CAUSES_INDEX, 6207 IXGBE_MISC_VEC_ID); 6208 break; 6209 case ixgbe_mac_82599EB: 6210 case ixgbe_mac_X540: 6211 case ixgbe_mac_X550: 6212 case ixgbe_mac_X550EM_x: 6213 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID); 6214 break; 6215 default: 6216 break; 6217 } 6218 } 6219 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID), 6220 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 6221 | IXGBE_EITR_CNT_WDIS); 6222 6223 /* set up to autoclear timer, and the vectors */ 6224 mask = IXGBE_EIMS_ENABLE_MASK; 6225 mask &= ~(IXGBE_EIMS_OTHER | 6226 IXGBE_EIMS_MAILBOX | 6227 IXGBE_EIMS_LSC); 6228 6229 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask); 6230 } 6231 6232 int 6233 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, 6234 uint16_t queue_idx, uint16_t tx_rate) 6235 { 6236 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6237 struct rte_eth_rxmode *rxmode; 6238 uint32_t rf_dec, rf_int; 6239 uint32_t bcnrc_val; 6240 uint16_t link_speed = dev->data->dev_link.link_speed; 6241 6242 if (queue_idx >= hw->mac.max_tx_queues) 6243 return -EINVAL; 6244 6245 if (tx_rate != 0) { 6246 /* Calculate the rate factor values to set */ 6247 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate; 6248 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate; 6249 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate; 6250 6251 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA; 6252 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) & 6253 IXGBE_RTTBCNRC_RF_INT_MASK_M); 6254 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK); 6255 } else { 6256 bcnrc_val = 0; 6257 } 6258 6259 rxmode = &dev->data->dev_conf.rxmode; 6260 /* 6261 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 6262 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise 6263 * set as 0x4. 6264 */ 6265 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) && 6266 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE)) 6267 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 6268 IXGBE_MMW_SIZE_JUMBO_FRAME); 6269 else 6270 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 6271 IXGBE_MMW_SIZE_DEFAULT); 6272 6273 /* Set RTTBCNRC of queue X */ 6274 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx); 6275 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 6276 IXGBE_WRITE_FLUSH(hw); 6277 6278 return 0; 6279 } 6280 6281 static int 6282 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 6283 __rte_unused uint32_t index, 6284 __rte_unused uint32_t pool) 6285 { 6286 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6287 int diag; 6288 6289 /* 6290 * On a 82599 VF, adding again the same MAC addr is not an idempotent 6291 * operation. Trap this case to avoid exhausting the [very limited] 6292 * set of PF resources used to store VF MAC addresses. 6293 */ 6294 if (memcmp(hw->mac.perm_addr, mac_addr, 6295 sizeof(struct rte_ether_addr)) == 0) 6296 return -1; 6297 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6298 if (diag != 0) 6299 PMD_DRV_LOG(ERR, "Unable to add MAC address " 6300 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d", 6301 mac_addr->addr_bytes[0], 6302 mac_addr->addr_bytes[1], 6303 mac_addr->addr_bytes[2], 6304 mac_addr->addr_bytes[3], 6305 mac_addr->addr_bytes[4], 6306 mac_addr->addr_bytes[5], 6307 diag); 6308 return diag; 6309 } 6310 6311 static void 6312 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index) 6313 { 6314 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6315 struct rte_ether_addr *perm_addr = 6316 (struct rte_ether_addr *)hw->mac.perm_addr; 6317 struct rte_ether_addr *mac_addr; 6318 uint32_t i; 6319 int diag; 6320 6321 /* 6322 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does 6323 * not support the deletion of a given MAC address. 6324 * Instead, it imposes to delete all MAC addresses, then to add again 6325 * all MAC addresses with the exception of the one to be deleted. 6326 */ 6327 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL); 6328 6329 /* 6330 * Add again all MAC addresses, with the exception of the deleted one 6331 * and of the permanent MAC address. 6332 */ 6333 for (i = 0, mac_addr = dev->data->mac_addrs; 6334 i < hw->mac.num_rar_entries; i++, mac_addr++) { 6335 /* Skip the deleted MAC address */ 6336 if (i == index) 6337 continue; 6338 /* Skip NULL MAC addresses */ 6339 if (rte_is_zero_ether_addr(mac_addr)) 6340 continue; 6341 /* Skip the permanent MAC address */ 6342 if (memcmp(perm_addr, mac_addr, 6343 sizeof(struct rte_ether_addr)) == 0) 6344 continue; 6345 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6346 if (diag != 0) 6347 PMD_DRV_LOG(ERR, 6348 "Adding again MAC address " 6349 "%02x:%02x:%02x:%02x:%02x:%02x failed " 6350 "diag=%d", 6351 mac_addr->addr_bytes[0], 6352 mac_addr->addr_bytes[1], 6353 mac_addr->addr_bytes[2], 6354 mac_addr->addr_bytes[3], 6355 mac_addr->addr_bytes[4], 6356 mac_addr->addr_bytes[5], 6357 diag); 6358 } 6359 } 6360 6361 static int 6362 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 6363 struct rte_ether_addr *addr) 6364 { 6365 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6366 6367 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0); 6368 6369 return 0; 6370 } 6371 6372 int 6373 ixgbe_syn_filter_set(struct rte_eth_dev *dev, 6374 struct rte_eth_syn_filter *filter, 6375 bool add) 6376 { 6377 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6378 struct ixgbe_filter_info *filter_info = 6379 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6380 uint32_t syn_info; 6381 uint32_t synqf; 6382 6383 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6384 return -EINVAL; 6385 6386 syn_info = filter_info->syn_info; 6387 6388 if (add) { 6389 if (syn_info & IXGBE_SYN_FILTER_ENABLE) 6390 return -EINVAL; 6391 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) & 6392 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE); 6393 6394 if (filter->hig_pri) 6395 synqf |= IXGBE_SYN_FILTER_SYNQFP; 6396 else 6397 synqf &= ~IXGBE_SYN_FILTER_SYNQFP; 6398 } else { 6399 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6400 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE)) 6401 return -ENOENT; 6402 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE); 6403 } 6404 6405 filter_info->syn_info = synqf; 6406 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 6407 IXGBE_WRITE_FLUSH(hw); 6408 return 0; 6409 } 6410 6411 static int 6412 ixgbe_syn_filter_get(struct rte_eth_dev *dev, 6413 struct rte_eth_syn_filter *filter) 6414 { 6415 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6416 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6417 6418 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 6419 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0; 6420 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1); 6421 return 0; 6422 } 6423 return -ENOENT; 6424 } 6425 6426 static int 6427 ixgbe_syn_filter_handle(struct rte_eth_dev *dev, 6428 enum rte_filter_op filter_op, 6429 void *arg) 6430 { 6431 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6432 int ret; 6433 6434 MAC_TYPE_FILTER_SUP(hw->mac.type); 6435 6436 if (filter_op == RTE_ETH_FILTER_NOP) 6437 return 0; 6438 6439 if (arg == NULL) { 6440 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u", 6441 filter_op); 6442 return -EINVAL; 6443 } 6444 6445 switch (filter_op) { 6446 case RTE_ETH_FILTER_ADD: 6447 ret = ixgbe_syn_filter_set(dev, 6448 (struct rte_eth_syn_filter *)arg, 6449 TRUE); 6450 break; 6451 case RTE_ETH_FILTER_DELETE: 6452 ret = ixgbe_syn_filter_set(dev, 6453 (struct rte_eth_syn_filter *)arg, 6454 FALSE); 6455 break; 6456 case RTE_ETH_FILTER_GET: 6457 ret = ixgbe_syn_filter_get(dev, 6458 (struct rte_eth_syn_filter *)arg); 6459 break; 6460 default: 6461 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op); 6462 ret = -EINVAL; 6463 break; 6464 } 6465 6466 return ret; 6467 } 6468 6469 6470 static inline enum ixgbe_5tuple_protocol 6471 convert_protocol_type(uint8_t protocol_value) 6472 { 6473 if (protocol_value == IPPROTO_TCP) 6474 return IXGBE_FILTER_PROTOCOL_TCP; 6475 else if (protocol_value == IPPROTO_UDP) 6476 return IXGBE_FILTER_PROTOCOL_UDP; 6477 else if (protocol_value == IPPROTO_SCTP) 6478 return IXGBE_FILTER_PROTOCOL_SCTP; 6479 else 6480 return IXGBE_FILTER_PROTOCOL_NONE; 6481 } 6482 6483 /* inject a 5-tuple filter to HW */ 6484 static inline void 6485 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev, 6486 struct ixgbe_5tuple_filter *filter) 6487 { 6488 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6489 int i; 6490 uint32_t ftqf, sdpqf; 6491 uint32_t l34timir = 0; 6492 uint8_t mask = 0xff; 6493 6494 i = filter->index; 6495 6496 sdpqf = (uint32_t)(filter->filter_info.dst_port << 6497 IXGBE_SDPQF_DSTPORT_SHIFT); 6498 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT); 6499 6500 ftqf = (uint32_t)(filter->filter_info.proto & 6501 IXGBE_FTQF_PROTOCOL_MASK); 6502 ftqf |= (uint32_t)((filter->filter_info.priority & 6503 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT); 6504 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */ 6505 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK; 6506 if (filter->filter_info.dst_ip_mask == 0) 6507 mask &= IXGBE_FTQF_DEST_ADDR_MASK; 6508 if (filter->filter_info.src_port_mask == 0) 6509 mask &= IXGBE_FTQF_SOURCE_PORT_MASK; 6510 if (filter->filter_info.dst_port_mask == 0) 6511 mask &= IXGBE_FTQF_DEST_PORT_MASK; 6512 if (filter->filter_info.proto_mask == 0) 6513 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK; 6514 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT; 6515 ftqf |= IXGBE_FTQF_POOL_MASK_EN; 6516 ftqf |= IXGBE_FTQF_QUEUE_ENABLE; 6517 6518 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip); 6519 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip); 6520 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf); 6521 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf); 6522 6523 l34timir |= IXGBE_L34T_IMIR_RESERVE; 6524 l34timir |= (uint32_t)(filter->queue << 6525 IXGBE_L34T_IMIR_QUEUE_SHIFT); 6526 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir); 6527 } 6528 6529 /* 6530 * add a 5tuple filter 6531 * 6532 * @param 6533 * dev: Pointer to struct rte_eth_dev. 6534 * index: the index the filter allocates. 6535 * filter: ponter to the filter that will be added. 6536 * rx_queue: the queue id the filter assigned to. 6537 * 6538 * @return 6539 * - On success, zero. 6540 * - On failure, a negative value. 6541 */ 6542 static int 6543 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 6544 struct ixgbe_5tuple_filter *filter) 6545 { 6546 struct ixgbe_filter_info *filter_info = 6547 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6548 int i, idx, shift; 6549 6550 /* 6551 * look for an unused 5tuple filter index, 6552 * and insert the filter to list. 6553 */ 6554 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) { 6555 idx = i / (sizeof(uint32_t) * NBBY); 6556 shift = i % (sizeof(uint32_t) * NBBY); 6557 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) { 6558 filter_info->fivetuple_mask[idx] |= 1 << shift; 6559 filter->index = i; 6560 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list, 6561 filter, 6562 entries); 6563 break; 6564 } 6565 } 6566 if (i >= IXGBE_MAX_FTQF_FILTERS) { 6567 PMD_DRV_LOG(ERR, "5tuple filters are full."); 6568 return -ENOSYS; 6569 } 6570 6571 ixgbe_inject_5tuple_filter(dev, filter); 6572 6573 return 0; 6574 } 6575 6576 /* 6577 * remove a 5tuple filter 6578 * 6579 * @param 6580 * dev: Pointer to struct rte_eth_dev. 6581 * filter: the pointer of the filter will be removed. 6582 */ 6583 static void 6584 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 6585 struct ixgbe_5tuple_filter *filter) 6586 { 6587 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6588 struct ixgbe_filter_info *filter_info = 6589 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6590 uint16_t index = filter->index; 6591 6592 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &= 6593 ~(1 << (index % (sizeof(uint32_t) * NBBY))); 6594 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries); 6595 rte_free(filter); 6596 6597 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0); 6598 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0); 6599 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0); 6600 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0); 6601 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0); 6602 } 6603 6604 static int 6605 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 6606 { 6607 struct ixgbe_hw *hw; 6608 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD; 6609 struct rte_eth_dev_data *dev_data = dev->data; 6610 6611 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6612 6613 if (mtu < RTE_ETHER_MIN_MTU || 6614 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN) 6615 return -EINVAL; 6616 6617 /* If device is started, refuse mtu that requires the support of 6618 * scattered packets when this feature has not been enabled before. 6619 */ 6620 if (dev_data->dev_started && !dev_data->scattered_rx && 6621 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE > 6622 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 6623 PMD_INIT_LOG(ERR, "Stop port first."); 6624 return -EINVAL; 6625 } 6626 6627 /* 6628 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU 6629 * request of the version 2.0 of the mailbox API. 6630 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0 6631 * of the mailbox API. 6632 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers 6633 * prior to 3.11.33 which contains the following change: 6634 * "ixgbe: Enable jumbo frames support w/ SR-IOV" 6635 */ 6636 ixgbevf_rlpml_set_vf(hw, max_frame); 6637 6638 /* update max frame size */ 6639 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame; 6640 return 0; 6641 } 6642 6643 static inline struct ixgbe_5tuple_filter * 6644 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list, 6645 struct ixgbe_5tuple_filter_info *key) 6646 { 6647 struct ixgbe_5tuple_filter *it; 6648 6649 TAILQ_FOREACH(it, filter_list, entries) { 6650 if (memcmp(key, &it->filter_info, 6651 sizeof(struct ixgbe_5tuple_filter_info)) == 0) { 6652 return it; 6653 } 6654 } 6655 return NULL; 6656 } 6657 6658 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/ 6659 static inline int 6660 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter, 6661 struct ixgbe_5tuple_filter_info *filter_info) 6662 { 6663 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM || 6664 filter->priority > IXGBE_5TUPLE_MAX_PRI || 6665 filter->priority < IXGBE_5TUPLE_MIN_PRI) 6666 return -EINVAL; 6667 6668 switch (filter->dst_ip_mask) { 6669 case UINT32_MAX: 6670 filter_info->dst_ip_mask = 0; 6671 filter_info->dst_ip = filter->dst_ip; 6672 break; 6673 case 0: 6674 filter_info->dst_ip_mask = 1; 6675 break; 6676 default: 6677 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 6678 return -EINVAL; 6679 } 6680 6681 switch (filter->src_ip_mask) { 6682 case UINT32_MAX: 6683 filter_info->src_ip_mask = 0; 6684 filter_info->src_ip = filter->src_ip; 6685 break; 6686 case 0: 6687 filter_info->src_ip_mask = 1; 6688 break; 6689 default: 6690 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 6691 return -EINVAL; 6692 } 6693 6694 switch (filter->dst_port_mask) { 6695 case UINT16_MAX: 6696 filter_info->dst_port_mask = 0; 6697 filter_info->dst_port = filter->dst_port; 6698 break; 6699 case 0: 6700 filter_info->dst_port_mask = 1; 6701 break; 6702 default: 6703 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 6704 return -EINVAL; 6705 } 6706 6707 switch (filter->src_port_mask) { 6708 case UINT16_MAX: 6709 filter_info->src_port_mask = 0; 6710 filter_info->src_port = filter->src_port; 6711 break; 6712 case 0: 6713 filter_info->src_port_mask = 1; 6714 break; 6715 default: 6716 PMD_DRV_LOG(ERR, "invalid src_port mask."); 6717 return -EINVAL; 6718 } 6719 6720 switch (filter->proto_mask) { 6721 case UINT8_MAX: 6722 filter_info->proto_mask = 0; 6723 filter_info->proto = 6724 convert_protocol_type(filter->proto); 6725 break; 6726 case 0: 6727 filter_info->proto_mask = 1; 6728 break; 6729 default: 6730 PMD_DRV_LOG(ERR, "invalid protocol mask."); 6731 return -EINVAL; 6732 } 6733 6734 filter_info->priority = (uint8_t)filter->priority; 6735 return 0; 6736 } 6737 6738 /* 6739 * add or delete a ntuple filter 6740 * 6741 * @param 6742 * dev: Pointer to struct rte_eth_dev. 6743 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6744 * add: if true, add filter, if false, remove filter 6745 * 6746 * @return 6747 * - On success, zero. 6748 * - On failure, a negative value. 6749 */ 6750 int 6751 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 6752 struct rte_eth_ntuple_filter *ntuple_filter, 6753 bool add) 6754 { 6755 struct ixgbe_filter_info *filter_info = 6756 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6757 struct ixgbe_5tuple_filter_info filter_5tuple; 6758 struct ixgbe_5tuple_filter *filter; 6759 int ret; 6760 6761 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6762 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6763 return -EINVAL; 6764 } 6765 6766 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6767 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6768 if (ret < 0) 6769 return ret; 6770 6771 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6772 &filter_5tuple); 6773 if (filter != NULL && add) { 6774 PMD_DRV_LOG(ERR, "filter exists."); 6775 return -EEXIST; 6776 } 6777 if (filter == NULL && !add) { 6778 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6779 return -ENOENT; 6780 } 6781 6782 if (add) { 6783 filter = rte_zmalloc("ixgbe_5tuple_filter", 6784 sizeof(struct ixgbe_5tuple_filter), 0); 6785 if (filter == NULL) 6786 return -ENOMEM; 6787 rte_memcpy(&filter->filter_info, 6788 &filter_5tuple, 6789 sizeof(struct ixgbe_5tuple_filter_info)); 6790 filter->queue = ntuple_filter->queue; 6791 ret = ixgbe_add_5tuple_filter(dev, filter); 6792 if (ret < 0) { 6793 rte_free(filter); 6794 return ret; 6795 } 6796 } else 6797 ixgbe_remove_5tuple_filter(dev, filter); 6798 6799 return 0; 6800 } 6801 6802 /* 6803 * get a ntuple filter 6804 * 6805 * @param 6806 * dev: Pointer to struct rte_eth_dev. 6807 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6808 * 6809 * @return 6810 * - On success, zero. 6811 * - On failure, a negative value. 6812 */ 6813 static int 6814 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev, 6815 struct rte_eth_ntuple_filter *ntuple_filter) 6816 { 6817 struct ixgbe_filter_info *filter_info = 6818 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6819 struct ixgbe_5tuple_filter_info filter_5tuple; 6820 struct ixgbe_5tuple_filter *filter; 6821 int ret; 6822 6823 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6824 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6825 return -EINVAL; 6826 } 6827 6828 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6829 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6830 if (ret < 0) 6831 return ret; 6832 6833 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6834 &filter_5tuple); 6835 if (filter == NULL) { 6836 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6837 return -ENOENT; 6838 } 6839 ntuple_filter->queue = filter->queue; 6840 return 0; 6841 } 6842 6843 /* 6844 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter. 6845 * @dev: pointer to rte_eth_dev structure 6846 * @filter_op:operation will be taken. 6847 * @arg: a pointer to specific structure corresponding to the filter_op 6848 * 6849 * @return 6850 * - On success, zero. 6851 * - On failure, a negative value. 6852 */ 6853 static int 6854 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev, 6855 enum rte_filter_op filter_op, 6856 void *arg) 6857 { 6858 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6859 int ret; 6860 6861 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type); 6862 6863 if (filter_op == RTE_ETH_FILTER_NOP) 6864 return 0; 6865 6866 if (arg == NULL) { 6867 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 6868 filter_op); 6869 return -EINVAL; 6870 } 6871 6872 switch (filter_op) { 6873 case RTE_ETH_FILTER_ADD: 6874 ret = ixgbe_add_del_ntuple_filter(dev, 6875 (struct rte_eth_ntuple_filter *)arg, 6876 TRUE); 6877 break; 6878 case RTE_ETH_FILTER_DELETE: 6879 ret = ixgbe_add_del_ntuple_filter(dev, 6880 (struct rte_eth_ntuple_filter *)arg, 6881 FALSE); 6882 break; 6883 case RTE_ETH_FILTER_GET: 6884 ret = ixgbe_get_ntuple_filter(dev, 6885 (struct rte_eth_ntuple_filter *)arg); 6886 break; 6887 default: 6888 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 6889 ret = -EINVAL; 6890 break; 6891 } 6892 return ret; 6893 } 6894 6895 int 6896 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 6897 struct rte_eth_ethertype_filter *filter, 6898 bool add) 6899 { 6900 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6901 struct ixgbe_filter_info *filter_info = 6902 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6903 uint32_t etqf = 0; 6904 uint32_t etqs = 0; 6905 int ret; 6906 struct ixgbe_ethertype_filter ethertype_filter; 6907 6908 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6909 return -EINVAL; 6910 6911 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 || 6912 filter->ether_type == RTE_ETHER_TYPE_IPV6) { 6913 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in" 6914 " ethertype filter.", filter->ether_type); 6915 return -EINVAL; 6916 } 6917 6918 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) { 6919 PMD_DRV_LOG(ERR, "mac compare is unsupported."); 6920 return -EINVAL; 6921 } 6922 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) { 6923 PMD_DRV_LOG(ERR, "drop option is unsupported."); 6924 return -EINVAL; 6925 } 6926 6927 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6928 if (ret >= 0 && add) { 6929 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.", 6930 filter->ether_type); 6931 return -EEXIST; 6932 } 6933 if (ret < 0 && !add) { 6934 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6935 filter->ether_type); 6936 return -ENOENT; 6937 } 6938 6939 if (add) { 6940 etqf = IXGBE_ETQF_FILTER_EN; 6941 etqf |= (uint32_t)filter->ether_type; 6942 etqs |= (uint32_t)((filter->queue << 6943 IXGBE_ETQS_RX_QUEUE_SHIFT) & 6944 IXGBE_ETQS_RX_QUEUE); 6945 etqs |= IXGBE_ETQS_QUEUE_EN; 6946 6947 ethertype_filter.ethertype = filter->ether_type; 6948 ethertype_filter.etqf = etqf; 6949 ethertype_filter.etqs = etqs; 6950 ethertype_filter.conf = FALSE; 6951 ret = ixgbe_ethertype_filter_insert(filter_info, 6952 ðertype_filter); 6953 if (ret < 0) { 6954 PMD_DRV_LOG(ERR, "ethertype filters are full."); 6955 return -ENOSPC; 6956 } 6957 } else { 6958 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret); 6959 if (ret < 0) 6960 return -ENOSYS; 6961 } 6962 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf); 6963 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs); 6964 IXGBE_WRITE_FLUSH(hw); 6965 6966 return 0; 6967 } 6968 6969 static int 6970 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, 6971 struct rte_eth_ethertype_filter *filter) 6972 { 6973 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6974 struct ixgbe_filter_info *filter_info = 6975 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6976 uint32_t etqf, etqs; 6977 int ret; 6978 6979 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6980 if (ret < 0) { 6981 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6982 filter->ether_type); 6983 return -ENOENT; 6984 } 6985 6986 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret)); 6987 if (etqf & IXGBE_ETQF_FILTER_EN) { 6988 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret)); 6989 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE; 6990 filter->flags = 0; 6991 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> 6992 IXGBE_ETQS_RX_QUEUE_SHIFT; 6993 return 0; 6994 } 6995 return -ENOENT; 6996 } 6997 6998 /* 6999 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter. 7000 * @dev: pointer to rte_eth_dev structure 7001 * @filter_op:operation will be taken. 7002 * @arg: a pointer to specific structure corresponding to the filter_op 7003 */ 7004 static int 7005 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev, 7006 enum rte_filter_op filter_op, 7007 void *arg) 7008 { 7009 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7010 int ret; 7011 7012 MAC_TYPE_FILTER_SUP(hw->mac.type); 7013 7014 if (filter_op == RTE_ETH_FILTER_NOP) 7015 return 0; 7016 7017 if (arg == NULL) { 7018 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 7019 filter_op); 7020 return -EINVAL; 7021 } 7022 7023 switch (filter_op) { 7024 case RTE_ETH_FILTER_ADD: 7025 ret = ixgbe_add_del_ethertype_filter(dev, 7026 (struct rte_eth_ethertype_filter *)arg, 7027 TRUE); 7028 break; 7029 case RTE_ETH_FILTER_DELETE: 7030 ret = ixgbe_add_del_ethertype_filter(dev, 7031 (struct rte_eth_ethertype_filter *)arg, 7032 FALSE); 7033 break; 7034 case RTE_ETH_FILTER_GET: 7035 ret = ixgbe_get_ethertype_filter(dev, 7036 (struct rte_eth_ethertype_filter *)arg); 7037 break; 7038 default: 7039 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 7040 ret = -EINVAL; 7041 break; 7042 } 7043 return ret; 7044 } 7045 7046 static int 7047 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 7048 enum rte_filter_type filter_type, 7049 enum rte_filter_op filter_op, 7050 void *arg) 7051 { 7052 int ret = 0; 7053 7054 switch (filter_type) { 7055 case RTE_ETH_FILTER_NTUPLE: 7056 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg); 7057 break; 7058 case RTE_ETH_FILTER_ETHERTYPE: 7059 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg); 7060 break; 7061 case RTE_ETH_FILTER_SYN: 7062 ret = ixgbe_syn_filter_handle(dev, filter_op, arg); 7063 break; 7064 case RTE_ETH_FILTER_FDIR: 7065 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg); 7066 break; 7067 case RTE_ETH_FILTER_L2_TUNNEL: 7068 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg); 7069 break; 7070 case RTE_ETH_FILTER_GENERIC: 7071 if (filter_op != RTE_ETH_FILTER_GET) 7072 return -EINVAL; 7073 *(const void **)arg = &ixgbe_flow_ops; 7074 break; 7075 default: 7076 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 7077 filter_type); 7078 ret = -EINVAL; 7079 break; 7080 } 7081 7082 return ret; 7083 } 7084 7085 static u8 * 7086 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw, 7087 u8 **mc_addr_ptr, u32 *vmdq) 7088 { 7089 u8 *mc_addr; 7090 7091 *vmdq = 0; 7092 mc_addr = *mc_addr_ptr; 7093 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr)); 7094 return mc_addr; 7095 } 7096 7097 static int 7098 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 7099 struct rte_ether_addr *mc_addr_set, 7100 uint32_t nb_mc_addr) 7101 { 7102 struct ixgbe_hw *hw; 7103 u8 *mc_addr_list; 7104 7105 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7106 mc_addr_list = (u8 *)mc_addr_set; 7107 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr, 7108 ixgbe_dev_addr_list_itr, TRUE); 7109 } 7110 7111 static uint64_t 7112 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev) 7113 { 7114 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7115 uint64_t systime_cycles; 7116 7117 switch (hw->mac.type) { 7118 case ixgbe_mac_X550: 7119 case ixgbe_mac_X550EM_x: 7120 case ixgbe_mac_X550EM_a: 7121 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */ 7122 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 7123 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 7124 * NSEC_PER_SEC; 7125 break; 7126 default: 7127 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 7128 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 7129 << 32; 7130 } 7131 7132 return systime_cycles; 7133 } 7134 7135 static uint64_t 7136 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) 7137 { 7138 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7139 uint64_t rx_tstamp_cycles; 7140 7141 switch (hw->mac.type) { 7142 case ixgbe_mac_X550: 7143 case ixgbe_mac_X550EM_x: 7144 case ixgbe_mac_X550EM_a: 7145 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 7146 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 7147 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 7148 * NSEC_PER_SEC; 7149 break; 7150 default: 7151 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 7152 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 7153 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 7154 << 32; 7155 } 7156 7157 return rx_tstamp_cycles; 7158 } 7159 7160 static uint64_t 7161 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 7162 { 7163 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7164 uint64_t tx_tstamp_cycles; 7165 7166 switch (hw->mac.type) { 7167 case ixgbe_mac_X550: 7168 case ixgbe_mac_X550EM_x: 7169 case ixgbe_mac_X550EM_a: 7170 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 7171 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 7172 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 7173 * NSEC_PER_SEC; 7174 break; 7175 default: 7176 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 7177 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 7178 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 7179 << 32; 7180 } 7181 7182 return tx_tstamp_cycles; 7183 } 7184 7185 static void 7186 ixgbe_start_timecounters(struct rte_eth_dev *dev) 7187 { 7188 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7189 struct ixgbe_adapter *adapter = dev->data->dev_private; 7190 struct rte_eth_link link; 7191 uint32_t incval = 0; 7192 uint32_t shift = 0; 7193 7194 /* Get current link speed. */ 7195 ixgbe_dev_link_update(dev, 1); 7196 rte_eth_linkstatus_get(dev, &link); 7197 7198 switch (link.link_speed) { 7199 case ETH_SPEED_NUM_100M: 7200 incval = IXGBE_INCVAL_100; 7201 shift = IXGBE_INCVAL_SHIFT_100; 7202 break; 7203 case ETH_SPEED_NUM_1G: 7204 incval = IXGBE_INCVAL_1GB; 7205 shift = IXGBE_INCVAL_SHIFT_1GB; 7206 break; 7207 case ETH_SPEED_NUM_10G: 7208 default: 7209 incval = IXGBE_INCVAL_10GB; 7210 shift = IXGBE_INCVAL_SHIFT_10GB; 7211 break; 7212 } 7213 7214 switch (hw->mac.type) { 7215 case ixgbe_mac_X550: 7216 case ixgbe_mac_X550EM_x: 7217 case ixgbe_mac_X550EM_a: 7218 /* Independent of link speed. */ 7219 incval = 1; 7220 /* Cycles read will be interpreted as ns. */ 7221 shift = 0; 7222 /* Fall-through */ 7223 case ixgbe_mac_X540: 7224 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval); 7225 break; 7226 case ixgbe_mac_82599EB: 7227 incval >>= IXGBE_INCVAL_SHIFT_82599; 7228 shift -= IXGBE_INCVAL_SHIFT_82599; 7229 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 7230 (1 << IXGBE_INCPER_SHIFT_82599) | incval); 7231 break; 7232 default: 7233 /* Not supported. */ 7234 return; 7235 } 7236 7237 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 7238 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 7239 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 7240 7241 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 7242 adapter->systime_tc.cc_shift = shift; 7243 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; 7244 7245 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 7246 adapter->rx_tstamp_tc.cc_shift = shift; 7247 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 7248 7249 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 7250 adapter->tx_tstamp_tc.cc_shift = shift; 7251 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 7252 } 7253 7254 static int 7255 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 7256 { 7257 struct ixgbe_adapter *adapter = dev->data->dev_private; 7258 7259 adapter->systime_tc.nsec += delta; 7260 adapter->rx_tstamp_tc.nsec += delta; 7261 adapter->tx_tstamp_tc.nsec += delta; 7262 7263 return 0; 7264 } 7265 7266 static int 7267 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 7268 { 7269 uint64_t ns; 7270 struct ixgbe_adapter *adapter = dev->data->dev_private; 7271 7272 ns = rte_timespec_to_ns(ts); 7273 /* Set the timecounters to a new value. */ 7274 adapter->systime_tc.nsec = ns; 7275 adapter->rx_tstamp_tc.nsec = ns; 7276 adapter->tx_tstamp_tc.nsec = ns; 7277 7278 return 0; 7279 } 7280 7281 static int 7282 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 7283 { 7284 uint64_t ns, systime_cycles; 7285 struct ixgbe_adapter *adapter = dev->data->dev_private; 7286 7287 systime_cycles = ixgbe_read_systime_cyclecounter(dev); 7288 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 7289 *ts = rte_ns_to_timespec(ns); 7290 7291 return 0; 7292 } 7293 7294 static int 7295 ixgbe_timesync_enable(struct rte_eth_dev *dev) 7296 { 7297 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7298 uint32_t tsync_ctl; 7299 uint32_t tsauxc; 7300 7301 /* Stop the timesync system time. */ 7302 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0); 7303 /* Reset the timesync system time value. */ 7304 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0); 7305 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0); 7306 7307 /* Enable system time for platforms where it isn't on by default. */ 7308 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC); 7309 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME; 7310 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc); 7311 7312 ixgbe_start_timecounters(dev); 7313 7314 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7315 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 7316 (RTE_ETHER_TYPE_1588 | 7317 IXGBE_ETQF_FILTER_EN | 7318 IXGBE_ETQF_1588)); 7319 7320 /* Enable timestamping of received PTP packets. */ 7321 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7322 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED; 7323 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7324 7325 /* Enable timestamping of transmitted PTP packets. */ 7326 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7327 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED; 7328 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7329 7330 IXGBE_WRITE_FLUSH(hw); 7331 7332 return 0; 7333 } 7334 7335 static int 7336 ixgbe_timesync_disable(struct rte_eth_dev *dev) 7337 { 7338 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7339 uint32_t tsync_ctl; 7340 7341 /* Disable timestamping of transmitted PTP packets. */ 7342 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7343 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED; 7344 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7345 7346 /* Disable timestamping of received PTP packets. */ 7347 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7348 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED; 7349 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7350 7351 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7352 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0); 7353 7354 /* Stop incrementating the System Time registers. */ 7355 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0); 7356 7357 return 0; 7358 } 7359 7360 static int 7361 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 7362 struct timespec *timestamp, 7363 uint32_t flags __rte_unused) 7364 { 7365 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7366 struct ixgbe_adapter *adapter = dev->data->dev_private; 7367 uint32_t tsync_rxctl; 7368 uint64_t rx_tstamp_cycles; 7369 uint64_t ns; 7370 7371 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7372 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0) 7373 return -EINVAL; 7374 7375 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev); 7376 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 7377 *timestamp = rte_ns_to_timespec(ns); 7378 7379 return 0; 7380 } 7381 7382 static int 7383 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 7384 struct timespec *timestamp) 7385 { 7386 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7387 struct ixgbe_adapter *adapter = dev->data->dev_private; 7388 uint32_t tsync_txctl; 7389 uint64_t tx_tstamp_cycles; 7390 uint64_t ns; 7391 7392 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7393 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0) 7394 return -EINVAL; 7395 7396 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev); 7397 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 7398 *timestamp = rte_ns_to_timespec(ns); 7399 7400 return 0; 7401 } 7402 7403 static int 7404 ixgbe_get_reg_length(struct rte_eth_dev *dev) 7405 { 7406 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7407 int count = 0; 7408 int g_ind = 0; 7409 const struct reg_info *reg_group; 7410 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7411 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7412 7413 while ((reg_group = reg_set[g_ind++])) 7414 count += ixgbe_regs_group_count(reg_group); 7415 7416 return count; 7417 } 7418 7419 static int 7420 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused) 7421 { 7422 int count = 0; 7423 int g_ind = 0; 7424 const struct reg_info *reg_group; 7425 7426 while ((reg_group = ixgbevf_regs[g_ind++])) 7427 count += ixgbe_regs_group_count(reg_group); 7428 7429 return count; 7430 } 7431 7432 static int 7433 ixgbe_get_regs(struct rte_eth_dev *dev, 7434 struct rte_dev_reg_info *regs) 7435 { 7436 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7437 uint32_t *data = regs->data; 7438 int g_ind = 0; 7439 int count = 0; 7440 const struct reg_info *reg_group; 7441 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7442 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7443 7444 if (data == NULL) { 7445 regs->length = ixgbe_get_reg_length(dev); 7446 regs->width = sizeof(uint32_t); 7447 return 0; 7448 } 7449 7450 /* Support only full register dump */ 7451 if ((regs->length == 0) || 7452 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) { 7453 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7454 hw->device_id; 7455 while ((reg_group = reg_set[g_ind++])) 7456 count += ixgbe_read_regs_group(dev, &data[count], 7457 reg_group); 7458 return 0; 7459 } 7460 7461 return -ENOTSUP; 7462 } 7463 7464 static int 7465 ixgbevf_get_regs(struct rte_eth_dev *dev, 7466 struct rte_dev_reg_info *regs) 7467 { 7468 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7469 uint32_t *data = regs->data; 7470 int g_ind = 0; 7471 int count = 0; 7472 const struct reg_info *reg_group; 7473 7474 if (data == NULL) { 7475 regs->length = ixgbevf_get_reg_length(dev); 7476 regs->width = sizeof(uint32_t); 7477 return 0; 7478 } 7479 7480 /* Support only full register dump */ 7481 if ((regs->length == 0) || 7482 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) { 7483 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7484 hw->device_id; 7485 while ((reg_group = ixgbevf_regs[g_ind++])) 7486 count += ixgbe_read_regs_group(dev, &data[count], 7487 reg_group); 7488 return 0; 7489 } 7490 7491 return -ENOTSUP; 7492 } 7493 7494 static int 7495 ixgbe_get_eeprom_length(struct rte_eth_dev *dev) 7496 { 7497 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7498 7499 /* Return unit is byte count */ 7500 return hw->eeprom.word_size * 2; 7501 } 7502 7503 static int 7504 ixgbe_get_eeprom(struct rte_eth_dev *dev, 7505 struct rte_dev_eeprom_info *in_eeprom) 7506 { 7507 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7508 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7509 uint16_t *data = in_eeprom->data; 7510 int first, length; 7511 7512 first = in_eeprom->offset >> 1; 7513 length = in_eeprom->length >> 1; 7514 if ((first > hw->eeprom.word_size) || 7515 ((first + length) > hw->eeprom.word_size)) 7516 return -EINVAL; 7517 7518 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7519 7520 return eeprom->ops.read_buffer(hw, first, length, data); 7521 } 7522 7523 static int 7524 ixgbe_set_eeprom(struct rte_eth_dev *dev, 7525 struct rte_dev_eeprom_info *in_eeprom) 7526 { 7527 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7528 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7529 uint16_t *data = in_eeprom->data; 7530 int first, length; 7531 7532 first = in_eeprom->offset >> 1; 7533 length = in_eeprom->length >> 1; 7534 if ((first > hw->eeprom.word_size) || 7535 ((first + length) > hw->eeprom.word_size)) 7536 return -EINVAL; 7537 7538 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7539 7540 return eeprom->ops.write_buffer(hw, first, length, data); 7541 } 7542 7543 static int 7544 ixgbe_get_module_info(struct rte_eth_dev *dev, 7545 struct rte_eth_dev_module_info *modinfo) 7546 { 7547 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7548 uint32_t status; 7549 uint8_t sff8472_rev, addr_mode; 7550 bool page_swap = false; 7551 7552 /* Check whether we support SFF-8472 or not */ 7553 status = hw->phy.ops.read_i2c_eeprom(hw, 7554 IXGBE_SFF_SFF_8472_COMP, 7555 &sff8472_rev); 7556 if (status != 0) 7557 return -EIO; 7558 7559 /* addressing mode is not supported */ 7560 status = hw->phy.ops.read_i2c_eeprom(hw, 7561 IXGBE_SFF_SFF_8472_SWAP, 7562 &addr_mode); 7563 if (status != 0) 7564 return -EIO; 7565 7566 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 7567 PMD_DRV_LOG(ERR, 7568 "Address change required to access page 0xA2, " 7569 "but not supported. Please report the module " 7570 "type to the driver maintainers."); 7571 page_swap = true; 7572 } 7573 7574 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) { 7575 /* We have a SFP, but it does not support SFF-8472 */ 7576 modinfo->type = RTE_ETH_MODULE_SFF_8079; 7577 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 7578 } else { 7579 /* We have a SFP which supports a revision of SFF-8472. */ 7580 modinfo->type = RTE_ETH_MODULE_SFF_8472; 7581 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 7582 } 7583 7584 return 0; 7585 } 7586 7587 static int 7588 ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 7589 struct rte_dev_eeprom_info *info) 7590 { 7591 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7592 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 7593 uint8_t databyte = 0xFF; 7594 uint8_t *data = info->data; 7595 uint32_t i = 0; 7596 7597 if (info->length == 0) 7598 return -EINVAL; 7599 7600 for (i = info->offset; i < info->offset + info->length; i++) { 7601 if (i < RTE_ETH_MODULE_SFF_8079_LEN) 7602 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 7603 else 7604 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 7605 7606 if (status != 0) 7607 return -EIO; 7608 7609 data[i - info->offset] = databyte; 7610 } 7611 7612 return 0; 7613 } 7614 7615 uint16_t 7616 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) { 7617 switch (mac_type) { 7618 case ixgbe_mac_X550: 7619 case ixgbe_mac_X550EM_x: 7620 case ixgbe_mac_X550EM_a: 7621 return ETH_RSS_RETA_SIZE_512; 7622 case ixgbe_mac_X550_vf: 7623 case ixgbe_mac_X550EM_x_vf: 7624 case ixgbe_mac_X550EM_a_vf: 7625 return ETH_RSS_RETA_SIZE_64; 7626 case ixgbe_mac_X540_vf: 7627 case ixgbe_mac_82599_vf: 7628 return 0; 7629 default: 7630 return ETH_RSS_RETA_SIZE_128; 7631 } 7632 } 7633 7634 uint32_t 7635 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) { 7636 switch (mac_type) { 7637 case ixgbe_mac_X550: 7638 case ixgbe_mac_X550EM_x: 7639 case ixgbe_mac_X550EM_a: 7640 if (reta_idx < ETH_RSS_RETA_SIZE_128) 7641 return IXGBE_RETA(reta_idx >> 2); 7642 else 7643 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2); 7644 case ixgbe_mac_X550_vf: 7645 case ixgbe_mac_X550EM_x_vf: 7646 case ixgbe_mac_X550EM_a_vf: 7647 return IXGBE_VFRETA(reta_idx >> 2); 7648 default: 7649 return IXGBE_RETA(reta_idx >> 2); 7650 } 7651 } 7652 7653 uint32_t 7654 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) { 7655 switch (mac_type) { 7656 case ixgbe_mac_X550_vf: 7657 case ixgbe_mac_X550EM_x_vf: 7658 case ixgbe_mac_X550EM_a_vf: 7659 return IXGBE_VFMRQC; 7660 default: 7661 return IXGBE_MRQC; 7662 } 7663 } 7664 7665 uint32_t 7666 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) { 7667 switch (mac_type) { 7668 case ixgbe_mac_X550_vf: 7669 case ixgbe_mac_X550EM_x_vf: 7670 case ixgbe_mac_X550EM_a_vf: 7671 return IXGBE_VFRSSRK(i); 7672 default: 7673 return IXGBE_RSSRK(i); 7674 } 7675 } 7676 7677 bool 7678 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) { 7679 switch (mac_type) { 7680 case ixgbe_mac_82599_vf: 7681 case ixgbe_mac_X540_vf: 7682 return 0; 7683 default: 7684 return 1; 7685 } 7686 } 7687 7688 static int 7689 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 7690 struct rte_eth_dcb_info *dcb_info) 7691 { 7692 struct ixgbe_dcb_config *dcb_config = 7693 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 7694 struct ixgbe_dcb_tc_config *tc; 7695 struct rte_eth_dcb_tc_queue_mapping *tc_queue; 7696 uint8_t nb_tcs; 7697 uint8_t i, j; 7698 7699 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG) 7700 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs; 7701 else 7702 dcb_info->nb_tcs = 1; 7703 7704 tc_queue = &dcb_info->tc_queue; 7705 nb_tcs = dcb_info->nb_tcs; 7706 7707 if (dcb_config->vt_mode) { /* vt is enabled*/ 7708 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf = 7709 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf; 7710 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7711 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i]; 7712 if (RTE_ETH_DEV_SRIOV(dev).active > 0) { 7713 for (j = 0; j < nb_tcs; j++) { 7714 tc_queue->tc_rxq[0][j].base = j; 7715 tc_queue->tc_rxq[0][j].nb_queue = 1; 7716 tc_queue->tc_txq[0][j].base = j; 7717 tc_queue->tc_txq[0][j].nb_queue = 1; 7718 } 7719 } else { 7720 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) { 7721 for (j = 0; j < nb_tcs; j++) { 7722 tc_queue->tc_rxq[i][j].base = 7723 i * nb_tcs + j; 7724 tc_queue->tc_rxq[i][j].nb_queue = 1; 7725 tc_queue->tc_txq[i][j].base = 7726 i * nb_tcs + j; 7727 tc_queue->tc_txq[i][j].nb_queue = 1; 7728 } 7729 } 7730 } 7731 } else { /* vt is disabled*/ 7732 struct rte_eth_dcb_rx_conf *rx_conf = 7733 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 7734 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7735 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i]; 7736 if (dcb_info->nb_tcs == ETH_4_TCS) { 7737 for (i = 0; i < dcb_info->nb_tcs; i++) { 7738 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32; 7739 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7740 } 7741 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7742 dcb_info->tc_queue.tc_txq[0][1].base = 64; 7743 dcb_info->tc_queue.tc_txq[0][2].base = 96; 7744 dcb_info->tc_queue.tc_txq[0][3].base = 112; 7745 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64; 7746 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7747 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7748 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7749 } else if (dcb_info->nb_tcs == ETH_8_TCS) { 7750 for (i = 0; i < dcb_info->nb_tcs; i++) { 7751 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16; 7752 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7753 } 7754 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7755 dcb_info->tc_queue.tc_txq[0][1].base = 32; 7756 dcb_info->tc_queue.tc_txq[0][2].base = 64; 7757 dcb_info->tc_queue.tc_txq[0][3].base = 80; 7758 dcb_info->tc_queue.tc_txq[0][4].base = 96; 7759 dcb_info->tc_queue.tc_txq[0][5].base = 104; 7760 dcb_info->tc_queue.tc_txq[0][6].base = 112; 7761 dcb_info->tc_queue.tc_txq[0][7].base = 120; 7762 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32; 7763 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7764 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7765 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7766 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8; 7767 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8; 7768 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8; 7769 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8; 7770 } 7771 } 7772 for (i = 0; i < dcb_info->nb_tcs; i++) { 7773 tc = &dcb_config->tc_config[i]; 7774 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent; 7775 } 7776 return 0; 7777 } 7778 7779 /* Update e-tag ether type */ 7780 static int 7781 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw, 7782 uint16_t ether_type) 7783 { 7784 uint32_t etag_etype; 7785 7786 if (hw->mac.type != ixgbe_mac_X550 && 7787 hw->mac.type != ixgbe_mac_X550EM_x && 7788 hw->mac.type != ixgbe_mac_X550EM_a) { 7789 return -ENOTSUP; 7790 } 7791 7792 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7793 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK; 7794 etag_etype |= ether_type; 7795 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7796 IXGBE_WRITE_FLUSH(hw); 7797 7798 return 0; 7799 } 7800 7801 /* Config l2 tunnel ether type */ 7802 static int 7803 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev, 7804 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7805 { 7806 int ret = 0; 7807 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7808 struct ixgbe_l2_tn_info *l2_tn_info = 7809 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7810 7811 if (l2_tunnel == NULL) 7812 return -EINVAL; 7813 7814 switch (l2_tunnel->l2_tunnel_type) { 7815 case RTE_L2_TUNNEL_TYPE_E_TAG: 7816 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type; 7817 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type); 7818 break; 7819 default: 7820 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7821 ret = -EINVAL; 7822 break; 7823 } 7824 7825 return ret; 7826 } 7827 7828 /* Enable e-tag tunnel */ 7829 static int 7830 ixgbe_e_tag_enable(struct ixgbe_hw *hw) 7831 { 7832 uint32_t etag_etype; 7833 7834 if (hw->mac.type != ixgbe_mac_X550 && 7835 hw->mac.type != ixgbe_mac_X550EM_x && 7836 hw->mac.type != ixgbe_mac_X550EM_a) { 7837 return -ENOTSUP; 7838 } 7839 7840 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7841 etag_etype |= IXGBE_ETAG_ETYPE_VALID; 7842 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7843 IXGBE_WRITE_FLUSH(hw); 7844 7845 return 0; 7846 } 7847 7848 /* Enable l2 tunnel */ 7849 static int 7850 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev, 7851 enum rte_eth_tunnel_type l2_tunnel_type) 7852 { 7853 int ret = 0; 7854 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7855 struct ixgbe_l2_tn_info *l2_tn_info = 7856 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7857 7858 switch (l2_tunnel_type) { 7859 case RTE_L2_TUNNEL_TYPE_E_TAG: 7860 l2_tn_info->e_tag_en = TRUE; 7861 ret = ixgbe_e_tag_enable(hw); 7862 break; 7863 default: 7864 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7865 ret = -EINVAL; 7866 break; 7867 } 7868 7869 return ret; 7870 } 7871 7872 /* Disable e-tag tunnel */ 7873 static int 7874 ixgbe_e_tag_disable(struct ixgbe_hw *hw) 7875 { 7876 uint32_t etag_etype; 7877 7878 if (hw->mac.type != ixgbe_mac_X550 && 7879 hw->mac.type != ixgbe_mac_X550EM_x && 7880 hw->mac.type != ixgbe_mac_X550EM_a) { 7881 return -ENOTSUP; 7882 } 7883 7884 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7885 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID; 7886 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7887 IXGBE_WRITE_FLUSH(hw); 7888 7889 return 0; 7890 } 7891 7892 /* Disable l2 tunnel */ 7893 static int 7894 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev, 7895 enum rte_eth_tunnel_type l2_tunnel_type) 7896 { 7897 int ret = 0; 7898 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7899 struct ixgbe_l2_tn_info *l2_tn_info = 7900 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7901 7902 switch (l2_tunnel_type) { 7903 case RTE_L2_TUNNEL_TYPE_E_TAG: 7904 l2_tn_info->e_tag_en = FALSE; 7905 ret = ixgbe_e_tag_disable(hw); 7906 break; 7907 default: 7908 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7909 ret = -EINVAL; 7910 break; 7911 } 7912 7913 return ret; 7914 } 7915 7916 static int 7917 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev, 7918 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7919 { 7920 int ret = 0; 7921 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7922 uint32_t i, rar_entries; 7923 uint32_t rar_low, rar_high; 7924 7925 if (hw->mac.type != ixgbe_mac_X550 && 7926 hw->mac.type != ixgbe_mac_X550EM_x && 7927 hw->mac.type != ixgbe_mac_X550EM_a) { 7928 return -ENOTSUP; 7929 } 7930 7931 rar_entries = ixgbe_get_num_rx_addrs(hw); 7932 7933 for (i = 1; i < rar_entries; i++) { 7934 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7935 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 7936 if ((rar_high & IXGBE_RAH_AV) && 7937 (rar_high & IXGBE_RAH_ADTYPE) && 7938 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) == 7939 l2_tunnel->tunnel_id)) { 7940 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 7941 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 7942 7943 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL); 7944 7945 return ret; 7946 } 7947 } 7948 7949 return ret; 7950 } 7951 7952 static int 7953 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev, 7954 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7955 { 7956 int ret = 0; 7957 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7958 uint32_t i, rar_entries; 7959 uint32_t rar_low, rar_high; 7960 7961 if (hw->mac.type != ixgbe_mac_X550 && 7962 hw->mac.type != ixgbe_mac_X550EM_x && 7963 hw->mac.type != ixgbe_mac_X550EM_a) { 7964 return -ENOTSUP; 7965 } 7966 7967 /* One entry for one tunnel. Try to remove potential existing entry. */ 7968 ixgbe_e_tag_filter_del(dev, l2_tunnel); 7969 7970 rar_entries = ixgbe_get_num_rx_addrs(hw); 7971 7972 for (i = 1; i < rar_entries; i++) { 7973 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7974 if (rar_high & IXGBE_RAH_AV) { 7975 continue; 7976 } else { 7977 ixgbe_set_vmdq(hw, i, l2_tunnel->pool); 7978 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE; 7979 rar_low = l2_tunnel->tunnel_id; 7980 7981 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low); 7982 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high); 7983 7984 return ret; 7985 } 7986 } 7987 7988 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full." 7989 " Please remove a rule before adding a new one."); 7990 return -EINVAL; 7991 } 7992 7993 static inline struct ixgbe_l2_tn_filter * 7994 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info, 7995 struct ixgbe_l2_tn_key *key) 7996 { 7997 int ret; 7998 7999 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key); 8000 if (ret < 0) 8001 return NULL; 8002 8003 return l2_tn_info->hash_map[ret]; 8004 } 8005 8006 static inline int 8007 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 8008 struct ixgbe_l2_tn_filter *l2_tn_filter) 8009 { 8010 int ret; 8011 8012 ret = rte_hash_add_key(l2_tn_info->hash_handle, 8013 &l2_tn_filter->key); 8014 8015 if (ret < 0) { 8016 PMD_DRV_LOG(ERR, 8017 "Failed to insert L2 tunnel filter" 8018 " to hash table %d!", 8019 ret); 8020 return ret; 8021 } 8022 8023 l2_tn_info->hash_map[ret] = l2_tn_filter; 8024 8025 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 8026 8027 return 0; 8028 } 8029 8030 static inline int 8031 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 8032 struct ixgbe_l2_tn_key *key) 8033 { 8034 int ret; 8035 struct ixgbe_l2_tn_filter *l2_tn_filter; 8036 8037 ret = rte_hash_del_key(l2_tn_info->hash_handle, key); 8038 8039 if (ret < 0) { 8040 PMD_DRV_LOG(ERR, 8041 "No such L2 tunnel filter to delete %d!", 8042 ret); 8043 return ret; 8044 } 8045 8046 l2_tn_filter = l2_tn_info->hash_map[ret]; 8047 l2_tn_info->hash_map[ret] = NULL; 8048 8049 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 8050 rte_free(l2_tn_filter); 8051 8052 return 0; 8053 } 8054 8055 /* Add l2 tunnel filter */ 8056 int 8057 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 8058 struct rte_eth_l2_tunnel_conf *l2_tunnel, 8059 bool restore) 8060 { 8061 int ret; 8062 struct ixgbe_l2_tn_info *l2_tn_info = 8063 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8064 struct ixgbe_l2_tn_key key; 8065 struct ixgbe_l2_tn_filter *node; 8066 8067 if (!restore) { 8068 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 8069 key.tn_id = l2_tunnel->tunnel_id; 8070 8071 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key); 8072 8073 if (node) { 8074 PMD_DRV_LOG(ERR, 8075 "The L2 tunnel filter already exists!"); 8076 return -EINVAL; 8077 } 8078 8079 node = rte_zmalloc("ixgbe_l2_tn", 8080 sizeof(struct ixgbe_l2_tn_filter), 8081 0); 8082 if (!node) 8083 return -ENOMEM; 8084 8085 rte_memcpy(&node->key, 8086 &key, 8087 sizeof(struct ixgbe_l2_tn_key)); 8088 node->pool = l2_tunnel->pool; 8089 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node); 8090 if (ret < 0) { 8091 rte_free(node); 8092 return ret; 8093 } 8094 } 8095 8096 switch (l2_tunnel->l2_tunnel_type) { 8097 case RTE_L2_TUNNEL_TYPE_E_TAG: 8098 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel); 8099 break; 8100 default: 8101 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8102 ret = -EINVAL; 8103 break; 8104 } 8105 8106 if ((!restore) && (ret < 0)) 8107 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 8108 8109 return ret; 8110 } 8111 8112 /* Delete l2 tunnel filter */ 8113 int 8114 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 8115 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8116 { 8117 int ret; 8118 struct ixgbe_l2_tn_info *l2_tn_info = 8119 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8120 struct ixgbe_l2_tn_key key; 8121 8122 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 8123 key.tn_id = l2_tunnel->tunnel_id; 8124 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 8125 if (ret < 0) 8126 return ret; 8127 8128 switch (l2_tunnel->l2_tunnel_type) { 8129 case RTE_L2_TUNNEL_TYPE_E_TAG: 8130 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel); 8131 break; 8132 default: 8133 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8134 ret = -EINVAL; 8135 break; 8136 } 8137 8138 return ret; 8139 } 8140 8141 /** 8142 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter. 8143 * @dev: pointer to rte_eth_dev structure 8144 * @filter_op:operation will be taken. 8145 * @arg: a pointer to specific structure corresponding to the filter_op 8146 */ 8147 static int 8148 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev, 8149 enum rte_filter_op filter_op, 8150 void *arg) 8151 { 8152 int ret; 8153 8154 if (filter_op == RTE_ETH_FILTER_NOP) 8155 return 0; 8156 8157 if (arg == NULL) { 8158 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 8159 filter_op); 8160 return -EINVAL; 8161 } 8162 8163 switch (filter_op) { 8164 case RTE_ETH_FILTER_ADD: 8165 ret = ixgbe_dev_l2_tunnel_filter_add 8166 (dev, 8167 (struct rte_eth_l2_tunnel_conf *)arg, 8168 FALSE); 8169 break; 8170 case RTE_ETH_FILTER_DELETE: 8171 ret = ixgbe_dev_l2_tunnel_filter_del 8172 (dev, 8173 (struct rte_eth_l2_tunnel_conf *)arg); 8174 break; 8175 default: 8176 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 8177 ret = -EINVAL; 8178 break; 8179 } 8180 return ret; 8181 } 8182 8183 static int 8184 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en) 8185 { 8186 int ret = 0; 8187 uint32_t ctrl; 8188 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8189 8190 if (hw->mac.type != ixgbe_mac_X550 && 8191 hw->mac.type != ixgbe_mac_X550EM_x && 8192 hw->mac.type != ixgbe_mac_X550EM_a) { 8193 return -ENOTSUP; 8194 } 8195 8196 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 8197 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 8198 if (en) 8199 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG; 8200 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 8201 8202 return ret; 8203 } 8204 8205 /* Enable l2 tunnel forwarding */ 8206 static int 8207 ixgbe_dev_l2_tunnel_forwarding_enable 8208 (struct rte_eth_dev *dev, 8209 enum rte_eth_tunnel_type l2_tunnel_type) 8210 { 8211 struct ixgbe_l2_tn_info *l2_tn_info = 8212 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8213 int ret = 0; 8214 8215 switch (l2_tunnel_type) { 8216 case RTE_L2_TUNNEL_TYPE_E_TAG: 8217 l2_tn_info->e_tag_fwd_en = TRUE; 8218 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1); 8219 break; 8220 default: 8221 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8222 ret = -EINVAL; 8223 break; 8224 } 8225 8226 return ret; 8227 } 8228 8229 /* Disable l2 tunnel forwarding */ 8230 static int 8231 ixgbe_dev_l2_tunnel_forwarding_disable 8232 (struct rte_eth_dev *dev, 8233 enum rte_eth_tunnel_type l2_tunnel_type) 8234 { 8235 struct ixgbe_l2_tn_info *l2_tn_info = 8236 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8237 int ret = 0; 8238 8239 switch (l2_tunnel_type) { 8240 case RTE_L2_TUNNEL_TYPE_E_TAG: 8241 l2_tn_info->e_tag_fwd_en = FALSE; 8242 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0); 8243 break; 8244 default: 8245 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8246 ret = -EINVAL; 8247 break; 8248 } 8249 8250 return ret; 8251 } 8252 8253 static int 8254 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev, 8255 struct rte_eth_l2_tunnel_conf *l2_tunnel, 8256 bool en) 8257 { 8258 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 8259 int ret = 0; 8260 uint32_t vmtir, vmvir; 8261 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8262 8263 if (l2_tunnel->vf_id >= pci_dev->max_vfs) { 8264 PMD_DRV_LOG(ERR, 8265 "VF id %u should be less than %u", 8266 l2_tunnel->vf_id, 8267 pci_dev->max_vfs); 8268 return -EINVAL; 8269 } 8270 8271 if (hw->mac.type != ixgbe_mac_X550 && 8272 hw->mac.type != ixgbe_mac_X550EM_x && 8273 hw->mac.type != ixgbe_mac_X550EM_a) { 8274 return -ENOTSUP; 8275 } 8276 8277 if (en) 8278 vmtir = l2_tunnel->tunnel_id; 8279 else 8280 vmtir = 0; 8281 8282 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir); 8283 8284 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id)); 8285 vmvir &= ~IXGBE_VMVIR_TAGA_MASK; 8286 if (en) 8287 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT; 8288 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir); 8289 8290 return ret; 8291 } 8292 8293 /* Enable l2 tunnel tag insertion */ 8294 static int 8295 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev, 8296 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8297 { 8298 int ret = 0; 8299 8300 switch (l2_tunnel->l2_tunnel_type) { 8301 case RTE_L2_TUNNEL_TYPE_E_TAG: 8302 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1); 8303 break; 8304 default: 8305 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8306 ret = -EINVAL; 8307 break; 8308 } 8309 8310 return ret; 8311 } 8312 8313 /* Disable l2 tunnel tag insertion */ 8314 static int 8315 ixgbe_dev_l2_tunnel_insertion_disable 8316 (struct rte_eth_dev *dev, 8317 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8318 { 8319 int ret = 0; 8320 8321 switch (l2_tunnel->l2_tunnel_type) { 8322 case RTE_L2_TUNNEL_TYPE_E_TAG: 8323 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0); 8324 break; 8325 default: 8326 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8327 ret = -EINVAL; 8328 break; 8329 } 8330 8331 return ret; 8332 } 8333 8334 static int 8335 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev, 8336 bool en) 8337 { 8338 int ret = 0; 8339 uint32_t qde; 8340 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8341 8342 if (hw->mac.type != ixgbe_mac_X550 && 8343 hw->mac.type != ixgbe_mac_X550EM_x && 8344 hw->mac.type != ixgbe_mac_X550EM_a) { 8345 return -ENOTSUP; 8346 } 8347 8348 qde = IXGBE_READ_REG(hw, IXGBE_QDE); 8349 if (en) 8350 qde |= IXGBE_QDE_STRIP_TAG; 8351 else 8352 qde &= ~IXGBE_QDE_STRIP_TAG; 8353 qde &= ~IXGBE_QDE_READ; 8354 qde |= IXGBE_QDE_WRITE; 8355 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde); 8356 8357 return ret; 8358 } 8359 8360 /* Enable l2 tunnel tag stripping */ 8361 static int 8362 ixgbe_dev_l2_tunnel_stripping_enable 8363 (struct rte_eth_dev *dev, 8364 enum rte_eth_tunnel_type l2_tunnel_type) 8365 { 8366 int ret = 0; 8367 8368 switch (l2_tunnel_type) { 8369 case RTE_L2_TUNNEL_TYPE_E_TAG: 8370 ret = ixgbe_e_tag_stripping_en_dis(dev, 1); 8371 break; 8372 default: 8373 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8374 ret = -EINVAL; 8375 break; 8376 } 8377 8378 return ret; 8379 } 8380 8381 /* Disable l2 tunnel tag stripping */ 8382 static int 8383 ixgbe_dev_l2_tunnel_stripping_disable 8384 (struct rte_eth_dev *dev, 8385 enum rte_eth_tunnel_type l2_tunnel_type) 8386 { 8387 int ret = 0; 8388 8389 switch (l2_tunnel_type) { 8390 case RTE_L2_TUNNEL_TYPE_E_TAG: 8391 ret = ixgbe_e_tag_stripping_en_dis(dev, 0); 8392 break; 8393 default: 8394 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8395 ret = -EINVAL; 8396 break; 8397 } 8398 8399 return ret; 8400 } 8401 8402 /* Enable/disable l2 tunnel offload functions */ 8403 static int 8404 ixgbe_dev_l2_tunnel_offload_set 8405 (struct rte_eth_dev *dev, 8406 struct rte_eth_l2_tunnel_conf *l2_tunnel, 8407 uint32_t mask, 8408 uint8_t en) 8409 { 8410 int ret = 0; 8411 8412 if (l2_tunnel == NULL) 8413 return -EINVAL; 8414 8415 ret = -EINVAL; 8416 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) { 8417 if (en) 8418 ret = ixgbe_dev_l2_tunnel_enable( 8419 dev, 8420 l2_tunnel->l2_tunnel_type); 8421 else 8422 ret = ixgbe_dev_l2_tunnel_disable( 8423 dev, 8424 l2_tunnel->l2_tunnel_type); 8425 } 8426 8427 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) { 8428 if (en) 8429 ret = ixgbe_dev_l2_tunnel_insertion_enable( 8430 dev, 8431 l2_tunnel); 8432 else 8433 ret = ixgbe_dev_l2_tunnel_insertion_disable( 8434 dev, 8435 l2_tunnel); 8436 } 8437 8438 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) { 8439 if (en) 8440 ret = ixgbe_dev_l2_tunnel_stripping_enable( 8441 dev, 8442 l2_tunnel->l2_tunnel_type); 8443 else 8444 ret = ixgbe_dev_l2_tunnel_stripping_disable( 8445 dev, 8446 l2_tunnel->l2_tunnel_type); 8447 } 8448 8449 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) { 8450 if (en) 8451 ret = ixgbe_dev_l2_tunnel_forwarding_enable( 8452 dev, 8453 l2_tunnel->l2_tunnel_type); 8454 else 8455 ret = ixgbe_dev_l2_tunnel_forwarding_disable( 8456 dev, 8457 l2_tunnel->l2_tunnel_type); 8458 } 8459 8460 return ret; 8461 } 8462 8463 static int 8464 ixgbe_update_vxlan_port(struct ixgbe_hw *hw, 8465 uint16_t port) 8466 { 8467 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port); 8468 IXGBE_WRITE_FLUSH(hw); 8469 8470 return 0; 8471 } 8472 8473 /* There's only one register for VxLAN UDP port. 8474 * So, we cannot add several ports. Will update it. 8475 */ 8476 static int 8477 ixgbe_add_vxlan_port(struct ixgbe_hw *hw, 8478 uint16_t port) 8479 { 8480 if (port == 0) { 8481 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 8482 return -EINVAL; 8483 } 8484 8485 return ixgbe_update_vxlan_port(hw, port); 8486 } 8487 8488 /* We cannot delete the VxLAN port. For there's a register for VxLAN 8489 * UDP port, it must have a value. 8490 * So, will reset it to the original value 0. 8491 */ 8492 static int 8493 ixgbe_del_vxlan_port(struct ixgbe_hw *hw, 8494 uint16_t port) 8495 { 8496 uint16_t cur_port; 8497 8498 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL); 8499 8500 if (cur_port != port) { 8501 PMD_DRV_LOG(ERR, "Port %u does not exist.", port); 8502 return -EINVAL; 8503 } 8504 8505 return ixgbe_update_vxlan_port(hw, 0); 8506 } 8507 8508 /* Add UDP tunneling port */ 8509 static int 8510 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 8511 struct rte_eth_udp_tunnel *udp_tunnel) 8512 { 8513 int ret = 0; 8514 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8515 8516 if (hw->mac.type != ixgbe_mac_X550 && 8517 hw->mac.type != ixgbe_mac_X550EM_x && 8518 hw->mac.type != ixgbe_mac_X550EM_a) { 8519 return -ENOTSUP; 8520 } 8521 8522 if (udp_tunnel == NULL) 8523 return -EINVAL; 8524 8525 switch (udp_tunnel->prot_type) { 8526 case RTE_TUNNEL_TYPE_VXLAN: 8527 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port); 8528 break; 8529 8530 case RTE_TUNNEL_TYPE_GENEVE: 8531 case RTE_TUNNEL_TYPE_TEREDO: 8532 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8533 ret = -EINVAL; 8534 break; 8535 8536 default: 8537 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8538 ret = -EINVAL; 8539 break; 8540 } 8541 8542 return ret; 8543 } 8544 8545 /* Remove UDP tunneling port */ 8546 static int 8547 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 8548 struct rte_eth_udp_tunnel *udp_tunnel) 8549 { 8550 int ret = 0; 8551 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8552 8553 if (hw->mac.type != ixgbe_mac_X550 && 8554 hw->mac.type != ixgbe_mac_X550EM_x && 8555 hw->mac.type != ixgbe_mac_X550EM_a) { 8556 return -ENOTSUP; 8557 } 8558 8559 if (udp_tunnel == NULL) 8560 return -EINVAL; 8561 8562 switch (udp_tunnel->prot_type) { 8563 case RTE_TUNNEL_TYPE_VXLAN: 8564 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port); 8565 break; 8566 case RTE_TUNNEL_TYPE_GENEVE: 8567 case RTE_TUNNEL_TYPE_TEREDO: 8568 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8569 ret = -EINVAL; 8570 break; 8571 default: 8572 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8573 ret = -EINVAL; 8574 break; 8575 } 8576 8577 return ret; 8578 } 8579 8580 static int 8581 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev) 8582 { 8583 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8584 int ret; 8585 8586 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) { 8587 case IXGBE_SUCCESS: 8588 ret = 0; 8589 break; 8590 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 8591 ret = -ENOTSUP; 8592 break; 8593 default: 8594 ret = -EAGAIN; 8595 break; 8596 } 8597 8598 return ret; 8599 } 8600 8601 static int 8602 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev) 8603 { 8604 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8605 int ret; 8606 8607 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) { 8608 case IXGBE_SUCCESS: 8609 ret = 0; 8610 break; 8611 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 8612 ret = -ENOTSUP; 8613 break; 8614 default: 8615 ret = -EAGAIN; 8616 break; 8617 } 8618 8619 return ret; 8620 } 8621 8622 static int 8623 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev) 8624 { 8625 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8626 int ret; 8627 int mode = IXGBEVF_XCAST_MODE_ALLMULTI; 8628 8629 switch (hw->mac.ops.update_xcast_mode(hw, mode)) { 8630 case IXGBE_SUCCESS: 8631 ret = 0; 8632 break; 8633 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 8634 ret = -ENOTSUP; 8635 break; 8636 default: 8637 ret = -EAGAIN; 8638 break; 8639 } 8640 8641 return ret; 8642 } 8643 8644 static int 8645 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev) 8646 { 8647 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8648 int ret; 8649 8650 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) { 8651 case IXGBE_SUCCESS: 8652 ret = 0; 8653 break; 8654 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 8655 ret = -ENOTSUP; 8656 break; 8657 default: 8658 ret = -EAGAIN; 8659 break; 8660 } 8661 8662 return ret; 8663 } 8664 8665 static void ixgbevf_mbx_process(struct rte_eth_dev *dev) 8666 { 8667 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8668 u32 in_msg = 0; 8669 8670 /* peek the message first */ 8671 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM); 8672 8673 /* PF reset VF event */ 8674 if (in_msg == IXGBE_PF_CONTROL_MSG) { 8675 /* dummy mbx read to ack pf */ 8676 if (ixgbe_read_mbx(hw, &in_msg, 1, 0)) 8677 return; 8678 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 8679 NULL); 8680 } 8681 } 8682 8683 static int 8684 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev) 8685 { 8686 uint32_t eicr; 8687 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8688 struct ixgbe_interrupt *intr = 8689 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8690 ixgbevf_intr_disable(dev); 8691 8692 /* read-on-clear nic registers here */ 8693 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR); 8694 intr->flags = 0; 8695 8696 /* only one misc vector supported - mailbox */ 8697 eicr &= IXGBE_VTEICR_MASK; 8698 if (eicr == IXGBE_MISC_VEC_ID) 8699 intr->flags |= IXGBE_FLAG_MAILBOX; 8700 8701 return 0; 8702 } 8703 8704 static int 8705 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev) 8706 { 8707 struct ixgbe_interrupt *intr = 8708 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8709 8710 if (intr->flags & IXGBE_FLAG_MAILBOX) { 8711 ixgbevf_mbx_process(dev); 8712 intr->flags &= ~IXGBE_FLAG_MAILBOX; 8713 } 8714 8715 ixgbevf_intr_enable(dev); 8716 8717 return 0; 8718 } 8719 8720 static void 8721 ixgbevf_dev_interrupt_handler(void *param) 8722 { 8723 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 8724 8725 ixgbevf_dev_interrupt_get_status(dev); 8726 ixgbevf_dev_interrupt_action(dev); 8727 } 8728 8729 /** 8730 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path 8731 * @hw: pointer to hardware structure 8732 * 8733 * Stops the transmit data path and waits for the HW to internally empty 8734 * the Tx security block 8735 **/ 8736 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw) 8737 { 8738 #define IXGBE_MAX_SECTX_POLL 40 8739 8740 int i; 8741 int sectxreg; 8742 8743 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8744 sectxreg |= IXGBE_SECTXCTRL_TX_DIS; 8745 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8746 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) { 8747 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT); 8748 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY) 8749 break; 8750 /* Use interrupt-safe sleep just in case */ 8751 usec_delay(1000); 8752 } 8753 8754 /* For informational purposes only */ 8755 if (i >= IXGBE_MAX_SECTX_POLL) 8756 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security " 8757 "path fully disabled. Continuing with init."); 8758 8759 return IXGBE_SUCCESS; 8760 } 8761 8762 /** 8763 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path 8764 * @hw: pointer to hardware structure 8765 * 8766 * Enables the transmit data path. 8767 **/ 8768 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw) 8769 { 8770 uint32_t sectxreg; 8771 8772 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8773 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS; 8774 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8775 IXGBE_WRITE_FLUSH(hw); 8776 8777 return IXGBE_SUCCESS; 8778 } 8779 8780 /* restore n-tuple filter */ 8781 static inline void 8782 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev) 8783 { 8784 struct ixgbe_filter_info *filter_info = 8785 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8786 struct ixgbe_5tuple_filter *node; 8787 8788 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) { 8789 ixgbe_inject_5tuple_filter(dev, node); 8790 } 8791 } 8792 8793 /* restore ethernet type filter */ 8794 static inline void 8795 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev) 8796 { 8797 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8798 struct ixgbe_filter_info *filter_info = 8799 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8800 int i; 8801 8802 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8803 if (filter_info->ethertype_mask & (1 << i)) { 8804 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 8805 filter_info->ethertype_filters[i].etqf); 8806 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 8807 filter_info->ethertype_filters[i].etqs); 8808 IXGBE_WRITE_FLUSH(hw); 8809 } 8810 } 8811 } 8812 8813 /* restore SYN filter */ 8814 static inline void 8815 ixgbe_syn_filter_restore(struct rte_eth_dev *dev) 8816 { 8817 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8818 struct ixgbe_filter_info *filter_info = 8819 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8820 uint32_t synqf; 8821 8822 synqf = filter_info->syn_info; 8823 8824 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 8825 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 8826 IXGBE_WRITE_FLUSH(hw); 8827 } 8828 } 8829 8830 /* restore L2 tunnel filter */ 8831 static inline void 8832 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev) 8833 { 8834 struct ixgbe_l2_tn_info *l2_tn_info = 8835 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8836 struct ixgbe_l2_tn_filter *node; 8837 struct rte_eth_l2_tunnel_conf l2_tn_conf; 8838 8839 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) { 8840 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type; 8841 l2_tn_conf.tunnel_id = node->key.tn_id; 8842 l2_tn_conf.pool = node->pool; 8843 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE); 8844 } 8845 } 8846 8847 /* restore rss filter */ 8848 static inline void 8849 ixgbe_rss_filter_restore(struct rte_eth_dev *dev) 8850 { 8851 struct ixgbe_filter_info *filter_info = 8852 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8853 8854 if (filter_info->rss_info.conf.queue_num) 8855 ixgbe_config_rss_filter(dev, 8856 &filter_info->rss_info, TRUE); 8857 } 8858 8859 static int 8860 ixgbe_filter_restore(struct rte_eth_dev *dev) 8861 { 8862 ixgbe_ntuple_filter_restore(dev); 8863 ixgbe_ethertype_filter_restore(dev); 8864 ixgbe_syn_filter_restore(dev); 8865 ixgbe_fdir_filter_restore(dev); 8866 ixgbe_l2_tn_filter_restore(dev); 8867 ixgbe_rss_filter_restore(dev); 8868 8869 return 0; 8870 } 8871 8872 static void 8873 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev) 8874 { 8875 struct ixgbe_l2_tn_info *l2_tn_info = 8876 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8877 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8878 8879 if (l2_tn_info->e_tag_en) 8880 (void)ixgbe_e_tag_enable(hw); 8881 8882 if (l2_tn_info->e_tag_fwd_en) 8883 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1); 8884 8885 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type); 8886 } 8887 8888 /* remove all the n-tuple filters */ 8889 void 8890 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev) 8891 { 8892 struct ixgbe_filter_info *filter_info = 8893 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8894 struct ixgbe_5tuple_filter *p_5tuple; 8895 8896 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) 8897 ixgbe_remove_5tuple_filter(dev, p_5tuple); 8898 } 8899 8900 /* remove all the ether type filters */ 8901 void 8902 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev) 8903 { 8904 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8905 struct ixgbe_filter_info *filter_info = 8906 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8907 int i; 8908 8909 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8910 if (filter_info->ethertype_mask & (1 << i) && 8911 !filter_info->ethertype_filters[i].conf) { 8912 (void)ixgbe_ethertype_filter_remove(filter_info, 8913 (uint8_t)i); 8914 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0); 8915 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0); 8916 IXGBE_WRITE_FLUSH(hw); 8917 } 8918 } 8919 } 8920 8921 /* remove the SYN filter */ 8922 void 8923 ixgbe_clear_syn_filter(struct rte_eth_dev *dev) 8924 { 8925 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8926 struct ixgbe_filter_info *filter_info = 8927 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8928 8929 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) { 8930 filter_info->syn_info = 0; 8931 8932 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0); 8933 IXGBE_WRITE_FLUSH(hw); 8934 } 8935 } 8936 8937 /* remove all the L2 tunnel filters */ 8938 int 8939 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev) 8940 { 8941 struct ixgbe_l2_tn_info *l2_tn_info = 8942 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8943 struct ixgbe_l2_tn_filter *l2_tn_filter; 8944 struct rte_eth_l2_tunnel_conf l2_tn_conf; 8945 int ret = 0; 8946 8947 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 8948 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type; 8949 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id; 8950 l2_tn_conf.pool = l2_tn_filter->pool; 8951 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf); 8952 if (ret < 0) 8953 return ret; 8954 } 8955 8956 return 0; 8957 } 8958 8959 void 8960 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev, 8961 struct ixgbe_macsec_setting *macsec_setting) 8962 { 8963 struct ixgbe_macsec_setting *macsec = 8964 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 8965 8966 macsec->offload_en = macsec_setting->offload_en; 8967 macsec->encrypt_en = macsec_setting->encrypt_en; 8968 macsec->replayprotect_en = macsec_setting->replayprotect_en; 8969 } 8970 8971 void 8972 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev) 8973 { 8974 struct ixgbe_macsec_setting *macsec = 8975 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 8976 8977 macsec->offload_en = 0; 8978 macsec->encrypt_en = 0; 8979 macsec->replayprotect_en = 0; 8980 } 8981 8982 void 8983 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev, 8984 struct ixgbe_macsec_setting *macsec_setting) 8985 { 8986 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8987 uint32_t ctrl; 8988 uint8_t en = macsec_setting->encrypt_en; 8989 uint8_t rp = macsec_setting->replayprotect_en; 8990 8991 /** 8992 * Workaround: 8993 * As no ixgbe_disable_sec_rx_path equivalent is 8994 * implemented for tx in the base code, and we are 8995 * not allowed to modify the base code in DPDK, so 8996 * just call the hand-written one directly for now. 8997 * The hardware support has been checked by 8998 * ixgbe_disable_sec_rx_path(). 8999 */ 9000 ixgbe_disable_sec_tx_path_generic(hw); 9001 9002 /* Enable Ethernet CRC (required by MACsec offload) */ 9003 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0); 9004 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP; 9005 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl); 9006 9007 /* Enable the TX and RX crypto engines */ 9008 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 9009 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS; 9010 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl); 9011 9012 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 9013 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS; 9014 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl); 9015 9016 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 9017 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK; 9018 ctrl |= 0x3; 9019 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl); 9020 9021 /* Enable SA lookup */ 9022 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL); 9023 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK; 9024 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT : 9025 IXGBE_LSECTXCTRL_AUTH; 9026 ctrl |= IXGBE_LSECTXCTRL_AISCI; 9027 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK; 9028 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK; 9029 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl); 9030 9031 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL); 9032 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK; 9033 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT; 9034 ctrl &= ~IXGBE_LSECRXCTRL_PLSH; 9035 if (rp) 9036 ctrl |= IXGBE_LSECRXCTRL_RP; 9037 else 9038 ctrl &= ~IXGBE_LSECRXCTRL_RP; 9039 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl); 9040 9041 /* Start the data paths */ 9042 ixgbe_enable_sec_rx_path(hw); 9043 /** 9044 * Workaround: 9045 * As no ixgbe_enable_sec_rx_path equivalent is 9046 * implemented for tx in the base code, and we are 9047 * not allowed to modify the base code in DPDK, so 9048 * just call the hand-written one directly for now. 9049 */ 9050 ixgbe_enable_sec_tx_path_generic(hw); 9051 } 9052 9053 void 9054 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev) 9055 { 9056 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 9057 uint32_t ctrl; 9058 9059 /** 9060 * Workaround: 9061 * As no ixgbe_disable_sec_rx_path equivalent is 9062 * implemented for tx in the base code, and we are 9063 * not allowed to modify the base code in DPDK, so 9064 * just call the hand-written one directly for now. 9065 * The hardware support has been checked by 9066 * ixgbe_disable_sec_rx_path(). 9067 */ 9068 ixgbe_disable_sec_tx_path_generic(hw); 9069 9070 /* Disable the TX and RX crypto engines */ 9071 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 9072 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS; 9073 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl); 9074 9075 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 9076 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS; 9077 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl); 9078 9079 /* Disable SA lookup */ 9080 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL); 9081 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK; 9082 ctrl |= IXGBE_LSECTXCTRL_DISABLE; 9083 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl); 9084 9085 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL); 9086 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK; 9087 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT; 9088 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl); 9089 9090 /* Start the data paths */ 9091 ixgbe_enable_sec_rx_path(hw); 9092 /** 9093 * Workaround: 9094 * As no ixgbe_enable_sec_rx_path equivalent is 9095 * implemented for tx in the base code, and we are 9096 * not allowed to modify the base code in DPDK, so 9097 * just call the hand-written one directly for now. 9098 */ 9099 ixgbe_enable_sec_tx_path_generic(hw); 9100 } 9101 9102 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd); 9103 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map); 9104 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 9105 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd); 9106 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map); 9107 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci"); 9108 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf, 9109 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>"); 9110 9111 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE); 9112 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE); 9113 9114 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX 9115 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG); 9116 #endif 9117 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX 9118 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG); 9119 #endif 9120 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE 9121 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG); 9122 #endif 9123