1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <inttypes.h> 13 #include <netinet/in.h> 14 #include <rte_string_fns.h> 15 #include <rte_byteorder.h> 16 #include <rte_common.h> 17 #include <rte_cycles.h> 18 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_bus_pci.h> 24 #include <rte_branch_prediction.h> 25 #include <rte_memory.h> 26 #include <rte_kvargs.h> 27 #include <rte_eal.h> 28 #include <rte_alarm.h> 29 #include <rte_ether.h> 30 #include <ethdev_driver.h> 31 #include <ethdev_pci.h> 32 #include <rte_malloc.h> 33 #include <rte_random.h> 34 #include <rte_dev.h> 35 #include <rte_hash_crc.h> 36 #ifdef RTE_LIB_SECURITY 37 #include <rte_security_driver.h> 38 #endif 39 40 #include "ixgbe_logs.h" 41 #include "base/ixgbe_api.h" 42 #include "base/ixgbe_vf.h" 43 #include "base/ixgbe_common.h" 44 #include "ixgbe_ethdev.h" 45 #include "ixgbe_bypass.h" 46 #include "ixgbe_rxtx.h" 47 #include "base/ixgbe_type.h" 48 #include "base/ixgbe_phy.h" 49 #include "ixgbe_regs.h" 50 51 /* 52 * High threshold controlling when to start sending XOFF frames. Must be at 53 * least 8 bytes less than receive packet buffer size. This value is in units 54 * of 1024 bytes. 55 */ 56 #define IXGBE_FC_HI 0x80 57 58 /* 59 * Low threshold controlling when to start sending XON frames. This value is 60 * in units of 1024 bytes. 61 */ 62 #define IXGBE_FC_LO 0x40 63 64 /* Timer value included in XOFF frames. */ 65 #define IXGBE_FC_PAUSE 0x680 66 67 /*Default value of Max Rx Queue*/ 68 #define IXGBE_MAX_RX_QUEUE_NUM 128 69 70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */ 71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */ 72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */ 73 74 #define IXGBE_MMW_SIZE_DEFAULT 0x4 75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14 76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */ 77 78 /* 79 * Default values for RX/TX configuration 80 */ 81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32 82 #define IXGBE_DEFAULT_RX_PTHRESH 8 83 #define IXGBE_DEFAULT_RX_HTHRESH 8 84 #define IXGBE_DEFAULT_RX_WTHRESH 0 85 86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32 87 #define IXGBE_DEFAULT_TX_PTHRESH 32 88 #define IXGBE_DEFAULT_TX_HTHRESH 0 89 #define IXGBE_DEFAULT_TX_WTHRESH 0 90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32 91 92 /* Bit shift and mask */ 93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2) 94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t) 95 #define IXGBE_8_BIT_WIDTH CHAR_BIT 96 #define IXGBE_8_BIT_MASK UINT8_MAX 97 98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */ 99 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0])) 101 102 /* Additional timesync values. */ 103 #define NSEC_PER_SEC 1000000000L 104 #define IXGBE_INCVAL_10GB 0x66666666 105 #define IXGBE_INCVAL_1GB 0x40000000 106 #define IXGBE_INCVAL_100 0x50000000 107 #define IXGBE_INCVAL_SHIFT_10GB 28 108 #define IXGBE_INCVAL_SHIFT_1GB 24 109 #define IXGBE_INCVAL_SHIFT_100 21 110 #define IXGBE_INCVAL_SHIFT_82599 7 111 #define IXGBE_INCPER_SHIFT_82599 24 112 113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL 114 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000 117 #define IXGBE_ETAG_ETYPE 0x00005084 118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff 119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000 120 #define IXGBE_RAH_ADTYPE 0x40000000 121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff 122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */ 125 #define IXGBE_QDE_STRIP_TAG 0x00000004 126 #define IXGBE_VTEICR_MASK 0x07 127 128 #define IXGBE_EXVET_VET_EXT_SHIFT 16 129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000 130 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk" 132 133 static const char * const ixgbevf_valid_arguments[] = { 134 IXGBEVF_DEVARG_PFLINK_FULLCHK, 135 NULL 136 }; 137 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev); 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev); 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev); 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev); 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev); 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev); 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev); 146 static int ixgbe_dev_start(struct rte_eth_dev *dev); 147 static int ixgbe_dev_stop(struct rte_eth_dev *dev); 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev); 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev); 150 static int ixgbe_dev_close(struct rte_eth_dev *dev); 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev); 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev, 157 int wait_to_complete); 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev, 159 struct rte_eth_stats *stats); 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev, 161 struct rte_eth_xstat *xstats, unsigned n); 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, 163 struct rte_eth_xstat *xstats, unsigned n); 164 static int 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 166 uint64_t *values, unsigned int n); 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev); 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev); 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 170 struct rte_eth_xstat_name *xstats_names, 171 unsigned int size); 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev, 173 struct rte_eth_xstat_name *xstats_names, unsigned limit); 174 static int ixgbe_dev_xstats_get_names_by_id( 175 struct rte_eth_dev *dev, 176 struct rte_eth_xstat_name *xstats_names, 177 const uint64_t *ids, 178 unsigned int limit); 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 180 uint16_t queue_id, 181 uint8_t stat_idx, 182 uint8_t is_rx); 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 184 size_t fw_size); 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev, 186 struct rte_eth_dev_info *dev_info); 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev, 189 struct rte_eth_dev_info *dev_info); 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 191 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev, 193 uint16_t vlan_id, int on); 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 195 enum rte_vlan_type vlan_type, 196 uint16_t tpid_id); 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, 198 uint16_t queue, bool on); 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, 200 int on); 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, 202 int mask); 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask); 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask); 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue); 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue); 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev); 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev); 209 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev); 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev); 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, 213 struct rte_eth_fc_conf *fc_conf); 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, 215 struct rte_eth_fc_conf *fc_conf); 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 217 struct rte_eth_pfc_conf *pfc_conf); 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 219 struct rte_eth_rss_reta_entry64 *reta_conf, 220 uint16_t reta_size); 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 222 struct rte_eth_rss_reta_entry64 *reta_conf, 223 uint16_t reta_size); 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev); 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev); 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev); 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev); 230 static void ixgbe_dev_interrupt_handler(void *param); 231 static void ixgbe_dev_interrupt_delayed_handler(void *param); 232 static void *ixgbe_dev_setup_link_thread_handler(void *param); 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, 234 uint32_t timeout_ms); 235 236 static int ixgbe_add_rar(struct rte_eth_dev *dev, 237 struct rte_ether_addr *mac_addr, 238 uint32_t index, uint32_t pool); 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index); 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, 241 struct rte_ether_addr *mac_addr); 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config); 243 static bool is_device_supported(struct rte_eth_dev *dev, 244 struct rte_pci_driver *drv); 245 246 /* For Virtual Function support */ 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev); 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev); 249 static int ixgbevf_dev_configure(struct rte_eth_dev *dev); 250 static int ixgbevf_dev_start(struct rte_eth_dev *dev); 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev, 252 int wait_to_complete); 253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev); 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev); 255 static int ixgbevf_dev_reset(struct rte_eth_dev *dev); 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev); 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev); 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev, 259 struct rte_eth_stats *stats); 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev); 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, 262 uint16_t vlan_id, int on); 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, 264 uint16_t queue, int on); 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask); 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask); 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on); 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 269 uint16_t queue_id); 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 271 uint16_t queue_id); 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 273 uint8_t queue, uint8_t msix_vector); 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev); 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev); 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev); 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev); 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev); 279 280 /* For Eth VMDQ APIs support */ 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct 282 rte_ether_addr * mac_addr, uint8_t on); 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on); 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 285 struct rte_eth_mirror_conf *mirror_conf, 286 uint8_t rule_id, uint8_t on); 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, 288 uint8_t rule_id); 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 290 uint16_t queue_id); 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 292 uint16_t queue_id); 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 294 uint8_t queue, uint8_t msix_vector); 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev); 296 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev, 298 struct rte_ether_addr *mac_addr, 299 uint32_t index, uint32_t pool); 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index); 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 302 struct rte_ether_addr *mac_addr); 303 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 304 struct ixgbe_5tuple_filter *filter); 305 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 306 struct ixgbe_5tuple_filter *filter); 307 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 308 enum rte_filter_type filter_type, 309 enum rte_filter_op filter_op, 310 void *arg); 311 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 312 313 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 314 struct rte_ether_addr *mc_addr_set, 315 uint32_t nb_mc_addr); 316 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 317 struct rte_eth_dcb_info *dcb_info); 318 319 static int ixgbe_get_reg_length(struct rte_eth_dev *dev); 320 static int ixgbe_get_regs(struct rte_eth_dev *dev, 321 struct rte_dev_reg_info *regs); 322 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev); 323 static int ixgbe_get_eeprom(struct rte_eth_dev *dev, 324 struct rte_dev_eeprom_info *eeprom); 325 static int ixgbe_set_eeprom(struct rte_eth_dev *dev, 326 struct rte_dev_eeprom_info *eeprom); 327 328 static int ixgbe_get_module_info(struct rte_eth_dev *dev, 329 struct rte_eth_dev_module_info *modinfo); 330 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 331 struct rte_dev_eeprom_info *info); 332 333 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev); 334 static int ixgbevf_get_regs(struct rte_eth_dev *dev, 335 struct rte_dev_reg_info *regs); 336 337 static int ixgbe_timesync_enable(struct rte_eth_dev *dev); 338 static int ixgbe_timesync_disable(struct rte_eth_dev *dev); 339 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 340 struct timespec *timestamp, 341 uint32_t flags); 342 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 343 struct timespec *timestamp); 344 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 345 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev, 346 struct timespec *timestamp); 347 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev, 348 const struct timespec *timestamp); 349 static void ixgbevf_dev_interrupt_handler(void *param); 350 351 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 352 struct rte_eth_udp_tunnel *udp_tunnel); 353 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 354 struct rte_eth_udp_tunnel *udp_tunnel); 355 static int ixgbe_filter_restore(struct rte_eth_dev *dev); 356 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev); 357 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw); 358 359 /* 360 * Define VF Stats MACRO for Non "cleared on read" register 361 */ 362 #define UPDATE_VF_STAT(reg, last, cur) \ 363 { \ 364 uint32_t latest = IXGBE_READ_REG(hw, reg); \ 365 cur += (latest - last) & UINT_MAX; \ 366 last = latest; \ 367 } 368 369 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \ 370 { \ 371 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \ 372 u64 new_msb = IXGBE_READ_REG(hw, msb); \ 373 u64 latest = ((new_msb << 32) | new_lsb); \ 374 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \ 375 last = latest; \ 376 } 377 378 #define IXGBE_SET_HWSTRIP(h, q) do {\ 379 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 380 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 381 (h)->bitmap[idx] |= 1 << bit;\ 382 } while (0) 383 384 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\ 385 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 386 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 387 (h)->bitmap[idx] &= ~(1 << bit);\ 388 } while (0) 389 390 #define IXGBE_GET_HWSTRIP(h, q, r) do {\ 391 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 392 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 393 (r) = (h)->bitmap[idx] >> bit & 1;\ 394 } while (0) 395 396 /* 397 * The set of PCI devices this driver supports 398 */ 399 static const struct rte_pci_id pci_id_ixgbe_map[] = { 400 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) }, 401 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) }, 402 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) }, 403 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) }, 404 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) }, 405 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) }, 406 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) }, 407 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) }, 408 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) }, 409 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) }, 410 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) }, 411 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) }, 412 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) }, 413 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) }, 414 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) }, 415 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) }, 416 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) }, 417 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) }, 418 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) }, 419 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) }, 420 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) }, 421 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) }, 422 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) }, 423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) }, 424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) }, 425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) }, 426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) }, 427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) }, 428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) }, 429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) }, 430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) }, 431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) }, 432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) }, 433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) }, 434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) }, 435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) }, 436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) }, 437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) }, 438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) }, 439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) }, 440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) }, 441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) }, 442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) }, 443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) }, 444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) }, 445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) }, 446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) }, 447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) }, 448 #ifdef RTE_LIBRTE_IXGBE_BYPASS 449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) }, 450 #endif 451 { .vendor_id = 0, /* sentinel */ }, 452 }; 453 454 /* 455 * The set of PCI devices this driver supports (for 82599 VF) 456 */ 457 static const struct rte_pci_id pci_id_ixgbevf_map[] = { 458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) }, 459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) }, 460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) }, 461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) }, 462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) }, 463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) }, 464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) }, 465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) }, 466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) }, 467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) }, 468 { .vendor_id = 0, /* sentinel */ }, 469 }; 470 471 static const struct rte_eth_desc_lim rx_desc_lim = { 472 .nb_max = IXGBE_MAX_RING_DESC, 473 .nb_min = IXGBE_MIN_RING_DESC, 474 .nb_align = IXGBE_RXD_ALIGN, 475 }; 476 477 static const struct rte_eth_desc_lim tx_desc_lim = { 478 .nb_max = IXGBE_MAX_RING_DESC, 479 .nb_min = IXGBE_MIN_RING_DESC, 480 .nb_align = IXGBE_TXD_ALIGN, 481 .nb_seg_max = IXGBE_TX_MAX_SEG, 482 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG, 483 }; 484 485 static const struct eth_dev_ops ixgbe_eth_dev_ops = { 486 .dev_configure = ixgbe_dev_configure, 487 .dev_start = ixgbe_dev_start, 488 .dev_stop = ixgbe_dev_stop, 489 .dev_set_link_up = ixgbe_dev_set_link_up, 490 .dev_set_link_down = ixgbe_dev_set_link_down, 491 .dev_close = ixgbe_dev_close, 492 .dev_reset = ixgbe_dev_reset, 493 .promiscuous_enable = ixgbe_dev_promiscuous_enable, 494 .promiscuous_disable = ixgbe_dev_promiscuous_disable, 495 .allmulticast_enable = ixgbe_dev_allmulticast_enable, 496 .allmulticast_disable = ixgbe_dev_allmulticast_disable, 497 .link_update = ixgbe_dev_link_update, 498 .stats_get = ixgbe_dev_stats_get, 499 .xstats_get = ixgbe_dev_xstats_get, 500 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id, 501 .stats_reset = ixgbe_dev_stats_reset, 502 .xstats_reset = ixgbe_dev_xstats_reset, 503 .xstats_get_names = ixgbe_dev_xstats_get_names, 504 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id, 505 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set, 506 .fw_version_get = ixgbe_fw_version_get, 507 .dev_infos_get = ixgbe_dev_info_get, 508 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 509 .mtu_set = ixgbe_dev_mtu_set, 510 .vlan_filter_set = ixgbe_vlan_filter_set, 511 .vlan_tpid_set = ixgbe_vlan_tpid_set, 512 .vlan_offload_set = ixgbe_vlan_offload_set, 513 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set, 514 .rx_queue_start = ixgbe_dev_rx_queue_start, 515 .rx_queue_stop = ixgbe_dev_rx_queue_stop, 516 .tx_queue_start = ixgbe_dev_tx_queue_start, 517 .tx_queue_stop = ixgbe_dev_tx_queue_stop, 518 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 519 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable, 520 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable, 521 .rx_queue_release = ixgbe_dev_rx_queue_release, 522 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 523 .tx_queue_release = ixgbe_dev_tx_queue_release, 524 .dev_led_on = ixgbe_dev_led_on, 525 .dev_led_off = ixgbe_dev_led_off, 526 .flow_ctrl_get = ixgbe_flow_ctrl_get, 527 .flow_ctrl_set = ixgbe_flow_ctrl_set, 528 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set, 529 .mac_addr_add = ixgbe_add_rar, 530 .mac_addr_remove = ixgbe_remove_rar, 531 .mac_addr_set = ixgbe_set_default_mac_addr, 532 .uc_hash_table_set = ixgbe_uc_hash_table_set, 533 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set, 534 .mirror_rule_set = ixgbe_mirror_rule_set, 535 .mirror_rule_reset = ixgbe_mirror_rule_reset, 536 .set_queue_rate_limit = ixgbe_set_queue_rate_limit, 537 .reta_update = ixgbe_dev_rss_reta_update, 538 .reta_query = ixgbe_dev_rss_reta_query, 539 .rss_hash_update = ixgbe_dev_rss_hash_update, 540 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 541 .filter_ctrl = ixgbe_dev_filter_ctrl, 542 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 543 .rxq_info_get = ixgbe_rxq_info_get, 544 .txq_info_get = ixgbe_txq_info_get, 545 .timesync_enable = ixgbe_timesync_enable, 546 .timesync_disable = ixgbe_timesync_disable, 547 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp, 548 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp, 549 .get_reg = ixgbe_get_regs, 550 .get_eeprom_length = ixgbe_get_eeprom_length, 551 .get_eeprom = ixgbe_get_eeprom, 552 .set_eeprom = ixgbe_set_eeprom, 553 .get_module_info = ixgbe_get_module_info, 554 .get_module_eeprom = ixgbe_get_module_eeprom, 555 .get_dcb_info = ixgbe_dev_get_dcb_info, 556 .timesync_adjust_time = ixgbe_timesync_adjust_time, 557 .timesync_read_time = ixgbe_timesync_read_time, 558 .timesync_write_time = ixgbe_timesync_write_time, 559 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add, 560 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del, 561 .tm_ops_get = ixgbe_tm_ops_get, 562 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup, 563 .get_monitor_addr = ixgbe_get_monitor_addr, 564 }; 565 566 /* 567 * dev_ops for virtual function, bare necessities for basic vf 568 * operation have been implemented 569 */ 570 static const struct eth_dev_ops ixgbevf_eth_dev_ops = { 571 .dev_configure = ixgbevf_dev_configure, 572 .dev_start = ixgbevf_dev_start, 573 .dev_stop = ixgbevf_dev_stop, 574 .link_update = ixgbevf_dev_link_update, 575 .stats_get = ixgbevf_dev_stats_get, 576 .xstats_get = ixgbevf_dev_xstats_get, 577 .stats_reset = ixgbevf_dev_stats_reset, 578 .xstats_reset = ixgbevf_dev_stats_reset, 579 .xstats_get_names = ixgbevf_dev_xstats_get_names, 580 .dev_close = ixgbevf_dev_close, 581 .dev_reset = ixgbevf_dev_reset, 582 .promiscuous_enable = ixgbevf_dev_promiscuous_enable, 583 .promiscuous_disable = ixgbevf_dev_promiscuous_disable, 584 .allmulticast_enable = ixgbevf_dev_allmulticast_enable, 585 .allmulticast_disable = ixgbevf_dev_allmulticast_disable, 586 .dev_infos_get = ixgbevf_dev_info_get, 587 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 588 .mtu_set = ixgbevf_dev_set_mtu, 589 .vlan_filter_set = ixgbevf_vlan_filter_set, 590 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set, 591 .vlan_offload_set = ixgbevf_vlan_offload_set, 592 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 593 .rx_queue_release = ixgbe_dev_rx_queue_release, 594 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 595 .tx_queue_release = ixgbe_dev_tx_queue_release, 596 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable, 597 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable, 598 .mac_addr_add = ixgbevf_add_mac_addr, 599 .mac_addr_remove = ixgbevf_remove_mac_addr, 600 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 601 .rxq_info_get = ixgbe_rxq_info_get, 602 .txq_info_get = ixgbe_txq_info_get, 603 .mac_addr_set = ixgbevf_set_default_mac_addr, 604 .get_reg = ixgbevf_get_regs, 605 .reta_update = ixgbe_dev_rss_reta_update, 606 .reta_query = ixgbe_dev_rss_reta_query, 607 .rss_hash_update = ixgbe_dev_rss_hash_update, 608 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 609 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup, 610 }; 611 612 /* store statistics names and its offset in stats structure */ 613 struct rte_ixgbe_xstats_name_off { 614 char name[RTE_ETH_XSTATS_NAME_SIZE]; 615 unsigned offset; 616 }; 617 618 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = { 619 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)}, 620 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)}, 621 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)}, 622 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)}, 623 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)}, 624 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)}, 625 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)}, 626 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)}, 627 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)}, 628 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)}, 629 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)}, 630 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)}, 631 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)}, 632 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)}, 633 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 634 prc1023)}, 635 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 636 prc1522)}, 637 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)}, 638 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)}, 639 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)}, 640 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)}, 641 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)}, 642 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)}, 643 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)}, 644 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)}, 645 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)}, 646 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)}, 647 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)}, 648 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)}, 649 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)}, 650 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)}, 651 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)}, 652 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)}, 653 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 654 ptc1023)}, 655 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 656 ptc1522)}, 657 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)}, 658 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)}, 659 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)}, 660 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)}, 661 662 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats, 663 fdirustat_add)}, 664 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats, 665 fdirustat_remove)}, 666 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats, 667 fdirfstat_fadd)}, 668 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats, 669 fdirfstat_fremove)}, 670 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats, 671 fdirmatch)}, 672 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats, 673 fdirmiss)}, 674 675 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)}, 676 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)}, 677 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, 678 fclast)}, 679 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)}, 680 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)}, 681 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)}, 682 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)}, 683 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats, 684 fcoe_noddp)}, 685 {"rx_fcoe_no_direct_data_placement_ext_buff", 686 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)}, 687 688 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 689 lxontxc)}, 690 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 691 lxonrxc)}, 692 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 693 lxofftxc)}, 694 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 695 lxoffrxc)}, 696 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)}, 697 }; 698 699 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \ 700 sizeof(rte_ixgbe_stats_strings[0])) 701 702 /* MACsec statistics */ 703 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = { 704 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 705 out_pkts_untagged)}, 706 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats, 707 out_pkts_encrypted)}, 708 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats, 709 out_pkts_protected)}, 710 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats, 711 out_octets_encrypted)}, 712 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats, 713 out_octets_protected)}, 714 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 715 in_pkts_untagged)}, 716 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats, 717 in_pkts_badtag)}, 718 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats, 719 in_pkts_nosci)}, 720 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats, 721 in_pkts_unknownsci)}, 722 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats, 723 in_octets_decrypted)}, 724 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats, 725 in_octets_validated)}, 726 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats, 727 in_pkts_unchecked)}, 728 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats, 729 in_pkts_delayed)}, 730 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats, 731 in_pkts_late)}, 732 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats, 733 in_pkts_ok)}, 734 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats, 735 in_pkts_invalid)}, 736 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats, 737 in_pkts_notvalid)}, 738 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats, 739 in_pkts_unusedsa)}, 740 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats, 741 in_pkts_notusingsa)}, 742 }; 743 744 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \ 745 sizeof(rte_ixgbe_macsec_strings[0])) 746 747 /* Per-queue statistics */ 748 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = { 749 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)}, 750 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)}, 751 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)}, 752 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)}, 753 }; 754 755 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \ 756 sizeof(rte_ixgbe_rxq_strings[0])) 757 #define IXGBE_NB_RXQ_PRIO_VALUES 8 758 759 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = { 760 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)}, 761 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)}, 762 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats, 763 pxon2offc)}, 764 }; 765 766 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \ 767 sizeof(rte_ixgbe_txq_strings[0])) 768 #define IXGBE_NB_TXQ_PRIO_VALUES 8 769 770 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = { 771 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)}, 772 }; 773 774 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \ 775 sizeof(rte_ixgbevf_stats_strings[0])) 776 777 /* 778 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h. 779 */ 780 static inline int 781 ixgbe_is_sfp(struct ixgbe_hw *hw) 782 { 783 switch (hw->phy.type) { 784 case ixgbe_phy_sfp_avago: 785 case ixgbe_phy_sfp_ftl: 786 case ixgbe_phy_sfp_intel: 787 case ixgbe_phy_sfp_unknown: 788 case ixgbe_phy_sfp_passive_tyco: 789 case ixgbe_phy_sfp_passive_unknown: 790 return 1; 791 default: 792 return 0; 793 } 794 } 795 796 static inline int32_t 797 ixgbe_pf_reset_hw(struct ixgbe_hw *hw) 798 { 799 uint32_t ctrl_ext; 800 int32_t status; 801 802 status = ixgbe_reset_hw(hw); 803 804 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 805 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 806 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 807 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 808 IXGBE_WRITE_FLUSH(hw); 809 810 if (status == IXGBE_ERR_SFP_NOT_PRESENT) 811 status = IXGBE_SUCCESS; 812 return status; 813 } 814 815 static inline void 816 ixgbe_enable_intr(struct rte_eth_dev *dev) 817 { 818 struct ixgbe_interrupt *intr = 819 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 820 struct ixgbe_hw *hw = 821 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 822 823 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask); 824 IXGBE_WRITE_FLUSH(hw); 825 } 826 827 /* 828 * This function is based on ixgbe_disable_intr() in base/ixgbe.h. 829 */ 830 static void 831 ixgbe_disable_intr(struct ixgbe_hw *hw) 832 { 833 PMD_INIT_FUNC_TRACE(); 834 835 if (hw->mac.type == ixgbe_mac_82598EB) { 836 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0); 837 } else { 838 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000); 839 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0); 840 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0); 841 } 842 IXGBE_WRITE_FLUSH(hw); 843 } 844 845 /* 846 * This function resets queue statistics mapping registers. 847 * From Niantic datasheet, Initialization of Statistics section: 848 * "...if software requires the queue counters, the RQSMR and TQSM registers 849 * must be re-programmed following a device reset. 850 */ 851 static void 852 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw) 853 { 854 uint32_t i; 855 856 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) { 857 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0); 858 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0); 859 } 860 } 861 862 863 static int 864 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 865 uint16_t queue_id, 866 uint8_t stat_idx, 867 uint8_t is_rx) 868 { 869 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8 870 #define NB_QMAP_FIELDS_PER_QSM_REG 4 871 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f 872 873 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 874 struct ixgbe_stat_mapping_registers *stat_mappings = 875 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private); 876 uint32_t qsmr_mask = 0; 877 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK; 878 uint32_t q_map; 879 uint8_t n, offset; 880 881 if ((hw->mac.type != ixgbe_mac_82599EB) && 882 (hw->mac.type != ixgbe_mac_X540) && 883 (hw->mac.type != ixgbe_mac_X550) && 884 (hw->mac.type != ixgbe_mac_X550EM_x) && 885 (hw->mac.type != ixgbe_mac_X550EM_a)) 886 return -ENOSYS; 887 888 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d", 889 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 890 queue_id, stat_idx); 891 892 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG); 893 if (n >= IXGBE_NB_STAT_MAPPING_REGS) { 894 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded"); 895 return -EIO; 896 } 897 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG); 898 899 /* Now clear any previous stat_idx set */ 900 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 901 if (!is_rx) 902 stat_mappings->tqsm[n] &= ~clearing_mask; 903 else 904 stat_mappings->rqsmr[n] &= ~clearing_mask; 905 906 q_map = (uint32_t)stat_idx; 907 q_map &= QMAP_FIELD_RESERVED_BITS_MASK; 908 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 909 if (!is_rx) 910 stat_mappings->tqsm[n] |= qsmr_mask; 911 else 912 stat_mappings->rqsmr[n] |= qsmr_mask; 913 914 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d", 915 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 916 queue_id, stat_idx); 917 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n, 918 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]); 919 920 /* Now write the mapping in the appropriate register */ 921 if (is_rx) { 922 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d", 923 stat_mappings->rqsmr[n], n); 924 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]); 925 } else { 926 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d", 927 stat_mappings->tqsm[n], n); 928 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]); 929 } 930 return 0; 931 } 932 933 static void 934 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev) 935 { 936 struct ixgbe_stat_mapping_registers *stat_mappings = 937 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private); 938 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 939 int i; 940 941 /* write whatever was in stat mapping table to the NIC */ 942 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) { 943 /* rx */ 944 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]); 945 946 /* tx */ 947 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]); 948 } 949 } 950 951 static void 952 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config) 953 { 954 uint8_t i; 955 struct ixgbe_dcb_tc_config *tc; 956 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS; 957 958 dcb_config->num_tcs.pg_tcs = dcb_max_tc; 959 dcb_config->num_tcs.pfc_tcs = dcb_max_tc; 960 for (i = 0; i < dcb_max_tc; i++) { 961 tc = &dcb_config->tc_config[i]; 962 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i; 963 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 964 (uint8_t)(100/dcb_max_tc + (i & 1)); 965 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i; 966 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 967 (uint8_t)(100/dcb_max_tc + (i & 1)); 968 tc->pfc = ixgbe_dcb_pfc_disabled; 969 } 970 971 /* Initialize default user to priority mapping, UPx->TC0 */ 972 tc = &dcb_config->tc_config[0]; 973 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 974 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 975 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) { 976 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100; 977 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100; 978 } 979 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal; 980 dcb_config->pfc_mode_enable = false; 981 dcb_config->vt_mode = true; 982 dcb_config->round_robin_enable = false; 983 /* support all DCB capabilities in 82599 */ 984 dcb_config->support.capabilities = 0xFF; 985 986 /*we only support 4 Tcs for X540, X550 */ 987 if (hw->mac.type == ixgbe_mac_X540 || 988 hw->mac.type == ixgbe_mac_X550 || 989 hw->mac.type == ixgbe_mac_X550EM_x || 990 hw->mac.type == ixgbe_mac_X550EM_a) { 991 dcb_config->num_tcs.pg_tcs = 4; 992 dcb_config->num_tcs.pfc_tcs = 4; 993 } 994 } 995 996 /* 997 * Ensure that all locks are released before first NVM or PHY access 998 */ 999 static void 1000 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw) 1001 { 1002 uint16_t mask; 1003 1004 /* 1005 * Phy lock should not fail in this early stage. If this is the case, 1006 * it is due to an improper exit of the application. 1007 * So force the release of the faulty lock. Release of common lock 1008 * is done automatically by swfw_sync function. 1009 */ 1010 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func; 1011 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1012 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func); 1013 } 1014 ixgbe_release_swfw_semaphore(hw, mask); 1015 1016 /* 1017 * These ones are more tricky since they are common to all ports; but 1018 * swfw_sync retries last long enough (1s) to be almost sure that if 1019 * lock can not be taken it is due to an improper lock of the 1020 * semaphore. 1021 */ 1022 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM; 1023 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1024 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 1025 } 1026 ixgbe_release_swfw_semaphore(hw, mask); 1027 } 1028 1029 /* 1030 * This function is based on code in ixgbe_attach() in base/ixgbe.c. 1031 * It returns 0 on success. 1032 */ 1033 static int 1034 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) 1035 { 1036 struct ixgbe_adapter *ad = eth_dev->data->dev_private; 1037 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1038 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1039 struct ixgbe_hw *hw = 1040 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1041 struct ixgbe_vfta *shadow_vfta = 1042 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1043 struct ixgbe_hwstrip *hwstrip = 1044 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1045 struct ixgbe_dcb_config *dcb_config = 1046 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private); 1047 struct ixgbe_filter_info *filter_info = 1048 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1049 struct ixgbe_bw_conf *bw_conf = 1050 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private); 1051 uint32_t ctrl_ext; 1052 uint16_t csum; 1053 int diag, i, ret; 1054 1055 PMD_INIT_FUNC_TRACE(); 1056 1057 ixgbe_dev_macsec_setting_reset(eth_dev); 1058 1059 eth_dev->dev_ops = &ixgbe_eth_dev_ops; 1060 eth_dev->rx_queue_count = ixgbe_dev_rx_queue_count; 1061 eth_dev->rx_descriptor_done = ixgbe_dev_rx_descriptor_done; 1062 eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status; 1063 eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status; 1064 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1065 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1066 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts; 1067 1068 /* 1069 * For secondary processes, we don't initialise any further as primary 1070 * has already done this work. Only check we don't need a different 1071 * RX and TX function. 1072 */ 1073 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1074 struct ixgbe_tx_queue *txq; 1075 /* TX queue function in primary, set by last queue initialized 1076 * Tx queue may not initialized by primary process 1077 */ 1078 if (eth_dev->data->tx_queues) { 1079 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1]; 1080 ixgbe_set_tx_function(eth_dev, txq); 1081 } else { 1082 /* Use default TX function if we get here */ 1083 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. " 1084 "Using default TX function."); 1085 } 1086 1087 ixgbe_set_rx_function(eth_dev); 1088 1089 return 0; 1090 } 1091 1092 rte_atomic32_clear(&ad->link_thread_running); 1093 rte_eth_copy_pci_info(eth_dev, pci_dev); 1094 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1095 1096 /* Vendor and Device ID need to be set before init of shared code */ 1097 hw->device_id = pci_dev->id.device_id; 1098 hw->vendor_id = pci_dev->id.vendor_id; 1099 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1100 hw->allow_unsupported_sfp = 1; 1101 1102 /* Initialize the shared code (base driver) */ 1103 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1104 diag = ixgbe_bypass_init_shared_code(hw); 1105 #else 1106 diag = ixgbe_init_shared_code(hw); 1107 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1108 1109 if (diag != IXGBE_SUCCESS) { 1110 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag); 1111 return -EIO; 1112 } 1113 1114 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 1115 PMD_INIT_LOG(ERR, "\nERROR: " 1116 "Firmware recovery mode detected. Limiting functionality.\n" 1117 "Refer to the Intel(R) Ethernet Adapters and Devices " 1118 "User Guide for details on firmware recovery mode."); 1119 return -EIO; 1120 } 1121 1122 /* pick up the PCI bus settings for reporting later */ 1123 ixgbe_get_bus_info(hw); 1124 1125 /* Unlock any pending hardware semaphore */ 1126 ixgbe_swfw_lock_reset(hw); 1127 1128 #ifdef RTE_LIB_SECURITY 1129 /* Initialize security_ctx only for primary process*/ 1130 if (ixgbe_ipsec_ctx_create(eth_dev)) 1131 return -ENOMEM; 1132 #endif 1133 1134 /* Initialize DCB configuration*/ 1135 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config)); 1136 ixgbe_dcb_init(hw, dcb_config); 1137 /* Get Hardware Flow Control setting */ 1138 hw->fc.requested_mode = ixgbe_fc_none; 1139 hw->fc.current_mode = ixgbe_fc_none; 1140 hw->fc.pause_time = IXGBE_FC_PAUSE; 1141 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 1142 hw->fc.low_water[i] = IXGBE_FC_LO; 1143 hw->fc.high_water[i] = IXGBE_FC_HI; 1144 } 1145 hw->fc.send_xon = 1; 1146 1147 /* Make sure we have a good EEPROM before we read from it */ 1148 diag = ixgbe_validate_eeprom_checksum(hw, &csum); 1149 if (diag != IXGBE_SUCCESS) { 1150 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag); 1151 return -EIO; 1152 } 1153 1154 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1155 diag = ixgbe_bypass_init_hw(hw); 1156 #else 1157 diag = ixgbe_init_hw(hw); 1158 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1159 1160 /* 1161 * Devices with copper phys will fail to initialise if ixgbe_init_hw() 1162 * is called too soon after the kernel driver unbinding/binding occurs. 1163 * The failure occurs in ixgbe_identify_phy_generic() for all devices, 1164 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is 1165 * also called. See ixgbe_identify_phy_82599(). The reason for the 1166 * failure is not known, and only occuts when virtualisation features 1167 * are disabled in the bios. A delay of 100ms was found to be enough by 1168 * trial-and-error, and is doubled to be safe. 1169 */ 1170 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) { 1171 rte_delay_ms(200); 1172 diag = ixgbe_init_hw(hw); 1173 } 1174 1175 if (diag == IXGBE_ERR_SFP_NOT_PRESENT) 1176 diag = IXGBE_SUCCESS; 1177 1178 if (diag == IXGBE_ERR_EEPROM_VERSION) { 1179 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/" 1180 "LOM. Please be aware there may be issues associated " 1181 "with your hardware."); 1182 PMD_INIT_LOG(ERR, "If you are experiencing problems " 1183 "please contact your Intel or hardware representative " 1184 "who provided you with this hardware."); 1185 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED) 1186 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module"); 1187 if (diag) { 1188 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag); 1189 return -EIO; 1190 } 1191 1192 /* Reset the hw statistics */ 1193 ixgbe_dev_stats_reset(eth_dev); 1194 1195 /* disable interrupt */ 1196 ixgbe_disable_intr(hw); 1197 1198 /* reset mappings for queue statistics hw counters*/ 1199 ixgbe_reset_qstat_mappings(hw); 1200 1201 /* Allocate memory for storing MAC addresses */ 1202 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN * 1203 hw->mac.num_rar_entries, 0); 1204 if (eth_dev->data->mac_addrs == NULL) { 1205 PMD_INIT_LOG(ERR, 1206 "Failed to allocate %u bytes needed to store " 1207 "MAC addresses", 1208 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1209 return -ENOMEM; 1210 } 1211 /* Copy the permanent MAC address */ 1212 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr, 1213 ð_dev->data->mac_addrs[0]); 1214 1215 /* Allocate memory for storing hash filter MAC addresses */ 1216 eth_dev->data->hash_mac_addrs = rte_zmalloc( 1217 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0); 1218 if (eth_dev->data->hash_mac_addrs == NULL) { 1219 PMD_INIT_LOG(ERR, 1220 "Failed to allocate %d bytes needed to store MAC addresses", 1221 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC); 1222 return -ENOMEM; 1223 } 1224 1225 /* initialize the vfta */ 1226 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1227 1228 /* initialize the hw strip bitmap*/ 1229 memset(hwstrip, 0, sizeof(*hwstrip)); 1230 1231 /* initialize PF if max_vfs not zero */ 1232 ret = ixgbe_pf_host_init(eth_dev); 1233 if (ret) { 1234 rte_free(eth_dev->data->mac_addrs); 1235 eth_dev->data->mac_addrs = NULL; 1236 rte_free(eth_dev->data->hash_mac_addrs); 1237 eth_dev->data->hash_mac_addrs = NULL; 1238 return ret; 1239 } 1240 1241 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 1242 /* let hardware know driver is loaded */ 1243 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD; 1244 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 1245 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 1246 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 1247 IXGBE_WRITE_FLUSH(hw); 1248 1249 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 1250 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d", 1251 (int) hw->mac.type, (int) hw->phy.type, 1252 (int) hw->phy.sfp_type); 1253 else 1254 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d", 1255 (int) hw->mac.type, (int) hw->phy.type); 1256 1257 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 1258 eth_dev->data->port_id, pci_dev->id.vendor_id, 1259 pci_dev->id.device_id); 1260 1261 rte_intr_callback_register(intr_handle, 1262 ixgbe_dev_interrupt_handler, eth_dev); 1263 1264 /* enable uio/vfio intr/eventfd mapping */ 1265 rte_intr_enable(intr_handle); 1266 1267 /* enable support intr */ 1268 ixgbe_enable_intr(eth_dev); 1269 1270 /* initialize filter info */ 1271 memset(filter_info, 0, 1272 sizeof(struct ixgbe_filter_info)); 1273 1274 /* initialize 5tuple filter list */ 1275 TAILQ_INIT(&filter_info->fivetuple_list); 1276 1277 /* initialize flow director filter list & hash */ 1278 ixgbe_fdir_filter_init(eth_dev); 1279 1280 /* initialize l2 tunnel filter list & hash */ 1281 ixgbe_l2_tn_filter_init(eth_dev); 1282 1283 /* initialize flow filter lists */ 1284 ixgbe_filterlist_init(); 1285 1286 /* initialize bandwidth configuration info */ 1287 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf)); 1288 1289 /* initialize Traffic Manager configuration */ 1290 ixgbe_tm_conf_init(eth_dev); 1291 1292 return 0; 1293 } 1294 1295 static int 1296 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1297 { 1298 PMD_INIT_FUNC_TRACE(); 1299 1300 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1301 return 0; 1302 1303 ixgbe_dev_close(eth_dev); 1304 1305 return 0; 1306 } 1307 1308 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev) 1309 { 1310 struct ixgbe_filter_info *filter_info = 1311 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1312 struct ixgbe_5tuple_filter *p_5tuple; 1313 1314 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) { 1315 TAILQ_REMOVE(&filter_info->fivetuple_list, 1316 p_5tuple, 1317 entries); 1318 rte_free(p_5tuple); 1319 } 1320 memset(filter_info->fivetuple_mask, 0, 1321 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE); 1322 1323 return 0; 1324 } 1325 1326 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev) 1327 { 1328 struct ixgbe_hw_fdir_info *fdir_info = 1329 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1330 struct ixgbe_fdir_filter *fdir_filter; 1331 1332 if (fdir_info->hash_map) 1333 rte_free(fdir_info->hash_map); 1334 if (fdir_info->hash_handle) 1335 rte_hash_free(fdir_info->hash_handle); 1336 1337 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 1338 TAILQ_REMOVE(&fdir_info->fdir_list, 1339 fdir_filter, 1340 entries); 1341 rte_free(fdir_filter); 1342 } 1343 1344 return 0; 1345 } 1346 1347 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev) 1348 { 1349 struct ixgbe_l2_tn_info *l2_tn_info = 1350 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1351 struct ixgbe_l2_tn_filter *l2_tn_filter; 1352 1353 if (l2_tn_info->hash_map) 1354 rte_free(l2_tn_info->hash_map); 1355 if (l2_tn_info->hash_handle) 1356 rte_hash_free(l2_tn_info->hash_handle); 1357 1358 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 1359 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, 1360 l2_tn_filter, 1361 entries); 1362 rte_free(l2_tn_filter); 1363 } 1364 1365 return 0; 1366 } 1367 1368 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev) 1369 { 1370 struct ixgbe_hw_fdir_info *fdir_info = 1371 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1372 char fdir_hash_name[RTE_HASH_NAMESIZE]; 1373 struct rte_hash_parameters fdir_hash_params = { 1374 .name = fdir_hash_name, 1375 .entries = IXGBE_MAX_FDIR_FILTER_NUM, 1376 .key_len = sizeof(union ixgbe_atr_input), 1377 .hash_func = rte_hash_crc, 1378 .hash_func_init_val = 0, 1379 .socket_id = rte_socket_id(), 1380 }; 1381 1382 TAILQ_INIT(&fdir_info->fdir_list); 1383 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 1384 "fdir_%s", eth_dev->device->name); 1385 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params); 1386 if (!fdir_info->hash_handle) { 1387 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 1388 return -EINVAL; 1389 } 1390 fdir_info->hash_map = rte_zmalloc("ixgbe", 1391 sizeof(struct ixgbe_fdir_filter *) * 1392 IXGBE_MAX_FDIR_FILTER_NUM, 1393 0); 1394 if (!fdir_info->hash_map) { 1395 PMD_INIT_LOG(ERR, 1396 "Failed to allocate memory for fdir hash map!"); 1397 return -ENOMEM; 1398 } 1399 fdir_info->mask_added = FALSE; 1400 1401 return 0; 1402 } 1403 1404 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) 1405 { 1406 struct ixgbe_l2_tn_info *l2_tn_info = 1407 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1408 char l2_tn_hash_name[RTE_HASH_NAMESIZE]; 1409 struct rte_hash_parameters l2_tn_hash_params = { 1410 .name = l2_tn_hash_name, 1411 .entries = IXGBE_MAX_L2_TN_FILTER_NUM, 1412 .key_len = sizeof(struct ixgbe_l2_tn_key), 1413 .hash_func = rte_hash_crc, 1414 .hash_func_init_val = 0, 1415 .socket_id = rte_socket_id(), 1416 }; 1417 1418 TAILQ_INIT(&l2_tn_info->l2_tn_list); 1419 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE, 1420 "l2_tn_%s", eth_dev->device->name); 1421 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params); 1422 if (!l2_tn_info->hash_handle) { 1423 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!"); 1424 return -EINVAL; 1425 } 1426 l2_tn_info->hash_map = rte_zmalloc("ixgbe", 1427 sizeof(struct ixgbe_l2_tn_filter *) * 1428 IXGBE_MAX_L2_TN_FILTER_NUM, 1429 0); 1430 if (!l2_tn_info->hash_map) { 1431 PMD_INIT_LOG(ERR, 1432 "Failed to allocate memory for L2 TN hash map!"); 1433 return -ENOMEM; 1434 } 1435 l2_tn_info->e_tag_en = FALSE; 1436 l2_tn_info->e_tag_fwd_en = FALSE; 1437 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG; 1438 1439 return 0; 1440 } 1441 /* 1442 * Negotiate mailbox API version with the PF. 1443 * After reset API version is always set to the basic one (ixgbe_mbox_api_10). 1444 * Then we try to negotiate starting with the most recent one. 1445 * If all negotiation attempts fail, then we will proceed with 1446 * the default one (ixgbe_mbox_api_10). 1447 */ 1448 static void 1449 ixgbevf_negotiate_api(struct ixgbe_hw *hw) 1450 { 1451 int32_t i; 1452 1453 /* start with highest supported, proceed down */ 1454 static const enum ixgbe_pfvf_api_rev sup_ver[] = { 1455 ixgbe_mbox_api_13, 1456 ixgbe_mbox_api_12, 1457 ixgbe_mbox_api_11, 1458 ixgbe_mbox_api_10, 1459 }; 1460 1461 for (i = 0; 1462 i != RTE_DIM(sup_ver) && 1463 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0; 1464 i++) 1465 ; 1466 } 1467 1468 static void 1469 generate_random_mac_addr(struct rte_ether_addr *mac_addr) 1470 { 1471 uint64_t random; 1472 1473 /* Set Organizationally Unique Identifier (OUI) prefix. */ 1474 mac_addr->addr_bytes[0] = 0x00; 1475 mac_addr->addr_bytes[1] = 0x09; 1476 mac_addr->addr_bytes[2] = 0xC0; 1477 /* Force indication of locally assigned MAC address. */ 1478 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR; 1479 /* Generate the last 3 bytes of the MAC address with a random number. */ 1480 random = rte_rand(); 1481 memcpy(&mac_addr->addr_bytes[3], &random, 3); 1482 } 1483 1484 static int 1485 devarg_handle_int(__rte_unused const char *key, const char *value, 1486 void *extra_args) 1487 { 1488 uint16_t *n = extra_args; 1489 1490 if (value == NULL || extra_args == NULL) 1491 return -EINVAL; 1492 1493 *n = (uint16_t)strtoul(value, NULL, 0); 1494 if (*n == USHRT_MAX && errno == ERANGE) 1495 return -1; 1496 1497 return 0; 1498 } 1499 1500 static void 1501 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter, 1502 struct rte_devargs *devargs) 1503 { 1504 struct rte_kvargs *kvlist; 1505 uint16_t pflink_fullchk; 1506 1507 if (devargs == NULL) 1508 return; 1509 1510 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments); 1511 if (kvlist == NULL) 1512 return; 1513 1514 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 && 1515 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK, 1516 devarg_handle_int, &pflink_fullchk) == 0 && 1517 pflink_fullchk == 1) 1518 adapter->pflink_fullchk = 1; 1519 1520 rte_kvargs_free(kvlist); 1521 } 1522 1523 /* 1524 * Virtual Function device init 1525 */ 1526 static int 1527 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev) 1528 { 1529 int diag; 1530 uint32_t tc, tcs; 1531 struct ixgbe_adapter *ad = eth_dev->data->dev_private; 1532 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1533 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1534 struct ixgbe_hw *hw = 1535 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1536 struct ixgbe_vfta *shadow_vfta = 1537 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1538 struct ixgbe_hwstrip *hwstrip = 1539 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1540 struct rte_ether_addr *perm_addr = 1541 (struct rte_ether_addr *)hw->mac.perm_addr; 1542 1543 PMD_INIT_FUNC_TRACE(); 1544 1545 eth_dev->dev_ops = &ixgbevf_eth_dev_ops; 1546 eth_dev->rx_descriptor_done = ixgbe_dev_rx_descriptor_done; 1547 eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status; 1548 eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status; 1549 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1550 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1551 1552 /* for secondary processes, we don't initialise any further as primary 1553 * has already done this work. Only check we don't need a different 1554 * RX function 1555 */ 1556 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1557 struct ixgbe_tx_queue *txq; 1558 /* TX queue function in primary, set by last queue initialized 1559 * Tx queue may not initialized by primary process 1560 */ 1561 if (eth_dev->data->tx_queues) { 1562 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1]; 1563 ixgbe_set_tx_function(eth_dev, txq); 1564 } else { 1565 /* Use default TX function if we get here */ 1566 PMD_INIT_LOG(NOTICE, 1567 "No TX queues configured yet. Using default TX function."); 1568 } 1569 1570 ixgbe_set_rx_function(eth_dev); 1571 1572 return 0; 1573 } 1574 1575 rte_atomic32_clear(&ad->link_thread_running); 1576 ixgbevf_parse_devargs(eth_dev->data->dev_private, 1577 pci_dev->device.devargs); 1578 1579 rte_eth_copy_pci_info(eth_dev, pci_dev); 1580 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1581 1582 hw->device_id = pci_dev->id.device_id; 1583 hw->vendor_id = pci_dev->id.vendor_id; 1584 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1585 1586 /* initialize the vfta */ 1587 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1588 1589 /* initialize the hw strip bitmap*/ 1590 memset(hwstrip, 0, sizeof(*hwstrip)); 1591 1592 /* Initialize the shared code (base driver) */ 1593 diag = ixgbe_init_shared_code(hw); 1594 if (diag != IXGBE_SUCCESS) { 1595 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag); 1596 return -EIO; 1597 } 1598 1599 /* init_mailbox_params */ 1600 hw->mbx.ops.init_params(hw); 1601 1602 /* Reset the hw statistics */ 1603 ixgbevf_dev_stats_reset(eth_dev); 1604 1605 /* Disable the interrupts for VF */ 1606 ixgbevf_intr_disable(eth_dev); 1607 1608 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */ 1609 diag = hw->mac.ops.reset_hw(hw); 1610 1611 /* 1612 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when 1613 * the underlying PF driver has not assigned a MAC address to the VF. 1614 * In this case, assign a random MAC address. 1615 */ 1616 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) { 1617 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1618 /* 1619 * This error code will be propagated to the app by 1620 * rte_eth_dev_reset, so use a public error code rather than 1621 * the internal-only IXGBE_ERR_RESET_FAILED 1622 */ 1623 return -EAGAIN; 1624 } 1625 1626 /* negotiate mailbox API version to use with the PF. */ 1627 ixgbevf_negotiate_api(hw); 1628 1629 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */ 1630 ixgbevf_get_queues(hw, &tcs, &tc); 1631 1632 /* Allocate memory for storing MAC addresses */ 1633 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN * 1634 hw->mac.num_rar_entries, 0); 1635 if (eth_dev->data->mac_addrs == NULL) { 1636 PMD_INIT_LOG(ERR, 1637 "Failed to allocate %u bytes needed to store " 1638 "MAC addresses", 1639 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1640 return -ENOMEM; 1641 } 1642 1643 /* Generate a random MAC address, if none was assigned by PF. */ 1644 if (rte_is_zero_ether_addr(perm_addr)) { 1645 generate_random_mac_addr(perm_addr); 1646 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1); 1647 if (diag) { 1648 rte_free(eth_dev->data->mac_addrs); 1649 eth_dev->data->mac_addrs = NULL; 1650 return diag; 1651 } 1652 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF"); 1653 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address " 1654 "%02x:%02x:%02x:%02x:%02x:%02x", 1655 perm_addr->addr_bytes[0], 1656 perm_addr->addr_bytes[1], 1657 perm_addr->addr_bytes[2], 1658 perm_addr->addr_bytes[3], 1659 perm_addr->addr_bytes[4], 1660 perm_addr->addr_bytes[5]); 1661 } 1662 1663 /* Copy the permanent MAC address */ 1664 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]); 1665 1666 /* reset the hardware with the new settings */ 1667 diag = hw->mac.ops.start_hw(hw); 1668 switch (diag) { 1669 case 0: 1670 break; 1671 1672 default: 1673 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1674 return -EIO; 1675 } 1676 1677 rte_intr_callback_register(intr_handle, 1678 ixgbevf_dev_interrupt_handler, eth_dev); 1679 rte_intr_enable(intr_handle); 1680 ixgbevf_intr_enable(eth_dev); 1681 1682 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s", 1683 eth_dev->data->port_id, pci_dev->id.vendor_id, 1684 pci_dev->id.device_id, "ixgbe_mac_82599_vf"); 1685 1686 return 0; 1687 } 1688 1689 /* Virtual Function device uninit */ 1690 1691 static int 1692 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev) 1693 { 1694 PMD_INIT_FUNC_TRACE(); 1695 1696 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1697 return 0; 1698 1699 ixgbevf_dev_close(eth_dev); 1700 1701 return 0; 1702 } 1703 1704 static int 1705 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1706 struct rte_pci_device *pci_dev) 1707 { 1708 char name[RTE_ETH_NAME_MAX_LEN]; 1709 struct rte_eth_dev *pf_ethdev; 1710 struct rte_eth_devargs eth_da; 1711 int i, retval; 1712 1713 if (pci_dev->device.devargs) { 1714 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 1715 ð_da); 1716 if (retval) 1717 return retval; 1718 } else 1719 memset(ð_da, 0, sizeof(eth_da)); 1720 1721 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 1722 sizeof(struct ixgbe_adapter), 1723 eth_dev_pci_specific_init, pci_dev, 1724 eth_ixgbe_dev_init, NULL); 1725 1726 if (retval || eth_da.nb_representor_ports < 1) 1727 return retval; 1728 1729 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1730 if (pf_ethdev == NULL) 1731 return -ENODEV; 1732 1733 /* probe VF representor ports */ 1734 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1735 struct ixgbe_vf_info *vfinfo; 1736 struct ixgbe_vf_representor representor; 1737 1738 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA( 1739 pf_ethdev->data->dev_private); 1740 if (vfinfo == NULL) { 1741 PMD_DRV_LOG(ERR, 1742 "no virtual functions supported by PF"); 1743 break; 1744 } 1745 1746 representor.vf_id = eth_da.representor_ports[i]; 1747 representor.switch_domain_id = vfinfo->switch_domain_id; 1748 representor.pf_ethdev = pf_ethdev; 1749 1750 /* representor port net_bdf_port */ 1751 snprintf(name, sizeof(name), "net_%s_representor_%d", 1752 pci_dev->device.name, 1753 eth_da.representor_ports[i]); 1754 1755 retval = rte_eth_dev_create(&pci_dev->device, name, 1756 sizeof(struct ixgbe_vf_representor), NULL, NULL, 1757 ixgbe_vf_representor_init, &representor); 1758 1759 if (retval) 1760 PMD_DRV_LOG(ERR, "failed to create ixgbe vf " 1761 "representor %s.", name); 1762 } 1763 1764 return 0; 1765 } 1766 1767 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev) 1768 { 1769 struct rte_eth_dev *ethdev; 1770 1771 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1772 if (!ethdev) 1773 return 0; 1774 1775 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 1776 return rte_eth_dev_pci_generic_remove(pci_dev, 1777 ixgbe_vf_representor_uninit); 1778 else 1779 return rte_eth_dev_pci_generic_remove(pci_dev, 1780 eth_ixgbe_dev_uninit); 1781 } 1782 1783 static struct rte_pci_driver rte_ixgbe_pmd = { 1784 .id_table = pci_id_ixgbe_map, 1785 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1786 .probe = eth_ixgbe_pci_probe, 1787 .remove = eth_ixgbe_pci_remove, 1788 }; 1789 1790 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1791 struct rte_pci_device *pci_dev) 1792 { 1793 return rte_eth_dev_pci_generic_probe(pci_dev, 1794 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init); 1795 } 1796 1797 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev) 1798 { 1799 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit); 1800 } 1801 1802 /* 1803 * virtual function driver struct 1804 */ 1805 static struct rte_pci_driver rte_ixgbevf_pmd = { 1806 .id_table = pci_id_ixgbevf_map, 1807 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1808 .probe = eth_ixgbevf_pci_probe, 1809 .remove = eth_ixgbevf_pci_remove, 1810 }; 1811 1812 static int 1813 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1814 { 1815 struct ixgbe_hw *hw = 1816 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1817 struct ixgbe_vfta *shadow_vfta = 1818 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1819 uint32_t vfta; 1820 uint32_t vid_idx; 1821 uint32_t vid_bit; 1822 1823 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 1824 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 1825 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx)); 1826 if (on) 1827 vfta |= vid_bit; 1828 else 1829 vfta &= ~vid_bit; 1830 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta); 1831 1832 /* update local VFTA copy */ 1833 shadow_vfta->vfta[vid_idx] = vfta; 1834 1835 return 0; 1836 } 1837 1838 static void 1839 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 1840 { 1841 if (on) 1842 ixgbe_vlan_hw_strip_enable(dev, queue); 1843 else 1844 ixgbe_vlan_hw_strip_disable(dev, queue); 1845 } 1846 1847 static int 1848 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1849 enum rte_vlan_type vlan_type, 1850 uint16_t tpid) 1851 { 1852 struct ixgbe_hw *hw = 1853 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1854 int ret = 0; 1855 uint32_t reg; 1856 uint32_t qinq; 1857 1858 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1859 qinq &= IXGBE_DMATXCTL_GDV; 1860 1861 switch (vlan_type) { 1862 case ETH_VLAN_TYPE_INNER: 1863 if (qinq) { 1864 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1865 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1866 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1867 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1868 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1869 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1870 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1871 } else { 1872 ret = -ENOTSUP; 1873 PMD_DRV_LOG(ERR, "Inner type is not supported" 1874 " by single VLAN"); 1875 } 1876 break; 1877 case ETH_VLAN_TYPE_OUTER: 1878 if (qinq) { 1879 /* Only the high 16-bits is valid */ 1880 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid << 1881 IXGBE_EXVET_VET_EXT_SHIFT); 1882 } else { 1883 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1884 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1885 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1886 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1887 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1888 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1889 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1890 } 1891 1892 break; 1893 default: 1894 ret = -EINVAL; 1895 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type); 1896 break; 1897 } 1898 1899 return ret; 1900 } 1901 1902 void 1903 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev) 1904 { 1905 struct ixgbe_hw *hw = 1906 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1907 uint32_t vlnctrl; 1908 1909 PMD_INIT_FUNC_TRACE(); 1910 1911 /* Filter Table Disable */ 1912 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1913 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 1914 1915 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1916 } 1917 1918 void 1919 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1920 { 1921 struct ixgbe_hw *hw = 1922 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1923 struct ixgbe_vfta *shadow_vfta = 1924 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1925 uint32_t vlnctrl; 1926 uint16_t i; 1927 1928 PMD_INIT_FUNC_TRACE(); 1929 1930 /* Filter Table Enable */ 1931 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1932 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; 1933 vlnctrl |= IXGBE_VLNCTRL_VFE; 1934 1935 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1936 1937 /* write whatever is in local vfta copy */ 1938 for (i = 0; i < IXGBE_VFTA_SIZE; i++) 1939 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]); 1940 } 1941 1942 static void 1943 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on) 1944 { 1945 struct ixgbe_hwstrip *hwstrip = 1946 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private); 1947 struct ixgbe_rx_queue *rxq; 1948 1949 if (queue >= IXGBE_MAX_RX_QUEUE_NUM) 1950 return; 1951 1952 if (on) 1953 IXGBE_SET_HWSTRIP(hwstrip, queue); 1954 else 1955 IXGBE_CLEAR_HWSTRIP(hwstrip, queue); 1956 1957 if (queue >= dev->data->nb_rx_queues) 1958 return; 1959 1960 rxq = dev->data->rx_queues[queue]; 1961 1962 if (on) { 1963 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; 1964 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 1965 } else { 1966 rxq->vlan_flags = PKT_RX_VLAN; 1967 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 1968 } 1969 } 1970 1971 static void 1972 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue) 1973 { 1974 struct ixgbe_hw *hw = 1975 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1976 uint32_t ctrl; 1977 1978 PMD_INIT_FUNC_TRACE(); 1979 1980 if (hw->mac.type == ixgbe_mac_82598EB) { 1981 /* No queue level support */ 1982 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 1983 return; 1984 } 1985 1986 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 1987 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 1988 ctrl &= ~IXGBE_RXDCTL_VME; 1989 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 1990 1991 /* record those setting for HW strip per queue */ 1992 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0); 1993 } 1994 1995 static void 1996 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue) 1997 { 1998 struct ixgbe_hw *hw = 1999 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2000 uint32_t ctrl; 2001 2002 PMD_INIT_FUNC_TRACE(); 2003 2004 if (hw->mac.type == ixgbe_mac_82598EB) { 2005 /* No queue level supported */ 2006 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2007 return; 2008 } 2009 2010 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2011 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2012 ctrl |= IXGBE_RXDCTL_VME; 2013 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2014 2015 /* record those setting for HW strip per queue */ 2016 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1); 2017 } 2018 2019 static void 2020 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev) 2021 { 2022 struct ixgbe_hw *hw = 2023 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2024 uint32_t ctrl; 2025 2026 PMD_INIT_FUNC_TRACE(); 2027 2028 /* DMATXCTRL: Geric Double VLAN Disable */ 2029 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2030 ctrl &= ~IXGBE_DMATXCTL_GDV; 2031 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2032 2033 /* CTRL_EXT: Global Double VLAN Disable */ 2034 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2035 ctrl &= ~IXGBE_EXTENDED_VLAN; 2036 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2037 2038 } 2039 2040 static void 2041 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) 2042 { 2043 struct ixgbe_hw *hw = 2044 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2045 uint32_t ctrl; 2046 2047 PMD_INIT_FUNC_TRACE(); 2048 2049 /* DMATXCTRL: Geric Double VLAN Enable */ 2050 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2051 ctrl |= IXGBE_DMATXCTL_GDV; 2052 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2053 2054 /* CTRL_EXT: Global Double VLAN Enable */ 2055 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2056 ctrl |= IXGBE_EXTENDED_VLAN; 2057 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2058 2059 /* Clear pooling mode of PFVTCTL. It's required by X550. */ 2060 if (hw->mac.type == ixgbe_mac_X550 || 2061 hw->mac.type == ixgbe_mac_X550EM_x || 2062 hw->mac.type == ixgbe_mac_X550EM_a) { 2063 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 2064 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 2065 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 2066 } 2067 2068 /* 2069 * VET EXT field in the EXVET register = 0x8100 by default 2070 * So no need to change. Same to VT field of DMATXCTL register 2071 */ 2072 } 2073 2074 void 2075 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev) 2076 { 2077 struct ixgbe_hw *hw = 2078 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2079 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 2080 uint32_t ctrl; 2081 uint16_t i; 2082 struct ixgbe_rx_queue *rxq; 2083 bool on; 2084 2085 PMD_INIT_FUNC_TRACE(); 2086 2087 if (hw->mac.type == ixgbe_mac_82598EB) { 2088 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2089 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2090 ctrl |= IXGBE_VLNCTRL_VME; 2091 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2092 } else { 2093 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2094 ctrl &= ~IXGBE_VLNCTRL_VME; 2095 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2096 } 2097 } else { 2098 /* 2099 * Other 10G NIC, the VLAN strip can be setup 2100 * per queue in RXDCTL 2101 */ 2102 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2103 rxq = dev->data->rx_queues[i]; 2104 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx)); 2105 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2106 ctrl |= IXGBE_RXDCTL_VME; 2107 on = TRUE; 2108 } else { 2109 ctrl &= ~IXGBE_RXDCTL_VME; 2110 on = FALSE; 2111 } 2112 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl); 2113 2114 /* record those setting for HW strip per queue */ 2115 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on); 2116 } 2117 } 2118 } 2119 2120 static void 2121 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask) 2122 { 2123 uint16_t i; 2124 struct rte_eth_rxmode *rxmode; 2125 struct ixgbe_rx_queue *rxq; 2126 2127 if (mask & ETH_VLAN_STRIP_MASK) { 2128 rxmode = &dev->data->dev_conf.rxmode; 2129 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 2130 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2131 rxq = dev->data->rx_queues[i]; 2132 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 2133 } 2134 else 2135 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2136 rxq = dev->data->rx_queues[i]; 2137 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 2138 } 2139 } 2140 } 2141 2142 static int 2143 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask) 2144 { 2145 struct rte_eth_rxmode *rxmode; 2146 rxmode = &dev->data->dev_conf.rxmode; 2147 2148 if (mask & ETH_VLAN_STRIP_MASK) { 2149 ixgbe_vlan_hw_strip_config(dev); 2150 } 2151 2152 if (mask & ETH_VLAN_FILTER_MASK) { 2153 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 2154 ixgbe_vlan_hw_filter_enable(dev); 2155 else 2156 ixgbe_vlan_hw_filter_disable(dev); 2157 } 2158 2159 if (mask & ETH_VLAN_EXTEND_MASK) { 2160 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2161 ixgbe_vlan_hw_extend_enable(dev); 2162 else 2163 ixgbe_vlan_hw_extend_disable(dev); 2164 } 2165 2166 return 0; 2167 } 2168 2169 static int 2170 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2171 { 2172 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 2173 2174 ixgbe_vlan_offload_config(dev, mask); 2175 2176 return 0; 2177 } 2178 2179 static void 2180 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev) 2181 { 2182 struct ixgbe_hw *hw = 2183 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2184 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */ 2185 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2186 2187 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */ 2188 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl); 2189 } 2190 2191 static int 2192 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q) 2193 { 2194 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2195 2196 switch (nb_rx_q) { 2197 case 1: 2198 case 2: 2199 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS; 2200 break; 2201 case 4: 2202 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS; 2203 break; 2204 default: 2205 return -EINVAL; 2206 } 2207 2208 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 2209 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2210 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 2211 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2212 return 0; 2213 } 2214 2215 static int 2216 ixgbe_check_mq_mode(struct rte_eth_dev *dev) 2217 { 2218 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 2219 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2220 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2221 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2222 2223 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 2224 /* check multi-queue mode */ 2225 switch (dev_conf->rxmode.mq_mode) { 2226 case ETH_MQ_RX_VMDQ_DCB: 2227 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV"); 2228 break; 2229 case ETH_MQ_RX_VMDQ_DCB_RSS: 2230 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */ 2231 PMD_INIT_LOG(ERR, "SRIOV active," 2232 " unsupported mq_mode rx %d.", 2233 dev_conf->rxmode.mq_mode); 2234 return -EINVAL; 2235 case ETH_MQ_RX_RSS: 2236 case ETH_MQ_RX_VMDQ_RSS: 2237 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS; 2238 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) 2239 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) { 2240 PMD_INIT_LOG(ERR, "SRIOV is active," 2241 " invalid queue number" 2242 " for VMDQ RSS, allowed" 2243 " value are 1, 2 or 4."); 2244 return -EINVAL; 2245 } 2246 break; 2247 case ETH_MQ_RX_VMDQ_ONLY: 2248 case ETH_MQ_RX_NONE: 2249 /* if nothing mq mode configure, use default scheme */ 2250 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY; 2251 break; 2252 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/ 2253 /* SRIOV only works in VMDq enable mode */ 2254 PMD_INIT_LOG(ERR, "SRIOV is active," 2255 " wrong mq_mode rx %d.", 2256 dev_conf->rxmode.mq_mode); 2257 return -EINVAL; 2258 } 2259 2260 switch (dev_conf->txmode.mq_mode) { 2261 case ETH_MQ_TX_VMDQ_DCB: 2262 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV"); 2263 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB; 2264 break; 2265 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */ 2266 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY; 2267 break; 2268 } 2269 2270 /* check valid queue number */ 2271 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) || 2272 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) { 2273 PMD_INIT_LOG(ERR, "SRIOV is active," 2274 " nb_rx_q=%d nb_tx_q=%d queue number" 2275 " must be less than or equal to %d.", 2276 nb_rx_q, nb_tx_q, 2277 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool); 2278 return -EINVAL; 2279 } 2280 } else { 2281 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) { 2282 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is" 2283 " not supported."); 2284 return -EINVAL; 2285 } 2286 /* check configuration for vmdb+dcb mode */ 2287 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) { 2288 const struct rte_eth_vmdq_dcb_conf *conf; 2289 2290 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2291 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.", 2292 IXGBE_VMDQ_DCB_NB_QUEUES); 2293 return -EINVAL; 2294 } 2295 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf; 2296 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2297 conf->nb_queue_pools == ETH_32_POOLS)) { 2298 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2299 " nb_queue_pools must be %d or %d.", 2300 ETH_16_POOLS, ETH_32_POOLS); 2301 return -EINVAL; 2302 } 2303 } 2304 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) { 2305 const struct rte_eth_vmdq_dcb_tx_conf *conf; 2306 2307 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2308 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d", 2309 IXGBE_VMDQ_DCB_NB_QUEUES); 2310 return -EINVAL; 2311 } 2312 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf; 2313 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2314 conf->nb_queue_pools == ETH_32_POOLS)) { 2315 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2316 " nb_queue_pools != %d and" 2317 " nb_queue_pools != %d.", 2318 ETH_16_POOLS, ETH_32_POOLS); 2319 return -EINVAL; 2320 } 2321 } 2322 2323 /* For DCB mode check our configuration before we go further */ 2324 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) { 2325 const struct rte_eth_dcb_rx_conf *conf; 2326 2327 conf = &dev_conf->rx_adv_conf.dcb_rx_conf; 2328 if (!(conf->nb_tcs == ETH_4_TCS || 2329 conf->nb_tcs == ETH_8_TCS)) { 2330 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2331 " and nb_tcs != %d.", 2332 ETH_4_TCS, ETH_8_TCS); 2333 return -EINVAL; 2334 } 2335 } 2336 2337 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) { 2338 const struct rte_eth_dcb_tx_conf *conf; 2339 2340 conf = &dev_conf->tx_adv_conf.dcb_tx_conf; 2341 if (!(conf->nb_tcs == ETH_4_TCS || 2342 conf->nb_tcs == ETH_8_TCS)) { 2343 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2344 " and nb_tcs != %d.", 2345 ETH_4_TCS, ETH_8_TCS); 2346 return -EINVAL; 2347 } 2348 } 2349 2350 /* 2351 * When DCB/VT is off, maximum number of queues changes, 2352 * except for 82598EB, which remains constant. 2353 */ 2354 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 2355 hw->mac.type != ixgbe_mac_82598EB) { 2356 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) { 2357 PMD_INIT_LOG(ERR, 2358 "Neither VT nor DCB are enabled, " 2359 "nb_tx_q > %d.", 2360 IXGBE_NONE_MODE_TX_NB_QUEUES); 2361 return -EINVAL; 2362 } 2363 } 2364 } 2365 return 0; 2366 } 2367 2368 static int 2369 ixgbe_dev_configure(struct rte_eth_dev *dev) 2370 { 2371 struct ixgbe_interrupt *intr = 2372 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2373 struct ixgbe_adapter *adapter = dev->data->dev_private; 2374 int ret; 2375 2376 PMD_INIT_FUNC_TRACE(); 2377 2378 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 2379 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 2380 2381 /* multipe queue mode checking */ 2382 ret = ixgbe_check_mq_mode(dev); 2383 if (ret != 0) { 2384 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.", 2385 ret); 2386 return ret; 2387 } 2388 2389 /* set flag to update link status after init */ 2390 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2391 2392 /* 2393 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 2394 * allocation or vector Rx preconditions we will reset it. 2395 */ 2396 adapter->rx_bulk_alloc_allowed = true; 2397 adapter->rx_vec_allowed = true; 2398 2399 return 0; 2400 } 2401 2402 static void 2403 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) 2404 { 2405 struct ixgbe_hw *hw = 2406 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2407 struct ixgbe_interrupt *intr = 2408 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2409 uint32_t gpie; 2410 2411 /* only set up it on X550EM_X */ 2412 if (hw->mac.type == ixgbe_mac_X550EM_x) { 2413 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 2414 gpie |= IXGBE_SDP0_GPIEN_X550EM_x; 2415 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 2416 if (hw->phy.type == ixgbe_phy_x550em_ext_t) 2417 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x; 2418 } 2419 } 2420 2421 int 2422 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 2423 uint16_t tx_rate, uint64_t q_msk) 2424 { 2425 struct ixgbe_hw *hw; 2426 struct ixgbe_vf_info *vfinfo; 2427 struct rte_eth_link link; 2428 uint8_t nb_q_per_pool; 2429 uint32_t queue_stride; 2430 uint32_t queue_idx, idx = 0, vf_idx; 2431 uint32_t queue_end; 2432 uint16_t total_rate = 0; 2433 struct rte_pci_device *pci_dev; 2434 int ret; 2435 2436 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2437 ret = rte_eth_link_get_nowait(dev->data->port_id, &link); 2438 if (ret < 0) 2439 return ret; 2440 2441 if (vf >= pci_dev->max_vfs) 2442 return -EINVAL; 2443 2444 if (tx_rate > link.link_speed) 2445 return -EINVAL; 2446 2447 if (q_msk == 0) 2448 return 0; 2449 2450 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2451 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 2452 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2453 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2454 queue_idx = vf * queue_stride; 2455 queue_end = queue_idx + nb_q_per_pool - 1; 2456 if (queue_end >= hw->mac.max_tx_queues) 2457 return -EINVAL; 2458 2459 if (vfinfo) { 2460 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) { 2461 if (vf_idx == vf) 2462 continue; 2463 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate); 2464 idx++) 2465 total_rate += vfinfo[vf_idx].tx_rate[idx]; 2466 } 2467 } else { 2468 return -EINVAL; 2469 } 2470 2471 /* Store tx_rate for this vf. */ 2472 for (idx = 0; idx < nb_q_per_pool; idx++) { 2473 if (((uint64_t)0x1 << idx) & q_msk) { 2474 if (vfinfo[vf].tx_rate[idx] != tx_rate) 2475 vfinfo[vf].tx_rate[idx] = tx_rate; 2476 total_rate += tx_rate; 2477 } 2478 } 2479 2480 if (total_rate > dev->data->dev_link.link_speed) { 2481 /* Reset stored TX rate of the VF if it causes exceed 2482 * link speed. 2483 */ 2484 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate)); 2485 return -EINVAL; 2486 } 2487 2488 /* Set RTTBCNRC of each queue/pool for vf X */ 2489 for (; queue_idx <= queue_end; queue_idx++) { 2490 if (0x1 & q_msk) 2491 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate); 2492 q_msk = q_msk >> 1; 2493 } 2494 2495 return 0; 2496 } 2497 2498 static int 2499 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw) 2500 { 2501 struct ixgbe_adapter *adapter = dev->data->dev_private; 2502 int err; 2503 uint32_t mflcn; 2504 2505 ixgbe_setup_fc(hw); 2506 2507 err = ixgbe_fc_enable(hw); 2508 2509 /* Not negotiated is not an error case */ 2510 if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) { 2511 /* 2512 *check if we want to forward MAC frames - driver doesn't 2513 *have native capability to do that, 2514 *so we'll write the registers ourselves 2515 */ 2516 2517 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2518 2519 /* set or clear MFLCN.PMCF bit depending on configuration */ 2520 if (adapter->mac_ctrl_frame_fwd != 0) 2521 mflcn |= IXGBE_MFLCN_PMCF; 2522 else 2523 mflcn &= ~IXGBE_MFLCN_PMCF; 2524 2525 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn); 2526 IXGBE_WRITE_FLUSH(hw); 2527 2528 return 0; 2529 } 2530 return err; 2531 } 2532 2533 /* 2534 * Configure device link speed and setup link. 2535 * It returns 0 on success. 2536 */ 2537 static int 2538 ixgbe_dev_start(struct rte_eth_dev *dev) 2539 { 2540 struct ixgbe_hw *hw = 2541 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2542 struct ixgbe_vf_info *vfinfo = 2543 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2544 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2545 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2546 uint32_t intr_vector = 0; 2547 int err; 2548 bool link_up = false, negotiate = 0; 2549 uint32_t speed = 0; 2550 uint32_t allowed_speeds = 0; 2551 int mask = 0; 2552 int status; 2553 uint16_t vf, idx; 2554 uint32_t *link_speeds; 2555 struct ixgbe_tm_conf *tm_conf = 2556 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2557 struct ixgbe_macsec_setting *macsec_setting = 2558 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 2559 2560 PMD_INIT_FUNC_TRACE(); 2561 2562 /* Stop the link setup handler before resetting the HW. */ 2563 ixgbe_dev_wait_setup_link_complete(dev, 0); 2564 2565 /* disable uio/vfio intr/eventfd mapping */ 2566 rte_intr_disable(intr_handle); 2567 2568 /* stop adapter */ 2569 hw->adapter_stopped = 0; 2570 ixgbe_stop_adapter(hw); 2571 2572 /* reinitialize adapter 2573 * this calls reset and start 2574 */ 2575 status = ixgbe_pf_reset_hw(hw); 2576 if (status != 0) 2577 return -1; 2578 hw->mac.ops.start_hw(hw); 2579 hw->mac.get_link_status = true; 2580 2581 /* configure PF module if SRIOV enabled */ 2582 ixgbe_pf_host_configure(dev); 2583 2584 ixgbe_dev_phy_intr_setup(dev); 2585 2586 /* check and configure queue intr-vector mapping */ 2587 if ((rte_intr_cap_multiple(intr_handle) || 2588 !RTE_ETH_DEV_SRIOV(dev).active) && 2589 dev->data->dev_conf.intr_conf.rxq != 0) { 2590 intr_vector = dev->data->nb_rx_queues; 2591 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) { 2592 PMD_INIT_LOG(ERR, "At most %d intr queues supported", 2593 IXGBE_MAX_INTR_QUEUE_NUM); 2594 return -ENOTSUP; 2595 } 2596 if (rte_intr_efd_enable(intr_handle, intr_vector)) 2597 return -1; 2598 } 2599 2600 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 2601 intr_handle->intr_vec = 2602 rte_zmalloc("intr_vec", 2603 dev->data->nb_rx_queues * sizeof(int), 0); 2604 if (intr_handle->intr_vec == NULL) { 2605 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 2606 " intr_vec", dev->data->nb_rx_queues); 2607 return -ENOMEM; 2608 } 2609 } 2610 2611 /* confiugre msix for sleep until rx interrupt */ 2612 ixgbe_configure_msix(dev); 2613 2614 /* initialize transmission unit */ 2615 ixgbe_dev_tx_init(dev); 2616 2617 /* This can fail when allocating mbufs for descriptor rings */ 2618 err = ixgbe_dev_rx_init(dev); 2619 if (err) { 2620 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 2621 goto error; 2622 } 2623 2624 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 2625 ETH_VLAN_EXTEND_MASK; 2626 err = ixgbe_vlan_offload_config(dev, mask); 2627 if (err) { 2628 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 2629 goto error; 2630 } 2631 2632 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) { 2633 /* Enable vlan filtering for VMDq */ 2634 ixgbe_vmdq_vlan_hw_filter_enable(dev); 2635 } 2636 2637 /* Configure DCB hw */ 2638 ixgbe_configure_dcb(dev); 2639 2640 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) { 2641 err = ixgbe_fdir_configure(dev); 2642 if (err) 2643 goto error; 2644 } 2645 2646 /* Restore vf rate limit */ 2647 if (vfinfo != NULL) { 2648 for (vf = 0; vf < pci_dev->max_vfs; vf++) 2649 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++) 2650 if (vfinfo[vf].tx_rate[idx] != 0) 2651 ixgbe_set_vf_rate_limit( 2652 dev, vf, 2653 vfinfo[vf].tx_rate[idx], 2654 1 << idx); 2655 } 2656 2657 ixgbe_restore_statistics_mapping(dev); 2658 2659 err = ixgbe_flow_ctrl_enable(dev, hw); 2660 if (err < 0) { 2661 PMD_INIT_LOG(ERR, "enable flow ctrl err"); 2662 goto error; 2663 } 2664 2665 err = ixgbe_dev_rxtx_start(dev); 2666 if (err < 0) { 2667 PMD_INIT_LOG(ERR, "Unable to start rxtx queues"); 2668 goto error; 2669 } 2670 2671 /* Skip link setup if loopback mode is enabled. */ 2672 if (dev->data->dev_conf.lpbk_mode != 0) { 2673 err = ixgbe_check_supported_loopback_mode(dev); 2674 if (err < 0) { 2675 PMD_INIT_LOG(ERR, "Unsupported loopback mode"); 2676 goto error; 2677 } else { 2678 goto skip_link_setup; 2679 } 2680 } 2681 2682 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) { 2683 err = hw->mac.ops.setup_sfp(hw); 2684 if (err) 2685 goto error; 2686 } 2687 2688 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2689 /* Turn on the copper */ 2690 ixgbe_set_phy_power(hw, true); 2691 } else { 2692 /* Turn on the laser */ 2693 ixgbe_enable_tx_laser(hw); 2694 } 2695 2696 err = ixgbe_check_link(hw, &speed, &link_up, 0); 2697 if (err) 2698 goto error; 2699 dev->data->dev_link.link_status = link_up; 2700 2701 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate); 2702 if (err) 2703 goto error; 2704 2705 switch (hw->mac.type) { 2706 case ixgbe_mac_X550: 2707 case ixgbe_mac_X550EM_x: 2708 case ixgbe_mac_X550EM_a: 2709 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2710 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G | 2711 ETH_LINK_SPEED_10G; 2712 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 2713 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 2714 allowed_speeds = ETH_LINK_SPEED_10M | 2715 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G; 2716 break; 2717 default: 2718 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2719 ETH_LINK_SPEED_10G; 2720 } 2721 2722 link_speeds = &dev->data->dev_conf.link_speeds; 2723 2724 /* Ignore autoneg flag bit and check the validity of 2725 * link_speed 2726 */ 2727 if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) { 2728 PMD_INIT_LOG(ERR, "Invalid link setting"); 2729 goto error; 2730 } 2731 2732 speed = 0x0; 2733 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) { 2734 switch (hw->mac.type) { 2735 case ixgbe_mac_82598EB: 2736 speed = IXGBE_LINK_SPEED_82598_AUTONEG; 2737 break; 2738 case ixgbe_mac_82599EB: 2739 case ixgbe_mac_X540: 2740 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2741 break; 2742 case ixgbe_mac_X550: 2743 case ixgbe_mac_X550EM_x: 2744 case ixgbe_mac_X550EM_a: 2745 speed = IXGBE_LINK_SPEED_X550_AUTONEG; 2746 break; 2747 default: 2748 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2749 } 2750 } else { 2751 if (*link_speeds & ETH_LINK_SPEED_10G) 2752 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2753 if (*link_speeds & ETH_LINK_SPEED_5G) 2754 speed |= IXGBE_LINK_SPEED_5GB_FULL; 2755 if (*link_speeds & ETH_LINK_SPEED_2_5G) 2756 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 2757 if (*link_speeds & ETH_LINK_SPEED_1G) 2758 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2759 if (*link_speeds & ETH_LINK_SPEED_100M) 2760 speed |= IXGBE_LINK_SPEED_100_FULL; 2761 if (*link_speeds & ETH_LINK_SPEED_10M) 2762 speed |= IXGBE_LINK_SPEED_10_FULL; 2763 } 2764 2765 err = ixgbe_setup_link(hw, speed, link_up); 2766 if (err) 2767 goto error; 2768 2769 skip_link_setup: 2770 2771 if (rte_intr_allow_others(intr_handle)) { 2772 /* check if lsc interrupt is enabled */ 2773 if (dev->data->dev_conf.intr_conf.lsc != 0) 2774 ixgbe_dev_lsc_interrupt_setup(dev, TRUE); 2775 else 2776 ixgbe_dev_lsc_interrupt_setup(dev, FALSE); 2777 ixgbe_dev_macsec_interrupt_setup(dev); 2778 } else { 2779 rte_intr_callback_unregister(intr_handle, 2780 ixgbe_dev_interrupt_handler, dev); 2781 if (dev->data->dev_conf.intr_conf.lsc != 0) 2782 PMD_INIT_LOG(INFO, "lsc won't enable because of" 2783 " no intr multiplex"); 2784 } 2785 2786 /* check if rxq interrupt is enabled */ 2787 if (dev->data->dev_conf.intr_conf.rxq != 0 && 2788 rte_intr_dp_is_en(intr_handle)) 2789 ixgbe_dev_rxq_interrupt_setup(dev); 2790 2791 /* enable uio/vfio intr/eventfd mapping */ 2792 rte_intr_enable(intr_handle); 2793 2794 /* resume enabled intr since hw reset */ 2795 ixgbe_enable_intr(dev); 2796 ixgbe_l2_tunnel_conf(dev); 2797 ixgbe_filter_restore(dev); 2798 2799 if (tm_conf->root && !tm_conf->committed) 2800 PMD_DRV_LOG(WARNING, 2801 "please call hierarchy_commit() " 2802 "before starting the port"); 2803 2804 /* wait for the controller to acquire link */ 2805 err = ixgbe_wait_for_link_up(hw); 2806 if (err) 2807 goto error; 2808 2809 /* 2810 * Update link status right before return, because it may 2811 * start link configuration process in a separate thread. 2812 */ 2813 ixgbe_dev_link_update(dev, 0); 2814 2815 /* setup the macsec setting register */ 2816 if (macsec_setting->offload_en) 2817 ixgbe_dev_macsec_register_enable(dev, macsec_setting); 2818 2819 return 0; 2820 2821 error: 2822 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err); 2823 ixgbe_dev_clear_queues(dev); 2824 return -EIO; 2825 } 2826 2827 /* 2828 * Stop device: disable rx and tx functions to allow for reconfiguring. 2829 */ 2830 static int 2831 ixgbe_dev_stop(struct rte_eth_dev *dev) 2832 { 2833 struct rte_eth_link link; 2834 struct ixgbe_adapter *adapter = dev->data->dev_private; 2835 struct ixgbe_hw *hw = 2836 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2837 struct ixgbe_vf_info *vfinfo = 2838 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2839 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2840 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2841 int vf; 2842 struct ixgbe_tm_conf *tm_conf = 2843 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2844 2845 if (hw->adapter_stopped) 2846 return 0; 2847 2848 PMD_INIT_FUNC_TRACE(); 2849 2850 ixgbe_dev_wait_setup_link_complete(dev, 0); 2851 2852 /* disable interrupts */ 2853 ixgbe_disable_intr(hw); 2854 2855 /* reset the NIC */ 2856 ixgbe_pf_reset_hw(hw); 2857 hw->adapter_stopped = 0; 2858 2859 /* stop adapter */ 2860 ixgbe_stop_adapter(hw); 2861 2862 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++) 2863 vfinfo[vf].clear_to_send = false; 2864 2865 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2866 /* Turn off the copper */ 2867 ixgbe_set_phy_power(hw, false); 2868 } else { 2869 /* Turn off the laser */ 2870 ixgbe_disable_tx_laser(hw); 2871 } 2872 2873 ixgbe_dev_clear_queues(dev); 2874 2875 /* Clear stored conf */ 2876 dev->data->scattered_rx = 0; 2877 dev->data->lro = 0; 2878 2879 /* Clear recorded link status */ 2880 memset(&link, 0, sizeof(link)); 2881 rte_eth_linkstatus_set(dev, &link); 2882 2883 if (!rte_intr_allow_others(intr_handle)) 2884 /* resume to the default handler */ 2885 rte_intr_callback_register(intr_handle, 2886 ixgbe_dev_interrupt_handler, 2887 (void *)dev); 2888 2889 /* Clean datapath event and queue/vec mapping */ 2890 rte_intr_efd_disable(intr_handle); 2891 if (intr_handle->intr_vec != NULL) { 2892 rte_free(intr_handle->intr_vec); 2893 intr_handle->intr_vec = NULL; 2894 } 2895 2896 /* reset hierarchy commit */ 2897 tm_conf->committed = false; 2898 2899 adapter->rss_reta_updated = 0; 2900 2901 hw->adapter_stopped = true; 2902 dev->data->dev_started = 0; 2903 2904 return 0; 2905 } 2906 2907 /* 2908 * Set device link up: enable tx. 2909 */ 2910 static int 2911 ixgbe_dev_set_link_up(struct rte_eth_dev *dev) 2912 { 2913 struct ixgbe_hw *hw = 2914 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2915 if (hw->mac.type == ixgbe_mac_82599EB) { 2916 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2917 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2918 /* Not suported in bypass mode */ 2919 PMD_INIT_LOG(ERR, "Set link up is not supported " 2920 "by device id 0x%x", hw->device_id); 2921 return -ENOTSUP; 2922 } 2923 #endif 2924 } 2925 2926 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2927 /* Turn on the copper */ 2928 ixgbe_set_phy_power(hw, true); 2929 } else { 2930 /* Turn on the laser */ 2931 ixgbe_enable_tx_laser(hw); 2932 ixgbe_dev_link_update(dev, 0); 2933 } 2934 2935 return 0; 2936 } 2937 2938 /* 2939 * Set device link down: disable tx. 2940 */ 2941 static int 2942 ixgbe_dev_set_link_down(struct rte_eth_dev *dev) 2943 { 2944 struct ixgbe_hw *hw = 2945 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2946 if (hw->mac.type == ixgbe_mac_82599EB) { 2947 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2948 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2949 /* Not suported in bypass mode */ 2950 PMD_INIT_LOG(ERR, "Set link down is not supported " 2951 "by device id 0x%x", hw->device_id); 2952 return -ENOTSUP; 2953 } 2954 #endif 2955 } 2956 2957 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2958 /* Turn off the copper */ 2959 ixgbe_set_phy_power(hw, false); 2960 } else { 2961 /* Turn off the laser */ 2962 ixgbe_disable_tx_laser(hw); 2963 ixgbe_dev_link_update(dev, 0); 2964 } 2965 2966 return 0; 2967 } 2968 2969 /* 2970 * Reset and stop device. 2971 */ 2972 static int 2973 ixgbe_dev_close(struct rte_eth_dev *dev) 2974 { 2975 struct ixgbe_hw *hw = 2976 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2977 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2978 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2979 int retries = 0; 2980 int ret; 2981 2982 PMD_INIT_FUNC_TRACE(); 2983 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2984 return 0; 2985 2986 ixgbe_pf_reset_hw(hw); 2987 2988 ret = ixgbe_dev_stop(dev); 2989 2990 ixgbe_dev_free_queues(dev); 2991 2992 ixgbe_disable_pcie_master(hw); 2993 2994 /* reprogram the RAR[0] in case user changed it. */ 2995 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2996 2997 /* Unlock any pending hardware semaphore */ 2998 ixgbe_swfw_lock_reset(hw); 2999 3000 /* disable uio intr before callback unregister */ 3001 rte_intr_disable(intr_handle); 3002 3003 do { 3004 ret = rte_intr_callback_unregister(intr_handle, 3005 ixgbe_dev_interrupt_handler, dev); 3006 if (ret >= 0 || ret == -ENOENT) { 3007 break; 3008 } else if (ret != -EAGAIN) { 3009 PMD_INIT_LOG(ERR, 3010 "intr callback unregister failed: %d", 3011 ret); 3012 } 3013 rte_delay_ms(100); 3014 } while (retries++ < (10 + IXGBE_LINK_UP_TIME)); 3015 3016 /* cancel the delay handler before remove dev */ 3017 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev); 3018 3019 /* uninitialize PF if max_vfs not zero */ 3020 ixgbe_pf_host_uninit(dev); 3021 3022 /* remove all the fdir filters & hash */ 3023 ixgbe_fdir_filter_uninit(dev); 3024 3025 /* remove all the L2 tunnel filters & hash */ 3026 ixgbe_l2_tn_filter_uninit(dev); 3027 3028 /* Remove all ntuple filters of the device */ 3029 ixgbe_ntuple_filter_uninit(dev); 3030 3031 /* clear all the filters list */ 3032 ixgbe_filterlist_flush(); 3033 3034 /* Remove all Traffic Manager configuration */ 3035 ixgbe_tm_conf_uninit(dev); 3036 3037 #ifdef RTE_LIB_SECURITY 3038 rte_free(dev->security_ctx); 3039 #endif 3040 3041 return ret; 3042 } 3043 3044 /* 3045 * Reset PF device. 3046 */ 3047 static int 3048 ixgbe_dev_reset(struct rte_eth_dev *dev) 3049 { 3050 int ret; 3051 3052 /* When a DPDK PMD PF begin to reset PF port, it should notify all 3053 * its VF to make them align with it. The detailed notification 3054 * mechanism is PMD specific. As to ixgbe PF, it is rather complex. 3055 * To avoid unexpected behavior in VF, currently reset of PF with 3056 * SR-IOV activation is not supported. It might be supported later. 3057 */ 3058 if (dev->data->sriov.active) 3059 return -ENOTSUP; 3060 3061 ret = eth_ixgbe_dev_uninit(dev); 3062 if (ret) 3063 return ret; 3064 3065 ret = eth_ixgbe_dev_init(dev, NULL); 3066 3067 return ret; 3068 } 3069 3070 static void 3071 ixgbe_read_stats_registers(struct ixgbe_hw *hw, 3072 struct ixgbe_hw_stats *hw_stats, 3073 struct ixgbe_macsec_stats *macsec_stats, 3074 uint64_t *total_missed_rx, uint64_t *total_qbrc, 3075 uint64_t *total_qprc, uint64_t *total_qprdc) 3076 { 3077 uint32_t bprc, lxon, lxoff, total; 3078 uint32_t delta_gprc = 0; 3079 unsigned i; 3080 /* Workaround for RX byte count not including CRC bytes when CRC 3081 * strip is enabled. CRC bytes are removed from counters when crc_strip 3082 * is disabled. 3083 */ 3084 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) & 3085 IXGBE_HLREG0_RXCRCSTRP); 3086 3087 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 3088 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC); 3089 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC); 3090 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC); 3091 3092 for (i = 0; i < 8; i++) { 3093 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 3094 3095 /* global total per queue */ 3096 hw_stats->mpc[i] += mp; 3097 /* Running comprehensive total for stats display */ 3098 *total_missed_rx += hw_stats->mpc[i]; 3099 if (hw->mac.type == ixgbe_mac_82598EB) { 3100 hw_stats->rnbc[i] += 3101 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 3102 hw_stats->pxonrxc[i] += 3103 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 3104 hw_stats->pxoffrxc[i] += 3105 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 3106 } else { 3107 hw_stats->pxonrxc[i] += 3108 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 3109 hw_stats->pxoffrxc[i] += 3110 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 3111 hw_stats->pxon2offc[i] += 3112 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 3113 } 3114 hw_stats->pxontxc[i] += 3115 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 3116 hw_stats->pxofftxc[i] += 3117 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 3118 } 3119 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3120 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 3121 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 3122 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 3123 3124 delta_gprc += delta_qprc; 3125 3126 hw_stats->qprc[i] += delta_qprc; 3127 hw_stats->qptc[i] += delta_qptc; 3128 3129 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 3130 hw_stats->qbrc[i] += 3131 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32); 3132 if (crc_strip == 0) 3133 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN; 3134 3135 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 3136 hw_stats->qbtc[i] += 3137 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32); 3138 3139 hw_stats->qprdc[i] += delta_qprdc; 3140 *total_qprdc += hw_stats->qprdc[i]; 3141 3142 *total_qprc += hw_stats->qprc[i]; 3143 *total_qbrc += hw_stats->qbrc[i]; 3144 } 3145 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC); 3146 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC); 3147 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 3148 3149 /* 3150 * An errata states that gprc actually counts good + missed packets: 3151 * Workaround to set gprc to summated queue packet receives 3152 */ 3153 hw_stats->gprc = *total_qprc; 3154 3155 if (hw->mac.type != ixgbe_mac_82598EB) { 3156 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 3157 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32); 3158 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 3159 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32); 3160 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 3161 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32); 3162 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 3163 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 3164 } else { 3165 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 3166 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 3167 /* 82598 only has a counter in the high register */ 3168 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 3169 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 3170 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 3171 } 3172 uint64_t old_tpr = hw_stats->tpr; 3173 3174 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 3175 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT); 3176 3177 if (crc_strip == 0) 3178 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN; 3179 3180 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC); 3181 hw_stats->gptc += delta_gptc; 3182 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN; 3183 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN; 3184 3185 /* 3186 * Workaround: mprc hardware is incorrectly counting 3187 * broadcasts, so for now we subtract those. 3188 */ 3189 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 3190 hw_stats->bprc += bprc; 3191 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 3192 if (hw->mac.type == ixgbe_mac_82598EB) 3193 hw_stats->mprc -= bprc; 3194 3195 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 3196 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 3197 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 3198 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 3199 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 3200 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 3201 3202 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 3203 hw_stats->lxontxc += lxon; 3204 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 3205 hw_stats->lxofftxc += lxoff; 3206 total = lxon + lxoff; 3207 3208 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 3209 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 3210 hw_stats->gptc -= total; 3211 hw_stats->mptc -= total; 3212 hw_stats->ptc64 -= total; 3213 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN; 3214 3215 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 3216 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 3217 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 3218 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 3219 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC); 3220 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC); 3221 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC); 3222 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 3223 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 3224 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 3225 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 3226 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 3227 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 3228 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC); 3229 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 3230 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST); 3231 /* Only read FCOE on 82599 */ 3232 if (hw->mac.type != ixgbe_mac_82598EB) { 3233 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 3234 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 3235 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 3236 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 3237 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 3238 } 3239 3240 /* Flow Director Stats registers */ 3241 if (hw->mac.type != ixgbe_mac_82598EB) { 3242 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 3243 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 3244 hw_stats->fdirustat_add += IXGBE_READ_REG(hw, 3245 IXGBE_FDIRUSTAT) & 0xFFFF; 3246 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw, 3247 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF; 3248 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw, 3249 IXGBE_FDIRFSTAT) & 0xFFFF; 3250 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw, 3251 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF; 3252 } 3253 /* MACsec Stats registers */ 3254 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT); 3255 macsec_stats->out_pkts_encrypted += 3256 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE); 3257 macsec_stats->out_pkts_protected += 3258 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP); 3259 macsec_stats->out_octets_encrypted += 3260 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE); 3261 macsec_stats->out_octets_protected += 3262 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP); 3263 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT); 3264 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD); 3265 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI); 3266 macsec_stats->in_pkts_unknownsci += 3267 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI); 3268 macsec_stats->in_octets_decrypted += 3269 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD); 3270 macsec_stats->in_octets_validated += 3271 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV); 3272 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH); 3273 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY); 3274 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE); 3275 for (i = 0; i < 2; i++) { 3276 macsec_stats->in_pkts_ok += 3277 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i)); 3278 macsec_stats->in_pkts_invalid += 3279 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i)); 3280 macsec_stats->in_pkts_notvalid += 3281 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i)); 3282 } 3283 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA); 3284 macsec_stats->in_pkts_notusingsa += 3285 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA); 3286 } 3287 3288 /* 3289 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c 3290 */ 3291 static int 3292 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3293 { 3294 struct ixgbe_hw *hw = 3295 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3296 struct ixgbe_hw_stats *hw_stats = 3297 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3298 struct ixgbe_macsec_stats *macsec_stats = 3299 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3300 dev->data->dev_private); 3301 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3302 unsigned i; 3303 3304 total_missed_rx = 0; 3305 total_qbrc = 0; 3306 total_qprc = 0; 3307 total_qprdc = 0; 3308 3309 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3310 &total_qbrc, &total_qprc, &total_qprdc); 3311 3312 if (stats == NULL) 3313 return -EINVAL; 3314 3315 /* Fill out the rte_eth_stats statistics structure */ 3316 stats->ipackets = total_qprc; 3317 stats->ibytes = total_qbrc; 3318 stats->opackets = hw_stats->gptc; 3319 stats->obytes = hw_stats->gotc; 3320 3321 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3322 stats->q_ipackets[i] = hw_stats->qprc[i]; 3323 stats->q_opackets[i] = hw_stats->qptc[i]; 3324 stats->q_ibytes[i] = hw_stats->qbrc[i]; 3325 stats->q_obytes[i] = hw_stats->qbtc[i]; 3326 stats->q_errors[i] = hw_stats->qprdc[i]; 3327 } 3328 3329 /* Rx Errors */ 3330 stats->imissed = total_missed_rx; 3331 stats->ierrors = hw_stats->crcerrs + 3332 hw_stats->mspdc + 3333 hw_stats->rlec + 3334 hw_stats->ruc + 3335 hw_stats->roc + 3336 hw_stats->illerrc + 3337 hw_stats->errbc + 3338 hw_stats->rfc + 3339 hw_stats->fccrc + 3340 hw_stats->fclast; 3341 3342 /* Tx Errors */ 3343 stats->oerrors = 0; 3344 return 0; 3345 } 3346 3347 static int 3348 ixgbe_dev_stats_reset(struct rte_eth_dev *dev) 3349 { 3350 struct ixgbe_hw_stats *stats = 3351 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3352 3353 /* HW registers are cleared on read */ 3354 ixgbe_dev_stats_get(dev, NULL); 3355 3356 /* Reset software totals */ 3357 memset(stats, 0, sizeof(*stats)); 3358 3359 return 0; 3360 } 3361 3362 /* This function calculates the number of xstats based on the current config */ 3363 static unsigned 3364 ixgbe_xstats_calc_num(void) { 3365 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS + 3366 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) + 3367 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES); 3368 } 3369 3370 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3371 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size) 3372 { 3373 const unsigned cnt_stats = ixgbe_xstats_calc_num(); 3374 unsigned stat, i, count; 3375 3376 if (xstats_names != NULL) { 3377 count = 0; 3378 3379 /* Note: limit >= cnt_stats checked upstream 3380 * in rte_eth_xstats_names() 3381 */ 3382 3383 /* Extended stats from ixgbe_hw_stats */ 3384 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3385 strlcpy(xstats_names[count].name, 3386 rte_ixgbe_stats_strings[i].name, 3387 sizeof(xstats_names[count].name)); 3388 count++; 3389 } 3390 3391 /* MACsec Stats */ 3392 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3393 strlcpy(xstats_names[count].name, 3394 rte_ixgbe_macsec_strings[i].name, 3395 sizeof(xstats_names[count].name)); 3396 count++; 3397 } 3398 3399 /* RX Priority Stats */ 3400 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3401 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3402 snprintf(xstats_names[count].name, 3403 sizeof(xstats_names[count].name), 3404 "rx_priority%u_%s", i, 3405 rte_ixgbe_rxq_strings[stat].name); 3406 count++; 3407 } 3408 } 3409 3410 /* TX Priority Stats */ 3411 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3412 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3413 snprintf(xstats_names[count].name, 3414 sizeof(xstats_names[count].name), 3415 "tx_priority%u_%s", i, 3416 rte_ixgbe_txq_strings[stat].name); 3417 count++; 3418 } 3419 } 3420 } 3421 return cnt_stats; 3422 } 3423 3424 static int ixgbe_dev_xstats_get_names_by_id( 3425 struct rte_eth_dev *dev, 3426 struct rte_eth_xstat_name *xstats_names, 3427 const uint64_t *ids, 3428 unsigned int limit) 3429 { 3430 if (!ids) { 3431 const unsigned int cnt_stats = ixgbe_xstats_calc_num(); 3432 unsigned int stat, i, count; 3433 3434 if (xstats_names != NULL) { 3435 count = 0; 3436 3437 /* Note: limit >= cnt_stats checked upstream 3438 * in rte_eth_xstats_names() 3439 */ 3440 3441 /* Extended stats from ixgbe_hw_stats */ 3442 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3443 strlcpy(xstats_names[count].name, 3444 rte_ixgbe_stats_strings[i].name, 3445 sizeof(xstats_names[count].name)); 3446 count++; 3447 } 3448 3449 /* MACsec Stats */ 3450 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3451 strlcpy(xstats_names[count].name, 3452 rte_ixgbe_macsec_strings[i].name, 3453 sizeof(xstats_names[count].name)); 3454 count++; 3455 } 3456 3457 /* RX Priority Stats */ 3458 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3459 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3460 snprintf(xstats_names[count].name, 3461 sizeof(xstats_names[count].name), 3462 "rx_priority%u_%s", i, 3463 rte_ixgbe_rxq_strings[stat].name); 3464 count++; 3465 } 3466 } 3467 3468 /* TX Priority Stats */ 3469 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3470 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3471 snprintf(xstats_names[count].name, 3472 sizeof(xstats_names[count].name), 3473 "tx_priority%u_%s", i, 3474 rte_ixgbe_txq_strings[stat].name); 3475 count++; 3476 } 3477 } 3478 } 3479 return cnt_stats; 3480 } 3481 3482 uint16_t i; 3483 uint16_t size = ixgbe_xstats_calc_num(); 3484 struct rte_eth_xstat_name xstats_names_copy[size]; 3485 3486 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL, 3487 size); 3488 3489 for (i = 0; i < limit; i++) { 3490 if (ids[i] >= size) { 3491 PMD_INIT_LOG(ERR, "id value isn't valid"); 3492 return -1; 3493 } 3494 strcpy(xstats_names[i].name, 3495 xstats_names_copy[ids[i]].name); 3496 } 3497 return limit; 3498 } 3499 3500 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3501 struct rte_eth_xstat_name *xstats_names, unsigned limit) 3502 { 3503 unsigned i; 3504 3505 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL) 3506 return -ENOMEM; 3507 3508 if (xstats_names != NULL) 3509 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) 3510 strlcpy(xstats_names[i].name, 3511 rte_ixgbevf_stats_strings[i].name, 3512 sizeof(xstats_names[i].name)); 3513 return IXGBEVF_NB_XSTATS; 3514 } 3515 3516 static int 3517 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3518 unsigned n) 3519 { 3520 struct ixgbe_hw *hw = 3521 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3522 struct ixgbe_hw_stats *hw_stats = 3523 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3524 struct ixgbe_macsec_stats *macsec_stats = 3525 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3526 dev->data->dev_private); 3527 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3528 unsigned i, stat, count = 0; 3529 3530 count = ixgbe_xstats_calc_num(); 3531 3532 if (n < count) 3533 return count; 3534 3535 total_missed_rx = 0; 3536 total_qbrc = 0; 3537 total_qprc = 0; 3538 total_qprdc = 0; 3539 3540 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3541 &total_qbrc, &total_qprc, &total_qprdc); 3542 3543 /* If this is a reset xstats is NULL, and we have cleared the 3544 * registers by reading them. 3545 */ 3546 if (!xstats) 3547 return 0; 3548 3549 /* Extended stats from ixgbe_hw_stats */ 3550 count = 0; 3551 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3552 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3553 rte_ixgbe_stats_strings[i].offset); 3554 xstats[count].id = count; 3555 count++; 3556 } 3557 3558 /* MACsec Stats */ 3559 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3560 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) + 3561 rte_ixgbe_macsec_strings[i].offset); 3562 xstats[count].id = count; 3563 count++; 3564 } 3565 3566 /* RX Priority Stats */ 3567 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3568 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3569 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3570 rte_ixgbe_rxq_strings[stat].offset + 3571 (sizeof(uint64_t) * i)); 3572 xstats[count].id = count; 3573 count++; 3574 } 3575 } 3576 3577 /* TX Priority Stats */ 3578 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3579 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3580 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3581 rte_ixgbe_txq_strings[stat].offset + 3582 (sizeof(uint64_t) * i)); 3583 xstats[count].id = count; 3584 count++; 3585 } 3586 } 3587 return count; 3588 } 3589 3590 static int 3591 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 3592 uint64_t *values, unsigned int n) 3593 { 3594 if (!ids) { 3595 struct ixgbe_hw *hw = 3596 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3597 struct ixgbe_hw_stats *hw_stats = 3598 IXGBE_DEV_PRIVATE_TO_STATS( 3599 dev->data->dev_private); 3600 struct ixgbe_macsec_stats *macsec_stats = 3601 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3602 dev->data->dev_private); 3603 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3604 unsigned int i, stat, count = 0; 3605 3606 count = ixgbe_xstats_calc_num(); 3607 3608 if (!ids && n < count) 3609 return count; 3610 3611 total_missed_rx = 0; 3612 total_qbrc = 0; 3613 total_qprc = 0; 3614 total_qprdc = 0; 3615 3616 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, 3617 &total_missed_rx, &total_qbrc, &total_qprc, 3618 &total_qprdc); 3619 3620 /* If this is a reset xstats is NULL, and we have cleared the 3621 * registers by reading them. 3622 */ 3623 if (!ids && !values) 3624 return 0; 3625 3626 /* Extended stats from ixgbe_hw_stats */ 3627 count = 0; 3628 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3629 values[count] = *(uint64_t *)(((char *)hw_stats) + 3630 rte_ixgbe_stats_strings[i].offset); 3631 count++; 3632 } 3633 3634 /* MACsec Stats */ 3635 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3636 values[count] = *(uint64_t *)(((char *)macsec_stats) + 3637 rte_ixgbe_macsec_strings[i].offset); 3638 count++; 3639 } 3640 3641 /* RX Priority Stats */ 3642 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3643 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3644 values[count] = 3645 *(uint64_t *)(((char *)hw_stats) + 3646 rte_ixgbe_rxq_strings[stat].offset + 3647 (sizeof(uint64_t) * i)); 3648 count++; 3649 } 3650 } 3651 3652 /* TX Priority Stats */ 3653 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3654 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3655 values[count] = 3656 *(uint64_t *)(((char *)hw_stats) + 3657 rte_ixgbe_txq_strings[stat].offset + 3658 (sizeof(uint64_t) * i)); 3659 count++; 3660 } 3661 } 3662 return count; 3663 } 3664 3665 uint16_t i; 3666 uint16_t size = ixgbe_xstats_calc_num(); 3667 uint64_t values_copy[size]; 3668 3669 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size); 3670 3671 for (i = 0; i < n; i++) { 3672 if (ids[i] >= size) { 3673 PMD_INIT_LOG(ERR, "id value isn't valid"); 3674 return -1; 3675 } 3676 values[i] = values_copy[ids[i]]; 3677 } 3678 return n; 3679 } 3680 3681 static int 3682 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev) 3683 { 3684 struct ixgbe_hw_stats *stats = 3685 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3686 struct ixgbe_macsec_stats *macsec_stats = 3687 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3688 dev->data->dev_private); 3689 3690 unsigned count = ixgbe_xstats_calc_num(); 3691 3692 /* HW registers are cleared on read */ 3693 ixgbe_dev_xstats_get(dev, NULL, count); 3694 3695 /* Reset software totals */ 3696 memset(stats, 0, sizeof(*stats)); 3697 memset(macsec_stats, 0, sizeof(*macsec_stats)); 3698 3699 return 0; 3700 } 3701 3702 static void 3703 ixgbevf_update_stats(struct rte_eth_dev *dev) 3704 { 3705 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3706 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3707 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3708 3709 /* Good Rx packet, include VF loopback */ 3710 UPDATE_VF_STAT(IXGBE_VFGPRC, 3711 hw_stats->last_vfgprc, hw_stats->vfgprc); 3712 3713 /* Good Rx octets, include VF loopback */ 3714 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB, 3715 hw_stats->last_vfgorc, hw_stats->vfgorc); 3716 3717 /* Good Tx packet, include VF loopback */ 3718 UPDATE_VF_STAT(IXGBE_VFGPTC, 3719 hw_stats->last_vfgptc, hw_stats->vfgptc); 3720 3721 /* Good Tx octets, include VF loopback */ 3722 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB, 3723 hw_stats->last_vfgotc, hw_stats->vfgotc); 3724 3725 /* Rx Multicst Packet */ 3726 UPDATE_VF_STAT(IXGBE_VFMPRC, 3727 hw_stats->last_vfmprc, hw_stats->vfmprc); 3728 } 3729 3730 static int 3731 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3732 unsigned n) 3733 { 3734 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3735 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3736 unsigned i; 3737 3738 if (n < IXGBEVF_NB_XSTATS) 3739 return IXGBEVF_NB_XSTATS; 3740 3741 ixgbevf_update_stats(dev); 3742 3743 if (!xstats) 3744 return 0; 3745 3746 /* Extended stats */ 3747 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) { 3748 xstats[i].id = i; 3749 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + 3750 rte_ixgbevf_stats_strings[i].offset); 3751 } 3752 3753 return IXGBEVF_NB_XSTATS; 3754 } 3755 3756 static int 3757 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3758 { 3759 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3760 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3761 3762 ixgbevf_update_stats(dev); 3763 3764 if (stats == NULL) 3765 return -EINVAL; 3766 3767 stats->ipackets = hw_stats->vfgprc; 3768 stats->ibytes = hw_stats->vfgorc; 3769 stats->opackets = hw_stats->vfgptc; 3770 stats->obytes = hw_stats->vfgotc; 3771 return 0; 3772 } 3773 3774 static int 3775 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev) 3776 { 3777 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3778 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3779 3780 /* Sync HW register to the last stats */ 3781 ixgbevf_dev_stats_get(dev, NULL); 3782 3783 /* reset HW current stats*/ 3784 hw_stats->vfgprc = 0; 3785 hw_stats->vfgorc = 0; 3786 hw_stats->vfgptc = 0; 3787 hw_stats->vfgotc = 0; 3788 3789 return 0; 3790 } 3791 3792 static int 3793 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 3794 { 3795 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3796 u16 eeprom_verh, eeprom_verl; 3797 u32 etrack_id; 3798 int ret; 3799 3800 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh); 3801 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl); 3802 3803 etrack_id = (eeprom_verh << 16) | eeprom_verl; 3804 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id); 3805 3806 ret += 1; /* add the size of '\0' */ 3807 if (fw_size < (u32)ret) 3808 return ret; 3809 else 3810 return 0; 3811 } 3812 3813 static int 3814 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3815 { 3816 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3817 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3818 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 3819 3820 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3821 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3822 if (RTE_ETH_DEV_SRIOV(dev).active == 0) { 3823 /* 3824 * When DCB/VT is off, maximum number of queues changes, 3825 * except for 82598EB, which remains constant. 3826 */ 3827 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 3828 hw->mac.type != ixgbe_mac_82598EB) 3829 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES; 3830 } 3831 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */ 3832 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */ 3833 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3834 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3835 dev_info->max_vfs = pci_dev->max_vfs; 3836 if (hw->mac.type == ixgbe_mac_82598EB) 3837 dev_info->max_vmdq_pools = ETH_16_POOLS; 3838 else 3839 dev_info->max_vmdq_pools = ETH_64_POOLS; 3840 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD; 3841 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 3842 dev_info->vmdq_queue_num = dev_info->max_rx_queues; 3843 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3844 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3845 dev_info->rx_queue_offload_capa); 3846 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3847 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3848 3849 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3850 .rx_thresh = { 3851 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3852 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3853 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3854 }, 3855 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3856 .rx_drop_en = 0, 3857 .offloads = 0, 3858 }; 3859 3860 dev_info->default_txconf = (struct rte_eth_txconf) { 3861 .tx_thresh = { 3862 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3863 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3864 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3865 }, 3866 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3867 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3868 .offloads = 0, 3869 }; 3870 3871 dev_info->rx_desc_lim = rx_desc_lim; 3872 dev_info->tx_desc_lim = tx_desc_lim; 3873 3874 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 3875 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 3876 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 3877 3878 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 3879 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 3880 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 3881 dev_info->speed_capa = ETH_LINK_SPEED_10M | 3882 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G; 3883 3884 if (hw->mac.type == ixgbe_mac_X540 || 3885 hw->mac.type == ixgbe_mac_X540_vf || 3886 hw->mac.type == ixgbe_mac_X550 || 3887 hw->mac.type == ixgbe_mac_X550_vf) { 3888 dev_info->speed_capa |= ETH_LINK_SPEED_100M; 3889 } 3890 if (hw->mac.type == ixgbe_mac_X550) { 3891 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G; 3892 dev_info->speed_capa |= ETH_LINK_SPEED_5G; 3893 } 3894 3895 /* Driver-preferred Rx/Tx parameters */ 3896 dev_info->default_rxportconf.burst_size = 32; 3897 dev_info->default_txportconf.burst_size = 32; 3898 dev_info->default_rxportconf.nb_queues = 1; 3899 dev_info->default_txportconf.nb_queues = 1; 3900 dev_info->default_rxportconf.ring_size = 256; 3901 dev_info->default_txportconf.ring_size = 256; 3902 3903 return 0; 3904 } 3905 3906 static const uint32_t * 3907 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 3908 { 3909 static const uint32_t ptypes[] = { 3910 /* For non-vec functions, 3911 * refers to ixgbe_rxd_pkt_info_to_pkt_type(); 3912 * for vec functions, 3913 * refers to _recv_raw_pkts_vec(). 3914 */ 3915 RTE_PTYPE_L2_ETHER, 3916 RTE_PTYPE_L3_IPV4, 3917 RTE_PTYPE_L3_IPV4_EXT, 3918 RTE_PTYPE_L3_IPV6, 3919 RTE_PTYPE_L3_IPV6_EXT, 3920 RTE_PTYPE_L4_SCTP, 3921 RTE_PTYPE_L4_TCP, 3922 RTE_PTYPE_L4_UDP, 3923 RTE_PTYPE_TUNNEL_IP, 3924 RTE_PTYPE_INNER_L3_IPV6, 3925 RTE_PTYPE_INNER_L3_IPV6_EXT, 3926 RTE_PTYPE_INNER_L4_TCP, 3927 RTE_PTYPE_INNER_L4_UDP, 3928 RTE_PTYPE_UNKNOWN 3929 }; 3930 3931 if (dev->rx_pkt_burst == ixgbe_recv_pkts || 3932 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc || 3933 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc || 3934 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc) 3935 return ptypes; 3936 3937 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON) 3938 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec || 3939 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec) 3940 return ptypes; 3941 #endif 3942 return NULL; 3943 } 3944 3945 static int 3946 ixgbevf_dev_info_get(struct rte_eth_dev *dev, 3947 struct rte_eth_dev_info *dev_info) 3948 { 3949 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3950 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3951 3952 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3953 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3954 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */ 3955 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */ 3956 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD; 3957 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3958 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3959 dev_info->max_vfs = pci_dev->max_vfs; 3960 if (hw->mac.type == ixgbe_mac_82598EB) 3961 dev_info->max_vmdq_pools = ETH_16_POOLS; 3962 else 3963 dev_info->max_vmdq_pools = ETH_64_POOLS; 3964 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3965 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3966 dev_info->rx_queue_offload_capa); 3967 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3968 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3969 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 3970 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 3971 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 3972 3973 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3974 .rx_thresh = { 3975 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3976 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3977 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3978 }, 3979 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3980 .rx_drop_en = 0, 3981 .offloads = 0, 3982 }; 3983 3984 dev_info->default_txconf = (struct rte_eth_txconf) { 3985 .tx_thresh = { 3986 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3987 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3988 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3989 }, 3990 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3991 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3992 .offloads = 0, 3993 }; 3994 3995 dev_info->rx_desc_lim = rx_desc_lim; 3996 dev_info->tx_desc_lim = tx_desc_lim; 3997 3998 return 0; 3999 } 4000 4001 static int 4002 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4003 bool *link_up, int wait_to_complete) 4004 { 4005 struct ixgbe_adapter *adapter = container_of(hw, 4006 struct ixgbe_adapter, hw); 4007 struct ixgbe_mbx_info *mbx = &hw->mbx; 4008 struct ixgbe_mac_info *mac = &hw->mac; 4009 uint32_t links_reg, in_msg; 4010 int ret_val = 0; 4011 4012 /* If we were hit with a reset drop the link */ 4013 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout) 4014 mac->get_link_status = true; 4015 4016 if (!mac->get_link_status) 4017 goto out; 4018 4019 /* if link status is down no point in checking to see if pf is up */ 4020 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 4021 if (!(links_reg & IXGBE_LINKS_UP)) 4022 goto out; 4023 4024 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs 4025 * before the link status is correct 4026 */ 4027 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) { 4028 int i; 4029 4030 for (i = 0; i < 5; i++) { 4031 rte_delay_us(100); 4032 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 4033 4034 if (!(links_reg & IXGBE_LINKS_UP)) 4035 goto out; 4036 } 4037 } 4038 4039 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 4040 case IXGBE_LINKS_SPEED_10G_82599: 4041 *speed = IXGBE_LINK_SPEED_10GB_FULL; 4042 if (hw->mac.type >= ixgbe_mac_X550) { 4043 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4044 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4045 } 4046 break; 4047 case IXGBE_LINKS_SPEED_1G_82599: 4048 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4049 break; 4050 case IXGBE_LINKS_SPEED_100_82599: 4051 *speed = IXGBE_LINK_SPEED_100_FULL; 4052 if (hw->mac.type == ixgbe_mac_X550) { 4053 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4054 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4055 } 4056 break; 4057 case IXGBE_LINKS_SPEED_10_X550EM_A: 4058 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4059 /* Since Reserved in older MAC's */ 4060 if (hw->mac.type >= ixgbe_mac_X550) 4061 *speed = IXGBE_LINK_SPEED_10_FULL; 4062 break; 4063 default: 4064 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4065 } 4066 4067 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) { 4068 if (*speed == IXGBE_LINK_SPEED_UNKNOWN) 4069 mac->get_link_status = true; 4070 else 4071 mac->get_link_status = false; 4072 4073 goto out; 4074 } 4075 4076 /* if the read failed it could just be a mailbox collision, best wait 4077 * until we are called again and don't report an error 4078 */ 4079 if (mbx->ops.read(hw, &in_msg, 1, 0)) 4080 goto out; 4081 4082 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) { 4083 /* msg is not CTS and is NACK we must have lost CTS status */ 4084 if (in_msg & IXGBE_VT_MSGTYPE_NACK) 4085 mac->get_link_status = false; 4086 goto out; 4087 } 4088 4089 /* the pf is talking, if we timed out in the past we reinit */ 4090 if (!mbx->timeout) { 4091 ret_val = -1; 4092 goto out; 4093 } 4094 4095 /* if we passed all the tests above then the link is up and we no 4096 * longer need to check for link 4097 */ 4098 mac->get_link_status = false; 4099 4100 out: 4101 *link_up = !mac->get_link_status; 4102 return ret_val; 4103 } 4104 4105 /* 4106 * If @timeout_ms was 0, it means that it will not return until link complete. 4107 * It returns 1 on complete, return 0 on timeout. 4108 */ 4109 static int 4110 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms) 4111 { 4112 #define WARNING_TIMEOUT 9000 /* 9s in total */ 4113 struct ixgbe_adapter *ad = dev->data->dev_private; 4114 uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT; 4115 4116 while (rte_atomic32_read(&ad->link_thread_running)) { 4117 msec_delay(1); 4118 timeout--; 4119 4120 if (timeout_ms) { 4121 if (!timeout) 4122 return 0; 4123 } else if (!timeout) { 4124 /* It will not return until link complete */ 4125 timeout = WARNING_TIMEOUT; 4126 PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!"); 4127 } 4128 } 4129 4130 return 1; 4131 } 4132 4133 static void * 4134 ixgbe_dev_setup_link_thread_handler(void *param) 4135 { 4136 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4137 struct ixgbe_adapter *ad = dev->data->dev_private; 4138 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4139 struct ixgbe_interrupt *intr = 4140 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4141 u32 speed; 4142 bool autoneg = false; 4143 4144 pthread_detach(pthread_self()); 4145 speed = hw->phy.autoneg_advertised; 4146 if (!speed) 4147 ixgbe_get_link_capabilities(hw, &speed, &autoneg); 4148 4149 ixgbe_setup_link(hw, speed, true); 4150 4151 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 4152 rte_atomic32_clear(&ad->link_thread_running); 4153 return NULL; 4154 } 4155 4156 /* 4157 * In freebsd environment, nic_uio drivers do not support interrupts, 4158 * rte_intr_callback_register() will fail to register interrupts. 4159 * We can not make link status to change from down to up by interrupt 4160 * callback. So we need to wait for the controller to acquire link 4161 * when ports start. 4162 * It returns 0 on link up. 4163 */ 4164 static int 4165 ixgbe_wait_for_link_up(struct ixgbe_hw *hw) 4166 { 4167 #ifdef RTE_EXEC_ENV_FREEBSD 4168 int err, i; 4169 bool link_up = false; 4170 uint32_t speed = 0; 4171 const int nb_iter = 25; 4172 4173 for (i = 0; i < nb_iter; i++) { 4174 err = ixgbe_check_link(hw, &speed, &link_up, 0); 4175 if (err) 4176 return err; 4177 if (link_up) 4178 return 0; 4179 msec_delay(200); 4180 } 4181 4182 return 0; 4183 #else 4184 RTE_SET_USED(hw); 4185 return 0; 4186 #endif 4187 } 4188 4189 /* return 0 means link status changed, -1 means not changed */ 4190 int 4191 ixgbe_dev_link_update_share(struct rte_eth_dev *dev, 4192 int wait_to_complete, int vf) 4193 { 4194 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4195 struct ixgbe_adapter *ad = dev->data->dev_private; 4196 struct rte_eth_link link; 4197 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4198 struct ixgbe_interrupt *intr = 4199 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4200 bool link_up; 4201 int diag; 4202 int wait = 1; 4203 u32 esdp_reg; 4204 4205 memset(&link, 0, sizeof(link)); 4206 link.link_status = ETH_LINK_DOWN; 4207 link.link_speed = ETH_SPEED_NUM_NONE; 4208 link.link_duplex = ETH_LINK_HALF_DUPLEX; 4209 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 4210 ETH_LINK_SPEED_FIXED); 4211 4212 hw->mac.get_link_status = true; 4213 4214 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) 4215 return rte_eth_linkstatus_set(dev, &link); 4216 4217 /* check if it needs to wait to complete, if lsc interrupt is enabled */ 4218 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0) 4219 wait = 0; 4220 4221 /* BSD has no interrupt mechanism, so force NIC status synchronization. */ 4222 #ifdef RTE_EXEC_ENV_FREEBSD 4223 wait = 1; 4224 #endif 4225 4226 if (vf) 4227 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait); 4228 else 4229 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait); 4230 4231 if (diag != 0) { 4232 link.link_speed = ETH_SPEED_NUM_100M; 4233 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4234 return rte_eth_linkstatus_set(dev, &link); 4235 } 4236 4237 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) { 4238 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 4239 if ((esdp_reg & IXGBE_ESDP_SDP3)) 4240 link_up = 0; 4241 } 4242 4243 if (link_up == 0) { 4244 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) { 4245 ixgbe_dev_wait_setup_link_complete(dev, 0); 4246 if (rte_atomic32_test_and_set(&ad->link_thread_running)) { 4247 /* To avoid race condition between threads, set 4248 * the IXGBE_FLAG_NEED_LINK_CONFIG flag only 4249 * when there is no link thread running. 4250 */ 4251 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 4252 if (rte_ctrl_thread_create(&ad->link_thread_tid, 4253 "ixgbe-link-handler", 4254 NULL, 4255 ixgbe_dev_setup_link_thread_handler, 4256 dev) < 0) { 4257 PMD_DRV_LOG(ERR, 4258 "Create link thread failed!"); 4259 rte_atomic32_clear(&ad->link_thread_running); 4260 } 4261 } else { 4262 PMD_DRV_LOG(ERR, 4263 "Other link thread is running now!"); 4264 } 4265 } 4266 return rte_eth_linkstatus_set(dev, &link); 4267 } 4268 4269 link.link_status = ETH_LINK_UP; 4270 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4271 4272 switch (link_speed) { 4273 default: 4274 case IXGBE_LINK_SPEED_UNKNOWN: 4275 link.link_speed = ETH_SPEED_NUM_UNKNOWN; 4276 break; 4277 4278 case IXGBE_LINK_SPEED_10_FULL: 4279 link.link_speed = ETH_SPEED_NUM_10M; 4280 break; 4281 4282 case IXGBE_LINK_SPEED_100_FULL: 4283 link.link_speed = ETH_SPEED_NUM_100M; 4284 break; 4285 4286 case IXGBE_LINK_SPEED_1GB_FULL: 4287 link.link_speed = ETH_SPEED_NUM_1G; 4288 break; 4289 4290 case IXGBE_LINK_SPEED_2_5GB_FULL: 4291 link.link_speed = ETH_SPEED_NUM_2_5G; 4292 break; 4293 4294 case IXGBE_LINK_SPEED_5GB_FULL: 4295 link.link_speed = ETH_SPEED_NUM_5G; 4296 break; 4297 4298 case IXGBE_LINK_SPEED_10GB_FULL: 4299 link.link_speed = ETH_SPEED_NUM_10G; 4300 break; 4301 } 4302 4303 return rte_eth_linkstatus_set(dev, &link); 4304 } 4305 4306 static int 4307 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4308 { 4309 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0); 4310 } 4311 4312 static int 4313 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4314 { 4315 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1); 4316 } 4317 4318 static int 4319 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 4320 { 4321 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4322 uint32_t fctrl; 4323 4324 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4325 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4326 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4327 4328 return 0; 4329 } 4330 4331 static int 4332 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 4333 { 4334 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4335 uint32_t fctrl; 4336 4337 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4338 fctrl &= (~IXGBE_FCTRL_UPE); 4339 if (dev->data->all_multicast == 1) 4340 fctrl |= IXGBE_FCTRL_MPE; 4341 else 4342 fctrl &= (~IXGBE_FCTRL_MPE); 4343 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4344 4345 return 0; 4346 } 4347 4348 static int 4349 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 4350 { 4351 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4352 uint32_t fctrl; 4353 4354 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4355 fctrl |= IXGBE_FCTRL_MPE; 4356 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4357 4358 return 0; 4359 } 4360 4361 static int 4362 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 4363 { 4364 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4365 uint32_t fctrl; 4366 4367 if (dev->data->promiscuous == 1) 4368 return 0; /* must remain in all_multicast mode */ 4369 4370 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4371 fctrl &= (~IXGBE_FCTRL_MPE); 4372 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4373 4374 return 0; 4375 } 4376 4377 /** 4378 * It clears the interrupt causes and enables the interrupt. 4379 * It will be called once only during nic initialized. 4380 * 4381 * @param dev 4382 * Pointer to struct rte_eth_dev. 4383 * @param on 4384 * Enable or Disable. 4385 * 4386 * @return 4387 * - On success, zero. 4388 * - On failure, a negative value. 4389 */ 4390 static int 4391 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 4392 { 4393 struct ixgbe_interrupt *intr = 4394 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4395 4396 ixgbe_dev_link_status_print(dev); 4397 if (on) 4398 intr->mask |= IXGBE_EICR_LSC; 4399 else 4400 intr->mask &= ~IXGBE_EICR_LSC; 4401 4402 return 0; 4403 } 4404 4405 /** 4406 * It clears the interrupt causes and enables the interrupt. 4407 * It will be called once only during nic initialized. 4408 * 4409 * @param dev 4410 * Pointer to struct rte_eth_dev. 4411 * 4412 * @return 4413 * - On success, zero. 4414 * - On failure, a negative value. 4415 */ 4416 static int 4417 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev) 4418 { 4419 struct ixgbe_interrupt *intr = 4420 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4421 4422 intr->mask |= IXGBE_EICR_RTX_QUEUE; 4423 4424 return 0; 4425 } 4426 4427 /** 4428 * It clears the interrupt causes and enables the interrupt. 4429 * It will be called once only during nic initialized. 4430 * 4431 * @param dev 4432 * Pointer to struct rte_eth_dev. 4433 * 4434 * @return 4435 * - On success, zero. 4436 * - On failure, a negative value. 4437 */ 4438 static int 4439 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev) 4440 { 4441 struct ixgbe_interrupt *intr = 4442 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4443 4444 intr->mask |= IXGBE_EICR_LINKSEC; 4445 4446 return 0; 4447 } 4448 4449 /* 4450 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update. 4451 * 4452 * @param dev 4453 * Pointer to struct rte_eth_dev. 4454 * 4455 * @return 4456 * - On success, zero. 4457 * - On failure, a negative value. 4458 */ 4459 static int 4460 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev) 4461 { 4462 uint32_t eicr; 4463 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4464 struct ixgbe_interrupt *intr = 4465 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4466 4467 /* clear all cause mask */ 4468 ixgbe_disable_intr(hw); 4469 4470 /* read-on-clear nic registers here */ 4471 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4472 PMD_DRV_LOG(DEBUG, "eicr %x", eicr); 4473 4474 intr->flags = 0; 4475 4476 /* set flag for async link update */ 4477 if (eicr & IXGBE_EICR_LSC) 4478 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 4479 4480 if (eicr & IXGBE_EICR_MAILBOX) 4481 intr->flags |= IXGBE_FLAG_MAILBOX; 4482 4483 if (eicr & IXGBE_EICR_LINKSEC) 4484 intr->flags |= IXGBE_FLAG_MACSEC; 4485 4486 if (hw->mac.type == ixgbe_mac_X550EM_x && 4487 hw->phy.type == ixgbe_phy_x550em_ext_t && 4488 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x)) 4489 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT; 4490 4491 return 0; 4492 } 4493 4494 /** 4495 * It gets and then prints the link status. 4496 * 4497 * @param dev 4498 * Pointer to struct rte_eth_dev. 4499 * 4500 * @return 4501 * - On success, zero. 4502 * - On failure, a negative value. 4503 */ 4504 static void 4505 ixgbe_dev_link_status_print(struct rte_eth_dev *dev) 4506 { 4507 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4508 struct rte_eth_link link; 4509 4510 rte_eth_linkstatus_get(dev, &link); 4511 4512 if (link.link_status) { 4513 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", 4514 (int)(dev->data->port_id), 4515 (unsigned)link.link_speed, 4516 link.link_duplex == ETH_LINK_FULL_DUPLEX ? 4517 "full-duplex" : "half-duplex"); 4518 } else { 4519 PMD_INIT_LOG(INFO, " Port %d: Link Down", 4520 (int)(dev->data->port_id)); 4521 } 4522 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 4523 pci_dev->addr.domain, 4524 pci_dev->addr.bus, 4525 pci_dev->addr.devid, 4526 pci_dev->addr.function); 4527 } 4528 4529 /* 4530 * It executes link_update after knowing an interrupt occurred. 4531 * 4532 * @param dev 4533 * Pointer to struct rte_eth_dev. 4534 * 4535 * @return 4536 * - On success, zero. 4537 * - On failure, a negative value. 4538 */ 4539 static int 4540 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev) 4541 { 4542 struct ixgbe_interrupt *intr = 4543 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4544 int64_t timeout; 4545 struct ixgbe_hw *hw = 4546 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4547 4548 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags); 4549 4550 if (intr->flags & IXGBE_FLAG_MAILBOX) { 4551 ixgbe_pf_mbx_process(dev); 4552 intr->flags &= ~IXGBE_FLAG_MAILBOX; 4553 } 4554 4555 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4556 ixgbe_handle_lasi(hw); 4557 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4558 } 4559 4560 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4561 struct rte_eth_link link; 4562 4563 /* get the link status before link update, for predicting later */ 4564 rte_eth_linkstatus_get(dev, &link); 4565 4566 ixgbe_dev_link_update(dev, 0); 4567 4568 /* likely to up */ 4569 if (!link.link_status) 4570 /* handle it 1 sec later, wait it being stable */ 4571 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT; 4572 /* likely to down */ 4573 else 4574 /* handle it 4 sec later, wait it being stable */ 4575 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT; 4576 4577 ixgbe_dev_link_status_print(dev); 4578 if (rte_eal_alarm_set(timeout * 1000, 4579 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0) 4580 PMD_DRV_LOG(ERR, "Error setting alarm"); 4581 else { 4582 /* remember original mask */ 4583 intr->mask_original = intr->mask; 4584 /* only disable lsc interrupt */ 4585 intr->mask &= ~IXGBE_EIMS_LSC; 4586 } 4587 } 4588 4589 PMD_DRV_LOG(DEBUG, "enable intr immediately"); 4590 ixgbe_enable_intr(dev); 4591 4592 return 0; 4593 } 4594 4595 /** 4596 * Interrupt handler which shall be registered for alarm callback for delayed 4597 * handling specific interrupt to wait for the stable nic state. As the 4598 * NIC interrupt state is not stable for ixgbe after link is just down, 4599 * it needs to wait 4 seconds to get the stable status. 4600 * 4601 * @param handle 4602 * Pointer to interrupt handle. 4603 * @param param 4604 * The address of parameter (struct rte_eth_dev *) regsitered before. 4605 * 4606 * @return 4607 * void 4608 */ 4609 static void 4610 ixgbe_dev_interrupt_delayed_handler(void *param) 4611 { 4612 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4613 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4614 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4615 struct ixgbe_interrupt *intr = 4616 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4617 struct ixgbe_hw *hw = 4618 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4619 uint32_t eicr; 4620 4621 ixgbe_disable_intr(hw); 4622 4623 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4624 if (eicr & IXGBE_EICR_MAILBOX) 4625 ixgbe_pf_mbx_process(dev); 4626 4627 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4628 ixgbe_handle_lasi(hw); 4629 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4630 } 4631 4632 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4633 ixgbe_dev_link_update(dev, 0); 4634 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 4635 ixgbe_dev_link_status_print(dev); 4636 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 4637 } 4638 4639 if (intr->flags & IXGBE_FLAG_MACSEC) { 4640 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL); 4641 intr->flags &= ~IXGBE_FLAG_MACSEC; 4642 } 4643 4644 /* restore original mask */ 4645 intr->mask = intr->mask_original; 4646 intr->mask_original = 0; 4647 4648 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr); 4649 ixgbe_enable_intr(dev); 4650 rte_intr_ack(intr_handle); 4651 } 4652 4653 /** 4654 * Interrupt handler triggered by NIC for handling 4655 * specific interrupt. 4656 * 4657 * @param handle 4658 * Pointer to interrupt handle. 4659 * @param param 4660 * The address of parameter (struct rte_eth_dev *) regsitered before. 4661 * 4662 * @return 4663 * void 4664 */ 4665 static void 4666 ixgbe_dev_interrupt_handler(void *param) 4667 { 4668 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4669 4670 ixgbe_dev_interrupt_get_status(dev); 4671 ixgbe_dev_interrupt_action(dev); 4672 } 4673 4674 static int 4675 ixgbe_dev_led_on(struct rte_eth_dev *dev) 4676 { 4677 struct ixgbe_hw *hw; 4678 4679 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4680 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4681 } 4682 4683 static int 4684 ixgbe_dev_led_off(struct rte_eth_dev *dev) 4685 { 4686 struct ixgbe_hw *hw; 4687 4688 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4689 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4690 } 4691 4692 static int 4693 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4694 { 4695 struct ixgbe_hw *hw; 4696 uint32_t mflcn_reg; 4697 uint32_t fccfg_reg; 4698 int rx_pause; 4699 int tx_pause; 4700 4701 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4702 4703 fc_conf->pause_time = hw->fc.pause_time; 4704 fc_conf->high_water = hw->fc.high_water[0]; 4705 fc_conf->low_water = hw->fc.low_water[0]; 4706 fc_conf->send_xon = hw->fc.send_xon; 4707 fc_conf->autoneg = !hw->fc.disable_fc_autoneg; 4708 4709 /* 4710 * Return rx_pause status according to actual setting of 4711 * MFLCN register. 4712 */ 4713 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4714 if (mflcn_reg & IXGBE_MFLCN_PMCF) 4715 fc_conf->mac_ctrl_frame_fwd = 1; 4716 else 4717 fc_conf->mac_ctrl_frame_fwd = 0; 4718 4719 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE)) 4720 rx_pause = 1; 4721 else 4722 rx_pause = 0; 4723 4724 /* 4725 * Return tx_pause status according to actual setting of 4726 * FCCFG register. 4727 */ 4728 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4729 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY)) 4730 tx_pause = 1; 4731 else 4732 tx_pause = 0; 4733 4734 if (rx_pause && tx_pause) 4735 fc_conf->mode = RTE_FC_FULL; 4736 else if (rx_pause) 4737 fc_conf->mode = RTE_FC_RX_PAUSE; 4738 else if (tx_pause) 4739 fc_conf->mode = RTE_FC_TX_PAUSE; 4740 else 4741 fc_conf->mode = RTE_FC_NONE; 4742 4743 return 0; 4744 } 4745 4746 static int 4747 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4748 { 4749 struct ixgbe_hw *hw; 4750 struct ixgbe_adapter *adapter = dev->data->dev_private; 4751 int err; 4752 uint32_t rx_buf_size; 4753 uint32_t max_high_water; 4754 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4755 ixgbe_fc_none, 4756 ixgbe_fc_rx_pause, 4757 ixgbe_fc_tx_pause, 4758 ixgbe_fc_full 4759 }; 4760 4761 PMD_INIT_FUNC_TRACE(); 4762 4763 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4764 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)); 4765 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4766 4767 /* 4768 * At least reserve one Ethernet frame for watermark 4769 * high_water/low_water in kilo bytes for ixgbe 4770 */ 4771 max_high_water = (rx_buf_size - 4772 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4773 if ((fc_conf->high_water > max_high_water) || 4774 (fc_conf->high_water < fc_conf->low_water)) { 4775 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4776 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4777 return -EINVAL; 4778 } 4779 4780 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode]; 4781 hw->fc.pause_time = fc_conf->pause_time; 4782 hw->fc.high_water[0] = fc_conf->high_water; 4783 hw->fc.low_water[0] = fc_conf->low_water; 4784 hw->fc.send_xon = fc_conf->send_xon; 4785 hw->fc.disable_fc_autoneg = !fc_conf->autoneg; 4786 adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; 4787 4788 err = ixgbe_flow_ctrl_enable(dev, hw); 4789 if (err < 0) { 4790 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err); 4791 return -EIO; 4792 } 4793 return err; 4794 } 4795 4796 /** 4797 * ixgbe_pfc_enable_generic - Enable flow control 4798 * @hw: pointer to hardware structure 4799 * @tc_num: traffic class number 4800 * Enable flow control according to the current settings. 4801 */ 4802 static int 4803 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num) 4804 { 4805 int ret_val = 0; 4806 uint32_t mflcn_reg, fccfg_reg; 4807 uint32_t reg; 4808 uint32_t fcrtl, fcrth; 4809 uint8_t i; 4810 uint8_t nb_rx_en; 4811 4812 /* Validate the water mark configuration */ 4813 if (!hw->fc.pause_time) { 4814 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4815 goto out; 4816 } 4817 4818 /* Low water mark of zero causes XOFF floods */ 4819 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 4820 /* High/Low water can not be 0 */ 4821 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) { 4822 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4823 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4824 goto out; 4825 } 4826 4827 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) { 4828 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4829 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4830 goto out; 4831 } 4832 } 4833 /* Negotiate the fc mode to use */ 4834 ixgbe_fc_autoneg(hw); 4835 4836 /* Disable any previous flow control settings */ 4837 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4838 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE); 4839 4840 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4841 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 4842 4843 switch (hw->fc.current_mode) { 4844 case ixgbe_fc_none: 4845 /* 4846 * If the count of enabled RX Priority Flow control >1, 4847 * and the TX pause can not be disabled 4848 */ 4849 nb_rx_en = 0; 4850 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4851 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4852 if (reg & IXGBE_FCRTH_FCEN) 4853 nb_rx_en++; 4854 } 4855 if (nb_rx_en > 1) 4856 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4857 break; 4858 case ixgbe_fc_rx_pause: 4859 /* 4860 * Rx Flow control is enabled and Tx Flow control is 4861 * disabled by software override. Since there really 4862 * isn't a way to advertise that we are capable of RX 4863 * Pause ONLY, we will advertise that we support both 4864 * symmetric and asymmetric Rx PAUSE. Later, we will 4865 * disable the adapter's ability to send PAUSE frames. 4866 */ 4867 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4868 /* 4869 * If the count of enabled RX Priority Flow control >1, 4870 * and the TX pause can not be disabled 4871 */ 4872 nb_rx_en = 0; 4873 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4874 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4875 if (reg & IXGBE_FCRTH_FCEN) 4876 nb_rx_en++; 4877 } 4878 if (nb_rx_en > 1) 4879 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4880 break; 4881 case ixgbe_fc_tx_pause: 4882 /* 4883 * Tx Flow control is enabled, and Rx Flow control is 4884 * disabled by software override. 4885 */ 4886 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4887 break; 4888 case ixgbe_fc_full: 4889 /* Flow control (both Rx and Tx) is enabled by SW override. */ 4890 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4891 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4892 break; 4893 default: 4894 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly"); 4895 ret_val = IXGBE_ERR_CONFIG; 4896 goto out; 4897 } 4898 4899 /* Set 802.3x based flow control settings. */ 4900 mflcn_reg |= IXGBE_MFLCN_DPF; 4901 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 4902 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 4903 4904 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 4905 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 4906 hw->fc.high_water[tc_num]) { 4907 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE; 4908 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl); 4909 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN; 4910 } else { 4911 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0); 4912 /* 4913 * In order to prevent Tx hangs when the internal Tx 4914 * switch is enabled we must set the high water mark 4915 * to the maximum FCRTH value. This allows the Tx 4916 * switch to function even under heavy Rx workloads. 4917 */ 4918 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32; 4919 } 4920 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth); 4921 4922 /* Configure pause time (2 TCs per register) */ 4923 reg = hw->fc.pause_time * 0x00010001; 4924 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 4925 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 4926 4927 /* Configure flow control refresh threshold value */ 4928 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 4929 4930 out: 4931 return ret_val; 4932 } 4933 4934 static int 4935 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num) 4936 { 4937 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4938 int32_t ret_val = IXGBE_NOT_IMPLEMENTED; 4939 4940 if (hw->mac.type != ixgbe_mac_82598EB) { 4941 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num); 4942 } 4943 return ret_val; 4944 } 4945 4946 static int 4947 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf) 4948 { 4949 int err; 4950 uint32_t rx_buf_size; 4951 uint32_t max_high_water; 4952 uint8_t tc_num; 4953 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 4954 struct ixgbe_hw *hw = 4955 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4956 struct ixgbe_dcb_config *dcb_config = 4957 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 4958 4959 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4960 ixgbe_fc_none, 4961 ixgbe_fc_rx_pause, 4962 ixgbe_fc_tx_pause, 4963 ixgbe_fc_full 4964 }; 4965 4966 PMD_INIT_FUNC_TRACE(); 4967 4968 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map); 4969 tc_num = map[pfc_conf->priority]; 4970 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)); 4971 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4972 /* 4973 * At least reserve one Ethernet frame for watermark 4974 * high_water/low_water in kilo bytes for ixgbe 4975 */ 4976 max_high_water = (rx_buf_size - 4977 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4978 if ((pfc_conf->fc.high_water > max_high_water) || 4979 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) { 4980 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4981 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4982 return -EINVAL; 4983 } 4984 4985 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode]; 4986 hw->fc.pause_time = pfc_conf->fc.pause_time; 4987 hw->fc.send_xon = pfc_conf->fc.send_xon; 4988 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water; 4989 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; 4990 4991 err = ixgbe_dcb_pfc_enable(dev, tc_num); 4992 4993 /* Not negotiated is not an error case */ 4994 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) 4995 return 0; 4996 4997 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err); 4998 return -EIO; 4999 } 5000 5001 static int 5002 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 5003 struct rte_eth_rss_reta_entry64 *reta_conf, 5004 uint16_t reta_size) 5005 { 5006 uint16_t i, sp_reta_size; 5007 uint8_t j, mask; 5008 uint32_t reta, r; 5009 uint16_t idx, shift; 5010 struct ixgbe_adapter *adapter = dev->data->dev_private; 5011 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5012 uint32_t reta_reg; 5013 5014 PMD_INIT_FUNC_TRACE(); 5015 5016 if (!ixgbe_rss_update_sp(hw->mac.type)) { 5017 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " 5018 "NIC."); 5019 return -ENOTSUP; 5020 } 5021 5022 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 5023 if (reta_size != sp_reta_size) { 5024 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 5025 "(%d) doesn't match the number hardware can supported " 5026 "(%d)", reta_size, sp_reta_size); 5027 return -EINVAL; 5028 } 5029 5030 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 5031 idx = i / RTE_RETA_GROUP_SIZE; 5032 shift = i % RTE_RETA_GROUP_SIZE; 5033 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 5034 IXGBE_4_BIT_MASK); 5035 if (!mask) 5036 continue; 5037 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 5038 if (mask == IXGBE_4_BIT_MASK) 5039 r = 0; 5040 else 5041 r = IXGBE_READ_REG(hw, reta_reg); 5042 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) { 5043 if (mask & (0x1 << j)) 5044 reta |= reta_conf[idx].reta[shift + j] << 5045 (CHAR_BIT * j); 5046 else 5047 reta |= r & (IXGBE_8_BIT_MASK << 5048 (CHAR_BIT * j)); 5049 } 5050 IXGBE_WRITE_REG(hw, reta_reg, reta); 5051 } 5052 adapter->rss_reta_updated = 1; 5053 5054 return 0; 5055 } 5056 5057 static int 5058 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 5059 struct rte_eth_rss_reta_entry64 *reta_conf, 5060 uint16_t reta_size) 5061 { 5062 uint16_t i, sp_reta_size; 5063 uint8_t j, mask; 5064 uint32_t reta; 5065 uint16_t idx, shift; 5066 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5067 uint32_t reta_reg; 5068 5069 PMD_INIT_FUNC_TRACE(); 5070 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 5071 if (reta_size != sp_reta_size) { 5072 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 5073 "(%d) doesn't match the number hardware can supported " 5074 "(%d)", reta_size, sp_reta_size); 5075 return -EINVAL; 5076 } 5077 5078 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 5079 idx = i / RTE_RETA_GROUP_SIZE; 5080 shift = i % RTE_RETA_GROUP_SIZE; 5081 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 5082 IXGBE_4_BIT_MASK); 5083 if (!mask) 5084 continue; 5085 5086 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 5087 reta = IXGBE_READ_REG(hw, reta_reg); 5088 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) { 5089 if (mask & (0x1 << j)) 5090 reta_conf[idx].reta[shift + j] = 5091 ((reta >> (CHAR_BIT * j)) & 5092 IXGBE_8_BIT_MASK); 5093 } 5094 } 5095 5096 return 0; 5097 } 5098 5099 static int 5100 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 5101 uint32_t index, uint32_t pool) 5102 { 5103 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5104 uint32_t enable_addr = 1; 5105 5106 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes, 5107 pool, enable_addr); 5108 } 5109 5110 static void 5111 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) 5112 { 5113 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5114 5115 ixgbe_clear_rar(hw, index); 5116 } 5117 5118 static int 5119 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 5120 { 5121 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5122 5123 ixgbe_remove_rar(dev, 0); 5124 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs); 5125 5126 return 0; 5127 } 5128 5129 static bool 5130 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 5131 { 5132 if (strcmp(dev->device->driver->name, drv->driver.name)) 5133 return false; 5134 5135 return true; 5136 } 5137 5138 bool 5139 is_ixgbe_supported(struct rte_eth_dev *dev) 5140 { 5141 return is_device_supported(dev, &rte_ixgbe_pmd); 5142 } 5143 5144 static int 5145 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 5146 { 5147 uint32_t hlreg0; 5148 uint32_t maxfrs; 5149 struct ixgbe_hw *hw; 5150 struct rte_eth_dev_info dev_info; 5151 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD; 5152 struct rte_eth_dev_data *dev_data = dev->data; 5153 int ret; 5154 5155 ret = ixgbe_dev_info_get(dev, &dev_info); 5156 if (ret != 0) 5157 return ret; 5158 5159 /* check that mtu is within the allowed range */ 5160 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) 5161 return -EINVAL; 5162 5163 /* If device is started, refuse mtu that requires the support of 5164 * scattered packets when this feature has not been enabled before. 5165 */ 5166 if (dev_data->dev_started && !dev_data->scattered_rx && 5167 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE > 5168 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 5169 PMD_INIT_LOG(ERR, "Stop port first."); 5170 return -EINVAL; 5171 } 5172 5173 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5174 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 5175 5176 /* switch to jumbo mode if needed */ 5177 if (frame_size > IXGBE_ETH_MAX_LEN) { 5178 dev->data->dev_conf.rxmode.offloads |= 5179 DEV_RX_OFFLOAD_JUMBO_FRAME; 5180 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 5181 } else { 5182 dev->data->dev_conf.rxmode.offloads &= 5183 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 5184 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; 5185 } 5186 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 5187 5188 /* update max frame size */ 5189 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 5190 5191 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS); 5192 maxfrs &= 0x0000FFFF; 5193 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16); 5194 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs); 5195 5196 return 0; 5197 } 5198 5199 /* 5200 * Virtual Function operations 5201 */ 5202 static void 5203 ixgbevf_intr_disable(struct rte_eth_dev *dev) 5204 { 5205 struct ixgbe_interrupt *intr = 5206 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5207 struct ixgbe_hw *hw = 5208 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5209 5210 PMD_INIT_FUNC_TRACE(); 5211 5212 /* Clear interrupt mask to stop from interrupts being generated */ 5213 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK); 5214 5215 IXGBE_WRITE_FLUSH(hw); 5216 5217 /* Clear mask value. */ 5218 intr->mask = 0; 5219 } 5220 5221 static void 5222 ixgbevf_intr_enable(struct rte_eth_dev *dev) 5223 { 5224 struct ixgbe_interrupt *intr = 5225 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5226 struct ixgbe_hw *hw = 5227 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5228 5229 PMD_INIT_FUNC_TRACE(); 5230 5231 /* VF enable interrupt autoclean */ 5232 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK); 5233 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK); 5234 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK); 5235 5236 IXGBE_WRITE_FLUSH(hw); 5237 5238 /* Save IXGBE_VTEIMS value to mask. */ 5239 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK; 5240 } 5241 5242 static int 5243 ixgbevf_dev_configure(struct rte_eth_dev *dev) 5244 { 5245 struct rte_eth_conf *conf = &dev->data->dev_conf; 5246 struct ixgbe_adapter *adapter = dev->data->dev_private; 5247 5248 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d", 5249 dev->data->port_id); 5250 5251 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 5252 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 5253 5254 /* 5255 * VF has no ability to enable/disable HW CRC 5256 * Keep the persistent behavior the same as Host PF 5257 */ 5258 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC 5259 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) { 5260 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip"); 5261 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC; 5262 } 5263 #else 5264 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) { 5265 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip"); 5266 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC; 5267 } 5268 #endif 5269 5270 /* 5271 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 5272 * allocation or vector Rx preconditions we will reset it. 5273 */ 5274 adapter->rx_bulk_alloc_allowed = true; 5275 adapter->rx_vec_allowed = true; 5276 5277 return 0; 5278 } 5279 5280 static int 5281 ixgbevf_dev_start(struct rte_eth_dev *dev) 5282 { 5283 struct ixgbe_hw *hw = 5284 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5285 uint32_t intr_vector = 0; 5286 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5287 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5288 5289 int err, mask = 0; 5290 5291 PMD_INIT_FUNC_TRACE(); 5292 5293 /* Stop the link setup handler before resetting the HW. */ 5294 ixgbe_dev_wait_setup_link_complete(dev, 0); 5295 5296 err = hw->mac.ops.reset_hw(hw); 5297 5298 /** 5299 * In this case, reuses the MAC address assigned by VF 5300 * initialization. 5301 */ 5302 if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) { 5303 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err); 5304 return err; 5305 } 5306 5307 hw->mac.get_link_status = true; 5308 5309 /* negotiate mailbox API version to use with the PF. */ 5310 ixgbevf_negotiate_api(hw); 5311 5312 ixgbevf_dev_tx_init(dev); 5313 5314 /* This can fail when allocating mbufs for descriptor rings */ 5315 err = ixgbevf_dev_rx_init(dev); 5316 if (err) { 5317 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err); 5318 ixgbe_dev_clear_queues(dev); 5319 return err; 5320 } 5321 5322 /* Set vfta */ 5323 ixgbevf_set_vfta_all(dev, 1); 5324 5325 /* Set HW strip */ 5326 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 5327 ETH_VLAN_EXTEND_MASK; 5328 err = ixgbevf_vlan_offload_config(dev, mask); 5329 if (err) { 5330 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err); 5331 ixgbe_dev_clear_queues(dev); 5332 return err; 5333 } 5334 5335 ixgbevf_dev_rxtx_start(dev); 5336 5337 /* check and configure queue intr-vector mapping */ 5338 if (rte_intr_cap_multiple(intr_handle) && 5339 dev->data->dev_conf.intr_conf.rxq) { 5340 /* According to datasheet, only vector 0/1/2 can be used, 5341 * now only one vector is used for Rx queue 5342 */ 5343 intr_vector = 1; 5344 if (rte_intr_efd_enable(intr_handle, intr_vector)) 5345 return -1; 5346 } 5347 5348 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 5349 intr_handle->intr_vec = 5350 rte_zmalloc("intr_vec", 5351 dev->data->nb_rx_queues * sizeof(int), 0); 5352 if (intr_handle->intr_vec == NULL) { 5353 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 5354 " intr_vec", dev->data->nb_rx_queues); 5355 return -ENOMEM; 5356 } 5357 } 5358 ixgbevf_configure_msix(dev); 5359 5360 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt 5361 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ). 5362 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( ) 5363 * is not cleared, it will fail when following rte_intr_enable( ) tries 5364 * to map Rx queue interrupt to other VFIO vectors. 5365 * So clear uio/vfio intr/evevnfd first to avoid failure. 5366 */ 5367 rte_intr_disable(intr_handle); 5368 5369 rte_intr_enable(intr_handle); 5370 5371 /* Re-enable interrupt for VF */ 5372 ixgbevf_intr_enable(dev); 5373 5374 /* 5375 * Update link status right before return, because it may 5376 * start link configuration process in a separate thread. 5377 */ 5378 ixgbevf_dev_link_update(dev, 0); 5379 5380 hw->adapter_stopped = false; 5381 5382 return 0; 5383 } 5384 5385 static int 5386 ixgbevf_dev_stop(struct rte_eth_dev *dev) 5387 { 5388 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5389 struct ixgbe_adapter *adapter = dev->data->dev_private; 5390 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5391 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5392 5393 if (hw->adapter_stopped) 5394 return 0; 5395 5396 PMD_INIT_FUNC_TRACE(); 5397 5398 ixgbe_dev_wait_setup_link_complete(dev, 0); 5399 5400 ixgbevf_intr_disable(dev); 5401 5402 dev->data->dev_started = 0; 5403 hw->adapter_stopped = 1; 5404 ixgbe_stop_adapter(hw); 5405 5406 /* 5407 * Clear what we set, but we still keep shadow_vfta to 5408 * restore after device starts 5409 */ 5410 ixgbevf_set_vfta_all(dev, 0); 5411 5412 /* Clear stored conf */ 5413 dev->data->scattered_rx = 0; 5414 5415 ixgbe_dev_clear_queues(dev); 5416 5417 /* Clean datapath event and queue/vec mapping */ 5418 rte_intr_efd_disable(intr_handle); 5419 if (intr_handle->intr_vec != NULL) { 5420 rte_free(intr_handle->intr_vec); 5421 intr_handle->intr_vec = NULL; 5422 } 5423 5424 adapter->rss_reta_updated = 0; 5425 5426 return 0; 5427 } 5428 5429 static int 5430 ixgbevf_dev_close(struct rte_eth_dev *dev) 5431 { 5432 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5433 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5434 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5435 int ret; 5436 5437 PMD_INIT_FUNC_TRACE(); 5438 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5439 return 0; 5440 5441 ixgbe_reset_hw(hw); 5442 5443 ret = ixgbevf_dev_stop(dev); 5444 5445 ixgbe_dev_free_queues(dev); 5446 5447 /** 5448 * Remove the VF MAC address ro ensure 5449 * that the VF traffic goes to the PF 5450 * after stop, close and detach of the VF 5451 **/ 5452 ixgbevf_remove_mac_addr(dev, 0); 5453 5454 rte_intr_disable(intr_handle); 5455 rte_intr_callback_unregister(intr_handle, 5456 ixgbevf_dev_interrupt_handler, dev); 5457 5458 return ret; 5459 } 5460 5461 /* 5462 * Reset VF device 5463 */ 5464 static int 5465 ixgbevf_dev_reset(struct rte_eth_dev *dev) 5466 { 5467 int ret; 5468 5469 ret = eth_ixgbevf_dev_uninit(dev); 5470 if (ret) 5471 return ret; 5472 5473 ret = eth_ixgbevf_dev_init(dev); 5474 5475 return ret; 5476 } 5477 5478 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) 5479 { 5480 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5481 struct ixgbe_vfta *shadow_vfta = 5482 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5483 int i = 0, j = 0, vfta = 0, mask = 1; 5484 5485 for (i = 0; i < IXGBE_VFTA_SIZE; i++) { 5486 vfta = shadow_vfta->vfta[i]; 5487 if (vfta) { 5488 mask = 1; 5489 for (j = 0; j < 32; j++) { 5490 if (vfta & mask) 5491 ixgbe_set_vfta(hw, (i<<5)+j, 0, 5492 on, false); 5493 mask <<= 1; 5494 } 5495 } 5496 } 5497 5498 } 5499 5500 static int 5501 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 5502 { 5503 struct ixgbe_hw *hw = 5504 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5505 struct ixgbe_vfta *shadow_vfta = 5506 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5507 uint32_t vid_idx = 0; 5508 uint32_t vid_bit = 0; 5509 int ret = 0; 5510 5511 PMD_INIT_FUNC_TRACE(); 5512 5513 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */ 5514 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false); 5515 if (ret) { 5516 PMD_INIT_LOG(ERR, "Unable to set VF vlan"); 5517 return ret; 5518 } 5519 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 5520 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 5521 5522 /* Save what we set and retore it after device reset */ 5523 if (on) 5524 shadow_vfta->vfta[vid_idx] |= vid_bit; 5525 else 5526 shadow_vfta->vfta[vid_idx] &= ~vid_bit; 5527 5528 return 0; 5529 } 5530 5531 static void 5532 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 5533 { 5534 struct ixgbe_hw *hw = 5535 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5536 uint32_t ctrl; 5537 5538 PMD_INIT_FUNC_TRACE(); 5539 5540 if (queue >= hw->mac.max_rx_queues) 5541 return; 5542 5543 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 5544 if (on) 5545 ctrl |= IXGBE_RXDCTL_VME; 5546 else 5547 ctrl &= ~IXGBE_RXDCTL_VME; 5548 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 5549 5550 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on); 5551 } 5552 5553 static int 5554 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask) 5555 { 5556 struct ixgbe_rx_queue *rxq; 5557 uint16_t i; 5558 int on = 0; 5559 5560 /* VF function only support hw strip feature, others are not support */ 5561 if (mask & ETH_VLAN_STRIP_MASK) { 5562 for (i = 0; i < dev->data->nb_rx_queues; i++) { 5563 rxq = dev->data->rx_queues[i]; 5564 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP); 5565 ixgbevf_vlan_strip_queue_set(dev, i, on); 5566 } 5567 } 5568 5569 return 0; 5570 } 5571 5572 static int 5573 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 5574 { 5575 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 5576 5577 ixgbevf_vlan_offload_config(dev, mask); 5578 5579 return 0; 5580 } 5581 5582 int 5583 ixgbe_vt_check(struct ixgbe_hw *hw) 5584 { 5585 uint32_t reg_val; 5586 5587 /* if Virtualization Technology is enabled */ 5588 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 5589 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) { 5590 PMD_INIT_LOG(ERR, "VT must be enabled for this setting"); 5591 return -1; 5592 } 5593 5594 return 0; 5595 } 5596 5597 static uint32_t 5598 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr) 5599 { 5600 uint32_t vector = 0; 5601 5602 switch (hw->mac.mc_filter_type) { 5603 case 0: /* use bits [47:36] of the address */ 5604 vector = ((uc_addr->addr_bytes[4] >> 4) | 5605 (((uint16_t)uc_addr->addr_bytes[5]) << 4)); 5606 break; 5607 case 1: /* use bits [46:35] of the address */ 5608 vector = ((uc_addr->addr_bytes[4] >> 3) | 5609 (((uint16_t)uc_addr->addr_bytes[5]) << 5)); 5610 break; 5611 case 2: /* use bits [45:34] of the address */ 5612 vector = ((uc_addr->addr_bytes[4] >> 2) | 5613 (((uint16_t)uc_addr->addr_bytes[5]) << 6)); 5614 break; 5615 case 3: /* use bits [43:32] of the address */ 5616 vector = ((uc_addr->addr_bytes[4]) | 5617 (((uint16_t)uc_addr->addr_bytes[5]) << 8)); 5618 break; 5619 default: /* Invalid mc_filter_type */ 5620 break; 5621 } 5622 5623 /* vector can only be 12-bits or boundary will be exceeded */ 5624 vector &= 0xFFF; 5625 return vector; 5626 } 5627 5628 static int 5629 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, 5630 struct rte_ether_addr *mac_addr, uint8_t on) 5631 { 5632 uint32_t vector; 5633 uint32_t uta_idx; 5634 uint32_t reg_val; 5635 uint32_t uta_shift; 5636 uint32_t rc; 5637 const uint32_t ixgbe_uta_idx_mask = 0x7F; 5638 const uint32_t ixgbe_uta_bit_shift = 5; 5639 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1; 5640 const uint32_t bit1 = 0x1; 5641 5642 struct ixgbe_hw *hw = 5643 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5644 struct ixgbe_uta_info *uta_info = 5645 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5646 5647 /* The UTA table only exists on 82599 hardware and newer */ 5648 if (hw->mac.type < ixgbe_mac_82599EB) 5649 return -ENOTSUP; 5650 5651 vector = ixgbe_uta_vector(hw, mac_addr); 5652 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask; 5653 uta_shift = vector & ixgbe_uta_bit_mask; 5654 5655 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0); 5656 if (rc == on) 5657 return 0; 5658 5659 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx)); 5660 if (on) { 5661 uta_info->uta_in_use++; 5662 reg_val |= (bit1 << uta_shift); 5663 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift); 5664 } else { 5665 uta_info->uta_in_use--; 5666 reg_val &= ~(bit1 << uta_shift); 5667 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift); 5668 } 5669 5670 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val); 5671 5672 if (uta_info->uta_in_use > 0) 5673 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 5674 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 5675 else 5676 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 5677 5678 return 0; 5679 } 5680 5681 static int 5682 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) 5683 { 5684 int i; 5685 struct ixgbe_hw *hw = 5686 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5687 struct ixgbe_uta_info *uta_info = 5688 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5689 5690 /* The UTA table only exists on 82599 hardware and newer */ 5691 if (hw->mac.type < ixgbe_mac_82599EB) 5692 return -ENOTSUP; 5693 5694 if (on) { 5695 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5696 uta_info->uta_shadow[i] = ~0; 5697 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); 5698 } 5699 } else { 5700 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5701 uta_info->uta_shadow[i] = 0; 5702 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 5703 } 5704 } 5705 return 0; 5706 5707 } 5708 5709 uint32_t 5710 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val) 5711 { 5712 uint32_t new_val = orig_val; 5713 5714 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG) 5715 new_val |= IXGBE_VMOLR_AUPE; 5716 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC) 5717 new_val |= IXGBE_VMOLR_ROMPE; 5718 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC) 5719 new_val |= IXGBE_VMOLR_ROPE; 5720 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST) 5721 new_val |= IXGBE_VMOLR_BAM; 5722 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST) 5723 new_val |= IXGBE_VMOLR_MPE; 5724 5725 return new_val; 5726 } 5727 5728 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */ 5729 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */ 5730 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */ 5731 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */ 5732 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \ 5733 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \ 5734 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN)) 5735 5736 static int 5737 ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 5738 struct rte_eth_mirror_conf *mirror_conf, 5739 uint8_t rule_id, uint8_t on) 5740 { 5741 uint32_t mr_ctl, vlvf; 5742 uint32_t mp_lsb = 0; 5743 uint32_t mv_msb = 0; 5744 uint32_t mv_lsb = 0; 5745 uint32_t mp_msb = 0; 5746 uint8_t i = 0; 5747 int reg_index = 0; 5748 uint64_t vlan_mask = 0; 5749 5750 const uint8_t pool_mask_offset = 32; 5751 const uint8_t vlan_mask_offset = 32; 5752 const uint8_t dst_pool_offset = 8; 5753 const uint8_t rule_mr_offset = 4; 5754 const uint8_t mirror_rule_mask = 0x0F; 5755 5756 struct ixgbe_mirror_info *mr_info = 5757 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5758 struct ixgbe_hw *hw = 5759 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5760 uint8_t mirror_type = 0; 5761 5762 if (ixgbe_vt_check(hw) < 0) 5763 return -ENOTSUP; 5764 5765 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5766 return -EINVAL; 5767 5768 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) { 5769 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.", 5770 mirror_conf->rule_type); 5771 return -EINVAL; 5772 } 5773 5774 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5775 mirror_type |= IXGBE_MRCTL_VLME; 5776 /* Check if vlan id is valid and find conresponding VLAN ID 5777 * index in VLVF 5778 */ 5779 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) { 5780 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) { 5781 /* search vlan id related pool vlan filter 5782 * index 5783 */ 5784 reg_index = ixgbe_find_vlvf_slot( 5785 hw, 5786 mirror_conf->vlan.vlan_id[i], 5787 false); 5788 if (reg_index < 0) 5789 return -EINVAL; 5790 vlvf = IXGBE_READ_REG(hw, 5791 IXGBE_VLVF(reg_index)); 5792 if ((vlvf & IXGBE_VLVF_VIEN) && 5793 ((vlvf & IXGBE_VLVF_VLANID_MASK) == 5794 mirror_conf->vlan.vlan_id[i])) 5795 vlan_mask |= (1ULL << reg_index); 5796 else 5797 return -EINVAL; 5798 } 5799 } 5800 5801 if (on) { 5802 mv_lsb = vlan_mask & 0xFFFFFFFF; 5803 mv_msb = vlan_mask >> vlan_mask_offset; 5804 5805 mr_info->mr_conf[rule_id].vlan.vlan_mask = 5806 mirror_conf->vlan.vlan_mask; 5807 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) { 5808 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) 5809 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 5810 mirror_conf->vlan.vlan_id[i]; 5811 } 5812 } else { 5813 mv_lsb = 0; 5814 mv_msb = 0; 5815 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0; 5816 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) 5817 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0; 5818 } 5819 } 5820 5821 /** 5822 * if enable pool mirror, write related pool mask register,if disable 5823 * pool mirror, clear PFMRVM register 5824 */ 5825 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5826 mirror_type |= IXGBE_MRCTL_VPME; 5827 if (on) { 5828 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF; 5829 mp_msb = mirror_conf->pool_mask >> pool_mask_offset; 5830 mr_info->mr_conf[rule_id].pool_mask = 5831 mirror_conf->pool_mask; 5832 5833 } else { 5834 mp_lsb = 0; 5835 mp_msb = 0; 5836 mr_info->mr_conf[rule_id].pool_mask = 0; 5837 } 5838 } 5839 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT) 5840 mirror_type |= IXGBE_MRCTL_UPME; 5841 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT) 5842 mirror_type |= IXGBE_MRCTL_DPME; 5843 5844 /* read mirror control register and recalculate it */ 5845 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id)); 5846 5847 if (on) { 5848 mr_ctl |= mirror_type; 5849 mr_ctl &= mirror_rule_mask; 5850 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset; 5851 } else { 5852 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask); 5853 } 5854 5855 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type; 5856 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool; 5857 5858 /* write mirrror control register */ 5859 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5860 5861 /* write pool mirrror control register */ 5862 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5863 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb); 5864 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), 5865 mp_msb); 5866 } 5867 /* write VLAN mirrror control register */ 5868 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5869 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb); 5870 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), 5871 mv_msb); 5872 } 5873 5874 return 0; 5875 } 5876 5877 static int 5878 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id) 5879 { 5880 int mr_ctl = 0; 5881 uint32_t lsb_val = 0; 5882 uint32_t msb_val = 0; 5883 const uint8_t rule_mr_offset = 4; 5884 5885 struct ixgbe_hw *hw = 5886 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5887 struct ixgbe_mirror_info *mr_info = 5888 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5889 5890 if (ixgbe_vt_check(hw) < 0) 5891 return -ENOTSUP; 5892 5893 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5894 return -EINVAL; 5895 5896 memset(&mr_info->mr_conf[rule_id], 0, 5897 sizeof(struct rte_eth_mirror_conf)); 5898 5899 /* clear PFVMCTL register */ 5900 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5901 5902 /* clear pool mask register */ 5903 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val); 5904 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val); 5905 5906 /* clear vlan mask register */ 5907 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val); 5908 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val); 5909 5910 return 0; 5911 } 5912 5913 static int 5914 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5915 { 5916 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5917 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5918 struct ixgbe_interrupt *intr = 5919 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5920 struct ixgbe_hw *hw = 5921 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5922 uint32_t vec = IXGBE_MISC_VEC_ID; 5923 5924 if (rte_intr_allow_others(intr_handle)) 5925 vec = IXGBE_RX_VEC_START; 5926 intr->mask |= (1 << vec); 5927 RTE_SET_USED(queue_id); 5928 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5929 5930 rte_intr_ack(intr_handle); 5931 5932 return 0; 5933 } 5934 5935 static int 5936 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5937 { 5938 struct ixgbe_interrupt *intr = 5939 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5940 struct ixgbe_hw *hw = 5941 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5942 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5943 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5944 uint32_t vec = IXGBE_MISC_VEC_ID; 5945 5946 if (rte_intr_allow_others(intr_handle)) 5947 vec = IXGBE_RX_VEC_START; 5948 intr->mask &= ~(1 << vec); 5949 RTE_SET_USED(queue_id); 5950 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5951 5952 return 0; 5953 } 5954 5955 static int 5956 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5957 { 5958 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5959 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5960 uint32_t mask; 5961 struct ixgbe_hw *hw = 5962 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5963 struct ixgbe_interrupt *intr = 5964 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5965 5966 if (queue_id < 16) { 5967 ixgbe_disable_intr(hw); 5968 intr->mask |= (1 << queue_id); 5969 ixgbe_enable_intr(dev); 5970 } else if (queue_id < 32) { 5971 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5972 mask &= (1 << queue_id); 5973 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5974 } else if (queue_id < 64) { 5975 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5976 mask &= (1 << (queue_id - 32)); 5977 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5978 } 5979 rte_intr_ack(intr_handle); 5980 5981 return 0; 5982 } 5983 5984 static int 5985 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5986 { 5987 uint32_t mask; 5988 struct ixgbe_hw *hw = 5989 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5990 struct ixgbe_interrupt *intr = 5991 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5992 5993 if (queue_id < 16) { 5994 ixgbe_disable_intr(hw); 5995 intr->mask &= ~(1 << queue_id); 5996 ixgbe_enable_intr(dev); 5997 } else if (queue_id < 32) { 5998 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5999 mask &= ~(1 << queue_id); 6000 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 6001 } else if (queue_id < 64) { 6002 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 6003 mask &= ~(1 << (queue_id - 32)); 6004 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 6005 } 6006 6007 return 0; 6008 } 6009 6010 static void 6011 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 6012 uint8_t queue, uint8_t msix_vector) 6013 { 6014 uint32_t tmp, idx; 6015 6016 if (direction == -1) { 6017 /* other causes */ 6018 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 6019 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC); 6020 tmp &= ~0xFF; 6021 tmp |= msix_vector; 6022 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp); 6023 } else { 6024 /* rx or tx cause */ 6025 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 6026 idx = ((16 * (queue & 1)) + (8 * direction)); 6027 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1)); 6028 tmp &= ~(0xFF << idx); 6029 tmp |= (msix_vector << idx); 6030 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp); 6031 } 6032 } 6033 6034 /** 6035 * set the IVAR registers, mapping interrupt causes to vectors 6036 * @param hw 6037 * pointer to ixgbe_hw struct 6038 * @direction 6039 * 0 for Rx, 1 for Tx, -1 for other causes 6040 * @queue 6041 * queue to map the corresponding interrupt to 6042 * @msix_vector 6043 * the vector to map to the corresponding queue 6044 */ 6045 static void 6046 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 6047 uint8_t queue, uint8_t msix_vector) 6048 { 6049 uint32_t tmp, idx; 6050 6051 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 6052 if (hw->mac.type == ixgbe_mac_82598EB) { 6053 if (direction == -1) 6054 direction = 0; 6055 idx = (((direction * 64) + queue) >> 2) & 0x1F; 6056 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx)); 6057 tmp &= ~(0xFF << (8 * (queue & 0x3))); 6058 tmp |= (msix_vector << (8 * (queue & 0x3))); 6059 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp); 6060 } else if ((hw->mac.type == ixgbe_mac_82599EB) || 6061 (hw->mac.type == ixgbe_mac_X540) || 6062 (hw->mac.type == ixgbe_mac_X550) || 6063 (hw->mac.type == ixgbe_mac_X550EM_x)) { 6064 if (direction == -1) { 6065 /* other causes */ 6066 idx = ((queue & 1) * 8); 6067 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC); 6068 tmp &= ~(0xFF << idx); 6069 tmp |= (msix_vector << idx); 6070 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp); 6071 } else { 6072 /* rx or tx causes */ 6073 idx = ((16 * (queue & 1)) + (8 * direction)); 6074 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 6075 tmp &= ~(0xFF << idx); 6076 tmp |= (msix_vector << idx); 6077 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp); 6078 } 6079 } 6080 } 6081 6082 static void 6083 ixgbevf_configure_msix(struct rte_eth_dev *dev) 6084 { 6085 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 6086 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 6087 struct ixgbe_hw *hw = 6088 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6089 uint32_t q_idx; 6090 uint32_t vector_idx = IXGBE_MISC_VEC_ID; 6091 uint32_t base = IXGBE_MISC_VEC_ID; 6092 6093 /* Configure VF other cause ivar */ 6094 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx); 6095 6096 /* won't configure msix register if no mapping is done 6097 * between intr vector and event fd. 6098 */ 6099 if (!rte_intr_dp_is_en(intr_handle)) 6100 return; 6101 6102 if (rte_intr_allow_others(intr_handle)) { 6103 base = IXGBE_RX_VEC_START; 6104 vector_idx = IXGBE_RX_VEC_START; 6105 } 6106 6107 /* Configure all RX queues of VF */ 6108 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) { 6109 /* Force all queue use vector 0, 6110 * as IXGBE_VF_MAXMSIVECOTR = 1 6111 */ 6112 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx); 6113 intr_handle->intr_vec[q_idx] = vector_idx; 6114 if (vector_idx < base + intr_handle->nb_efd - 1) 6115 vector_idx++; 6116 } 6117 6118 /* As RX queue setting above show, all queues use the vector 0. 6119 * Set only the ITR value of IXGBE_MISC_VEC_ID. 6120 */ 6121 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID), 6122 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 6123 | IXGBE_EITR_CNT_WDIS); 6124 } 6125 6126 /** 6127 * Sets up the hardware to properly generate MSI-X interrupts 6128 * @hw 6129 * board private structure 6130 */ 6131 static void 6132 ixgbe_configure_msix(struct rte_eth_dev *dev) 6133 { 6134 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 6135 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 6136 struct ixgbe_hw *hw = 6137 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6138 uint32_t queue_id, base = IXGBE_MISC_VEC_ID; 6139 uint32_t vec = IXGBE_MISC_VEC_ID; 6140 uint32_t mask; 6141 uint32_t gpie; 6142 6143 /* won't configure msix register if no mapping is done 6144 * between intr vector and event fd 6145 * but if misx has been enabled already, need to configure 6146 * auto clean, auto mask and throttling. 6147 */ 6148 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 6149 if (!rte_intr_dp_is_en(intr_handle) && 6150 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT))) 6151 return; 6152 6153 if (rte_intr_allow_others(intr_handle)) 6154 vec = base = IXGBE_RX_VEC_START; 6155 6156 /* setup GPIE for MSI-x mode */ 6157 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 6158 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 6159 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME; 6160 /* auto clearing and auto setting corresponding bits in EIMS 6161 * when MSI-X interrupt is triggered 6162 */ 6163 if (hw->mac.type == ixgbe_mac_82598EB) { 6164 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 6165 } else { 6166 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 6167 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 6168 } 6169 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 6170 6171 /* Populate the IVAR table and set the ITR values to the 6172 * corresponding register. 6173 */ 6174 if (rte_intr_dp_is_en(intr_handle)) { 6175 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; 6176 queue_id++) { 6177 /* by default, 1:1 mapping */ 6178 ixgbe_set_ivar_map(hw, 0, queue_id, vec); 6179 intr_handle->intr_vec[queue_id] = vec; 6180 if (vec < base + intr_handle->nb_efd - 1) 6181 vec++; 6182 } 6183 6184 switch (hw->mac.type) { 6185 case ixgbe_mac_82598EB: 6186 ixgbe_set_ivar_map(hw, -1, 6187 IXGBE_IVAR_OTHER_CAUSES_INDEX, 6188 IXGBE_MISC_VEC_ID); 6189 break; 6190 case ixgbe_mac_82599EB: 6191 case ixgbe_mac_X540: 6192 case ixgbe_mac_X550: 6193 case ixgbe_mac_X550EM_x: 6194 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID); 6195 break; 6196 default: 6197 break; 6198 } 6199 } 6200 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID), 6201 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 6202 | IXGBE_EITR_CNT_WDIS); 6203 6204 /* set up to autoclear timer, and the vectors */ 6205 mask = IXGBE_EIMS_ENABLE_MASK; 6206 mask &= ~(IXGBE_EIMS_OTHER | 6207 IXGBE_EIMS_MAILBOX | 6208 IXGBE_EIMS_LSC); 6209 6210 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask); 6211 } 6212 6213 int 6214 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, 6215 uint16_t queue_idx, uint16_t tx_rate) 6216 { 6217 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6218 struct rte_eth_rxmode *rxmode; 6219 uint32_t rf_dec, rf_int; 6220 uint32_t bcnrc_val; 6221 uint16_t link_speed = dev->data->dev_link.link_speed; 6222 6223 if (queue_idx >= hw->mac.max_tx_queues) 6224 return -EINVAL; 6225 6226 if (tx_rate != 0) { 6227 /* Calculate the rate factor values to set */ 6228 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate; 6229 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate; 6230 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate; 6231 6232 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA; 6233 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) & 6234 IXGBE_RTTBCNRC_RF_INT_MASK_M); 6235 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK); 6236 } else { 6237 bcnrc_val = 0; 6238 } 6239 6240 rxmode = &dev->data->dev_conf.rxmode; 6241 /* 6242 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 6243 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise 6244 * set as 0x4. 6245 */ 6246 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) && 6247 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE)) 6248 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 6249 IXGBE_MMW_SIZE_JUMBO_FRAME); 6250 else 6251 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 6252 IXGBE_MMW_SIZE_DEFAULT); 6253 6254 /* Set RTTBCNRC of queue X */ 6255 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx); 6256 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 6257 IXGBE_WRITE_FLUSH(hw); 6258 6259 return 0; 6260 } 6261 6262 static int 6263 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 6264 __rte_unused uint32_t index, 6265 __rte_unused uint32_t pool) 6266 { 6267 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6268 int diag; 6269 6270 /* 6271 * On a 82599 VF, adding again the same MAC addr is not an idempotent 6272 * operation. Trap this case to avoid exhausting the [very limited] 6273 * set of PF resources used to store VF MAC addresses. 6274 */ 6275 if (memcmp(hw->mac.perm_addr, mac_addr, 6276 sizeof(struct rte_ether_addr)) == 0) 6277 return -1; 6278 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6279 if (diag != 0) 6280 PMD_DRV_LOG(ERR, "Unable to add MAC address " 6281 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d", 6282 mac_addr->addr_bytes[0], 6283 mac_addr->addr_bytes[1], 6284 mac_addr->addr_bytes[2], 6285 mac_addr->addr_bytes[3], 6286 mac_addr->addr_bytes[4], 6287 mac_addr->addr_bytes[5], 6288 diag); 6289 return diag; 6290 } 6291 6292 static void 6293 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index) 6294 { 6295 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6296 struct rte_ether_addr *perm_addr = 6297 (struct rte_ether_addr *)hw->mac.perm_addr; 6298 struct rte_ether_addr *mac_addr; 6299 uint32_t i; 6300 int diag; 6301 6302 /* 6303 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does 6304 * not support the deletion of a given MAC address. 6305 * Instead, it imposes to delete all MAC addresses, then to add again 6306 * all MAC addresses with the exception of the one to be deleted. 6307 */ 6308 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL); 6309 6310 /* 6311 * Add again all MAC addresses, with the exception of the deleted one 6312 * and of the permanent MAC address. 6313 */ 6314 for (i = 0, mac_addr = dev->data->mac_addrs; 6315 i < hw->mac.num_rar_entries; i++, mac_addr++) { 6316 /* Skip the deleted MAC address */ 6317 if (i == index) 6318 continue; 6319 /* Skip NULL MAC addresses */ 6320 if (rte_is_zero_ether_addr(mac_addr)) 6321 continue; 6322 /* Skip the permanent MAC address */ 6323 if (memcmp(perm_addr, mac_addr, 6324 sizeof(struct rte_ether_addr)) == 0) 6325 continue; 6326 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6327 if (diag != 0) 6328 PMD_DRV_LOG(ERR, 6329 "Adding again MAC address " 6330 "%02x:%02x:%02x:%02x:%02x:%02x failed " 6331 "diag=%d", 6332 mac_addr->addr_bytes[0], 6333 mac_addr->addr_bytes[1], 6334 mac_addr->addr_bytes[2], 6335 mac_addr->addr_bytes[3], 6336 mac_addr->addr_bytes[4], 6337 mac_addr->addr_bytes[5], 6338 diag); 6339 } 6340 } 6341 6342 static int 6343 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 6344 struct rte_ether_addr *addr) 6345 { 6346 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6347 6348 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0); 6349 6350 return 0; 6351 } 6352 6353 int 6354 ixgbe_syn_filter_set(struct rte_eth_dev *dev, 6355 struct rte_eth_syn_filter *filter, 6356 bool add) 6357 { 6358 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6359 struct ixgbe_filter_info *filter_info = 6360 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6361 uint32_t syn_info; 6362 uint32_t synqf; 6363 6364 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6365 return -EINVAL; 6366 6367 syn_info = filter_info->syn_info; 6368 6369 if (add) { 6370 if (syn_info & IXGBE_SYN_FILTER_ENABLE) 6371 return -EINVAL; 6372 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) & 6373 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE); 6374 6375 if (filter->hig_pri) 6376 synqf |= IXGBE_SYN_FILTER_SYNQFP; 6377 else 6378 synqf &= ~IXGBE_SYN_FILTER_SYNQFP; 6379 } else { 6380 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6381 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE)) 6382 return -ENOENT; 6383 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE); 6384 } 6385 6386 filter_info->syn_info = synqf; 6387 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 6388 IXGBE_WRITE_FLUSH(hw); 6389 return 0; 6390 } 6391 6392 6393 static inline enum ixgbe_5tuple_protocol 6394 convert_protocol_type(uint8_t protocol_value) 6395 { 6396 if (protocol_value == IPPROTO_TCP) 6397 return IXGBE_FILTER_PROTOCOL_TCP; 6398 else if (protocol_value == IPPROTO_UDP) 6399 return IXGBE_FILTER_PROTOCOL_UDP; 6400 else if (protocol_value == IPPROTO_SCTP) 6401 return IXGBE_FILTER_PROTOCOL_SCTP; 6402 else 6403 return IXGBE_FILTER_PROTOCOL_NONE; 6404 } 6405 6406 /* inject a 5-tuple filter to HW */ 6407 static inline void 6408 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev, 6409 struct ixgbe_5tuple_filter *filter) 6410 { 6411 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6412 int i; 6413 uint32_t ftqf, sdpqf; 6414 uint32_t l34timir = 0; 6415 uint8_t mask = 0xff; 6416 6417 i = filter->index; 6418 6419 sdpqf = (uint32_t)(filter->filter_info.dst_port << 6420 IXGBE_SDPQF_DSTPORT_SHIFT); 6421 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT); 6422 6423 ftqf = (uint32_t)(filter->filter_info.proto & 6424 IXGBE_FTQF_PROTOCOL_MASK); 6425 ftqf |= (uint32_t)((filter->filter_info.priority & 6426 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT); 6427 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */ 6428 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK; 6429 if (filter->filter_info.dst_ip_mask == 0) 6430 mask &= IXGBE_FTQF_DEST_ADDR_MASK; 6431 if (filter->filter_info.src_port_mask == 0) 6432 mask &= IXGBE_FTQF_SOURCE_PORT_MASK; 6433 if (filter->filter_info.dst_port_mask == 0) 6434 mask &= IXGBE_FTQF_DEST_PORT_MASK; 6435 if (filter->filter_info.proto_mask == 0) 6436 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK; 6437 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT; 6438 ftqf |= IXGBE_FTQF_POOL_MASK_EN; 6439 ftqf |= IXGBE_FTQF_QUEUE_ENABLE; 6440 6441 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip); 6442 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip); 6443 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf); 6444 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf); 6445 6446 l34timir |= IXGBE_L34T_IMIR_RESERVE; 6447 l34timir |= (uint32_t)(filter->queue << 6448 IXGBE_L34T_IMIR_QUEUE_SHIFT); 6449 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir); 6450 } 6451 6452 /* 6453 * add a 5tuple filter 6454 * 6455 * @param 6456 * dev: Pointer to struct rte_eth_dev. 6457 * index: the index the filter allocates. 6458 * filter: ponter to the filter that will be added. 6459 * rx_queue: the queue id the filter assigned to. 6460 * 6461 * @return 6462 * - On success, zero. 6463 * - On failure, a negative value. 6464 */ 6465 static int 6466 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 6467 struct ixgbe_5tuple_filter *filter) 6468 { 6469 struct ixgbe_filter_info *filter_info = 6470 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6471 int i, idx, shift; 6472 6473 /* 6474 * look for an unused 5tuple filter index, 6475 * and insert the filter to list. 6476 */ 6477 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) { 6478 idx = i / (sizeof(uint32_t) * NBBY); 6479 shift = i % (sizeof(uint32_t) * NBBY); 6480 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) { 6481 filter_info->fivetuple_mask[idx] |= 1 << shift; 6482 filter->index = i; 6483 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list, 6484 filter, 6485 entries); 6486 break; 6487 } 6488 } 6489 if (i >= IXGBE_MAX_FTQF_FILTERS) { 6490 PMD_DRV_LOG(ERR, "5tuple filters are full."); 6491 return -ENOSYS; 6492 } 6493 6494 ixgbe_inject_5tuple_filter(dev, filter); 6495 6496 return 0; 6497 } 6498 6499 /* 6500 * remove a 5tuple filter 6501 * 6502 * @param 6503 * dev: Pointer to struct rte_eth_dev. 6504 * filter: the pointer of the filter will be removed. 6505 */ 6506 static void 6507 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 6508 struct ixgbe_5tuple_filter *filter) 6509 { 6510 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6511 struct ixgbe_filter_info *filter_info = 6512 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6513 uint16_t index = filter->index; 6514 6515 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &= 6516 ~(1 << (index % (sizeof(uint32_t) * NBBY))); 6517 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries); 6518 rte_free(filter); 6519 6520 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0); 6521 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0); 6522 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0); 6523 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0); 6524 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0); 6525 } 6526 6527 static int 6528 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 6529 { 6530 struct ixgbe_hw *hw; 6531 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD; 6532 struct rte_eth_dev_data *dev_data = dev->data; 6533 6534 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6535 6536 if (mtu < RTE_ETHER_MIN_MTU || 6537 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN) 6538 return -EINVAL; 6539 6540 /* If device is started, refuse mtu that requires the support of 6541 * scattered packets when this feature has not been enabled before. 6542 */ 6543 if (dev_data->dev_started && !dev_data->scattered_rx && 6544 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE > 6545 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 6546 PMD_INIT_LOG(ERR, "Stop port first."); 6547 return -EINVAL; 6548 } 6549 6550 /* 6551 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU 6552 * request of the version 2.0 of the mailbox API. 6553 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0 6554 * of the mailbox API. 6555 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers 6556 * prior to 3.11.33 which contains the following change: 6557 * "ixgbe: Enable jumbo frames support w/ SR-IOV" 6558 */ 6559 if (ixgbevf_rlpml_set_vf(hw, max_frame)) 6560 return -EINVAL; 6561 6562 /* update max frame size */ 6563 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame; 6564 return 0; 6565 } 6566 6567 static inline struct ixgbe_5tuple_filter * 6568 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list, 6569 struct ixgbe_5tuple_filter_info *key) 6570 { 6571 struct ixgbe_5tuple_filter *it; 6572 6573 TAILQ_FOREACH(it, filter_list, entries) { 6574 if (memcmp(key, &it->filter_info, 6575 sizeof(struct ixgbe_5tuple_filter_info)) == 0) { 6576 return it; 6577 } 6578 } 6579 return NULL; 6580 } 6581 6582 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/ 6583 static inline int 6584 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter, 6585 struct ixgbe_5tuple_filter_info *filter_info) 6586 { 6587 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM || 6588 filter->priority > IXGBE_5TUPLE_MAX_PRI || 6589 filter->priority < IXGBE_5TUPLE_MIN_PRI) 6590 return -EINVAL; 6591 6592 switch (filter->dst_ip_mask) { 6593 case UINT32_MAX: 6594 filter_info->dst_ip_mask = 0; 6595 filter_info->dst_ip = filter->dst_ip; 6596 break; 6597 case 0: 6598 filter_info->dst_ip_mask = 1; 6599 break; 6600 default: 6601 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 6602 return -EINVAL; 6603 } 6604 6605 switch (filter->src_ip_mask) { 6606 case UINT32_MAX: 6607 filter_info->src_ip_mask = 0; 6608 filter_info->src_ip = filter->src_ip; 6609 break; 6610 case 0: 6611 filter_info->src_ip_mask = 1; 6612 break; 6613 default: 6614 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 6615 return -EINVAL; 6616 } 6617 6618 switch (filter->dst_port_mask) { 6619 case UINT16_MAX: 6620 filter_info->dst_port_mask = 0; 6621 filter_info->dst_port = filter->dst_port; 6622 break; 6623 case 0: 6624 filter_info->dst_port_mask = 1; 6625 break; 6626 default: 6627 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 6628 return -EINVAL; 6629 } 6630 6631 switch (filter->src_port_mask) { 6632 case UINT16_MAX: 6633 filter_info->src_port_mask = 0; 6634 filter_info->src_port = filter->src_port; 6635 break; 6636 case 0: 6637 filter_info->src_port_mask = 1; 6638 break; 6639 default: 6640 PMD_DRV_LOG(ERR, "invalid src_port mask."); 6641 return -EINVAL; 6642 } 6643 6644 switch (filter->proto_mask) { 6645 case UINT8_MAX: 6646 filter_info->proto_mask = 0; 6647 filter_info->proto = 6648 convert_protocol_type(filter->proto); 6649 break; 6650 case 0: 6651 filter_info->proto_mask = 1; 6652 break; 6653 default: 6654 PMD_DRV_LOG(ERR, "invalid protocol mask."); 6655 return -EINVAL; 6656 } 6657 6658 filter_info->priority = (uint8_t)filter->priority; 6659 return 0; 6660 } 6661 6662 /* 6663 * add or delete a ntuple filter 6664 * 6665 * @param 6666 * dev: Pointer to struct rte_eth_dev. 6667 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6668 * add: if true, add filter, if false, remove filter 6669 * 6670 * @return 6671 * - On success, zero. 6672 * - On failure, a negative value. 6673 */ 6674 int 6675 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 6676 struct rte_eth_ntuple_filter *ntuple_filter, 6677 bool add) 6678 { 6679 struct ixgbe_filter_info *filter_info = 6680 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6681 struct ixgbe_5tuple_filter_info filter_5tuple; 6682 struct ixgbe_5tuple_filter *filter; 6683 int ret; 6684 6685 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6686 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6687 return -EINVAL; 6688 } 6689 6690 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6691 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6692 if (ret < 0) 6693 return ret; 6694 6695 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6696 &filter_5tuple); 6697 if (filter != NULL && add) { 6698 PMD_DRV_LOG(ERR, "filter exists."); 6699 return -EEXIST; 6700 } 6701 if (filter == NULL && !add) { 6702 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6703 return -ENOENT; 6704 } 6705 6706 if (add) { 6707 filter = rte_zmalloc("ixgbe_5tuple_filter", 6708 sizeof(struct ixgbe_5tuple_filter), 0); 6709 if (filter == NULL) 6710 return -ENOMEM; 6711 rte_memcpy(&filter->filter_info, 6712 &filter_5tuple, 6713 sizeof(struct ixgbe_5tuple_filter_info)); 6714 filter->queue = ntuple_filter->queue; 6715 ret = ixgbe_add_5tuple_filter(dev, filter); 6716 if (ret < 0) { 6717 rte_free(filter); 6718 return ret; 6719 } 6720 } else 6721 ixgbe_remove_5tuple_filter(dev, filter); 6722 6723 return 0; 6724 } 6725 6726 int 6727 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 6728 struct rte_eth_ethertype_filter *filter, 6729 bool add) 6730 { 6731 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6732 struct ixgbe_filter_info *filter_info = 6733 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6734 uint32_t etqf = 0; 6735 uint32_t etqs = 0; 6736 int ret; 6737 struct ixgbe_ethertype_filter ethertype_filter; 6738 6739 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6740 return -EINVAL; 6741 6742 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 || 6743 filter->ether_type == RTE_ETHER_TYPE_IPV6) { 6744 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in" 6745 " ethertype filter.", filter->ether_type); 6746 return -EINVAL; 6747 } 6748 6749 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) { 6750 PMD_DRV_LOG(ERR, "mac compare is unsupported."); 6751 return -EINVAL; 6752 } 6753 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) { 6754 PMD_DRV_LOG(ERR, "drop option is unsupported."); 6755 return -EINVAL; 6756 } 6757 6758 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6759 if (ret >= 0 && add) { 6760 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.", 6761 filter->ether_type); 6762 return -EEXIST; 6763 } 6764 if (ret < 0 && !add) { 6765 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6766 filter->ether_type); 6767 return -ENOENT; 6768 } 6769 6770 if (add) { 6771 etqf = IXGBE_ETQF_FILTER_EN; 6772 etqf |= (uint32_t)filter->ether_type; 6773 etqs |= (uint32_t)((filter->queue << 6774 IXGBE_ETQS_RX_QUEUE_SHIFT) & 6775 IXGBE_ETQS_RX_QUEUE); 6776 etqs |= IXGBE_ETQS_QUEUE_EN; 6777 6778 ethertype_filter.ethertype = filter->ether_type; 6779 ethertype_filter.etqf = etqf; 6780 ethertype_filter.etqs = etqs; 6781 ethertype_filter.conf = FALSE; 6782 ret = ixgbe_ethertype_filter_insert(filter_info, 6783 ðertype_filter); 6784 if (ret < 0) { 6785 PMD_DRV_LOG(ERR, "ethertype filters are full."); 6786 return -ENOSPC; 6787 } 6788 } else { 6789 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret); 6790 if (ret < 0) 6791 return -ENOSYS; 6792 } 6793 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf); 6794 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs); 6795 IXGBE_WRITE_FLUSH(hw); 6796 6797 return 0; 6798 } 6799 6800 static int 6801 ixgbe_dev_filter_ctrl(__rte_unused struct rte_eth_dev *dev, 6802 enum rte_filter_type filter_type, 6803 enum rte_filter_op filter_op, 6804 void *arg) 6805 { 6806 int ret = 0; 6807 6808 switch (filter_type) { 6809 case RTE_ETH_FILTER_GENERIC: 6810 if (filter_op != RTE_ETH_FILTER_GET) 6811 return -EINVAL; 6812 *(const void **)arg = &ixgbe_flow_ops; 6813 break; 6814 default: 6815 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 6816 filter_type); 6817 ret = -EINVAL; 6818 break; 6819 } 6820 6821 return ret; 6822 } 6823 6824 static u8 * 6825 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw, 6826 u8 **mc_addr_ptr, u32 *vmdq) 6827 { 6828 u8 *mc_addr; 6829 6830 *vmdq = 0; 6831 mc_addr = *mc_addr_ptr; 6832 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr)); 6833 return mc_addr; 6834 } 6835 6836 static int 6837 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 6838 struct rte_ether_addr *mc_addr_set, 6839 uint32_t nb_mc_addr) 6840 { 6841 struct ixgbe_hw *hw; 6842 u8 *mc_addr_list; 6843 6844 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6845 mc_addr_list = (u8 *)mc_addr_set; 6846 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr, 6847 ixgbe_dev_addr_list_itr, TRUE); 6848 } 6849 6850 static uint64_t 6851 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev) 6852 { 6853 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6854 uint64_t systime_cycles; 6855 6856 switch (hw->mac.type) { 6857 case ixgbe_mac_X550: 6858 case ixgbe_mac_X550EM_x: 6859 case ixgbe_mac_X550EM_a: 6860 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */ 6861 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 6862 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 6863 * NSEC_PER_SEC; 6864 break; 6865 default: 6866 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 6867 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 6868 << 32; 6869 } 6870 6871 return systime_cycles; 6872 } 6873 6874 static uint64_t 6875 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) 6876 { 6877 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6878 uint64_t rx_tstamp_cycles; 6879 6880 switch (hw->mac.type) { 6881 case ixgbe_mac_X550: 6882 case ixgbe_mac_X550EM_x: 6883 case ixgbe_mac_X550EM_a: 6884 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 6885 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 6886 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 6887 * NSEC_PER_SEC; 6888 break; 6889 default: 6890 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 6891 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 6892 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 6893 << 32; 6894 } 6895 6896 return rx_tstamp_cycles; 6897 } 6898 6899 static uint64_t 6900 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 6901 { 6902 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6903 uint64_t tx_tstamp_cycles; 6904 6905 switch (hw->mac.type) { 6906 case ixgbe_mac_X550: 6907 case ixgbe_mac_X550EM_x: 6908 case ixgbe_mac_X550EM_a: 6909 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 6910 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 6911 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 6912 * NSEC_PER_SEC; 6913 break; 6914 default: 6915 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 6916 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 6917 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 6918 << 32; 6919 } 6920 6921 return tx_tstamp_cycles; 6922 } 6923 6924 static void 6925 ixgbe_start_timecounters(struct rte_eth_dev *dev) 6926 { 6927 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6928 struct ixgbe_adapter *adapter = dev->data->dev_private; 6929 struct rte_eth_link link; 6930 uint32_t incval = 0; 6931 uint32_t shift = 0; 6932 6933 /* Get current link speed. */ 6934 ixgbe_dev_link_update(dev, 1); 6935 rte_eth_linkstatus_get(dev, &link); 6936 6937 switch (link.link_speed) { 6938 case ETH_SPEED_NUM_100M: 6939 incval = IXGBE_INCVAL_100; 6940 shift = IXGBE_INCVAL_SHIFT_100; 6941 break; 6942 case ETH_SPEED_NUM_1G: 6943 incval = IXGBE_INCVAL_1GB; 6944 shift = IXGBE_INCVAL_SHIFT_1GB; 6945 break; 6946 case ETH_SPEED_NUM_10G: 6947 default: 6948 incval = IXGBE_INCVAL_10GB; 6949 shift = IXGBE_INCVAL_SHIFT_10GB; 6950 break; 6951 } 6952 6953 switch (hw->mac.type) { 6954 case ixgbe_mac_X550: 6955 case ixgbe_mac_X550EM_x: 6956 case ixgbe_mac_X550EM_a: 6957 /* Independent of link speed. */ 6958 incval = 1; 6959 /* Cycles read will be interpreted as ns. */ 6960 shift = 0; 6961 /* Fall-through */ 6962 case ixgbe_mac_X540: 6963 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval); 6964 break; 6965 case ixgbe_mac_82599EB: 6966 incval >>= IXGBE_INCVAL_SHIFT_82599; 6967 shift -= IXGBE_INCVAL_SHIFT_82599; 6968 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 6969 (1 << IXGBE_INCPER_SHIFT_82599) | incval); 6970 break; 6971 default: 6972 /* Not supported. */ 6973 return; 6974 } 6975 6976 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 6977 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 6978 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 6979 6980 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6981 adapter->systime_tc.cc_shift = shift; 6982 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; 6983 6984 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6985 adapter->rx_tstamp_tc.cc_shift = shift; 6986 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 6987 6988 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6989 adapter->tx_tstamp_tc.cc_shift = shift; 6990 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 6991 } 6992 6993 static int 6994 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 6995 { 6996 struct ixgbe_adapter *adapter = dev->data->dev_private; 6997 6998 adapter->systime_tc.nsec += delta; 6999 adapter->rx_tstamp_tc.nsec += delta; 7000 adapter->tx_tstamp_tc.nsec += delta; 7001 7002 return 0; 7003 } 7004 7005 static int 7006 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 7007 { 7008 uint64_t ns; 7009 struct ixgbe_adapter *adapter = dev->data->dev_private; 7010 7011 ns = rte_timespec_to_ns(ts); 7012 /* Set the timecounters to a new value. */ 7013 adapter->systime_tc.nsec = ns; 7014 adapter->rx_tstamp_tc.nsec = ns; 7015 adapter->tx_tstamp_tc.nsec = ns; 7016 7017 return 0; 7018 } 7019 7020 static int 7021 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 7022 { 7023 uint64_t ns, systime_cycles; 7024 struct ixgbe_adapter *adapter = dev->data->dev_private; 7025 7026 systime_cycles = ixgbe_read_systime_cyclecounter(dev); 7027 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 7028 *ts = rte_ns_to_timespec(ns); 7029 7030 return 0; 7031 } 7032 7033 static int 7034 ixgbe_timesync_enable(struct rte_eth_dev *dev) 7035 { 7036 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7037 uint32_t tsync_ctl; 7038 uint32_t tsauxc; 7039 7040 /* Stop the timesync system time. */ 7041 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0); 7042 /* Reset the timesync system time value. */ 7043 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0); 7044 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0); 7045 7046 /* Enable system time for platforms where it isn't on by default. */ 7047 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC); 7048 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME; 7049 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc); 7050 7051 ixgbe_start_timecounters(dev); 7052 7053 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7054 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 7055 (RTE_ETHER_TYPE_1588 | 7056 IXGBE_ETQF_FILTER_EN | 7057 IXGBE_ETQF_1588)); 7058 7059 /* Enable timestamping of received PTP packets. */ 7060 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7061 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED; 7062 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7063 7064 /* Enable timestamping of transmitted PTP packets. */ 7065 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7066 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED; 7067 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7068 7069 IXGBE_WRITE_FLUSH(hw); 7070 7071 return 0; 7072 } 7073 7074 static int 7075 ixgbe_timesync_disable(struct rte_eth_dev *dev) 7076 { 7077 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7078 uint32_t tsync_ctl; 7079 7080 /* Disable timestamping of transmitted PTP packets. */ 7081 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7082 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED; 7083 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7084 7085 /* Disable timestamping of received PTP packets. */ 7086 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7087 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED; 7088 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7089 7090 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7091 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0); 7092 7093 /* Stop incrementating the System Time registers. */ 7094 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0); 7095 7096 return 0; 7097 } 7098 7099 static int 7100 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 7101 struct timespec *timestamp, 7102 uint32_t flags __rte_unused) 7103 { 7104 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7105 struct ixgbe_adapter *adapter = dev->data->dev_private; 7106 uint32_t tsync_rxctl; 7107 uint64_t rx_tstamp_cycles; 7108 uint64_t ns; 7109 7110 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7111 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0) 7112 return -EINVAL; 7113 7114 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev); 7115 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 7116 *timestamp = rte_ns_to_timespec(ns); 7117 7118 return 0; 7119 } 7120 7121 static int 7122 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 7123 struct timespec *timestamp) 7124 { 7125 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7126 struct ixgbe_adapter *adapter = dev->data->dev_private; 7127 uint32_t tsync_txctl; 7128 uint64_t tx_tstamp_cycles; 7129 uint64_t ns; 7130 7131 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7132 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0) 7133 return -EINVAL; 7134 7135 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev); 7136 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 7137 *timestamp = rte_ns_to_timespec(ns); 7138 7139 return 0; 7140 } 7141 7142 static int 7143 ixgbe_get_reg_length(struct rte_eth_dev *dev) 7144 { 7145 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7146 int count = 0; 7147 int g_ind = 0; 7148 const struct reg_info *reg_group; 7149 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7150 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7151 7152 while ((reg_group = reg_set[g_ind++])) 7153 count += ixgbe_regs_group_count(reg_group); 7154 7155 return count; 7156 } 7157 7158 static int 7159 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused) 7160 { 7161 int count = 0; 7162 int g_ind = 0; 7163 const struct reg_info *reg_group; 7164 7165 while ((reg_group = ixgbevf_regs[g_ind++])) 7166 count += ixgbe_regs_group_count(reg_group); 7167 7168 return count; 7169 } 7170 7171 static int 7172 ixgbe_get_regs(struct rte_eth_dev *dev, 7173 struct rte_dev_reg_info *regs) 7174 { 7175 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7176 uint32_t *data = regs->data; 7177 int g_ind = 0; 7178 int count = 0; 7179 const struct reg_info *reg_group; 7180 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7181 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7182 7183 if (data == NULL) { 7184 regs->length = ixgbe_get_reg_length(dev); 7185 regs->width = sizeof(uint32_t); 7186 return 0; 7187 } 7188 7189 /* Support only full register dump */ 7190 if ((regs->length == 0) || 7191 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) { 7192 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7193 hw->device_id; 7194 while ((reg_group = reg_set[g_ind++])) 7195 count += ixgbe_read_regs_group(dev, &data[count], 7196 reg_group); 7197 return 0; 7198 } 7199 7200 return -ENOTSUP; 7201 } 7202 7203 static int 7204 ixgbevf_get_regs(struct rte_eth_dev *dev, 7205 struct rte_dev_reg_info *regs) 7206 { 7207 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7208 uint32_t *data = regs->data; 7209 int g_ind = 0; 7210 int count = 0; 7211 const struct reg_info *reg_group; 7212 7213 if (data == NULL) { 7214 regs->length = ixgbevf_get_reg_length(dev); 7215 regs->width = sizeof(uint32_t); 7216 return 0; 7217 } 7218 7219 /* Support only full register dump */ 7220 if ((regs->length == 0) || 7221 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) { 7222 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7223 hw->device_id; 7224 while ((reg_group = ixgbevf_regs[g_ind++])) 7225 count += ixgbe_read_regs_group(dev, &data[count], 7226 reg_group); 7227 return 0; 7228 } 7229 7230 return -ENOTSUP; 7231 } 7232 7233 static int 7234 ixgbe_get_eeprom_length(struct rte_eth_dev *dev) 7235 { 7236 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7237 7238 /* Return unit is byte count */ 7239 return hw->eeprom.word_size * 2; 7240 } 7241 7242 static int 7243 ixgbe_get_eeprom(struct rte_eth_dev *dev, 7244 struct rte_dev_eeprom_info *in_eeprom) 7245 { 7246 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7247 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7248 uint16_t *data = in_eeprom->data; 7249 int first, length; 7250 7251 first = in_eeprom->offset >> 1; 7252 length = in_eeprom->length >> 1; 7253 if ((first > hw->eeprom.word_size) || 7254 ((first + length) > hw->eeprom.word_size)) 7255 return -EINVAL; 7256 7257 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7258 7259 return eeprom->ops.read_buffer(hw, first, length, data); 7260 } 7261 7262 static int 7263 ixgbe_set_eeprom(struct rte_eth_dev *dev, 7264 struct rte_dev_eeprom_info *in_eeprom) 7265 { 7266 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7267 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7268 uint16_t *data = in_eeprom->data; 7269 int first, length; 7270 7271 first = in_eeprom->offset >> 1; 7272 length = in_eeprom->length >> 1; 7273 if ((first > hw->eeprom.word_size) || 7274 ((first + length) > hw->eeprom.word_size)) 7275 return -EINVAL; 7276 7277 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7278 7279 return eeprom->ops.write_buffer(hw, first, length, data); 7280 } 7281 7282 static int 7283 ixgbe_get_module_info(struct rte_eth_dev *dev, 7284 struct rte_eth_dev_module_info *modinfo) 7285 { 7286 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7287 uint32_t status; 7288 uint8_t sff8472_rev, addr_mode; 7289 bool page_swap = false; 7290 7291 /* Check whether we support SFF-8472 or not */ 7292 status = hw->phy.ops.read_i2c_eeprom(hw, 7293 IXGBE_SFF_SFF_8472_COMP, 7294 &sff8472_rev); 7295 if (status != 0) 7296 return -EIO; 7297 7298 /* addressing mode is not supported */ 7299 status = hw->phy.ops.read_i2c_eeprom(hw, 7300 IXGBE_SFF_SFF_8472_SWAP, 7301 &addr_mode); 7302 if (status != 0) 7303 return -EIO; 7304 7305 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 7306 PMD_DRV_LOG(ERR, 7307 "Address change required to access page 0xA2, " 7308 "but not supported. Please report the module " 7309 "type to the driver maintainers."); 7310 page_swap = true; 7311 } 7312 7313 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) { 7314 /* We have a SFP, but it does not support SFF-8472 */ 7315 modinfo->type = RTE_ETH_MODULE_SFF_8079; 7316 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 7317 } else { 7318 /* We have a SFP which supports a revision of SFF-8472. */ 7319 modinfo->type = RTE_ETH_MODULE_SFF_8472; 7320 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 7321 } 7322 7323 return 0; 7324 } 7325 7326 static int 7327 ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 7328 struct rte_dev_eeprom_info *info) 7329 { 7330 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7331 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 7332 uint8_t databyte = 0xFF; 7333 uint8_t *data = info->data; 7334 uint32_t i = 0; 7335 7336 if (info->length == 0) 7337 return -EINVAL; 7338 7339 for (i = info->offset; i < info->offset + info->length; i++) { 7340 if (i < RTE_ETH_MODULE_SFF_8079_LEN) 7341 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 7342 else 7343 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 7344 7345 if (status != 0) 7346 return -EIO; 7347 7348 data[i - info->offset] = databyte; 7349 } 7350 7351 return 0; 7352 } 7353 7354 uint16_t 7355 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) { 7356 switch (mac_type) { 7357 case ixgbe_mac_X550: 7358 case ixgbe_mac_X550EM_x: 7359 case ixgbe_mac_X550EM_a: 7360 return ETH_RSS_RETA_SIZE_512; 7361 case ixgbe_mac_X550_vf: 7362 case ixgbe_mac_X550EM_x_vf: 7363 case ixgbe_mac_X550EM_a_vf: 7364 return ETH_RSS_RETA_SIZE_64; 7365 case ixgbe_mac_X540_vf: 7366 case ixgbe_mac_82599_vf: 7367 return 0; 7368 default: 7369 return ETH_RSS_RETA_SIZE_128; 7370 } 7371 } 7372 7373 uint32_t 7374 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) { 7375 switch (mac_type) { 7376 case ixgbe_mac_X550: 7377 case ixgbe_mac_X550EM_x: 7378 case ixgbe_mac_X550EM_a: 7379 if (reta_idx < ETH_RSS_RETA_SIZE_128) 7380 return IXGBE_RETA(reta_idx >> 2); 7381 else 7382 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2); 7383 case ixgbe_mac_X550_vf: 7384 case ixgbe_mac_X550EM_x_vf: 7385 case ixgbe_mac_X550EM_a_vf: 7386 return IXGBE_VFRETA(reta_idx >> 2); 7387 default: 7388 return IXGBE_RETA(reta_idx >> 2); 7389 } 7390 } 7391 7392 uint32_t 7393 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) { 7394 switch (mac_type) { 7395 case ixgbe_mac_X550_vf: 7396 case ixgbe_mac_X550EM_x_vf: 7397 case ixgbe_mac_X550EM_a_vf: 7398 return IXGBE_VFMRQC; 7399 default: 7400 return IXGBE_MRQC; 7401 } 7402 } 7403 7404 uint32_t 7405 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) { 7406 switch (mac_type) { 7407 case ixgbe_mac_X550_vf: 7408 case ixgbe_mac_X550EM_x_vf: 7409 case ixgbe_mac_X550EM_a_vf: 7410 return IXGBE_VFRSSRK(i); 7411 default: 7412 return IXGBE_RSSRK(i); 7413 } 7414 } 7415 7416 bool 7417 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) { 7418 switch (mac_type) { 7419 case ixgbe_mac_82599_vf: 7420 case ixgbe_mac_X540_vf: 7421 return 0; 7422 default: 7423 return 1; 7424 } 7425 } 7426 7427 static int 7428 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 7429 struct rte_eth_dcb_info *dcb_info) 7430 { 7431 struct ixgbe_dcb_config *dcb_config = 7432 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 7433 struct ixgbe_dcb_tc_config *tc; 7434 struct rte_eth_dcb_tc_queue_mapping *tc_queue; 7435 uint8_t nb_tcs; 7436 uint8_t i, j; 7437 7438 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG) 7439 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs; 7440 else 7441 dcb_info->nb_tcs = 1; 7442 7443 tc_queue = &dcb_info->tc_queue; 7444 nb_tcs = dcb_info->nb_tcs; 7445 7446 if (dcb_config->vt_mode) { /* vt is enabled*/ 7447 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf = 7448 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf; 7449 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7450 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i]; 7451 if (RTE_ETH_DEV_SRIOV(dev).active > 0) { 7452 for (j = 0; j < nb_tcs; j++) { 7453 tc_queue->tc_rxq[0][j].base = j; 7454 tc_queue->tc_rxq[0][j].nb_queue = 1; 7455 tc_queue->tc_txq[0][j].base = j; 7456 tc_queue->tc_txq[0][j].nb_queue = 1; 7457 } 7458 } else { 7459 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) { 7460 for (j = 0; j < nb_tcs; j++) { 7461 tc_queue->tc_rxq[i][j].base = 7462 i * nb_tcs + j; 7463 tc_queue->tc_rxq[i][j].nb_queue = 1; 7464 tc_queue->tc_txq[i][j].base = 7465 i * nb_tcs + j; 7466 tc_queue->tc_txq[i][j].nb_queue = 1; 7467 } 7468 } 7469 } 7470 } else { /* vt is disabled*/ 7471 struct rte_eth_dcb_rx_conf *rx_conf = 7472 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 7473 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7474 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i]; 7475 if (dcb_info->nb_tcs == ETH_4_TCS) { 7476 for (i = 0; i < dcb_info->nb_tcs; i++) { 7477 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32; 7478 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7479 } 7480 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7481 dcb_info->tc_queue.tc_txq[0][1].base = 64; 7482 dcb_info->tc_queue.tc_txq[0][2].base = 96; 7483 dcb_info->tc_queue.tc_txq[0][3].base = 112; 7484 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64; 7485 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7486 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7487 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7488 } else if (dcb_info->nb_tcs == ETH_8_TCS) { 7489 for (i = 0; i < dcb_info->nb_tcs; i++) { 7490 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16; 7491 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7492 } 7493 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7494 dcb_info->tc_queue.tc_txq[0][1].base = 32; 7495 dcb_info->tc_queue.tc_txq[0][2].base = 64; 7496 dcb_info->tc_queue.tc_txq[0][3].base = 80; 7497 dcb_info->tc_queue.tc_txq[0][4].base = 96; 7498 dcb_info->tc_queue.tc_txq[0][5].base = 104; 7499 dcb_info->tc_queue.tc_txq[0][6].base = 112; 7500 dcb_info->tc_queue.tc_txq[0][7].base = 120; 7501 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32; 7502 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7503 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7504 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7505 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8; 7506 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8; 7507 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8; 7508 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8; 7509 } 7510 } 7511 for (i = 0; i < dcb_info->nb_tcs; i++) { 7512 tc = &dcb_config->tc_config[i]; 7513 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent; 7514 } 7515 return 0; 7516 } 7517 7518 /* Update e-tag ether type */ 7519 static int 7520 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw, 7521 uint16_t ether_type) 7522 { 7523 uint32_t etag_etype; 7524 7525 if (hw->mac.type != ixgbe_mac_X550 && 7526 hw->mac.type != ixgbe_mac_X550EM_x && 7527 hw->mac.type != ixgbe_mac_X550EM_a) { 7528 return -ENOTSUP; 7529 } 7530 7531 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7532 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK; 7533 etag_etype |= ether_type; 7534 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7535 IXGBE_WRITE_FLUSH(hw); 7536 7537 return 0; 7538 } 7539 7540 /* Enable e-tag tunnel */ 7541 static int 7542 ixgbe_e_tag_enable(struct ixgbe_hw *hw) 7543 { 7544 uint32_t etag_etype; 7545 7546 if (hw->mac.type != ixgbe_mac_X550 && 7547 hw->mac.type != ixgbe_mac_X550EM_x && 7548 hw->mac.type != ixgbe_mac_X550EM_a) { 7549 return -ENOTSUP; 7550 } 7551 7552 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7553 etag_etype |= IXGBE_ETAG_ETYPE_VALID; 7554 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7555 IXGBE_WRITE_FLUSH(hw); 7556 7557 return 0; 7558 } 7559 7560 static int 7561 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev, 7562 struct ixgbe_l2_tunnel_conf *l2_tunnel) 7563 { 7564 int ret = 0; 7565 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7566 uint32_t i, rar_entries; 7567 uint32_t rar_low, rar_high; 7568 7569 if (hw->mac.type != ixgbe_mac_X550 && 7570 hw->mac.type != ixgbe_mac_X550EM_x && 7571 hw->mac.type != ixgbe_mac_X550EM_a) { 7572 return -ENOTSUP; 7573 } 7574 7575 rar_entries = ixgbe_get_num_rx_addrs(hw); 7576 7577 for (i = 1; i < rar_entries; i++) { 7578 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7579 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 7580 if ((rar_high & IXGBE_RAH_AV) && 7581 (rar_high & IXGBE_RAH_ADTYPE) && 7582 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) == 7583 l2_tunnel->tunnel_id)) { 7584 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 7585 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 7586 7587 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL); 7588 7589 return ret; 7590 } 7591 } 7592 7593 return ret; 7594 } 7595 7596 static int 7597 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev, 7598 struct ixgbe_l2_tunnel_conf *l2_tunnel) 7599 { 7600 int ret = 0; 7601 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7602 uint32_t i, rar_entries; 7603 uint32_t rar_low, rar_high; 7604 7605 if (hw->mac.type != ixgbe_mac_X550 && 7606 hw->mac.type != ixgbe_mac_X550EM_x && 7607 hw->mac.type != ixgbe_mac_X550EM_a) { 7608 return -ENOTSUP; 7609 } 7610 7611 /* One entry for one tunnel. Try to remove potential existing entry. */ 7612 ixgbe_e_tag_filter_del(dev, l2_tunnel); 7613 7614 rar_entries = ixgbe_get_num_rx_addrs(hw); 7615 7616 for (i = 1; i < rar_entries; i++) { 7617 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7618 if (rar_high & IXGBE_RAH_AV) { 7619 continue; 7620 } else { 7621 ixgbe_set_vmdq(hw, i, l2_tunnel->pool); 7622 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE; 7623 rar_low = l2_tunnel->tunnel_id; 7624 7625 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low); 7626 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high); 7627 7628 return ret; 7629 } 7630 } 7631 7632 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full." 7633 " Please remove a rule before adding a new one."); 7634 return -EINVAL; 7635 } 7636 7637 static inline struct ixgbe_l2_tn_filter * 7638 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info, 7639 struct ixgbe_l2_tn_key *key) 7640 { 7641 int ret; 7642 7643 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key); 7644 if (ret < 0) 7645 return NULL; 7646 7647 return l2_tn_info->hash_map[ret]; 7648 } 7649 7650 static inline int 7651 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7652 struct ixgbe_l2_tn_filter *l2_tn_filter) 7653 { 7654 int ret; 7655 7656 ret = rte_hash_add_key(l2_tn_info->hash_handle, 7657 &l2_tn_filter->key); 7658 7659 if (ret < 0) { 7660 PMD_DRV_LOG(ERR, 7661 "Failed to insert L2 tunnel filter" 7662 " to hash table %d!", 7663 ret); 7664 return ret; 7665 } 7666 7667 l2_tn_info->hash_map[ret] = l2_tn_filter; 7668 7669 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 7670 7671 return 0; 7672 } 7673 7674 static inline int 7675 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7676 struct ixgbe_l2_tn_key *key) 7677 { 7678 int ret; 7679 struct ixgbe_l2_tn_filter *l2_tn_filter; 7680 7681 ret = rte_hash_del_key(l2_tn_info->hash_handle, key); 7682 7683 if (ret < 0) { 7684 PMD_DRV_LOG(ERR, 7685 "No such L2 tunnel filter to delete %d!", 7686 ret); 7687 return ret; 7688 } 7689 7690 l2_tn_filter = l2_tn_info->hash_map[ret]; 7691 l2_tn_info->hash_map[ret] = NULL; 7692 7693 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 7694 rte_free(l2_tn_filter); 7695 7696 return 0; 7697 } 7698 7699 /* Add l2 tunnel filter */ 7700 int 7701 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 7702 struct ixgbe_l2_tunnel_conf *l2_tunnel, 7703 bool restore) 7704 { 7705 int ret; 7706 struct ixgbe_l2_tn_info *l2_tn_info = 7707 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7708 struct ixgbe_l2_tn_key key; 7709 struct ixgbe_l2_tn_filter *node; 7710 7711 if (!restore) { 7712 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 7713 key.tn_id = l2_tunnel->tunnel_id; 7714 7715 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key); 7716 7717 if (node) { 7718 PMD_DRV_LOG(ERR, 7719 "The L2 tunnel filter already exists!"); 7720 return -EINVAL; 7721 } 7722 7723 node = rte_zmalloc("ixgbe_l2_tn", 7724 sizeof(struct ixgbe_l2_tn_filter), 7725 0); 7726 if (!node) 7727 return -ENOMEM; 7728 7729 rte_memcpy(&node->key, 7730 &key, 7731 sizeof(struct ixgbe_l2_tn_key)); 7732 node->pool = l2_tunnel->pool; 7733 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node); 7734 if (ret < 0) { 7735 rte_free(node); 7736 return ret; 7737 } 7738 } 7739 7740 switch (l2_tunnel->l2_tunnel_type) { 7741 case RTE_L2_TUNNEL_TYPE_E_TAG: 7742 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel); 7743 break; 7744 default: 7745 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7746 ret = -EINVAL; 7747 break; 7748 } 7749 7750 if ((!restore) && (ret < 0)) 7751 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 7752 7753 return ret; 7754 } 7755 7756 /* Delete l2 tunnel filter */ 7757 int 7758 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 7759 struct ixgbe_l2_tunnel_conf *l2_tunnel) 7760 { 7761 int ret; 7762 struct ixgbe_l2_tn_info *l2_tn_info = 7763 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7764 struct ixgbe_l2_tn_key key; 7765 7766 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 7767 key.tn_id = l2_tunnel->tunnel_id; 7768 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 7769 if (ret < 0) 7770 return ret; 7771 7772 switch (l2_tunnel->l2_tunnel_type) { 7773 case RTE_L2_TUNNEL_TYPE_E_TAG: 7774 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel); 7775 break; 7776 default: 7777 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7778 ret = -EINVAL; 7779 break; 7780 } 7781 7782 return ret; 7783 } 7784 7785 static int 7786 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en) 7787 { 7788 int ret = 0; 7789 uint32_t ctrl; 7790 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7791 7792 if (hw->mac.type != ixgbe_mac_X550 && 7793 hw->mac.type != ixgbe_mac_X550EM_x && 7794 hw->mac.type != ixgbe_mac_X550EM_a) { 7795 return -ENOTSUP; 7796 } 7797 7798 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 7799 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 7800 if (en) 7801 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG; 7802 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 7803 7804 return ret; 7805 } 7806 7807 static int 7808 ixgbe_update_vxlan_port(struct ixgbe_hw *hw, 7809 uint16_t port) 7810 { 7811 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port); 7812 IXGBE_WRITE_FLUSH(hw); 7813 7814 return 0; 7815 } 7816 7817 /* There's only one register for VxLAN UDP port. 7818 * So, we cannot add several ports. Will update it. 7819 */ 7820 static int 7821 ixgbe_add_vxlan_port(struct ixgbe_hw *hw, 7822 uint16_t port) 7823 { 7824 if (port == 0) { 7825 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 7826 return -EINVAL; 7827 } 7828 7829 return ixgbe_update_vxlan_port(hw, port); 7830 } 7831 7832 /* We cannot delete the VxLAN port. For there's a register for VxLAN 7833 * UDP port, it must have a value. 7834 * So, will reset it to the original value 0. 7835 */ 7836 static int 7837 ixgbe_del_vxlan_port(struct ixgbe_hw *hw, 7838 uint16_t port) 7839 { 7840 uint16_t cur_port; 7841 7842 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL); 7843 7844 if (cur_port != port) { 7845 PMD_DRV_LOG(ERR, "Port %u does not exist.", port); 7846 return -EINVAL; 7847 } 7848 7849 return ixgbe_update_vxlan_port(hw, 0); 7850 } 7851 7852 /* Add UDP tunneling port */ 7853 static int 7854 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 7855 struct rte_eth_udp_tunnel *udp_tunnel) 7856 { 7857 int ret = 0; 7858 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7859 7860 if (hw->mac.type != ixgbe_mac_X550 && 7861 hw->mac.type != ixgbe_mac_X550EM_x && 7862 hw->mac.type != ixgbe_mac_X550EM_a) { 7863 return -ENOTSUP; 7864 } 7865 7866 if (udp_tunnel == NULL) 7867 return -EINVAL; 7868 7869 switch (udp_tunnel->prot_type) { 7870 case RTE_TUNNEL_TYPE_VXLAN: 7871 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port); 7872 break; 7873 7874 case RTE_TUNNEL_TYPE_GENEVE: 7875 case RTE_TUNNEL_TYPE_TEREDO: 7876 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 7877 ret = -EINVAL; 7878 break; 7879 7880 default: 7881 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7882 ret = -EINVAL; 7883 break; 7884 } 7885 7886 return ret; 7887 } 7888 7889 /* Remove UDP tunneling port */ 7890 static int 7891 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 7892 struct rte_eth_udp_tunnel *udp_tunnel) 7893 { 7894 int ret = 0; 7895 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7896 7897 if (hw->mac.type != ixgbe_mac_X550 && 7898 hw->mac.type != ixgbe_mac_X550EM_x && 7899 hw->mac.type != ixgbe_mac_X550EM_a) { 7900 return -ENOTSUP; 7901 } 7902 7903 if (udp_tunnel == NULL) 7904 return -EINVAL; 7905 7906 switch (udp_tunnel->prot_type) { 7907 case RTE_TUNNEL_TYPE_VXLAN: 7908 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port); 7909 break; 7910 case RTE_TUNNEL_TYPE_GENEVE: 7911 case RTE_TUNNEL_TYPE_TEREDO: 7912 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 7913 ret = -EINVAL; 7914 break; 7915 default: 7916 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7917 ret = -EINVAL; 7918 break; 7919 } 7920 7921 return ret; 7922 } 7923 7924 static int 7925 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev) 7926 { 7927 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7928 int ret; 7929 7930 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) { 7931 case IXGBE_SUCCESS: 7932 ret = 0; 7933 break; 7934 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 7935 ret = -ENOTSUP; 7936 break; 7937 default: 7938 ret = -EAGAIN; 7939 break; 7940 } 7941 7942 return ret; 7943 } 7944 7945 static int 7946 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev) 7947 { 7948 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7949 int ret; 7950 7951 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) { 7952 case IXGBE_SUCCESS: 7953 ret = 0; 7954 break; 7955 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 7956 ret = -ENOTSUP; 7957 break; 7958 default: 7959 ret = -EAGAIN; 7960 break; 7961 } 7962 7963 return ret; 7964 } 7965 7966 static int 7967 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev) 7968 { 7969 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7970 int ret; 7971 int mode = IXGBEVF_XCAST_MODE_ALLMULTI; 7972 7973 switch (hw->mac.ops.update_xcast_mode(hw, mode)) { 7974 case IXGBE_SUCCESS: 7975 ret = 0; 7976 break; 7977 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 7978 ret = -ENOTSUP; 7979 break; 7980 default: 7981 ret = -EAGAIN; 7982 break; 7983 } 7984 7985 return ret; 7986 } 7987 7988 static int 7989 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev) 7990 { 7991 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7992 int ret; 7993 7994 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) { 7995 case IXGBE_SUCCESS: 7996 ret = 0; 7997 break; 7998 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 7999 ret = -ENOTSUP; 8000 break; 8001 default: 8002 ret = -EAGAIN; 8003 break; 8004 } 8005 8006 return ret; 8007 } 8008 8009 static void ixgbevf_mbx_process(struct rte_eth_dev *dev) 8010 { 8011 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8012 u32 in_msg = 0; 8013 8014 /* peek the message first */ 8015 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM); 8016 8017 /* PF reset VF event */ 8018 if (in_msg == IXGBE_PF_CONTROL_MSG) { 8019 /* dummy mbx read to ack pf */ 8020 if (ixgbe_read_mbx(hw, &in_msg, 1, 0)) 8021 return; 8022 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 8023 NULL); 8024 } 8025 } 8026 8027 static int 8028 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev) 8029 { 8030 uint32_t eicr; 8031 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8032 struct ixgbe_interrupt *intr = 8033 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8034 ixgbevf_intr_disable(dev); 8035 8036 /* read-on-clear nic registers here */ 8037 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR); 8038 intr->flags = 0; 8039 8040 /* only one misc vector supported - mailbox */ 8041 eicr &= IXGBE_VTEICR_MASK; 8042 if (eicr == IXGBE_MISC_VEC_ID) 8043 intr->flags |= IXGBE_FLAG_MAILBOX; 8044 8045 return 0; 8046 } 8047 8048 static int 8049 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev) 8050 { 8051 struct ixgbe_interrupt *intr = 8052 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8053 8054 if (intr->flags & IXGBE_FLAG_MAILBOX) { 8055 ixgbevf_mbx_process(dev); 8056 intr->flags &= ~IXGBE_FLAG_MAILBOX; 8057 } 8058 8059 ixgbevf_intr_enable(dev); 8060 8061 return 0; 8062 } 8063 8064 static void 8065 ixgbevf_dev_interrupt_handler(void *param) 8066 { 8067 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 8068 8069 ixgbevf_dev_interrupt_get_status(dev); 8070 ixgbevf_dev_interrupt_action(dev); 8071 } 8072 8073 /** 8074 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path 8075 * @hw: pointer to hardware structure 8076 * 8077 * Stops the transmit data path and waits for the HW to internally empty 8078 * the Tx security block 8079 **/ 8080 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw) 8081 { 8082 #define IXGBE_MAX_SECTX_POLL 40 8083 8084 int i; 8085 int sectxreg; 8086 8087 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8088 sectxreg |= IXGBE_SECTXCTRL_TX_DIS; 8089 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8090 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) { 8091 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT); 8092 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY) 8093 break; 8094 /* Use interrupt-safe sleep just in case */ 8095 usec_delay(1000); 8096 } 8097 8098 /* For informational purposes only */ 8099 if (i >= IXGBE_MAX_SECTX_POLL) 8100 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security " 8101 "path fully disabled. Continuing with init."); 8102 8103 return IXGBE_SUCCESS; 8104 } 8105 8106 /** 8107 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path 8108 * @hw: pointer to hardware structure 8109 * 8110 * Enables the transmit data path. 8111 **/ 8112 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw) 8113 { 8114 uint32_t sectxreg; 8115 8116 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8117 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS; 8118 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8119 IXGBE_WRITE_FLUSH(hw); 8120 8121 return IXGBE_SUCCESS; 8122 } 8123 8124 /* restore n-tuple filter */ 8125 static inline void 8126 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev) 8127 { 8128 struct ixgbe_filter_info *filter_info = 8129 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8130 struct ixgbe_5tuple_filter *node; 8131 8132 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) { 8133 ixgbe_inject_5tuple_filter(dev, node); 8134 } 8135 } 8136 8137 /* restore ethernet type filter */ 8138 static inline void 8139 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev) 8140 { 8141 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8142 struct ixgbe_filter_info *filter_info = 8143 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8144 int i; 8145 8146 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8147 if (filter_info->ethertype_mask & (1 << i)) { 8148 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 8149 filter_info->ethertype_filters[i].etqf); 8150 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 8151 filter_info->ethertype_filters[i].etqs); 8152 IXGBE_WRITE_FLUSH(hw); 8153 } 8154 } 8155 } 8156 8157 /* restore SYN filter */ 8158 static inline void 8159 ixgbe_syn_filter_restore(struct rte_eth_dev *dev) 8160 { 8161 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8162 struct ixgbe_filter_info *filter_info = 8163 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8164 uint32_t synqf; 8165 8166 synqf = filter_info->syn_info; 8167 8168 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 8169 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 8170 IXGBE_WRITE_FLUSH(hw); 8171 } 8172 } 8173 8174 /* restore L2 tunnel filter */ 8175 static inline void 8176 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev) 8177 { 8178 struct ixgbe_l2_tn_info *l2_tn_info = 8179 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8180 struct ixgbe_l2_tn_filter *node; 8181 struct ixgbe_l2_tunnel_conf l2_tn_conf; 8182 8183 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) { 8184 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type; 8185 l2_tn_conf.tunnel_id = node->key.tn_id; 8186 l2_tn_conf.pool = node->pool; 8187 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE); 8188 } 8189 } 8190 8191 /* restore rss filter */ 8192 static inline void 8193 ixgbe_rss_filter_restore(struct rte_eth_dev *dev) 8194 { 8195 struct ixgbe_filter_info *filter_info = 8196 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8197 8198 if (filter_info->rss_info.conf.queue_num) 8199 ixgbe_config_rss_filter(dev, 8200 &filter_info->rss_info, TRUE); 8201 } 8202 8203 static int 8204 ixgbe_filter_restore(struct rte_eth_dev *dev) 8205 { 8206 ixgbe_ntuple_filter_restore(dev); 8207 ixgbe_ethertype_filter_restore(dev); 8208 ixgbe_syn_filter_restore(dev); 8209 ixgbe_fdir_filter_restore(dev); 8210 ixgbe_l2_tn_filter_restore(dev); 8211 ixgbe_rss_filter_restore(dev); 8212 8213 return 0; 8214 } 8215 8216 static void 8217 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev) 8218 { 8219 struct ixgbe_l2_tn_info *l2_tn_info = 8220 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8221 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8222 8223 if (l2_tn_info->e_tag_en) 8224 (void)ixgbe_e_tag_enable(hw); 8225 8226 if (l2_tn_info->e_tag_fwd_en) 8227 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1); 8228 8229 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type); 8230 } 8231 8232 /* remove all the n-tuple filters */ 8233 void 8234 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev) 8235 { 8236 struct ixgbe_filter_info *filter_info = 8237 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8238 struct ixgbe_5tuple_filter *p_5tuple; 8239 8240 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) 8241 ixgbe_remove_5tuple_filter(dev, p_5tuple); 8242 } 8243 8244 /* remove all the ether type filters */ 8245 void 8246 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev) 8247 { 8248 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8249 struct ixgbe_filter_info *filter_info = 8250 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8251 int i; 8252 8253 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8254 if (filter_info->ethertype_mask & (1 << i) && 8255 !filter_info->ethertype_filters[i].conf) { 8256 (void)ixgbe_ethertype_filter_remove(filter_info, 8257 (uint8_t)i); 8258 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0); 8259 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0); 8260 IXGBE_WRITE_FLUSH(hw); 8261 } 8262 } 8263 } 8264 8265 /* remove the SYN filter */ 8266 void 8267 ixgbe_clear_syn_filter(struct rte_eth_dev *dev) 8268 { 8269 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8270 struct ixgbe_filter_info *filter_info = 8271 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8272 8273 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) { 8274 filter_info->syn_info = 0; 8275 8276 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0); 8277 IXGBE_WRITE_FLUSH(hw); 8278 } 8279 } 8280 8281 /* remove all the L2 tunnel filters */ 8282 int 8283 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev) 8284 { 8285 struct ixgbe_l2_tn_info *l2_tn_info = 8286 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8287 struct ixgbe_l2_tn_filter *l2_tn_filter; 8288 struct ixgbe_l2_tunnel_conf l2_tn_conf; 8289 int ret = 0; 8290 8291 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 8292 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type; 8293 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id; 8294 l2_tn_conf.pool = l2_tn_filter->pool; 8295 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf); 8296 if (ret < 0) 8297 return ret; 8298 } 8299 8300 return 0; 8301 } 8302 8303 void 8304 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev, 8305 struct ixgbe_macsec_setting *macsec_setting) 8306 { 8307 struct ixgbe_macsec_setting *macsec = 8308 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 8309 8310 macsec->offload_en = macsec_setting->offload_en; 8311 macsec->encrypt_en = macsec_setting->encrypt_en; 8312 macsec->replayprotect_en = macsec_setting->replayprotect_en; 8313 } 8314 8315 void 8316 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev) 8317 { 8318 struct ixgbe_macsec_setting *macsec = 8319 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 8320 8321 macsec->offload_en = 0; 8322 macsec->encrypt_en = 0; 8323 macsec->replayprotect_en = 0; 8324 } 8325 8326 void 8327 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev, 8328 struct ixgbe_macsec_setting *macsec_setting) 8329 { 8330 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8331 uint32_t ctrl; 8332 uint8_t en = macsec_setting->encrypt_en; 8333 uint8_t rp = macsec_setting->replayprotect_en; 8334 8335 /** 8336 * Workaround: 8337 * As no ixgbe_disable_sec_rx_path equivalent is 8338 * implemented for tx in the base code, and we are 8339 * not allowed to modify the base code in DPDK, so 8340 * just call the hand-written one directly for now. 8341 * The hardware support has been checked by 8342 * ixgbe_disable_sec_rx_path(). 8343 */ 8344 ixgbe_disable_sec_tx_path_generic(hw); 8345 8346 /* Enable Ethernet CRC (required by MACsec offload) */ 8347 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0); 8348 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP; 8349 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl); 8350 8351 /* Enable the TX and RX crypto engines */ 8352 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8353 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS; 8354 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl); 8355 8356 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 8357 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS; 8358 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl); 8359 8360 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 8361 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK; 8362 ctrl |= 0x3; 8363 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl); 8364 8365 /* Enable SA lookup */ 8366 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL); 8367 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK; 8368 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT : 8369 IXGBE_LSECTXCTRL_AUTH; 8370 ctrl |= IXGBE_LSECTXCTRL_AISCI; 8371 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK; 8372 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK; 8373 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl); 8374 8375 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL); 8376 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK; 8377 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT; 8378 ctrl &= ~IXGBE_LSECRXCTRL_PLSH; 8379 if (rp) 8380 ctrl |= IXGBE_LSECRXCTRL_RP; 8381 else 8382 ctrl &= ~IXGBE_LSECRXCTRL_RP; 8383 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl); 8384 8385 /* Start the data paths */ 8386 ixgbe_enable_sec_rx_path(hw); 8387 /** 8388 * Workaround: 8389 * As no ixgbe_enable_sec_rx_path equivalent is 8390 * implemented for tx in the base code, and we are 8391 * not allowed to modify the base code in DPDK, so 8392 * just call the hand-written one directly for now. 8393 */ 8394 ixgbe_enable_sec_tx_path_generic(hw); 8395 } 8396 8397 void 8398 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev) 8399 { 8400 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8401 uint32_t ctrl; 8402 8403 /** 8404 * Workaround: 8405 * As no ixgbe_disable_sec_rx_path equivalent is 8406 * implemented for tx in the base code, and we are 8407 * not allowed to modify the base code in DPDK, so 8408 * just call the hand-written one directly for now. 8409 * The hardware support has been checked by 8410 * ixgbe_disable_sec_rx_path(). 8411 */ 8412 ixgbe_disable_sec_tx_path_generic(hw); 8413 8414 /* Disable the TX and RX crypto engines */ 8415 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8416 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS; 8417 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl); 8418 8419 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 8420 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS; 8421 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl); 8422 8423 /* Disable SA lookup */ 8424 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL); 8425 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK; 8426 ctrl |= IXGBE_LSECTXCTRL_DISABLE; 8427 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl); 8428 8429 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL); 8430 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK; 8431 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT; 8432 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl); 8433 8434 /* Start the data paths */ 8435 ixgbe_enable_sec_rx_path(hw); 8436 /** 8437 * Workaround: 8438 * As no ixgbe_enable_sec_rx_path equivalent is 8439 * implemented for tx in the base code, and we are 8440 * not allowed to modify the base code in DPDK, so 8441 * just call the hand-written one directly for now. 8442 */ 8443 ixgbe_enable_sec_tx_path_generic(hw); 8444 } 8445 8446 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd); 8447 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map); 8448 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 8449 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd); 8450 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map); 8451 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci"); 8452 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf, 8453 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>"); 8454 8455 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE); 8456 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE); 8457 8458 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX 8459 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG); 8460 #endif 8461 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX 8462 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG); 8463 #endif 8464 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE 8465 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG); 8466 #endif 8467