1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <inttypes.h> 13 #include <netinet/in.h> 14 #include <rte_string_fns.h> 15 #include <rte_byteorder.h> 16 #include <rte_common.h> 17 #include <rte_cycles.h> 18 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_bus_pci.h> 24 #include <rte_branch_prediction.h> 25 #include <rte_memory.h> 26 #include <rte_kvargs.h> 27 #include <rte_eal.h> 28 #include <rte_alarm.h> 29 #include <rte_ether.h> 30 #include <rte_ethdev_driver.h> 31 #include <rte_ethdev_pci.h> 32 #include <rte_malloc.h> 33 #include <rte_random.h> 34 #include <rte_dev.h> 35 #include <rte_hash_crc.h> 36 #ifdef RTE_LIBRTE_SECURITY 37 #include <rte_security_driver.h> 38 #endif 39 40 #include "ixgbe_logs.h" 41 #include "base/ixgbe_api.h" 42 #include "base/ixgbe_vf.h" 43 #include "base/ixgbe_common.h" 44 #include "ixgbe_ethdev.h" 45 #include "ixgbe_bypass.h" 46 #include "ixgbe_rxtx.h" 47 #include "base/ixgbe_type.h" 48 #include "base/ixgbe_phy.h" 49 #include "ixgbe_regs.h" 50 51 /* 52 * High threshold controlling when to start sending XOFF frames. Must be at 53 * least 8 bytes less than receive packet buffer size. This value is in units 54 * of 1024 bytes. 55 */ 56 #define IXGBE_FC_HI 0x80 57 58 /* 59 * Low threshold controlling when to start sending XON frames. This value is 60 * in units of 1024 bytes. 61 */ 62 #define IXGBE_FC_LO 0x40 63 64 /* Timer value included in XOFF frames. */ 65 #define IXGBE_FC_PAUSE 0x680 66 67 /*Default value of Max Rx Queue*/ 68 #define IXGBE_MAX_RX_QUEUE_NUM 128 69 70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */ 71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */ 72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */ 73 74 #define IXGBE_MMW_SIZE_DEFAULT 0x4 75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14 76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */ 77 78 /* 79 * Default values for RX/TX configuration 80 */ 81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32 82 #define IXGBE_DEFAULT_RX_PTHRESH 8 83 #define IXGBE_DEFAULT_RX_HTHRESH 8 84 #define IXGBE_DEFAULT_RX_WTHRESH 0 85 86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32 87 #define IXGBE_DEFAULT_TX_PTHRESH 32 88 #define IXGBE_DEFAULT_TX_HTHRESH 0 89 #define IXGBE_DEFAULT_TX_WTHRESH 0 90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32 91 92 /* Bit shift and mask */ 93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2) 94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t) 95 #define IXGBE_8_BIT_WIDTH CHAR_BIT 96 #define IXGBE_8_BIT_MASK UINT8_MAX 97 98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */ 99 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0])) 101 102 /* Additional timesync values. */ 103 #define NSEC_PER_SEC 1000000000L 104 #define IXGBE_INCVAL_10GB 0x66666666 105 #define IXGBE_INCVAL_1GB 0x40000000 106 #define IXGBE_INCVAL_100 0x50000000 107 #define IXGBE_INCVAL_SHIFT_10GB 28 108 #define IXGBE_INCVAL_SHIFT_1GB 24 109 #define IXGBE_INCVAL_SHIFT_100 21 110 #define IXGBE_INCVAL_SHIFT_82599 7 111 #define IXGBE_INCPER_SHIFT_82599 24 112 113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL 114 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000 117 #define IXGBE_ETAG_ETYPE 0x00005084 118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff 119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000 120 #define IXGBE_RAH_ADTYPE 0x40000000 121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff 122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */ 125 #define IXGBE_QDE_STRIP_TAG 0x00000004 126 #define IXGBE_VTEICR_MASK 0x07 127 128 #define IXGBE_EXVET_VET_EXT_SHIFT 16 129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000 130 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk" 132 133 static const char * const ixgbevf_valid_arguments[] = { 134 IXGBEVF_DEVARG_PFLINK_FULLCHK, 135 NULL 136 }; 137 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev); 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev); 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev); 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev); 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev); 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev); 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev); 146 static int ixgbe_dev_start(struct rte_eth_dev *dev); 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev); 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev); 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev); 150 static void ixgbe_dev_close(struct rte_eth_dev *dev); 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev); 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev, 157 int wait_to_complete); 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev, 159 struct rte_eth_stats *stats); 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev, 161 struct rte_eth_xstat *xstats, unsigned n); 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, 163 struct rte_eth_xstat *xstats, unsigned n); 164 static int 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 166 uint64_t *values, unsigned int n); 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev); 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev); 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 170 struct rte_eth_xstat_name *xstats_names, 171 unsigned int size); 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev, 173 struct rte_eth_xstat_name *xstats_names, unsigned limit); 174 static int ixgbe_dev_xstats_get_names_by_id( 175 struct rte_eth_dev *dev, 176 struct rte_eth_xstat_name *xstats_names, 177 const uint64_t *ids, 178 unsigned int limit); 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 180 uint16_t queue_id, 181 uint8_t stat_idx, 182 uint8_t is_rx); 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 184 size_t fw_size); 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev, 186 struct rte_eth_dev_info *dev_info); 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev, 189 struct rte_eth_dev_info *dev_info); 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 191 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev, 193 uint16_t vlan_id, int on); 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 195 enum rte_vlan_type vlan_type, 196 uint16_t tpid_id); 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, 198 uint16_t queue, bool on); 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, 200 int on); 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, 202 int mask); 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask); 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask); 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue); 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue); 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev); 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev); 209 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev); 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev); 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, 213 struct rte_eth_fc_conf *fc_conf); 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, 215 struct rte_eth_fc_conf *fc_conf); 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 217 struct rte_eth_pfc_conf *pfc_conf); 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 219 struct rte_eth_rss_reta_entry64 *reta_conf, 220 uint16_t reta_size); 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 222 struct rte_eth_rss_reta_entry64 *reta_conf, 223 uint16_t reta_size); 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev); 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev); 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev); 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev); 230 static void ixgbe_dev_interrupt_handler(void *param); 231 static void ixgbe_dev_interrupt_delayed_handler(void *param); 232 static void *ixgbe_dev_setup_link_thread_handler(void *param); 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, 234 uint32_t timeout_ms); 235 236 static int ixgbe_add_rar(struct rte_eth_dev *dev, 237 struct rte_ether_addr *mac_addr, 238 uint32_t index, uint32_t pool); 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index); 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, 241 struct rte_ether_addr *mac_addr); 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config); 243 static bool is_device_supported(struct rte_eth_dev *dev, 244 struct rte_pci_driver *drv); 245 246 /* For Virtual Function support */ 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev); 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev); 249 static int ixgbevf_dev_configure(struct rte_eth_dev *dev); 250 static int ixgbevf_dev_start(struct rte_eth_dev *dev); 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev, 252 int wait_to_complete); 253 static void ixgbevf_dev_stop(struct rte_eth_dev *dev); 254 static void ixgbevf_dev_close(struct rte_eth_dev *dev); 255 static int ixgbevf_dev_reset(struct rte_eth_dev *dev); 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev); 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev); 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev, 259 struct rte_eth_stats *stats); 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev); 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, 262 uint16_t vlan_id, int on); 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, 264 uint16_t queue, int on); 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask); 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask); 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on); 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 269 uint16_t queue_id); 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 271 uint16_t queue_id); 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 273 uint8_t queue, uint8_t msix_vector); 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev); 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev); 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev); 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev); 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev); 279 280 /* For Eth VMDQ APIs support */ 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct 282 rte_ether_addr * mac_addr, uint8_t on); 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on); 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 285 struct rte_eth_mirror_conf *mirror_conf, 286 uint8_t rule_id, uint8_t on); 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, 288 uint8_t rule_id); 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 290 uint16_t queue_id); 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 292 uint16_t queue_id); 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 294 uint8_t queue, uint8_t msix_vector); 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev); 296 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev, 298 struct rte_ether_addr *mac_addr, 299 uint32_t index, uint32_t pool); 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index); 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 302 struct rte_ether_addr *mac_addr); 303 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev, 304 struct rte_eth_syn_filter *filter); 305 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev, 306 enum rte_filter_op filter_op, 307 void *arg); 308 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 309 struct ixgbe_5tuple_filter *filter); 310 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 311 struct ixgbe_5tuple_filter *filter); 312 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev, 313 enum rte_filter_op filter_op, 314 void *arg); 315 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev, 316 struct rte_eth_ntuple_filter *filter); 317 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev, 318 enum rte_filter_op filter_op, 319 void *arg); 320 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, 321 struct rte_eth_ethertype_filter *filter); 322 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 323 enum rte_filter_type filter_type, 324 enum rte_filter_op filter_op, 325 void *arg); 326 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 327 328 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 329 struct rte_ether_addr *mc_addr_set, 330 uint32_t nb_mc_addr); 331 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 332 struct rte_eth_dcb_info *dcb_info); 333 334 static int ixgbe_get_reg_length(struct rte_eth_dev *dev); 335 static int ixgbe_get_regs(struct rte_eth_dev *dev, 336 struct rte_dev_reg_info *regs); 337 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev); 338 static int ixgbe_get_eeprom(struct rte_eth_dev *dev, 339 struct rte_dev_eeprom_info *eeprom); 340 static int ixgbe_set_eeprom(struct rte_eth_dev *dev, 341 struct rte_dev_eeprom_info *eeprom); 342 343 static int ixgbe_get_module_info(struct rte_eth_dev *dev, 344 struct rte_eth_dev_module_info *modinfo); 345 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 346 struct rte_dev_eeprom_info *info); 347 348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev); 349 static int ixgbevf_get_regs(struct rte_eth_dev *dev, 350 struct rte_dev_reg_info *regs); 351 352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev); 353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev); 354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 355 struct timespec *timestamp, 356 uint32_t flags); 357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 358 struct timespec *timestamp); 359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev, 361 struct timespec *timestamp); 362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev, 363 const struct timespec *timestamp); 364 static void ixgbevf_dev_interrupt_handler(void *param); 365 366 static int ixgbe_dev_l2_tunnel_eth_type_conf 367 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel); 368 static int ixgbe_dev_l2_tunnel_offload_set 369 (struct rte_eth_dev *dev, 370 struct rte_eth_l2_tunnel_conf *l2_tunnel, 371 uint32_t mask, 372 uint8_t en); 373 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev, 374 enum rte_filter_op filter_op, 375 void *arg); 376 377 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 378 struct rte_eth_udp_tunnel *udp_tunnel); 379 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 380 struct rte_eth_udp_tunnel *udp_tunnel); 381 static int ixgbe_filter_restore(struct rte_eth_dev *dev); 382 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev); 383 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw); 384 385 /* 386 * Define VF Stats MACRO for Non "cleared on read" register 387 */ 388 #define UPDATE_VF_STAT(reg, last, cur) \ 389 { \ 390 uint32_t latest = IXGBE_READ_REG(hw, reg); \ 391 cur += (latest - last) & UINT_MAX; \ 392 last = latest; \ 393 } 394 395 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \ 396 { \ 397 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \ 398 u64 new_msb = IXGBE_READ_REG(hw, msb); \ 399 u64 latest = ((new_msb << 32) | new_lsb); \ 400 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \ 401 last = latest; \ 402 } 403 404 #define IXGBE_SET_HWSTRIP(h, q) do {\ 405 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 406 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 407 (h)->bitmap[idx] |= 1 << bit;\ 408 } while (0) 409 410 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\ 411 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 412 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 413 (h)->bitmap[idx] &= ~(1 << bit);\ 414 } while (0) 415 416 #define IXGBE_GET_HWSTRIP(h, q, r) do {\ 417 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 418 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 419 (r) = (h)->bitmap[idx] >> bit & 1;\ 420 } while (0) 421 422 /* 423 * The set of PCI devices this driver supports 424 */ 425 static const struct rte_pci_id pci_id_ixgbe_map[] = { 426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) }, 427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) }, 428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) }, 429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) }, 430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) }, 431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) }, 432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) }, 433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) }, 434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) }, 435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) }, 436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) }, 437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) }, 438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) }, 439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) }, 440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) }, 441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) }, 442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) }, 443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) }, 444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) }, 445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) }, 446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) }, 447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) }, 448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) }, 449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) }, 450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) }, 451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) }, 452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) }, 453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) }, 454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) }, 455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) }, 456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) }, 457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) }, 458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) }, 459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) }, 460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) }, 461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) }, 462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) }, 463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) }, 464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) }, 465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) }, 466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) }, 467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) }, 468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) }, 469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) }, 470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) }, 471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) }, 472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) }, 473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) }, 474 #ifdef RTE_LIBRTE_IXGBE_BYPASS 475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) }, 476 #endif 477 { .vendor_id = 0, /* sentinel */ }, 478 }; 479 480 /* 481 * The set of PCI devices this driver supports (for 82599 VF) 482 */ 483 static const struct rte_pci_id pci_id_ixgbevf_map[] = { 484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) }, 485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) }, 486 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) }, 487 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) }, 488 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) }, 489 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) }, 490 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) }, 491 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) }, 492 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) }, 493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) }, 494 { .vendor_id = 0, /* sentinel */ }, 495 }; 496 497 static const struct rte_eth_desc_lim rx_desc_lim = { 498 .nb_max = IXGBE_MAX_RING_DESC, 499 .nb_min = IXGBE_MIN_RING_DESC, 500 .nb_align = IXGBE_RXD_ALIGN, 501 }; 502 503 static const struct rte_eth_desc_lim tx_desc_lim = { 504 .nb_max = IXGBE_MAX_RING_DESC, 505 .nb_min = IXGBE_MIN_RING_DESC, 506 .nb_align = IXGBE_TXD_ALIGN, 507 .nb_seg_max = IXGBE_TX_MAX_SEG, 508 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG, 509 }; 510 511 static const struct eth_dev_ops ixgbe_eth_dev_ops = { 512 .dev_configure = ixgbe_dev_configure, 513 .dev_start = ixgbe_dev_start, 514 .dev_stop = ixgbe_dev_stop, 515 .dev_set_link_up = ixgbe_dev_set_link_up, 516 .dev_set_link_down = ixgbe_dev_set_link_down, 517 .dev_close = ixgbe_dev_close, 518 .dev_reset = ixgbe_dev_reset, 519 .promiscuous_enable = ixgbe_dev_promiscuous_enable, 520 .promiscuous_disable = ixgbe_dev_promiscuous_disable, 521 .allmulticast_enable = ixgbe_dev_allmulticast_enable, 522 .allmulticast_disable = ixgbe_dev_allmulticast_disable, 523 .link_update = ixgbe_dev_link_update, 524 .stats_get = ixgbe_dev_stats_get, 525 .xstats_get = ixgbe_dev_xstats_get, 526 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id, 527 .stats_reset = ixgbe_dev_stats_reset, 528 .xstats_reset = ixgbe_dev_xstats_reset, 529 .xstats_get_names = ixgbe_dev_xstats_get_names, 530 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id, 531 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set, 532 .fw_version_get = ixgbe_fw_version_get, 533 .dev_infos_get = ixgbe_dev_info_get, 534 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 535 .mtu_set = ixgbe_dev_mtu_set, 536 .vlan_filter_set = ixgbe_vlan_filter_set, 537 .vlan_tpid_set = ixgbe_vlan_tpid_set, 538 .vlan_offload_set = ixgbe_vlan_offload_set, 539 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set, 540 .rx_queue_start = ixgbe_dev_rx_queue_start, 541 .rx_queue_stop = ixgbe_dev_rx_queue_stop, 542 .tx_queue_start = ixgbe_dev_tx_queue_start, 543 .tx_queue_stop = ixgbe_dev_tx_queue_stop, 544 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 545 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable, 546 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable, 547 .rx_queue_release = ixgbe_dev_rx_queue_release, 548 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 549 .tx_queue_release = ixgbe_dev_tx_queue_release, 550 .dev_led_on = ixgbe_dev_led_on, 551 .dev_led_off = ixgbe_dev_led_off, 552 .flow_ctrl_get = ixgbe_flow_ctrl_get, 553 .flow_ctrl_set = ixgbe_flow_ctrl_set, 554 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set, 555 .mac_addr_add = ixgbe_add_rar, 556 .mac_addr_remove = ixgbe_remove_rar, 557 .mac_addr_set = ixgbe_set_default_mac_addr, 558 .uc_hash_table_set = ixgbe_uc_hash_table_set, 559 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set, 560 .mirror_rule_set = ixgbe_mirror_rule_set, 561 .mirror_rule_reset = ixgbe_mirror_rule_reset, 562 .set_queue_rate_limit = ixgbe_set_queue_rate_limit, 563 .reta_update = ixgbe_dev_rss_reta_update, 564 .reta_query = ixgbe_dev_rss_reta_query, 565 .rss_hash_update = ixgbe_dev_rss_hash_update, 566 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 567 .filter_ctrl = ixgbe_dev_filter_ctrl, 568 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 569 .rxq_info_get = ixgbe_rxq_info_get, 570 .txq_info_get = ixgbe_txq_info_get, 571 .timesync_enable = ixgbe_timesync_enable, 572 .timesync_disable = ixgbe_timesync_disable, 573 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp, 574 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp, 575 .get_reg = ixgbe_get_regs, 576 .get_eeprom_length = ixgbe_get_eeprom_length, 577 .get_eeprom = ixgbe_get_eeprom, 578 .set_eeprom = ixgbe_set_eeprom, 579 .get_module_info = ixgbe_get_module_info, 580 .get_module_eeprom = ixgbe_get_module_eeprom, 581 .get_dcb_info = ixgbe_dev_get_dcb_info, 582 .timesync_adjust_time = ixgbe_timesync_adjust_time, 583 .timesync_read_time = ixgbe_timesync_read_time, 584 .timesync_write_time = ixgbe_timesync_write_time, 585 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf, 586 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set, 587 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add, 588 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del, 589 .tm_ops_get = ixgbe_tm_ops_get, 590 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup, 591 }; 592 593 /* 594 * dev_ops for virtual function, bare necessities for basic vf 595 * operation have been implemented 596 */ 597 static const struct eth_dev_ops ixgbevf_eth_dev_ops = { 598 .dev_configure = ixgbevf_dev_configure, 599 .dev_start = ixgbevf_dev_start, 600 .dev_stop = ixgbevf_dev_stop, 601 .link_update = ixgbevf_dev_link_update, 602 .stats_get = ixgbevf_dev_stats_get, 603 .xstats_get = ixgbevf_dev_xstats_get, 604 .stats_reset = ixgbevf_dev_stats_reset, 605 .xstats_reset = ixgbevf_dev_stats_reset, 606 .xstats_get_names = ixgbevf_dev_xstats_get_names, 607 .dev_close = ixgbevf_dev_close, 608 .dev_reset = ixgbevf_dev_reset, 609 .promiscuous_enable = ixgbevf_dev_promiscuous_enable, 610 .promiscuous_disable = ixgbevf_dev_promiscuous_disable, 611 .allmulticast_enable = ixgbevf_dev_allmulticast_enable, 612 .allmulticast_disable = ixgbevf_dev_allmulticast_disable, 613 .dev_infos_get = ixgbevf_dev_info_get, 614 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 615 .mtu_set = ixgbevf_dev_set_mtu, 616 .vlan_filter_set = ixgbevf_vlan_filter_set, 617 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set, 618 .vlan_offload_set = ixgbevf_vlan_offload_set, 619 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 620 .rx_queue_release = ixgbe_dev_rx_queue_release, 621 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 622 .tx_queue_release = ixgbe_dev_tx_queue_release, 623 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable, 624 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable, 625 .mac_addr_add = ixgbevf_add_mac_addr, 626 .mac_addr_remove = ixgbevf_remove_mac_addr, 627 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 628 .rxq_info_get = ixgbe_rxq_info_get, 629 .txq_info_get = ixgbe_txq_info_get, 630 .mac_addr_set = ixgbevf_set_default_mac_addr, 631 .get_reg = ixgbevf_get_regs, 632 .reta_update = ixgbe_dev_rss_reta_update, 633 .reta_query = ixgbe_dev_rss_reta_query, 634 .rss_hash_update = ixgbe_dev_rss_hash_update, 635 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 636 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup, 637 }; 638 639 /* store statistics names and its offset in stats structure */ 640 struct rte_ixgbe_xstats_name_off { 641 char name[RTE_ETH_XSTATS_NAME_SIZE]; 642 unsigned offset; 643 }; 644 645 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = { 646 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)}, 647 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)}, 648 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)}, 649 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)}, 650 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)}, 651 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)}, 652 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)}, 653 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)}, 654 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)}, 655 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)}, 656 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)}, 657 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)}, 658 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)}, 659 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)}, 660 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 661 prc1023)}, 662 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 663 prc1522)}, 664 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)}, 665 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)}, 666 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)}, 667 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)}, 668 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)}, 669 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)}, 670 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)}, 671 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)}, 672 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)}, 673 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)}, 674 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)}, 675 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)}, 676 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)}, 677 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)}, 678 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)}, 679 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)}, 680 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 681 ptc1023)}, 682 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 683 ptc1522)}, 684 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)}, 685 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)}, 686 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)}, 687 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)}, 688 689 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats, 690 fdirustat_add)}, 691 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats, 692 fdirustat_remove)}, 693 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats, 694 fdirfstat_fadd)}, 695 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats, 696 fdirfstat_fremove)}, 697 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats, 698 fdirmatch)}, 699 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats, 700 fdirmiss)}, 701 702 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)}, 703 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)}, 704 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, 705 fclast)}, 706 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)}, 707 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)}, 708 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)}, 709 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)}, 710 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats, 711 fcoe_noddp)}, 712 {"rx_fcoe_no_direct_data_placement_ext_buff", 713 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)}, 714 715 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 716 lxontxc)}, 717 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 718 lxonrxc)}, 719 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 720 lxofftxc)}, 721 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 722 lxoffrxc)}, 723 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)}, 724 }; 725 726 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \ 727 sizeof(rte_ixgbe_stats_strings[0])) 728 729 /* MACsec statistics */ 730 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = { 731 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 732 out_pkts_untagged)}, 733 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats, 734 out_pkts_encrypted)}, 735 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats, 736 out_pkts_protected)}, 737 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats, 738 out_octets_encrypted)}, 739 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats, 740 out_octets_protected)}, 741 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 742 in_pkts_untagged)}, 743 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats, 744 in_pkts_badtag)}, 745 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats, 746 in_pkts_nosci)}, 747 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats, 748 in_pkts_unknownsci)}, 749 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats, 750 in_octets_decrypted)}, 751 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats, 752 in_octets_validated)}, 753 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats, 754 in_pkts_unchecked)}, 755 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats, 756 in_pkts_delayed)}, 757 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats, 758 in_pkts_late)}, 759 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats, 760 in_pkts_ok)}, 761 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats, 762 in_pkts_invalid)}, 763 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats, 764 in_pkts_notvalid)}, 765 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats, 766 in_pkts_unusedsa)}, 767 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats, 768 in_pkts_notusingsa)}, 769 }; 770 771 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \ 772 sizeof(rte_ixgbe_macsec_strings[0])) 773 774 /* Per-queue statistics */ 775 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = { 776 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)}, 777 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)}, 778 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)}, 779 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)}, 780 }; 781 782 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \ 783 sizeof(rte_ixgbe_rxq_strings[0])) 784 #define IXGBE_NB_RXQ_PRIO_VALUES 8 785 786 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = { 787 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)}, 788 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)}, 789 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats, 790 pxon2offc)}, 791 }; 792 793 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \ 794 sizeof(rte_ixgbe_txq_strings[0])) 795 #define IXGBE_NB_TXQ_PRIO_VALUES 8 796 797 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = { 798 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)}, 799 }; 800 801 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \ 802 sizeof(rte_ixgbevf_stats_strings[0])) 803 804 /* 805 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h. 806 */ 807 static inline int 808 ixgbe_is_sfp(struct ixgbe_hw *hw) 809 { 810 switch (hw->phy.type) { 811 case ixgbe_phy_sfp_avago: 812 case ixgbe_phy_sfp_ftl: 813 case ixgbe_phy_sfp_intel: 814 case ixgbe_phy_sfp_unknown: 815 case ixgbe_phy_sfp_passive_tyco: 816 case ixgbe_phy_sfp_passive_unknown: 817 return 1; 818 default: 819 return 0; 820 } 821 } 822 823 static inline int32_t 824 ixgbe_pf_reset_hw(struct ixgbe_hw *hw) 825 { 826 uint32_t ctrl_ext; 827 int32_t status; 828 829 status = ixgbe_reset_hw(hw); 830 831 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 832 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 833 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 834 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 835 IXGBE_WRITE_FLUSH(hw); 836 837 if (status == IXGBE_ERR_SFP_NOT_PRESENT) 838 status = IXGBE_SUCCESS; 839 return status; 840 } 841 842 static inline void 843 ixgbe_enable_intr(struct rte_eth_dev *dev) 844 { 845 struct ixgbe_interrupt *intr = 846 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 847 struct ixgbe_hw *hw = 848 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 849 850 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask); 851 IXGBE_WRITE_FLUSH(hw); 852 } 853 854 /* 855 * This function is based on ixgbe_disable_intr() in base/ixgbe.h. 856 */ 857 static void 858 ixgbe_disable_intr(struct ixgbe_hw *hw) 859 { 860 PMD_INIT_FUNC_TRACE(); 861 862 if (hw->mac.type == ixgbe_mac_82598EB) { 863 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0); 864 } else { 865 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000); 866 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0); 867 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0); 868 } 869 IXGBE_WRITE_FLUSH(hw); 870 } 871 872 /* 873 * This function resets queue statistics mapping registers. 874 * From Niantic datasheet, Initialization of Statistics section: 875 * "...if software requires the queue counters, the RQSMR and TQSM registers 876 * must be re-programmed following a device reset. 877 */ 878 static void 879 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw) 880 { 881 uint32_t i; 882 883 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) { 884 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0); 885 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0); 886 } 887 } 888 889 890 static int 891 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 892 uint16_t queue_id, 893 uint8_t stat_idx, 894 uint8_t is_rx) 895 { 896 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8 897 #define NB_QMAP_FIELDS_PER_QSM_REG 4 898 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f 899 900 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 901 struct ixgbe_stat_mapping_registers *stat_mappings = 902 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private); 903 uint32_t qsmr_mask = 0; 904 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK; 905 uint32_t q_map; 906 uint8_t n, offset; 907 908 if ((hw->mac.type != ixgbe_mac_82599EB) && 909 (hw->mac.type != ixgbe_mac_X540) && 910 (hw->mac.type != ixgbe_mac_X550) && 911 (hw->mac.type != ixgbe_mac_X550EM_x) && 912 (hw->mac.type != ixgbe_mac_X550EM_a)) 913 return -ENOSYS; 914 915 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d", 916 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 917 queue_id, stat_idx); 918 919 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG); 920 if (n >= IXGBE_NB_STAT_MAPPING_REGS) { 921 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded"); 922 return -EIO; 923 } 924 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG); 925 926 /* Now clear any previous stat_idx set */ 927 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 928 if (!is_rx) 929 stat_mappings->tqsm[n] &= ~clearing_mask; 930 else 931 stat_mappings->rqsmr[n] &= ~clearing_mask; 932 933 q_map = (uint32_t)stat_idx; 934 q_map &= QMAP_FIELD_RESERVED_BITS_MASK; 935 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 936 if (!is_rx) 937 stat_mappings->tqsm[n] |= qsmr_mask; 938 else 939 stat_mappings->rqsmr[n] |= qsmr_mask; 940 941 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d", 942 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 943 queue_id, stat_idx); 944 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n, 945 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]); 946 947 /* Now write the mapping in the appropriate register */ 948 if (is_rx) { 949 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d", 950 stat_mappings->rqsmr[n], n); 951 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]); 952 } else { 953 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d", 954 stat_mappings->tqsm[n], n); 955 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]); 956 } 957 return 0; 958 } 959 960 static void 961 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev) 962 { 963 struct ixgbe_stat_mapping_registers *stat_mappings = 964 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private); 965 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 966 int i; 967 968 /* write whatever was in stat mapping table to the NIC */ 969 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) { 970 /* rx */ 971 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]); 972 973 /* tx */ 974 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]); 975 } 976 } 977 978 static void 979 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config) 980 { 981 uint8_t i; 982 struct ixgbe_dcb_tc_config *tc; 983 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS; 984 985 dcb_config->num_tcs.pg_tcs = dcb_max_tc; 986 dcb_config->num_tcs.pfc_tcs = dcb_max_tc; 987 for (i = 0; i < dcb_max_tc; i++) { 988 tc = &dcb_config->tc_config[i]; 989 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i; 990 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 991 (uint8_t)(100/dcb_max_tc + (i & 1)); 992 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i; 993 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 994 (uint8_t)(100/dcb_max_tc + (i & 1)); 995 tc->pfc = ixgbe_dcb_pfc_disabled; 996 } 997 998 /* Initialize default user to priority mapping, UPx->TC0 */ 999 tc = &dcb_config->tc_config[0]; 1000 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 1001 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 1002 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) { 1003 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100; 1004 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100; 1005 } 1006 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal; 1007 dcb_config->pfc_mode_enable = false; 1008 dcb_config->vt_mode = true; 1009 dcb_config->round_robin_enable = false; 1010 /* support all DCB capabilities in 82599 */ 1011 dcb_config->support.capabilities = 0xFF; 1012 1013 /*we only support 4 Tcs for X540, X550 */ 1014 if (hw->mac.type == ixgbe_mac_X540 || 1015 hw->mac.type == ixgbe_mac_X550 || 1016 hw->mac.type == ixgbe_mac_X550EM_x || 1017 hw->mac.type == ixgbe_mac_X550EM_a) { 1018 dcb_config->num_tcs.pg_tcs = 4; 1019 dcb_config->num_tcs.pfc_tcs = 4; 1020 } 1021 } 1022 1023 /* 1024 * Ensure that all locks are released before first NVM or PHY access 1025 */ 1026 static void 1027 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw) 1028 { 1029 uint16_t mask; 1030 1031 /* 1032 * Phy lock should not fail in this early stage. If this is the case, 1033 * it is due to an improper exit of the application. 1034 * So force the release of the faulty lock. Release of common lock 1035 * is done automatically by swfw_sync function. 1036 */ 1037 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func; 1038 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1039 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func); 1040 } 1041 ixgbe_release_swfw_semaphore(hw, mask); 1042 1043 /* 1044 * These ones are more tricky since they are common to all ports; but 1045 * swfw_sync retries last long enough (1s) to be almost sure that if 1046 * lock can not be taken it is due to an improper lock of the 1047 * semaphore. 1048 */ 1049 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM; 1050 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1051 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 1052 } 1053 ixgbe_release_swfw_semaphore(hw, mask); 1054 } 1055 1056 /* 1057 * This function is based on code in ixgbe_attach() in base/ixgbe.c. 1058 * It returns 0 on success. 1059 */ 1060 static int 1061 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) 1062 { 1063 struct ixgbe_adapter *ad = eth_dev->data->dev_private; 1064 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1065 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1066 struct ixgbe_hw *hw = 1067 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1068 struct ixgbe_vfta *shadow_vfta = 1069 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1070 struct ixgbe_hwstrip *hwstrip = 1071 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1072 struct ixgbe_dcb_config *dcb_config = 1073 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private); 1074 struct ixgbe_filter_info *filter_info = 1075 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1076 struct ixgbe_bw_conf *bw_conf = 1077 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private); 1078 uint32_t ctrl_ext; 1079 uint16_t csum; 1080 int diag, i; 1081 1082 PMD_INIT_FUNC_TRACE(); 1083 1084 ixgbe_dev_macsec_setting_reset(eth_dev); 1085 1086 eth_dev->dev_ops = &ixgbe_eth_dev_ops; 1087 eth_dev->rx_queue_count = ixgbe_dev_rx_queue_count; 1088 eth_dev->rx_descriptor_done = ixgbe_dev_rx_descriptor_done; 1089 eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status; 1090 eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status; 1091 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1092 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1093 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts; 1094 1095 /* 1096 * For secondary processes, we don't initialise any further as primary 1097 * has already done this work. Only check we don't need a different 1098 * RX and TX function. 1099 */ 1100 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1101 struct ixgbe_tx_queue *txq; 1102 /* TX queue function in primary, set by last queue initialized 1103 * Tx queue may not initialized by primary process 1104 */ 1105 if (eth_dev->data->tx_queues) { 1106 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1]; 1107 ixgbe_set_tx_function(eth_dev, txq); 1108 } else { 1109 /* Use default TX function if we get here */ 1110 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. " 1111 "Using default TX function."); 1112 } 1113 1114 ixgbe_set_rx_function(eth_dev); 1115 1116 return 0; 1117 } 1118 1119 rte_atomic32_clear(&ad->link_thread_running); 1120 rte_eth_copy_pci_info(eth_dev, pci_dev); 1121 1122 /* Vendor and Device ID need to be set before init of shared code */ 1123 hw->device_id = pci_dev->id.device_id; 1124 hw->vendor_id = pci_dev->id.vendor_id; 1125 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1126 hw->allow_unsupported_sfp = 1; 1127 1128 /* Initialize the shared code (base driver) */ 1129 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1130 diag = ixgbe_bypass_init_shared_code(hw); 1131 #else 1132 diag = ixgbe_init_shared_code(hw); 1133 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1134 1135 if (diag != IXGBE_SUCCESS) { 1136 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag); 1137 return -EIO; 1138 } 1139 1140 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 1141 PMD_INIT_LOG(ERR, "\nERROR: " 1142 "Firmware recovery mode detected. Limiting functionality.\n" 1143 "Refer to the Intel(R) Ethernet Adapters and Devices " 1144 "User Guide for details on firmware recovery mode."); 1145 return -EIO; 1146 } 1147 1148 /* pick up the PCI bus settings for reporting later */ 1149 ixgbe_get_bus_info(hw); 1150 1151 /* Unlock any pending hardware semaphore */ 1152 ixgbe_swfw_lock_reset(hw); 1153 1154 #ifdef RTE_LIBRTE_SECURITY 1155 /* Initialize security_ctx only for primary process*/ 1156 if (ixgbe_ipsec_ctx_create(eth_dev)) 1157 return -ENOMEM; 1158 #endif 1159 1160 /* Initialize DCB configuration*/ 1161 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config)); 1162 ixgbe_dcb_init(hw, dcb_config); 1163 /* Get Hardware Flow Control setting */ 1164 hw->fc.requested_mode = ixgbe_fc_none; 1165 hw->fc.current_mode = ixgbe_fc_none; 1166 hw->fc.pause_time = IXGBE_FC_PAUSE; 1167 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 1168 hw->fc.low_water[i] = IXGBE_FC_LO; 1169 hw->fc.high_water[i] = IXGBE_FC_HI; 1170 } 1171 hw->fc.send_xon = 1; 1172 1173 /* Make sure we have a good EEPROM before we read from it */ 1174 diag = ixgbe_validate_eeprom_checksum(hw, &csum); 1175 if (diag != IXGBE_SUCCESS) { 1176 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag); 1177 return -EIO; 1178 } 1179 1180 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1181 diag = ixgbe_bypass_init_hw(hw); 1182 #else 1183 diag = ixgbe_init_hw(hw); 1184 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1185 1186 /* 1187 * Devices with copper phys will fail to initialise if ixgbe_init_hw() 1188 * is called too soon after the kernel driver unbinding/binding occurs. 1189 * The failure occurs in ixgbe_identify_phy_generic() for all devices, 1190 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is 1191 * also called. See ixgbe_identify_phy_82599(). The reason for the 1192 * failure is not known, and only occuts when virtualisation features 1193 * are disabled in the bios. A delay of 100ms was found to be enough by 1194 * trial-and-error, and is doubled to be safe. 1195 */ 1196 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) { 1197 rte_delay_ms(200); 1198 diag = ixgbe_init_hw(hw); 1199 } 1200 1201 if (diag == IXGBE_ERR_SFP_NOT_PRESENT) 1202 diag = IXGBE_SUCCESS; 1203 1204 if (diag == IXGBE_ERR_EEPROM_VERSION) { 1205 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/" 1206 "LOM. Please be aware there may be issues associated " 1207 "with your hardware."); 1208 PMD_INIT_LOG(ERR, "If you are experiencing problems " 1209 "please contact your Intel or hardware representative " 1210 "who provided you with this hardware."); 1211 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED) 1212 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module"); 1213 if (diag) { 1214 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag); 1215 return -EIO; 1216 } 1217 1218 /* Reset the hw statistics */ 1219 ixgbe_dev_stats_reset(eth_dev); 1220 1221 /* disable interrupt */ 1222 ixgbe_disable_intr(hw); 1223 1224 /* reset mappings for queue statistics hw counters*/ 1225 ixgbe_reset_qstat_mappings(hw); 1226 1227 /* Allocate memory for storing MAC addresses */ 1228 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN * 1229 hw->mac.num_rar_entries, 0); 1230 if (eth_dev->data->mac_addrs == NULL) { 1231 PMD_INIT_LOG(ERR, 1232 "Failed to allocate %u bytes needed to store " 1233 "MAC addresses", 1234 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1235 return -ENOMEM; 1236 } 1237 /* Copy the permanent MAC address */ 1238 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr, 1239 ð_dev->data->mac_addrs[0]); 1240 1241 /* Allocate memory for storing hash filter MAC addresses */ 1242 eth_dev->data->hash_mac_addrs = rte_zmalloc( 1243 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0); 1244 if (eth_dev->data->hash_mac_addrs == NULL) { 1245 PMD_INIT_LOG(ERR, 1246 "Failed to allocate %d bytes needed to store MAC addresses", 1247 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC); 1248 return -ENOMEM; 1249 } 1250 1251 /* Pass the information to the rte_eth_dev_close() that it should also 1252 * release the private port resources. 1253 */ 1254 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1255 1256 /* initialize the vfta */ 1257 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1258 1259 /* initialize the hw strip bitmap*/ 1260 memset(hwstrip, 0, sizeof(*hwstrip)); 1261 1262 /* initialize PF if max_vfs not zero */ 1263 ixgbe_pf_host_init(eth_dev); 1264 1265 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 1266 /* let hardware know driver is loaded */ 1267 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD; 1268 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 1269 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 1270 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 1271 IXGBE_WRITE_FLUSH(hw); 1272 1273 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 1274 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d", 1275 (int) hw->mac.type, (int) hw->phy.type, 1276 (int) hw->phy.sfp_type); 1277 else 1278 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d", 1279 (int) hw->mac.type, (int) hw->phy.type); 1280 1281 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 1282 eth_dev->data->port_id, pci_dev->id.vendor_id, 1283 pci_dev->id.device_id); 1284 1285 rte_intr_callback_register(intr_handle, 1286 ixgbe_dev_interrupt_handler, eth_dev); 1287 1288 /* enable uio/vfio intr/eventfd mapping */ 1289 rte_intr_enable(intr_handle); 1290 1291 /* enable support intr */ 1292 ixgbe_enable_intr(eth_dev); 1293 1294 /* initialize filter info */ 1295 memset(filter_info, 0, 1296 sizeof(struct ixgbe_filter_info)); 1297 1298 /* initialize 5tuple filter list */ 1299 TAILQ_INIT(&filter_info->fivetuple_list); 1300 1301 /* initialize flow director filter list & hash */ 1302 ixgbe_fdir_filter_init(eth_dev); 1303 1304 /* initialize l2 tunnel filter list & hash */ 1305 ixgbe_l2_tn_filter_init(eth_dev); 1306 1307 /* initialize flow filter lists */ 1308 ixgbe_filterlist_init(); 1309 1310 /* initialize bandwidth configuration info */ 1311 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf)); 1312 1313 /* initialize Traffic Manager configuration */ 1314 ixgbe_tm_conf_init(eth_dev); 1315 1316 return 0; 1317 } 1318 1319 static int 1320 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1321 { 1322 PMD_INIT_FUNC_TRACE(); 1323 1324 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1325 return 0; 1326 1327 ixgbe_dev_close(eth_dev); 1328 1329 return 0; 1330 } 1331 1332 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev) 1333 { 1334 struct ixgbe_filter_info *filter_info = 1335 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1336 struct ixgbe_5tuple_filter *p_5tuple; 1337 1338 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) { 1339 TAILQ_REMOVE(&filter_info->fivetuple_list, 1340 p_5tuple, 1341 entries); 1342 rte_free(p_5tuple); 1343 } 1344 memset(filter_info->fivetuple_mask, 0, 1345 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE); 1346 1347 return 0; 1348 } 1349 1350 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev) 1351 { 1352 struct ixgbe_hw_fdir_info *fdir_info = 1353 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1354 struct ixgbe_fdir_filter *fdir_filter; 1355 1356 if (fdir_info->hash_map) 1357 rte_free(fdir_info->hash_map); 1358 if (fdir_info->hash_handle) 1359 rte_hash_free(fdir_info->hash_handle); 1360 1361 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 1362 TAILQ_REMOVE(&fdir_info->fdir_list, 1363 fdir_filter, 1364 entries); 1365 rte_free(fdir_filter); 1366 } 1367 1368 return 0; 1369 } 1370 1371 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev) 1372 { 1373 struct ixgbe_l2_tn_info *l2_tn_info = 1374 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1375 struct ixgbe_l2_tn_filter *l2_tn_filter; 1376 1377 if (l2_tn_info->hash_map) 1378 rte_free(l2_tn_info->hash_map); 1379 if (l2_tn_info->hash_handle) 1380 rte_hash_free(l2_tn_info->hash_handle); 1381 1382 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 1383 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, 1384 l2_tn_filter, 1385 entries); 1386 rte_free(l2_tn_filter); 1387 } 1388 1389 return 0; 1390 } 1391 1392 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev) 1393 { 1394 struct ixgbe_hw_fdir_info *fdir_info = 1395 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1396 char fdir_hash_name[RTE_HASH_NAMESIZE]; 1397 struct rte_hash_parameters fdir_hash_params = { 1398 .name = fdir_hash_name, 1399 .entries = IXGBE_MAX_FDIR_FILTER_NUM, 1400 .key_len = sizeof(union ixgbe_atr_input), 1401 .hash_func = rte_hash_crc, 1402 .hash_func_init_val = 0, 1403 .socket_id = rte_socket_id(), 1404 }; 1405 1406 TAILQ_INIT(&fdir_info->fdir_list); 1407 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 1408 "fdir_%s", eth_dev->device->name); 1409 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params); 1410 if (!fdir_info->hash_handle) { 1411 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 1412 return -EINVAL; 1413 } 1414 fdir_info->hash_map = rte_zmalloc("ixgbe", 1415 sizeof(struct ixgbe_fdir_filter *) * 1416 IXGBE_MAX_FDIR_FILTER_NUM, 1417 0); 1418 if (!fdir_info->hash_map) { 1419 PMD_INIT_LOG(ERR, 1420 "Failed to allocate memory for fdir hash map!"); 1421 return -ENOMEM; 1422 } 1423 fdir_info->mask_added = FALSE; 1424 1425 return 0; 1426 } 1427 1428 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) 1429 { 1430 struct ixgbe_l2_tn_info *l2_tn_info = 1431 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1432 char l2_tn_hash_name[RTE_HASH_NAMESIZE]; 1433 struct rte_hash_parameters l2_tn_hash_params = { 1434 .name = l2_tn_hash_name, 1435 .entries = IXGBE_MAX_L2_TN_FILTER_NUM, 1436 .key_len = sizeof(struct ixgbe_l2_tn_key), 1437 .hash_func = rte_hash_crc, 1438 .hash_func_init_val = 0, 1439 .socket_id = rte_socket_id(), 1440 }; 1441 1442 TAILQ_INIT(&l2_tn_info->l2_tn_list); 1443 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE, 1444 "l2_tn_%s", eth_dev->device->name); 1445 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params); 1446 if (!l2_tn_info->hash_handle) { 1447 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!"); 1448 return -EINVAL; 1449 } 1450 l2_tn_info->hash_map = rte_zmalloc("ixgbe", 1451 sizeof(struct ixgbe_l2_tn_filter *) * 1452 IXGBE_MAX_L2_TN_FILTER_NUM, 1453 0); 1454 if (!l2_tn_info->hash_map) { 1455 PMD_INIT_LOG(ERR, 1456 "Failed to allocate memory for L2 TN hash map!"); 1457 return -ENOMEM; 1458 } 1459 l2_tn_info->e_tag_en = FALSE; 1460 l2_tn_info->e_tag_fwd_en = FALSE; 1461 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG; 1462 1463 return 0; 1464 } 1465 /* 1466 * Negotiate mailbox API version with the PF. 1467 * After reset API version is always set to the basic one (ixgbe_mbox_api_10). 1468 * Then we try to negotiate starting with the most recent one. 1469 * If all negotiation attempts fail, then we will proceed with 1470 * the default one (ixgbe_mbox_api_10). 1471 */ 1472 static void 1473 ixgbevf_negotiate_api(struct ixgbe_hw *hw) 1474 { 1475 int32_t i; 1476 1477 /* start with highest supported, proceed down */ 1478 static const enum ixgbe_pfvf_api_rev sup_ver[] = { 1479 ixgbe_mbox_api_13, 1480 ixgbe_mbox_api_12, 1481 ixgbe_mbox_api_11, 1482 ixgbe_mbox_api_10, 1483 }; 1484 1485 for (i = 0; 1486 i != RTE_DIM(sup_ver) && 1487 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0; 1488 i++) 1489 ; 1490 } 1491 1492 static void 1493 generate_random_mac_addr(struct rte_ether_addr *mac_addr) 1494 { 1495 uint64_t random; 1496 1497 /* Set Organizationally Unique Identifier (OUI) prefix. */ 1498 mac_addr->addr_bytes[0] = 0x00; 1499 mac_addr->addr_bytes[1] = 0x09; 1500 mac_addr->addr_bytes[2] = 0xC0; 1501 /* Force indication of locally assigned MAC address. */ 1502 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR; 1503 /* Generate the last 3 bytes of the MAC address with a random number. */ 1504 random = rte_rand(); 1505 memcpy(&mac_addr->addr_bytes[3], &random, 3); 1506 } 1507 1508 static int 1509 devarg_handle_int(__rte_unused const char *key, const char *value, 1510 void *extra_args) 1511 { 1512 uint16_t *n = extra_args; 1513 1514 if (value == NULL || extra_args == NULL) 1515 return -EINVAL; 1516 1517 *n = (uint16_t)strtoul(value, NULL, 0); 1518 if (*n == USHRT_MAX && errno == ERANGE) 1519 return -1; 1520 1521 return 0; 1522 } 1523 1524 static void 1525 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter, 1526 struct rte_devargs *devargs) 1527 { 1528 struct rte_kvargs *kvlist; 1529 uint16_t pflink_fullchk; 1530 1531 if (devargs == NULL) 1532 return; 1533 1534 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments); 1535 if (kvlist == NULL) 1536 return; 1537 1538 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 && 1539 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK, 1540 devarg_handle_int, &pflink_fullchk) == 0 && 1541 pflink_fullchk == 1) 1542 adapter->pflink_fullchk = 1; 1543 1544 rte_kvargs_free(kvlist); 1545 } 1546 1547 /* 1548 * Virtual Function device init 1549 */ 1550 static int 1551 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev) 1552 { 1553 int diag; 1554 uint32_t tc, tcs; 1555 struct ixgbe_adapter *ad = eth_dev->data->dev_private; 1556 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1557 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1558 struct ixgbe_hw *hw = 1559 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1560 struct ixgbe_vfta *shadow_vfta = 1561 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1562 struct ixgbe_hwstrip *hwstrip = 1563 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1564 struct rte_ether_addr *perm_addr = 1565 (struct rte_ether_addr *)hw->mac.perm_addr; 1566 1567 PMD_INIT_FUNC_TRACE(); 1568 1569 eth_dev->dev_ops = &ixgbevf_eth_dev_ops; 1570 eth_dev->rx_descriptor_done = ixgbe_dev_rx_descriptor_done; 1571 eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status; 1572 eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status; 1573 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1574 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1575 1576 /* for secondary processes, we don't initialise any further as primary 1577 * has already done this work. Only check we don't need a different 1578 * RX function 1579 */ 1580 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1581 struct ixgbe_tx_queue *txq; 1582 /* TX queue function in primary, set by last queue initialized 1583 * Tx queue may not initialized by primary process 1584 */ 1585 if (eth_dev->data->tx_queues) { 1586 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1]; 1587 ixgbe_set_tx_function(eth_dev, txq); 1588 } else { 1589 /* Use default TX function if we get here */ 1590 PMD_INIT_LOG(NOTICE, 1591 "No TX queues configured yet. Using default TX function."); 1592 } 1593 1594 ixgbe_set_rx_function(eth_dev); 1595 1596 return 0; 1597 } 1598 1599 rte_atomic32_clear(&ad->link_thread_running); 1600 ixgbevf_parse_devargs(eth_dev->data->dev_private, 1601 pci_dev->device.devargs); 1602 1603 rte_eth_copy_pci_info(eth_dev, pci_dev); 1604 1605 hw->device_id = pci_dev->id.device_id; 1606 hw->vendor_id = pci_dev->id.vendor_id; 1607 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1608 1609 /* initialize the vfta */ 1610 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1611 1612 /* initialize the hw strip bitmap*/ 1613 memset(hwstrip, 0, sizeof(*hwstrip)); 1614 1615 /* Initialize the shared code (base driver) */ 1616 diag = ixgbe_init_shared_code(hw); 1617 if (diag != IXGBE_SUCCESS) { 1618 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag); 1619 return -EIO; 1620 } 1621 1622 /* init_mailbox_params */ 1623 hw->mbx.ops.init_params(hw); 1624 1625 /* Reset the hw statistics */ 1626 ixgbevf_dev_stats_reset(eth_dev); 1627 1628 /* Disable the interrupts for VF */ 1629 ixgbevf_intr_disable(eth_dev); 1630 1631 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */ 1632 diag = hw->mac.ops.reset_hw(hw); 1633 1634 /* 1635 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when 1636 * the underlying PF driver has not assigned a MAC address to the VF. 1637 * In this case, assign a random MAC address. 1638 */ 1639 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) { 1640 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1641 /* 1642 * This error code will be propagated to the app by 1643 * rte_eth_dev_reset, so use a public error code rather than 1644 * the internal-only IXGBE_ERR_RESET_FAILED 1645 */ 1646 return -EAGAIN; 1647 } 1648 1649 /* negotiate mailbox API version to use with the PF. */ 1650 ixgbevf_negotiate_api(hw); 1651 1652 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */ 1653 ixgbevf_get_queues(hw, &tcs, &tc); 1654 1655 /* Allocate memory for storing MAC addresses */ 1656 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN * 1657 hw->mac.num_rar_entries, 0); 1658 if (eth_dev->data->mac_addrs == NULL) { 1659 PMD_INIT_LOG(ERR, 1660 "Failed to allocate %u bytes needed to store " 1661 "MAC addresses", 1662 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1663 return -ENOMEM; 1664 } 1665 1666 /* Pass the information to the rte_eth_dev_close() that it should also 1667 * release the private port resources. 1668 */ 1669 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1670 1671 /* Generate a random MAC address, if none was assigned by PF. */ 1672 if (rte_is_zero_ether_addr(perm_addr)) { 1673 generate_random_mac_addr(perm_addr); 1674 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1); 1675 if (diag) { 1676 rte_free(eth_dev->data->mac_addrs); 1677 eth_dev->data->mac_addrs = NULL; 1678 return diag; 1679 } 1680 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF"); 1681 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address " 1682 "%02x:%02x:%02x:%02x:%02x:%02x", 1683 perm_addr->addr_bytes[0], 1684 perm_addr->addr_bytes[1], 1685 perm_addr->addr_bytes[2], 1686 perm_addr->addr_bytes[3], 1687 perm_addr->addr_bytes[4], 1688 perm_addr->addr_bytes[5]); 1689 } 1690 1691 /* Copy the permanent MAC address */ 1692 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]); 1693 1694 /* reset the hardware with the new settings */ 1695 diag = hw->mac.ops.start_hw(hw); 1696 switch (diag) { 1697 case 0: 1698 break; 1699 1700 default: 1701 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1702 return -EIO; 1703 } 1704 1705 rte_intr_callback_register(intr_handle, 1706 ixgbevf_dev_interrupt_handler, eth_dev); 1707 rte_intr_enable(intr_handle); 1708 ixgbevf_intr_enable(eth_dev); 1709 1710 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s", 1711 eth_dev->data->port_id, pci_dev->id.vendor_id, 1712 pci_dev->id.device_id, "ixgbe_mac_82599_vf"); 1713 1714 return 0; 1715 } 1716 1717 /* Virtual Function device uninit */ 1718 1719 static int 1720 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev) 1721 { 1722 PMD_INIT_FUNC_TRACE(); 1723 1724 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1725 return 0; 1726 1727 ixgbevf_dev_close(eth_dev); 1728 1729 return 0; 1730 } 1731 1732 static int 1733 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1734 struct rte_pci_device *pci_dev) 1735 { 1736 char name[RTE_ETH_NAME_MAX_LEN]; 1737 struct rte_eth_dev *pf_ethdev; 1738 struct rte_eth_devargs eth_da; 1739 int i, retval; 1740 1741 if (pci_dev->device.devargs) { 1742 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 1743 ð_da); 1744 if (retval) 1745 return retval; 1746 } else 1747 memset(ð_da, 0, sizeof(eth_da)); 1748 1749 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 1750 sizeof(struct ixgbe_adapter), 1751 eth_dev_pci_specific_init, pci_dev, 1752 eth_ixgbe_dev_init, NULL); 1753 1754 if (retval || eth_da.nb_representor_ports < 1) 1755 return retval; 1756 1757 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1758 if (pf_ethdev == NULL) 1759 return -ENODEV; 1760 1761 /* probe VF representor ports */ 1762 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1763 struct ixgbe_vf_info *vfinfo; 1764 struct ixgbe_vf_representor representor; 1765 1766 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA( 1767 pf_ethdev->data->dev_private); 1768 if (vfinfo == NULL) { 1769 PMD_DRV_LOG(ERR, 1770 "no virtual functions supported by PF"); 1771 break; 1772 } 1773 1774 representor.vf_id = eth_da.representor_ports[i]; 1775 representor.switch_domain_id = vfinfo->switch_domain_id; 1776 representor.pf_ethdev = pf_ethdev; 1777 1778 /* representor port net_bdf_port */ 1779 snprintf(name, sizeof(name), "net_%s_representor_%d", 1780 pci_dev->device.name, 1781 eth_da.representor_ports[i]); 1782 1783 retval = rte_eth_dev_create(&pci_dev->device, name, 1784 sizeof(struct ixgbe_vf_representor), NULL, NULL, 1785 ixgbe_vf_representor_init, &representor); 1786 1787 if (retval) 1788 PMD_DRV_LOG(ERR, "failed to create ixgbe vf " 1789 "representor %s.", name); 1790 } 1791 1792 return 0; 1793 } 1794 1795 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev) 1796 { 1797 struct rte_eth_dev *ethdev; 1798 1799 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1800 if (!ethdev) 1801 return 0; 1802 1803 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 1804 return rte_eth_dev_pci_generic_remove(pci_dev, 1805 ixgbe_vf_representor_uninit); 1806 else 1807 return rte_eth_dev_pci_generic_remove(pci_dev, 1808 eth_ixgbe_dev_uninit); 1809 } 1810 1811 static struct rte_pci_driver rte_ixgbe_pmd = { 1812 .id_table = pci_id_ixgbe_map, 1813 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1814 .probe = eth_ixgbe_pci_probe, 1815 .remove = eth_ixgbe_pci_remove, 1816 }; 1817 1818 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1819 struct rte_pci_device *pci_dev) 1820 { 1821 return rte_eth_dev_pci_generic_probe(pci_dev, 1822 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init); 1823 } 1824 1825 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev) 1826 { 1827 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit); 1828 } 1829 1830 /* 1831 * virtual function driver struct 1832 */ 1833 static struct rte_pci_driver rte_ixgbevf_pmd = { 1834 .id_table = pci_id_ixgbevf_map, 1835 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1836 .probe = eth_ixgbevf_pci_probe, 1837 .remove = eth_ixgbevf_pci_remove, 1838 }; 1839 1840 static int 1841 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1842 { 1843 struct ixgbe_hw *hw = 1844 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1845 struct ixgbe_vfta *shadow_vfta = 1846 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1847 uint32_t vfta; 1848 uint32_t vid_idx; 1849 uint32_t vid_bit; 1850 1851 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 1852 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 1853 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx)); 1854 if (on) 1855 vfta |= vid_bit; 1856 else 1857 vfta &= ~vid_bit; 1858 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta); 1859 1860 /* update local VFTA copy */ 1861 shadow_vfta->vfta[vid_idx] = vfta; 1862 1863 return 0; 1864 } 1865 1866 static void 1867 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 1868 { 1869 if (on) 1870 ixgbe_vlan_hw_strip_enable(dev, queue); 1871 else 1872 ixgbe_vlan_hw_strip_disable(dev, queue); 1873 } 1874 1875 static int 1876 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1877 enum rte_vlan_type vlan_type, 1878 uint16_t tpid) 1879 { 1880 struct ixgbe_hw *hw = 1881 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1882 int ret = 0; 1883 uint32_t reg; 1884 uint32_t qinq; 1885 1886 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1887 qinq &= IXGBE_DMATXCTL_GDV; 1888 1889 switch (vlan_type) { 1890 case ETH_VLAN_TYPE_INNER: 1891 if (qinq) { 1892 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1893 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1894 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1895 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1896 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1897 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1898 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1899 } else { 1900 ret = -ENOTSUP; 1901 PMD_DRV_LOG(ERR, "Inner type is not supported" 1902 " by single VLAN"); 1903 } 1904 break; 1905 case ETH_VLAN_TYPE_OUTER: 1906 if (qinq) { 1907 /* Only the high 16-bits is valid */ 1908 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid << 1909 IXGBE_EXVET_VET_EXT_SHIFT); 1910 } else { 1911 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1912 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1913 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1914 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1915 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1916 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1917 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1918 } 1919 1920 break; 1921 default: 1922 ret = -EINVAL; 1923 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type); 1924 break; 1925 } 1926 1927 return ret; 1928 } 1929 1930 void 1931 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev) 1932 { 1933 struct ixgbe_hw *hw = 1934 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1935 uint32_t vlnctrl; 1936 1937 PMD_INIT_FUNC_TRACE(); 1938 1939 /* Filter Table Disable */ 1940 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1941 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 1942 1943 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1944 } 1945 1946 void 1947 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1948 { 1949 struct ixgbe_hw *hw = 1950 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1951 struct ixgbe_vfta *shadow_vfta = 1952 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1953 uint32_t vlnctrl; 1954 uint16_t i; 1955 1956 PMD_INIT_FUNC_TRACE(); 1957 1958 /* Filter Table Enable */ 1959 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1960 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; 1961 vlnctrl |= IXGBE_VLNCTRL_VFE; 1962 1963 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1964 1965 /* write whatever is in local vfta copy */ 1966 for (i = 0; i < IXGBE_VFTA_SIZE; i++) 1967 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]); 1968 } 1969 1970 static void 1971 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on) 1972 { 1973 struct ixgbe_hwstrip *hwstrip = 1974 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private); 1975 struct ixgbe_rx_queue *rxq; 1976 1977 if (queue >= IXGBE_MAX_RX_QUEUE_NUM) 1978 return; 1979 1980 if (on) 1981 IXGBE_SET_HWSTRIP(hwstrip, queue); 1982 else 1983 IXGBE_CLEAR_HWSTRIP(hwstrip, queue); 1984 1985 if (queue >= dev->data->nb_rx_queues) 1986 return; 1987 1988 rxq = dev->data->rx_queues[queue]; 1989 1990 if (on) { 1991 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; 1992 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 1993 } else { 1994 rxq->vlan_flags = PKT_RX_VLAN; 1995 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 1996 } 1997 } 1998 1999 static void 2000 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue) 2001 { 2002 struct ixgbe_hw *hw = 2003 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2004 uint32_t ctrl; 2005 2006 PMD_INIT_FUNC_TRACE(); 2007 2008 if (hw->mac.type == ixgbe_mac_82598EB) { 2009 /* No queue level support */ 2010 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2011 return; 2012 } 2013 2014 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2015 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2016 ctrl &= ~IXGBE_RXDCTL_VME; 2017 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2018 2019 /* record those setting for HW strip per queue */ 2020 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0); 2021 } 2022 2023 static void 2024 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue) 2025 { 2026 struct ixgbe_hw *hw = 2027 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2028 uint32_t ctrl; 2029 2030 PMD_INIT_FUNC_TRACE(); 2031 2032 if (hw->mac.type == ixgbe_mac_82598EB) { 2033 /* No queue level supported */ 2034 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2035 return; 2036 } 2037 2038 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2039 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2040 ctrl |= IXGBE_RXDCTL_VME; 2041 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2042 2043 /* record those setting for HW strip per queue */ 2044 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1); 2045 } 2046 2047 static void 2048 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev) 2049 { 2050 struct ixgbe_hw *hw = 2051 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2052 uint32_t ctrl; 2053 2054 PMD_INIT_FUNC_TRACE(); 2055 2056 /* DMATXCTRL: Geric Double VLAN Disable */ 2057 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2058 ctrl &= ~IXGBE_DMATXCTL_GDV; 2059 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2060 2061 /* CTRL_EXT: Global Double VLAN Disable */ 2062 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2063 ctrl &= ~IXGBE_EXTENDED_VLAN; 2064 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2065 2066 } 2067 2068 static void 2069 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) 2070 { 2071 struct ixgbe_hw *hw = 2072 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2073 uint32_t ctrl; 2074 2075 PMD_INIT_FUNC_TRACE(); 2076 2077 /* DMATXCTRL: Geric Double VLAN Enable */ 2078 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2079 ctrl |= IXGBE_DMATXCTL_GDV; 2080 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2081 2082 /* CTRL_EXT: Global Double VLAN Enable */ 2083 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2084 ctrl |= IXGBE_EXTENDED_VLAN; 2085 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2086 2087 /* Clear pooling mode of PFVTCTL. It's required by X550. */ 2088 if (hw->mac.type == ixgbe_mac_X550 || 2089 hw->mac.type == ixgbe_mac_X550EM_x || 2090 hw->mac.type == ixgbe_mac_X550EM_a) { 2091 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 2092 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 2093 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 2094 } 2095 2096 /* 2097 * VET EXT field in the EXVET register = 0x8100 by default 2098 * So no need to change. Same to VT field of DMATXCTL register 2099 */ 2100 } 2101 2102 void 2103 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev) 2104 { 2105 struct ixgbe_hw *hw = 2106 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2107 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 2108 uint32_t ctrl; 2109 uint16_t i; 2110 struct ixgbe_rx_queue *rxq; 2111 bool on; 2112 2113 PMD_INIT_FUNC_TRACE(); 2114 2115 if (hw->mac.type == ixgbe_mac_82598EB) { 2116 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2117 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2118 ctrl |= IXGBE_VLNCTRL_VME; 2119 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2120 } else { 2121 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2122 ctrl &= ~IXGBE_VLNCTRL_VME; 2123 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2124 } 2125 } else { 2126 /* 2127 * Other 10G NIC, the VLAN strip can be setup 2128 * per queue in RXDCTL 2129 */ 2130 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2131 rxq = dev->data->rx_queues[i]; 2132 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx)); 2133 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2134 ctrl |= IXGBE_RXDCTL_VME; 2135 on = TRUE; 2136 } else { 2137 ctrl &= ~IXGBE_RXDCTL_VME; 2138 on = FALSE; 2139 } 2140 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl); 2141 2142 /* record those setting for HW strip per queue */ 2143 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on); 2144 } 2145 } 2146 } 2147 2148 static void 2149 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask) 2150 { 2151 uint16_t i; 2152 struct rte_eth_rxmode *rxmode; 2153 struct ixgbe_rx_queue *rxq; 2154 2155 if (mask & ETH_VLAN_STRIP_MASK) { 2156 rxmode = &dev->data->dev_conf.rxmode; 2157 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 2158 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2159 rxq = dev->data->rx_queues[i]; 2160 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 2161 } 2162 else 2163 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2164 rxq = dev->data->rx_queues[i]; 2165 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 2166 } 2167 } 2168 } 2169 2170 static int 2171 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask) 2172 { 2173 struct rte_eth_rxmode *rxmode; 2174 rxmode = &dev->data->dev_conf.rxmode; 2175 2176 if (mask & ETH_VLAN_STRIP_MASK) { 2177 ixgbe_vlan_hw_strip_config(dev); 2178 } 2179 2180 if (mask & ETH_VLAN_FILTER_MASK) { 2181 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 2182 ixgbe_vlan_hw_filter_enable(dev); 2183 else 2184 ixgbe_vlan_hw_filter_disable(dev); 2185 } 2186 2187 if (mask & ETH_VLAN_EXTEND_MASK) { 2188 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2189 ixgbe_vlan_hw_extend_enable(dev); 2190 else 2191 ixgbe_vlan_hw_extend_disable(dev); 2192 } 2193 2194 return 0; 2195 } 2196 2197 static int 2198 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2199 { 2200 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 2201 2202 ixgbe_vlan_offload_config(dev, mask); 2203 2204 return 0; 2205 } 2206 2207 static void 2208 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev) 2209 { 2210 struct ixgbe_hw *hw = 2211 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2212 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */ 2213 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2214 2215 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */ 2216 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl); 2217 } 2218 2219 static int 2220 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q) 2221 { 2222 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2223 2224 switch (nb_rx_q) { 2225 case 1: 2226 case 2: 2227 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS; 2228 break; 2229 case 4: 2230 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS; 2231 break; 2232 default: 2233 return -EINVAL; 2234 } 2235 2236 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 2237 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2238 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 2239 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2240 return 0; 2241 } 2242 2243 static int 2244 ixgbe_check_mq_mode(struct rte_eth_dev *dev) 2245 { 2246 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 2247 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2248 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2249 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2250 2251 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 2252 /* check multi-queue mode */ 2253 switch (dev_conf->rxmode.mq_mode) { 2254 case ETH_MQ_RX_VMDQ_DCB: 2255 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV"); 2256 break; 2257 case ETH_MQ_RX_VMDQ_DCB_RSS: 2258 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */ 2259 PMD_INIT_LOG(ERR, "SRIOV active," 2260 " unsupported mq_mode rx %d.", 2261 dev_conf->rxmode.mq_mode); 2262 return -EINVAL; 2263 case ETH_MQ_RX_RSS: 2264 case ETH_MQ_RX_VMDQ_RSS: 2265 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS; 2266 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) 2267 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) { 2268 PMD_INIT_LOG(ERR, "SRIOV is active," 2269 " invalid queue number" 2270 " for VMDQ RSS, allowed" 2271 " value are 1, 2 or 4."); 2272 return -EINVAL; 2273 } 2274 break; 2275 case ETH_MQ_RX_VMDQ_ONLY: 2276 case ETH_MQ_RX_NONE: 2277 /* if nothing mq mode configure, use default scheme */ 2278 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY; 2279 break; 2280 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/ 2281 /* SRIOV only works in VMDq enable mode */ 2282 PMD_INIT_LOG(ERR, "SRIOV is active," 2283 " wrong mq_mode rx %d.", 2284 dev_conf->rxmode.mq_mode); 2285 return -EINVAL; 2286 } 2287 2288 switch (dev_conf->txmode.mq_mode) { 2289 case ETH_MQ_TX_VMDQ_DCB: 2290 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV"); 2291 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB; 2292 break; 2293 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */ 2294 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY; 2295 break; 2296 } 2297 2298 /* check valid queue number */ 2299 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) || 2300 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) { 2301 PMD_INIT_LOG(ERR, "SRIOV is active," 2302 " nb_rx_q=%d nb_tx_q=%d queue number" 2303 " must be less than or equal to %d.", 2304 nb_rx_q, nb_tx_q, 2305 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool); 2306 return -EINVAL; 2307 } 2308 } else { 2309 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) { 2310 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is" 2311 " not supported."); 2312 return -EINVAL; 2313 } 2314 /* check configuration for vmdb+dcb mode */ 2315 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) { 2316 const struct rte_eth_vmdq_dcb_conf *conf; 2317 2318 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2319 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.", 2320 IXGBE_VMDQ_DCB_NB_QUEUES); 2321 return -EINVAL; 2322 } 2323 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf; 2324 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2325 conf->nb_queue_pools == ETH_32_POOLS)) { 2326 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2327 " nb_queue_pools must be %d or %d.", 2328 ETH_16_POOLS, ETH_32_POOLS); 2329 return -EINVAL; 2330 } 2331 } 2332 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) { 2333 const struct rte_eth_vmdq_dcb_tx_conf *conf; 2334 2335 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2336 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d", 2337 IXGBE_VMDQ_DCB_NB_QUEUES); 2338 return -EINVAL; 2339 } 2340 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf; 2341 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2342 conf->nb_queue_pools == ETH_32_POOLS)) { 2343 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2344 " nb_queue_pools != %d and" 2345 " nb_queue_pools != %d.", 2346 ETH_16_POOLS, ETH_32_POOLS); 2347 return -EINVAL; 2348 } 2349 } 2350 2351 /* For DCB mode check our configuration before we go further */ 2352 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) { 2353 const struct rte_eth_dcb_rx_conf *conf; 2354 2355 conf = &dev_conf->rx_adv_conf.dcb_rx_conf; 2356 if (!(conf->nb_tcs == ETH_4_TCS || 2357 conf->nb_tcs == ETH_8_TCS)) { 2358 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2359 " and nb_tcs != %d.", 2360 ETH_4_TCS, ETH_8_TCS); 2361 return -EINVAL; 2362 } 2363 } 2364 2365 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) { 2366 const struct rte_eth_dcb_tx_conf *conf; 2367 2368 conf = &dev_conf->tx_adv_conf.dcb_tx_conf; 2369 if (!(conf->nb_tcs == ETH_4_TCS || 2370 conf->nb_tcs == ETH_8_TCS)) { 2371 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2372 " and nb_tcs != %d.", 2373 ETH_4_TCS, ETH_8_TCS); 2374 return -EINVAL; 2375 } 2376 } 2377 2378 /* 2379 * When DCB/VT is off, maximum number of queues changes, 2380 * except for 82598EB, which remains constant. 2381 */ 2382 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 2383 hw->mac.type != ixgbe_mac_82598EB) { 2384 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) { 2385 PMD_INIT_LOG(ERR, 2386 "Neither VT nor DCB are enabled, " 2387 "nb_tx_q > %d.", 2388 IXGBE_NONE_MODE_TX_NB_QUEUES); 2389 return -EINVAL; 2390 } 2391 } 2392 } 2393 return 0; 2394 } 2395 2396 static int 2397 ixgbe_dev_configure(struct rte_eth_dev *dev) 2398 { 2399 struct ixgbe_interrupt *intr = 2400 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2401 struct ixgbe_adapter *adapter = dev->data->dev_private; 2402 int ret; 2403 2404 PMD_INIT_FUNC_TRACE(); 2405 2406 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 2407 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 2408 2409 /* multipe queue mode checking */ 2410 ret = ixgbe_check_mq_mode(dev); 2411 if (ret != 0) { 2412 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.", 2413 ret); 2414 return ret; 2415 } 2416 2417 /* set flag to update link status after init */ 2418 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2419 2420 /* 2421 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 2422 * allocation or vector Rx preconditions we will reset it. 2423 */ 2424 adapter->rx_bulk_alloc_allowed = true; 2425 adapter->rx_vec_allowed = true; 2426 2427 return 0; 2428 } 2429 2430 static void 2431 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) 2432 { 2433 struct ixgbe_hw *hw = 2434 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2435 struct ixgbe_interrupt *intr = 2436 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2437 uint32_t gpie; 2438 2439 /* only set up it on X550EM_X */ 2440 if (hw->mac.type == ixgbe_mac_X550EM_x) { 2441 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 2442 gpie |= IXGBE_SDP0_GPIEN_X550EM_x; 2443 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 2444 if (hw->phy.type == ixgbe_phy_x550em_ext_t) 2445 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x; 2446 } 2447 } 2448 2449 int 2450 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 2451 uint16_t tx_rate, uint64_t q_msk) 2452 { 2453 struct ixgbe_hw *hw; 2454 struct ixgbe_vf_info *vfinfo; 2455 struct rte_eth_link link; 2456 uint8_t nb_q_per_pool; 2457 uint32_t queue_stride; 2458 uint32_t queue_idx, idx = 0, vf_idx; 2459 uint32_t queue_end; 2460 uint16_t total_rate = 0; 2461 struct rte_pci_device *pci_dev; 2462 int ret; 2463 2464 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2465 ret = rte_eth_link_get_nowait(dev->data->port_id, &link); 2466 if (ret < 0) 2467 return ret; 2468 2469 if (vf >= pci_dev->max_vfs) 2470 return -EINVAL; 2471 2472 if (tx_rate > link.link_speed) 2473 return -EINVAL; 2474 2475 if (q_msk == 0) 2476 return 0; 2477 2478 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2479 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 2480 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2481 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2482 queue_idx = vf * queue_stride; 2483 queue_end = queue_idx + nb_q_per_pool - 1; 2484 if (queue_end >= hw->mac.max_tx_queues) 2485 return -EINVAL; 2486 2487 if (vfinfo) { 2488 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) { 2489 if (vf_idx == vf) 2490 continue; 2491 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate); 2492 idx++) 2493 total_rate += vfinfo[vf_idx].tx_rate[idx]; 2494 } 2495 } else { 2496 return -EINVAL; 2497 } 2498 2499 /* Store tx_rate for this vf. */ 2500 for (idx = 0; idx < nb_q_per_pool; idx++) { 2501 if (((uint64_t)0x1 << idx) & q_msk) { 2502 if (vfinfo[vf].tx_rate[idx] != tx_rate) 2503 vfinfo[vf].tx_rate[idx] = tx_rate; 2504 total_rate += tx_rate; 2505 } 2506 } 2507 2508 if (total_rate > dev->data->dev_link.link_speed) { 2509 /* Reset stored TX rate of the VF if it causes exceed 2510 * link speed. 2511 */ 2512 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate)); 2513 return -EINVAL; 2514 } 2515 2516 /* Set RTTBCNRC of each queue/pool for vf X */ 2517 for (; queue_idx <= queue_end; queue_idx++) { 2518 if (0x1 & q_msk) 2519 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate); 2520 q_msk = q_msk >> 1; 2521 } 2522 2523 return 0; 2524 } 2525 2526 static int 2527 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw) 2528 { 2529 struct ixgbe_adapter *adapter = dev->data->dev_private; 2530 int err; 2531 uint32_t mflcn; 2532 2533 ixgbe_setup_fc(hw); 2534 2535 err = ixgbe_fc_enable(hw); 2536 2537 /* Not negotiated is not an error case */ 2538 if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) { 2539 /* 2540 *check if we want to forward MAC frames - driver doesn't 2541 *have native capability to do that, 2542 *so we'll write the registers ourselves 2543 */ 2544 2545 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2546 2547 /* set or clear MFLCN.PMCF bit depending on configuration */ 2548 if (adapter->mac_ctrl_frame_fwd != 0) 2549 mflcn |= IXGBE_MFLCN_PMCF; 2550 else 2551 mflcn &= ~IXGBE_MFLCN_PMCF; 2552 2553 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn); 2554 IXGBE_WRITE_FLUSH(hw); 2555 2556 return 0; 2557 } 2558 return err; 2559 } 2560 2561 /* 2562 * Configure device link speed and setup link. 2563 * It returns 0 on success. 2564 */ 2565 static int 2566 ixgbe_dev_start(struct rte_eth_dev *dev) 2567 { 2568 struct ixgbe_hw *hw = 2569 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2570 struct ixgbe_vf_info *vfinfo = 2571 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2572 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2573 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2574 uint32_t intr_vector = 0; 2575 int err; 2576 bool link_up = false, negotiate = 0; 2577 uint32_t speed = 0; 2578 uint32_t allowed_speeds = 0; 2579 int mask = 0; 2580 int status; 2581 uint16_t vf, idx; 2582 uint32_t *link_speeds; 2583 struct ixgbe_tm_conf *tm_conf = 2584 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2585 struct ixgbe_macsec_setting *macsec_setting = 2586 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 2587 2588 PMD_INIT_FUNC_TRACE(); 2589 2590 /* Stop the link setup handler before resetting the HW. */ 2591 ixgbe_dev_wait_setup_link_complete(dev, 0); 2592 2593 /* disable uio/vfio intr/eventfd mapping */ 2594 rte_intr_disable(intr_handle); 2595 2596 /* stop adapter */ 2597 hw->adapter_stopped = 0; 2598 ixgbe_stop_adapter(hw); 2599 2600 /* reinitialize adapter 2601 * this calls reset and start 2602 */ 2603 status = ixgbe_pf_reset_hw(hw); 2604 if (status != 0) 2605 return -1; 2606 hw->mac.ops.start_hw(hw); 2607 hw->mac.get_link_status = true; 2608 2609 /* configure PF module if SRIOV enabled */ 2610 ixgbe_pf_host_configure(dev); 2611 2612 ixgbe_dev_phy_intr_setup(dev); 2613 2614 /* check and configure queue intr-vector mapping */ 2615 if ((rte_intr_cap_multiple(intr_handle) || 2616 !RTE_ETH_DEV_SRIOV(dev).active) && 2617 dev->data->dev_conf.intr_conf.rxq != 0) { 2618 intr_vector = dev->data->nb_rx_queues; 2619 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) { 2620 PMD_INIT_LOG(ERR, "At most %d intr queues supported", 2621 IXGBE_MAX_INTR_QUEUE_NUM); 2622 return -ENOTSUP; 2623 } 2624 if (rte_intr_efd_enable(intr_handle, intr_vector)) 2625 return -1; 2626 } 2627 2628 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 2629 intr_handle->intr_vec = 2630 rte_zmalloc("intr_vec", 2631 dev->data->nb_rx_queues * sizeof(int), 0); 2632 if (intr_handle->intr_vec == NULL) { 2633 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 2634 " intr_vec", dev->data->nb_rx_queues); 2635 return -ENOMEM; 2636 } 2637 } 2638 2639 /* confiugre msix for sleep until rx interrupt */ 2640 ixgbe_configure_msix(dev); 2641 2642 /* initialize transmission unit */ 2643 ixgbe_dev_tx_init(dev); 2644 2645 /* This can fail when allocating mbufs for descriptor rings */ 2646 err = ixgbe_dev_rx_init(dev); 2647 if (err) { 2648 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 2649 goto error; 2650 } 2651 2652 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 2653 ETH_VLAN_EXTEND_MASK; 2654 err = ixgbe_vlan_offload_config(dev, mask); 2655 if (err) { 2656 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 2657 goto error; 2658 } 2659 2660 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) { 2661 /* Enable vlan filtering for VMDq */ 2662 ixgbe_vmdq_vlan_hw_filter_enable(dev); 2663 } 2664 2665 /* Configure DCB hw */ 2666 ixgbe_configure_dcb(dev); 2667 2668 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) { 2669 err = ixgbe_fdir_configure(dev); 2670 if (err) 2671 goto error; 2672 } 2673 2674 /* Restore vf rate limit */ 2675 if (vfinfo != NULL) { 2676 for (vf = 0; vf < pci_dev->max_vfs; vf++) 2677 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++) 2678 if (vfinfo[vf].tx_rate[idx] != 0) 2679 ixgbe_set_vf_rate_limit( 2680 dev, vf, 2681 vfinfo[vf].tx_rate[idx], 2682 1 << idx); 2683 } 2684 2685 ixgbe_restore_statistics_mapping(dev); 2686 2687 err = ixgbe_flow_ctrl_enable(dev, hw); 2688 if (err < 0) { 2689 PMD_INIT_LOG(ERR, "enable flow ctrl err"); 2690 goto error; 2691 } 2692 2693 err = ixgbe_dev_rxtx_start(dev); 2694 if (err < 0) { 2695 PMD_INIT_LOG(ERR, "Unable to start rxtx queues"); 2696 goto error; 2697 } 2698 2699 /* Skip link setup if loopback mode is enabled. */ 2700 if (dev->data->dev_conf.lpbk_mode != 0) { 2701 err = ixgbe_check_supported_loopback_mode(dev); 2702 if (err < 0) { 2703 PMD_INIT_LOG(ERR, "Unsupported loopback mode"); 2704 goto error; 2705 } else { 2706 goto skip_link_setup; 2707 } 2708 } 2709 2710 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) { 2711 err = hw->mac.ops.setup_sfp(hw); 2712 if (err) 2713 goto error; 2714 } 2715 2716 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2717 /* Turn on the copper */ 2718 ixgbe_set_phy_power(hw, true); 2719 } else { 2720 /* Turn on the laser */ 2721 ixgbe_enable_tx_laser(hw); 2722 } 2723 2724 err = ixgbe_check_link(hw, &speed, &link_up, 0); 2725 if (err) 2726 goto error; 2727 dev->data->dev_link.link_status = link_up; 2728 2729 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate); 2730 if (err) 2731 goto error; 2732 2733 switch (hw->mac.type) { 2734 case ixgbe_mac_X550: 2735 case ixgbe_mac_X550EM_x: 2736 case ixgbe_mac_X550EM_a: 2737 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2738 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G | 2739 ETH_LINK_SPEED_10G; 2740 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 2741 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 2742 allowed_speeds = ETH_LINK_SPEED_10M | 2743 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G; 2744 break; 2745 default: 2746 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2747 ETH_LINK_SPEED_10G; 2748 } 2749 2750 link_speeds = &dev->data->dev_conf.link_speeds; 2751 2752 /* Ignore autoneg flag bit and check the validity of 2753 * link_speed 2754 */ 2755 if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) { 2756 PMD_INIT_LOG(ERR, "Invalid link setting"); 2757 goto error; 2758 } 2759 2760 speed = 0x0; 2761 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) { 2762 switch (hw->mac.type) { 2763 case ixgbe_mac_82598EB: 2764 speed = IXGBE_LINK_SPEED_82598_AUTONEG; 2765 break; 2766 case ixgbe_mac_82599EB: 2767 case ixgbe_mac_X540: 2768 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2769 break; 2770 case ixgbe_mac_X550: 2771 case ixgbe_mac_X550EM_x: 2772 case ixgbe_mac_X550EM_a: 2773 speed = IXGBE_LINK_SPEED_X550_AUTONEG; 2774 break; 2775 default: 2776 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2777 } 2778 } else { 2779 if (*link_speeds & ETH_LINK_SPEED_10G) 2780 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2781 if (*link_speeds & ETH_LINK_SPEED_5G) 2782 speed |= IXGBE_LINK_SPEED_5GB_FULL; 2783 if (*link_speeds & ETH_LINK_SPEED_2_5G) 2784 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 2785 if (*link_speeds & ETH_LINK_SPEED_1G) 2786 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2787 if (*link_speeds & ETH_LINK_SPEED_100M) 2788 speed |= IXGBE_LINK_SPEED_100_FULL; 2789 if (*link_speeds & ETH_LINK_SPEED_10M) 2790 speed |= IXGBE_LINK_SPEED_10_FULL; 2791 } 2792 2793 err = ixgbe_setup_link(hw, speed, link_up); 2794 if (err) 2795 goto error; 2796 2797 skip_link_setup: 2798 2799 if (rte_intr_allow_others(intr_handle)) { 2800 /* check if lsc interrupt is enabled */ 2801 if (dev->data->dev_conf.intr_conf.lsc != 0) 2802 ixgbe_dev_lsc_interrupt_setup(dev, TRUE); 2803 else 2804 ixgbe_dev_lsc_interrupt_setup(dev, FALSE); 2805 ixgbe_dev_macsec_interrupt_setup(dev); 2806 } else { 2807 rte_intr_callback_unregister(intr_handle, 2808 ixgbe_dev_interrupt_handler, dev); 2809 if (dev->data->dev_conf.intr_conf.lsc != 0) 2810 PMD_INIT_LOG(INFO, "lsc won't enable because of" 2811 " no intr multiplex"); 2812 } 2813 2814 /* check if rxq interrupt is enabled */ 2815 if (dev->data->dev_conf.intr_conf.rxq != 0 && 2816 rte_intr_dp_is_en(intr_handle)) 2817 ixgbe_dev_rxq_interrupt_setup(dev); 2818 2819 /* enable uio/vfio intr/eventfd mapping */ 2820 rte_intr_enable(intr_handle); 2821 2822 /* resume enabled intr since hw reset */ 2823 ixgbe_enable_intr(dev); 2824 ixgbe_l2_tunnel_conf(dev); 2825 ixgbe_filter_restore(dev); 2826 2827 if (tm_conf->root && !tm_conf->committed) 2828 PMD_DRV_LOG(WARNING, 2829 "please call hierarchy_commit() " 2830 "before starting the port"); 2831 2832 /* wait for the controller to acquire link */ 2833 err = ixgbe_wait_for_link_up(hw); 2834 if (err) 2835 goto error; 2836 2837 /* 2838 * Update link status right before return, because it may 2839 * start link configuration process in a separate thread. 2840 */ 2841 ixgbe_dev_link_update(dev, 0); 2842 2843 /* setup the macsec setting register */ 2844 if (macsec_setting->offload_en) 2845 ixgbe_dev_macsec_register_enable(dev, macsec_setting); 2846 2847 return 0; 2848 2849 error: 2850 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err); 2851 ixgbe_dev_clear_queues(dev); 2852 return -EIO; 2853 } 2854 2855 /* 2856 * Stop device: disable rx and tx functions to allow for reconfiguring. 2857 */ 2858 static void 2859 ixgbe_dev_stop(struct rte_eth_dev *dev) 2860 { 2861 struct rte_eth_link link; 2862 struct ixgbe_adapter *adapter = dev->data->dev_private; 2863 struct ixgbe_hw *hw = 2864 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2865 struct ixgbe_vf_info *vfinfo = 2866 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2867 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2868 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2869 int vf; 2870 struct ixgbe_tm_conf *tm_conf = 2871 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2872 2873 if (hw->adapter_stopped) 2874 return; 2875 2876 PMD_INIT_FUNC_TRACE(); 2877 2878 ixgbe_dev_wait_setup_link_complete(dev, 0); 2879 2880 /* disable interrupts */ 2881 ixgbe_disable_intr(hw); 2882 2883 /* reset the NIC */ 2884 ixgbe_pf_reset_hw(hw); 2885 hw->adapter_stopped = 0; 2886 2887 /* stop adapter */ 2888 ixgbe_stop_adapter(hw); 2889 2890 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++) 2891 vfinfo[vf].clear_to_send = false; 2892 2893 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2894 /* Turn off the copper */ 2895 ixgbe_set_phy_power(hw, false); 2896 } else { 2897 /* Turn off the laser */ 2898 ixgbe_disable_tx_laser(hw); 2899 } 2900 2901 ixgbe_dev_clear_queues(dev); 2902 2903 /* Clear stored conf */ 2904 dev->data->scattered_rx = 0; 2905 dev->data->lro = 0; 2906 2907 /* Clear recorded link status */ 2908 memset(&link, 0, sizeof(link)); 2909 rte_eth_linkstatus_set(dev, &link); 2910 2911 if (!rte_intr_allow_others(intr_handle)) 2912 /* resume to the default handler */ 2913 rte_intr_callback_register(intr_handle, 2914 ixgbe_dev_interrupt_handler, 2915 (void *)dev); 2916 2917 /* Clean datapath event and queue/vec mapping */ 2918 rte_intr_efd_disable(intr_handle); 2919 if (intr_handle->intr_vec != NULL) { 2920 rte_free(intr_handle->intr_vec); 2921 intr_handle->intr_vec = NULL; 2922 } 2923 2924 /* reset hierarchy commit */ 2925 tm_conf->committed = false; 2926 2927 adapter->rss_reta_updated = 0; 2928 2929 hw->adapter_stopped = true; 2930 } 2931 2932 /* 2933 * Set device link up: enable tx. 2934 */ 2935 static int 2936 ixgbe_dev_set_link_up(struct rte_eth_dev *dev) 2937 { 2938 struct ixgbe_hw *hw = 2939 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2940 if (hw->mac.type == ixgbe_mac_82599EB) { 2941 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2942 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2943 /* Not suported in bypass mode */ 2944 PMD_INIT_LOG(ERR, "Set link up is not supported " 2945 "by device id 0x%x", hw->device_id); 2946 return -ENOTSUP; 2947 } 2948 #endif 2949 } 2950 2951 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2952 /* Turn on the copper */ 2953 ixgbe_set_phy_power(hw, true); 2954 } else { 2955 /* Turn on the laser */ 2956 ixgbe_enable_tx_laser(hw); 2957 ixgbe_dev_link_update(dev, 0); 2958 } 2959 2960 return 0; 2961 } 2962 2963 /* 2964 * Set device link down: disable tx. 2965 */ 2966 static int 2967 ixgbe_dev_set_link_down(struct rte_eth_dev *dev) 2968 { 2969 struct ixgbe_hw *hw = 2970 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2971 if (hw->mac.type == ixgbe_mac_82599EB) { 2972 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2973 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2974 /* Not suported in bypass mode */ 2975 PMD_INIT_LOG(ERR, "Set link down is not supported " 2976 "by device id 0x%x", hw->device_id); 2977 return -ENOTSUP; 2978 } 2979 #endif 2980 } 2981 2982 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2983 /* Turn off the copper */ 2984 ixgbe_set_phy_power(hw, false); 2985 } else { 2986 /* Turn off the laser */ 2987 ixgbe_disable_tx_laser(hw); 2988 ixgbe_dev_link_update(dev, 0); 2989 } 2990 2991 return 0; 2992 } 2993 2994 /* 2995 * Reset and stop device. 2996 */ 2997 static void 2998 ixgbe_dev_close(struct rte_eth_dev *dev) 2999 { 3000 struct ixgbe_hw *hw = 3001 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3002 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3003 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3004 int retries = 0; 3005 int ret; 3006 3007 PMD_INIT_FUNC_TRACE(); 3008 3009 ixgbe_pf_reset_hw(hw); 3010 3011 ixgbe_dev_stop(dev); 3012 3013 ixgbe_dev_free_queues(dev); 3014 3015 ixgbe_disable_pcie_master(hw); 3016 3017 /* reprogram the RAR[0] in case user changed it. */ 3018 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 3019 3020 dev->dev_ops = NULL; 3021 dev->rx_pkt_burst = NULL; 3022 dev->tx_pkt_burst = NULL; 3023 3024 /* Unlock any pending hardware semaphore */ 3025 ixgbe_swfw_lock_reset(hw); 3026 3027 /* disable uio intr before callback unregister */ 3028 rte_intr_disable(intr_handle); 3029 3030 do { 3031 ret = rte_intr_callback_unregister(intr_handle, 3032 ixgbe_dev_interrupt_handler, dev); 3033 if (ret >= 0 || ret == -ENOENT) { 3034 break; 3035 } else if (ret != -EAGAIN) { 3036 PMD_INIT_LOG(ERR, 3037 "intr callback unregister failed: %d", 3038 ret); 3039 } 3040 rte_delay_ms(100); 3041 } while (retries++ < (10 + IXGBE_LINK_UP_TIME)); 3042 3043 /* cancel the delay handler before remove dev */ 3044 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev); 3045 3046 /* uninitialize PF if max_vfs not zero */ 3047 ixgbe_pf_host_uninit(dev); 3048 3049 /* remove all the fdir filters & hash */ 3050 ixgbe_fdir_filter_uninit(dev); 3051 3052 /* remove all the L2 tunnel filters & hash */ 3053 ixgbe_l2_tn_filter_uninit(dev); 3054 3055 /* Remove all ntuple filters of the device */ 3056 ixgbe_ntuple_filter_uninit(dev); 3057 3058 /* clear all the filters list */ 3059 ixgbe_filterlist_flush(); 3060 3061 /* Remove all Traffic Manager configuration */ 3062 ixgbe_tm_conf_uninit(dev); 3063 3064 #ifdef RTE_LIBRTE_SECURITY 3065 rte_free(dev->security_ctx); 3066 #endif 3067 3068 } 3069 3070 /* 3071 * Reset PF device. 3072 */ 3073 static int 3074 ixgbe_dev_reset(struct rte_eth_dev *dev) 3075 { 3076 int ret; 3077 3078 /* When a DPDK PMD PF begin to reset PF port, it should notify all 3079 * its VF to make them align with it. The detailed notification 3080 * mechanism is PMD specific. As to ixgbe PF, it is rather complex. 3081 * To avoid unexpected behavior in VF, currently reset of PF with 3082 * SR-IOV activation is not supported. It might be supported later. 3083 */ 3084 if (dev->data->sriov.active) 3085 return -ENOTSUP; 3086 3087 ret = eth_ixgbe_dev_uninit(dev); 3088 if (ret) 3089 return ret; 3090 3091 ret = eth_ixgbe_dev_init(dev, NULL); 3092 3093 return ret; 3094 } 3095 3096 static void 3097 ixgbe_read_stats_registers(struct ixgbe_hw *hw, 3098 struct ixgbe_hw_stats *hw_stats, 3099 struct ixgbe_macsec_stats *macsec_stats, 3100 uint64_t *total_missed_rx, uint64_t *total_qbrc, 3101 uint64_t *total_qprc, uint64_t *total_qprdc) 3102 { 3103 uint32_t bprc, lxon, lxoff, total; 3104 uint32_t delta_gprc = 0; 3105 unsigned i; 3106 /* Workaround for RX byte count not including CRC bytes when CRC 3107 * strip is enabled. CRC bytes are removed from counters when crc_strip 3108 * is disabled. 3109 */ 3110 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) & 3111 IXGBE_HLREG0_RXCRCSTRP); 3112 3113 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 3114 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC); 3115 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC); 3116 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC); 3117 3118 for (i = 0; i < 8; i++) { 3119 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 3120 3121 /* global total per queue */ 3122 hw_stats->mpc[i] += mp; 3123 /* Running comprehensive total for stats display */ 3124 *total_missed_rx += hw_stats->mpc[i]; 3125 if (hw->mac.type == ixgbe_mac_82598EB) { 3126 hw_stats->rnbc[i] += 3127 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 3128 hw_stats->pxonrxc[i] += 3129 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 3130 hw_stats->pxoffrxc[i] += 3131 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 3132 } else { 3133 hw_stats->pxonrxc[i] += 3134 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 3135 hw_stats->pxoffrxc[i] += 3136 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 3137 hw_stats->pxon2offc[i] += 3138 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 3139 } 3140 hw_stats->pxontxc[i] += 3141 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 3142 hw_stats->pxofftxc[i] += 3143 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 3144 } 3145 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3146 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 3147 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 3148 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 3149 3150 delta_gprc += delta_qprc; 3151 3152 hw_stats->qprc[i] += delta_qprc; 3153 hw_stats->qptc[i] += delta_qptc; 3154 3155 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 3156 hw_stats->qbrc[i] += 3157 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32); 3158 if (crc_strip == 0) 3159 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN; 3160 3161 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 3162 hw_stats->qbtc[i] += 3163 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32); 3164 3165 hw_stats->qprdc[i] += delta_qprdc; 3166 *total_qprdc += hw_stats->qprdc[i]; 3167 3168 *total_qprc += hw_stats->qprc[i]; 3169 *total_qbrc += hw_stats->qbrc[i]; 3170 } 3171 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC); 3172 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC); 3173 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 3174 3175 /* 3176 * An errata states that gprc actually counts good + missed packets: 3177 * Workaround to set gprc to summated queue packet receives 3178 */ 3179 hw_stats->gprc = *total_qprc; 3180 3181 if (hw->mac.type != ixgbe_mac_82598EB) { 3182 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 3183 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32); 3184 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 3185 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32); 3186 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 3187 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32); 3188 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 3189 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 3190 } else { 3191 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 3192 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 3193 /* 82598 only has a counter in the high register */ 3194 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 3195 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 3196 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 3197 } 3198 uint64_t old_tpr = hw_stats->tpr; 3199 3200 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 3201 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT); 3202 3203 if (crc_strip == 0) 3204 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN; 3205 3206 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC); 3207 hw_stats->gptc += delta_gptc; 3208 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN; 3209 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN; 3210 3211 /* 3212 * Workaround: mprc hardware is incorrectly counting 3213 * broadcasts, so for now we subtract those. 3214 */ 3215 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 3216 hw_stats->bprc += bprc; 3217 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 3218 if (hw->mac.type == ixgbe_mac_82598EB) 3219 hw_stats->mprc -= bprc; 3220 3221 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 3222 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 3223 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 3224 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 3225 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 3226 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 3227 3228 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 3229 hw_stats->lxontxc += lxon; 3230 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 3231 hw_stats->lxofftxc += lxoff; 3232 total = lxon + lxoff; 3233 3234 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 3235 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 3236 hw_stats->gptc -= total; 3237 hw_stats->mptc -= total; 3238 hw_stats->ptc64 -= total; 3239 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN; 3240 3241 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 3242 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 3243 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 3244 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 3245 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC); 3246 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC); 3247 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC); 3248 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 3249 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 3250 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 3251 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 3252 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 3253 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 3254 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC); 3255 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 3256 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST); 3257 /* Only read FCOE on 82599 */ 3258 if (hw->mac.type != ixgbe_mac_82598EB) { 3259 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 3260 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 3261 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 3262 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 3263 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 3264 } 3265 3266 /* Flow Director Stats registers */ 3267 if (hw->mac.type != ixgbe_mac_82598EB) { 3268 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 3269 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 3270 hw_stats->fdirustat_add += IXGBE_READ_REG(hw, 3271 IXGBE_FDIRUSTAT) & 0xFFFF; 3272 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw, 3273 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF; 3274 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw, 3275 IXGBE_FDIRFSTAT) & 0xFFFF; 3276 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw, 3277 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF; 3278 } 3279 /* MACsec Stats registers */ 3280 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT); 3281 macsec_stats->out_pkts_encrypted += 3282 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE); 3283 macsec_stats->out_pkts_protected += 3284 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP); 3285 macsec_stats->out_octets_encrypted += 3286 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE); 3287 macsec_stats->out_octets_protected += 3288 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP); 3289 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT); 3290 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD); 3291 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI); 3292 macsec_stats->in_pkts_unknownsci += 3293 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI); 3294 macsec_stats->in_octets_decrypted += 3295 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD); 3296 macsec_stats->in_octets_validated += 3297 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV); 3298 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH); 3299 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY); 3300 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE); 3301 for (i = 0; i < 2; i++) { 3302 macsec_stats->in_pkts_ok += 3303 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i)); 3304 macsec_stats->in_pkts_invalid += 3305 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i)); 3306 macsec_stats->in_pkts_notvalid += 3307 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i)); 3308 } 3309 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA); 3310 macsec_stats->in_pkts_notusingsa += 3311 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA); 3312 } 3313 3314 /* 3315 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c 3316 */ 3317 static int 3318 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3319 { 3320 struct ixgbe_hw *hw = 3321 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3322 struct ixgbe_hw_stats *hw_stats = 3323 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3324 struct ixgbe_macsec_stats *macsec_stats = 3325 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3326 dev->data->dev_private); 3327 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3328 unsigned i; 3329 3330 total_missed_rx = 0; 3331 total_qbrc = 0; 3332 total_qprc = 0; 3333 total_qprdc = 0; 3334 3335 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3336 &total_qbrc, &total_qprc, &total_qprdc); 3337 3338 if (stats == NULL) 3339 return -EINVAL; 3340 3341 /* Fill out the rte_eth_stats statistics structure */ 3342 stats->ipackets = total_qprc; 3343 stats->ibytes = total_qbrc; 3344 stats->opackets = hw_stats->gptc; 3345 stats->obytes = hw_stats->gotc; 3346 3347 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3348 stats->q_ipackets[i] = hw_stats->qprc[i]; 3349 stats->q_opackets[i] = hw_stats->qptc[i]; 3350 stats->q_ibytes[i] = hw_stats->qbrc[i]; 3351 stats->q_obytes[i] = hw_stats->qbtc[i]; 3352 stats->q_errors[i] = hw_stats->qprdc[i]; 3353 } 3354 3355 /* Rx Errors */ 3356 stats->imissed = total_missed_rx; 3357 stats->ierrors = hw_stats->crcerrs + 3358 hw_stats->mspdc + 3359 hw_stats->rlec + 3360 hw_stats->ruc + 3361 hw_stats->roc + 3362 hw_stats->illerrc + 3363 hw_stats->errbc + 3364 hw_stats->rfc + 3365 hw_stats->fccrc + 3366 hw_stats->fclast; 3367 3368 /* Tx Errors */ 3369 stats->oerrors = 0; 3370 return 0; 3371 } 3372 3373 static int 3374 ixgbe_dev_stats_reset(struct rte_eth_dev *dev) 3375 { 3376 struct ixgbe_hw_stats *stats = 3377 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3378 3379 /* HW registers are cleared on read */ 3380 ixgbe_dev_stats_get(dev, NULL); 3381 3382 /* Reset software totals */ 3383 memset(stats, 0, sizeof(*stats)); 3384 3385 return 0; 3386 } 3387 3388 /* This function calculates the number of xstats based on the current config */ 3389 static unsigned 3390 ixgbe_xstats_calc_num(void) { 3391 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS + 3392 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) + 3393 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES); 3394 } 3395 3396 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3397 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size) 3398 { 3399 const unsigned cnt_stats = ixgbe_xstats_calc_num(); 3400 unsigned stat, i, count; 3401 3402 if (xstats_names != NULL) { 3403 count = 0; 3404 3405 /* Note: limit >= cnt_stats checked upstream 3406 * in rte_eth_xstats_names() 3407 */ 3408 3409 /* Extended stats from ixgbe_hw_stats */ 3410 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3411 strlcpy(xstats_names[count].name, 3412 rte_ixgbe_stats_strings[i].name, 3413 sizeof(xstats_names[count].name)); 3414 count++; 3415 } 3416 3417 /* MACsec Stats */ 3418 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3419 strlcpy(xstats_names[count].name, 3420 rte_ixgbe_macsec_strings[i].name, 3421 sizeof(xstats_names[count].name)); 3422 count++; 3423 } 3424 3425 /* RX Priority Stats */ 3426 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3427 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3428 snprintf(xstats_names[count].name, 3429 sizeof(xstats_names[count].name), 3430 "rx_priority%u_%s", i, 3431 rte_ixgbe_rxq_strings[stat].name); 3432 count++; 3433 } 3434 } 3435 3436 /* TX Priority Stats */ 3437 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3438 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3439 snprintf(xstats_names[count].name, 3440 sizeof(xstats_names[count].name), 3441 "tx_priority%u_%s", i, 3442 rte_ixgbe_txq_strings[stat].name); 3443 count++; 3444 } 3445 } 3446 } 3447 return cnt_stats; 3448 } 3449 3450 static int ixgbe_dev_xstats_get_names_by_id( 3451 struct rte_eth_dev *dev, 3452 struct rte_eth_xstat_name *xstats_names, 3453 const uint64_t *ids, 3454 unsigned int limit) 3455 { 3456 if (!ids) { 3457 const unsigned int cnt_stats = ixgbe_xstats_calc_num(); 3458 unsigned int stat, i, count; 3459 3460 if (xstats_names != NULL) { 3461 count = 0; 3462 3463 /* Note: limit >= cnt_stats checked upstream 3464 * in rte_eth_xstats_names() 3465 */ 3466 3467 /* Extended stats from ixgbe_hw_stats */ 3468 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3469 strlcpy(xstats_names[count].name, 3470 rte_ixgbe_stats_strings[i].name, 3471 sizeof(xstats_names[count].name)); 3472 count++; 3473 } 3474 3475 /* MACsec Stats */ 3476 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3477 strlcpy(xstats_names[count].name, 3478 rte_ixgbe_macsec_strings[i].name, 3479 sizeof(xstats_names[count].name)); 3480 count++; 3481 } 3482 3483 /* RX Priority Stats */ 3484 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3485 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3486 snprintf(xstats_names[count].name, 3487 sizeof(xstats_names[count].name), 3488 "rx_priority%u_%s", i, 3489 rte_ixgbe_rxq_strings[stat].name); 3490 count++; 3491 } 3492 } 3493 3494 /* TX Priority Stats */ 3495 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3496 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3497 snprintf(xstats_names[count].name, 3498 sizeof(xstats_names[count].name), 3499 "tx_priority%u_%s", i, 3500 rte_ixgbe_txq_strings[stat].name); 3501 count++; 3502 } 3503 } 3504 } 3505 return cnt_stats; 3506 } 3507 3508 uint16_t i; 3509 uint16_t size = ixgbe_xstats_calc_num(); 3510 struct rte_eth_xstat_name xstats_names_copy[size]; 3511 3512 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL, 3513 size); 3514 3515 for (i = 0; i < limit; i++) { 3516 if (ids[i] >= size) { 3517 PMD_INIT_LOG(ERR, "id value isn't valid"); 3518 return -1; 3519 } 3520 strcpy(xstats_names[i].name, 3521 xstats_names_copy[ids[i]].name); 3522 } 3523 return limit; 3524 } 3525 3526 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3527 struct rte_eth_xstat_name *xstats_names, unsigned limit) 3528 { 3529 unsigned i; 3530 3531 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL) 3532 return -ENOMEM; 3533 3534 if (xstats_names != NULL) 3535 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) 3536 strlcpy(xstats_names[i].name, 3537 rte_ixgbevf_stats_strings[i].name, 3538 sizeof(xstats_names[i].name)); 3539 return IXGBEVF_NB_XSTATS; 3540 } 3541 3542 static int 3543 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3544 unsigned n) 3545 { 3546 struct ixgbe_hw *hw = 3547 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3548 struct ixgbe_hw_stats *hw_stats = 3549 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3550 struct ixgbe_macsec_stats *macsec_stats = 3551 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3552 dev->data->dev_private); 3553 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3554 unsigned i, stat, count = 0; 3555 3556 count = ixgbe_xstats_calc_num(); 3557 3558 if (n < count) 3559 return count; 3560 3561 total_missed_rx = 0; 3562 total_qbrc = 0; 3563 total_qprc = 0; 3564 total_qprdc = 0; 3565 3566 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3567 &total_qbrc, &total_qprc, &total_qprdc); 3568 3569 /* If this is a reset xstats is NULL, and we have cleared the 3570 * registers by reading them. 3571 */ 3572 if (!xstats) 3573 return 0; 3574 3575 /* Extended stats from ixgbe_hw_stats */ 3576 count = 0; 3577 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3578 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3579 rte_ixgbe_stats_strings[i].offset); 3580 xstats[count].id = count; 3581 count++; 3582 } 3583 3584 /* MACsec Stats */ 3585 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3586 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) + 3587 rte_ixgbe_macsec_strings[i].offset); 3588 xstats[count].id = count; 3589 count++; 3590 } 3591 3592 /* RX Priority Stats */ 3593 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3594 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3595 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3596 rte_ixgbe_rxq_strings[stat].offset + 3597 (sizeof(uint64_t) * i)); 3598 xstats[count].id = count; 3599 count++; 3600 } 3601 } 3602 3603 /* TX Priority Stats */ 3604 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3605 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3606 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3607 rte_ixgbe_txq_strings[stat].offset + 3608 (sizeof(uint64_t) * i)); 3609 xstats[count].id = count; 3610 count++; 3611 } 3612 } 3613 return count; 3614 } 3615 3616 static int 3617 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 3618 uint64_t *values, unsigned int n) 3619 { 3620 if (!ids) { 3621 struct ixgbe_hw *hw = 3622 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3623 struct ixgbe_hw_stats *hw_stats = 3624 IXGBE_DEV_PRIVATE_TO_STATS( 3625 dev->data->dev_private); 3626 struct ixgbe_macsec_stats *macsec_stats = 3627 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3628 dev->data->dev_private); 3629 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3630 unsigned int i, stat, count = 0; 3631 3632 count = ixgbe_xstats_calc_num(); 3633 3634 if (!ids && n < count) 3635 return count; 3636 3637 total_missed_rx = 0; 3638 total_qbrc = 0; 3639 total_qprc = 0; 3640 total_qprdc = 0; 3641 3642 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, 3643 &total_missed_rx, &total_qbrc, &total_qprc, 3644 &total_qprdc); 3645 3646 /* If this is a reset xstats is NULL, and we have cleared the 3647 * registers by reading them. 3648 */ 3649 if (!ids && !values) 3650 return 0; 3651 3652 /* Extended stats from ixgbe_hw_stats */ 3653 count = 0; 3654 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3655 values[count] = *(uint64_t *)(((char *)hw_stats) + 3656 rte_ixgbe_stats_strings[i].offset); 3657 count++; 3658 } 3659 3660 /* MACsec Stats */ 3661 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3662 values[count] = *(uint64_t *)(((char *)macsec_stats) + 3663 rte_ixgbe_macsec_strings[i].offset); 3664 count++; 3665 } 3666 3667 /* RX Priority Stats */ 3668 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3669 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3670 values[count] = 3671 *(uint64_t *)(((char *)hw_stats) + 3672 rte_ixgbe_rxq_strings[stat].offset + 3673 (sizeof(uint64_t) * i)); 3674 count++; 3675 } 3676 } 3677 3678 /* TX Priority Stats */ 3679 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3680 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3681 values[count] = 3682 *(uint64_t *)(((char *)hw_stats) + 3683 rte_ixgbe_txq_strings[stat].offset + 3684 (sizeof(uint64_t) * i)); 3685 count++; 3686 } 3687 } 3688 return count; 3689 } 3690 3691 uint16_t i; 3692 uint16_t size = ixgbe_xstats_calc_num(); 3693 uint64_t values_copy[size]; 3694 3695 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size); 3696 3697 for (i = 0; i < n; i++) { 3698 if (ids[i] >= size) { 3699 PMD_INIT_LOG(ERR, "id value isn't valid"); 3700 return -1; 3701 } 3702 values[i] = values_copy[ids[i]]; 3703 } 3704 return n; 3705 } 3706 3707 static int 3708 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev) 3709 { 3710 struct ixgbe_hw_stats *stats = 3711 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3712 struct ixgbe_macsec_stats *macsec_stats = 3713 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3714 dev->data->dev_private); 3715 3716 unsigned count = ixgbe_xstats_calc_num(); 3717 3718 /* HW registers are cleared on read */ 3719 ixgbe_dev_xstats_get(dev, NULL, count); 3720 3721 /* Reset software totals */ 3722 memset(stats, 0, sizeof(*stats)); 3723 memset(macsec_stats, 0, sizeof(*macsec_stats)); 3724 3725 return 0; 3726 } 3727 3728 static void 3729 ixgbevf_update_stats(struct rte_eth_dev *dev) 3730 { 3731 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3732 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3733 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3734 3735 /* Good Rx packet, include VF loopback */ 3736 UPDATE_VF_STAT(IXGBE_VFGPRC, 3737 hw_stats->last_vfgprc, hw_stats->vfgprc); 3738 3739 /* Good Rx octets, include VF loopback */ 3740 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB, 3741 hw_stats->last_vfgorc, hw_stats->vfgorc); 3742 3743 /* Good Tx packet, include VF loopback */ 3744 UPDATE_VF_STAT(IXGBE_VFGPTC, 3745 hw_stats->last_vfgptc, hw_stats->vfgptc); 3746 3747 /* Good Tx octets, include VF loopback */ 3748 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB, 3749 hw_stats->last_vfgotc, hw_stats->vfgotc); 3750 3751 /* Rx Multicst Packet */ 3752 UPDATE_VF_STAT(IXGBE_VFMPRC, 3753 hw_stats->last_vfmprc, hw_stats->vfmprc); 3754 } 3755 3756 static int 3757 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3758 unsigned n) 3759 { 3760 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3761 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3762 unsigned i; 3763 3764 if (n < IXGBEVF_NB_XSTATS) 3765 return IXGBEVF_NB_XSTATS; 3766 3767 ixgbevf_update_stats(dev); 3768 3769 if (!xstats) 3770 return 0; 3771 3772 /* Extended stats */ 3773 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) { 3774 xstats[i].id = i; 3775 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + 3776 rte_ixgbevf_stats_strings[i].offset); 3777 } 3778 3779 return IXGBEVF_NB_XSTATS; 3780 } 3781 3782 static int 3783 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3784 { 3785 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3786 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3787 3788 ixgbevf_update_stats(dev); 3789 3790 if (stats == NULL) 3791 return -EINVAL; 3792 3793 stats->ipackets = hw_stats->vfgprc; 3794 stats->ibytes = hw_stats->vfgorc; 3795 stats->opackets = hw_stats->vfgptc; 3796 stats->obytes = hw_stats->vfgotc; 3797 return 0; 3798 } 3799 3800 static int 3801 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev) 3802 { 3803 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3804 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3805 3806 /* Sync HW register to the last stats */ 3807 ixgbevf_dev_stats_get(dev, NULL); 3808 3809 /* reset HW current stats*/ 3810 hw_stats->vfgprc = 0; 3811 hw_stats->vfgorc = 0; 3812 hw_stats->vfgptc = 0; 3813 hw_stats->vfgotc = 0; 3814 3815 return 0; 3816 } 3817 3818 static int 3819 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 3820 { 3821 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3822 u16 eeprom_verh, eeprom_verl; 3823 u32 etrack_id; 3824 int ret; 3825 3826 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh); 3827 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl); 3828 3829 etrack_id = (eeprom_verh << 16) | eeprom_verl; 3830 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id); 3831 3832 ret += 1; /* add the size of '\0' */ 3833 if (fw_size < (u32)ret) 3834 return ret; 3835 else 3836 return 0; 3837 } 3838 3839 static int 3840 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3841 { 3842 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3843 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3844 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 3845 3846 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3847 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3848 if (RTE_ETH_DEV_SRIOV(dev).active == 0) { 3849 /* 3850 * When DCB/VT is off, maximum number of queues changes, 3851 * except for 82598EB, which remains constant. 3852 */ 3853 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 3854 hw->mac.type != ixgbe_mac_82598EB) 3855 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES; 3856 } 3857 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */ 3858 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */ 3859 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3860 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3861 dev_info->max_vfs = pci_dev->max_vfs; 3862 if (hw->mac.type == ixgbe_mac_82598EB) 3863 dev_info->max_vmdq_pools = ETH_16_POOLS; 3864 else 3865 dev_info->max_vmdq_pools = ETH_64_POOLS; 3866 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD; 3867 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 3868 dev_info->vmdq_queue_num = dev_info->max_rx_queues; 3869 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3870 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3871 dev_info->rx_queue_offload_capa); 3872 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3873 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3874 3875 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3876 .rx_thresh = { 3877 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3878 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3879 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3880 }, 3881 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3882 .rx_drop_en = 0, 3883 .offloads = 0, 3884 }; 3885 3886 dev_info->default_txconf = (struct rte_eth_txconf) { 3887 .tx_thresh = { 3888 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3889 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3890 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3891 }, 3892 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3893 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3894 .offloads = 0, 3895 }; 3896 3897 dev_info->rx_desc_lim = rx_desc_lim; 3898 dev_info->tx_desc_lim = tx_desc_lim; 3899 3900 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 3901 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 3902 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 3903 3904 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 3905 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 3906 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 3907 dev_info->speed_capa = ETH_LINK_SPEED_10M | 3908 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G; 3909 3910 if (hw->mac.type == ixgbe_mac_X540 || 3911 hw->mac.type == ixgbe_mac_X540_vf || 3912 hw->mac.type == ixgbe_mac_X550 || 3913 hw->mac.type == ixgbe_mac_X550_vf) { 3914 dev_info->speed_capa |= ETH_LINK_SPEED_100M; 3915 } 3916 if (hw->mac.type == ixgbe_mac_X550) { 3917 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G; 3918 dev_info->speed_capa |= ETH_LINK_SPEED_5G; 3919 } 3920 3921 /* Driver-preferred Rx/Tx parameters */ 3922 dev_info->default_rxportconf.burst_size = 32; 3923 dev_info->default_txportconf.burst_size = 32; 3924 dev_info->default_rxportconf.nb_queues = 1; 3925 dev_info->default_txportconf.nb_queues = 1; 3926 dev_info->default_rxportconf.ring_size = 256; 3927 dev_info->default_txportconf.ring_size = 256; 3928 3929 return 0; 3930 } 3931 3932 static const uint32_t * 3933 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 3934 { 3935 static const uint32_t ptypes[] = { 3936 /* For non-vec functions, 3937 * refers to ixgbe_rxd_pkt_info_to_pkt_type(); 3938 * for vec functions, 3939 * refers to _recv_raw_pkts_vec(). 3940 */ 3941 RTE_PTYPE_L2_ETHER, 3942 RTE_PTYPE_L3_IPV4, 3943 RTE_PTYPE_L3_IPV4_EXT, 3944 RTE_PTYPE_L3_IPV6, 3945 RTE_PTYPE_L3_IPV6_EXT, 3946 RTE_PTYPE_L4_SCTP, 3947 RTE_PTYPE_L4_TCP, 3948 RTE_PTYPE_L4_UDP, 3949 RTE_PTYPE_TUNNEL_IP, 3950 RTE_PTYPE_INNER_L3_IPV6, 3951 RTE_PTYPE_INNER_L3_IPV6_EXT, 3952 RTE_PTYPE_INNER_L4_TCP, 3953 RTE_PTYPE_INNER_L4_UDP, 3954 RTE_PTYPE_UNKNOWN 3955 }; 3956 3957 if (dev->rx_pkt_burst == ixgbe_recv_pkts || 3958 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc || 3959 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc || 3960 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc) 3961 return ptypes; 3962 3963 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON) 3964 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec || 3965 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec) 3966 return ptypes; 3967 #endif 3968 return NULL; 3969 } 3970 3971 static int 3972 ixgbevf_dev_info_get(struct rte_eth_dev *dev, 3973 struct rte_eth_dev_info *dev_info) 3974 { 3975 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3976 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3977 3978 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3979 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3980 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */ 3981 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */ 3982 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD; 3983 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3984 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3985 dev_info->max_vfs = pci_dev->max_vfs; 3986 if (hw->mac.type == ixgbe_mac_82598EB) 3987 dev_info->max_vmdq_pools = ETH_16_POOLS; 3988 else 3989 dev_info->max_vmdq_pools = ETH_64_POOLS; 3990 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3991 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3992 dev_info->rx_queue_offload_capa); 3993 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3994 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3995 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 3996 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 3997 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 3998 3999 dev_info->default_rxconf = (struct rte_eth_rxconf) { 4000 .rx_thresh = { 4001 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 4002 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 4003 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 4004 }, 4005 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 4006 .rx_drop_en = 0, 4007 .offloads = 0, 4008 }; 4009 4010 dev_info->default_txconf = (struct rte_eth_txconf) { 4011 .tx_thresh = { 4012 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 4013 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 4014 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 4015 }, 4016 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 4017 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 4018 .offloads = 0, 4019 }; 4020 4021 dev_info->rx_desc_lim = rx_desc_lim; 4022 dev_info->tx_desc_lim = tx_desc_lim; 4023 4024 return 0; 4025 } 4026 4027 static int 4028 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4029 bool *link_up, int wait_to_complete) 4030 { 4031 struct ixgbe_adapter *adapter = container_of(hw, 4032 struct ixgbe_adapter, hw); 4033 struct ixgbe_mbx_info *mbx = &hw->mbx; 4034 struct ixgbe_mac_info *mac = &hw->mac; 4035 uint32_t links_reg, in_msg; 4036 int ret_val = 0; 4037 4038 /* If we were hit with a reset drop the link */ 4039 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout) 4040 mac->get_link_status = true; 4041 4042 if (!mac->get_link_status) 4043 goto out; 4044 4045 /* if link status is down no point in checking to see if pf is up */ 4046 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 4047 if (!(links_reg & IXGBE_LINKS_UP)) 4048 goto out; 4049 4050 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs 4051 * before the link status is correct 4052 */ 4053 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) { 4054 int i; 4055 4056 for (i = 0; i < 5; i++) { 4057 rte_delay_us(100); 4058 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 4059 4060 if (!(links_reg & IXGBE_LINKS_UP)) 4061 goto out; 4062 } 4063 } 4064 4065 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 4066 case IXGBE_LINKS_SPEED_10G_82599: 4067 *speed = IXGBE_LINK_SPEED_10GB_FULL; 4068 if (hw->mac.type >= ixgbe_mac_X550) { 4069 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4070 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4071 } 4072 break; 4073 case IXGBE_LINKS_SPEED_1G_82599: 4074 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4075 break; 4076 case IXGBE_LINKS_SPEED_100_82599: 4077 *speed = IXGBE_LINK_SPEED_100_FULL; 4078 if (hw->mac.type == ixgbe_mac_X550) { 4079 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4080 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4081 } 4082 break; 4083 case IXGBE_LINKS_SPEED_10_X550EM_A: 4084 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4085 /* Since Reserved in older MAC's */ 4086 if (hw->mac.type >= ixgbe_mac_X550) 4087 *speed = IXGBE_LINK_SPEED_10_FULL; 4088 break; 4089 default: 4090 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4091 } 4092 4093 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) { 4094 if (*speed == IXGBE_LINK_SPEED_UNKNOWN) 4095 mac->get_link_status = true; 4096 else 4097 mac->get_link_status = false; 4098 4099 goto out; 4100 } 4101 4102 /* if the read failed it could just be a mailbox collision, best wait 4103 * until we are called again and don't report an error 4104 */ 4105 if (mbx->ops.read(hw, &in_msg, 1, 0)) 4106 goto out; 4107 4108 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) { 4109 /* msg is not CTS and is NACK we must have lost CTS status */ 4110 if (in_msg & IXGBE_VT_MSGTYPE_NACK) 4111 mac->get_link_status = false; 4112 goto out; 4113 } 4114 4115 /* the pf is talking, if we timed out in the past we reinit */ 4116 if (!mbx->timeout) { 4117 ret_val = -1; 4118 goto out; 4119 } 4120 4121 /* if we passed all the tests above then the link is up and we no 4122 * longer need to check for link 4123 */ 4124 mac->get_link_status = false; 4125 4126 out: 4127 *link_up = !mac->get_link_status; 4128 return ret_val; 4129 } 4130 4131 /* 4132 * If @timeout_ms was 0, it means that it will not return until link complete. 4133 * It returns 1 on complete, return 0 on timeout. 4134 */ 4135 static int 4136 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms) 4137 { 4138 #define WARNING_TIMEOUT 9000 /* 9s in total */ 4139 struct ixgbe_adapter *ad = dev->data->dev_private; 4140 uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT; 4141 4142 while (rte_atomic32_read(&ad->link_thread_running)) { 4143 msec_delay(1); 4144 timeout--; 4145 4146 if (timeout_ms) { 4147 if (!timeout) 4148 return 0; 4149 } else if (!timeout) { 4150 /* It will not return until link complete */ 4151 timeout = WARNING_TIMEOUT; 4152 PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!"); 4153 } 4154 } 4155 4156 return 1; 4157 } 4158 4159 static void * 4160 ixgbe_dev_setup_link_thread_handler(void *param) 4161 { 4162 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4163 struct ixgbe_adapter *ad = dev->data->dev_private; 4164 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4165 struct ixgbe_interrupt *intr = 4166 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4167 u32 speed; 4168 bool autoneg = false; 4169 4170 pthread_detach(pthread_self()); 4171 speed = hw->phy.autoneg_advertised; 4172 if (!speed) 4173 ixgbe_get_link_capabilities(hw, &speed, &autoneg); 4174 4175 ixgbe_setup_link(hw, speed, true); 4176 4177 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 4178 rte_atomic32_clear(&ad->link_thread_running); 4179 return NULL; 4180 } 4181 4182 /* 4183 * In freebsd environment, nic_uio drivers do not support interrupts, 4184 * rte_intr_callback_register() will fail to register interrupts. 4185 * We can not make link status to change from down to up by interrupt 4186 * callback. So we need to wait for the controller to acquire link 4187 * when ports start. 4188 * It returns 0 on link up. 4189 */ 4190 static int 4191 ixgbe_wait_for_link_up(struct ixgbe_hw *hw) 4192 { 4193 #ifdef RTE_EXEC_ENV_FREEBSD 4194 int err, i; 4195 bool link_up = false; 4196 uint32_t speed = 0; 4197 const int nb_iter = 25; 4198 4199 for (i = 0; i < nb_iter; i++) { 4200 err = ixgbe_check_link(hw, &speed, &link_up, 0); 4201 if (err) 4202 return err; 4203 if (link_up) 4204 return 0; 4205 msec_delay(200); 4206 } 4207 4208 return 0; 4209 #else 4210 RTE_SET_USED(hw); 4211 return 0; 4212 #endif 4213 } 4214 4215 /* return 0 means link status changed, -1 means not changed */ 4216 int 4217 ixgbe_dev_link_update_share(struct rte_eth_dev *dev, 4218 int wait_to_complete, int vf) 4219 { 4220 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4221 struct ixgbe_adapter *ad = dev->data->dev_private; 4222 struct rte_eth_link link; 4223 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4224 struct ixgbe_interrupt *intr = 4225 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4226 bool link_up; 4227 int diag; 4228 int wait = 1; 4229 u32 esdp_reg; 4230 4231 memset(&link, 0, sizeof(link)); 4232 link.link_status = ETH_LINK_DOWN; 4233 link.link_speed = ETH_SPEED_NUM_NONE; 4234 link.link_duplex = ETH_LINK_HALF_DUPLEX; 4235 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 4236 ETH_LINK_SPEED_FIXED); 4237 4238 hw->mac.get_link_status = true; 4239 4240 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) 4241 return rte_eth_linkstatus_set(dev, &link); 4242 4243 /* check if it needs to wait to complete, if lsc interrupt is enabled */ 4244 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0) 4245 wait = 0; 4246 4247 /* BSD has no interrupt mechanism, so force NIC status synchronization. */ 4248 #ifdef RTE_EXEC_ENV_FREEBSD 4249 wait = 1; 4250 #endif 4251 4252 if (vf) 4253 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait); 4254 else 4255 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait); 4256 4257 if (diag != 0) { 4258 link.link_speed = ETH_SPEED_NUM_100M; 4259 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4260 return rte_eth_linkstatus_set(dev, &link); 4261 } 4262 4263 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) { 4264 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 4265 if ((esdp_reg & IXGBE_ESDP_SDP3)) 4266 link_up = 0; 4267 } 4268 4269 if (link_up == 0) { 4270 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) { 4271 ixgbe_dev_wait_setup_link_complete(dev, 0); 4272 if (rte_atomic32_test_and_set(&ad->link_thread_running)) { 4273 /* To avoid race condition between threads, set 4274 * the IXGBE_FLAG_NEED_LINK_CONFIG flag only 4275 * when there is no link thread running. 4276 */ 4277 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 4278 if (rte_ctrl_thread_create(&ad->link_thread_tid, 4279 "ixgbe-link-handler", 4280 NULL, 4281 ixgbe_dev_setup_link_thread_handler, 4282 dev) < 0) { 4283 PMD_DRV_LOG(ERR, 4284 "Create link thread failed!"); 4285 rte_atomic32_clear(&ad->link_thread_running); 4286 } 4287 } else { 4288 PMD_DRV_LOG(ERR, 4289 "Other link thread is running now!"); 4290 } 4291 } 4292 return rte_eth_linkstatus_set(dev, &link); 4293 } 4294 4295 link.link_status = ETH_LINK_UP; 4296 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4297 4298 switch (link_speed) { 4299 default: 4300 case IXGBE_LINK_SPEED_UNKNOWN: 4301 link.link_speed = ETH_SPEED_NUM_UNKNOWN; 4302 break; 4303 4304 case IXGBE_LINK_SPEED_10_FULL: 4305 link.link_speed = ETH_SPEED_NUM_10M; 4306 break; 4307 4308 case IXGBE_LINK_SPEED_100_FULL: 4309 link.link_speed = ETH_SPEED_NUM_100M; 4310 break; 4311 4312 case IXGBE_LINK_SPEED_1GB_FULL: 4313 link.link_speed = ETH_SPEED_NUM_1G; 4314 break; 4315 4316 case IXGBE_LINK_SPEED_2_5GB_FULL: 4317 link.link_speed = ETH_SPEED_NUM_2_5G; 4318 break; 4319 4320 case IXGBE_LINK_SPEED_5GB_FULL: 4321 link.link_speed = ETH_SPEED_NUM_5G; 4322 break; 4323 4324 case IXGBE_LINK_SPEED_10GB_FULL: 4325 link.link_speed = ETH_SPEED_NUM_10G; 4326 break; 4327 } 4328 4329 return rte_eth_linkstatus_set(dev, &link); 4330 } 4331 4332 static int 4333 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4334 { 4335 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0); 4336 } 4337 4338 static int 4339 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4340 { 4341 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1); 4342 } 4343 4344 static int 4345 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 4346 { 4347 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4348 uint32_t fctrl; 4349 4350 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4351 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4352 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4353 4354 return 0; 4355 } 4356 4357 static int 4358 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 4359 { 4360 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4361 uint32_t fctrl; 4362 4363 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4364 fctrl &= (~IXGBE_FCTRL_UPE); 4365 if (dev->data->all_multicast == 1) 4366 fctrl |= IXGBE_FCTRL_MPE; 4367 else 4368 fctrl &= (~IXGBE_FCTRL_MPE); 4369 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4370 4371 return 0; 4372 } 4373 4374 static int 4375 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 4376 { 4377 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4378 uint32_t fctrl; 4379 4380 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4381 fctrl |= IXGBE_FCTRL_MPE; 4382 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4383 4384 return 0; 4385 } 4386 4387 static int 4388 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 4389 { 4390 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4391 uint32_t fctrl; 4392 4393 if (dev->data->promiscuous == 1) 4394 return 0; /* must remain in all_multicast mode */ 4395 4396 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4397 fctrl &= (~IXGBE_FCTRL_MPE); 4398 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4399 4400 return 0; 4401 } 4402 4403 /** 4404 * It clears the interrupt causes and enables the interrupt. 4405 * It will be called once only during nic initialized. 4406 * 4407 * @param dev 4408 * Pointer to struct rte_eth_dev. 4409 * @param on 4410 * Enable or Disable. 4411 * 4412 * @return 4413 * - On success, zero. 4414 * - On failure, a negative value. 4415 */ 4416 static int 4417 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 4418 { 4419 struct ixgbe_interrupt *intr = 4420 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4421 4422 ixgbe_dev_link_status_print(dev); 4423 if (on) 4424 intr->mask |= IXGBE_EICR_LSC; 4425 else 4426 intr->mask &= ~IXGBE_EICR_LSC; 4427 4428 return 0; 4429 } 4430 4431 /** 4432 * It clears the interrupt causes and enables the interrupt. 4433 * It will be called once only during nic initialized. 4434 * 4435 * @param dev 4436 * Pointer to struct rte_eth_dev. 4437 * 4438 * @return 4439 * - On success, zero. 4440 * - On failure, a negative value. 4441 */ 4442 static int 4443 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev) 4444 { 4445 struct ixgbe_interrupt *intr = 4446 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4447 4448 intr->mask |= IXGBE_EICR_RTX_QUEUE; 4449 4450 return 0; 4451 } 4452 4453 /** 4454 * It clears the interrupt causes and enables the interrupt. 4455 * It will be called once only during nic initialized. 4456 * 4457 * @param dev 4458 * Pointer to struct rte_eth_dev. 4459 * 4460 * @return 4461 * - On success, zero. 4462 * - On failure, a negative value. 4463 */ 4464 static int 4465 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev) 4466 { 4467 struct ixgbe_interrupt *intr = 4468 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4469 4470 intr->mask |= IXGBE_EICR_LINKSEC; 4471 4472 return 0; 4473 } 4474 4475 /* 4476 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update. 4477 * 4478 * @param dev 4479 * Pointer to struct rte_eth_dev. 4480 * 4481 * @return 4482 * - On success, zero. 4483 * - On failure, a negative value. 4484 */ 4485 static int 4486 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev) 4487 { 4488 uint32_t eicr; 4489 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4490 struct ixgbe_interrupt *intr = 4491 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4492 4493 /* clear all cause mask */ 4494 ixgbe_disable_intr(hw); 4495 4496 /* read-on-clear nic registers here */ 4497 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4498 PMD_DRV_LOG(DEBUG, "eicr %x", eicr); 4499 4500 intr->flags = 0; 4501 4502 /* set flag for async link update */ 4503 if (eicr & IXGBE_EICR_LSC) 4504 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 4505 4506 if (eicr & IXGBE_EICR_MAILBOX) 4507 intr->flags |= IXGBE_FLAG_MAILBOX; 4508 4509 if (eicr & IXGBE_EICR_LINKSEC) 4510 intr->flags |= IXGBE_FLAG_MACSEC; 4511 4512 if (hw->mac.type == ixgbe_mac_X550EM_x && 4513 hw->phy.type == ixgbe_phy_x550em_ext_t && 4514 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x)) 4515 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT; 4516 4517 return 0; 4518 } 4519 4520 /** 4521 * It gets and then prints the link status. 4522 * 4523 * @param dev 4524 * Pointer to struct rte_eth_dev. 4525 * 4526 * @return 4527 * - On success, zero. 4528 * - On failure, a negative value. 4529 */ 4530 static void 4531 ixgbe_dev_link_status_print(struct rte_eth_dev *dev) 4532 { 4533 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4534 struct rte_eth_link link; 4535 4536 rte_eth_linkstatus_get(dev, &link); 4537 4538 if (link.link_status) { 4539 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", 4540 (int)(dev->data->port_id), 4541 (unsigned)link.link_speed, 4542 link.link_duplex == ETH_LINK_FULL_DUPLEX ? 4543 "full-duplex" : "half-duplex"); 4544 } else { 4545 PMD_INIT_LOG(INFO, " Port %d: Link Down", 4546 (int)(dev->data->port_id)); 4547 } 4548 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 4549 pci_dev->addr.domain, 4550 pci_dev->addr.bus, 4551 pci_dev->addr.devid, 4552 pci_dev->addr.function); 4553 } 4554 4555 /* 4556 * It executes link_update after knowing an interrupt occurred. 4557 * 4558 * @param dev 4559 * Pointer to struct rte_eth_dev. 4560 * 4561 * @return 4562 * - On success, zero. 4563 * - On failure, a negative value. 4564 */ 4565 static int 4566 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev) 4567 { 4568 struct ixgbe_interrupt *intr = 4569 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4570 int64_t timeout; 4571 struct ixgbe_hw *hw = 4572 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4573 4574 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags); 4575 4576 if (intr->flags & IXGBE_FLAG_MAILBOX) { 4577 ixgbe_pf_mbx_process(dev); 4578 intr->flags &= ~IXGBE_FLAG_MAILBOX; 4579 } 4580 4581 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4582 ixgbe_handle_lasi(hw); 4583 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4584 } 4585 4586 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4587 struct rte_eth_link link; 4588 4589 /* get the link status before link update, for predicting later */ 4590 rte_eth_linkstatus_get(dev, &link); 4591 4592 ixgbe_dev_link_update(dev, 0); 4593 4594 /* likely to up */ 4595 if (!link.link_status) 4596 /* handle it 1 sec later, wait it being stable */ 4597 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT; 4598 /* likely to down */ 4599 else 4600 /* handle it 4 sec later, wait it being stable */ 4601 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT; 4602 4603 ixgbe_dev_link_status_print(dev); 4604 if (rte_eal_alarm_set(timeout * 1000, 4605 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0) 4606 PMD_DRV_LOG(ERR, "Error setting alarm"); 4607 else { 4608 /* remember original mask */ 4609 intr->mask_original = intr->mask; 4610 /* only disable lsc interrupt */ 4611 intr->mask &= ~IXGBE_EIMS_LSC; 4612 } 4613 } 4614 4615 PMD_DRV_LOG(DEBUG, "enable intr immediately"); 4616 ixgbe_enable_intr(dev); 4617 4618 return 0; 4619 } 4620 4621 /** 4622 * Interrupt handler which shall be registered for alarm callback for delayed 4623 * handling specific interrupt to wait for the stable nic state. As the 4624 * NIC interrupt state is not stable for ixgbe after link is just down, 4625 * it needs to wait 4 seconds to get the stable status. 4626 * 4627 * @param handle 4628 * Pointer to interrupt handle. 4629 * @param param 4630 * The address of parameter (struct rte_eth_dev *) regsitered before. 4631 * 4632 * @return 4633 * void 4634 */ 4635 static void 4636 ixgbe_dev_interrupt_delayed_handler(void *param) 4637 { 4638 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4639 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4640 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4641 struct ixgbe_interrupt *intr = 4642 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4643 struct ixgbe_hw *hw = 4644 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4645 uint32_t eicr; 4646 4647 ixgbe_disable_intr(hw); 4648 4649 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4650 if (eicr & IXGBE_EICR_MAILBOX) 4651 ixgbe_pf_mbx_process(dev); 4652 4653 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4654 ixgbe_handle_lasi(hw); 4655 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4656 } 4657 4658 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4659 ixgbe_dev_link_update(dev, 0); 4660 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 4661 ixgbe_dev_link_status_print(dev); 4662 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 4663 } 4664 4665 if (intr->flags & IXGBE_FLAG_MACSEC) { 4666 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL); 4667 intr->flags &= ~IXGBE_FLAG_MACSEC; 4668 } 4669 4670 /* restore original mask */ 4671 intr->mask = intr->mask_original; 4672 intr->mask_original = 0; 4673 4674 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr); 4675 ixgbe_enable_intr(dev); 4676 rte_intr_ack(intr_handle); 4677 } 4678 4679 /** 4680 * Interrupt handler triggered by NIC for handling 4681 * specific interrupt. 4682 * 4683 * @param handle 4684 * Pointer to interrupt handle. 4685 * @param param 4686 * The address of parameter (struct rte_eth_dev *) regsitered before. 4687 * 4688 * @return 4689 * void 4690 */ 4691 static void 4692 ixgbe_dev_interrupt_handler(void *param) 4693 { 4694 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4695 4696 ixgbe_dev_interrupt_get_status(dev); 4697 ixgbe_dev_interrupt_action(dev); 4698 } 4699 4700 static int 4701 ixgbe_dev_led_on(struct rte_eth_dev *dev) 4702 { 4703 struct ixgbe_hw *hw; 4704 4705 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4706 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4707 } 4708 4709 static int 4710 ixgbe_dev_led_off(struct rte_eth_dev *dev) 4711 { 4712 struct ixgbe_hw *hw; 4713 4714 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4715 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4716 } 4717 4718 static int 4719 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4720 { 4721 struct ixgbe_hw *hw; 4722 uint32_t mflcn_reg; 4723 uint32_t fccfg_reg; 4724 int rx_pause; 4725 int tx_pause; 4726 4727 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4728 4729 fc_conf->pause_time = hw->fc.pause_time; 4730 fc_conf->high_water = hw->fc.high_water[0]; 4731 fc_conf->low_water = hw->fc.low_water[0]; 4732 fc_conf->send_xon = hw->fc.send_xon; 4733 fc_conf->autoneg = !hw->fc.disable_fc_autoneg; 4734 4735 /* 4736 * Return rx_pause status according to actual setting of 4737 * MFLCN register. 4738 */ 4739 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4740 if (mflcn_reg & IXGBE_MFLCN_PMCF) 4741 fc_conf->mac_ctrl_frame_fwd = 1; 4742 else 4743 fc_conf->mac_ctrl_frame_fwd = 0; 4744 4745 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE)) 4746 rx_pause = 1; 4747 else 4748 rx_pause = 0; 4749 4750 /* 4751 * Return tx_pause status according to actual setting of 4752 * FCCFG register. 4753 */ 4754 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4755 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY)) 4756 tx_pause = 1; 4757 else 4758 tx_pause = 0; 4759 4760 if (rx_pause && tx_pause) 4761 fc_conf->mode = RTE_FC_FULL; 4762 else if (rx_pause) 4763 fc_conf->mode = RTE_FC_RX_PAUSE; 4764 else if (tx_pause) 4765 fc_conf->mode = RTE_FC_TX_PAUSE; 4766 else 4767 fc_conf->mode = RTE_FC_NONE; 4768 4769 return 0; 4770 } 4771 4772 static int 4773 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4774 { 4775 struct ixgbe_hw *hw; 4776 struct ixgbe_adapter *adapter = dev->data->dev_private; 4777 int err; 4778 uint32_t rx_buf_size; 4779 uint32_t max_high_water; 4780 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4781 ixgbe_fc_none, 4782 ixgbe_fc_rx_pause, 4783 ixgbe_fc_tx_pause, 4784 ixgbe_fc_full 4785 }; 4786 4787 PMD_INIT_FUNC_TRACE(); 4788 4789 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4790 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)); 4791 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4792 4793 /* 4794 * At least reserve one Ethernet frame for watermark 4795 * high_water/low_water in kilo bytes for ixgbe 4796 */ 4797 max_high_water = (rx_buf_size - 4798 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4799 if ((fc_conf->high_water > max_high_water) || 4800 (fc_conf->high_water < fc_conf->low_water)) { 4801 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4802 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4803 return -EINVAL; 4804 } 4805 4806 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode]; 4807 hw->fc.pause_time = fc_conf->pause_time; 4808 hw->fc.high_water[0] = fc_conf->high_water; 4809 hw->fc.low_water[0] = fc_conf->low_water; 4810 hw->fc.send_xon = fc_conf->send_xon; 4811 hw->fc.disable_fc_autoneg = !fc_conf->autoneg; 4812 adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; 4813 4814 err = ixgbe_flow_ctrl_enable(dev, hw); 4815 if (err < 0) { 4816 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err); 4817 return -EIO; 4818 } 4819 return err; 4820 } 4821 4822 /** 4823 * ixgbe_pfc_enable_generic - Enable flow control 4824 * @hw: pointer to hardware structure 4825 * @tc_num: traffic class number 4826 * Enable flow control according to the current settings. 4827 */ 4828 static int 4829 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num) 4830 { 4831 int ret_val = 0; 4832 uint32_t mflcn_reg, fccfg_reg; 4833 uint32_t reg; 4834 uint32_t fcrtl, fcrth; 4835 uint8_t i; 4836 uint8_t nb_rx_en; 4837 4838 /* Validate the water mark configuration */ 4839 if (!hw->fc.pause_time) { 4840 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4841 goto out; 4842 } 4843 4844 /* Low water mark of zero causes XOFF floods */ 4845 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 4846 /* High/Low water can not be 0 */ 4847 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) { 4848 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4849 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4850 goto out; 4851 } 4852 4853 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) { 4854 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4855 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4856 goto out; 4857 } 4858 } 4859 /* Negotiate the fc mode to use */ 4860 ixgbe_fc_autoneg(hw); 4861 4862 /* Disable any previous flow control settings */ 4863 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4864 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE); 4865 4866 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4867 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 4868 4869 switch (hw->fc.current_mode) { 4870 case ixgbe_fc_none: 4871 /* 4872 * If the count of enabled RX Priority Flow control >1, 4873 * and the TX pause can not be disabled 4874 */ 4875 nb_rx_en = 0; 4876 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4877 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4878 if (reg & IXGBE_FCRTH_FCEN) 4879 nb_rx_en++; 4880 } 4881 if (nb_rx_en > 1) 4882 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4883 break; 4884 case ixgbe_fc_rx_pause: 4885 /* 4886 * Rx Flow control is enabled and Tx Flow control is 4887 * disabled by software override. Since there really 4888 * isn't a way to advertise that we are capable of RX 4889 * Pause ONLY, we will advertise that we support both 4890 * symmetric and asymmetric Rx PAUSE. Later, we will 4891 * disable the adapter's ability to send PAUSE frames. 4892 */ 4893 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4894 /* 4895 * If the count of enabled RX Priority Flow control >1, 4896 * and the TX pause can not be disabled 4897 */ 4898 nb_rx_en = 0; 4899 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4900 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4901 if (reg & IXGBE_FCRTH_FCEN) 4902 nb_rx_en++; 4903 } 4904 if (nb_rx_en > 1) 4905 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4906 break; 4907 case ixgbe_fc_tx_pause: 4908 /* 4909 * Tx Flow control is enabled, and Rx Flow control is 4910 * disabled by software override. 4911 */ 4912 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4913 break; 4914 case ixgbe_fc_full: 4915 /* Flow control (both Rx and Tx) is enabled by SW override. */ 4916 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4917 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4918 break; 4919 default: 4920 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly"); 4921 ret_val = IXGBE_ERR_CONFIG; 4922 goto out; 4923 } 4924 4925 /* Set 802.3x based flow control settings. */ 4926 mflcn_reg |= IXGBE_MFLCN_DPF; 4927 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 4928 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 4929 4930 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 4931 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 4932 hw->fc.high_water[tc_num]) { 4933 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE; 4934 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl); 4935 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN; 4936 } else { 4937 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0); 4938 /* 4939 * In order to prevent Tx hangs when the internal Tx 4940 * switch is enabled we must set the high water mark 4941 * to the maximum FCRTH value. This allows the Tx 4942 * switch to function even under heavy Rx workloads. 4943 */ 4944 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32; 4945 } 4946 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth); 4947 4948 /* Configure pause time (2 TCs per register) */ 4949 reg = hw->fc.pause_time * 0x00010001; 4950 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 4951 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 4952 4953 /* Configure flow control refresh threshold value */ 4954 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 4955 4956 out: 4957 return ret_val; 4958 } 4959 4960 static int 4961 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num) 4962 { 4963 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4964 int32_t ret_val = IXGBE_NOT_IMPLEMENTED; 4965 4966 if (hw->mac.type != ixgbe_mac_82598EB) { 4967 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num); 4968 } 4969 return ret_val; 4970 } 4971 4972 static int 4973 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf) 4974 { 4975 int err; 4976 uint32_t rx_buf_size; 4977 uint32_t max_high_water; 4978 uint8_t tc_num; 4979 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 4980 struct ixgbe_hw *hw = 4981 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4982 struct ixgbe_dcb_config *dcb_config = 4983 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 4984 4985 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4986 ixgbe_fc_none, 4987 ixgbe_fc_rx_pause, 4988 ixgbe_fc_tx_pause, 4989 ixgbe_fc_full 4990 }; 4991 4992 PMD_INIT_FUNC_TRACE(); 4993 4994 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map); 4995 tc_num = map[pfc_conf->priority]; 4996 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)); 4997 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4998 /* 4999 * At least reserve one Ethernet frame for watermark 5000 * high_water/low_water in kilo bytes for ixgbe 5001 */ 5002 max_high_water = (rx_buf_size - 5003 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 5004 if ((pfc_conf->fc.high_water > max_high_water) || 5005 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) { 5006 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 5007 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 5008 return -EINVAL; 5009 } 5010 5011 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode]; 5012 hw->fc.pause_time = pfc_conf->fc.pause_time; 5013 hw->fc.send_xon = pfc_conf->fc.send_xon; 5014 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water; 5015 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; 5016 5017 err = ixgbe_dcb_pfc_enable(dev, tc_num); 5018 5019 /* Not negotiated is not an error case */ 5020 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) 5021 return 0; 5022 5023 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err); 5024 return -EIO; 5025 } 5026 5027 static int 5028 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 5029 struct rte_eth_rss_reta_entry64 *reta_conf, 5030 uint16_t reta_size) 5031 { 5032 uint16_t i, sp_reta_size; 5033 uint8_t j, mask; 5034 uint32_t reta, r; 5035 uint16_t idx, shift; 5036 struct ixgbe_adapter *adapter = dev->data->dev_private; 5037 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5038 uint32_t reta_reg; 5039 5040 PMD_INIT_FUNC_TRACE(); 5041 5042 if (!ixgbe_rss_update_sp(hw->mac.type)) { 5043 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " 5044 "NIC."); 5045 return -ENOTSUP; 5046 } 5047 5048 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 5049 if (reta_size != sp_reta_size) { 5050 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 5051 "(%d) doesn't match the number hardware can supported " 5052 "(%d)", reta_size, sp_reta_size); 5053 return -EINVAL; 5054 } 5055 5056 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 5057 idx = i / RTE_RETA_GROUP_SIZE; 5058 shift = i % RTE_RETA_GROUP_SIZE; 5059 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 5060 IXGBE_4_BIT_MASK); 5061 if (!mask) 5062 continue; 5063 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 5064 if (mask == IXGBE_4_BIT_MASK) 5065 r = 0; 5066 else 5067 r = IXGBE_READ_REG(hw, reta_reg); 5068 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) { 5069 if (mask & (0x1 << j)) 5070 reta |= reta_conf[idx].reta[shift + j] << 5071 (CHAR_BIT * j); 5072 else 5073 reta |= r & (IXGBE_8_BIT_MASK << 5074 (CHAR_BIT * j)); 5075 } 5076 IXGBE_WRITE_REG(hw, reta_reg, reta); 5077 } 5078 adapter->rss_reta_updated = 1; 5079 5080 return 0; 5081 } 5082 5083 static int 5084 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 5085 struct rte_eth_rss_reta_entry64 *reta_conf, 5086 uint16_t reta_size) 5087 { 5088 uint16_t i, sp_reta_size; 5089 uint8_t j, mask; 5090 uint32_t reta; 5091 uint16_t idx, shift; 5092 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5093 uint32_t reta_reg; 5094 5095 PMD_INIT_FUNC_TRACE(); 5096 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 5097 if (reta_size != sp_reta_size) { 5098 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 5099 "(%d) doesn't match the number hardware can supported " 5100 "(%d)", reta_size, sp_reta_size); 5101 return -EINVAL; 5102 } 5103 5104 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 5105 idx = i / RTE_RETA_GROUP_SIZE; 5106 shift = i % RTE_RETA_GROUP_SIZE; 5107 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 5108 IXGBE_4_BIT_MASK); 5109 if (!mask) 5110 continue; 5111 5112 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 5113 reta = IXGBE_READ_REG(hw, reta_reg); 5114 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) { 5115 if (mask & (0x1 << j)) 5116 reta_conf[idx].reta[shift + j] = 5117 ((reta >> (CHAR_BIT * j)) & 5118 IXGBE_8_BIT_MASK); 5119 } 5120 } 5121 5122 return 0; 5123 } 5124 5125 static int 5126 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 5127 uint32_t index, uint32_t pool) 5128 { 5129 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5130 uint32_t enable_addr = 1; 5131 5132 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes, 5133 pool, enable_addr); 5134 } 5135 5136 static void 5137 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) 5138 { 5139 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5140 5141 ixgbe_clear_rar(hw, index); 5142 } 5143 5144 static int 5145 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 5146 { 5147 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5148 5149 ixgbe_remove_rar(dev, 0); 5150 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs); 5151 5152 return 0; 5153 } 5154 5155 static bool 5156 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 5157 { 5158 if (strcmp(dev->device->driver->name, drv->driver.name)) 5159 return false; 5160 5161 return true; 5162 } 5163 5164 bool 5165 is_ixgbe_supported(struct rte_eth_dev *dev) 5166 { 5167 return is_device_supported(dev, &rte_ixgbe_pmd); 5168 } 5169 5170 static int 5171 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 5172 { 5173 uint32_t hlreg0; 5174 uint32_t maxfrs; 5175 struct ixgbe_hw *hw; 5176 struct rte_eth_dev_info dev_info; 5177 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD; 5178 struct rte_eth_dev_data *dev_data = dev->data; 5179 int ret; 5180 5181 ret = ixgbe_dev_info_get(dev, &dev_info); 5182 if (ret != 0) 5183 return ret; 5184 5185 /* check that mtu is within the allowed range */ 5186 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) 5187 return -EINVAL; 5188 5189 /* If device is started, refuse mtu that requires the support of 5190 * scattered packets when this feature has not been enabled before. 5191 */ 5192 if (dev_data->dev_started && !dev_data->scattered_rx && 5193 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE > 5194 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 5195 PMD_INIT_LOG(ERR, "Stop port first."); 5196 return -EINVAL; 5197 } 5198 5199 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5200 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 5201 5202 /* switch to jumbo mode if needed */ 5203 if (frame_size > RTE_ETHER_MAX_LEN) { 5204 dev->data->dev_conf.rxmode.offloads |= 5205 DEV_RX_OFFLOAD_JUMBO_FRAME; 5206 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 5207 } else { 5208 dev->data->dev_conf.rxmode.offloads &= 5209 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 5210 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; 5211 } 5212 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 5213 5214 /* update max frame size */ 5215 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 5216 5217 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS); 5218 maxfrs &= 0x0000FFFF; 5219 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16); 5220 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs); 5221 5222 return 0; 5223 } 5224 5225 /* 5226 * Virtual Function operations 5227 */ 5228 static void 5229 ixgbevf_intr_disable(struct rte_eth_dev *dev) 5230 { 5231 struct ixgbe_interrupt *intr = 5232 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5233 struct ixgbe_hw *hw = 5234 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5235 5236 PMD_INIT_FUNC_TRACE(); 5237 5238 /* Clear interrupt mask to stop from interrupts being generated */ 5239 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK); 5240 5241 IXGBE_WRITE_FLUSH(hw); 5242 5243 /* Clear mask value. */ 5244 intr->mask = 0; 5245 } 5246 5247 static void 5248 ixgbevf_intr_enable(struct rte_eth_dev *dev) 5249 { 5250 struct ixgbe_interrupt *intr = 5251 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5252 struct ixgbe_hw *hw = 5253 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5254 5255 PMD_INIT_FUNC_TRACE(); 5256 5257 /* VF enable interrupt autoclean */ 5258 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK); 5259 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK); 5260 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK); 5261 5262 IXGBE_WRITE_FLUSH(hw); 5263 5264 /* Save IXGBE_VTEIMS value to mask. */ 5265 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK; 5266 } 5267 5268 static int 5269 ixgbevf_dev_configure(struct rte_eth_dev *dev) 5270 { 5271 struct rte_eth_conf *conf = &dev->data->dev_conf; 5272 struct ixgbe_adapter *adapter = dev->data->dev_private; 5273 5274 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d", 5275 dev->data->port_id); 5276 5277 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 5278 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 5279 5280 /* 5281 * VF has no ability to enable/disable HW CRC 5282 * Keep the persistent behavior the same as Host PF 5283 */ 5284 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC 5285 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) { 5286 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip"); 5287 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC; 5288 } 5289 #else 5290 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) { 5291 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip"); 5292 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC; 5293 } 5294 #endif 5295 5296 /* 5297 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 5298 * allocation or vector Rx preconditions we will reset it. 5299 */ 5300 adapter->rx_bulk_alloc_allowed = true; 5301 adapter->rx_vec_allowed = true; 5302 5303 return 0; 5304 } 5305 5306 static int 5307 ixgbevf_dev_start(struct rte_eth_dev *dev) 5308 { 5309 struct ixgbe_hw *hw = 5310 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5311 uint32_t intr_vector = 0; 5312 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5313 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5314 5315 int err, mask = 0; 5316 5317 PMD_INIT_FUNC_TRACE(); 5318 5319 /* Stop the link setup handler before resetting the HW. */ 5320 ixgbe_dev_wait_setup_link_complete(dev, 0); 5321 5322 err = hw->mac.ops.reset_hw(hw); 5323 if (err) { 5324 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err); 5325 return err; 5326 } 5327 hw->mac.get_link_status = true; 5328 5329 /* negotiate mailbox API version to use with the PF. */ 5330 ixgbevf_negotiate_api(hw); 5331 5332 ixgbevf_dev_tx_init(dev); 5333 5334 /* This can fail when allocating mbufs for descriptor rings */ 5335 err = ixgbevf_dev_rx_init(dev); 5336 if (err) { 5337 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err); 5338 ixgbe_dev_clear_queues(dev); 5339 return err; 5340 } 5341 5342 /* Set vfta */ 5343 ixgbevf_set_vfta_all(dev, 1); 5344 5345 /* Set HW strip */ 5346 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 5347 ETH_VLAN_EXTEND_MASK; 5348 err = ixgbevf_vlan_offload_config(dev, mask); 5349 if (err) { 5350 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err); 5351 ixgbe_dev_clear_queues(dev); 5352 return err; 5353 } 5354 5355 ixgbevf_dev_rxtx_start(dev); 5356 5357 /* check and configure queue intr-vector mapping */ 5358 if (rte_intr_cap_multiple(intr_handle) && 5359 dev->data->dev_conf.intr_conf.rxq) { 5360 /* According to datasheet, only vector 0/1/2 can be used, 5361 * now only one vector is used for Rx queue 5362 */ 5363 intr_vector = 1; 5364 if (rte_intr_efd_enable(intr_handle, intr_vector)) 5365 return -1; 5366 } 5367 5368 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 5369 intr_handle->intr_vec = 5370 rte_zmalloc("intr_vec", 5371 dev->data->nb_rx_queues * sizeof(int), 0); 5372 if (intr_handle->intr_vec == NULL) { 5373 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 5374 " intr_vec", dev->data->nb_rx_queues); 5375 return -ENOMEM; 5376 } 5377 } 5378 ixgbevf_configure_msix(dev); 5379 5380 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt 5381 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ). 5382 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( ) 5383 * is not cleared, it will fail when following rte_intr_enable( ) tries 5384 * to map Rx queue interrupt to other VFIO vectors. 5385 * So clear uio/vfio intr/evevnfd first to avoid failure. 5386 */ 5387 rte_intr_disable(intr_handle); 5388 5389 rte_intr_enable(intr_handle); 5390 5391 /* Re-enable interrupt for VF */ 5392 ixgbevf_intr_enable(dev); 5393 5394 /* 5395 * Update link status right before return, because it may 5396 * start link configuration process in a separate thread. 5397 */ 5398 ixgbevf_dev_link_update(dev, 0); 5399 5400 hw->adapter_stopped = false; 5401 5402 return 0; 5403 } 5404 5405 static void 5406 ixgbevf_dev_stop(struct rte_eth_dev *dev) 5407 { 5408 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5409 struct ixgbe_adapter *adapter = dev->data->dev_private; 5410 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5411 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5412 5413 if (hw->adapter_stopped) 5414 return; 5415 5416 PMD_INIT_FUNC_TRACE(); 5417 5418 ixgbe_dev_wait_setup_link_complete(dev, 0); 5419 5420 ixgbevf_intr_disable(dev); 5421 5422 hw->adapter_stopped = 1; 5423 ixgbe_stop_adapter(hw); 5424 5425 /* 5426 * Clear what we set, but we still keep shadow_vfta to 5427 * restore after device starts 5428 */ 5429 ixgbevf_set_vfta_all(dev, 0); 5430 5431 /* Clear stored conf */ 5432 dev->data->scattered_rx = 0; 5433 5434 ixgbe_dev_clear_queues(dev); 5435 5436 /* Clean datapath event and queue/vec mapping */ 5437 rte_intr_efd_disable(intr_handle); 5438 if (intr_handle->intr_vec != NULL) { 5439 rte_free(intr_handle->intr_vec); 5440 intr_handle->intr_vec = NULL; 5441 } 5442 5443 adapter->rss_reta_updated = 0; 5444 } 5445 5446 static void 5447 ixgbevf_dev_close(struct rte_eth_dev *dev) 5448 { 5449 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5450 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5451 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5452 5453 PMD_INIT_FUNC_TRACE(); 5454 5455 ixgbe_reset_hw(hw); 5456 5457 ixgbevf_dev_stop(dev); 5458 5459 ixgbe_dev_free_queues(dev); 5460 5461 /** 5462 * Remove the VF MAC address ro ensure 5463 * that the VF traffic goes to the PF 5464 * after stop, close and detach of the VF 5465 **/ 5466 ixgbevf_remove_mac_addr(dev, 0); 5467 5468 dev->dev_ops = NULL; 5469 dev->rx_pkt_burst = NULL; 5470 dev->tx_pkt_burst = NULL; 5471 5472 rte_intr_disable(intr_handle); 5473 rte_intr_callback_unregister(intr_handle, 5474 ixgbevf_dev_interrupt_handler, dev); 5475 } 5476 5477 /* 5478 * Reset VF device 5479 */ 5480 static int 5481 ixgbevf_dev_reset(struct rte_eth_dev *dev) 5482 { 5483 int ret; 5484 5485 ret = eth_ixgbevf_dev_uninit(dev); 5486 if (ret) 5487 return ret; 5488 5489 ret = eth_ixgbevf_dev_init(dev); 5490 5491 return ret; 5492 } 5493 5494 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) 5495 { 5496 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5497 struct ixgbe_vfta *shadow_vfta = 5498 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5499 int i = 0, j = 0, vfta = 0, mask = 1; 5500 5501 for (i = 0; i < IXGBE_VFTA_SIZE; i++) { 5502 vfta = shadow_vfta->vfta[i]; 5503 if (vfta) { 5504 mask = 1; 5505 for (j = 0; j < 32; j++) { 5506 if (vfta & mask) 5507 ixgbe_set_vfta(hw, (i<<5)+j, 0, 5508 on, false); 5509 mask <<= 1; 5510 } 5511 } 5512 } 5513 5514 } 5515 5516 static int 5517 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 5518 { 5519 struct ixgbe_hw *hw = 5520 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5521 struct ixgbe_vfta *shadow_vfta = 5522 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5523 uint32_t vid_idx = 0; 5524 uint32_t vid_bit = 0; 5525 int ret = 0; 5526 5527 PMD_INIT_FUNC_TRACE(); 5528 5529 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */ 5530 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false); 5531 if (ret) { 5532 PMD_INIT_LOG(ERR, "Unable to set VF vlan"); 5533 return ret; 5534 } 5535 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 5536 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 5537 5538 /* Save what we set and retore it after device reset */ 5539 if (on) 5540 shadow_vfta->vfta[vid_idx] |= vid_bit; 5541 else 5542 shadow_vfta->vfta[vid_idx] &= ~vid_bit; 5543 5544 return 0; 5545 } 5546 5547 static void 5548 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 5549 { 5550 struct ixgbe_hw *hw = 5551 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5552 uint32_t ctrl; 5553 5554 PMD_INIT_FUNC_TRACE(); 5555 5556 if (queue >= hw->mac.max_rx_queues) 5557 return; 5558 5559 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 5560 if (on) 5561 ctrl |= IXGBE_RXDCTL_VME; 5562 else 5563 ctrl &= ~IXGBE_RXDCTL_VME; 5564 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 5565 5566 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on); 5567 } 5568 5569 static int 5570 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask) 5571 { 5572 struct ixgbe_rx_queue *rxq; 5573 uint16_t i; 5574 int on = 0; 5575 5576 /* VF function only support hw strip feature, others are not support */ 5577 if (mask & ETH_VLAN_STRIP_MASK) { 5578 for (i = 0; i < dev->data->nb_rx_queues; i++) { 5579 rxq = dev->data->rx_queues[i]; 5580 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP); 5581 ixgbevf_vlan_strip_queue_set(dev, i, on); 5582 } 5583 } 5584 5585 return 0; 5586 } 5587 5588 static int 5589 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 5590 { 5591 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 5592 5593 ixgbevf_vlan_offload_config(dev, mask); 5594 5595 return 0; 5596 } 5597 5598 int 5599 ixgbe_vt_check(struct ixgbe_hw *hw) 5600 { 5601 uint32_t reg_val; 5602 5603 /* if Virtualization Technology is enabled */ 5604 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 5605 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) { 5606 PMD_INIT_LOG(ERR, "VT must be enabled for this setting"); 5607 return -1; 5608 } 5609 5610 return 0; 5611 } 5612 5613 static uint32_t 5614 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr) 5615 { 5616 uint32_t vector = 0; 5617 5618 switch (hw->mac.mc_filter_type) { 5619 case 0: /* use bits [47:36] of the address */ 5620 vector = ((uc_addr->addr_bytes[4] >> 4) | 5621 (((uint16_t)uc_addr->addr_bytes[5]) << 4)); 5622 break; 5623 case 1: /* use bits [46:35] of the address */ 5624 vector = ((uc_addr->addr_bytes[4] >> 3) | 5625 (((uint16_t)uc_addr->addr_bytes[5]) << 5)); 5626 break; 5627 case 2: /* use bits [45:34] of the address */ 5628 vector = ((uc_addr->addr_bytes[4] >> 2) | 5629 (((uint16_t)uc_addr->addr_bytes[5]) << 6)); 5630 break; 5631 case 3: /* use bits [43:32] of the address */ 5632 vector = ((uc_addr->addr_bytes[4]) | 5633 (((uint16_t)uc_addr->addr_bytes[5]) << 8)); 5634 break; 5635 default: /* Invalid mc_filter_type */ 5636 break; 5637 } 5638 5639 /* vector can only be 12-bits or boundary will be exceeded */ 5640 vector &= 0xFFF; 5641 return vector; 5642 } 5643 5644 static int 5645 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, 5646 struct rte_ether_addr *mac_addr, uint8_t on) 5647 { 5648 uint32_t vector; 5649 uint32_t uta_idx; 5650 uint32_t reg_val; 5651 uint32_t uta_shift; 5652 uint32_t rc; 5653 const uint32_t ixgbe_uta_idx_mask = 0x7F; 5654 const uint32_t ixgbe_uta_bit_shift = 5; 5655 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1; 5656 const uint32_t bit1 = 0x1; 5657 5658 struct ixgbe_hw *hw = 5659 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5660 struct ixgbe_uta_info *uta_info = 5661 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5662 5663 /* The UTA table only exists on 82599 hardware and newer */ 5664 if (hw->mac.type < ixgbe_mac_82599EB) 5665 return -ENOTSUP; 5666 5667 vector = ixgbe_uta_vector(hw, mac_addr); 5668 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask; 5669 uta_shift = vector & ixgbe_uta_bit_mask; 5670 5671 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0); 5672 if (rc == on) 5673 return 0; 5674 5675 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx)); 5676 if (on) { 5677 uta_info->uta_in_use++; 5678 reg_val |= (bit1 << uta_shift); 5679 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift); 5680 } else { 5681 uta_info->uta_in_use--; 5682 reg_val &= ~(bit1 << uta_shift); 5683 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift); 5684 } 5685 5686 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val); 5687 5688 if (uta_info->uta_in_use > 0) 5689 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 5690 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 5691 else 5692 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 5693 5694 return 0; 5695 } 5696 5697 static int 5698 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) 5699 { 5700 int i; 5701 struct ixgbe_hw *hw = 5702 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5703 struct ixgbe_uta_info *uta_info = 5704 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5705 5706 /* The UTA table only exists on 82599 hardware and newer */ 5707 if (hw->mac.type < ixgbe_mac_82599EB) 5708 return -ENOTSUP; 5709 5710 if (on) { 5711 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5712 uta_info->uta_shadow[i] = ~0; 5713 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); 5714 } 5715 } else { 5716 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5717 uta_info->uta_shadow[i] = 0; 5718 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 5719 } 5720 } 5721 return 0; 5722 5723 } 5724 5725 uint32_t 5726 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val) 5727 { 5728 uint32_t new_val = orig_val; 5729 5730 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG) 5731 new_val |= IXGBE_VMOLR_AUPE; 5732 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC) 5733 new_val |= IXGBE_VMOLR_ROMPE; 5734 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC) 5735 new_val |= IXGBE_VMOLR_ROPE; 5736 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST) 5737 new_val |= IXGBE_VMOLR_BAM; 5738 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST) 5739 new_val |= IXGBE_VMOLR_MPE; 5740 5741 return new_val; 5742 } 5743 5744 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */ 5745 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */ 5746 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */ 5747 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */ 5748 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \ 5749 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \ 5750 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN)) 5751 5752 static int 5753 ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 5754 struct rte_eth_mirror_conf *mirror_conf, 5755 uint8_t rule_id, uint8_t on) 5756 { 5757 uint32_t mr_ctl, vlvf; 5758 uint32_t mp_lsb = 0; 5759 uint32_t mv_msb = 0; 5760 uint32_t mv_lsb = 0; 5761 uint32_t mp_msb = 0; 5762 uint8_t i = 0; 5763 int reg_index = 0; 5764 uint64_t vlan_mask = 0; 5765 5766 const uint8_t pool_mask_offset = 32; 5767 const uint8_t vlan_mask_offset = 32; 5768 const uint8_t dst_pool_offset = 8; 5769 const uint8_t rule_mr_offset = 4; 5770 const uint8_t mirror_rule_mask = 0x0F; 5771 5772 struct ixgbe_mirror_info *mr_info = 5773 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5774 struct ixgbe_hw *hw = 5775 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5776 uint8_t mirror_type = 0; 5777 5778 if (ixgbe_vt_check(hw) < 0) 5779 return -ENOTSUP; 5780 5781 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5782 return -EINVAL; 5783 5784 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) { 5785 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.", 5786 mirror_conf->rule_type); 5787 return -EINVAL; 5788 } 5789 5790 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5791 mirror_type |= IXGBE_MRCTL_VLME; 5792 /* Check if vlan id is valid and find conresponding VLAN ID 5793 * index in VLVF 5794 */ 5795 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) { 5796 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) { 5797 /* search vlan id related pool vlan filter 5798 * index 5799 */ 5800 reg_index = ixgbe_find_vlvf_slot( 5801 hw, 5802 mirror_conf->vlan.vlan_id[i], 5803 false); 5804 if (reg_index < 0) 5805 return -EINVAL; 5806 vlvf = IXGBE_READ_REG(hw, 5807 IXGBE_VLVF(reg_index)); 5808 if ((vlvf & IXGBE_VLVF_VIEN) && 5809 ((vlvf & IXGBE_VLVF_VLANID_MASK) == 5810 mirror_conf->vlan.vlan_id[i])) 5811 vlan_mask |= (1ULL << reg_index); 5812 else 5813 return -EINVAL; 5814 } 5815 } 5816 5817 if (on) { 5818 mv_lsb = vlan_mask & 0xFFFFFFFF; 5819 mv_msb = vlan_mask >> vlan_mask_offset; 5820 5821 mr_info->mr_conf[rule_id].vlan.vlan_mask = 5822 mirror_conf->vlan.vlan_mask; 5823 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) { 5824 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) 5825 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 5826 mirror_conf->vlan.vlan_id[i]; 5827 } 5828 } else { 5829 mv_lsb = 0; 5830 mv_msb = 0; 5831 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0; 5832 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) 5833 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0; 5834 } 5835 } 5836 5837 /** 5838 * if enable pool mirror, write related pool mask register,if disable 5839 * pool mirror, clear PFMRVM register 5840 */ 5841 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5842 mirror_type |= IXGBE_MRCTL_VPME; 5843 if (on) { 5844 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF; 5845 mp_msb = mirror_conf->pool_mask >> pool_mask_offset; 5846 mr_info->mr_conf[rule_id].pool_mask = 5847 mirror_conf->pool_mask; 5848 5849 } else { 5850 mp_lsb = 0; 5851 mp_msb = 0; 5852 mr_info->mr_conf[rule_id].pool_mask = 0; 5853 } 5854 } 5855 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT) 5856 mirror_type |= IXGBE_MRCTL_UPME; 5857 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT) 5858 mirror_type |= IXGBE_MRCTL_DPME; 5859 5860 /* read mirror control register and recalculate it */ 5861 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id)); 5862 5863 if (on) { 5864 mr_ctl |= mirror_type; 5865 mr_ctl &= mirror_rule_mask; 5866 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset; 5867 } else { 5868 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask); 5869 } 5870 5871 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type; 5872 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool; 5873 5874 /* write mirrror control register */ 5875 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5876 5877 /* write pool mirrror control register */ 5878 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5879 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb); 5880 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), 5881 mp_msb); 5882 } 5883 /* write VLAN mirrror control register */ 5884 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5885 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb); 5886 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), 5887 mv_msb); 5888 } 5889 5890 return 0; 5891 } 5892 5893 static int 5894 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id) 5895 { 5896 int mr_ctl = 0; 5897 uint32_t lsb_val = 0; 5898 uint32_t msb_val = 0; 5899 const uint8_t rule_mr_offset = 4; 5900 5901 struct ixgbe_hw *hw = 5902 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5903 struct ixgbe_mirror_info *mr_info = 5904 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5905 5906 if (ixgbe_vt_check(hw) < 0) 5907 return -ENOTSUP; 5908 5909 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5910 return -EINVAL; 5911 5912 memset(&mr_info->mr_conf[rule_id], 0, 5913 sizeof(struct rte_eth_mirror_conf)); 5914 5915 /* clear PFVMCTL register */ 5916 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5917 5918 /* clear pool mask register */ 5919 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val); 5920 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val); 5921 5922 /* clear vlan mask register */ 5923 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val); 5924 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val); 5925 5926 return 0; 5927 } 5928 5929 static int 5930 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5931 { 5932 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5933 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5934 struct ixgbe_interrupt *intr = 5935 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5936 struct ixgbe_hw *hw = 5937 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5938 uint32_t vec = IXGBE_MISC_VEC_ID; 5939 5940 if (rte_intr_allow_others(intr_handle)) 5941 vec = IXGBE_RX_VEC_START; 5942 intr->mask |= (1 << vec); 5943 RTE_SET_USED(queue_id); 5944 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5945 5946 rte_intr_ack(intr_handle); 5947 5948 return 0; 5949 } 5950 5951 static int 5952 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5953 { 5954 struct ixgbe_interrupt *intr = 5955 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5956 struct ixgbe_hw *hw = 5957 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5958 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5959 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5960 uint32_t vec = IXGBE_MISC_VEC_ID; 5961 5962 if (rte_intr_allow_others(intr_handle)) 5963 vec = IXGBE_RX_VEC_START; 5964 intr->mask &= ~(1 << vec); 5965 RTE_SET_USED(queue_id); 5966 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5967 5968 return 0; 5969 } 5970 5971 static int 5972 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5973 { 5974 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5975 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5976 uint32_t mask; 5977 struct ixgbe_hw *hw = 5978 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5979 struct ixgbe_interrupt *intr = 5980 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5981 5982 if (queue_id < 16) { 5983 ixgbe_disable_intr(hw); 5984 intr->mask |= (1 << queue_id); 5985 ixgbe_enable_intr(dev); 5986 } else if (queue_id < 32) { 5987 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5988 mask &= (1 << queue_id); 5989 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5990 } else if (queue_id < 64) { 5991 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5992 mask &= (1 << (queue_id - 32)); 5993 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5994 } 5995 rte_intr_ack(intr_handle); 5996 5997 return 0; 5998 } 5999 6000 static int 6001 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 6002 { 6003 uint32_t mask; 6004 struct ixgbe_hw *hw = 6005 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6006 struct ixgbe_interrupt *intr = 6007 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 6008 6009 if (queue_id < 16) { 6010 ixgbe_disable_intr(hw); 6011 intr->mask &= ~(1 << queue_id); 6012 ixgbe_enable_intr(dev); 6013 } else if (queue_id < 32) { 6014 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 6015 mask &= ~(1 << queue_id); 6016 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 6017 } else if (queue_id < 64) { 6018 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 6019 mask &= ~(1 << (queue_id - 32)); 6020 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 6021 } 6022 6023 return 0; 6024 } 6025 6026 static void 6027 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 6028 uint8_t queue, uint8_t msix_vector) 6029 { 6030 uint32_t tmp, idx; 6031 6032 if (direction == -1) { 6033 /* other causes */ 6034 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 6035 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC); 6036 tmp &= ~0xFF; 6037 tmp |= msix_vector; 6038 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp); 6039 } else { 6040 /* rx or tx cause */ 6041 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 6042 idx = ((16 * (queue & 1)) + (8 * direction)); 6043 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1)); 6044 tmp &= ~(0xFF << idx); 6045 tmp |= (msix_vector << idx); 6046 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp); 6047 } 6048 } 6049 6050 /** 6051 * set the IVAR registers, mapping interrupt causes to vectors 6052 * @param hw 6053 * pointer to ixgbe_hw struct 6054 * @direction 6055 * 0 for Rx, 1 for Tx, -1 for other causes 6056 * @queue 6057 * queue to map the corresponding interrupt to 6058 * @msix_vector 6059 * the vector to map to the corresponding queue 6060 */ 6061 static void 6062 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 6063 uint8_t queue, uint8_t msix_vector) 6064 { 6065 uint32_t tmp, idx; 6066 6067 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 6068 if (hw->mac.type == ixgbe_mac_82598EB) { 6069 if (direction == -1) 6070 direction = 0; 6071 idx = (((direction * 64) + queue) >> 2) & 0x1F; 6072 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx)); 6073 tmp &= ~(0xFF << (8 * (queue & 0x3))); 6074 tmp |= (msix_vector << (8 * (queue & 0x3))); 6075 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp); 6076 } else if ((hw->mac.type == ixgbe_mac_82599EB) || 6077 (hw->mac.type == ixgbe_mac_X540) || 6078 (hw->mac.type == ixgbe_mac_X550) || 6079 (hw->mac.type == ixgbe_mac_X550EM_x)) { 6080 if (direction == -1) { 6081 /* other causes */ 6082 idx = ((queue & 1) * 8); 6083 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC); 6084 tmp &= ~(0xFF << idx); 6085 tmp |= (msix_vector << idx); 6086 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp); 6087 } else { 6088 /* rx or tx causes */ 6089 idx = ((16 * (queue & 1)) + (8 * direction)); 6090 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 6091 tmp &= ~(0xFF << idx); 6092 tmp |= (msix_vector << idx); 6093 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp); 6094 } 6095 } 6096 } 6097 6098 static void 6099 ixgbevf_configure_msix(struct rte_eth_dev *dev) 6100 { 6101 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 6102 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 6103 struct ixgbe_hw *hw = 6104 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6105 uint32_t q_idx; 6106 uint32_t vector_idx = IXGBE_MISC_VEC_ID; 6107 uint32_t base = IXGBE_MISC_VEC_ID; 6108 6109 /* Configure VF other cause ivar */ 6110 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx); 6111 6112 /* won't configure msix register if no mapping is done 6113 * between intr vector and event fd. 6114 */ 6115 if (!rte_intr_dp_is_en(intr_handle)) 6116 return; 6117 6118 if (rte_intr_allow_others(intr_handle)) { 6119 base = IXGBE_RX_VEC_START; 6120 vector_idx = IXGBE_RX_VEC_START; 6121 } 6122 6123 /* Configure all RX queues of VF */ 6124 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) { 6125 /* Force all queue use vector 0, 6126 * as IXGBE_VF_MAXMSIVECOTR = 1 6127 */ 6128 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx); 6129 intr_handle->intr_vec[q_idx] = vector_idx; 6130 if (vector_idx < base + intr_handle->nb_efd - 1) 6131 vector_idx++; 6132 } 6133 6134 /* As RX queue setting above show, all queues use the vector 0. 6135 * Set only the ITR value of IXGBE_MISC_VEC_ID. 6136 */ 6137 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID), 6138 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 6139 | IXGBE_EITR_CNT_WDIS); 6140 } 6141 6142 /** 6143 * Sets up the hardware to properly generate MSI-X interrupts 6144 * @hw 6145 * board private structure 6146 */ 6147 static void 6148 ixgbe_configure_msix(struct rte_eth_dev *dev) 6149 { 6150 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 6151 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 6152 struct ixgbe_hw *hw = 6153 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6154 uint32_t queue_id, base = IXGBE_MISC_VEC_ID; 6155 uint32_t vec = IXGBE_MISC_VEC_ID; 6156 uint32_t mask; 6157 uint32_t gpie; 6158 6159 /* won't configure msix register if no mapping is done 6160 * between intr vector and event fd 6161 * but if misx has been enabled already, need to configure 6162 * auto clean, auto mask and throttling. 6163 */ 6164 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 6165 if (!rte_intr_dp_is_en(intr_handle) && 6166 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT))) 6167 return; 6168 6169 if (rte_intr_allow_others(intr_handle)) 6170 vec = base = IXGBE_RX_VEC_START; 6171 6172 /* setup GPIE for MSI-x mode */ 6173 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 6174 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 6175 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME; 6176 /* auto clearing and auto setting corresponding bits in EIMS 6177 * when MSI-X interrupt is triggered 6178 */ 6179 if (hw->mac.type == ixgbe_mac_82598EB) { 6180 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 6181 } else { 6182 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 6183 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 6184 } 6185 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 6186 6187 /* Populate the IVAR table and set the ITR values to the 6188 * corresponding register. 6189 */ 6190 if (rte_intr_dp_is_en(intr_handle)) { 6191 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; 6192 queue_id++) { 6193 /* by default, 1:1 mapping */ 6194 ixgbe_set_ivar_map(hw, 0, queue_id, vec); 6195 intr_handle->intr_vec[queue_id] = vec; 6196 if (vec < base + intr_handle->nb_efd - 1) 6197 vec++; 6198 } 6199 6200 switch (hw->mac.type) { 6201 case ixgbe_mac_82598EB: 6202 ixgbe_set_ivar_map(hw, -1, 6203 IXGBE_IVAR_OTHER_CAUSES_INDEX, 6204 IXGBE_MISC_VEC_ID); 6205 break; 6206 case ixgbe_mac_82599EB: 6207 case ixgbe_mac_X540: 6208 case ixgbe_mac_X550: 6209 case ixgbe_mac_X550EM_x: 6210 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID); 6211 break; 6212 default: 6213 break; 6214 } 6215 } 6216 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID), 6217 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 6218 | IXGBE_EITR_CNT_WDIS); 6219 6220 /* set up to autoclear timer, and the vectors */ 6221 mask = IXGBE_EIMS_ENABLE_MASK; 6222 mask &= ~(IXGBE_EIMS_OTHER | 6223 IXGBE_EIMS_MAILBOX | 6224 IXGBE_EIMS_LSC); 6225 6226 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask); 6227 } 6228 6229 int 6230 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, 6231 uint16_t queue_idx, uint16_t tx_rate) 6232 { 6233 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6234 struct rte_eth_rxmode *rxmode; 6235 uint32_t rf_dec, rf_int; 6236 uint32_t bcnrc_val; 6237 uint16_t link_speed = dev->data->dev_link.link_speed; 6238 6239 if (queue_idx >= hw->mac.max_tx_queues) 6240 return -EINVAL; 6241 6242 if (tx_rate != 0) { 6243 /* Calculate the rate factor values to set */ 6244 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate; 6245 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate; 6246 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate; 6247 6248 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA; 6249 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) & 6250 IXGBE_RTTBCNRC_RF_INT_MASK_M); 6251 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK); 6252 } else { 6253 bcnrc_val = 0; 6254 } 6255 6256 rxmode = &dev->data->dev_conf.rxmode; 6257 /* 6258 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 6259 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise 6260 * set as 0x4. 6261 */ 6262 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) && 6263 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE)) 6264 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 6265 IXGBE_MMW_SIZE_JUMBO_FRAME); 6266 else 6267 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 6268 IXGBE_MMW_SIZE_DEFAULT); 6269 6270 /* Set RTTBCNRC of queue X */ 6271 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx); 6272 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 6273 IXGBE_WRITE_FLUSH(hw); 6274 6275 return 0; 6276 } 6277 6278 static int 6279 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 6280 __rte_unused uint32_t index, 6281 __rte_unused uint32_t pool) 6282 { 6283 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6284 int diag; 6285 6286 /* 6287 * On a 82599 VF, adding again the same MAC addr is not an idempotent 6288 * operation. Trap this case to avoid exhausting the [very limited] 6289 * set of PF resources used to store VF MAC addresses. 6290 */ 6291 if (memcmp(hw->mac.perm_addr, mac_addr, 6292 sizeof(struct rte_ether_addr)) == 0) 6293 return -1; 6294 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6295 if (diag != 0) 6296 PMD_DRV_LOG(ERR, "Unable to add MAC address " 6297 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d", 6298 mac_addr->addr_bytes[0], 6299 mac_addr->addr_bytes[1], 6300 mac_addr->addr_bytes[2], 6301 mac_addr->addr_bytes[3], 6302 mac_addr->addr_bytes[4], 6303 mac_addr->addr_bytes[5], 6304 diag); 6305 return diag; 6306 } 6307 6308 static void 6309 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index) 6310 { 6311 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6312 struct rte_ether_addr *perm_addr = 6313 (struct rte_ether_addr *)hw->mac.perm_addr; 6314 struct rte_ether_addr *mac_addr; 6315 uint32_t i; 6316 int diag; 6317 6318 /* 6319 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does 6320 * not support the deletion of a given MAC address. 6321 * Instead, it imposes to delete all MAC addresses, then to add again 6322 * all MAC addresses with the exception of the one to be deleted. 6323 */ 6324 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL); 6325 6326 /* 6327 * Add again all MAC addresses, with the exception of the deleted one 6328 * and of the permanent MAC address. 6329 */ 6330 for (i = 0, mac_addr = dev->data->mac_addrs; 6331 i < hw->mac.num_rar_entries; i++, mac_addr++) { 6332 /* Skip the deleted MAC address */ 6333 if (i == index) 6334 continue; 6335 /* Skip NULL MAC addresses */ 6336 if (rte_is_zero_ether_addr(mac_addr)) 6337 continue; 6338 /* Skip the permanent MAC address */ 6339 if (memcmp(perm_addr, mac_addr, 6340 sizeof(struct rte_ether_addr)) == 0) 6341 continue; 6342 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6343 if (diag != 0) 6344 PMD_DRV_LOG(ERR, 6345 "Adding again MAC address " 6346 "%02x:%02x:%02x:%02x:%02x:%02x failed " 6347 "diag=%d", 6348 mac_addr->addr_bytes[0], 6349 mac_addr->addr_bytes[1], 6350 mac_addr->addr_bytes[2], 6351 mac_addr->addr_bytes[3], 6352 mac_addr->addr_bytes[4], 6353 mac_addr->addr_bytes[5], 6354 diag); 6355 } 6356 } 6357 6358 static int 6359 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 6360 struct rte_ether_addr *addr) 6361 { 6362 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6363 6364 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0); 6365 6366 return 0; 6367 } 6368 6369 int 6370 ixgbe_syn_filter_set(struct rte_eth_dev *dev, 6371 struct rte_eth_syn_filter *filter, 6372 bool add) 6373 { 6374 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6375 struct ixgbe_filter_info *filter_info = 6376 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6377 uint32_t syn_info; 6378 uint32_t synqf; 6379 6380 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6381 return -EINVAL; 6382 6383 syn_info = filter_info->syn_info; 6384 6385 if (add) { 6386 if (syn_info & IXGBE_SYN_FILTER_ENABLE) 6387 return -EINVAL; 6388 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) & 6389 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE); 6390 6391 if (filter->hig_pri) 6392 synqf |= IXGBE_SYN_FILTER_SYNQFP; 6393 else 6394 synqf &= ~IXGBE_SYN_FILTER_SYNQFP; 6395 } else { 6396 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6397 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE)) 6398 return -ENOENT; 6399 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE); 6400 } 6401 6402 filter_info->syn_info = synqf; 6403 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 6404 IXGBE_WRITE_FLUSH(hw); 6405 return 0; 6406 } 6407 6408 static int 6409 ixgbe_syn_filter_get(struct rte_eth_dev *dev, 6410 struct rte_eth_syn_filter *filter) 6411 { 6412 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6413 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6414 6415 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 6416 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0; 6417 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1); 6418 return 0; 6419 } 6420 return -ENOENT; 6421 } 6422 6423 static int 6424 ixgbe_syn_filter_handle(struct rte_eth_dev *dev, 6425 enum rte_filter_op filter_op, 6426 void *arg) 6427 { 6428 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6429 int ret; 6430 6431 MAC_TYPE_FILTER_SUP(hw->mac.type); 6432 6433 if (filter_op == RTE_ETH_FILTER_NOP) 6434 return 0; 6435 6436 if (arg == NULL) { 6437 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u", 6438 filter_op); 6439 return -EINVAL; 6440 } 6441 6442 switch (filter_op) { 6443 case RTE_ETH_FILTER_ADD: 6444 ret = ixgbe_syn_filter_set(dev, 6445 (struct rte_eth_syn_filter *)arg, 6446 TRUE); 6447 break; 6448 case RTE_ETH_FILTER_DELETE: 6449 ret = ixgbe_syn_filter_set(dev, 6450 (struct rte_eth_syn_filter *)arg, 6451 FALSE); 6452 break; 6453 case RTE_ETH_FILTER_GET: 6454 ret = ixgbe_syn_filter_get(dev, 6455 (struct rte_eth_syn_filter *)arg); 6456 break; 6457 default: 6458 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op); 6459 ret = -EINVAL; 6460 break; 6461 } 6462 6463 return ret; 6464 } 6465 6466 6467 static inline enum ixgbe_5tuple_protocol 6468 convert_protocol_type(uint8_t protocol_value) 6469 { 6470 if (protocol_value == IPPROTO_TCP) 6471 return IXGBE_FILTER_PROTOCOL_TCP; 6472 else if (protocol_value == IPPROTO_UDP) 6473 return IXGBE_FILTER_PROTOCOL_UDP; 6474 else if (protocol_value == IPPROTO_SCTP) 6475 return IXGBE_FILTER_PROTOCOL_SCTP; 6476 else 6477 return IXGBE_FILTER_PROTOCOL_NONE; 6478 } 6479 6480 /* inject a 5-tuple filter to HW */ 6481 static inline void 6482 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev, 6483 struct ixgbe_5tuple_filter *filter) 6484 { 6485 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6486 int i; 6487 uint32_t ftqf, sdpqf; 6488 uint32_t l34timir = 0; 6489 uint8_t mask = 0xff; 6490 6491 i = filter->index; 6492 6493 sdpqf = (uint32_t)(filter->filter_info.dst_port << 6494 IXGBE_SDPQF_DSTPORT_SHIFT); 6495 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT); 6496 6497 ftqf = (uint32_t)(filter->filter_info.proto & 6498 IXGBE_FTQF_PROTOCOL_MASK); 6499 ftqf |= (uint32_t)((filter->filter_info.priority & 6500 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT); 6501 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */ 6502 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK; 6503 if (filter->filter_info.dst_ip_mask == 0) 6504 mask &= IXGBE_FTQF_DEST_ADDR_MASK; 6505 if (filter->filter_info.src_port_mask == 0) 6506 mask &= IXGBE_FTQF_SOURCE_PORT_MASK; 6507 if (filter->filter_info.dst_port_mask == 0) 6508 mask &= IXGBE_FTQF_DEST_PORT_MASK; 6509 if (filter->filter_info.proto_mask == 0) 6510 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK; 6511 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT; 6512 ftqf |= IXGBE_FTQF_POOL_MASK_EN; 6513 ftqf |= IXGBE_FTQF_QUEUE_ENABLE; 6514 6515 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip); 6516 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip); 6517 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf); 6518 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf); 6519 6520 l34timir |= IXGBE_L34T_IMIR_RESERVE; 6521 l34timir |= (uint32_t)(filter->queue << 6522 IXGBE_L34T_IMIR_QUEUE_SHIFT); 6523 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir); 6524 } 6525 6526 /* 6527 * add a 5tuple filter 6528 * 6529 * @param 6530 * dev: Pointer to struct rte_eth_dev. 6531 * index: the index the filter allocates. 6532 * filter: ponter to the filter that will be added. 6533 * rx_queue: the queue id the filter assigned to. 6534 * 6535 * @return 6536 * - On success, zero. 6537 * - On failure, a negative value. 6538 */ 6539 static int 6540 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 6541 struct ixgbe_5tuple_filter *filter) 6542 { 6543 struct ixgbe_filter_info *filter_info = 6544 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6545 int i, idx, shift; 6546 6547 /* 6548 * look for an unused 5tuple filter index, 6549 * and insert the filter to list. 6550 */ 6551 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) { 6552 idx = i / (sizeof(uint32_t) * NBBY); 6553 shift = i % (sizeof(uint32_t) * NBBY); 6554 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) { 6555 filter_info->fivetuple_mask[idx] |= 1 << shift; 6556 filter->index = i; 6557 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list, 6558 filter, 6559 entries); 6560 break; 6561 } 6562 } 6563 if (i >= IXGBE_MAX_FTQF_FILTERS) { 6564 PMD_DRV_LOG(ERR, "5tuple filters are full."); 6565 return -ENOSYS; 6566 } 6567 6568 ixgbe_inject_5tuple_filter(dev, filter); 6569 6570 return 0; 6571 } 6572 6573 /* 6574 * remove a 5tuple filter 6575 * 6576 * @param 6577 * dev: Pointer to struct rte_eth_dev. 6578 * filter: the pointer of the filter will be removed. 6579 */ 6580 static void 6581 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 6582 struct ixgbe_5tuple_filter *filter) 6583 { 6584 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6585 struct ixgbe_filter_info *filter_info = 6586 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6587 uint16_t index = filter->index; 6588 6589 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &= 6590 ~(1 << (index % (sizeof(uint32_t) * NBBY))); 6591 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries); 6592 rte_free(filter); 6593 6594 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0); 6595 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0); 6596 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0); 6597 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0); 6598 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0); 6599 } 6600 6601 static int 6602 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 6603 { 6604 struct ixgbe_hw *hw; 6605 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD; 6606 struct rte_eth_dev_data *dev_data = dev->data; 6607 6608 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6609 6610 if (mtu < RTE_ETHER_MIN_MTU || 6611 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN) 6612 return -EINVAL; 6613 6614 /* If device is started, refuse mtu that requires the support of 6615 * scattered packets when this feature has not been enabled before. 6616 */ 6617 if (dev_data->dev_started && !dev_data->scattered_rx && 6618 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE > 6619 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 6620 PMD_INIT_LOG(ERR, "Stop port first."); 6621 return -EINVAL; 6622 } 6623 6624 /* 6625 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU 6626 * request of the version 2.0 of the mailbox API. 6627 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0 6628 * of the mailbox API. 6629 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers 6630 * prior to 3.11.33 which contains the following change: 6631 * "ixgbe: Enable jumbo frames support w/ SR-IOV" 6632 */ 6633 ixgbevf_rlpml_set_vf(hw, max_frame); 6634 6635 /* update max frame size */ 6636 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame; 6637 return 0; 6638 } 6639 6640 static inline struct ixgbe_5tuple_filter * 6641 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list, 6642 struct ixgbe_5tuple_filter_info *key) 6643 { 6644 struct ixgbe_5tuple_filter *it; 6645 6646 TAILQ_FOREACH(it, filter_list, entries) { 6647 if (memcmp(key, &it->filter_info, 6648 sizeof(struct ixgbe_5tuple_filter_info)) == 0) { 6649 return it; 6650 } 6651 } 6652 return NULL; 6653 } 6654 6655 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/ 6656 static inline int 6657 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter, 6658 struct ixgbe_5tuple_filter_info *filter_info) 6659 { 6660 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM || 6661 filter->priority > IXGBE_5TUPLE_MAX_PRI || 6662 filter->priority < IXGBE_5TUPLE_MIN_PRI) 6663 return -EINVAL; 6664 6665 switch (filter->dst_ip_mask) { 6666 case UINT32_MAX: 6667 filter_info->dst_ip_mask = 0; 6668 filter_info->dst_ip = filter->dst_ip; 6669 break; 6670 case 0: 6671 filter_info->dst_ip_mask = 1; 6672 break; 6673 default: 6674 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 6675 return -EINVAL; 6676 } 6677 6678 switch (filter->src_ip_mask) { 6679 case UINT32_MAX: 6680 filter_info->src_ip_mask = 0; 6681 filter_info->src_ip = filter->src_ip; 6682 break; 6683 case 0: 6684 filter_info->src_ip_mask = 1; 6685 break; 6686 default: 6687 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 6688 return -EINVAL; 6689 } 6690 6691 switch (filter->dst_port_mask) { 6692 case UINT16_MAX: 6693 filter_info->dst_port_mask = 0; 6694 filter_info->dst_port = filter->dst_port; 6695 break; 6696 case 0: 6697 filter_info->dst_port_mask = 1; 6698 break; 6699 default: 6700 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 6701 return -EINVAL; 6702 } 6703 6704 switch (filter->src_port_mask) { 6705 case UINT16_MAX: 6706 filter_info->src_port_mask = 0; 6707 filter_info->src_port = filter->src_port; 6708 break; 6709 case 0: 6710 filter_info->src_port_mask = 1; 6711 break; 6712 default: 6713 PMD_DRV_LOG(ERR, "invalid src_port mask."); 6714 return -EINVAL; 6715 } 6716 6717 switch (filter->proto_mask) { 6718 case UINT8_MAX: 6719 filter_info->proto_mask = 0; 6720 filter_info->proto = 6721 convert_protocol_type(filter->proto); 6722 break; 6723 case 0: 6724 filter_info->proto_mask = 1; 6725 break; 6726 default: 6727 PMD_DRV_LOG(ERR, "invalid protocol mask."); 6728 return -EINVAL; 6729 } 6730 6731 filter_info->priority = (uint8_t)filter->priority; 6732 return 0; 6733 } 6734 6735 /* 6736 * add or delete a ntuple filter 6737 * 6738 * @param 6739 * dev: Pointer to struct rte_eth_dev. 6740 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6741 * add: if true, add filter, if false, remove filter 6742 * 6743 * @return 6744 * - On success, zero. 6745 * - On failure, a negative value. 6746 */ 6747 int 6748 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 6749 struct rte_eth_ntuple_filter *ntuple_filter, 6750 bool add) 6751 { 6752 struct ixgbe_filter_info *filter_info = 6753 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6754 struct ixgbe_5tuple_filter_info filter_5tuple; 6755 struct ixgbe_5tuple_filter *filter; 6756 int ret; 6757 6758 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6759 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6760 return -EINVAL; 6761 } 6762 6763 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6764 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6765 if (ret < 0) 6766 return ret; 6767 6768 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6769 &filter_5tuple); 6770 if (filter != NULL && add) { 6771 PMD_DRV_LOG(ERR, "filter exists."); 6772 return -EEXIST; 6773 } 6774 if (filter == NULL && !add) { 6775 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6776 return -ENOENT; 6777 } 6778 6779 if (add) { 6780 filter = rte_zmalloc("ixgbe_5tuple_filter", 6781 sizeof(struct ixgbe_5tuple_filter), 0); 6782 if (filter == NULL) 6783 return -ENOMEM; 6784 rte_memcpy(&filter->filter_info, 6785 &filter_5tuple, 6786 sizeof(struct ixgbe_5tuple_filter_info)); 6787 filter->queue = ntuple_filter->queue; 6788 ret = ixgbe_add_5tuple_filter(dev, filter); 6789 if (ret < 0) { 6790 rte_free(filter); 6791 return ret; 6792 } 6793 } else 6794 ixgbe_remove_5tuple_filter(dev, filter); 6795 6796 return 0; 6797 } 6798 6799 /* 6800 * get a ntuple filter 6801 * 6802 * @param 6803 * dev: Pointer to struct rte_eth_dev. 6804 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6805 * 6806 * @return 6807 * - On success, zero. 6808 * - On failure, a negative value. 6809 */ 6810 static int 6811 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev, 6812 struct rte_eth_ntuple_filter *ntuple_filter) 6813 { 6814 struct ixgbe_filter_info *filter_info = 6815 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6816 struct ixgbe_5tuple_filter_info filter_5tuple; 6817 struct ixgbe_5tuple_filter *filter; 6818 int ret; 6819 6820 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6821 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6822 return -EINVAL; 6823 } 6824 6825 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6826 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6827 if (ret < 0) 6828 return ret; 6829 6830 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6831 &filter_5tuple); 6832 if (filter == NULL) { 6833 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6834 return -ENOENT; 6835 } 6836 ntuple_filter->queue = filter->queue; 6837 return 0; 6838 } 6839 6840 /* 6841 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter. 6842 * @dev: pointer to rte_eth_dev structure 6843 * @filter_op:operation will be taken. 6844 * @arg: a pointer to specific structure corresponding to the filter_op 6845 * 6846 * @return 6847 * - On success, zero. 6848 * - On failure, a negative value. 6849 */ 6850 static int 6851 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev, 6852 enum rte_filter_op filter_op, 6853 void *arg) 6854 { 6855 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6856 int ret; 6857 6858 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type); 6859 6860 if (filter_op == RTE_ETH_FILTER_NOP) 6861 return 0; 6862 6863 if (arg == NULL) { 6864 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 6865 filter_op); 6866 return -EINVAL; 6867 } 6868 6869 switch (filter_op) { 6870 case RTE_ETH_FILTER_ADD: 6871 ret = ixgbe_add_del_ntuple_filter(dev, 6872 (struct rte_eth_ntuple_filter *)arg, 6873 TRUE); 6874 break; 6875 case RTE_ETH_FILTER_DELETE: 6876 ret = ixgbe_add_del_ntuple_filter(dev, 6877 (struct rte_eth_ntuple_filter *)arg, 6878 FALSE); 6879 break; 6880 case RTE_ETH_FILTER_GET: 6881 ret = ixgbe_get_ntuple_filter(dev, 6882 (struct rte_eth_ntuple_filter *)arg); 6883 break; 6884 default: 6885 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 6886 ret = -EINVAL; 6887 break; 6888 } 6889 return ret; 6890 } 6891 6892 int 6893 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 6894 struct rte_eth_ethertype_filter *filter, 6895 bool add) 6896 { 6897 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6898 struct ixgbe_filter_info *filter_info = 6899 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6900 uint32_t etqf = 0; 6901 uint32_t etqs = 0; 6902 int ret; 6903 struct ixgbe_ethertype_filter ethertype_filter; 6904 6905 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6906 return -EINVAL; 6907 6908 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 || 6909 filter->ether_type == RTE_ETHER_TYPE_IPV6) { 6910 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in" 6911 " ethertype filter.", filter->ether_type); 6912 return -EINVAL; 6913 } 6914 6915 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) { 6916 PMD_DRV_LOG(ERR, "mac compare is unsupported."); 6917 return -EINVAL; 6918 } 6919 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) { 6920 PMD_DRV_LOG(ERR, "drop option is unsupported."); 6921 return -EINVAL; 6922 } 6923 6924 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6925 if (ret >= 0 && add) { 6926 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.", 6927 filter->ether_type); 6928 return -EEXIST; 6929 } 6930 if (ret < 0 && !add) { 6931 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6932 filter->ether_type); 6933 return -ENOENT; 6934 } 6935 6936 if (add) { 6937 etqf = IXGBE_ETQF_FILTER_EN; 6938 etqf |= (uint32_t)filter->ether_type; 6939 etqs |= (uint32_t)((filter->queue << 6940 IXGBE_ETQS_RX_QUEUE_SHIFT) & 6941 IXGBE_ETQS_RX_QUEUE); 6942 etqs |= IXGBE_ETQS_QUEUE_EN; 6943 6944 ethertype_filter.ethertype = filter->ether_type; 6945 ethertype_filter.etqf = etqf; 6946 ethertype_filter.etqs = etqs; 6947 ethertype_filter.conf = FALSE; 6948 ret = ixgbe_ethertype_filter_insert(filter_info, 6949 ðertype_filter); 6950 if (ret < 0) { 6951 PMD_DRV_LOG(ERR, "ethertype filters are full."); 6952 return -ENOSPC; 6953 } 6954 } else { 6955 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret); 6956 if (ret < 0) 6957 return -ENOSYS; 6958 } 6959 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf); 6960 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs); 6961 IXGBE_WRITE_FLUSH(hw); 6962 6963 return 0; 6964 } 6965 6966 static int 6967 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, 6968 struct rte_eth_ethertype_filter *filter) 6969 { 6970 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6971 struct ixgbe_filter_info *filter_info = 6972 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6973 uint32_t etqf, etqs; 6974 int ret; 6975 6976 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6977 if (ret < 0) { 6978 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6979 filter->ether_type); 6980 return -ENOENT; 6981 } 6982 6983 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret)); 6984 if (etqf & IXGBE_ETQF_FILTER_EN) { 6985 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret)); 6986 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE; 6987 filter->flags = 0; 6988 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> 6989 IXGBE_ETQS_RX_QUEUE_SHIFT; 6990 return 0; 6991 } 6992 return -ENOENT; 6993 } 6994 6995 /* 6996 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter. 6997 * @dev: pointer to rte_eth_dev structure 6998 * @filter_op:operation will be taken. 6999 * @arg: a pointer to specific structure corresponding to the filter_op 7000 */ 7001 static int 7002 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev, 7003 enum rte_filter_op filter_op, 7004 void *arg) 7005 { 7006 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7007 int ret; 7008 7009 MAC_TYPE_FILTER_SUP(hw->mac.type); 7010 7011 if (filter_op == RTE_ETH_FILTER_NOP) 7012 return 0; 7013 7014 if (arg == NULL) { 7015 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 7016 filter_op); 7017 return -EINVAL; 7018 } 7019 7020 switch (filter_op) { 7021 case RTE_ETH_FILTER_ADD: 7022 ret = ixgbe_add_del_ethertype_filter(dev, 7023 (struct rte_eth_ethertype_filter *)arg, 7024 TRUE); 7025 break; 7026 case RTE_ETH_FILTER_DELETE: 7027 ret = ixgbe_add_del_ethertype_filter(dev, 7028 (struct rte_eth_ethertype_filter *)arg, 7029 FALSE); 7030 break; 7031 case RTE_ETH_FILTER_GET: 7032 ret = ixgbe_get_ethertype_filter(dev, 7033 (struct rte_eth_ethertype_filter *)arg); 7034 break; 7035 default: 7036 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 7037 ret = -EINVAL; 7038 break; 7039 } 7040 return ret; 7041 } 7042 7043 static int 7044 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 7045 enum rte_filter_type filter_type, 7046 enum rte_filter_op filter_op, 7047 void *arg) 7048 { 7049 int ret = 0; 7050 7051 switch (filter_type) { 7052 case RTE_ETH_FILTER_NTUPLE: 7053 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg); 7054 break; 7055 case RTE_ETH_FILTER_ETHERTYPE: 7056 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg); 7057 break; 7058 case RTE_ETH_FILTER_SYN: 7059 ret = ixgbe_syn_filter_handle(dev, filter_op, arg); 7060 break; 7061 case RTE_ETH_FILTER_FDIR: 7062 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg); 7063 break; 7064 case RTE_ETH_FILTER_L2_TUNNEL: 7065 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg); 7066 break; 7067 case RTE_ETH_FILTER_GENERIC: 7068 if (filter_op != RTE_ETH_FILTER_GET) 7069 return -EINVAL; 7070 *(const void **)arg = &ixgbe_flow_ops; 7071 break; 7072 default: 7073 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 7074 filter_type); 7075 ret = -EINVAL; 7076 break; 7077 } 7078 7079 return ret; 7080 } 7081 7082 static u8 * 7083 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw, 7084 u8 **mc_addr_ptr, u32 *vmdq) 7085 { 7086 u8 *mc_addr; 7087 7088 *vmdq = 0; 7089 mc_addr = *mc_addr_ptr; 7090 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr)); 7091 return mc_addr; 7092 } 7093 7094 static int 7095 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 7096 struct rte_ether_addr *mc_addr_set, 7097 uint32_t nb_mc_addr) 7098 { 7099 struct ixgbe_hw *hw; 7100 u8 *mc_addr_list; 7101 7102 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7103 mc_addr_list = (u8 *)mc_addr_set; 7104 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr, 7105 ixgbe_dev_addr_list_itr, TRUE); 7106 } 7107 7108 static uint64_t 7109 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev) 7110 { 7111 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7112 uint64_t systime_cycles; 7113 7114 switch (hw->mac.type) { 7115 case ixgbe_mac_X550: 7116 case ixgbe_mac_X550EM_x: 7117 case ixgbe_mac_X550EM_a: 7118 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */ 7119 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 7120 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 7121 * NSEC_PER_SEC; 7122 break; 7123 default: 7124 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 7125 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 7126 << 32; 7127 } 7128 7129 return systime_cycles; 7130 } 7131 7132 static uint64_t 7133 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) 7134 { 7135 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7136 uint64_t rx_tstamp_cycles; 7137 7138 switch (hw->mac.type) { 7139 case ixgbe_mac_X550: 7140 case ixgbe_mac_X550EM_x: 7141 case ixgbe_mac_X550EM_a: 7142 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 7143 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 7144 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 7145 * NSEC_PER_SEC; 7146 break; 7147 default: 7148 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 7149 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 7150 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 7151 << 32; 7152 } 7153 7154 return rx_tstamp_cycles; 7155 } 7156 7157 static uint64_t 7158 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 7159 { 7160 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7161 uint64_t tx_tstamp_cycles; 7162 7163 switch (hw->mac.type) { 7164 case ixgbe_mac_X550: 7165 case ixgbe_mac_X550EM_x: 7166 case ixgbe_mac_X550EM_a: 7167 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 7168 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 7169 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 7170 * NSEC_PER_SEC; 7171 break; 7172 default: 7173 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 7174 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 7175 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 7176 << 32; 7177 } 7178 7179 return tx_tstamp_cycles; 7180 } 7181 7182 static void 7183 ixgbe_start_timecounters(struct rte_eth_dev *dev) 7184 { 7185 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7186 struct ixgbe_adapter *adapter = dev->data->dev_private; 7187 struct rte_eth_link link; 7188 uint32_t incval = 0; 7189 uint32_t shift = 0; 7190 7191 /* Get current link speed. */ 7192 ixgbe_dev_link_update(dev, 1); 7193 rte_eth_linkstatus_get(dev, &link); 7194 7195 switch (link.link_speed) { 7196 case ETH_SPEED_NUM_100M: 7197 incval = IXGBE_INCVAL_100; 7198 shift = IXGBE_INCVAL_SHIFT_100; 7199 break; 7200 case ETH_SPEED_NUM_1G: 7201 incval = IXGBE_INCVAL_1GB; 7202 shift = IXGBE_INCVAL_SHIFT_1GB; 7203 break; 7204 case ETH_SPEED_NUM_10G: 7205 default: 7206 incval = IXGBE_INCVAL_10GB; 7207 shift = IXGBE_INCVAL_SHIFT_10GB; 7208 break; 7209 } 7210 7211 switch (hw->mac.type) { 7212 case ixgbe_mac_X550: 7213 case ixgbe_mac_X550EM_x: 7214 case ixgbe_mac_X550EM_a: 7215 /* Independent of link speed. */ 7216 incval = 1; 7217 /* Cycles read will be interpreted as ns. */ 7218 shift = 0; 7219 /* Fall-through */ 7220 case ixgbe_mac_X540: 7221 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval); 7222 break; 7223 case ixgbe_mac_82599EB: 7224 incval >>= IXGBE_INCVAL_SHIFT_82599; 7225 shift -= IXGBE_INCVAL_SHIFT_82599; 7226 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 7227 (1 << IXGBE_INCPER_SHIFT_82599) | incval); 7228 break; 7229 default: 7230 /* Not supported. */ 7231 return; 7232 } 7233 7234 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 7235 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 7236 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 7237 7238 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 7239 adapter->systime_tc.cc_shift = shift; 7240 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; 7241 7242 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 7243 adapter->rx_tstamp_tc.cc_shift = shift; 7244 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 7245 7246 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 7247 adapter->tx_tstamp_tc.cc_shift = shift; 7248 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 7249 } 7250 7251 static int 7252 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 7253 { 7254 struct ixgbe_adapter *adapter = dev->data->dev_private; 7255 7256 adapter->systime_tc.nsec += delta; 7257 adapter->rx_tstamp_tc.nsec += delta; 7258 adapter->tx_tstamp_tc.nsec += delta; 7259 7260 return 0; 7261 } 7262 7263 static int 7264 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 7265 { 7266 uint64_t ns; 7267 struct ixgbe_adapter *adapter = dev->data->dev_private; 7268 7269 ns = rte_timespec_to_ns(ts); 7270 /* Set the timecounters to a new value. */ 7271 adapter->systime_tc.nsec = ns; 7272 adapter->rx_tstamp_tc.nsec = ns; 7273 adapter->tx_tstamp_tc.nsec = ns; 7274 7275 return 0; 7276 } 7277 7278 static int 7279 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 7280 { 7281 uint64_t ns, systime_cycles; 7282 struct ixgbe_adapter *adapter = dev->data->dev_private; 7283 7284 systime_cycles = ixgbe_read_systime_cyclecounter(dev); 7285 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 7286 *ts = rte_ns_to_timespec(ns); 7287 7288 return 0; 7289 } 7290 7291 static int 7292 ixgbe_timesync_enable(struct rte_eth_dev *dev) 7293 { 7294 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7295 uint32_t tsync_ctl; 7296 uint32_t tsauxc; 7297 7298 /* Stop the timesync system time. */ 7299 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0); 7300 /* Reset the timesync system time value. */ 7301 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0); 7302 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0); 7303 7304 /* Enable system time for platforms where it isn't on by default. */ 7305 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC); 7306 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME; 7307 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc); 7308 7309 ixgbe_start_timecounters(dev); 7310 7311 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7312 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 7313 (RTE_ETHER_TYPE_1588 | 7314 IXGBE_ETQF_FILTER_EN | 7315 IXGBE_ETQF_1588)); 7316 7317 /* Enable timestamping of received PTP packets. */ 7318 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7319 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED; 7320 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7321 7322 /* Enable timestamping of transmitted PTP packets. */ 7323 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7324 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED; 7325 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7326 7327 IXGBE_WRITE_FLUSH(hw); 7328 7329 return 0; 7330 } 7331 7332 static int 7333 ixgbe_timesync_disable(struct rte_eth_dev *dev) 7334 { 7335 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7336 uint32_t tsync_ctl; 7337 7338 /* Disable timestamping of transmitted PTP packets. */ 7339 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7340 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED; 7341 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7342 7343 /* Disable timestamping of received PTP packets. */ 7344 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7345 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED; 7346 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7347 7348 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7349 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0); 7350 7351 /* Stop incrementating the System Time registers. */ 7352 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0); 7353 7354 return 0; 7355 } 7356 7357 static int 7358 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 7359 struct timespec *timestamp, 7360 uint32_t flags __rte_unused) 7361 { 7362 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7363 struct ixgbe_adapter *adapter = dev->data->dev_private; 7364 uint32_t tsync_rxctl; 7365 uint64_t rx_tstamp_cycles; 7366 uint64_t ns; 7367 7368 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7369 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0) 7370 return -EINVAL; 7371 7372 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev); 7373 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 7374 *timestamp = rte_ns_to_timespec(ns); 7375 7376 return 0; 7377 } 7378 7379 static int 7380 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 7381 struct timespec *timestamp) 7382 { 7383 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7384 struct ixgbe_adapter *adapter = dev->data->dev_private; 7385 uint32_t tsync_txctl; 7386 uint64_t tx_tstamp_cycles; 7387 uint64_t ns; 7388 7389 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7390 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0) 7391 return -EINVAL; 7392 7393 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev); 7394 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 7395 *timestamp = rte_ns_to_timespec(ns); 7396 7397 return 0; 7398 } 7399 7400 static int 7401 ixgbe_get_reg_length(struct rte_eth_dev *dev) 7402 { 7403 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7404 int count = 0; 7405 int g_ind = 0; 7406 const struct reg_info *reg_group; 7407 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7408 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7409 7410 while ((reg_group = reg_set[g_ind++])) 7411 count += ixgbe_regs_group_count(reg_group); 7412 7413 return count; 7414 } 7415 7416 static int 7417 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused) 7418 { 7419 int count = 0; 7420 int g_ind = 0; 7421 const struct reg_info *reg_group; 7422 7423 while ((reg_group = ixgbevf_regs[g_ind++])) 7424 count += ixgbe_regs_group_count(reg_group); 7425 7426 return count; 7427 } 7428 7429 static int 7430 ixgbe_get_regs(struct rte_eth_dev *dev, 7431 struct rte_dev_reg_info *regs) 7432 { 7433 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7434 uint32_t *data = regs->data; 7435 int g_ind = 0; 7436 int count = 0; 7437 const struct reg_info *reg_group; 7438 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7439 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7440 7441 if (data == NULL) { 7442 regs->length = ixgbe_get_reg_length(dev); 7443 regs->width = sizeof(uint32_t); 7444 return 0; 7445 } 7446 7447 /* Support only full register dump */ 7448 if ((regs->length == 0) || 7449 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) { 7450 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7451 hw->device_id; 7452 while ((reg_group = reg_set[g_ind++])) 7453 count += ixgbe_read_regs_group(dev, &data[count], 7454 reg_group); 7455 return 0; 7456 } 7457 7458 return -ENOTSUP; 7459 } 7460 7461 static int 7462 ixgbevf_get_regs(struct rte_eth_dev *dev, 7463 struct rte_dev_reg_info *regs) 7464 { 7465 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7466 uint32_t *data = regs->data; 7467 int g_ind = 0; 7468 int count = 0; 7469 const struct reg_info *reg_group; 7470 7471 if (data == NULL) { 7472 regs->length = ixgbevf_get_reg_length(dev); 7473 regs->width = sizeof(uint32_t); 7474 return 0; 7475 } 7476 7477 /* Support only full register dump */ 7478 if ((regs->length == 0) || 7479 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) { 7480 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7481 hw->device_id; 7482 while ((reg_group = ixgbevf_regs[g_ind++])) 7483 count += ixgbe_read_regs_group(dev, &data[count], 7484 reg_group); 7485 return 0; 7486 } 7487 7488 return -ENOTSUP; 7489 } 7490 7491 static int 7492 ixgbe_get_eeprom_length(struct rte_eth_dev *dev) 7493 { 7494 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7495 7496 /* Return unit is byte count */ 7497 return hw->eeprom.word_size * 2; 7498 } 7499 7500 static int 7501 ixgbe_get_eeprom(struct rte_eth_dev *dev, 7502 struct rte_dev_eeprom_info *in_eeprom) 7503 { 7504 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7505 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7506 uint16_t *data = in_eeprom->data; 7507 int first, length; 7508 7509 first = in_eeprom->offset >> 1; 7510 length = in_eeprom->length >> 1; 7511 if ((first > hw->eeprom.word_size) || 7512 ((first + length) > hw->eeprom.word_size)) 7513 return -EINVAL; 7514 7515 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7516 7517 return eeprom->ops.read_buffer(hw, first, length, data); 7518 } 7519 7520 static int 7521 ixgbe_set_eeprom(struct rte_eth_dev *dev, 7522 struct rte_dev_eeprom_info *in_eeprom) 7523 { 7524 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7525 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7526 uint16_t *data = in_eeprom->data; 7527 int first, length; 7528 7529 first = in_eeprom->offset >> 1; 7530 length = in_eeprom->length >> 1; 7531 if ((first > hw->eeprom.word_size) || 7532 ((first + length) > hw->eeprom.word_size)) 7533 return -EINVAL; 7534 7535 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7536 7537 return eeprom->ops.write_buffer(hw, first, length, data); 7538 } 7539 7540 static int 7541 ixgbe_get_module_info(struct rte_eth_dev *dev, 7542 struct rte_eth_dev_module_info *modinfo) 7543 { 7544 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7545 uint32_t status; 7546 uint8_t sff8472_rev, addr_mode; 7547 bool page_swap = false; 7548 7549 /* Check whether we support SFF-8472 or not */ 7550 status = hw->phy.ops.read_i2c_eeprom(hw, 7551 IXGBE_SFF_SFF_8472_COMP, 7552 &sff8472_rev); 7553 if (status != 0) 7554 return -EIO; 7555 7556 /* addressing mode is not supported */ 7557 status = hw->phy.ops.read_i2c_eeprom(hw, 7558 IXGBE_SFF_SFF_8472_SWAP, 7559 &addr_mode); 7560 if (status != 0) 7561 return -EIO; 7562 7563 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 7564 PMD_DRV_LOG(ERR, 7565 "Address change required to access page 0xA2, " 7566 "but not supported. Please report the module " 7567 "type to the driver maintainers."); 7568 page_swap = true; 7569 } 7570 7571 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) { 7572 /* We have a SFP, but it does not support SFF-8472 */ 7573 modinfo->type = RTE_ETH_MODULE_SFF_8079; 7574 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 7575 } else { 7576 /* We have a SFP which supports a revision of SFF-8472. */ 7577 modinfo->type = RTE_ETH_MODULE_SFF_8472; 7578 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 7579 } 7580 7581 return 0; 7582 } 7583 7584 static int 7585 ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 7586 struct rte_dev_eeprom_info *info) 7587 { 7588 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7589 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 7590 uint8_t databyte = 0xFF; 7591 uint8_t *data = info->data; 7592 uint32_t i = 0; 7593 7594 if (info->length == 0) 7595 return -EINVAL; 7596 7597 for (i = info->offset; i < info->offset + info->length; i++) { 7598 if (i < RTE_ETH_MODULE_SFF_8079_LEN) 7599 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 7600 else 7601 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 7602 7603 if (status != 0) 7604 return -EIO; 7605 7606 data[i - info->offset] = databyte; 7607 } 7608 7609 return 0; 7610 } 7611 7612 uint16_t 7613 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) { 7614 switch (mac_type) { 7615 case ixgbe_mac_X550: 7616 case ixgbe_mac_X550EM_x: 7617 case ixgbe_mac_X550EM_a: 7618 return ETH_RSS_RETA_SIZE_512; 7619 case ixgbe_mac_X550_vf: 7620 case ixgbe_mac_X550EM_x_vf: 7621 case ixgbe_mac_X550EM_a_vf: 7622 return ETH_RSS_RETA_SIZE_64; 7623 case ixgbe_mac_X540_vf: 7624 case ixgbe_mac_82599_vf: 7625 return 0; 7626 default: 7627 return ETH_RSS_RETA_SIZE_128; 7628 } 7629 } 7630 7631 uint32_t 7632 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) { 7633 switch (mac_type) { 7634 case ixgbe_mac_X550: 7635 case ixgbe_mac_X550EM_x: 7636 case ixgbe_mac_X550EM_a: 7637 if (reta_idx < ETH_RSS_RETA_SIZE_128) 7638 return IXGBE_RETA(reta_idx >> 2); 7639 else 7640 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2); 7641 case ixgbe_mac_X550_vf: 7642 case ixgbe_mac_X550EM_x_vf: 7643 case ixgbe_mac_X550EM_a_vf: 7644 return IXGBE_VFRETA(reta_idx >> 2); 7645 default: 7646 return IXGBE_RETA(reta_idx >> 2); 7647 } 7648 } 7649 7650 uint32_t 7651 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) { 7652 switch (mac_type) { 7653 case ixgbe_mac_X550_vf: 7654 case ixgbe_mac_X550EM_x_vf: 7655 case ixgbe_mac_X550EM_a_vf: 7656 return IXGBE_VFMRQC; 7657 default: 7658 return IXGBE_MRQC; 7659 } 7660 } 7661 7662 uint32_t 7663 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) { 7664 switch (mac_type) { 7665 case ixgbe_mac_X550_vf: 7666 case ixgbe_mac_X550EM_x_vf: 7667 case ixgbe_mac_X550EM_a_vf: 7668 return IXGBE_VFRSSRK(i); 7669 default: 7670 return IXGBE_RSSRK(i); 7671 } 7672 } 7673 7674 bool 7675 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) { 7676 switch (mac_type) { 7677 case ixgbe_mac_82599_vf: 7678 case ixgbe_mac_X540_vf: 7679 return 0; 7680 default: 7681 return 1; 7682 } 7683 } 7684 7685 static int 7686 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 7687 struct rte_eth_dcb_info *dcb_info) 7688 { 7689 struct ixgbe_dcb_config *dcb_config = 7690 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 7691 struct ixgbe_dcb_tc_config *tc; 7692 struct rte_eth_dcb_tc_queue_mapping *tc_queue; 7693 uint8_t nb_tcs; 7694 uint8_t i, j; 7695 7696 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG) 7697 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs; 7698 else 7699 dcb_info->nb_tcs = 1; 7700 7701 tc_queue = &dcb_info->tc_queue; 7702 nb_tcs = dcb_info->nb_tcs; 7703 7704 if (dcb_config->vt_mode) { /* vt is enabled*/ 7705 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf = 7706 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf; 7707 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7708 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i]; 7709 if (RTE_ETH_DEV_SRIOV(dev).active > 0) { 7710 for (j = 0; j < nb_tcs; j++) { 7711 tc_queue->tc_rxq[0][j].base = j; 7712 tc_queue->tc_rxq[0][j].nb_queue = 1; 7713 tc_queue->tc_txq[0][j].base = j; 7714 tc_queue->tc_txq[0][j].nb_queue = 1; 7715 } 7716 } else { 7717 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) { 7718 for (j = 0; j < nb_tcs; j++) { 7719 tc_queue->tc_rxq[i][j].base = 7720 i * nb_tcs + j; 7721 tc_queue->tc_rxq[i][j].nb_queue = 1; 7722 tc_queue->tc_txq[i][j].base = 7723 i * nb_tcs + j; 7724 tc_queue->tc_txq[i][j].nb_queue = 1; 7725 } 7726 } 7727 } 7728 } else { /* vt is disabled*/ 7729 struct rte_eth_dcb_rx_conf *rx_conf = 7730 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 7731 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7732 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i]; 7733 if (dcb_info->nb_tcs == ETH_4_TCS) { 7734 for (i = 0; i < dcb_info->nb_tcs; i++) { 7735 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32; 7736 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7737 } 7738 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7739 dcb_info->tc_queue.tc_txq[0][1].base = 64; 7740 dcb_info->tc_queue.tc_txq[0][2].base = 96; 7741 dcb_info->tc_queue.tc_txq[0][3].base = 112; 7742 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64; 7743 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7744 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7745 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7746 } else if (dcb_info->nb_tcs == ETH_8_TCS) { 7747 for (i = 0; i < dcb_info->nb_tcs; i++) { 7748 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16; 7749 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7750 } 7751 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7752 dcb_info->tc_queue.tc_txq[0][1].base = 32; 7753 dcb_info->tc_queue.tc_txq[0][2].base = 64; 7754 dcb_info->tc_queue.tc_txq[0][3].base = 80; 7755 dcb_info->tc_queue.tc_txq[0][4].base = 96; 7756 dcb_info->tc_queue.tc_txq[0][5].base = 104; 7757 dcb_info->tc_queue.tc_txq[0][6].base = 112; 7758 dcb_info->tc_queue.tc_txq[0][7].base = 120; 7759 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32; 7760 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7761 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7762 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7763 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8; 7764 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8; 7765 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8; 7766 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8; 7767 } 7768 } 7769 for (i = 0; i < dcb_info->nb_tcs; i++) { 7770 tc = &dcb_config->tc_config[i]; 7771 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent; 7772 } 7773 return 0; 7774 } 7775 7776 /* Update e-tag ether type */ 7777 static int 7778 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw, 7779 uint16_t ether_type) 7780 { 7781 uint32_t etag_etype; 7782 7783 if (hw->mac.type != ixgbe_mac_X550 && 7784 hw->mac.type != ixgbe_mac_X550EM_x && 7785 hw->mac.type != ixgbe_mac_X550EM_a) { 7786 return -ENOTSUP; 7787 } 7788 7789 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7790 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK; 7791 etag_etype |= ether_type; 7792 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7793 IXGBE_WRITE_FLUSH(hw); 7794 7795 return 0; 7796 } 7797 7798 /* Config l2 tunnel ether type */ 7799 static int 7800 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev, 7801 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7802 { 7803 int ret = 0; 7804 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7805 struct ixgbe_l2_tn_info *l2_tn_info = 7806 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7807 7808 if (l2_tunnel == NULL) 7809 return -EINVAL; 7810 7811 switch (l2_tunnel->l2_tunnel_type) { 7812 case RTE_L2_TUNNEL_TYPE_E_TAG: 7813 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type; 7814 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type); 7815 break; 7816 default: 7817 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7818 ret = -EINVAL; 7819 break; 7820 } 7821 7822 return ret; 7823 } 7824 7825 /* Enable e-tag tunnel */ 7826 static int 7827 ixgbe_e_tag_enable(struct ixgbe_hw *hw) 7828 { 7829 uint32_t etag_etype; 7830 7831 if (hw->mac.type != ixgbe_mac_X550 && 7832 hw->mac.type != ixgbe_mac_X550EM_x && 7833 hw->mac.type != ixgbe_mac_X550EM_a) { 7834 return -ENOTSUP; 7835 } 7836 7837 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7838 etag_etype |= IXGBE_ETAG_ETYPE_VALID; 7839 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7840 IXGBE_WRITE_FLUSH(hw); 7841 7842 return 0; 7843 } 7844 7845 /* Enable l2 tunnel */ 7846 static int 7847 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev, 7848 enum rte_eth_tunnel_type l2_tunnel_type) 7849 { 7850 int ret = 0; 7851 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7852 struct ixgbe_l2_tn_info *l2_tn_info = 7853 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7854 7855 switch (l2_tunnel_type) { 7856 case RTE_L2_TUNNEL_TYPE_E_TAG: 7857 l2_tn_info->e_tag_en = TRUE; 7858 ret = ixgbe_e_tag_enable(hw); 7859 break; 7860 default: 7861 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7862 ret = -EINVAL; 7863 break; 7864 } 7865 7866 return ret; 7867 } 7868 7869 /* Disable e-tag tunnel */ 7870 static int 7871 ixgbe_e_tag_disable(struct ixgbe_hw *hw) 7872 { 7873 uint32_t etag_etype; 7874 7875 if (hw->mac.type != ixgbe_mac_X550 && 7876 hw->mac.type != ixgbe_mac_X550EM_x && 7877 hw->mac.type != ixgbe_mac_X550EM_a) { 7878 return -ENOTSUP; 7879 } 7880 7881 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7882 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID; 7883 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7884 IXGBE_WRITE_FLUSH(hw); 7885 7886 return 0; 7887 } 7888 7889 /* Disable l2 tunnel */ 7890 static int 7891 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev, 7892 enum rte_eth_tunnel_type l2_tunnel_type) 7893 { 7894 int ret = 0; 7895 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7896 struct ixgbe_l2_tn_info *l2_tn_info = 7897 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7898 7899 switch (l2_tunnel_type) { 7900 case RTE_L2_TUNNEL_TYPE_E_TAG: 7901 l2_tn_info->e_tag_en = FALSE; 7902 ret = ixgbe_e_tag_disable(hw); 7903 break; 7904 default: 7905 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7906 ret = -EINVAL; 7907 break; 7908 } 7909 7910 return ret; 7911 } 7912 7913 static int 7914 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev, 7915 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7916 { 7917 int ret = 0; 7918 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7919 uint32_t i, rar_entries; 7920 uint32_t rar_low, rar_high; 7921 7922 if (hw->mac.type != ixgbe_mac_X550 && 7923 hw->mac.type != ixgbe_mac_X550EM_x && 7924 hw->mac.type != ixgbe_mac_X550EM_a) { 7925 return -ENOTSUP; 7926 } 7927 7928 rar_entries = ixgbe_get_num_rx_addrs(hw); 7929 7930 for (i = 1; i < rar_entries; i++) { 7931 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7932 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 7933 if ((rar_high & IXGBE_RAH_AV) && 7934 (rar_high & IXGBE_RAH_ADTYPE) && 7935 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) == 7936 l2_tunnel->tunnel_id)) { 7937 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 7938 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 7939 7940 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL); 7941 7942 return ret; 7943 } 7944 } 7945 7946 return ret; 7947 } 7948 7949 static int 7950 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev, 7951 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7952 { 7953 int ret = 0; 7954 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7955 uint32_t i, rar_entries; 7956 uint32_t rar_low, rar_high; 7957 7958 if (hw->mac.type != ixgbe_mac_X550 && 7959 hw->mac.type != ixgbe_mac_X550EM_x && 7960 hw->mac.type != ixgbe_mac_X550EM_a) { 7961 return -ENOTSUP; 7962 } 7963 7964 /* One entry for one tunnel. Try to remove potential existing entry. */ 7965 ixgbe_e_tag_filter_del(dev, l2_tunnel); 7966 7967 rar_entries = ixgbe_get_num_rx_addrs(hw); 7968 7969 for (i = 1; i < rar_entries; i++) { 7970 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7971 if (rar_high & IXGBE_RAH_AV) { 7972 continue; 7973 } else { 7974 ixgbe_set_vmdq(hw, i, l2_tunnel->pool); 7975 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE; 7976 rar_low = l2_tunnel->tunnel_id; 7977 7978 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low); 7979 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high); 7980 7981 return ret; 7982 } 7983 } 7984 7985 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full." 7986 " Please remove a rule before adding a new one."); 7987 return -EINVAL; 7988 } 7989 7990 static inline struct ixgbe_l2_tn_filter * 7991 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info, 7992 struct ixgbe_l2_tn_key *key) 7993 { 7994 int ret; 7995 7996 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key); 7997 if (ret < 0) 7998 return NULL; 7999 8000 return l2_tn_info->hash_map[ret]; 8001 } 8002 8003 static inline int 8004 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 8005 struct ixgbe_l2_tn_filter *l2_tn_filter) 8006 { 8007 int ret; 8008 8009 ret = rte_hash_add_key(l2_tn_info->hash_handle, 8010 &l2_tn_filter->key); 8011 8012 if (ret < 0) { 8013 PMD_DRV_LOG(ERR, 8014 "Failed to insert L2 tunnel filter" 8015 " to hash table %d!", 8016 ret); 8017 return ret; 8018 } 8019 8020 l2_tn_info->hash_map[ret] = l2_tn_filter; 8021 8022 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 8023 8024 return 0; 8025 } 8026 8027 static inline int 8028 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 8029 struct ixgbe_l2_tn_key *key) 8030 { 8031 int ret; 8032 struct ixgbe_l2_tn_filter *l2_tn_filter; 8033 8034 ret = rte_hash_del_key(l2_tn_info->hash_handle, key); 8035 8036 if (ret < 0) { 8037 PMD_DRV_LOG(ERR, 8038 "No such L2 tunnel filter to delete %d!", 8039 ret); 8040 return ret; 8041 } 8042 8043 l2_tn_filter = l2_tn_info->hash_map[ret]; 8044 l2_tn_info->hash_map[ret] = NULL; 8045 8046 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 8047 rte_free(l2_tn_filter); 8048 8049 return 0; 8050 } 8051 8052 /* Add l2 tunnel filter */ 8053 int 8054 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 8055 struct rte_eth_l2_tunnel_conf *l2_tunnel, 8056 bool restore) 8057 { 8058 int ret; 8059 struct ixgbe_l2_tn_info *l2_tn_info = 8060 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8061 struct ixgbe_l2_tn_key key; 8062 struct ixgbe_l2_tn_filter *node; 8063 8064 if (!restore) { 8065 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 8066 key.tn_id = l2_tunnel->tunnel_id; 8067 8068 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key); 8069 8070 if (node) { 8071 PMD_DRV_LOG(ERR, 8072 "The L2 tunnel filter already exists!"); 8073 return -EINVAL; 8074 } 8075 8076 node = rte_zmalloc("ixgbe_l2_tn", 8077 sizeof(struct ixgbe_l2_tn_filter), 8078 0); 8079 if (!node) 8080 return -ENOMEM; 8081 8082 rte_memcpy(&node->key, 8083 &key, 8084 sizeof(struct ixgbe_l2_tn_key)); 8085 node->pool = l2_tunnel->pool; 8086 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node); 8087 if (ret < 0) { 8088 rte_free(node); 8089 return ret; 8090 } 8091 } 8092 8093 switch (l2_tunnel->l2_tunnel_type) { 8094 case RTE_L2_TUNNEL_TYPE_E_TAG: 8095 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel); 8096 break; 8097 default: 8098 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8099 ret = -EINVAL; 8100 break; 8101 } 8102 8103 if ((!restore) && (ret < 0)) 8104 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 8105 8106 return ret; 8107 } 8108 8109 /* Delete l2 tunnel filter */ 8110 int 8111 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 8112 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8113 { 8114 int ret; 8115 struct ixgbe_l2_tn_info *l2_tn_info = 8116 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8117 struct ixgbe_l2_tn_key key; 8118 8119 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 8120 key.tn_id = l2_tunnel->tunnel_id; 8121 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 8122 if (ret < 0) 8123 return ret; 8124 8125 switch (l2_tunnel->l2_tunnel_type) { 8126 case RTE_L2_TUNNEL_TYPE_E_TAG: 8127 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel); 8128 break; 8129 default: 8130 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8131 ret = -EINVAL; 8132 break; 8133 } 8134 8135 return ret; 8136 } 8137 8138 /** 8139 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter. 8140 * @dev: pointer to rte_eth_dev structure 8141 * @filter_op:operation will be taken. 8142 * @arg: a pointer to specific structure corresponding to the filter_op 8143 */ 8144 static int 8145 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev, 8146 enum rte_filter_op filter_op, 8147 void *arg) 8148 { 8149 int ret; 8150 8151 if (filter_op == RTE_ETH_FILTER_NOP) 8152 return 0; 8153 8154 if (arg == NULL) { 8155 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 8156 filter_op); 8157 return -EINVAL; 8158 } 8159 8160 switch (filter_op) { 8161 case RTE_ETH_FILTER_ADD: 8162 ret = ixgbe_dev_l2_tunnel_filter_add 8163 (dev, 8164 (struct rte_eth_l2_tunnel_conf *)arg, 8165 FALSE); 8166 break; 8167 case RTE_ETH_FILTER_DELETE: 8168 ret = ixgbe_dev_l2_tunnel_filter_del 8169 (dev, 8170 (struct rte_eth_l2_tunnel_conf *)arg); 8171 break; 8172 default: 8173 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 8174 ret = -EINVAL; 8175 break; 8176 } 8177 return ret; 8178 } 8179 8180 static int 8181 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en) 8182 { 8183 int ret = 0; 8184 uint32_t ctrl; 8185 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8186 8187 if (hw->mac.type != ixgbe_mac_X550 && 8188 hw->mac.type != ixgbe_mac_X550EM_x && 8189 hw->mac.type != ixgbe_mac_X550EM_a) { 8190 return -ENOTSUP; 8191 } 8192 8193 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 8194 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 8195 if (en) 8196 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG; 8197 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 8198 8199 return ret; 8200 } 8201 8202 /* Enable l2 tunnel forwarding */ 8203 static int 8204 ixgbe_dev_l2_tunnel_forwarding_enable 8205 (struct rte_eth_dev *dev, 8206 enum rte_eth_tunnel_type l2_tunnel_type) 8207 { 8208 struct ixgbe_l2_tn_info *l2_tn_info = 8209 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8210 int ret = 0; 8211 8212 switch (l2_tunnel_type) { 8213 case RTE_L2_TUNNEL_TYPE_E_TAG: 8214 l2_tn_info->e_tag_fwd_en = TRUE; 8215 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1); 8216 break; 8217 default: 8218 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8219 ret = -EINVAL; 8220 break; 8221 } 8222 8223 return ret; 8224 } 8225 8226 /* Disable l2 tunnel forwarding */ 8227 static int 8228 ixgbe_dev_l2_tunnel_forwarding_disable 8229 (struct rte_eth_dev *dev, 8230 enum rte_eth_tunnel_type l2_tunnel_type) 8231 { 8232 struct ixgbe_l2_tn_info *l2_tn_info = 8233 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8234 int ret = 0; 8235 8236 switch (l2_tunnel_type) { 8237 case RTE_L2_TUNNEL_TYPE_E_TAG: 8238 l2_tn_info->e_tag_fwd_en = FALSE; 8239 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0); 8240 break; 8241 default: 8242 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8243 ret = -EINVAL; 8244 break; 8245 } 8246 8247 return ret; 8248 } 8249 8250 static int 8251 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev, 8252 struct rte_eth_l2_tunnel_conf *l2_tunnel, 8253 bool en) 8254 { 8255 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 8256 int ret = 0; 8257 uint32_t vmtir, vmvir; 8258 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8259 8260 if (l2_tunnel->vf_id >= pci_dev->max_vfs) { 8261 PMD_DRV_LOG(ERR, 8262 "VF id %u should be less than %u", 8263 l2_tunnel->vf_id, 8264 pci_dev->max_vfs); 8265 return -EINVAL; 8266 } 8267 8268 if (hw->mac.type != ixgbe_mac_X550 && 8269 hw->mac.type != ixgbe_mac_X550EM_x && 8270 hw->mac.type != ixgbe_mac_X550EM_a) { 8271 return -ENOTSUP; 8272 } 8273 8274 if (en) 8275 vmtir = l2_tunnel->tunnel_id; 8276 else 8277 vmtir = 0; 8278 8279 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir); 8280 8281 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id)); 8282 vmvir &= ~IXGBE_VMVIR_TAGA_MASK; 8283 if (en) 8284 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT; 8285 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir); 8286 8287 return ret; 8288 } 8289 8290 /* Enable l2 tunnel tag insertion */ 8291 static int 8292 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev, 8293 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8294 { 8295 int ret = 0; 8296 8297 switch (l2_tunnel->l2_tunnel_type) { 8298 case RTE_L2_TUNNEL_TYPE_E_TAG: 8299 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1); 8300 break; 8301 default: 8302 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8303 ret = -EINVAL; 8304 break; 8305 } 8306 8307 return ret; 8308 } 8309 8310 /* Disable l2 tunnel tag insertion */ 8311 static int 8312 ixgbe_dev_l2_tunnel_insertion_disable 8313 (struct rte_eth_dev *dev, 8314 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8315 { 8316 int ret = 0; 8317 8318 switch (l2_tunnel->l2_tunnel_type) { 8319 case RTE_L2_TUNNEL_TYPE_E_TAG: 8320 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0); 8321 break; 8322 default: 8323 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8324 ret = -EINVAL; 8325 break; 8326 } 8327 8328 return ret; 8329 } 8330 8331 static int 8332 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev, 8333 bool en) 8334 { 8335 int ret = 0; 8336 uint32_t qde; 8337 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8338 8339 if (hw->mac.type != ixgbe_mac_X550 && 8340 hw->mac.type != ixgbe_mac_X550EM_x && 8341 hw->mac.type != ixgbe_mac_X550EM_a) { 8342 return -ENOTSUP; 8343 } 8344 8345 qde = IXGBE_READ_REG(hw, IXGBE_QDE); 8346 if (en) 8347 qde |= IXGBE_QDE_STRIP_TAG; 8348 else 8349 qde &= ~IXGBE_QDE_STRIP_TAG; 8350 qde &= ~IXGBE_QDE_READ; 8351 qde |= IXGBE_QDE_WRITE; 8352 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde); 8353 8354 return ret; 8355 } 8356 8357 /* Enable l2 tunnel tag stripping */ 8358 static int 8359 ixgbe_dev_l2_tunnel_stripping_enable 8360 (struct rte_eth_dev *dev, 8361 enum rte_eth_tunnel_type l2_tunnel_type) 8362 { 8363 int ret = 0; 8364 8365 switch (l2_tunnel_type) { 8366 case RTE_L2_TUNNEL_TYPE_E_TAG: 8367 ret = ixgbe_e_tag_stripping_en_dis(dev, 1); 8368 break; 8369 default: 8370 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8371 ret = -EINVAL; 8372 break; 8373 } 8374 8375 return ret; 8376 } 8377 8378 /* Disable l2 tunnel tag stripping */ 8379 static int 8380 ixgbe_dev_l2_tunnel_stripping_disable 8381 (struct rte_eth_dev *dev, 8382 enum rte_eth_tunnel_type l2_tunnel_type) 8383 { 8384 int ret = 0; 8385 8386 switch (l2_tunnel_type) { 8387 case RTE_L2_TUNNEL_TYPE_E_TAG: 8388 ret = ixgbe_e_tag_stripping_en_dis(dev, 0); 8389 break; 8390 default: 8391 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8392 ret = -EINVAL; 8393 break; 8394 } 8395 8396 return ret; 8397 } 8398 8399 /* Enable/disable l2 tunnel offload functions */ 8400 static int 8401 ixgbe_dev_l2_tunnel_offload_set 8402 (struct rte_eth_dev *dev, 8403 struct rte_eth_l2_tunnel_conf *l2_tunnel, 8404 uint32_t mask, 8405 uint8_t en) 8406 { 8407 int ret = 0; 8408 8409 if (l2_tunnel == NULL) 8410 return -EINVAL; 8411 8412 ret = -EINVAL; 8413 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) { 8414 if (en) 8415 ret = ixgbe_dev_l2_tunnel_enable( 8416 dev, 8417 l2_tunnel->l2_tunnel_type); 8418 else 8419 ret = ixgbe_dev_l2_tunnel_disable( 8420 dev, 8421 l2_tunnel->l2_tunnel_type); 8422 } 8423 8424 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) { 8425 if (en) 8426 ret = ixgbe_dev_l2_tunnel_insertion_enable( 8427 dev, 8428 l2_tunnel); 8429 else 8430 ret = ixgbe_dev_l2_tunnel_insertion_disable( 8431 dev, 8432 l2_tunnel); 8433 } 8434 8435 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) { 8436 if (en) 8437 ret = ixgbe_dev_l2_tunnel_stripping_enable( 8438 dev, 8439 l2_tunnel->l2_tunnel_type); 8440 else 8441 ret = ixgbe_dev_l2_tunnel_stripping_disable( 8442 dev, 8443 l2_tunnel->l2_tunnel_type); 8444 } 8445 8446 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) { 8447 if (en) 8448 ret = ixgbe_dev_l2_tunnel_forwarding_enable( 8449 dev, 8450 l2_tunnel->l2_tunnel_type); 8451 else 8452 ret = ixgbe_dev_l2_tunnel_forwarding_disable( 8453 dev, 8454 l2_tunnel->l2_tunnel_type); 8455 } 8456 8457 return ret; 8458 } 8459 8460 static int 8461 ixgbe_update_vxlan_port(struct ixgbe_hw *hw, 8462 uint16_t port) 8463 { 8464 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port); 8465 IXGBE_WRITE_FLUSH(hw); 8466 8467 return 0; 8468 } 8469 8470 /* There's only one register for VxLAN UDP port. 8471 * So, we cannot add several ports. Will update it. 8472 */ 8473 static int 8474 ixgbe_add_vxlan_port(struct ixgbe_hw *hw, 8475 uint16_t port) 8476 { 8477 if (port == 0) { 8478 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 8479 return -EINVAL; 8480 } 8481 8482 return ixgbe_update_vxlan_port(hw, port); 8483 } 8484 8485 /* We cannot delete the VxLAN port. For there's a register for VxLAN 8486 * UDP port, it must have a value. 8487 * So, will reset it to the original value 0. 8488 */ 8489 static int 8490 ixgbe_del_vxlan_port(struct ixgbe_hw *hw, 8491 uint16_t port) 8492 { 8493 uint16_t cur_port; 8494 8495 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL); 8496 8497 if (cur_port != port) { 8498 PMD_DRV_LOG(ERR, "Port %u does not exist.", port); 8499 return -EINVAL; 8500 } 8501 8502 return ixgbe_update_vxlan_port(hw, 0); 8503 } 8504 8505 /* Add UDP tunneling port */ 8506 static int 8507 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 8508 struct rte_eth_udp_tunnel *udp_tunnel) 8509 { 8510 int ret = 0; 8511 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8512 8513 if (hw->mac.type != ixgbe_mac_X550 && 8514 hw->mac.type != ixgbe_mac_X550EM_x && 8515 hw->mac.type != ixgbe_mac_X550EM_a) { 8516 return -ENOTSUP; 8517 } 8518 8519 if (udp_tunnel == NULL) 8520 return -EINVAL; 8521 8522 switch (udp_tunnel->prot_type) { 8523 case RTE_TUNNEL_TYPE_VXLAN: 8524 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port); 8525 break; 8526 8527 case RTE_TUNNEL_TYPE_GENEVE: 8528 case RTE_TUNNEL_TYPE_TEREDO: 8529 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8530 ret = -EINVAL; 8531 break; 8532 8533 default: 8534 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8535 ret = -EINVAL; 8536 break; 8537 } 8538 8539 return ret; 8540 } 8541 8542 /* Remove UDP tunneling port */ 8543 static int 8544 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 8545 struct rte_eth_udp_tunnel *udp_tunnel) 8546 { 8547 int ret = 0; 8548 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8549 8550 if (hw->mac.type != ixgbe_mac_X550 && 8551 hw->mac.type != ixgbe_mac_X550EM_x && 8552 hw->mac.type != ixgbe_mac_X550EM_a) { 8553 return -ENOTSUP; 8554 } 8555 8556 if (udp_tunnel == NULL) 8557 return -EINVAL; 8558 8559 switch (udp_tunnel->prot_type) { 8560 case RTE_TUNNEL_TYPE_VXLAN: 8561 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port); 8562 break; 8563 case RTE_TUNNEL_TYPE_GENEVE: 8564 case RTE_TUNNEL_TYPE_TEREDO: 8565 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8566 ret = -EINVAL; 8567 break; 8568 default: 8569 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8570 ret = -EINVAL; 8571 break; 8572 } 8573 8574 return ret; 8575 } 8576 8577 static int 8578 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev) 8579 { 8580 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8581 int ret; 8582 8583 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) { 8584 case IXGBE_SUCCESS: 8585 ret = 0; 8586 break; 8587 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 8588 ret = -ENOTSUP; 8589 break; 8590 default: 8591 ret = -EAGAIN; 8592 break; 8593 } 8594 8595 return ret; 8596 } 8597 8598 static int 8599 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev) 8600 { 8601 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8602 int ret; 8603 8604 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) { 8605 case IXGBE_SUCCESS: 8606 ret = 0; 8607 break; 8608 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 8609 ret = -ENOTSUP; 8610 break; 8611 default: 8612 ret = -EAGAIN; 8613 break; 8614 } 8615 8616 return ret; 8617 } 8618 8619 static int 8620 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev) 8621 { 8622 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8623 int ret; 8624 int mode = IXGBEVF_XCAST_MODE_ALLMULTI; 8625 8626 switch (hw->mac.ops.update_xcast_mode(hw, mode)) { 8627 case IXGBE_SUCCESS: 8628 ret = 0; 8629 break; 8630 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 8631 ret = -ENOTSUP; 8632 break; 8633 default: 8634 ret = -EAGAIN; 8635 break; 8636 } 8637 8638 return ret; 8639 } 8640 8641 static int 8642 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev) 8643 { 8644 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8645 int ret; 8646 8647 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) { 8648 case IXGBE_SUCCESS: 8649 ret = 0; 8650 break; 8651 case IXGBE_ERR_FEATURE_NOT_SUPPORTED: 8652 ret = -ENOTSUP; 8653 break; 8654 default: 8655 ret = -EAGAIN; 8656 break; 8657 } 8658 8659 return ret; 8660 } 8661 8662 static void ixgbevf_mbx_process(struct rte_eth_dev *dev) 8663 { 8664 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8665 u32 in_msg = 0; 8666 8667 /* peek the message first */ 8668 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM); 8669 8670 /* PF reset VF event */ 8671 if (in_msg == IXGBE_PF_CONTROL_MSG) { 8672 /* dummy mbx read to ack pf */ 8673 if (ixgbe_read_mbx(hw, &in_msg, 1, 0)) 8674 return; 8675 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 8676 NULL); 8677 } 8678 } 8679 8680 static int 8681 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev) 8682 { 8683 uint32_t eicr; 8684 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8685 struct ixgbe_interrupt *intr = 8686 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8687 ixgbevf_intr_disable(dev); 8688 8689 /* read-on-clear nic registers here */ 8690 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR); 8691 intr->flags = 0; 8692 8693 /* only one misc vector supported - mailbox */ 8694 eicr &= IXGBE_VTEICR_MASK; 8695 if (eicr == IXGBE_MISC_VEC_ID) 8696 intr->flags |= IXGBE_FLAG_MAILBOX; 8697 8698 return 0; 8699 } 8700 8701 static int 8702 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev) 8703 { 8704 struct ixgbe_interrupt *intr = 8705 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8706 8707 if (intr->flags & IXGBE_FLAG_MAILBOX) { 8708 ixgbevf_mbx_process(dev); 8709 intr->flags &= ~IXGBE_FLAG_MAILBOX; 8710 } 8711 8712 ixgbevf_intr_enable(dev); 8713 8714 return 0; 8715 } 8716 8717 static void 8718 ixgbevf_dev_interrupt_handler(void *param) 8719 { 8720 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 8721 8722 ixgbevf_dev_interrupt_get_status(dev); 8723 ixgbevf_dev_interrupt_action(dev); 8724 } 8725 8726 /** 8727 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path 8728 * @hw: pointer to hardware structure 8729 * 8730 * Stops the transmit data path and waits for the HW to internally empty 8731 * the Tx security block 8732 **/ 8733 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw) 8734 { 8735 #define IXGBE_MAX_SECTX_POLL 40 8736 8737 int i; 8738 int sectxreg; 8739 8740 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8741 sectxreg |= IXGBE_SECTXCTRL_TX_DIS; 8742 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8743 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) { 8744 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT); 8745 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY) 8746 break; 8747 /* Use interrupt-safe sleep just in case */ 8748 usec_delay(1000); 8749 } 8750 8751 /* For informational purposes only */ 8752 if (i >= IXGBE_MAX_SECTX_POLL) 8753 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security " 8754 "path fully disabled. Continuing with init."); 8755 8756 return IXGBE_SUCCESS; 8757 } 8758 8759 /** 8760 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path 8761 * @hw: pointer to hardware structure 8762 * 8763 * Enables the transmit data path. 8764 **/ 8765 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw) 8766 { 8767 uint32_t sectxreg; 8768 8769 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8770 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS; 8771 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8772 IXGBE_WRITE_FLUSH(hw); 8773 8774 return IXGBE_SUCCESS; 8775 } 8776 8777 /* restore n-tuple filter */ 8778 static inline void 8779 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev) 8780 { 8781 struct ixgbe_filter_info *filter_info = 8782 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8783 struct ixgbe_5tuple_filter *node; 8784 8785 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) { 8786 ixgbe_inject_5tuple_filter(dev, node); 8787 } 8788 } 8789 8790 /* restore ethernet type filter */ 8791 static inline void 8792 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev) 8793 { 8794 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8795 struct ixgbe_filter_info *filter_info = 8796 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8797 int i; 8798 8799 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8800 if (filter_info->ethertype_mask & (1 << i)) { 8801 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 8802 filter_info->ethertype_filters[i].etqf); 8803 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 8804 filter_info->ethertype_filters[i].etqs); 8805 IXGBE_WRITE_FLUSH(hw); 8806 } 8807 } 8808 } 8809 8810 /* restore SYN filter */ 8811 static inline void 8812 ixgbe_syn_filter_restore(struct rte_eth_dev *dev) 8813 { 8814 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8815 struct ixgbe_filter_info *filter_info = 8816 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8817 uint32_t synqf; 8818 8819 synqf = filter_info->syn_info; 8820 8821 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 8822 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 8823 IXGBE_WRITE_FLUSH(hw); 8824 } 8825 } 8826 8827 /* restore L2 tunnel filter */ 8828 static inline void 8829 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev) 8830 { 8831 struct ixgbe_l2_tn_info *l2_tn_info = 8832 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8833 struct ixgbe_l2_tn_filter *node; 8834 struct rte_eth_l2_tunnel_conf l2_tn_conf; 8835 8836 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) { 8837 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type; 8838 l2_tn_conf.tunnel_id = node->key.tn_id; 8839 l2_tn_conf.pool = node->pool; 8840 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE); 8841 } 8842 } 8843 8844 /* restore rss filter */ 8845 static inline void 8846 ixgbe_rss_filter_restore(struct rte_eth_dev *dev) 8847 { 8848 struct ixgbe_filter_info *filter_info = 8849 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8850 8851 if (filter_info->rss_info.conf.queue_num) 8852 ixgbe_config_rss_filter(dev, 8853 &filter_info->rss_info, TRUE); 8854 } 8855 8856 static int 8857 ixgbe_filter_restore(struct rte_eth_dev *dev) 8858 { 8859 ixgbe_ntuple_filter_restore(dev); 8860 ixgbe_ethertype_filter_restore(dev); 8861 ixgbe_syn_filter_restore(dev); 8862 ixgbe_fdir_filter_restore(dev); 8863 ixgbe_l2_tn_filter_restore(dev); 8864 ixgbe_rss_filter_restore(dev); 8865 8866 return 0; 8867 } 8868 8869 static void 8870 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev) 8871 { 8872 struct ixgbe_l2_tn_info *l2_tn_info = 8873 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8874 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8875 8876 if (l2_tn_info->e_tag_en) 8877 (void)ixgbe_e_tag_enable(hw); 8878 8879 if (l2_tn_info->e_tag_fwd_en) 8880 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1); 8881 8882 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type); 8883 } 8884 8885 /* remove all the n-tuple filters */ 8886 void 8887 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev) 8888 { 8889 struct ixgbe_filter_info *filter_info = 8890 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8891 struct ixgbe_5tuple_filter *p_5tuple; 8892 8893 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) 8894 ixgbe_remove_5tuple_filter(dev, p_5tuple); 8895 } 8896 8897 /* remove all the ether type filters */ 8898 void 8899 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev) 8900 { 8901 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8902 struct ixgbe_filter_info *filter_info = 8903 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8904 int i; 8905 8906 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8907 if (filter_info->ethertype_mask & (1 << i) && 8908 !filter_info->ethertype_filters[i].conf) { 8909 (void)ixgbe_ethertype_filter_remove(filter_info, 8910 (uint8_t)i); 8911 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0); 8912 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0); 8913 IXGBE_WRITE_FLUSH(hw); 8914 } 8915 } 8916 } 8917 8918 /* remove the SYN filter */ 8919 void 8920 ixgbe_clear_syn_filter(struct rte_eth_dev *dev) 8921 { 8922 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8923 struct ixgbe_filter_info *filter_info = 8924 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8925 8926 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) { 8927 filter_info->syn_info = 0; 8928 8929 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0); 8930 IXGBE_WRITE_FLUSH(hw); 8931 } 8932 } 8933 8934 /* remove all the L2 tunnel filters */ 8935 int 8936 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev) 8937 { 8938 struct ixgbe_l2_tn_info *l2_tn_info = 8939 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8940 struct ixgbe_l2_tn_filter *l2_tn_filter; 8941 struct rte_eth_l2_tunnel_conf l2_tn_conf; 8942 int ret = 0; 8943 8944 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 8945 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type; 8946 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id; 8947 l2_tn_conf.pool = l2_tn_filter->pool; 8948 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf); 8949 if (ret < 0) 8950 return ret; 8951 } 8952 8953 return 0; 8954 } 8955 8956 void 8957 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev, 8958 struct ixgbe_macsec_setting *macsec_setting) 8959 { 8960 struct ixgbe_macsec_setting *macsec = 8961 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 8962 8963 macsec->offload_en = macsec_setting->offload_en; 8964 macsec->encrypt_en = macsec_setting->encrypt_en; 8965 macsec->replayprotect_en = macsec_setting->replayprotect_en; 8966 } 8967 8968 void 8969 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev) 8970 { 8971 struct ixgbe_macsec_setting *macsec = 8972 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); 8973 8974 macsec->offload_en = 0; 8975 macsec->encrypt_en = 0; 8976 macsec->replayprotect_en = 0; 8977 } 8978 8979 void 8980 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev, 8981 struct ixgbe_macsec_setting *macsec_setting) 8982 { 8983 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8984 uint32_t ctrl; 8985 uint8_t en = macsec_setting->encrypt_en; 8986 uint8_t rp = macsec_setting->replayprotect_en; 8987 8988 /** 8989 * Workaround: 8990 * As no ixgbe_disable_sec_rx_path equivalent is 8991 * implemented for tx in the base code, and we are 8992 * not allowed to modify the base code in DPDK, so 8993 * just call the hand-written one directly for now. 8994 * The hardware support has been checked by 8995 * ixgbe_disable_sec_rx_path(). 8996 */ 8997 ixgbe_disable_sec_tx_path_generic(hw); 8998 8999 /* Enable Ethernet CRC (required by MACsec offload) */ 9000 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0); 9001 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP; 9002 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl); 9003 9004 /* Enable the TX and RX crypto engines */ 9005 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 9006 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS; 9007 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl); 9008 9009 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 9010 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS; 9011 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl); 9012 9013 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 9014 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK; 9015 ctrl |= 0x3; 9016 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl); 9017 9018 /* Enable SA lookup */ 9019 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL); 9020 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK; 9021 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT : 9022 IXGBE_LSECTXCTRL_AUTH; 9023 ctrl |= IXGBE_LSECTXCTRL_AISCI; 9024 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK; 9025 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK; 9026 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl); 9027 9028 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL); 9029 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK; 9030 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT; 9031 ctrl &= ~IXGBE_LSECRXCTRL_PLSH; 9032 if (rp) 9033 ctrl |= IXGBE_LSECRXCTRL_RP; 9034 else 9035 ctrl &= ~IXGBE_LSECRXCTRL_RP; 9036 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl); 9037 9038 /* Start the data paths */ 9039 ixgbe_enable_sec_rx_path(hw); 9040 /** 9041 * Workaround: 9042 * As no ixgbe_enable_sec_rx_path equivalent is 9043 * implemented for tx in the base code, and we are 9044 * not allowed to modify the base code in DPDK, so 9045 * just call the hand-written one directly for now. 9046 */ 9047 ixgbe_enable_sec_tx_path_generic(hw); 9048 } 9049 9050 void 9051 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev) 9052 { 9053 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 9054 uint32_t ctrl; 9055 9056 /** 9057 * Workaround: 9058 * As no ixgbe_disable_sec_rx_path equivalent is 9059 * implemented for tx in the base code, and we are 9060 * not allowed to modify the base code in DPDK, so 9061 * just call the hand-written one directly for now. 9062 * The hardware support has been checked by 9063 * ixgbe_disable_sec_rx_path(). 9064 */ 9065 ixgbe_disable_sec_tx_path_generic(hw); 9066 9067 /* Disable the TX and RX crypto engines */ 9068 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 9069 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS; 9070 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl); 9071 9072 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 9073 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS; 9074 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl); 9075 9076 /* Disable SA lookup */ 9077 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL); 9078 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK; 9079 ctrl |= IXGBE_LSECTXCTRL_DISABLE; 9080 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl); 9081 9082 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL); 9083 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK; 9084 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT; 9085 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl); 9086 9087 /* Start the data paths */ 9088 ixgbe_enable_sec_rx_path(hw); 9089 /** 9090 * Workaround: 9091 * As no ixgbe_enable_sec_rx_path equivalent is 9092 * implemented for tx in the base code, and we are 9093 * not allowed to modify the base code in DPDK, so 9094 * just call the hand-written one directly for now. 9095 */ 9096 ixgbe_enable_sec_tx_path_generic(hw); 9097 } 9098 9099 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd); 9100 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map); 9101 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 9102 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd); 9103 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map); 9104 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci"); 9105 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf, 9106 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>"); 9107 9108 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE); 9109 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE); 9110 9111 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX 9112 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG); 9113 #endif 9114 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX 9115 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG); 9116 #endif 9117 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE 9118 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG); 9119 #endif 9120