1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #include "ixgbe_api.h" 6 #include "ixgbe_common.h" 7 8 #define IXGBE_EMPTY_PARAM 9 10 static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = { 11 IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM) 12 }; 13 14 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = { 15 IXGBE_MVALS_INIT(_X540) 16 }; 17 18 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 19 IXGBE_MVALS_INIT(_X550) 20 }; 21 22 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 23 IXGBE_MVALS_INIT(_X550EM_x) 24 }; 25 26 static const u32 ixgbe_mvals_X550EM_a[IXGBE_MVALS_IDX_LIMIT] = { 27 IXGBE_MVALS_INIT(_X550EM_a) 28 }; 29 30 /** 31 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg 32 * @hw: pointer to hardware structure 33 * @map: pointer to u8 arr for returning map 34 * 35 * Read the rtrup2tc HW register and resolve its content into map 36 **/ 37 void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map) 38 { 39 if (hw->mac.ops.get_rtrup2tc) 40 hw->mac.ops.get_rtrup2tc(hw, map); 41 } 42 43 /** 44 * ixgbe_init_shared_code - Initialize the shared code 45 * @hw: pointer to hardware structure 46 * 47 * This will assign function pointers and assign the MAC type and PHY code. 48 * Does not touch the hardware. This function must be called prior to any 49 * other function in the shared code. The ixgbe_hw structure should be 50 * memset to 0 prior to calling this function. The following fields in 51 * hw structure should be filled in prior to calling this function: 52 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 53 * subsystem_vendor_id, and revision_id 54 **/ 55 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 56 { 57 s32 status; 58 59 DEBUGFUNC("ixgbe_init_shared_code"); 60 61 /* 62 * Set the mac type 63 */ 64 ixgbe_set_mac_type(hw); 65 66 switch (hw->mac.type) { 67 case ixgbe_mac_82598EB: 68 status = ixgbe_init_ops_82598(hw); 69 break; 70 case ixgbe_mac_82599EB: 71 status = ixgbe_init_ops_82599(hw); 72 break; 73 case ixgbe_mac_X540: 74 status = ixgbe_init_ops_X540(hw); 75 break; 76 case ixgbe_mac_X550: 77 status = ixgbe_init_ops_X550(hw); 78 break; 79 case ixgbe_mac_X550EM_x: 80 status = ixgbe_init_ops_X550EM_x(hw); 81 break; 82 case ixgbe_mac_X550EM_a: 83 status = ixgbe_init_ops_X550EM_a(hw); 84 break; 85 case ixgbe_mac_82599_vf: 86 case ixgbe_mac_X540_vf: 87 case ixgbe_mac_X550_vf: 88 case ixgbe_mac_X550EM_x_vf: 89 case ixgbe_mac_X550EM_a_vf: 90 status = ixgbe_init_ops_vf(hw); 91 break; 92 default: 93 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 94 break; 95 } 96 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; 97 98 return status; 99 } 100 101 /** 102 * ixgbe_set_mac_type - Sets MAC type 103 * @hw: pointer to the HW structure 104 * 105 * This function sets the mac type of the adapter based on the 106 * vendor ID and device ID stored in the hw structure. 107 **/ 108 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 109 { 110 s32 ret_val = IXGBE_SUCCESS; 111 112 DEBUGFUNC("ixgbe_set_mac_type\n"); 113 114 if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { 115 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 116 "Unsupported vendor id: %x", hw->vendor_id); 117 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 118 } 119 120 hw->mvals = ixgbe_mvals_base; 121 122 switch (hw->device_id) { 123 case IXGBE_DEV_ID_82598: 124 case IXGBE_DEV_ID_82598_BX: 125 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 126 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 127 case IXGBE_DEV_ID_82598AT: 128 case IXGBE_DEV_ID_82598AT2: 129 case IXGBE_DEV_ID_82598EB_CX4: 130 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 131 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 132 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 133 case IXGBE_DEV_ID_82598EB_XF_LR: 134 case IXGBE_DEV_ID_82598EB_SFP_LOM: 135 hw->mac.type = ixgbe_mac_82598EB; 136 break; 137 case IXGBE_DEV_ID_82599_KX4: 138 case IXGBE_DEV_ID_82599_KX4_MEZZ: 139 case IXGBE_DEV_ID_82599_XAUI_LOM: 140 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 141 case IXGBE_DEV_ID_82599_KR: 142 case IXGBE_DEV_ID_82599_SFP: 143 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 144 case IXGBE_DEV_ID_82599_SFP_FCOE: 145 case IXGBE_DEV_ID_82599_SFP_EM: 146 case IXGBE_DEV_ID_82599_SFP_SF2: 147 case IXGBE_DEV_ID_82599_SFP_SF_QP: 148 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 149 case IXGBE_DEV_ID_82599EN_SFP: 150 case IXGBE_DEV_ID_82599_CX4: 151 case IXGBE_DEV_ID_82599_T3_LOM: 152 hw->mac.type = ixgbe_mac_82599EB; 153 break; 154 case IXGBE_DEV_ID_82599_VF: 155 case IXGBE_DEV_ID_82599_VF_HV: 156 hw->mac.type = ixgbe_mac_82599_vf; 157 break; 158 case IXGBE_DEV_ID_X540_VF: 159 case IXGBE_DEV_ID_X540_VF_HV: 160 hw->mac.type = ixgbe_mac_X540_vf; 161 hw->mvals = ixgbe_mvals_X540; 162 break; 163 case IXGBE_DEV_ID_X540T: 164 case IXGBE_DEV_ID_X540T1: 165 hw->mac.type = ixgbe_mac_X540; 166 hw->mvals = ixgbe_mvals_X540; 167 break; 168 case IXGBE_DEV_ID_X550T: 169 case IXGBE_DEV_ID_X550T1: 170 hw->mac.type = ixgbe_mac_X550; 171 hw->mvals = ixgbe_mvals_X550; 172 break; 173 case IXGBE_DEV_ID_X550EM_X_KX4: 174 case IXGBE_DEV_ID_X550EM_X_KR: 175 case IXGBE_DEV_ID_X550EM_X_10G_T: 176 case IXGBE_DEV_ID_X550EM_X_1G_T: 177 case IXGBE_DEV_ID_X550EM_X_SFP: 178 case IXGBE_DEV_ID_X550EM_X_XFI: 179 hw->mac.type = ixgbe_mac_X550EM_x; 180 hw->mvals = ixgbe_mvals_X550EM_x; 181 break; 182 case IXGBE_DEV_ID_X550EM_A_KR: 183 case IXGBE_DEV_ID_X550EM_A_KR_L: 184 case IXGBE_DEV_ID_X550EM_A_SFP_N: 185 case IXGBE_DEV_ID_X550EM_A_SGMII: 186 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 187 case IXGBE_DEV_ID_X550EM_A_1G_T: 188 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 189 case IXGBE_DEV_ID_X550EM_A_10G_T: 190 case IXGBE_DEV_ID_X550EM_A_QSFP: 191 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 192 case IXGBE_DEV_ID_X550EM_A_SFP: 193 hw->mac.type = ixgbe_mac_X550EM_a; 194 hw->mvals = ixgbe_mvals_X550EM_a; 195 break; 196 case IXGBE_DEV_ID_X550_VF: 197 case IXGBE_DEV_ID_X550_VF_HV: 198 hw->mac.type = ixgbe_mac_X550_vf; 199 hw->mvals = ixgbe_mvals_X550; 200 break; 201 case IXGBE_DEV_ID_X550EM_X_VF: 202 case IXGBE_DEV_ID_X550EM_X_VF_HV: 203 hw->mac.type = ixgbe_mac_X550EM_x_vf; 204 hw->mvals = ixgbe_mvals_X550EM_x; 205 break; 206 case IXGBE_DEV_ID_X550EM_A_VF: 207 case IXGBE_DEV_ID_X550EM_A_VF_HV: 208 hw->mac.type = ixgbe_mac_X550EM_a_vf; 209 hw->mvals = ixgbe_mvals_X550EM_a; 210 break; 211 default: 212 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 213 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 214 "Unsupported device id: %x", 215 hw->device_id); 216 break; 217 } 218 219 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 220 hw->mac.type, ret_val); 221 return ret_val; 222 } 223 224 /** 225 * ixgbe_init_hw - Initialize the hardware 226 * @hw: pointer to hardware structure 227 * 228 * Initialize the hardware by resetting and then starting the hardware 229 **/ 230 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 231 { 232 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 233 IXGBE_NOT_IMPLEMENTED); 234 } 235 236 /** 237 * ixgbe_reset_hw - Performs a hardware reset 238 * @hw: pointer to hardware structure 239 * 240 * Resets the hardware by resetting the transmit and receive units, masks and 241 * clears all interrupts, performs a PHY reset, and performs a MAC reset 242 **/ 243 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 244 { 245 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 246 IXGBE_NOT_IMPLEMENTED); 247 } 248 249 /** 250 * ixgbe_start_hw - Prepares hardware for Rx/Tx 251 * @hw: pointer to hardware structure 252 * 253 * Starts the hardware by filling the bus info structure and media type, 254 * clears all on chip counters, initializes receive address registers, 255 * multicast table, VLAN filter table, calls routine to setup link and 256 * flow control settings, and leaves transmit and receive units disabled 257 * and uninitialized. 258 **/ 259 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 260 { 261 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 262 IXGBE_NOT_IMPLEMENTED); 263 } 264 265 /** 266 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 267 * which is disabled by default in ixgbe_start_hw(); 268 * 269 * @hw: pointer to hardware structure 270 * 271 * Enable relaxed ordering; 272 **/ 273 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 274 { 275 if (hw->mac.ops.enable_relaxed_ordering) 276 hw->mac.ops.enable_relaxed_ordering(hw); 277 } 278 279 /** 280 * ixgbe_clear_hw_cntrs - Clear hardware counters 281 * @hw: pointer to hardware structure 282 * 283 * Clears all hardware statistics counters by reading them from the hardware 284 * Statistics counters are clear on read. 285 **/ 286 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 287 { 288 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 289 IXGBE_NOT_IMPLEMENTED); 290 } 291 292 /** 293 * ixgbe_get_media_type - Get media type 294 * @hw: pointer to hardware structure 295 * 296 * Returns the media type (fiber, copper, backplane) 297 **/ 298 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 299 { 300 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 301 ixgbe_media_type_unknown); 302 } 303 304 /** 305 * ixgbe_get_mac_addr - Get MAC address 306 * @hw: pointer to hardware structure 307 * @mac_addr: Adapter MAC address 308 * 309 * Reads the adapter's MAC address from the first Receive Address Register 310 * (RAR0) A reset of the adapter must have been performed prior to calling 311 * this function in order for the MAC address to have been loaded from the 312 * EEPROM into RAR0 313 **/ 314 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 315 { 316 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 317 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 318 } 319 320 /** 321 * ixgbe_get_san_mac_addr - Get SAN MAC address 322 * @hw: pointer to hardware structure 323 * @san_mac_addr: SAN MAC address 324 * 325 * Reads the SAN MAC address from the EEPROM, if it's available. This is 326 * per-port, so set_lan_id() must be called before reading the addresses. 327 **/ 328 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 329 { 330 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 331 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 332 } 333 334 /** 335 * ixgbe_set_san_mac_addr - Write a SAN MAC address 336 * @hw: pointer to hardware structure 337 * @san_mac_addr: SAN MAC address 338 * 339 * Writes A SAN MAC address to the EEPROM. 340 **/ 341 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 342 { 343 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 344 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 345 } 346 347 /** 348 * ixgbe_get_device_caps - Get additional device capabilities 349 * @hw: pointer to hardware structure 350 * @device_caps: the EEPROM word for device capabilities 351 * 352 * Reads the extra device capabilities from the EEPROM 353 **/ 354 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 355 { 356 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 357 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 358 } 359 360 /** 361 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 362 * @hw: pointer to hardware structure 363 * @wwnn_prefix: the alternative WWNN prefix 364 * @wwpn_prefix: the alternative WWPN prefix 365 * 366 * This function will read the EEPROM from the alternative SAN MAC address 367 * block to check the support for the alternative WWNN/WWPN prefix support. 368 **/ 369 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 370 u16 *wwpn_prefix) 371 { 372 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 373 (hw, wwnn_prefix, wwpn_prefix), 374 IXGBE_NOT_IMPLEMENTED); 375 } 376 377 /** 378 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 379 * @hw: pointer to hardware structure 380 * @bs: the fcoe boot status 381 * 382 * This function will read the FCOE boot status from the iSCSI FCOE block 383 **/ 384 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 385 { 386 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 387 (hw, bs), 388 IXGBE_NOT_IMPLEMENTED); 389 } 390 391 /** 392 * ixgbe_get_bus_info - Set PCI bus info 393 * @hw: pointer to hardware structure 394 * 395 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 396 **/ 397 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 398 { 399 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 400 IXGBE_NOT_IMPLEMENTED); 401 } 402 403 /** 404 * ixgbe_get_num_of_tx_queues - Get Tx queues 405 * @hw: pointer to hardware structure 406 * 407 * Returns the number of transmit queues for the given adapter. 408 **/ 409 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 410 { 411 return hw->mac.max_tx_queues; 412 } 413 414 /** 415 * ixgbe_get_num_of_rx_queues - Get Rx queues 416 * @hw: pointer to hardware structure 417 * 418 * Returns the number of receive queues for the given adapter. 419 **/ 420 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 421 { 422 return hw->mac.max_rx_queues; 423 } 424 425 /** 426 * ixgbe_stop_adapter - Disable Rx/Tx units 427 * @hw: pointer to hardware structure 428 * 429 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 430 * disables transmit and receive units. The adapter_stopped flag is used by 431 * the shared code and drivers to determine if the adapter is in a stopped 432 * state and should not touch the hardware. 433 **/ 434 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 435 { 436 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 437 IXGBE_NOT_IMPLEMENTED); 438 } 439 440 /** 441 * ixgbe_read_pba_string - Reads part number string from EEPROM 442 * @hw: pointer to hardware structure 443 * @pba_num: stores the part number string from the EEPROM 444 * @pba_num_size: part number string buffer length 445 * 446 * Reads the part number string from the EEPROM. 447 **/ 448 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 449 { 450 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 451 } 452 453 /** 454 * ixgbe_read_pba_num - Reads part number from EEPROM 455 * @hw: pointer to hardware structure 456 * @pba_num: stores the part number from the EEPROM 457 * 458 * Reads the part number from the EEPROM. 459 **/ 460 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 461 { 462 return ixgbe_read_pba_num_generic(hw, pba_num); 463 } 464 465 /** 466 * ixgbe_identify_phy - Get PHY type 467 * @hw: pointer to hardware structure 468 * 469 * Determines the physical layer module found on the current adapter. 470 **/ 471 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 472 { 473 s32 status = IXGBE_SUCCESS; 474 475 if (hw->phy.type == ixgbe_phy_unknown) { 476 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 477 IXGBE_NOT_IMPLEMENTED); 478 } 479 480 return status; 481 } 482 483 /** 484 * ixgbe_reset_phy - Perform a PHY reset 485 * @hw: pointer to hardware structure 486 **/ 487 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 488 { 489 s32 status = IXGBE_SUCCESS; 490 491 if (hw->phy.type == ixgbe_phy_unknown) { 492 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 493 status = IXGBE_ERR_PHY; 494 } 495 496 if (status == IXGBE_SUCCESS) { 497 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 498 IXGBE_NOT_IMPLEMENTED); 499 } 500 return status; 501 } 502 503 /** 504 * ixgbe_get_phy_firmware_version - 505 * @hw: pointer to hardware structure 506 * @firmware_version: pointer to firmware version 507 **/ 508 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 509 { 510 s32 status = IXGBE_SUCCESS; 511 512 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 513 (hw, firmware_version), 514 IXGBE_NOT_IMPLEMENTED); 515 return status; 516 } 517 518 /** 519 * ixgbe_read_phy_reg - Read PHY register 520 * @hw: pointer to hardware structure 521 * @reg_addr: 32 bit address of PHY register to read 522 * @device_type: type of device you want to communicate with 523 * @phy_data: Pointer to read data from PHY register 524 * 525 * Reads a value from a specified PHY register 526 **/ 527 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 528 u16 *phy_data) 529 { 530 if (hw->phy.id == 0) 531 ixgbe_identify_phy(hw); 532 533 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 534 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 535 } 536 537 /** 538 * ixgbe_write_phy_reg - Write PHY register 539 * @hw: pointer to hardware structure 540 * @reg_addr: 32 bit PHY register to write 541 * @device_type: type of device you want to communicate with 542 * @phy_data: Data to write to the PHY register 543 * 544 * Writes a value to specified PHY register 545 **/ 546 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 547 u16 phy_data) 548 { 549 if (hw->phy.id == 0) 550 ixgbe_identify_phy(hw); 551 552 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 553 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 554 } 555 556 /** 557 * ixgbe_setup_phy_link - Restart PHY autoneg 558 * @hw: pointer to hardware structure 559 * 560 * Restart autonegotiation and PHY and waits for completion. 561 **/ 562 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 563 { 564 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 565 IXGBE_NOT_IMPLEMENTED); 566 } 567 568 /** 569 * ixgbe_setup_internal_phy - Configure integrated PHY 570 * @hw: pointer to hardware structure 571 * 572 * Reconfigure the integrated PHY in order to enable talk to the external PHY. 573 * Returns success if not implemented, since nothing needs to be done in this 574 * case. 575 */ 576 s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw) 577 { 578 return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw), 579 IXGBE_SUCCESS); 580 } 581 582 /** 583 * ixgbe_check_phy_link - Determine link and speed status 584 * @hw: pointer to hardware structure 585 * @speed: link speed 586 * @link_up: true when link is up 587 * 588 * Reads a PHY register to determine if link is up and the current speed for 589 * the PHY. 590 **/ 591 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 592 bool *link_up) 593 { 594 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 595 link_up), IXGBE_NOT_IMPLEMENTED); 596 } 597 598 /** 599 * ixgbe_setup_phy_link_speed - Set auto advertise 600 * @hw: pointer to hardware structure 601 * @speed: new link speed 602 * @autoneg_wait_to_complete: true when waiting for completion is needed 603 * 604 * Sets the auto advertised capabilities 605 **/ 606 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 607 bool autoneg_wait_to_complete) 608 { 609 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 610 autoneg_wait_to_complete), 611 IXGBE_NOT_IMPLEMENTED); 612 } 613 614 /** 615 * ixgbe_set_phy_power - Control the phy power state 616 * @hw: pointer to hardware structure 617 * @on: true for on, false for off 618 */ 619 s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on) 620 { 621 return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on), 622 IXGBE_NOT_IMPLEMENTED); 623 } 624 625 /** 626 * ixgbe_check_link - Get link and speed status 627 * @hw: pointer to hardware structure 628 * @speed: pointer to link speed 629 * @link_up: true when link is up 630 * @link_up_wait_to_complete: bool used to wait for link up or not 631 * 632 * Reads the links register to determine if link is up and the current speed 633 **/ 634 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 635 bool *link_up, bool link_up_wait_to_complete) 636 { 637 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 638 link_up, link_up_wait_to_complete), 639 IXGBE_NOT_IMPLEMENTED); 640 } 641 642 /** 643 * ixgbe_disable_tx_laser - Disable Tx laser 644 * @hw: pointer to hardware structure 645 * 646 * If the driver needs to disable the laser on SFI optics. 647 **/ 648 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 649 { 650 if (hw->mac.ops.disable_tx_laser) 651 hw->mac.ops.disable_tx_laser(hw); 652 } 653 654 /** 655 * ixgbe_enable_tx_laser - Enable Tx laser 656 * @hw: pointer to hardware structure 657 * 658 * If the driver needs to enable the laser on SFI optics. 659 **/ 660 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 661 { 662 if (hw->mac.ops.enable_tx_laser) 663 hw->mac.ops.enable_tx_laser(hw); 664 } 665 666 /** 667 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 668 * @hw: pointer to hardware structure 669 * 670 * When the driver changes the link speeds that it can support then 671 * flap the tx laser to alert the link partner to start autotry 672 * process on its end. 673 **/ 674 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 675 { 676 if (hw->mac.ops.flap_tx_laser) 677 hw->mac.ops.flap_tx_laser(hw); 678 } 679 680 /** 681 * ixgbe_setup_link - Set link speed 682 * @hw: pointer to hardware structure 683 * @speed: new link speed 684 * @autoneg_wait_to_complete: true when waiting for completion is needed 685 * 686 * Configures link settings. Restarts the link. 687 * Performs autonegotiation if needed. 688 **/ 689 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 690 bool autoneg_wait_to_complete) 691 { 692 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 693 autoneg_wait_to_complete), 694 IXGBE_NOT_IMPLEMENTED); 695 } 696 697 /** 698 * ixgbe_setup_mac_link - Set link speed 699 * @hw: pointer to hardware structure 700 * @speed: new link speed 701 * @autoneg_wait_to_complete: true when waiting for completion is needed 702 * 703 * Configures link settings. Restarts the link. 704 * Performs autonegotiation if needed. 705 **/ 706 s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 707 bool autoneg_wait_to_complete) 708 { 709 return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed, 710 autoneg_wait_to_complete), 711 IXGBE_NOT_IMPLEMENTED); 712 } 713 714 /** 715 * ixgbe_get_link_capabilities - Returns link capabilities 716 * @hw: pointer to hardware structure 717 * @speed: link speed capabilities 718 * @autoneg: true when autoneg or autotry is enabled 719 * 720 * Determines the link capabilities of the current configuration. 721 **/ 722 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 723 bool *autoneg) 724 { 725 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 726 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 727 } 728 729 /** 730 * ixgbe_led_on - Turn on LEDs 731 * @hw: pointer to hardware structure 732 * @index: led number to turn on 733 * 734 * Turns on the software controllable LEDs. 735 **/ 736 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 737 { 738 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 739 IXGBE_NOT_IMPLEMENTED); 740 } 741 742 /** 743 * ixgbe_led_off - Turn off LEDs 744 * @hw: pointer to hardware structure 745 * @index: led number to turn off 746 * 747 * Turns off the software controllable LEDs. 748 **/ 749 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 750 { 751 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 752 IXGBE_NOT_IMPLEMENTED); 753 } 754 755 /** 756 * ixgbe_blink_led_start - Blink LEDs 757 * @hw: pointer to hardware structure 758 * @index: led number to blink 759 * 760 * Blink LED based on index. 761 **/ 762 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 763 { 764 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 765 IXGBE_NOT_IMPLEMENTED); 766 } 767 768 /** 769 * ixgbe_blink_led_stop - Stop blinking LEDs 770 * @hw: pointer to hardware structure 771 * @index: led number to stop 772 * 773 * Stop blinking LED based on index. 774 **/ 775 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 776 { 777 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 778 IXGBE_NOT_IMPLEMENTED); 779 } 780 781 /** 782 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 783 * @hw: pointer to hardware structure 784 * 785 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 786 * ixgbe_hw struct in order to set up EEPROM access. 787 **/ 788 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 789 { 790 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 791 IXGBE_NOT_IMPLEMENTED); 792 } 793 794 795 /** 796 * ixgbe_write_eeprom - Write word to EEPROM 797 * @hw: pointer to hardware structure 798 * @offset: offset within the EEPROM to be written to 799 * @data: 16 bit word to be written to the EEPROM 800 * 801 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 802 * called after this function, the EEPROM will most likely contain an 803 * invalid checksum. 804 **/ 805 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 806 { 807 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 808 IXGBE_NOT_IMPLEMENTED); 809 } 810 811 /** 812 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 813 * @hw: pointer to hardware structure 814 * @offset: offset within the EEPROM to be written to 815 * @data: 16 bit word(s) to be written to the EEPROM 816 * @words: number of words 817 * 818 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 819 * called after this function, the EEPROM will most likely contain an 820 * invalid checksum. 821 **/ 822 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 823 u16 *data) 824 { 825 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 826 (hw, offset, words, data), 827 IXGBE_NOT_IMPLEMENTED); 828 } 829 830 /** 831 * ixgbe_read_eeprom - Read word from EEPROM 832 * @hw: pointer to hardware structure 833 * @offset: offset within the EEPROM to be read 834 * @data: read 16 bit value from EEPROM 835 * 836 * Reads 16 bit value from EEPROM 837 **/ 838 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 839 { 840 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 841 IXGBE_NOT_IMPLEMENTED); 842 } 843 844 /** 845 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 846 * @hw: pointer to hardware structure 847 * @offset: offset within the EEPROM to be read 848 * @data: read 16 bit word(s) from EEPROM 849 * @words: number of words 850 * 851 * Reads 16 bit word(s) from EEPROM 852 **/ 853 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 854 u16 words, u16 *data) 855 { 856 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 857 (hw, offset, words, data), 858 IXGBE_NOT_IMPLEMENTED); 859 } 860 861 /** 862 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 863 * @hw: pointer to hardware structure 864 * @checksum_val: calculated checksum 865 * 866 * Performs checksum calculation and validates the EEPROM checksum 867 **/ 868 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 869 { 870 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 871 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 872 } 873 874 /** 875 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 876 * @hw: pointer to hardware structure 877 **/ 878 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 879 { 880 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 881 IXGBE_NOT_IMPLEMENTED); 882 } 883 884 /** 885 * ixgbe_insert_mac_addr - Find a RAR for this mac address 886 * @hw: pointer to hardware structure 887 * @addr: Address to put into receive address register 888 * @vmdq: VMDq pool to assign 889 * 890 * Puts an ethernet address into a receive address register, or 891 * finds the rar that it is aleady in; adds to the pool list 892 **/ 893 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 894 { 895 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 896 (hw, addr, vmdq), 897 IXGBE_NOT_IMPLEMENTED); 898 } 899 900 /** 901 * ixgbe_set_rar - Set Rx address register 902 * @hw: pointer to hardware structure 903 * @index: Receive address register to write 904 * @addr: Address to put into receive address register 905 * @vmdq: VMDq "set" 906 * @enable_addr: set flag that address is active 907 * 908 * Puts an ethernet address into a receive address register. 909 **/ 910 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 911 u32 enable_addr) 912 { 913 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 914 enable_addr), IXGBE_NOT_IMPLEMENTED); 915 } 916 917 /** 918 * ixgbe_clear_rar - Clear Rx address register 919 * @hw: pointer to hardware structure 920 * @index: Receive address register to write 921 * 922 * Puts an ethernet address into a receive address register. 923 **/ 924 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 925 { 926 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 927 IXGBE_NOT_IMPLEMENTED); 928 } 929 930 /** 931 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 932 * @hw: pointer to hardware structure 933 * @rar: receive address register index to associate with VMDq index 934 * @vmdq: VMDq set or pool index 935 **/ 936 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 937 { 938 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 939 IXGBE_NOT_IMPLEMENTED); 940 941 } 942 943 /** 944 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address 945 * @hw: pointer to hardware structure 946 * @vmdq: VMDq default pool index 947 **/ 948 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) 949 { 950 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac, 951 (hw, vmdq), IXGBE_NOT_IMPLEMENTED); 952 } 953 954 /** 955 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 956 * @hw: pointer to hardware structure 957 * @rar: receive address register index to disassociate with VMDq index 958 * @vmdq: VMDq set or pool index 959 **/ 960 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 961 { 962 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 963 IXGBE_NOT_IMPLEMENTED); 964 } 965 966 /** 967 * ixgbe_init_rx_addrs - Initializes receive address filters. 968 * @hw: pointer to hardware structure 969 * 970 * Places the MAC address in receive address register 0 and clears the rest 971 * of the receive address registers. Clears the multicast table. Assumes 972 * the receiver is in reset when the routine is called. 973 **/ 974 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 975 { 976 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 977 IXGBE_NOT_IMPLEMENTED); 978 } 979 980 /** 981 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 982 * @hw: pointer to hardware structure 983 **/ 984 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 985 { 986 return hw->mac.num_rar_entries; 987 } 988 989 /** 990 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 991 * @hw: pointer to hardware structure 992 * @addr_list: the list of new multicast addresses 993 * @addr_count: number of addresses 994 * @func: iterator function to walk the multicast address list 995 * 996 * The given list replaces any existing list. Clears the secondary addrs from 997 * receive address registers. Uses unused receive address registers for the 998 * first secondary addresses, and falls back to promiscuous mode as needed. 999 **/ 1000 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 1001 u32 addr_count, ixgbe_mc_addr_itr func) 1002 { 1003 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 1004 addr_list, addr_count, func), 1005 IXGBE_NOT_IMPLEMENTED); 1006 } 1007 1008 /** 1009 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 1010 * @hw: pointer to hardware structure 1011 * @mc_addr_list: the list of new multicast addresses 1012 * @mc_addr_count: number of addresses 1013 * @func: iterator function to walk the multicast address list 1014 * @clear: flag, when set clears the table beforehand 1015 * 1016 * The given list replaces any existing list. Clears the MC addrs from receive 1017 * address registers and the multicast table. Uses unused receive address 1018 * registers for the first multicast addresses, and hashes the rest into the 1019 * multicast table. 1020 **/ 1021 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 1022 u32 mc_addr_count, ixgbe_mc_addr_itr func, 1023 bool clear) 1024 { 1025 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 1026 mc_addr_list, mc_addr_count, func, clear), 1027 IXGBE_NOT_IMPLEMENTED); 1028 } 1029 1030 /** 1031 * ixgbe_enable_mc - Enable multicast address in RAR 1032 * @hw: pointer to hardware structure 1033 * 1034 * Enables multicast address in RAR and the use of the multicast hash table. 1035 **/ 1036 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 1037 { 1038 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 1039 IXGBE_NOT_IMPLEMENTED); 1040 } 1041 1042 /** 1043 * ixgbe_disable_mc - Disable multicast address in RAR 1044 * @hw: pointer to hardware structure 1045 * 1046 * Disables multicast address in RAR and the use of the multicast hash table. 1047 **/ 1048 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 1049 { 1050 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 1051 IXGBE_NOT_IMPLEMENTED); 1052 } 1053 1054 /** 1055 * ixgbe_clear_vfta - Clear VLAN filter table 1056 * @hw: pointer to hardware structure 1057 * 1058 * Clears the VLAN filer table, and the VMDq index associated with the filter 1059 **/ 1060 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 1061 { 1062 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 1063 IXGBE_NOT_IMPLEMENTED); 1064 } 1065 1066 /** 1067 * ixgbe_set_vfta - Set VLAN filter table 1068 * @hw: pointer to hardware structure 1069 * @vlan: VLAN id to write to VLAN filter 1070 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1071 * @vlan_on: boolean flag to turn on/off VLAN 1072 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1073 * 1074 * Turn on/off specified VLAN in the VLAN filter table. 1075 **/ 1076 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1077 bool vlvf_bypass) 1078 { 1079 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 1080 vlan_on, vlvf_bypass), IXGBE_NOT_IMPLEMENTED); 1081 } 1082 1083 /** 1084 * ixgbe_set_vlvf - Set VLAN Pool Filter 1085 * @hw: pointer to hardware structure 1086 * @vlan: VLAN id to write to VLAN filter 1087 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1088 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 1089 * @vfta_delta: pointer to the difference between the current value of VFTA 1090 * and the desired value 1091 * @vfta: the desired value of the VFTA 1092 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1093 * 1094 * Turn on/off specified bit in VLVF table. 1095 **/ 1096 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1097 u32 *vfta_delta, u32 vfta, bool vlvf_bypass) 1098 { 1099 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 1100 vlan_on, vfta_delta, vfta, vlvf_bypass), 1101 IXGBE_NOT_IMPLEMENTED); 1102 } 1103 1104 /** 1105 * ixgbe_fc_enable - Enable flow control 1106 * @hw: pointer to hardware structure 1107 * 1108 * Configures the flow control settings based on SW configuration. 1109 **/ 1110 s32 ixgbe_fc_enable(struct ixgbe_hw *hw) 1111 { 1112 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), 1113 IXGBE_NOT_IMPLEMENTED); 1114 } 1115 1116 /** 1117 * ixgbe_setup_fc - Set up flow control 1118 * @hw: pointer to hardware structure 1119 * 1120 * Called at init time to set up flow control. 1121 **/ 1122 s32 ixgbe_setup_fc(struct ixgbe_hw *hw) 1123 { 1124 return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw), 1125 IXGBE_NOT_IMPLEMENTED); 1126 } 1127 1128 /** 1129 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 1130 * @hw: pointer to hardware structure 1131 * @maj: driver major number to be sent to firmware 1132 * @min: driver minor number to be sent to firmware 1133 * @build: driver build number to be sent to firmware 1134 * @ver: driver version number to be sent to firmware 1135 * @len: length of driver_ver string 1136 * @driver_ver: driver string 1137 **/ 1138 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, 1139 u8 ver, u16 len, char *driver_ver) 1140 { 1141 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min, 1142 build, ver, len, driver_ver), 1143 IXGBE_NOT_IMPLEMENTED); 1144 } 1145 1146 1147 /** 1148 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data 1149 * @hw: pointer to hardware structure 1150 * 1151 * Updates the temperatures in mac.thermal_sensor_data 1152 **/ 1153 s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw) 1154 { 1155 return ixgbe_call_func(hw, hw->mac.ops.get_thermal_sensor_data, (hw), 1156 IXGBE_NOT_IMPLEMENTED); 1157 } 1158 1159 /** 1160 * ixgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds 1161 * @hw: pointer to hardware structure 1162 * 1163 * Inits the thermal sensor thresholds according to the NVM map 1164 **/ 1165 s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw) 1166 { 1167 return ixgbe_call_func(hw, hw->mac.ops.init_thermal_sensor_thresh, (hw), 1168 IXGBE_NOT_IMPLEMENTED); 1169 } 1170 1171 /** 1172 * ixgbe_dmac_config - Configure DMA Coalescing registers. 1173 * @hw: pointer to hardware structure 1174 * 1175 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1176 * When disabling dmac, dmac enable dmac bit is cleared. 1177 **/ 1178 s32 ixgbe_dmac_config(struct ixgbe_hw *hw) 1179 { 1180 return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw), 1181 IXGBE_NOT_IMPLEMENTED); 1182 } 1183 1184 /** 1185 * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers. 1186 * @hw: pointer to hardware structure 1187 * 1188 * Disables dmac, updates per TC settings, and then enable dmac. 1189 **/ 1190 s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw) 1191 { 1192 return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw), 1193 IXGBE_NOT_IMPLEMENTED); 1194 } 1195 1196 /** 1197 * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers. 1198 * @hw: pointer to hardware structure 1199 * 1200 * Configure DMA coalescing threshold per TC and set high priority bit for 1201 * FCOE TC. The dmac enable bit must be cleared before configuring. 1202 **/ 1203 s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw) 1204 { 1205 return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw), 1206 IXGBE_NOT_IMPLEMENTED); 1207 } 1208 1209 /** 1210 * ixgbe_setup_eee - Enable/disable EEE support 1211 * @hw: pointer to the HW structure 1212 * @enable_eee: boolean flag to enable EEE 1213 * 1214 * Enable/disable EEE based on enable_ee flag. 1215 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 1216 * are modified. 1217 * 1218 **/ 1219 s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee) 1220 { 1221 return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee), 1222 IXGBE_NOT_IMPLEMENTED); 1223 } 1224 1225 /** 1226 * ixgbe_set_source_address_pruning - Enable/Disable source address pruning 1227 * @hw: pointer to hardware structure 1228 * @enable: enable or disable source address pruning 1229 * @pool: Rx pool - Rx pool to toggle source address pruning 1230 **/ 1231 void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, 1232 unsigned int pool) 1233 { 1234 if (hw->mac.ops.set_source_address_pruning) 1235 hw->mac.ops.set_source_address_pruning(hw, enable, pool); 1236 } 1237 1238 /** 1239 * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing 1240 * @hw: pointer to hardware structure 1241 * @enable: enable or disable switch for Ethertype anti-spoofing 1242 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1243 * 1244 **/ 1245 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 1246 { 1247 if (hw->mac.ops.set_ethertype_anti_spoofing) 1248 hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf); 1249 } 1250 1251 /** 1252 * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register 1253 * @hw: pointer to hardware structure 1254 * @reg_addr: 32 bit address of PHY register to read 1255 * @device_type: type of device you want to communicate with 1256 * @phy_data: Pointer to read data from PHY register 1257 * 1258 * Reads a value from a specified PHY register 1259 **/ 1260 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1261 u32 device_type, u32 *phy_data) 1262 { 1263 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, 1264 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1265 } 1266 1267 /** 1268 * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband 1269 * @hw: pointer to hardware structure 1270 * @reg_addr: 32 bit PHY register to write 1271 * @device_type: type of device you want to communicate with 1272 * @phy_data: Data to write to the PHY register 1273 * 1274 * Writes a value to specified PHY register 1275 **/ 1276 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1277 u32 device_type, u32 phy_data) 1278 { 1279 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, 1280 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1281 } 1282 1283 /** 1284 * ixgbe_disable_mdd - Disable malicious driver detection 1285 * @hw: pointer to hardware structure 1286 * 1287 **/ 1288 void ixgbe_disable_mdd(struct ixgbe_hw *hw) 1289 { 1290 if (hw->mac.ops.disable_mdd) 1291 hw->mac.ops.disable_mdd(hw); 1292 } 1293 1294 /** 1295 * ixgbe_enable_mdd - Enable malicious driver detection 1296 * @hw: pointer to hardware structure 1297 * 1298 **/ 1299 void ixgbe_enable_mdd(struct ixgbe_hw *hw) 1300 { 1301 if (hw->mac.ops.enable_mdd) 1302 hw->mac.ops.enable_mdd(hw); 1303 } 1304 1305 /** 1306 * ixgbe_mdd_event - Handle malicious driver detection event 1307 * @hw: pointer to hardware structure 1308 * @vf_bitmap: vf bitmap of malicious vfs 1309 * 1310 **/ 1311 void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap) 1312 { 1313 if (hw->mac.ops.mdd_event) 1314 hw->mac.ops.mdd_event(hw, vf_bitmap); 1315 } 1316 1317 /** 1318 * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver 1319 * detection event 1320 * @hw: pointer to hardware structure 1321 * @vf: vf index 1322 * 1323 **/ 1324 void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf) 1325 { 1326 if (hw->mac.ops.restore_mdd_vf) 1327 hw->mac.ops.restore_mdd_vf(hw, vf); 1328 } 1329 1330 /** 1331 * ixgbe_fw_recovery_mode - Check if in FW NVM recovery mode 1332 * @hw: pointer to hardware structure 1333 * 1334 **/ 1335 bool ixgbe_fw_recovery_mode(struct ixgbe_hw *hw) 1336 { 1337 if (hw->mac.ops.fw_recovery_mode) 1338 return hw->mac.ops.fw_recovery_mode(hw); 1339 return false; 1340 } 1341 1342 /** 1343 * ixgbe_enter_lplu - Transition to low power states 1344 * @hw: pointer to hardware structure 1345 * 1346 * Configures Low Power Link Up on transition to low power states 1347 * (from D0 to non-D0). 1348 **/ 1349 s32 ixgbe_enter_lplu(struct ixgbe_hw *hw) 1350 { 1351 return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw), 1352 IXGBE_NOT_IMPLEMENTED); 1353 } 1354 1355 /** 1356 * ixgbe_handle_lasi - Handle external Base T PHY interrupt 1357 * @hw: pointer to hardware structure 1358 * 1359 * Handle external Base T PHY interrupt. If high temperature 1360 * failure alarm then return error, else if link status change 1361 * then setup internal/external PHY link 1362 * 1363 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1364 * failure alarm, else return PHY access status. 1365 */ 1366 s32 ixgbe_handle_lasi(struct ixgbe_hw *hw) 1367 { 1368 return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw), 1369 IXGBE_NOT_IMPLEMENTED); 1370 } 1371 1372 /** 1373 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 1374 * @hw: pointer to hardware structure 1375 * @reg: analog register to read 1376 * @val: read value 1377 * 1378 * Performs write operation to analog register specified. 1379 **/ 1380 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 1381 { 1382 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1383 val), IXGBE_NOT_IMPLEMENTED); 1384 } 1385 1386 /** 1387 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1388 * @hw: pointer to hardware structure 1389 * @reg: analog register to write 1390 * @val: value to write 1391 * 1392 * Performs write operation to Atlas analog register specified. 1393 **/ 1394 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1395 { 1396 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1397 val), IXGBE_NOT_IMPLEMENTED); 1398 } 1399 1400 /** 1401 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1402 * @hw: pointer to hardware structure 1403 * 1404 * Initializes the Unicast Table Arrays to zero on device load. This 1405 * is part of the Rx init addr execution path. 1406 **/ 1407 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1408 { 1409 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1410 IXGBE_NOT_IMPLEMENTED); 1411 } 1412 1413 /** 1414 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1415 * @hw: pointer to hardware structure 1416 * @byte_offset: byte offset to read 1417 * @dev_addr: I2C bus address to read from 1418 * @data: value read 1419 * 1420 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1421 **/ 1422 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1423 u8 *data) 1424 { 1425 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1426 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1427 } 1428 1429 /** 1430 * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address 1431 * @hw: pointer to hardware structure 1432 * @byte_offset: byte offset to read 1433 * @dev_addr: I2C bus address to read from 1434 * @data: value read 1435 * 1436 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1437 **/ 1438 s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1439 u8 dev_addr, u8 *data) 1440 { 1441 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked, 1442 (hw, byte_offset, dev_addr, data), 1443 IXGBE_NOT_IMPLEMENTED); 1444 } 1445 1446 /** 1447 * ixgbe_read_link - Perform read operation on link device 1448 * @hw: pointer to the hardware structure 1449 * @addr: bus address to read from 1450 * @reg: device register to read from 1451 * @val: pointer to location to receive read value 1452 * 1453 * Returns an error code on error. 1454 */ 1455 s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1456 { 1457 return ixgbe_call_func(hw, hw->link.ops.read_link, (hw, addr, 1458 reg, val), IXGBE_NOT_IMPLEMENTED); 1459 } 1460 1461 /** 1462 * ixgbe_read_link_unlocked - Perform read operation on link device 1463 * @hw: pointer to the hardware structure 1464 * @addr: bus address to read from 1465 * @reg: device register to read from 1466 * @val: pointer to location to receive read value 1467 * 1468 * Returns an error code on error. 1469 **/ 1470 s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1471 { 1472 return ixgbe_call_func(hw, hw->link.ops.read_link_unlocked, 1473 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1474 } 1475 1476 /** 1477 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1478 * @hw: pointer to hardware structure 1479 * @byte_offset: byte offset to write 1480 * @dev_addr: I2C bus address to write to 1481 * @data: value to write 1482 * 1483 * Performs byte write operation to SFP module's EEPROM over I2C interface 1484 * at a specified device address. 1485 **/ 1486 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1487 u8 data) 1488 { 1489 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1490 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1491 } 1492 1493 /** 1494 * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1495 * @hw: pointer to hardware structure 1496 * @byte_offset: byte offset to write 1497 * @dev_addr: I2C bus address to write to 1498 * @data: value to write 1499 * 1500 * Performs byte write operation to SFP module's EEPROM over I2C interface 1501 * at a specified device address. 1502 **/ 1503 s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1504 u8 dev_addr, u8 data) 1505 { 1506 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked, 1507 (hw, byte_offset, dev_addr, data), 1508 IXGBE_NOT_IMPLEMENTED); 1509 } 1510 1511 /** 1512 * ixgbe_write_link - Perform write operation on link device 1513 * @hw: pointer to the hardware structure 1514 * @addr: bus address to write to 1515 * @reg: device register to write to 1516 * @val: value to write 1517 * 1518 * Returns an error code on error. 1519 */ 1520 s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1521 { 1522 return ixgbe_call_func(hw, hw->link.ops.write_link, 1523 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1524 } 1525 1526 /** 1527 * ixgbe_write_link_unlocked - Perform write operation on link device 1528 * @hw: pointer to the hardware structure 1529 * @addr: bus address to write to 1530 * @reg: device register to write to 1531 * @val: value to write 1532 * 1533 * Returns an error code on error. 1534 **/ 1535 s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1536 { 1537 return ixgbe_call_func(hw, hw->link.ops.write_link_unlocked, 1538 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1539 } 1540 1541 /** 1542 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1543 * @hw: pointer to hardware structure 1544 * @byte_offset: EEPROM byte offset to write 1545 * @eeprom_data: value to write 1546 * 1547 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1548 **/ 1549 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1550 u8 byte_offset, u8 eeprom_data) 1551 { 1552 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1553 (hw, byte_offset, eeprom_data), 1554 IXGBE_NOT_IMPLEMENTED); 1555 } 1556 1557 /** 1558 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1559 * @hw: pointer to hardware structure 1560 * @byte_offset: EEPROM byte offset to read 1561 * @eeprom_data: value read 1562 * 1563 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1564 **/ 1565 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1566 { 1567 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1568 (hw, byte_offset, eeprom_data), 1569 IXGBE_NOT_IMPLEMENTED); 1570 } 1571 1572 /** 1573 * ixgbe_get_supported_physical_layer - Returns physical layer type 1574 * @hw: pointer to hardware structure 1575 * 1576 * Determines physical layer capabilities of the current configuration. 1577 **/ 1578 u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1579 { 1580 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1581 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1582 } 1583 1584 /** 1585 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics 1586 * @hw: pointer to hardware structure 1587 * @regval: bitfield to write to the Rx DMA register 1588 * 1589 * Enables the Rx DMA unit of the device. 1590 **/ 1591 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1592 { 1593 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1594 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1595 } 1596 1597 /** 1598 * ixgbe_disable_sec_rx_path - Stops the receive data path 1599 * @hw: pointer to hardware structure 1600 * 1601 * Stops the receive data path. 1602 **/ 1603 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1604 { 1605 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1606 (hw), IXGBE_NOT_IMPLEMENTED); 1607 } 1608 1609 /** 1610 * ixgbe_enable_sec_rx_path - Enables the receive data path 1611 * @hw: pointer to hardware structure 1612 * 1613 * Enables the receive data path. 1614 **/ 1615 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1616 { 1617 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1618 (hw), IXGBE_NOT_IMPLEMENTED); 1619 } 1620 1621 /** 1622 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1623 * @hw: pointer to hardware structure 1624 * @mask: Mask to specify which semaphore to acquire 1625 * 1626 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1627 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1628 **/ 1629 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1630 { 1631 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1632 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1633 } 1634 1635 /** 1636 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1637 * @hw: pointer to hardware structure 1638 * @mask: Mask to specify which semaphore to release 1639 * 1640 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1641 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1642 **/ 1643 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1644 { 1645 if (hw->mac.ops.release_swfw_sync) 1646 hw->mac.ops.release_swfw_sync(hw, mask); 1647 } 1648 1649 /** 1650 * ixgbe_init_swfw_semaphore - Clean up SWFW semaphore 1651 * @hw: pointer to hardware structure 1652 * 1653 * Attempts to acquire the SWFW semaphore through SW_FW_SYNC register. 1654 * Regardless of whether is succeeds or not it then release the semaphore. 1655 * This is function is called to recover from catastrophic failures that 1656 * may have left the semaphore locked. 1657 **/ 1658 void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw) 1659 { 1660 if (hw->mac.ops.init_swfw_sync) 1661 hw->mac.ops.init_swfw_sync(hw); 1662 } 1663 1664 1665 void ixgbe_disable_rx(struct ixgbe_hw *hw) 1666 { 1667 if (hw->mac.ops.disable_rx) 1668 hw->mac.ops.disable_rx(hw); 1669 } 1670 1671 void ixgbe_enable_rx(struct ixgbe_hw *hw) 1672 { 1673 if (hw->mac.ops.enable_rx) 1674 hw->mac.ops.enable_rx(hw); 1675 } 1676 1677 /** 1678 * ixgbe_set_rate_select_speed - Set module link speed 1679 * @hw: pointer to hardware structure 1680 * @speed: link speed to set 1681 * 1682 * Set module link speed via the rate select. 1683 */ 1684 void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 1685 { 1686 if (hw->mac.ops.set_rate_select_speed) 1687 hw->mac.ops.set_rate_select_speed(hw, speed); 1688 } 1689