1 /******************************************************************************* 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 #include "ixgbe_api.h" 35 #include "ixgbe_common.h" 36 37 #define IXGBE_EMPTY_PARAM 38 39 static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = { 40 IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM) 41 }; 42 43 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = { 44 IXGBE_MVALS_INIT(_X540) 45 }; 46 47 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 48 IXGBE_MVALS_INIT(_X550) 49 }; 50 51 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 52 IXGBE_MVALS_INIT(_X550EM_x) 53 }; 54 55 static const u32 ixgbe_mvals_X550EM_a[IXGBE_MVALS_IDX_LIMIT] = { 56 IXGBE_MVALS_INIT(_X550EM_a) 57 }; 58 59 /** 60 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg 61 * @hw: pointer to hardware structure 62 * @map: pointer to u8 arr for returning map 63 * 64 * Read the rtrup2tc HW register and resolve its content into map 65 **/ 66 void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map) 67 { 68 if (hw->mac.ops.get_rtrup2tc) 69 hw->mac.ops.get_rtrup2tc(hw, map); 70 } 71 72 /** 73 * ixgbe_init_shared_code - Initialize the shared code 74 * @hw: pointer to hardware structure 75 * 76 * This will assign function pointers and assign the MAC type and PHY code. 77 * Does not touch the hardware. This function must be called prior to any 78 * other function in the shared code. The ixgbe_hw structure should be 79 * memset to 0 prior to calling this function. The following fields in 80 * hw structure should be filled in prior to calling this function: 81 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 82 * subsystem_vendor_id, and revision_id 83 **/ 84 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 85 { 86 s32 status; 87 88 DEBUGFUNC("ixgbe_init_shared_code"); 89 90 /* 91 * Set the mac type 92 */ 93 ixgbe_set_mac_type(hw); 94 95 switch (hw->mac.type) { 96 case ixgbe_mac_82598EB: 97 status = ixgbe_init_ops_82598(hw); 98 break; 99 case ixgbe_mac_82599EB: 100 status = ixgbe_init_ops_82599(hw); 101 break; 102 case ixgbe_mac_X540: 103 status = ixgbe_init_ops_X540(hw); 104 break; 105 case ixgbe_mac_X550: 106 status = ixgbe_init_ops_X550(hw); 107 break; 108 case ixgbe_mac_X550EM_x: 109 status = ixgbe_init_ops_X550EM_x(hw); 110 break; 111 case ixgbe_mac_X550EM_a: 112 status = ixgbe_init_ops_X550EM_a(hw); 113 break; 114 case ixgbe_mac_82599_vf: 115 case ixgbe_mac_X540_vf: 116 case ixgbe_mac_X550_vf: 117 case ixgbe_mac_X550EM_x_vf: 118 case ixgbe_mac_X550EM_a_vf: 119 status = ixgbe_init_ops_vf(hw); 120 break; 121 default: 122 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 123 break; 124 } 125 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; 126 127 return status; 128 } 129 130 /** 131 * ixgbe_set_mac_type - Sets MAC type 132 * @hw: pointer to the HW structure 133 * 134 * This function sets the mac type of the adapter based on the 135 * vendor ID and device ID stored in the hw structure. 136 **/ 137 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 138 { 139 s32 ret_val = IXGBE_SUCCESS; 140 141 DEBUGFUNC("ixgbe_set_mac_type\n"); 142 143 if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { 144 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 145 "Unsupported vendor id: %x", hw->vendor_id); 146 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 147 } 148 149 hw->mvals = ixgbe_mvals_base; 150 151 switch (hw->device_id) { 152 case IXGBE_DEV_ID_82598: 153 case IXGBE_DEV_ID_82598_BX: 154 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 155 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 156 case IXGBE_DEV_ID_82598AT: 157 case IXGBE_DEV_ID_82598AT2: 158 case IXGBE_DEV_ID_82598EB_CX4: 159 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 160 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 161 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 162 case IXGBE_DEV_ID_82598EB_XF_LR: 163 case IXGBE_DEV_ID_82598EB_SFP_LOM: 164 hw->mac.type = ixgbe_mac_82598EB; 165 break; 166 case IXGBE_DEV_ID_82599_KX4: 167 case IXGBE_DEV_ID_82599_KX4_MEZZ: 168 case IXGBE_DEV_ID_82599_XAUI_LOM: 169 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 170 case IXGBE_DEV_ID_82599_KR: 171 case IXGBE_DEV_ID_82599_SFP: 172 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 173 case IXGBE_DEV_ID_82599_SFP_FCOE: 174 case IXGBE_DEV_ID_82599_SFP_EM: 175 case IXGBE_DEV_ID_82599_SFP_SF2: 176 case IXGBE_DEV_ID_82599_SFP_SF_QP: 177 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 178 case IXGBE_DEV_ID_82599EN_SFP: 179 case IXGBE_DEV_ID_82599_CX4: 180 case IXGBE_DEV_ID_82599_LS: 181 case IXGBE_DEV_ID_82599_T3_LOM: 182 hw->mac.type = ixgbe_mac_82599EB; 183 break; 184 case IXGBE_DEV_ID_82599_VF: 185 case IXGBE_DEV_ID_82599_VF_HV: 186 hw->mac.type = ixgbe_mac_82599_vf; 187 break; 188 case IXGBE_DEV_ID_X540_VF: 189 case IXGBE_DEV_ID_X540_VF_HV: 190 hw->mac.type = ixgbe_mac_X540_vf; 191 hw->mvals = ixgbe_mvals_X540; 192 break; 193 case IXGBE_DEV_ID_X540T: 194 case IXGBE_DEV_ID_X540T1: 195 hw->mac.type = ixgbe_mac_X540; 196 hw->mvals = ixgbe_mvals_X540; 197 break; 198 case IXGBE_DEV_ID_X550T: 199 case IXGBE_DEV_ID_X550T1: 200 hw->mac.type = ixgbe_mac_X550; 201 hw->mvals = ixgbe_mvals_X550; 202 break; 203 case IXGBE_DEV_ID_X550EM_X_KX4: 204 case IXGBE_DEV_ID_X550EM_X_KR: 205 case IXGBE_DEV_ID_X550EM_X_10G_T: 206 case IXGBE_DEV_ID_X550EM_X_1G_T: 207 case IXGBE_DEV_ID_X550EM_X_SFP: 208 hw->mac.type = ixgbe_mac_X550EM_x; 209 hw->mvals = ixgbe_mvals_X550EM_x; 210 break; 211 case IXGBE_DEV_ID_X550EM_A_KR: 212 case IXGBE_DEV_ID_X550EM_A_KR_L: 213 case IXGBE_DEV_ID_X550EM_A_SFP_N: 214 case IXGBE_DEV_ID_X550EM_A_SGMII: 215 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 216 case IXGBE_DEV_ID_X550EM_A_1G_T: 217 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 218 case IXGBE_DEV_ID_X550EM_A_10G_T: 219 case IXGBE_DEV_ID_X550EM_A_QSFP: 220 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 221 case IXGBE_DEV_ID_X550EM_A_SFP: 222 hw->mac.type = ixgbe_mac_X550EM_a; 223 hw->mvals = ixgbe_mvals_X550EM_a; 224 break; 225 case IXGBE_DEV_ID_X550_VF: 226 case IXGBE_DEV_ID_X550_VF_HV: 227 hw->mac.type = ixgbe_mac_X550_vf; 228 hw->mvals = ixgbe_mvals_X550; 229 break; 230 case IXGBE_DEV_ID_X550EM_X_VF: 231 case IXGBE_DEV_ID_X550EM_X_VF_HV: 232 hw->mac.type = ixgbe_mac_X550EM_x_vf; 233 hw->mvals = ixgbe_mvals_X550EM_x; 234 break; 235 case IXGBE_DEV_ID_X550EM_A_VF: 236 case IXGBE_DEV_ID_X550EM_A_VF_HV: 237 hw->mac.type = ixgbe_mac_X550EM_a_vf; 238 hw->mvals = ixgbe_mvals_X550EM_a; 239 break; 240 default: 241 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 242 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 243 "Unsupported device id: %x", 244 hw->device_id); 245 break; 246 } 247 248 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 249 hw->mac.type, ret_val); 250 return ret_val; 251 } 252 253 /** 254 * ixgbe_init_hw - Initialize the hardware 255 * @hw: pointer to hardware structure 256 * 257 * Initialize the hardware by resetting and then starting the hardware 258 **/ 259 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 260 { 261 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 262 IXGBE_NOT_IMPLEMENTED); 263 } 264 265 /** 266 * ixgbe_reset_hw - Performs a hardware reset 267 * @hw: pointer to hardware structure 268 * 269 * Resets the hardware by resetting the transmit and receive units, masks and 270 * clears all interrupts, performs a PHY reset, and performs a MAC reset 271 **/ 272 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 273 { 274 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 275 IXGBE_NOT_IMPLEMENTED); 276 } 277 278 /** 279 * ixgbe_start_hw - Prepares hardware for Rx/Tx 280 * @hw: pointer to hardware structure 281 * 282 * Starts the hardware by filling the bus info structure and media type, 283 * clears all on chip counters, initializes receive address registers, 284 * multicast table, VLAN filter table, calls routine to setup link and 285 * flow control settings, and leaves transmit and receive units disabled 286 * and uninitialized. 287 **/ 288 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 289 { 290 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 291 IXGBE_NOT_IMPLEMENTED); 292 } 293 294 /** 295 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 296 * which is disabled by default in ixgbe_start_hw(); 297 * 298 * @hw: pointer to hardware structure 299 * 300 * Enable relaxed ordering; 301 **/ 302 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 303 { 304 if (hw->mac.ops.enable_relaxed_ordering) 305 hw->mac.ops.enable_relaxed_ordering(hw); 306 } 307 308 /** 309 * ixgbe_clear_hw_cntrs - Clear hardware counters 310 * @hw: pointer to hardware structure 311 * 312 * Clears all hardware statistics counters by reading them from the hardware 313 * Statistics counters are clear on read. 314 **/ 315 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 316 { 317 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 318 IXGBE_NOT_IMPLEMENTED); 319 } 320 321 /** 322 * ixgbe_get_media_type - Get media type 323 * @hw: pointer to hardware structure 324 * 325 * Returns the media type (fiber, copper, backplane) 326 **/ 327 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 328 { 329 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 330 ixgbe_media_type_unknown); 331 } 332 333 /** 334 * ixgbe_get_mac_addr - Get MAC address 335 * @hw: pointer to hardware structure 336 * @mac_addr: Adapter MAC address 337 * 338 * Reads the adapter's MAC address from the first Receive Address Register 339 * (RAR0) A reset of the adapter must have been performed prior to calling 340 * this function in order for the MAC address to have been loaded from the 341 * EEPROM into RAR0 342 **/ 343 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 344 { 345 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 346 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 347 } 348 349 /** 350 * ixgbe_get_san_mac_addr - Get SAN MAC address 351 * @hw: pointer to hardware structure 352 * @san_mac_addr: SAN MAC address 353 * 354 * Reads the SAN MAC address from the EEPROM, if it's available. This is 355 * per-port, so set_lan_id() must be called before reading the addresses. 356 **/ 357 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 358 { 359 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 360 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 361 } 362 363 /** 364 * ixgbe_set_san_mac_addr - Write a SAN MAC address 365 * @hw: pointer to hardware structure 366 * @san_mac_addr: SAN MAC address 367 * 368 * Writes A SAN MAC address to the EEPROM. 369 **/ 370 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 371 { 372 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 373 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 374 } 375 376 /** 377 * ixgbe_get_device_caps - Get additional device capabilities 378 * @hw: pointer to hardware structure 379 * @device_caps: the EEPROM word for device capabilities 380 * 381 * Reads the extra device capabilities from the EEPROM 382 **/ 383 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 384 { 385 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 386 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 387 } 388 389 /** 390 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 391 * @hw: pointer to hardware structure 392 * @wwnn_prefix: the alternative WWNN prefix 393 * @wwpn_prefix: the alternative WWPN prefix 394 * 395 * This function will read the EEPROM from the alternative SAN MAC address 396 * block to check the support for the alternative WWNN/WWPN prefix support. 397 **/ 398 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 399 u16 *wwpn_prefix) 400 { 401 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 402 (hw, wwnn_prefix, wwpn_prefix), 403 IXGBE_NOT_IMPLEMENTED); 404 } 405 406 /** 407 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 408 * @hw: pointer to hardware structure 409 * @bs: the fcoe boot status 410 * 411 * This function will read the FCOE boot status from the iSCSI FCOE block 412 **/ 413 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 414 { 415 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 416 (hw, bs), 417 IXGBE_NOT_IMPLEMENTED); 418 } 419 420 /** 421 * ixgbe_get_bus_info - Set PCI bus info 422 * @hw: pointer to hardware structure 423 * 424 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 425 **/ 426 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 427 { 428 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 429 IXGBE_NOT_IMPLEMENTED); 430 } 431 432 /** 433 * ixgbe_get_num_of_tx_queues - Get Tx queues 434 * @hw: pointer to hardware structure 435 * 436 * Returns the number of transmit queues for the given adapter. 437 **/ 438 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 439 { 440 return hw->mac.max_tx_queues; 441 } 442 443 /** 444 * ixgbe_get_num_of_rx_queues - Get Rx queues 445 * @hw: pointer to hardware structure 446 * 447 * Returns the number of receive queues for the given adapter. 448 **/ 449 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 450 { 451 return hw->mac.max_rx_queues; 452 } 453 454 /** 455 * ixgbe_stop_adapter - Disable Rx/Tx units 456 * @hw: pointer to hardware structure 457 * 458 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 459 * disables transmit and receive units. The adapter_stopped flag is used by 460 * the shared code and drivers to determine if the adapter is in a stopped 461 * state and should not touch the hardware. 462 **/ 463 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 464 { 465 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 466 IXGBE_NOT_IMPLEMENTED); 467 } 468 469 /** 470 * ixgbe_read_pba_string - Reads part number string from EEPROM 471 * @hw: pointer to hardware structure 472 * @pba_num: stores the part number string from the EEPROM 473 * @pba_num_size: part number string buffer length 474 * 475 * Reads the part number string from the EEPROM. 476 **/ 477 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 478 { 479 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 480 } 481 482 /** 483 * ixgbe_read_pba_num - Reads part number from EEPROM 484 * @hw: pointer to hardware structure 485 * @pba_num: stores the part number from the EEPROM 486 * 487 * Reads the part number from the EEPROM. 488 **/ 489 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 490 { 491 return ixgbe_read_pba_num_generic(hw, pba_num); 492 } 493 494 /** 495 * ixgbe_identify_phy - Get PHY type 496 * @hw: pointer to hardware structure 497 * 498 * Determines the physical layer module found on the current adapter. 499 **/ 500 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 501 { 502 s32 status = IXGBE_SUCCESS; 503 504 if (hw->phy.type == ixgbe_phy_unknown) { 505 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 506 IXGBE_NOT_IMPLEMENTED); 507 } 508 509 return status; 510 } 511 512 /** 513 * ixgbe_reset_phy - Perform a PHY reset 514 * @hw: pointer to hardware structure 515 **/ 516 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 517 { 518 s32 status = IXGBE_SUCCESS; 519 520 if (hw->phy.type == ixgbe_phy_unknown) { 521 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 522 status = IXGBE_ERR_PHY; 523 } 524 525 if (status == IXGBE_SUCCESS) { 526 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 527 IXGBE_NOT_IMPLEMENTED); 528 } 529 return status; 530 } 531 532 /** 533 * ixgbe_get_phy_firmware_version - 534 * @hw: pointer to hardware structure 535 * @firmware_version: pointer to firmware version 536 **/ 537 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 538 { 539 s32 status = IXGBE_SUCCESS; 540 541 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 542 (hw, firmware_version), 543 IXGBE_NOT_IMPLEMENTED); 544 return status; 545 } 546 547 /** 548 * ixgbe_read_phy_reg - Read PHY register 549 * @hw: pointer to hardware structure 550 * @reg_addr: 32 bit address of PHY register to read 551 * @phy_data: Pointer to read data from PHY register 552 * 553 * Reads a value from a specified PHY register 554 **/ 555 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 556 u16 *phy_data) 557 { 558 if (hw->phy.id == 0) 559 ixgbe_identify_phy(hw); 560 561 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 562 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 563 } 564 565 /** 566 * ixgbe_write_phy_reg - Write PHY register 567 * @hw: pointer to hardware structure 568 * @reg_addr: 32 bit PHY register to write 569 * @phy_data: Data to write to the PHY register 570 * 571 * Writes a value to specified PHY register 572 **/ 573 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 574 u16 phy_data) 575 { 576 if (hw->phy.id == 0) 577 ixgbe_identify_phy(hw); 578 579 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 580 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 581 } 582 583 /** 584 * ixgbe_setup_phy_link - Restart PHY autoneg 585 * @hw: pointer to hardware structure 586 * 587 * Restart autonegotiation and PHY and waits for completion. 588 **/ 589 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 590 { 591 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 592 IXGBE_NOT_IMPLEMENTED); 593 } 594 595 /** 596 * ixgbe_setup_internal_phy - Configure integrated PHY 597 * @hw: pointer to hardware structure 598 * 599 * Reconfigure the integrated PHY in order to enable talk to the external PHY. 600 * Returns success if not implemented, since nothing needs to be done in this 601 * case. 602 */ 603 s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw) 604 { 605 return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw), 606 IXGBE_SUCCESS); 607 } 608 609 /** 610 * ixgbe_check_phy_link - Determine link and speed status 611 * @hw: pointer to hardware structure 612 * 613 * Reads a PHY register to determine if link is up and the current speed for 614 * the PHY. 615 **/ 616 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 617 bool *link_up) 618 { 619 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 620 link_up), IXGBE_NOT_IMPLEMENTED); 621 } 622 623 /** 624 * ixgbe_setup_phy_link_speed - Set auto advertise 625 * @hw: pointer to hardware structure 626 * @speed: new link speed 627 * 628 * Sets the auto advertised capabilities 629 **/ 630 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 631 bool autoneg_wait_to_complete) 632 { 633 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 634 autoneg_wait_to_complete), 635 IXGBE_NOT_IMPLEMENTED); 636 } 637 638 /** 639 * ixgbe_set_phy_power - Control the phy power state 640 * @hw: pointer to hardware structure 641 * @on: true for on, false for off 642 */ 643 s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on) 644 { 645 return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on), 646 IXGBE_NOT_IMPLEMENTED); 647 } 648 649 /** 650 * ixgbe_check_link - Get link and speed status 651 * @hw: pointer to hardware structure 652 * 653 * Reads the links register to determine if link is up and the current speed 654 **/ 655 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 656 bool *link_up, bool link_up_wait_to_complete) 657 { 658 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 659 link_up, link_up_wait_to_complete), 660 IXGBE_NOT_IMPLEMENTED); 661 } 662 663 /** 664 * ixgbe_disable_tx_laser - Disable Tx laser 665 * @hw: pointer to hardware structure 666 * 667 * If the driver needs to disable the laser on SFI optics. 668 **/ 669 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 670 { 671 if (hw->mac.ops.disable_tx_laser) 672 hw->mac.ops.disable_tx_laser(hw); 673 } 674 675 /** 676 * ixgbe_enable_tx_laser - Enable Tx laser 677 * @hw: pointer to hardware structure 678 * 679 * If the driver needs to enable the laser on SFI optics. 680 **/ 681 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 682 { 683 if (hw->mac.ops.enable_tx_laser) 684 hw->mac.ops.enable_tx_laser(hw); 685 } 686 687 /** 688 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 689 * @hw: pointer to hardware structure 690 * 691 * When the driver changes the link speeds that it can support then 692 * flap the tx laser to alert the link partner to start autotry 693 * process on its end. 694 **/ 695 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 696 { 697 if (hw->mac.ops.flap_tx_laser) 698 hw->mac.ops.flap_tx_laser(hw); 699 } 700 701 /** 702 * ixgbe_setup_link - Set link speed 703 * @hw: pointer to hardware structure 704 * @speed: new link speed 705 * 706 * Configures link settings. Restarts the link. 707 * Performs autonegotiation if needed. 708 **/ 709 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 710 bool autoneg_wait_to_complete) 711 { 712 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 713 autoneg_wait_to_complete), 714 IXGBE_NOT_IMPLEMENTED); 715 } 716 717 /** 718 * ixgbe_setup_mac_link - Set link speed 719 * @hw: pointer to hardware structure 720 * @speed: new link speed 721 * 722 * Configures link settings. Restarts the link. 723 * Performs autonegotiation if needed. 724 **/ 725 s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 726 bool autoneg_wait_to_complete) 727 { 728 return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed, 729 autoneg_wait_to_complete), 730 IXGBE_NOT_IMPLEMENTED); 731 } 732 733 /** 734 * ixgbe_get_link_capabilities - Returns link capabilities 735 * @hw: pointer to hardware structure 736 * 737 * Determines the link capabilities of the current configuration. 738 **/ 739 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 740 bool *autoneg) 741 { 742 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 743 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 744 } 745 746 /** 747 * ixgbe_led_on - Turn on LEDs 748 * @hw: pointer to hardware structure 749 * @index: led number to turn on 750 * 751 * Turns on the software controllable LEDs. 752 **/ 753 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 754 { 755 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 756 IXGBE_NOT_IMPLEMENTED); 757 } 758 759 /** 760 * ixgbe_led_off - Turn off LEDs 761 * @hw: pointer to hardware structure 762 * @index: led number to turn off 763 * 764 * Turns off the software controllable LEDs. 765 **/ 766 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 767 { 768 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 769 IXGBE_NOT_IMPLEMENTED); 770 } 771 772 /** 773 * ixgbe_blink_led_start - Blink LEDs 774 * @hw: pointer to hardware structure 775 * @index: led number to blink 776 * 777 * Blink LED based on index. 778 **/ 779 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 780 { 781 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 782 IXGBE_NOT_IMPLEMENTED); 783 } 784 785 /** 786 * ixgbe_blink_led_stop - Stop blinking LEDs 787 * @hw: pointer to hardware structure 788 * 789 * Stop blinking LED based on index. 790 **/ 791 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 792 { 793 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 794 IXGBE_NOT_IMPLEMENTED); 795 } 796 797 /** 798 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 799 * @hw: pointer to hardware structure 800 * 801 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 802 * ixgbe_hw struct in order to set up EEPROM access. 803 **/ 804 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 805 { 806 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 807 IXGBE_NOT_IMPLEMENTED); 808 } 809 810 811 /** 812 * ixgbe_write_eeprom - Write word to EEPROM 813 * @hw: pointer to hardware structure 814 * @offset: offset within the EEPROM to be written to 815 * @data: 16 bit word to be written to the EEPROM 816 * 817 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 818 * called after this function, the EEPROM will most likely contain an 819 * invalid checksum. 820 **/ 821 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 822 { 823 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 824 IXGBE_NOT_IMPLEMENTED); 825 } 826 827 /** 828 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 829 * @hw: pointer to hardware structure 830 * @offset: offset within the EEPROM to be written to 831 * @data: 16 bit word(s) to be written to the EEPROM 832 * @words: number of words 833 * 834 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 835 * called after this function, the EEPROM will most likely contain an 836 * invalid checksum. 837 **/ 838 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 839 u16 *data) 840 { 841 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 842 (hw, offset, words, data), 843 IXGBE_NOT_IMPLEMENTED); 844 } 845 846 /** 847 * ixgbe_read_eeprom - Read word from EEPROM 848 * @hw: pointer to hardware structure 849 * @offset: offset within the EEPROM to be read 850 * @data: read 16 bit value from EEPROM 851 * 852 * Reads 16 bit value from EEPROM 853 **/ 854 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 855 { 856 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 857 IXGBE_NOT_IMPLEMENTED); 858 } 859 860 /** 861 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 862 * @hw: pointer to hardware structure 863 * @offset: offset within the EEPROM to be read 864 * @data: read 16 bit word(s) from EEPROM 865 * @words: number of words 866 * 867 * Reads 16 bit word(s) from EEPROM 868 **/ 869 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 870 u16 words, u16 *data) 871 { 872 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 873 (hw, offset, words, data), 874 IXGBE_NOT_IMPLEMENTED); 875 } 876 877 /** 878 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 879 * @hw: pointer to hardware structure 880 * @checksum_val: calculated checksum 881 * 882 * Performs checksum calculation and validates the EEPROM checksum 883 **/ 884 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 885 { 886 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 887 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 888 } 889 890 /** 891 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 892 * @hw: pointer to hardware structure 893 **/ 894 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 895 { 896 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 897 IXGBE_NOT_IMPLEMENTED); 898 } 899 900 /** 901 * ixgbe_insert_mac_addr - Find a RAR for this mac address 902 * @hw: pointer to hardware structure 903 * @addr: Address to put into receive address register 904 * @vmdq: VMDq pool to assign 905 * 906 * Puts an ethernet address into a receive address register, or 907 * finds the rar that it is aleady in; adds to the pool list 908 **/ 909 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 910 { 911 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 912 (hw, addr, vmdq), 913 IXGBE_NOT_IMPLEMENTED); 914 } 915 916 /** 917 * ixgbe_set_rar - Set Rx address register 918 * @hw: pointer to hardware structure 919 * @index: Receive address register to write 920 * @addr: Address to put into receive address register 921 * @vmdq: VMDq "set" 922 * @enable_addr: set flag that address is active 923 * 924 * Puts an ethernet address into a receive address register. 925 **/ 926 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 927 u32 enable_addr) 928 { 929 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 930 enable_addr), IXGBE_NOT_IMPLEMENTED); 931 } 932 933 /** 934 * ixgbe_clear_rar - Clear Rx address register 935 * @hw: pointer to hardware structure 936 * @index: Receive address register to write 937 * 938 * Puts an ethernet address into a receive address register. 939 **/ 940 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 941 { 942 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 943 IXGBE_NOT_IMPLEMENTED); 944 } 945 946 /** 947 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 948 * @hw: pointer to hardware structure 949 * @rar: receive address register index to associate with VMDq index 950 * @vmdq: VMDq set or pool index 951 **/ 952 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 953 { 954 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 955 IXGBE_NOT_IMPLEMENTED); 956 957 } 958 959 /** 960 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address 961 * @hw: pointer to hardware structure 962 * @vmdq: VMDq default pool index 963 **/ 964 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) 965 { 966 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac, 967 (hw, vmdq), IXGBE_NOT_IMPLEMENTED); 968 } 969 970 /** 971 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 972 * @hw: pointer to hardware structure 973 * @rar: receive address register index to disassociate with VMDq index 974 * @vmdq: VMDq set or pool index 975 **/ 976 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 977 { 978 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 979 IXGBE_NOT_IMPLEMENTED); 980 } 981 982 /** 983 * ixgbe_init_rx_addrs - Initializes receive address filters. 984 * @hw: pointer to hardware structure 985 * 986 * Places the MAC address in receive address register 0 and clears the rest 987 * of the receive address registers. Clears the multicast table. Assumes 988 * the receiver is in reset when the routine is called. 989 **/ 990 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 991 { 992 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 993 IXGBE_NOT_IMPLEMENTED); 994 } 995 996 /** 997 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 998 * @hw: pointer to hardware structure 999 **/ 1000 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 1001 { 1002 return hw->mac.num_rar_entries; 1003 } 1004 1005 /** 1006 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 1007 * @hw: pointer to hardware structure 1008 * @addr_list: the list of new multicast addresses 1009 * @addr_count: number of addresses 1010 * @func: iterator function to walk the multicast address list 1011 * 1012 * The given list replaces any existing list. Clears the secondary addrs from 1013 * receive address registers. Uses unused receive address registers for the 1014 * first secondary addresses, and falls back to promiscuous mode as needed. 1015 **/ 1016 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 1017 u32 addr_count, ixgbe_mc_addr_itr func) 1018 { 1019 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 1020 addr_list, addr_count, func), 1021 IXGBE_NOT_IMPLEMENTED); 1022 } 1023 1024 /** 1025 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 1026 * @hw: pointer to hardware structure 1027 * @mc_addr_list: the list of new multicast addresses 1028 * @mc_addr_count: number of addresses 1029 * @func: iterator function to walk the multicast address list 1030 * 1031 * The given list replaces any existing list. Clears the MC addrs from receive 1032 * address registers and the multicast table. Uses unused receive address 1033 * registers for the first multicast addresses, and hashes the rest into the 1034 * multicast table. 1035 **/ 1036 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 1037 u32 mc_addr_count, ixgbe_mc_addr_itr func, 1038 bool clear) 1039 { 1040 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 1041 mc_addr_list, mc_addr_count, func, clear), 1042 IXGBE_NOT_IMPLEMENTED); 1043 } 1044 1045 /** 1046 * ixgbe_enable_mc - Enable multicast address in RAR 1047 * @hw: pointer to hardware structure 1048 * 1049 * Enables multicast address in RAR and the use of the multicast hash table. 1050 **/ 1051 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 1052 { 1053 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 1054 IXGBE_NOT_IMPLEMENTED); 1055 } 1056 1057 /** 1058 * ixgbe_disable_mc - Disable multicast address in RAR 1059 * @hw: pointer to hardware structure 1060 * 1061 * Disables multicast address in RAR and the use of the multicast hash table. 1062 **/ 1063 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 1064 { 1065 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 1066 IXGBE_NOT_IMPLEMENTED); 1067 } 1068 1069 /** 1070 * ixgbe_clear_vfta - Clear VLAN filter table 1071 * @hw: pointer to hardware structure 1072 * 1073 * Clears the VLAN filer table, and the VMDq index associated with the filter 1074 **/ 1075 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 1076 { 1077 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 1078 IXGBE_NOT_IMPLEMENTED); 1079 } 1080 1081 /** 1082 * ixgbe_set_vfta - Set VLAN filter table 1083 * @hw: pointer to hardware structure 1084 * @vlan: VLAN id to write to VLAN filter 1085 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1086 * @vlan_on: boolean flag to turn on/off VLAN 1087 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1088 * 1089 * Turn on/off specified VLAN in the VLAN filter table. 1090 **/ 1091 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1092 bool vlvf_bypass) 1093 { 1094 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 1095 vlan_on, vlvf_bypass), IXGBE_NOT_IMPLEMENTED); 1096 } 1097 1098 /** 1099 * ixgbe_set_vlvf - Set VLAN Pool Filter 1100 * @hw: pointer to hardware structure 1101 * @vlan: VLAN id to write to VLAN filter 1102 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1103 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 1104 * @vfta_delta: pointer to the difference between the current value of VFTA 1105 * and the desired value 1106 * @vfta: the desired value of the VFTA 1107 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1108 * 1109 * Turn on/off specified bit in VLVF table. 1110 **/ 1111 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1112 u32 *vfta_delta, u32 vfta, bool vlvf_bypass) 1113 { 1114 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 1115 vlan_on, vfta_delta, vfta, vlvf_bypass), 1116 IXGBE_NOT_IMPLEMENTED); 1117 } 1118 1119 /** 1120 * ixgbe_fc_enable - Enable flow control 1121 * @hw: pointer to hardware structure 1122 * 1123 * Configures the flow control settings based on SW configuration. 1124 **/ 1125 s32 ixgbe_fc_enable(struct ixgbe_hw *hw) 1126 { 1127 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), 1128 IXGBE_NOT_IMPLEMENTED); 1129 } 1130 1131 /** 1132 * ixgbe_setup_fc - Set up flow control 1133 * @hw: pointer to hardware structure 1134 * 1135 * Called at init time to set up flow control. 1136 **/ 1137 s32 ixgbe_setup_fc(struct ixgbe_hw *hw) 1138 { 1139 return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw), 1140 IXGBE_NOT_IMPLEMENTED); 1141 } 1142 1143 /** 1144 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 1145 * @hw: pointer to hardware structure 1146 * @maj: driver major number to be sent to firmware 1147 * @min: driver minor number to be sent to firmware 1148 * @build: driver build number to be sent to firmware 1149 * @ver: driver version number to be sent to firmware 1150 **/ 1151 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, 1152 u8 ver) 1153 { 1154 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min, 1155 build, ver), IXGBE_NOT_IMPLEMENTED); 1156 } 1157 1158 1159 /** 1160 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data 1161 * @hw: pointer to hardware structure 1162 * 1163 * Updates the temperatures in mac.thermal_sensor_data 1164 **/ 1165 s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw) 1166 { 1167 return ixgbe_call_func(hw, hw->mac.ops.get_thermal_sensor_data, (hw), 1168 IXGBE_NOT_IMPLEMENTED); 1169 } 1170 1171 /** 1172 * ixgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds 1173 * @hw: pointer to hardware structure 1174 * 1175 * Inits the thermal sensor thresholds according to the NVM map 1176 **/ 1177 s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw) 1178 { 1179 return ixgbe_call_func(hw, hw->mac.ops.init_thermal_sensor_thresh, (hw), 1180 IXGBE_NOT_IMPLEMENTED); 1181 } 1182 1183 /** 1184 * ixgbe_dmac_config - Configure DMA Coalescing registers. 1185 * @hw: pointer to hardware structure 1186 * 1187 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1188 * When disabling dmac, dmac enable dmac bit is cleared. 1189 **/ 1190 s32 ixgbe_dmac_config(struct ixgbe_hw *hw) 1191 { 1192 return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw), 1193 IXGBE_NOT_IMPLEMENTED); 1194 } 1195 1196 /** 1197 * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers. 1198 * @hw: pointer to hardware structure 1199 * 1200 * Disables dmac, updates per TC settings, and then enable dmac. 1201 **/ 1202 s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw) 1203 { 1204 return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw), 1205 IXGBE_NOT_IMPLEMENTED); 1206 } 1207 1208 /** 1209 * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers. 1210 * @hw: pointer to hardware structure 1211 * 1212 * Configure DMA coalescing threshold per TC and set high priority bit for 1213 * FCOE TC. The dmac enable bit must be cleared before configuring. 1214 **/ 1215 s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw) 1216 { 1217 return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw), 1218 IXGBE_NOT_IMPLEMENTED); 1219 } 1220 1221 /** 1222 * ixgbe_setup_eee - Enable/disable EEE support 1223 * @hw: pointer to the HW structure 1224 * @enable_eee: boolean flag to enable EEE 1225 * 1226 * Enable/disable EEE based on enable_ee flag. 1227 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 1228 * are modified. 1229 * 1230 **/ 1231 s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee) 1232 { 1233 return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee), 1234 IXGBE_NOT_IMPLEMENTED); 1235 } 1236 1237 /** 1238 * ixgbe_set_source_address_pruning - Enable/Disable source address pruning 1239 * @hw: pointer to hardware structure 1240 * @enbale: enable or disable source address pruning 1241 * @pool: Rx pool - Rx pool to toggle source address pruning 1242 **/ 1243 void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, 1244 unsigned int pool) 1245 { 1246 if (hw->mac.ops.set_source_address_pruning) 1247 hw->mac.ops.set_source_address_pruning(hw, enable, pool); 1248 } 1249 1250 /** 1251 * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing 1252 * @hw: pointer to hardware structure 1253 * @enable: enable or disable switch for Ethertype anti-spoofing 1254 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1255 * 1256 **/ 1257 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 1258 { 1259 if (hw->mac.ops.set_ethertype_anti_spoofing) 1260 hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf); 1261 } 1262 1263 /** 1264 * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register 1265 * @hw: pointer to hardware structure 1266 * @reg_addr: 32 bit address of PHY register to read 1267 * @device_type: type of device you want to communicate with 1268 * @phy_data: Pointer to read data from PHY register 1269 * 1270 * Reads a value from a specified PHY register 1271 **/ 1272 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1273 u32 device_type, u32 *phy_data) 1274 { 1275 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, 1276 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1277 } 1278 1279 /** 1280 * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband 1281 * @hw: pointer to hardware structure 1282 * @reg_addr: 32 bit PHY register to write 1283 * @device_type: type of device you want to communicate with 1284 * @phy_data: Data to write to the PHY register 1285 * 1286 * Writes a value to specified PHY register 1287 **/ 1288 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1289 u32 device_type, u32 phy_data) 1290 { 1291 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, 1292 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1293 } 1294 1295 /** 1296 * ixgbe_disable_mdd - Disable malicious driver detection 1297 * @hw: pointer to hardware structure 1298 * 1299 **/ 1300 void ixgbe_disable_mdd(struct ixgbe_hw *hw) 1301 { 1302 if (hw->mac.ops.disable_mdd) 1303 hw->mac.ops.disable_mdd(hw); 1304 } 1305 1306 /** 1307 * ixgbe_enable_mdd - Enable malicious driver detection 1308 * @hw: pointer to hardware structure 1309 * 1310 **/ 1311 void ixgbe_enable_mdd(struct ixgbe_hw *hw) 1312 { 1313 if (hw->mac.ops.enable_mdd) 1314 hw->mac.ops.enable_mdd(hw); 1315 } 1316 1317 /** 1318 * ixgbe_mdd_event - Handle malicious driver detection event 1319 * @hw: pointer to hardware structure 1320 * @vf_bitmap: vf bitmap of malicious vfs 1321 * 1322 **/ 1323 void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap) 1324 { 1325 if (hw->mac.ops.mdd_event) 1326 hw->mac.ops.mdd_event(hw, vf_bitmap); 1327 } 1328 1329 /** 1330 * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver 1331 * detection event 1332 * @hw: pointer to hardware structure 1333 * @vf: vf index 1334 * 1335 **/ 1336 void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf) 1337 { 1338 if (hw->mac.ops.restore_mdd_vf) 1339 hw->mac.ops.restore_mdd_vf(hw, vf); 1340 } 1341 1342 /** 1343 * ixgbe_enter_lplu - Transition to low power states 1344 * @hw: pointer to hardware structure 1345 * 1346 * Configures Low Power Link Up on transition to low power states 1347 * (from D0 to non-D0). 1348 **/ 1349 s32 ixgbe_enter_lplu(struct ixgbe_hw *hw) 1350 { 1351 return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw), 1352 IXGBE_NOT_IMPLEMENTED); 1353 } 1354 1355 /** 1356 * ixgbe_handle_lasi - Handle external Base T PHY interrupt 1357 * @hw: pointer to hardware structure 1358 * 1359 * Handle external Base T PHY interrupt. If high temperature 1360 * failure alarm then return error, else if link status change 1361 * then setup internal/external PHY link 1362 * 1363 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1364 * failure alarm, else return PHY access status. 1365 */ 1366 s32 ixgbe_handle_lasi(struct ixgbe_hw *hw) 1367 { 1368 return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw), 1369 IXGBE_NOT_IMPLEMENTED); 1370 } 1371 1372 /** 1373 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 1374 * @hw: pointer to hardware structure 1375 * @reg: analog register to read 1376 * @val: read value 1377 * 1378 * Performs write operation to analog register specified. 1379 **/ 1380 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 1381 { 1382 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1383 val), IXGBE_NOT_IMPLEMENTED); 1384 } 1385 1386 /** 1387 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1388 * @hw: pointer to hardware structure 1389 * @reg: analog register to write 1390 * @val: value to write 1391 * 1392 * Performs write operation to Atlas analog register specified. 1393 **/ 1394 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1395 { 1396 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1397 val), IXGBE_NOT_IMPLEMENTED); 1398 } 1399 1400 /** 1401 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1402 * @hw: pointer to hardware structure 1403 * 1404 * Initializes the Unicast Table Arrays to zero on device load. This 1405 * is part of the Rx init addr execution path. 1406 **/ 1407 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1408 { 1409 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1410 IXGBE_NOT_IMPLEMENTED); 1411 } 1412 1413 /** 1414 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1415 * @hw: pointer to hardware structure 1416 * @byte_offset: byte offset to read 1417 * @dev_addr: I2C bus address to read from 1418 * @data: value read 1419 * 1420 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1421 **/ 1422 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1423 u8 *data) 1424 { 1425 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1426 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1427 } 1428 1429 /** 1430 * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address 1431 * @hw: pointer to hardware structure 1432 * @byte_offset: byte offset to read 1433 * @dev_addr: I2C bus address to read from 1434 * @data: value read 1435 * 1436 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1437 **/ 1438 s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1439 u8 dev_addr, u8 *data) 1440 { 1441 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked, 1442 (hw, byte_offset, dev_addr, data), 1443 IXGBE_NOT_IMPLEMENTED); 1444 } 1445 1446 /** 1447 * ixgbe_read_link - Perform read operation on link device 1448 * @hw: pointer to the hardware structure 1449 * @addr: bus address to read from 1450 * @reg: device register to read from 1451 * @val: pointer to location to receive read value 1452 * 1453 * Returns an error code on error. 1454 */ 1455 s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1456 { 1457 return ixgbe_call_func(hw, hw->link.ops.read_link, (hw, addr, 1458 reg, val), IXGBE_NOT_IMPLEMENTED); 1459 } 1460 1461 /** 1462 * ixgbe_read_link_unlocked - Perform read operation on link device 1463 * @hw: pointer to the hardware structure 1464 * @addr: bus address to read from 1465 * @reg: device register to read from 1466 * @val: pointer to location to receive read value 1467 * 1468 * Returns an error code on error. 1469 **/ 1470 s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1471 { 1472 return ixgbe_call_func(hw, hw->link.ops.read_link_unlocked, 1473 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1474 } 1475 1476 /** 1477 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1478 * @hw: pointer to hardware structure 1479 * @byte_offset: byte offset to write 1480 * @dev_addr: I2C bus address to write to 1481 * @data: value to write 1482 * 1483 * Performs byte write operation to SFP module's EEPROM over I2C interface 1484 * at a specified device address. 1485 **/ 1486 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1487 u8 data) 1488 { 1489 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1490 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1491 } 1492 1493 /** 1494 * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1495 * @hw: pointer to hardware structure 1496 * @byte_offset: byte offset to write 1497 * @dev_addr: I2C bus address to write to 1498 * @data: value to write 1499 * 1500 * Performs byte write operation to SFP module's EEPROM over I2C interface 1501 * at a specified device address. 1502 **/ 1503 s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1504 u8 dev_addr, u8 data) 1505 { 1506 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked, 1507 (hw, byte_offset, dev_addr, data), 1508 IXGBE_NOT_IMPLEMENTED); 1509 } 1510 1511 /** 1512 * ixgbe_write_link - Perform write operation on link device 1513 * @hw: pointer to the hardware structure 1514 * @addr: bus address to write to 1515 * @reg: device register to write to 1516 * @val: value to write 1517 * 1518 * Returns an error code on error. 1519 */ 1520 s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1521 { 1522 return ixgbe_call_func(hw, hw->link.ops.write_link, 1523 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1524 } 1525 1526 /** 1527 * ixgbe_write_link_unlocked - Perform write operation on link device 1528 * @hw: pointer to the hardware structure 1529 * @addr: bus address to write to 1530 * @reg: device register to write to 1531 * @val: value to write 1532 * 1533 * Returns an error code on error. 1534 **/ 1535 s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1536 { 1537 return ixgbe_call_func(hw, hw->link.ops.write_link_unlocked, 1538 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1539 } 1540 1541 /** 1542 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1543 * @hw: pointer to hardware structure 1544 * @byte_offset: EEPROM byte offset to write 1545 * @eeprom_data: value to write 1546 * 1547 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1548 **/ 1549 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1550 u8 byte_offset, u8 eeprom_data) 1551 { 1552 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1553 (hw, byte_offset, eeprom_data), 1554 IXGBE_NOT_IMPLEMENTED); 1555 } 1556 1557 /** 1558 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1559 * @hw: pointer to hardware structure 1560 * @byte_offset: EEPROM byte offset to read 1561 * @eeprom_data: value read 1562 * 1563 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1564 **/ 1565 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1566 { 1567 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1568 (hw, byte_offset, eeprom_data), 1569 IXGBE_NOT_IMPLEMENTED); 1570 } 1571 1572 /** 1573 * ixgbe_get_supported_physical_layer - Returns physical layer type 1574 * @hw: pointer to hardware structure 1575 * 1576 * Determines physical layer capabilities of the current configuration. 1577 **/ 1578 u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1579 { 1580 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1581 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1582 } 1583 1584 /** 1585 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics 1586 * @hw: pointer to hardware structure 1587 * @regval: bitfield to write to the Rx DMA register 1588 * 1589 * Enables the Rx DMA unit of the device. 1590 **/ 1591 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1592 { 1593 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1594 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1595 } 1596 1597 /** 1598 * ixgbe_disable_sec_rx_path - Stops the receive data path 1599 * @hw: pointer to hardware structure 1600 * 1601 * Stops the receive data path. 1602 **/ 1603 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1604 { 1605 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1606 (hw), IXGBE_NOT_IMPLEMENTED); 1607 } 1608 1609 /** 1610 * ixgbe_enable_sec_rx_path - Enables the receive data path 1611 * @hw: pointer to hardware structure 1612 * 1613 * Enables the receive data path. 1614 **/ 1615 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1616 { 1617 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1618 (hw), IXGBE_NOT_IMPLEMENTED); 1619 } 1620 1621 /** 1622 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1623 * @hw: pointer to hardware structure 1624 * @mask: Mask to specify which semaphore to acquire 1625 * 1626 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1627 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1628 **/ 1629 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1630 { 1631 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1632 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1633 } 1634 1635 /** 1636 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1637 * @hw: pointer to hardware structure 1638 * @mask: Mask to specify which semaphore to release 1639 * 1640 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1641 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1642 **/ 1643 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1644 { 1645 if (hw->mac.ops.release_swfw_sync) 1646 hw->mac.ops.release_swfw_sync(hw, mask); 1647 } 1648 1649 /** 1650 * ixgbe_init_swfw_semaphore - Clean up SWFW semaphore 1651 * @hw: pointer to hardware structure 1652 * 1653 * Attempts to acquire the SWFW semaphore through SW_FW_SYNC register. 1654 * Regardless of whether is succeeds or not it then release the semaphore. 1655 * This is function is called to recover from catastrophic failures that 1656 * may have left the semaphore locked. 1657 **/ 1658 void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw) 1659 { 1660 if (hw->mac.ops.init_swfw_sync) 1661 hw->mac.ops.init_swfw_sync(hw); 1662 } 1663 1664 1665 void ixgbe_disable_rx(struct ixgbe_hw *hw) 1666 { 1667 if (hw->mac.ops.disable_rx) 1668 hw->mac.ops.disable_rx(hw); 1669 } 1670 1671 void ixgbe_enable_rx(struct ixgbe_hw *hw) 1672 { 1673 if (hw->mac.ops.enable_rx) 1674 hw->mac.ops.enable_rx(hw); 1675 } 1676 1677 /** 1678 * ixgbe_set_rate_select_speed - Set module link speed 1679 * @hw: pointer to hardware structure 1680 * @speed: link speed to set 1681 * 1682 * Set module link speed via the rate select. 1683 */ 1684 void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 1685 { 1686 if (hw->mac.ops.set_rate_select_speed) 1687 hw->mac.ops.set_rate_select_speed(hw, speed); 1688 } 1689