1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2018 3 */ 4 5 #include "ixgbe_api.h" 6 #include "ixgbe_common.h" 7 8 #define IXGBE_EMPTY_PARAM 9 10 static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = { 11 IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM) 12 }; 13 14 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = { 15 IXGBE_MVALS_INIT(_X540) 16 }; 17 18 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 19 IXGBE_MVALS_INIT(_X550) 20 }; 21 22 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 23 IXGBE_MVALS_INIT(_X550EM_x) 24 }; 25 26 static const u32 ixgbe_mvals_X550EM_a[IXGBE_MVALS_IDX_LIMIT] = { 27 IXGBE_MVALS_INIT(_X550EM_a) 28 }; 29 30 /** 31 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg 32 * @hw: pointer to hardware structure 33 * @map: pointer to u8 arr for returning map 34 * 35 * Read the rtrup2tc HW register and resolve its content into map 36 **/ 37 void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map) 38 { 39 if (hw->mac.ops.get_rtrup2tc) 40 hw->mac.ops.get_rtrup2tc(hw, map); 41 } 42 43 /** 44 * ixgbe_init_shared_code - Initialize the shared code 45 * @hw: pointer to hardware structure 46 * 47 * This will assign function pointers and assign the MAC type and PHY code. 48 * Does not touch the hardware. This function must be called prior to any 49 * other function in the shared code. The ixgbe_hw structure should be 50 * memset to 0 prior to calling this function. The following fields in 51 * hw structure should be filled in prior to calling this function: 52 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 53 * subsystem_vendor_id, and revision_id 54 **/ 55 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 56 { 57 s32 status; 58 59 DEBUGFUNC("ixgbe_init_shared_code"); 60 61 /* 62 * Set the mac type 63 */ 64 ixgbe_set_mac_type(hw); 65 66 switch (hw->mac.type) { 67 case ixgbe_mac_82598EB: 68 status = ixgbe_init_ops_82598(hw); 69 break; 70 case ixgbe_mac_82599EB: 71 status = ixgbe_init_ops_82599(hw); 72 break; 73 case ixgbe_mac_X540: 74 status = ixgbe_init_ops_X540(hw); 75 break; 76 case ixgbe_mac_X550: 77 status = ixgbe_init_ops_X550(hw); 78 break; 79 case ixgbe_mac_X550EM_x: 80 status = ixgbe_init_ops_X550EM_x(hw); 81 break; 82 case ixgbe_mac_X550EM_a: 83 status = ixgbe_init_ops_X550EM_a(hw); 84 break; 85 case ixgbe_mac_82599_vf: 86 case ixgbe_mac_X540_vf: 87 case ixgbe_mac_X550_vf: 88 case ixgbe_mac_X550EM_x_vf: 89 case ixgbe_mac_X550EM_a_vf: 90 status = ixgbe_init_ops_vf(hw); 91 break; 92 default: 93 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 94 break; 95 } 96 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; 97 98 return status; 99 } 100 101 /** 102 * ixgbe_set_mac_type - Sets MAC type 103 * @hw: pointer to the HW structure 104 * 105 * This function sets the mac type of the adapter based on the 106 * vendor ID and device ID stored in the hw structure. 107 **/ 108 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 109 { 110 s32 ret_val = IXGBE_SUCCESS; 111 112 DEBUGFUNC("ixgbe_set_mac_type\n"); 113 114 if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { 115 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 116 "Unsupported vendor id: %x", hw->vendor_id); 117 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 118 } 119 120 hw->mvals = ixgbe_mvals_base; 121 122 switch (hw->device_id) { 123 case IXGBE_DEV_ID_82598: 124 case IXGBE_DEV_ID_82598_BX: 125 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 126 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 127 case IXGBE_DEV_ID_82598AT: 128 case IXGBE_DEV_ID_82598AT2: 129 case IXGBE_DEV_ID_82598EB_CX4: 130 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 131 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 132 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 133 case IXGBE_DEV_ID_82598EB_XF_LR: 134 case IXGBE_DEV_ID_82598EB_SFP_LOM: 135 hw->mac.type = ixgbe_mac_82598EB; 136 break; 137 case IXGBE_DEV_ID_82599_KX4: 138 case IXGBE_DEV_ID_82599_KX4_MEZZ: 139 case IXGBE_DEV_ID_82599_XAUI_LOM: 140 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 141 case IXGBE_DEV_ID_82599_KR: 142 case IXGBE_DEV_ID_82599_SFP: 143 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 144 case IXGBE_DEV_ID_82599_SFP_FCOE: 145 case IXGBE_DEV_ID_82599_SFP_EM: 146 case IXGBE_DEV_ID_82599_SFP_SF2: 147 case IXGBE_DEV_ID_82599_SFP_SF_QP: 148 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 149 case IXGBE_DEV_ID_82599EN_SFP: 150 case IXGBE_DEV_ID_82599_CX4: 151 case IXGBE_DEV_ID_82599_LS: 152 case IXGBE_DEV_ID_82599_BYPASS: 153 case IXGBE_DEV_ID_82599_T3_LOM: 154 hw->mac.type = ixgbe_mac_82599EB; 155 break; 156 case IXGBE_DEV_ID_82599_VF: 157 case IXGBE_DEV_ID_82599_VF_HV: 158 hw->mac.type = ixgbe_mac_82599_vf; 159 break; 160 case IXGBE_DEV_ID_X540_VF: 161 case IXGBE_DEV_ID_X540_VF_HV: 162 hw->mac.type = ixgbe_mac_X540_vf; 163 hw->mvals = ixgbe_mvals_X540; 164 break; 165 case IXGBE_DEV_ID_X540T: 166 case IXGBE_DEV_ID_X540T1: 167 case IXGBE_DEV_ID_X540_BYPASS: 168 hw->mac.type = ixgbe_mac_X540; 169 hw->mvals = ixgbe_mvals_X540; 170 break; 171 case IXGBE_DEV_ID_X550T: 172 case IXGBE_DEV_ID_X550T1: 173 hw->mac.type = ixgbe_mac_X550; 174 hw->mvals = ixgbe_mvals_X550; 175 break; 176 case IXGBE_DEV_ID_X550EM_X_KX4: 177 case IXGBE_DEV_ID_X550EM_X_KR: 178 case IXGBE_DEV_ID_X550EM_X_10G_T: 179 case IXGBE_DEV_ID_X550EM_X_1G_T: 180 case IXGBE_DEV_ID_X550EM_X_SFP: 181 case IXGBE_DEV_ID_X550EM_X_XFI: 182 hw->mac.type = ixgbe_mac_X550EM_x; 183 hw->mvals = ixgbe_mvals_X550EM_x; 184 break; 185 case IXGBE_DEV_ID_X550EM_A_KR: 186 case IXGBE_DEV_ID_X550EM_A_KR_L: 187 case IXGBE_DEV_ID_X550EM_A_SFP_N: 188 case IXGBE_DEV_ID_X550EM_A_SGMII: 189 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 190 case IXGBE_DEV_ID_X550EM_A_1G_T: 191 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 192 case IXGBE_DEV_ID_X550EM_A_10G_T: 193 case IXGBE_DEV_ID_X550EM_A_QSFP: 194 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 195 case IXGBE_DEV_ID_X550EM_A_SFP: 196 hw->mac.type = ixgbe_mac_X550EM_a; 197 hw->mvals = ixgbe_mvals_X550EM_a; 198 break; 199 case IXGBE_DEV_ID_X550_VF: 200 case IXGBE_DEV_ID_X550_VF_HV: 201 hw->mac.type = ixgbe_mac_X550_vf; 202 hw->mvals = ixgbe_mvals_X550; 203 break; 204 case IXGBE_DEV_ID_X550EM_X_VF: 205 case IXGBE_DEV_ID_X550EM_X_VF_HV: 206 hw->mac.type = ixgbe_mac_X550EM_x_vf; 207 hw->mvals = ixgbe_mvals_X550EM_x; 208 break; 209 case IXGBE_DEV_ID_X550EM_A_VF: 210 case IXGBE_DEV_ID_X550EM_A_VF_HV: 211 hw->mac.type = ixgbe_mac_X550EM_a_vf; 212 hw->mvals = ixgbe_mvals_X550EM_a; 213 break; 214 default: 215 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 216 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 217 "Unsupported device id: %x", 218 hw->device_id); 219 break; 220 } 221 222 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 223 hw->mac.type, ret_val); 224 return ret_val; 225 } 226 227 /** 228 * ixgbe_init_hw - Initialize the hardware 229 * @hw: pointer to hardware structure 230 * 231 * Initialize the hardware by resetting and then starting the hardware 232 **/ 233 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 234 { 235 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 236 IXGBE_NOT_IMPLEMENTED); 237 } 238 239 /** 240 * ixgbe_reset_hw - Performs a hardware reset 241 * @hw: pointer to hardware structure 242 * 243 * Resets the hardware by resetting the transmit and receive units, masks and 244 * clears all interrupts, performs a PHY reset, and performs a MAC reset 245 **/ 246 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 247 { 248 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 249 IXGBE_NOT_IMPLEMENTED); 250 } 251 252 /** 253 * ixgbe_start_hw - Prepares hardware for Rx/Tx 254 * @hw: pointer to hardware structure 255 * 256 * Starts the hardware by filling the bus info structure and media type, 257 * clears all on chip counters, initializes receive address registers, 258 * multicast table, VLAN filter table, calls routine to setup link and 259 * flow control settings, and leaves transmit and receive units disabled 260 * and uninitialized. 261 **/ 262 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 263 { 264 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 265 IXGBE_NOT_IMPLEMENTED); 266 } 267 268 /** 269 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 270 * which is disabled by default in ixgbe_start_hw(); 271 * 272 * @hw: pointer to hardware structure 273 * 274 * Enable relaxed ordering; 275 **/ 276 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 277 { 278 if (hw->mac.ops.enable_relaxed_ordering) 279 hw->mac.ops.enable_relaxed_ordering(hw); 280 } 281 282 /** 283 * ixgbe_clear_hw_cntrs - Clear hardware counters 284 * @hw: pointer to hardware structure 285 * 286 * Clears all hardware statistics counters by reading them from the hardware 287 * Statistics counters are clear on read. 288 **/ 289 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 290 { 291 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 292 IXGBE_NOT_IMPLEMENTED); 293 } 294 295 /** 296 * ixgbe_get_media_type - Get media type 297 * @hw: pointer to hardware structure 298 * 299 * Returns the media type (fiber, copper, backplane) 300 **/ 301 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 302 { 303 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 304 ixgbe_media_type_unknown); 305 } 306 307 /** 308 * ixgbe_get_mac_addr - Get MAC address 309 * @hw: pointer to hardware structure 310 * @mac_addr: Adapter MAC address 311 * 312 * Reads the adapter's MAC address from the first Receive Address Register 313 * (RAR0) A reset of the adapter must have been performed prior to calling 314 * this function in order for the MAC address to have been loaded from the 315 * EEPROM into RAR0 316 **/ 317 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 318 { 319 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 320 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 321 } 322 323 /** 324 * ixgbe_get_san_mac_addr - Get SAN MAC address 325 * @hw: pointer to hardware structure 326 * @san_mac_addr: SAN MAC address 327 * 328 * Reads the SAN MAC address from the EEPROM, if it's available. This is 329 * per-port, so set_lan_id() must be called before reading the addresses. 330 **/ 331 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 332 { 333 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 334 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 335 } 336 337 /** 338 * ixgbe_set_san_mac_addr - Write a SAN MAC address 339 * @hw: pointer to hardware structure 340 * @san_mac_addr: SAN MAC address 341 * 342 * Writes A SAN MAC address to the EEPROM. 343 **/ 344 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 345 { 346 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 347 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 348 } 349 350 /** 351 * ixgbe_get_device_caps - Get additional device capabilities 352 * @hw: pointer to hardware structure 353 * @device_caps: the EEPROM word for device capabilities 354 * 355 * Reads the extra device capabilities from the EEPROM 356 **/ 357 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 358 { 359 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 360 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 361 } 362 363 /** 364 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 365 * @hw: pointer to hardware structure 366 * @wwnn_prefix: the alternative WWNN prefix 367 * @wwpn_prefix: the alternative WWPN prefix 368 * 369 * This function will read the EEPROM from the alternative SAN MAC address 370 * block to check the support for the alternative WWNN/WWPN prefix support. 371 **/ 372 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 373 u16 *wwpn_prefix) 374 { 375 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 376 (hw, wwnn_prefix, wwpn_prefix), 377 IXGBE_NOT_IMPLEMENTED); 378 } 379 380 /** 381 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 382 * @hw: pointer to hardware structure 383 * @bs: the fcoe boot status 384 * 385 * This function will read the FCOE boot status from the iSCSI FCOE block 386 **/ 387 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 388 { 389 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 390 (hw, bs), 391 IXGBE_NOT_IMPLEMENTED); 392 } 393 394 /** 395 * ixgbe_get_bus_info - Set PCI bus info 396 * @hw: pointer to hardware structure 397 * 398 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 399 **/ 400 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 401 { 402 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 403 IXGBE_NOT_IMPLEMENTED); 404 } 405 406 /** 407 * ixgbe_get_num_of_tx_queues - Get Tx queues 408 * @hw: pointer to hardware structure 409 * 410 * Returns the number of transmit queues for the given adapter. 411 **/ 412 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 413 { 414 return hw->mac.max_tx_queues; 415 } 416 417 /** 418 * ixgbe_get_num_of_rx_queues - Get Rx queues 419 * @hw: pointer to hardware structure 420 * 421 * Returns the number of receive queues for the given adapter. 422 **/ 423 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 424 { 425 return hw->mac.max_rx_queues; 426 } 427 428 /** 429 * ixgbe_stop_adapter - Disable Rx/Tx units 430 * @hw: pointer to hardware structure 431 * 432 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 433 * disables transmit and receive units. The adapter_stopped flag is used by 434 * the shared code and drivers to determine if the adapter is in a stopped 435 * state and should not touch the hardware. 436 **/ 437 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 438 { 439 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 440 IXGBE_NOT_IMPLEMENTED); 441 } 442 443 /** 444 * ixgbe_read_pba_string - Reads part number string from EEPROM 445 * @hw: pointer to hardware structure 446 * @pba_num: stores the part number string from the EEPROM 447 * @pba_num_size: part number string buffer length 448 * 449 * Reads the part number string from the EEPROM. 450 **/ 451 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 452 { 453 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 454 } 455 456 /** 457 * ixgbe_read_pba_num - Reads part number from EEPROM 458 * @hw: pointer to hardware structure 459 * @pba_num: stores the part number from the EEPROM 460 * 461 * Reads the part number from the EEPROM. 462 **/ 463 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 464 { 465 return ixgbe_read_pba_num_generic(hw, pba_num); 466 } 467 468 /** 469 * ixgbe_identify_phy - Get PHY type 470 * @hw: pointer to hardware structure 471 * 472 * Determines the physical layer module found on the current adapter. 473 **/ 474 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 475 { 476 s32 status = IXGBE_SUCCESS; 477 478 if (hw->phy.type == ixgbe_phy_unknown) { 479 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 480 IXGBE_NOT_IMPLEMENTED); 481 } 482 483 return status; 484 } 485 486 /** 487 * ixgbe_reset_phy - Perform a PHY reset 488 * @hw: pointer to hardware structure 489 **/ 490 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 491 { 492 s32 status = IXGBE_SUCCESS; 493 494 if (hw->phy.type == ixgbe_phy_unknown) { 495 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 496 status = IXGBE_ERR_PHY; 497 } 498 499 if (status == IXGBE_SUCCESS) { 500 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 501 IXGBE_NOT_IMPLEMENTED); 502 } 503 return status; 504 } 505 506 /** 507 * ixgbe_get_phy_firmware_version - 508 * @hw: pointer to hardware structure 509 * @firmware_version: pointer to firmware version 510 **/ 511 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 512 { 513 s32 status = IXGBE_SUCCESS; 514 515 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 516 (hw, firmware_version), 517 IXGBE_NOT_IMPLEMENTED); 518 return status; 519 } 520 521 /** 522 * ixgbe_read_phy_reg - Read PHY register 523 * @hw: pointer to hardware structure 524 * @reg_addr: 32 bit address of PHY register to read 525 * @device_type: type of device you want to communicate with 526 * @phy_data: Pointer to read data from PHY register 527 * 528 * Reads a value from a specified PHY register 529 **/ 530 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 531 u16 *phy_data) 532 { 533 if (hw->phy.id == 0) 534 ixgbe_identify_phy(hw); 535 536 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 537 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 538 } 539 540 /** 541 * ixgbe_write_phy_reg - Write PHY register 542 * @hw: pointer to hardware structure 543 * @reg_addr: 32 bit PHY register to write 544 * @device_type: type of device you want to communicate with 545 * @phy_data: Data to write to the PHY register 546 * 547 * Writes a value to specified PHY register 548 **/ 549 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 550 u16 phy_data) 551 { 552 if (hw->phy.id == 0) 553 ixgbe_identify_phy(hw); 554 555 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 556 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 557 } 558 559 /** 560 * ixgbe_setup_phy_link - Restart PHY autoneg 561 * @hw: pointer to hardware structure 562 * 563 * Restart autonegotiation and PHY and waits for completion. 564 **/ 565 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 566 { 567 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 568 IXGBE_NOT_IMPLEMENTED); 569 } 570 571 /** 572 * ixgbe_setup_internal_phy - Configure integrated PHY 573 * @hw: pointer to hardware structure 574 * 575 * Reconfigure the integrated PHY in order to enable talk to the external PHY. 576 * Returns success if not implemented, since nothing needs to be done in this 577 * case. 578 */ 579 s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw) 580 { 581 return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw), 582 IXGBE_SUCCESS); 583 } 584 585 /** 586 * ixgbe_check_phy_link - Determine link and speed status 587 * @hw: pointer to hardware structure 588 * @speed: link speed 589 * @link_up: true when link is up 590 * 591 * Reads a PHY register to determine if link is up and the current speed for 592 * the PHY. 593 **/ 594 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 595 bool *link_up) 596 { 597 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 598 link_up), IXGBE_NOT_IMPLEMENTED); 599 } 600 601 /** 602 * ixgbe_setup_phy_link_speed - Set auto advertise 603 * @hw: pointer to hardware structure 604 * @speed: new link speed 605 * @autoneg_wait_to_complete: true when waiting for completion is needed 606 * 607 * Sets the auto advertised capabilities 608 **/ 609 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 610 bool autoneg_wait_to_complete) 611 { 612 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 613 autoneg_wait_to_complete), 614 IXGBE_NOT_IMPLEMENTED); 615 } 616 617 /** 618 * ixgbe_set_phy_power - Control the phy power state 619 * @hw: pointer to hardware structure 620 * @on: true for on, false for off 621 */ 622 s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on) 623 { 624 return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on), 625 IXGBE_NOT_IMPLEMENTED); 626 } 627 628 /** 629 * ixgbe_check_link - Get link and speed status 630 * @hw: pointer to hardware structure 631 * @speed: pointer to link speed 632 * @link_up: true when link is up 633 * @link_up_wait_to_complete: bool used to wait for link up or not 634 * 635 * Reads the links register to determine if link is up and the current speed 636 **/ 637 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 638 bool *link_up, bool link_up_wait_to_complete) 639 { 640 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 641 link_up, link_up_wait_to_complete), 642 IXGBE_NOT_IMPLEMENTED); 643 } 644 645 /** 646 * ixgbe_disable_tx_laser - Disable Tx laser 647 * @hw: pointer to hardware structure 648 * 649 * If the driver needs to disable the laser on SFI optics. 650 **/ 651 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 652 { 653 if (hw->mac.ops.disable_tx_laser) 654 hw->mac.ops.disable_tx_laser(hw); 655 } 656 657 /** 658 * ixgbe_enable_tx_laser - Enable Tx laser 659 * @hw: pointer to hardware structure 660 * 661 * If the driver needs to enable the laser on SFI optics. 662 **/ 663 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 664 { 665 if (hw->mac.ops.enable_tx_laser) 666 hw->mac.ops.enable_tx_laser(hw); 667 } 668 669 /** 670 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 671 * @hw: pointer to hardware structure 672 * 673 * When the driver changes the link speeds that it can support then 674 * flap the tx laser to alert the link partner to start autotry 675 * process on its end. 676 **/ 677 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 678 { 679 if (hw->mac.ops.flap_tx_laser) 680 hw->mac.ops.flap_tx_laser(hw); 681 } 682 683 /** 684 * ixgbe_setup_link - Set link speed 685 * @hw: pointer to hardware structure 686 * @speed: new link speed 687 * @autoneg_wait_to_complete: true when waiting for completion is needed 688 * 689 * Configures link settings. Restarts the link. 690 * Performs autonegotiation if needed. 691 **/ 692 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 693 bool autoneg_wait_to_complete) 694 { 695 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 696 autoneg_wait_to_complete), 697 IXGBE_NOT_IMPLEMENTED); 698 } 699 700 /** 701 * ixgbe_setup_mac_link - Set link speed 702 * @hw: pointer to hardware structure 703 * @speed: new link speed 704 * @autoneg_wait_to_complete: true when waiting for completion is needed 705 * 706 * Configures link settings. Restarts the link. 707 * Performs autonegotiation if needed. 708 **/ 709 s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 710 bool autoneg_wait_to_complete) 711 { 712 return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed, 713 autoneg_wait_to_complete), 714 IXGBE_NOT_IMPLEMENTED); 715 } 716 717 /** 718 * ixgbe_get_link_capabilities - Returns link capabilities 719 * @hw: pointer to hardware structure 720 * @speed: link speed capabilities 721 * @autoneg: true when autoneg or autotry is enabled 722 * 723 * Determines the link capabilities of the current configuration. 724 **/ 725 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 726 bool *autoneg) 727 { 728 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 729 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 730 } 731 732 /** 733 * ixgbe_led_on - Turn on LEDs 734 * @hw: pointer to hardware structure 735 * @index: led number to turn on 736 * 737 * Turns on the software controllable LEDs. 738 **/ 739 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 740 { 741 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 742 IXGBE_NOT_IMPLEMENTED); 743 } 744 745 /** 746 * ixgbe_led_off - Turn off LEDs 747 * @hw: pointer to hardware structure 748 * @index: led number to turn off 749 * 750 * Turns off the software controllable LEDs. 751 **/ 752 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 753 { 754 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 755 IXGBE_NOT_IMPLEMENTED); 756 } 757 758 /** 759 * ixgbe_blink_led_start - Blink LEDs 760 * @hw: pointer to hardware structure 761 * @index: led number to blink 762 * 763 * Blink LED based on index. 764 **/ 765 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 766 { 767 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 768 IXGBE_NOT_IMPLEMENTED); 769 } 770 771 /** 772 * ixgbe_blink_led_stop - Stop blinking LEDs 773 * @hw: pointer to hardware structure 774 * @index: led number to stop 775 * 776 * Stop blinking LED based on index. 777 **/ 778 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 779 { 780 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 781 IXGBE_NOT_IMPLEMENTED); 782 } 783 784 /** 785 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 786 * @hw: pointer to hardware structure 787 * 788 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 789 * ixgbe_hw struct in order to set up EEPROM access. 790 **/ 791 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 792 { 793 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 794 IXGBE_NOT_IMPLEMENTED); 795 } 796 797 798 /** 799 * ixgbe_write_eeprom - Write word to EEPROM 800 * @hw: pointer to hardware structure 801 * @offset: offset within the EEPROM to be written to 802 * @data: 16 bit word to be written to the EEPROM 803 * 804 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 805 * called after this function, the EEPROM will most likely contain an 806 * invalid checksum. 807 **/ 808 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 809 { 810 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 811 IXGBE_NOT_IMPLEMENTED); 812 } 813 814 /** 815 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 816 * @hw: pointer to hardware structure 817 * @offset: offset within the EEPROM to be written to 818 * @data: 16 bit word(s) to be written to the EEPROM 819 * @words: number of words 820 * 821 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 822 * called after this function, the EEPROM will most likely contain an 823 * invalid checksum. 824 **/ 825 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 826 u16 *data) 827 { 828 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 829 (hw, offset, words, data), 830 IXGBE_NOT_IMPLEMENTED); 831 } 832 833 /** 834 * ixgbe_read_eeprom - Read word from EEPROM 835 * @hw: pointer to hardware structure 836 * @offset: offset within the EEPROM to be read 837 * @data: read 16 bit value from EEPROM 838 * 839 * Reads 16 bit value from EEPROM 840 **/ 841 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 842 { 843 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 844 IXGBE_NOT_IMPLEMENTED); 845 } 846 847 /** 848 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 849 * @hw: pointer to hardware structure 850 * @offset: offset within the EEPROM to be read 851 * @data: read 16 bit word(s) from EEPROM 852 * @words: number of words 853 * 854 * Reads 16 bit word(s) from EEPROM 855 **/ 856 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 857 u16 words, u16 *data) 858 { 859 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 860 (hw, offset, words, data), 861 IXGBE_NOT_IMPLEMENTED); 862 } 863 864 /** 865 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 866 * @hw: pointer to hardware structure 867 * @checksum_val: calculated checksum 868 * 869 * Performs checksum calculation and validates the EEPROM checksum 870 **/ 871 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 872 { 873 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 874 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 875 } 876 877 /** 878 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 879 * @hw: pointer to hardware structure 880 **/ 881 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 882 { 883 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 884 IXGBE_NOT_IMPLEMENTED); 885 } 886 887 /** 888 * ixgbe_insert_mac_addr - Find a RAR for this mac address 889 * @hw: pointer to hardware structure 890 * @addr: Address to put into receive address register 891 * @vmdq: VMDq pool to assign 892 * 893 * Puts an ethernet address into a receive address register, or 894 * finds the rar that it is aleady in; adds to the pool list 895 **/ 896 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 897 { 898 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 899 (hw, addr, vmdq), 900 IXGBE_NOT_IMPLEMENTED); 901 } 902 903 /** 904 * ixgbe_set_rar - Set Rx address register 905 * @hw: pointer to hardware structure 906 * @index: Receive address register to write 907 * @addr: Address to put into receive address register 908 * @vmdq: VMDq "set" 909 * @enable_addr: set flag that address is active 910 * 911 * Puts an ethernet address into a receive address register. 912 **/ 913 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 914 u32 enable_addr) 915 { 916 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 917 enable_addr), IXGBE_NOT_IMPLEMENTED); 918 } 919 920 /** 921 * ixgbe_clear_rar - Clear Rx address register 922 * @hw: pointer to hardware structure 923 * @index: Receive address register to write 924 * 925 * Puts an ethernet address into a receive address register. 926 **/ 927 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 928 { 929 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 930 IXGBE_NOT_IMPLEMENTED); 931 } 932 933 /** 934 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 935 * @hw: pointer to hardware structure 936 * @rar: receive address register index to associate with VMDq index 937 * @vmdq: VMDq set or pool index 938 **/ 939 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 940 { 941 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 942 IXGBE_NOT_IMPLEMENTED); 943 944 } 945 946 /** 947 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address 948 * @hw: pointer to hardware structure 949 * @vmdq: VMDq default pool index 950 **/ 951 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) 952 { 953 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac, 954 (hw, vmdq), IXGBE_NOT_IMPLEMENTED); 955 } 956 957 /** 958 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 959 * @hw: pointer to hardware structure 960 * @rar: receive address register index to disassociate with VMDq index 961 * @vmdq: VMDq set or pool index 962 **/ 963 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 964 { 965 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 966 IXGBE_NOT_IMPLEMENTED); 967 } 968 969 /** 970 * ixgbe_init_rx_addrs - Initializes receive address filters. 971 * @hw: pointer to hardware structure 972 * 973 * Places the MAC address in receive address register 0 and clears the rest 974 * of the receive address registers. Clears the multicast table. Assumes 975 * the receiver is in reset when the routine is called. 976 **/ 977 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 978 { 979 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 980 IXGBE_NOT_IMPLEMENTED); 981 } 982 983 /** 984 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 985 * @hw: pointer to hardware structure 986 **/ 987 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 988 { 989 return hw->mac.num_rar_entries; 990 } 991 992 /** 993 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 994 * @hw: pointer to hardware structure 995 * @addr_list: the list of new multicast addresses 996 * @addr_count: number of addresses 997 * @func: iterator function to walk the multicast address list 998 * 999 * The given list replaces any existing list. Clears the secondary addrs from 1000 * receive address registers. Uses unused receive address registers for the 1001 * first secondary addresses, and falls back to promiscuous mode as needed. 1002 **/ 1003 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 1004 u32 addr_count, ixgbe_mc_addr_itr func) 1005 { 1006 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 1007 addr_list, addr_count, func), 1008 IXGBE_NOT_IMPLEMENTED); 1009 } 1010 1011 /** 1012 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 1013 * @hw: pointer to hardware structure 1014 * @mc_addr_list: the list of new multicast addresses 1015 * @mc_addr_count: number of addresses 1016 * @func: iterator function to walk the multicast address list 1017 * @clear: flag, when set clears the table beforehand 1018 * 1019 * The given list replaces any existing list. Clears the MC addrs from receive 1020 * address registers and the multicast table. Uses unused receive address 1021 * registers for the first multicast addresses, and hashes the rest into the 1022 * multicast table. 1023 **/ 1024 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 1025 u32 mc_addr_count, ixgbe_mc_addr_itr func, 1026 bool clear) 1027 { 1028 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 1029 mc_addr_list, mc_addr_count, func, clear), 1030 IXGBE_NOT_IMPLEMENTED); 1031 } 1032 1033 /** 1034 * ixgbe_enable_mc - Enable multicast address in RAR 1035 * @hw: pointer to hardware structure 1036 * 1037 * Enables multicast address in RAR and the use of the multicast hash table. 1038 **/ 1039 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 1040 { 1041 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 1042 IXGBE_NOT_IMPLEMENTED); 1043 } 1044 1045 /** 1046 * ixgbe_disable_mc - Disable multicast address in RAR 1047 * @hw: pointer to hardware structure 1048 * 1049 * Disables multicast address in RAR and the use of the multicast hash table. 1050 **/ 1051 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 1052 { 1053 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 1054 IXGBE_NOT_IMPLEMENTED); 1055 } 1056 1057 /** 1058 * ixgbe_clear_vfta - Clear VLAN filter table 1059 * @hw: pointer to hardware structure 1060 * 1061 * Clears the VLAN filer table, and the VMDq index associated with the filter 1062 **/ 1063 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 1064 { 1065 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 1066 IXGBE_NOT_IMPLEMENTED); 1067 } 1068 1069 /** 1070 * ixgbe_set_vfta - Set VLAN filter table 1071 * @hw: pointer to hardware structure 1072 * @vlan: VLAN id to write to VLAN filter 1073 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1074 * @vlan_on: boolean flag to turn on/off VLAN 1075 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1076 * 1077 * Turn on/off specified VLAN in the VLAN filter table. 1078 **/ 1079 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1080 bool vlvf_bypass) 1081 { 1082 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 1083 vlan_on, vlvf_bypass), IXGBE_NOT_IMPLEMENTED); 1084 } 1085 1086 /** 1087 * ixgbe_set_vlvf - Set VLAN Pool Filter 1088 * @hw: pointer to hardware structure 1089 * @vlan: VLAN id to write to VLAN filter 1090 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1091 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 1092 * @vfta_delta: pointer to the difference between the current value of VFTA 1093 * and the desired value 1094 * @vfta: the desired value of the VFTA 1095 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1096 * 1097 * Turn on/off specified bit in VLVF table. 1098 **/ 1099 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1100 u32 *vfta_delta, u32 vfta, bool vlvf_bypass) 1101 { 1102 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 1103 vlan_on, vfta_delta, vfta, vlvf_bypass), 1104 IXGBE_NOT_IMPLEMENTED); 1105 } 1106 1107 /** 1108 * ixgbe_fc_enable - Enable flow control 1109 * @hw: pointer to hardware structure 1110 * 1111 * Configures the flow control settings based on SW configuration. 1112 **/ 1113 s32 ixgbe_fc_enable(struct ixgbe_hw *hw) 1114 { 1115 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), 1116 IXGBE_NOT_IMPLEMENTED); 1117 } 1118 1119 /** 1120 * ixgbe_setup_fc - Set up flow control 1121 * @hw: pointer to hardware structure 1122 * 1123 * Called at init time to set up flow control. 1124 **/ 1125 s32 ixgbe_setup_fc(struct ixgbe_hw *hw) 1126 { 1127 return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw), 1128 IXGBE_NOT_IMPLEMENTED); 1129 } 1130 1131 /** 1132 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 1133 * @hw: pointer to hardware structure 1134 * @maj: driver major number to be sent to firmware 1135 * @min: driver minor number to be sent to firmware 1136 * @build: driver build number to be sent to firmware 1137 * @ver: driver version number to be sent to firmware 1138 * @len: length of driver_ver string 1139 * @driver_ver: driver string 1140 **/ 1141 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, 1142 u8 ver, u16 len, char *driver_ver) 1143 { 1144 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min, 1145 build, ver, len, driver_ver), 1146 IXGBE_NOT_IMPLEMENTED); 1147 } 1148 1149 1150 /** 1151 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data 1152 * @hw: pointer to hardware structure 1153 * 1154 * Updates the temperatures in mac.thermal_sensor_data 1155 **/ 1156 s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw) 1157 { 1158 return ixgbe_call_func(hw, hw->mac.ops.get_thermal_sensor_data, (hw), 1159 IXGBE_NOT_IMPLEMENTED); 1160 } 1161 1162 /** 1163 * ixgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds 1164 * @hw: pointer to hardware structure 1165 * 1166 * Inits the thermal sensor thresholds according to the NVM map 1167 **/ 1168 s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw) 1169 { 1170 return ixgbe_call_func(hw, hw->mac.ops.init_thermal_sensor_thresh, (hw), 1171 IXGBE_NOT_IMPLEMENTED); 1172 } 1173 1174 /** 1175 * ixgbe_dmac_config - Configure DMA Coalescing registers. 1176 * @hw: pointer to hardware structure 1177 * 1178 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1179 * When disabling dmac, dmac enable dmac bit is cleared. 1180 **/ 1181 s32 ixgbe_dmac_config(struct ixgbe_hw *hw) 1182 { 1183 return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw), 1184 IXGBE_NOT_IMPLEMENTED); 1185 } 1186 1187 /** 1188 * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers. 1189 * @hw: pointer to hardware structure 1190 * 1191 * Disables dmac, updates per TC settings, and then enable dmac. 1192 **/ 1193 s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw) 1194 { 1195 return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw), 1196 IXGBE_NOT_IMPLEMENTED); 1197 } 1198 1199 /** 1200 * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers. 1201 * @hw: pointer to hardware structure 1202 * 1203 * Configure DMA coalescing threshold per TC and set high priority bit for 1204 * FCOE TC. The dmac enable bit must be cleared before configuring. 1205 **/ 1206 s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw) 1207 { 1208 return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw), 1209 IXGBE_NOT_IMPLEMENTED); 1210 } 1211 1212 /** 1213 * ixgbe_setup_eee - Enable/disable EEE support 1214 * @hw: pointer to the HW structure 1215 * @enable_eee: boolean flag to enable EEE 1216 * 1217 * Enable/disable EEE based on enable_ee flag. 1218 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 1219 * are modified. 1220 * 1221 **/ 1222 s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee) 1223 { 1224 return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee), 1225 IXGBE_NOT_IMPLEMENTED); 1226 } 1227 1228 /** 1229 * ixgbe_set_source_address_pruning - Enable/Disable source address pruning 1230 * @hw: pointer to hardware structure 1231 * @enable: enable or disable source address pruning 1232 * @pool: Rx pool - Rx pool to toggle source address pruning 1233 **/ 1234 void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, 1235 unsigned int pool) 1236 { 1237 if (hw->mac.ops.set_source_address_pruning) 1238 hw->mac.ops.set_source_address_pruning(hw, enable, pool); 1239 } 1240 1241 /** 1242 * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing 1243 * @hw: pointer to hardware structure 1244 * @enable: enable or disable switch for Ethertype anti-spoofing 1245 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1246 * 1247 **/ 1248 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 1249 { 1250 if (hw->mac.ops.set_ethertype_anti_spoofing) 1251 hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf); 1252 } 1253 1254 /** 1255 * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register 1256 * @hw: pointer to hardware structure 1257 * @reg_addr: 32 bit address of PHY register to read 1258 * @device_type: type of device you want to communicate with 1259 * @phy_data: Pointer to read data from PHY register 1260 * 1261 * Reads a value from a specified PHY register 1262 **/ 1263 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1264 u32 device_type, u32 *phy_data) 1265 { 1266 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, 1267 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1268 } 1269 1270 /** 1271 * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband 1272 * @hw: pointer to hardware structure 1273 * @reg_addr: 32 bit PHY register to write 1274 * @device_type: type of device you want to communicate with 1275 * @phy_data: Data to write to the PHY register 1276 * 1277 * Writes a value to specified PHY register 1278 **/ 1279 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1280 u32 device_type, u32 phy_data) 1281 { 1282 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, 1283 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1284 } 1285 1286 /** 1287 * ixgbe_disable_mdd - Disable malicious driver detection 1288 * @hw: pointer to hardware structure 1289 * 1290 **/ 1291 void ixgbe_disable_mdd(struct ixgbe_hw *hw) 1292 { 1293 if (hw->mac.ops.disable_mdd) 1294 hw->mac.ops.disable_mdd(hw); 1295 } 1296 1297 /** 1298 * ixgbe_enable_mdd - Enable malicious driver detection 1299 * @hw: pointer to hardware structure 1300 * 1301 **/ 1302 void ixgbe_enable_mdd(struct ixgbe_hw *hw) 1303 { 1304 if (hw->mac.ops.enable_mdd) 1305 hw->mac.ops.enable_mdd(hw); 1306 } 1307 1308 /** 1309 * ixgbe_mdd_event - Handle malicious driver detection event 1310 * @hw: pointer to hardware structure 1311 * @vf_bitmap: vf bitmap of malicious vfs 1312 * 1313 **/ 1314 void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap) 1315 { 1316 if (hw->mac.ops.mdd_event) 1317 hw->mac.ops.mdd_event(hw, vf_bitmap); 1318 } 1319 1320 /** 1321 * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver 1322 * detection event 1323 * @hw: pointer to hardware structure 1324 * @vf: vf index 1325 * 1326 **/ 1327 void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf) 1328 { 1329 if (hw->mac.ops.restore_mdd_vf) 1330 hw->mac.ops.restore_mdd_vf(hw, vf); 1331 } 1332 1333 /** 1334 * ixgbe_enter_lplu - Transition to low power states 1335 * @hw: pointer to hardware structure 1336 * 1337 * Configures Low Power Link Up on transition to low power states 1338 * (from D0 to non-D0). 1339 **/ 1340 s32 ixgbe_enter_lplu(struct ixgbe_hw *hw) 1341 { 1342 return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw), 1343 IXGBE_NOT_IMPLEMENTED); 1344 } 1345 1346 /** 1347 * ixgbe_handle_lasi - Handle external Base T PHY interrupt 1348 * @hw: pointer to hardware structure 1349 * 1350 * Handle external Base T PHY interrupt. If high temperature 1351 * failure alarm then return error, else if link status change 1352 * then setup internal/external PHY link 1353 * 1354 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1355 * failure alarm, else return PHY access status. 1356 */ 1357 s32 ixgbe_handle_lasi(struct ixgbe_hw *hw) 1358 { 1359 return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw), 1360 IXGBE_NOT_IMPLEMENTED); 1361 } 1362 1363 /** 1364 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 1365 * @hw: pointer to hardware structure 1366 * @reg: analog register to read 1367 * @val: read value 1368 * 1369 * Performs write operation to analog register specified. 1370 **/ 1371 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 1372 { 1373 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1374 val), IXGBE_NOT_IMPLEMENTED); 1375 } 1376 1377 /** 1378 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1379 * @hw: pointer to hardware structure 1380 * @reg: analog register to write 1381 * @val: value to write 1382 * 1383 * Performs write operation to Atlas analog register specified. 1384 **/ 1385 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1386 { 1387 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1388 val), IXGBE_NOT_IMPLEMENTED); 1389 } 1390 1391 /** 1392 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1393 * @hw: pointer to hardware structure 1394 * 1395 * Initializes the Unicast Table Arrays to zero on device load. This 1396 * is part of the Rx init addr execution path. 1397 **/ 1398 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1399 { 1400 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1401 IXGBE_NOT_IMPLEMENTED); 1402 } 1403 1404 /** 1405 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1406 * @hw: pointer to hardware structure 1407 * @byte_offset: byte offset to read 1408 * @dev_addr: I2C bus address to read from 1409 * @data: value read 1410 * 1411 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1412 **/ 1413 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1414 u8 *data) 1415 { 1416 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1417 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1418 } 1419 1420 /** 1421 * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address 1422 * @hw: pointer to hardware structure 1423 * @byte_offset: byte offset to read 1424 * @dev_addr: I2C bus address to read from 1425 * @data: value read 1426 * 1427 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1428 **/ 1429 s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1430 u8 dev_addr, u8 *data) 1431 { 1432 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked, 1433 (hw, byte_offset, dev_addr, data), 1434 IXGBE_NOT_IMPLEMENTED); 1435 } 1436 1437 /** 1438 * ixgbe_read_link - Perform read operation on link device 1439 * @hw: pointer to the hardware structure 1440 * @addr: bus address to read from 1441 * @reg: device register to read from 1442 * @val: pointer to location to receive read value 1443 * 1444 * Returns an error code on error. 1445 */ 1446 s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1447 { 1448 return ixgbe_call_func(hw, hw->link.ops.read_link, (hw, addr, 1449 reg, val), IXGBE_NOT_IMPLEMENTED); 1450 } 1451 1452 /** 1453 * ixgbe_read_link_unlocked - Perform read operation on link device 1454 * @hw: pointer to the hardware structure 1455 * @addr: bus address to read from 1456 * @reg: device register to read from 1457 * @val: pointer to location to receive read value 1458 * 1459 * Returns an error code on error. 1460 **/ 1461 s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1462 { 1463 return ixgbe_call_func(hw, hw->link.ops.read_link_unlocked, 1464 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1465 } 1466 1467 /** 1468 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1469 * @hw: pointer to hardware structure 1470 * @byte_offset: byte offset to write 1471 * @dev_addr: I2C bus address to write to 1472 * @data: value to write 1473 * 1474 * Performs byte write operation to SFP module's EEPROM over I2C interface 1475 * at a specified device address. 1476 **/ 1477 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1478 u8 data) 1479 { 1480 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1481 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1482 } 1483 1484 /** 1485 * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1486 * @hw: pointer to hardware structure 1487 * @byte_offset: byte offset to write 1488 * @dev_addr: I2C bus address to write to 1489 * @data: value to write 1490 * 1491 * Performs byte write operation to SFP module's EEPROM over I2C interface 1492 * at a specified device address. 1493 **/ 1494 s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1495 u8 dev_addr, u8 data) 1496 { 1497 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked, 1498 (hw, byte_offset, dev_addr, data), 1499 IXGBE_NOT_IMPLEMENTED); 1500 } 1501 1502 /** 1503 * ixgbe_write_link - Perform write operation on link device 1504 * @hw: pointer to the hardware structure 1505 * @addr: bus address to write to 1506 * @reg: device register to write to 1507 * @val: value to write 1508 * 1509 * Returns an error code on error. 1510 */ 1511 s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1512 { 1513 return ixgbe_call_func(hw, hw->link.ops.write_link, 1514 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1515 } 1516 1517 /** 1518 * ixgbe_write_link_unlocked - Perform write operation on link device 1519 * @hw: pointer to the hardware structure 1520 * @addr: bus address to write to 1521 * @reg: device register to write to 1522 * @val: value to write 1523 * 1524 * Returns an error code on error. 1525 **/ 1526 s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1527 { 1528 return ixgbe_call_func(hw, hw->link.ops.write_link_unlocked, 1529 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1530 } 1531 1532 /** 1533 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1534 * @hw: pointer to hardware structure 1535 * @byte_offset: EEPROM byte offset to write 1536 * @eeprom_data: value to write 1537 * 1538 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1539 **/ 1540 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1541 u8 byte_offset, u8 eeprom_data) 1542 { 1543 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1544 (hw, byte_offset, eeprom_data), 1545 IXGBE_NOT_IMPLEMENTED); 1546 } 1547 1548 /** 1549 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1550 * @hw: pointer to hardware structure 1551 * @byte_offset: EEPROM byte offset to read 1552 * @eeprom_data: value read 1553 * 1554 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1555 **/ 1556 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1557 { 1558 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1559 (hw, byte_offset, eeprom_data), 1560 IXGBE_NOT_IMPLEMENTED); 1561 } 1562 1563 /** 1564 * ixgbe_get_supported_physical_layer - Returns physical layer type 1565 * @hw: pointer to hardware structure 1566 * 1567 * Determines physical layer capabilities of the current configuration. 1568 **/ 1569 u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1570 { 1571 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1572 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1573 } 1574 1575 /** 1576 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics 1577 * @hw: pointer to hardware structure 1578 * @regval: bitfield to write to the Rx DMA register 1579 * 1580 * Enables the Rx DMA unit of the device. 1581 **/ 1582 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1583 { 1584 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1585 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1586 } 1587 1588 /** 1589 * ixgbe_disable_sec_rx_path - Stops the receive data path 1590 * @hw: pointer to hardware structure 1591 * 1592 * Stops the receive data path. 1593 **/ 1594 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1595 { 1596 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1597 (hw), IXGBE_NOT_IMPLEMENTED); 1598 } 1599 1600 /** 1601 * ixgbe_enable_sec_rx_path - Enables the receive data path 1602 * @hw: pointer to hardware structure 1603 * 1604 * Enables the receive data path. 1605 **/ 1606 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1607 { 1608 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1609 (hw), IXGBE_NOT_IMPLEMENTED); 1610 } 1611 1612 /** 1613 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1614 * @hw: pointer to hardware structure 1615 * @mask: Mask to specify which semaphore to acquire 1616 * 1617 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1618 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1619 **/ 1620 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1621 { 1622 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1623 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1624 } 1625 1626 /** 1627 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1628 * @hw: pointer to hardware structure 1629 * @mask: Mask to specify which semaphore to release 1630 * 1631 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1632 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1633 **/ 1634 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1635 { 1636 if (hw->mac.ops.release_swfw_sync) 1637 hw->mac.ops.release_swfw_sync(hw, mask); 1638 } 1639 1640 /** 1641 * ixgbe_init_swfw_semaphore - Clean up SWFW semaphore 1642 * @hw: pointer to hardware structure 1643 * 1644 * Attempts to acquire the SWFW semaphore through SW_FW_SYNC register. 1645 * Regardless of whether is succeeds or not it then release the semaphore. 1646 * This is function is called to recover from catastrophic failures that 1647 * may have left the semaphore locked. 1648 **/ 1649 void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw) 1650 { 1651 if (hw->mac.ops.init_swfw_sync) 1652 hw->mac.ops.init_swfw_sync(hw); 1653 } 1654 1655 1656 void ixgbe_disable_rx(struct ixgbe_hw *hw) 1657 { 1658 if (hw->mac.ops.disable_rx) 1659 hw->mac.ops.disable_rx(hw); 1660 } 1661 1662 void ixgbe_enable_rx(struct ixgbe_hw *hw) 1663 { 1664 if (hw->mac.ops.enable_rx) 1665 hw->mac.ops.enable_rx(hw); 1666 } 1667 1668 /** 1669 * ixgbe_set_rate_select_speed - Set module link speed 1670 * @hw: pointer to hardware structure 1671 * @speed: link speed to set 1672 * 1673 * Set module link speed via the rate select. 1674 */ 1675 void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 1676 { 1677 if (hw->mac.ops.set_rate_select_speed) 1678 hw->mac.ops.set_rate_select_speed(hw, speed); 1679 } 1680