1 /******************************************************************************* 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 #include "ixgbe_api.h" 35 #include "ixgbe_common.h" 36 37 /** 38 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg 39 * @hw: pointer to hardware structure 40 * @map: pointer to u8 arr for returning map 41 * 42 * Read the rtrup2tc HW register and resolve its content into map 43 **/ 44 void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map) 45 { 46 if (hw->mac.ops.get_rtrup2tc) 47 hw->mac.ops.get_rtrup2tc(hw, map); 48 } 49 50 /** 51 * ixgbe_init_shared_code - Initialize the shared code 52 * @hw: pointer to hardware structure 53 * 54 * This will assign function pointers and assign the MAC type and PHY code. 55 * Does not touch the hardware. This function must be called prior to any 56 * other function in the shared code. The ixgbe_hw structure should be 57 * memset to 0 prior to calling this function. The following fields in 58 * hw structure should be filled in prior to calling this function: 59 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 60 * subsystem_vendor_id, and revision_id 61 **/ 62 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 63 { 64 s32 status; 65 66 DEBUGFUNC("ixgbe_init_shared_code"); 67 68 /* 69 * Set the mac type 70 */ 71 ixgbe_set_mac_type(hw); 72 73 switch (hw->mac.type) { 74 case ixgbe_mac_82598EB: 75 status = ixgbe_init_ops_82598(hw); 76 break; 77 case ixgbe_mac_82599EB: 78 status = ixgbe_init_ops_82599(hw); 79 break; 80 case ixgbe_mac_X540: 81 status = ixgbe_init_ops_X540(hw); 82 break; 83 case ixgbe_mac_X550: 84 status = ixgbe_init_ops_X550(hw); 85 break; 86 case ixgbe_mac_X550EM_x: 87 status = ixgbe_init_ops_X550EM(hw); 88 break; 89 case ixgbe_mac_82599_vf: 90 case ixgbe_mac_X540_vf: 91 case ixgbe_mac_X550_vf: 92 case ixgbe_mac_X550EM_x_vf: 93 status = ixgbe_init_ops_vf(hw); 94 break; 95 default: 96 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 97 break; 98 } 99 100 return status; 101 } 102 103 /** 104 * ixgbe_set_mac_type - Sets MAC type 105 * @hw: pointer to the HW structure 106 * 107 * This function sets the mac type of the adapter based on the 108 * vendor ID and device ID stored in the hw structure. 109 **/ 110 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 111 { 112 s32 ret_val = IXGBE_SUCCESS; 113 114 DEBUGFUNC("ixgbe_set_mac_type\n"); 115 116 if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { 117 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 118 "Unsupported vendor id: %x", hw->vendor_id); 119 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 120 } 121 122 switch (hw->device_id) { 123 case IXGBE_DEV_ID_82598: 124 case IXGBE_DEV_ID_82598_BX: 125 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 126 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 127 case IXGBE_DEV_ID_82598AT: 128 case IXGBE_DEV_ID_82598AT2: 129 case IXGBE_DEV_ID_82598EB_CX4: 130 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 131 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 132 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 133 case IXGBE_DEV_ID_82598EB_XF_LR: 134 case IXGBE_DEV_ID_82598EB_SFP_LOM: 135 hw->mac.type = ixgbe_mac_82598EB; 136 break; 137 case IXGBE_DEV_ID_82599_KX4: 138 case IXGBE_DEV_ID_82599_KX4_MEZZ: 139 case IXGBE_DEV_ID_82599_XAUI_LOM: 140 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 141 case IXGBE_DEV_ID_82599_KR: 142 case IXGBE_DEV_ID_82599_SFP: 143 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 144 case IXGBE_DEV_ID_82599_SFP_FCOE: 145 case IXGBE_DEV_ID_82599_SFP_EM: 146 case IXGBE_DEV_ID_82599_SFP_SF2: 147 case IXGBE_DEV_ID_82599_SFP_SF_QP: 148 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 149 case IXGBE_DEV_ID_82599EN_SFP: 150 case IXGBE_DEV_ID_82599_CX4: 151 case IXGBE_DEV_ID_82599_LS: 152 case IXGBE_DEV_ID_82599_T3_LOM: 153 hw->mac.type = ixgbe_mac_82599EB; 154 break; 155 case IXGBE_DEV_ID_82599_VF: 156 case IXGBE_DEV_ID_82599_VF_HV: 157 hw->mac.type = ixgbe_mac_82599_vf; 158 break; 159 case IXGBE_DEV_ID_X540_VF: 160 case IXGBE_DEV_ID_X540_VF_HV: 161 hw->mac.type = ixgbe_mac_X540_vf; 162 break; 163 case IXGBE_DEV_ID_X540T: 164 case IXGBE_DEV_ID_X540T1: 165 hw->mac.type = ixgbe_mac_X540; 166 break; 167 case IXGBE_DEV_ID_X550T: 168 hw->mac.type = ixgbe_mac_X550; 169 break; 170 case IXGBE_DEV_ID_X550EM_X_KX4: 171 case IXGBE_DEV_ID_X550EM_X_KR: 172 case IXGBE_DEV_ID_X550EM_X_10G_T: 173 case IXGBE_DEV_ID_X550EM_X_1G_T: 174 case IXGBE_DEV_ID_X550EM_X_SFP: 175 hw->mac.type = ixgbe_mac_X550EM_x; 176 break; 177 case IXGBE_DEV_ID_X550_VF: 178 case IXGBE_DEV_ID_X550_VF_HV: 179 hw->mac.type = ixgbe_mac_X550_vf; 180 break; 181 case IXGBE_DEV_ID_X550EM_X_VF: 182 case IXGBE_DEV_ID_X550EM_X_VF_HV: 183 hw->mac.type = ixgbe_mac_X550EM_x_vf; 184 break; 185 default: 186 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 187 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 188 "Unsupported device id: %x", 189 hw->device_id); 190 break; 191 } 192 193 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 194 hw->mac.type, ret_val); 195 return ret_val; 196 } 197 198 /** 199 * ixgbe_init_hw - Initialize the hardware 200 * @hw: pointer to hardware structure 201 * 202 * Initialize the hardware by resetting and then starting the hardware 203 **/ 204 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 205 { 206 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 207 IXGBE_NOT_IMPLEMENTED); 208 } 209 210 /** 211 * ixgbe_reset_hw - Performs a hardware reset 212 * @hw: pointer to hardware structure 213 * 214 * Resets the hardware by resetting the transmit and receive units, masks and 215 * clears all interrupts, performs a PHY reset, and performs a MAC reset 216 **/ 217 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 218 { 219 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 220 IXGBE_NOT_IMPLEMENTED); 221 } 222 223 /** 224 * ixgbe_start_hw - Prepares hardware for Rx/Tx 225 * @hw: pointer to hardware structure 226 * 227 * Starts the hardware by filling the bus info structure and media type, 228 * clears all on chip counters, initializes receive address registers, 229 * multicast table, VLAN filter table, calls routine to setup link and 230 * flow control settings, and leaves transmit and receive units disabled 231 * and uninitialized. 232 **/ 233 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 234 { 235 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 236 IXGBE_NOT_IMPLEMENTED); 237 } 238 239 /** 240 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 241 * which is disabled by default in ixgbe_start_hw(); 242 * 243 * @hw: pointer to hardware structure 244 * 245 * Enable relaxed ordering; 246 **/ 247 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 248 { 249 if (hw->mac.ops.enable_relaxed_ordering) 250 hw->mac.ops.enable_relaxed_ordering(hw); 251 } 252 253 /** 254 * ixgbe_clear_hw_cntrs - Clear hardware counters 255 * @hw: pointer to hardware structure 256 * 257 * Clears all hardware statistics counters by reading them from the hardware 258 * Statistics counters are clear on read. 259 **/ 260 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 261 { 262 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 263 IXGBE_NOT_IMPLEMENTED); 264 } 265 266 /** 267 * ixgbe_get_media_type - Get media type 268 * @hw: pointer to hardware structure 269 * 270 * Returns the media type (fiber, copper, backplane) 271 **/ 272 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 273 { 274 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 275 ixgbe_media_type_unknown); 276 } 277 278 /** 279 * ixgbe_get_mac_addr - Get MAC address 280 * @hw: pointer to hardware structure 281 * @mac_addr: Adapter MAC address 282 * 283 * Reads the adapter's MAC address from the first Receive Address Register 284 * (RAR0) A reset of the adapter must have been performed prior to calling 285 * this function in order for the MAC address to have been loaded from the 286 * EEPROM into RAR0 287 **/ 288 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 289 { 290 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 291 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 292 } 293 294 /** 295 * ixgbe_get_san_mac_addr - Get SAN MAC address 296 * @hw: pointer to hardware structure 297 * @san_mac_addr: SAN MAC address 298 * 299 * Reads the SAN MAC address from the EEPROM, if it's available. This is 300 * per-port, so set_lan_id() must be called before reading the addresses. 301 **/ 302 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 303 { 304 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 305 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 306 } 307 308 /** 309 * ixgbe_set_san_mac_addr - Write a SAN MAC address 310 * @hw: pointer to hardware structure 311 * @san_mac_addr: SAN MAC address 312 * 313 * Writes A SAN MAC address to the EEPROM. 314 **/ 315 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 316 { 317 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 318 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 319 } 320 321 /** 322 * ixgbe_get_device_caps - Get additional device capabilities 323 * @hw: pointer to hardware structure 324 * @device_caps: the EEPROM word for device capabilities 325 * 326 * Reads the extra device capabilities from the EEPROM 327 **/ 328 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 329 { 330 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 331 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 332 } 333 334 /** 335 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 336 * @hw: pointer to hardware structure 337 * @wwnn_prefix: the alternative WWNN prefix 338 * @wwpn_prefix: the alternative WWPN prefix 339 * 340 * This function will read the EEPROM from the alternative SAN MAC address 341 * block to check the support for the alternative WWNN/WWPN prefix support. 342 **/ 343 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 344 u16 *wwpn_prefix) 345 { 346 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 347 (hw, wwnn_prefix, wwpn_prefix), 348 IXGBE_NOT_IMPLEMENTED); 349 } 350 351 /** 352 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 353 * @hw: pointer to hardware structure 354 * @bs: the fcoe boot status 355 * 356 * This function will read the FCOE boot status from the iSCSI FCOE block 357 **/ 358 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 359 { 360 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 361 (hw, bs), 362 IXGBE_NOT_IMPLEMENTED); 363 } 364 365 /** 366 * ixgbe_get_bus_info - Set PCI bus info 367 * @hw: pointer to hardware structure 368 * 369 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 370 **/ 371 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 372 { 373 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 374 IXGBE_NOT_IMPLEMENTED); 375 } 376 377 /** 378 * ixgbe_get_num_of_tx_queues - Get Tx queues 379 * @hw: pointer to hardware structure 380 * 381 * Returns the number of transmit queues for the given adapter. 382 **/ 383 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 384 { 385 return hw->mac.max_tx_queues; 386 } 387 388 /** 389 * ixgbe_get_num_of_rx_queues - Get Rx queues 390 * @hw: pointer to hardware structure 391 * 392 * Returns the number of receive queues for the given adapter. 393 **/ 394 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 395 { 396 return hw->mac.max_rx_queues; 397 } 398 399 /** 400 * ixgbe_stop_adapter - Disable Rx/Tx units 401 * @hw: pointer to hardware structure 402 * 403 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 404 * disables transmit and receive units. The adapter_stopped flag is used by 405 * the shared code and drivers to determine if the adapter is in a stopped 406 * state and should not touch the hardware. 407 **/ 408 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 409 { 410 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 411 IXGBE_NOT_IMPLEMENTED); 412 } 413 414 /** 415 * ixgbe_read_pba_string - Reads part number string from EEPROM 416 * @hw: pointer to hardware structure 417 * @pba_num: stores the part number string from the EEPROM 418 * @pba_num_size: part number string buffer length 419 * 420 * Reads the part number string from the EEPROM. 421 **/ 422 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 423 { 424 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 425 } 426 427 /** 428 * ixgbe_read_pba_num - Reads part number from EEPROM 429 * @hw: pointer to hardware structure 430 * @pba_num: stores the part number from the EEPROM 431 * 432 * Reads the part number from the EEPROM. 433 **/ 434 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 435 { 436 return ixgbe_read_pba_num_generic(hw, pba_num); 437 } 438 439 /** 440 * ixgbe_identify_phy - Get PHY type 441 * @hw: pointer to hardware structure 442 * 443 * Determines the physical layer module found on the current adapter. 444 **/ 445 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 446 { 447 s32 status = IXGBE_SUCCESS; 448 449 if (hw->phy.type == ixgbe_phy_unknown) { 450 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 451 IXGBE_NOT_IMPLEMENTED); 452 } 453 454 return status; 455 } 456 457 /** 458 * ixgbe_reset_phy - Perform a PHY reset 459 * @hw: pointer to hardware structure 460 **/ 461 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 462 { 463 s32 status = IXGBE_SUCCESS; 464 465 if (hw->phy.type == ixgbe_phy_unknown) { 466 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 467 status = IXGBE_ERR_PHY; 468 } 469 470 if (status == IXGBE_SUCCESS) { 471 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 472 IXGBE_NOT_IMPLEMENTED); 473 } 474 return status; 475 } 476 477 /** 478 * ixgbe_get_phy_firmware_version - 479 * @hw: pointer to hardware structure 480 * @firmware_version: pointer to firmware version 481 **/ 482 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 483 { 484 s32 status = IXGBE_SUCCESS; 485 486 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 487 (hw, firmware_version), 488 IXGBE_NOT_IMPLEMENTED); 489 return status; 490 } 491 492 /** 493 * ixgbe_read_phy_reg - Read PHY register 494 * @hw: pointer to hardware structure 495 * @reg_addr: 32 bit address of PHY register to read 496 * @phy_data: Pointer to read data from PHY register 497 * 498 * Reads a value from a specified PHY register 499 **/ 500 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 501 u16 *phy_data) 502 { 503 if (hw->phy.id == 0) 504 ixgbe_identify_phy(hw); 505 506 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 507 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 508 } 509 510 /** 511 * ixgbe_write_phy_reg - Write PHY register 512 * @hw: pointer to hardware structure 513 * @reg_addr: 32 bit PHY register to write 514 * @phy_data: Data to write to the PHY register 515 * 516 * Writes a value to specified PHY register 517 **/ 518 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 519 u16 phy_data) 520 { 521 if (hw->phy.id == 0) 522 ixgbe_identify_phy(hw); 523 524 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 525 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 526 } 527 528 /** 529 * ixgbe_setup_phy_link - Restart PHY autoneg 530 * @hw: pointer to hardware structure 531 * 532 * Restart autonegotiation and PHY and waits for completion. 533 **/ 534 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 535 { 536 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 537 IXGBE_NOT_IMPLEMENTED); 538 } 539 540 /** 541 * ixgbe_setup_internal_phy - Configure integrated PHY 542 * @hw: pointer to hardware structure 543 * 544 * Reconfigure the integrated PHY in order to enable talk to the external PHY. 545 * Returns success if not implemented, since nothing needs to be done in this 546 * case. 547 */ 548 s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw) 549 { 550 return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw), 551 IXGBE_SUCCESS); 552 } 553 554 /** 555 * ixgbe_check_phy_link - Determine link and speed status 556 * @hw: pointer to hardware structure 557 * 558 * Reads a PHY register to determine if link is up and the current speed for 559 * the PHY. 560 **/ 561 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 562 bool *link_up) 563 { 564 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 565 link_up), IXGBE_NOT_IMPLEMENTED); 566 } 567 568 /** 569 * ixgbe_setup_phy_link_speed - Set auto advertise 570 * @hw: pointer to hardware structure 571 * @speed: new link speed 572 * 573 * Sets the auto advertised capabilities 574 **/ 575 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 576 bool autoneg_wait_to_complete) 577 { 578 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 579 autoneg_wait_to_complete), 580 IXGBE_NOT_IMPLEMENTED); 581 } 582 583 /** 584 * ixgbe_set_phy_power - Control the phy power state 585 * @hw: pointer to hardware structure 586 * @on: true for on, false for off 587 */ 588 s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on) 589 { 590 return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on), 591 IXGBE_NOT_IMPLEMENTED); 592 } 593 594 /** 595 * ixgbe_check_link - Get link and speed status 596 * @hw: pointer to hardware structure 597 * 598 * Reads the links register to determine if link is up and the current speed 599 **/ 600 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 601 bool *link_up, bool link_up_wait_to_complete) 602 { 603 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 604 link_up, link_up_wait_to_complete), 605 IXGBE_NOT_IMPLEMENTED); 606 } 607 608 /** 609 * ixgbe_disable_tx_laser - Disable Tx laser 610 * @hw: pointer to hardware structure 611 * 612 * If the driver needs to disable the laser on SFI optics. 613 **/ 614 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 615 { 616 if (hw->mac.ops.disable_tx_laser) 617 hw->mac.ops.disable_tx_laser(hw); 618 } 619 620 /** 621 * ixgbe_enable_tx_laser - Enable Tx laser 622 * @hw: pointer to hardware structure 623 * 624 * If the driver needs to enable the laser on SFI optics. 625 **/ 626 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 627 { 628 if (hw->mac.ops.enable_tx_laser) 629 hw->mac.ops.enable_tx_laser(hw); 630 } 631 632 /** 633 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 634 * @hw: pointer to hardware structure 635 * 636 * When the driver changes the link speeds that it can support then 637 * flap the tx laser to alert the link partner to start autotry 638 * process on its end. 639 **/ 640 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 641 { 642 if (hw->mac.ops.flap_tx_laser) 643 hw->mac.ops.flap_tx_laser(hw); 644 } 645 646 /** 647 * ixgbe_setup_link - Set link speed 648 * @hw: pointer to hardware structure 649 * @speed: new link speed 650 * 651 * Configures link settings. Restarts the link. 652 * Performs autonegotiation if needed. 653 **/ 654 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 655 bool autoneg_wait_to_complete) 656 { 657 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 658 autoneg_wait_to_complete), 659 IXGBE_NOT_IMPLEMENTED); 660 } 661 662 /** 663 * ixgbe_setup_mac_link - Set link speed 664 * @hw: pointer to hardware structure 665 * @speed: new link speed 666 * 667 * Configures link settings. Restarts the link. 668 * Performs autonegotiation if needed. 669 **/ 670 s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 671 bool autoneg_wait_to_complete) 672 { 673 return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed, 674 autoneg_wait_to_complete), 675 IXGBE_NOT_IMPLEMENTED); 676 } 677 678 /** 679 * ixgbe_get_link_capabilities - Returns link capabilities 680 * @hw: pointer to hardware structure 681 * 682 * Determines the link capabilities of the current configuration. 683 **/ 684 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 685 bool *autoneg) 686 { 687 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 688 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 689 } 690 691 /** 692 * ixgbe_led_on - Turn on LEDs 693 * @hw: pointer to hardware structure 694 * @index: led number to turn on 695 * 696 * Turns on the software controllable LEDs. 697 **/ 698 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 699 { 700 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 701 IXGBE_NOT_IMPLEMENTED); 702 } 703 704 /** 705 * ixgbe_led_off - Turn off LEDs 706 * @hw: pointer to hardware structure 707 * @index: led number to turn off 708 * 709 * Turns off the software controllable LEDs. 710 **/ 711 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 712 { 713 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 714 IXGBE_NOT_IMPLEMENTED); 715 } 716 717 /** 718 * ixgbe_blink_led_start - Blink LEDs 719 * @hw: pointer to hardware structure 720 * @index: led number to blink 721 * 722 * Blink LED based on index. 723 **/ 724 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 725 { 726 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 727 IXGBE_NOT_IMPLEMENTED); 728 } 729 730 /** 731 * ixgbe_blink_led_stop - Stop blinking LEDs 732 * @hw: pointer to hardware structure 733 * 734 * Stop blinking LED based on index. 735 **/ 736 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 737 { 738 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 739 IXGBE_NOT_IMPLEMENTED); 740 } 741 742 /** 743 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 744 * @hw: pointer to hardware structure 745 * 746 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 747 * ixgbe_hw struct in order to set up EEPROM access. 748 **/ 749 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 750 { 751 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 752 IXGBE_NOT_IMPLEMENTED); 753 } 754 755 756 /** 757 * ixgbe_write_eeprom - Write word to EEPROM 758 * @hw: pointer to hardware structure 759 * @offset: offset within the EEPROM to be written to 760 * @data: 16 bit word to be written to the EEPROM 761 * 762 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 763 * called after this function, the EEPROM will most likely contain an 764 * invalid checksum. 765 **/ 766 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 767 { 768 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 769 IXGBE_NOT_IMPLEMENTED); 770 } 771 772 /** 773 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 774 * @hw: pointer to hardware structure 775 * @offset: offset within the EEPROM to be written to 776 * @data: 16 bit word(s) to be written to the EEPROM 777 * @words: number of words 778 * 779 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 780 * called after this function, the EEPROM will most likely contain an 781 * invalid checksum. 782 **/ 783 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 784 u16 *data) 785 { 786 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 787 (hw, offset, words, data), 788 IXGBE_NOT_IMPLEMENTED); 789 } 790 791 /** 792 * ixgbe_read_eeprom - Read word from EEPROM 793 * @hw: pointer to hardware structure 794 * @offset: offset within the EEPROM to be read 795 * @data: read 16 bit value from EEPROM 796 * 797 * Reads 16 bit value from EEPROM 798 **/ 799 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 800 { 801 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 802 IXGBE_NOT_IMPLEMENTED); 803 } 804 805 /** 806 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 807 * @hw: pointer to hardware structure 808 * @offset: offset within the EEPROM to be read 809 * @data: read 16 bit word(s) from EEPROM 810 * @words: number of words 811 * 812 * Reads 16 bit word(s) from EEPROM 813 **/ 814 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 815 u16 words, u16 *data) 816 { 817 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 818 (hw, offset, words, data), 819 IXGBE_NOT_IMPLEMENTED); 820 } 821 822 /** 823 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 824 * @hw: pointer to hardware structure 825 * @checksum_val: calculated checksum 826 * 827 * Performs checksum calculation and validates the EEPROM checksum 828 **/ 829 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 830 { 831 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 832 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 833 } 834 835 /** 836 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 837 * @hw: pointer to hardware structure 838 **/ 839 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 840 { 841 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 842 IXGBE_NOT_IMPLEMENTED); 843 } 844 845 /** 846 * ixgbe_insert_mac_addr - Find a RAR for this mac address 847 * @hw: pointer to hardware structure 848 * @addr: Address to put into receive address register 849 * @vmdq: VMDq pool to assign 850 * 851 * Puts an ethernet address into a receive address register, or 852 * finds the rar that it is aleady in; adds to the pool list 853 **/ 854 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 855 { 856 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 857 (hw, addr, vmdq), 858 IXGBE_NOT_IMPLEMENTED); 859 } 860 861 /** 862 * ixgbe_set_rar - Set Rx address register 863 * @hw: pointer to hardware structure 864 * @index: Receive address register to write 865 * @addr: Address to put into receive address register 866 * @vmdq: VMDq "set" 867 * @enable_addr: set flag that address is active 868 * 869 * Puts an ethernet address into a receive address register. 870 **/ 871 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 872 u32 enable_addr) 873 { 874 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 875 enable_addr), IXGBE_NOT_IMPLEMENTED); 876 } 877 878 /** 879 * ixgbe_clear_rar - Clear Rx address register 880 * @hw: pointer to hardware structure 881 * @index: Receive address register to write 882 * 883 * Puts an ethernet address into a receive address register. 884 **/ 885 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 886 { 887 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 888 IXGBE_NOT_IMPLEMENTED); 889 } 890 891 /** 892 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 893 * @hw: pointer to hardware structure 894 * @rar: receive address register index to associate with VMDq index 895 * @vmdq: VMDq set or pool index 896 **/ 897 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 898 { 899 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 900 IXGBE_NOT_IMPLEMENTED); 901 902 } 903 904 /** 905 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address 906 * @hw: pointer to hardware structure 907 * @vmdq: VMDq default pool index 908 **/ 909 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) 910 { 911 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac, 912 (hw, vmdq), IXGBE_NOT_IMPLEMENTED); 913 } 914 915 /** 916 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 917 * @hw: pointer to hardware structure 918 * @rar: receive address register index to disassociate with VMDq index 919 * @vmdq: VMDq set or pool index 920 **/ 921 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 922 { 923 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 924 IXGBE_NOT_IMPLEMENTED); 925 } 926 927 /** 928 * ixgbe_init_rx_addrs - Initializes receive address filters. 929 * @hw: pointer to hardware structure 930 * 931 * Places the MAC address in receive address register 0 and clears the rest 932 * of the receive address registers. Clears the multicast table. Assumes 933 * the receiver is in reset when the routine is called. 934 **/ 935 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 936 { 937 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 938 IXGBE_NOT_IMPLEMENTED); 939 } 940 941 /** 942 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 943 * @hw: pointer to hardware structure 944 **/ 945 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 946 { 947 return hw->mac.num_rar_entries; 948 } 949 950 /** 951 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 952 * @hw: pointer to hardware structure 953 * @addr_list: the list of new multicast addresses 954 * @addr_count: number of addresses 955 * @func: iterator function to walk the multicast address list 956 * 957 * The given list replaces any existing list. Clears the secondary addrs from 958 * receive address registers. Uses unused receive address registers for the 959 * first secondary addresses, and falls back to promiscuous mode as needed. 960 **/ 961 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 962 u32 addr_count, ixgbe_mc_addr_itr func) 963 { 964 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 965 addr_list, addr_count, func), 966 IXGBE_NOT_IMPLEMENTED); 967 } 968 969 /** 970 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 971 * @hw: pointer to hardware structure 972 * @mc_addr_list: the list of new multicast addresses 973 * @mc_addr_count: number of addresses 974 * @func: iterator function to walk the multicast address list 975 * 976 * The given list replaces any existing list. Clears the MC addrs from receive 977 * address registers and the multicast table. Uses unused receive address 978 * registers for the first multicast addresses, and hashes the rest into the 979 * multicast table. 980 **/ 981 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 982 u32 mc_addr_count, ixgbe_mc_addr_itr func, 983 bool clear) 984 { 985 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 986 mc_addr_list, mc_addr_count, func, clear), 987 IXGBE_NOT_IMPLEMENTED); 988 } 989 990 /** 991 * ixgbe_enable_mc - Enable multicast address in RAR 992 * @hw: pointer to hardware structure 993 * 994 * Enables multicast address in RAR and the use of the multicast hash table. 995 **/ 996 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 997 { 998 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 999 IXGBE_NOT_IMPLEMENTED); 1000 } 1001 1002 /** 1003 * ixgbe_disable_mc - Disable multicast address in RAR 1004 * @hw: pointer to hardware structure 1005 * 1006 * Disables multicast address in RAR and the use of the multicast hash table. 1007 **/ 1008 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 1009 { 1010 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 1011 IXGBE_NOT_IMPLEMENTED); 1012 } 1013 1014 /** 1015 * ixgbe_clear_vfta - Clear VLAN filter table 1016 * @hw: pointer to hardware structure 1017 * 1018 * Clears the VLAN filer table, and the VMDq index associated with the filter 1019 **/ 1020 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 1021 { 1022 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 1023 IXGBE_NOT_IMPLEMENTED); 1024 } 1025 1026 /** 1027 * ixgbe_set_vfta - Set VLAN filter table 1028 * @hw: pointer to hardware structure 1029 * @vlan: VLAN id to write to VLAN filter 1030 * @vind: VMDq output index that maps queue to VLAN id in VFTA 1031 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 1032 * 1033 * Turn on/off specified VLAN in the VLAN filter table. 1034 **/ 1035 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 1036 { 1037 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 1038 vlan_on), IXGBE_NOT_IMPLEMENTED); 1039 } 1040 1041 /** 1042 * ixgbe_set_vlvf - Set VLAN Pool Filter 1043 * @hw: pointer to hardware structure 1044 * @vlan: VLAN id to write to VLAN filter 1045 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 1046 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 1047 * @vfta_changed: pointer to boolean flag which indicates whether VFTA 1048 * should be changed 1049 * 1050 * Turn on/off specified bit in VLVF table. 1051 **/ 1052 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1053 bool *vfta_changed) 1054 { 1055 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 1056 vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED); 1057 } 1058 1059 /** 1060 * ixgbe_fc_enable - Enable flow control 1061 * @hw: pointer to hardware structure 1062 * 1063 * Configures the flow control settings based on SW configuration. 1064 **/ 1065 s32 ixgbe_fc_enable(struct ixgbe_hw *hw) 1066 { 1067 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), 1068 IXGBE_NOT_IMPLEMENTED); 1069 } 1070 1071 /** 1072 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 1073 * @hw: pointer to hardware structure 1074 * @maj: driver major number to be sent to firmware 1075 * @min: driver minor number to be sent to firmware 1076 * @build: driver build number to be sent to firmware 1077 * @ver: driver version number to be sent to firmware 1078 **/ 1079 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, 1080 u8 ver) 1081 { 1082 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min, 1083 build, ver), IXGBE_NOT_IMPLEMENTED); 1084 } 1085 1086 1087 /** 1088 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data 1089 * @hw: pointer to hardware structure 1090 * 1091 * Updates the temperatures in mac.thermal_sensor_data 1092 **/ 1093 s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw) 1094 { 1095 return ixgbe_call_func(hw, hw->mac.ops.get_thermal_sensor_data, (hw), 1096 IXGBE_NOT_IMPLEMENTED); 1097 } 1098 1099 /** 1100 * ixgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds 1101 * @hw: pointer to hardware structure 1102 * 1103 * Inits the thermal sensor thresholds according to the NVM map 1104 **/ 1105 s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw) 1106 { 1107 return ixgbe_call_func(hw, hw->mac.ops.init_thermal_sensor_thresh, (hw), 1108 IXGBE_NOT_IMPLEMENTED); 1109 } 1110 1111 /** 1112 * ixgbe_dmac_config - Configure DMA Coalescing registers. 1113 * @hw: pointer to hardware structure 1114 * 1115 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1116 * When disabling dmac, dmac enable dmac bit is cleared. 1117 **/ 1118 s32 ixgbe_dmac_config(struct ixgbe_hw *hw) 1119 { 1120 return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw), 1121 IXGBE_NOT_IMPLEMENTED); 1122 } 1123 1124 /** 1125 * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers. 1126 * @hw: pointer to hardware structure 1127 * 1128 * Disables dmac, updates per TC settings, and then enable dmac. 1129 **/ 1130 s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw) 1131 { 1132 return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw), 1133 IXGBE_NOT_IMPLEMENTED); 1134 } 1135 1136 /** 1137 * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers. 1138 * @hw: pointer to hardware structure 1139 * 1140 * Configure DMA coalescing threshold per TC and set high priority bit for 1141 * FCOE TC. The dmac enable bit must be cleared before configuring. 1142 **/ 1143 s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw) 1144 { 1145 return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw), 1146 IXGBE_NOT_IMPLEMENTED); 1147 } 1148 1149 /** 1150 * ixgbe_setup_eee - Enable/disable EEE support 1151 * @hw: pointer to the HW structure 1152 * @enable_eee: boolean flag to enable EEE 1153 * 1154 * Enable/disable EEE based on enable_ee flag. 1155 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 1156 * are modified. 1157 * 1158 **/ 1159 s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee) 1160 { 1161 return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee), 1162 IXGBE_NOT_IMPLEMENTED); 1163 } 1164 1165 /** 1166 * ixgbe_set_source_address_pruning - Enable/Disable source address pruning 1167 * @hw: pointer to hardware structure 1168 * @enbale: enable or disable source address pruning 1169 * @pool: Rx pool - Rx pool to toggle source address pruning 1170 **/ 1171 void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, 1172 unsigned int pool) 1173 { 1174 if (hw->mac.ops.set_source_address_pruning) 1175 hw->mac.ops.set_source_address_pruning(hw, enable, pool); 1176 } 1177 1178 /** 1179 * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing 1180 * @hw: pointer to hardware structure 1181 * @enable: enable or disable switch for Ethertype anti-spoofing 1182 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1183 * 1184 **/ 1185 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 1186 { 1187 if (hw->mac.ops.set_ethertype_anti_spoofing) 1188 hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf); 1189 } 1190 1191 /** 1192 * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register 1193 * @hw: pointer to hardware structure 1194 * @reg_addr: 32 bit address of PHY register to read 1195 * @device_type: type of device you want to communicate with 1196 * @phy_data: Pointer to read data from PHY register 1197 * 1198 * Reads a value from a specified PHY register 1199 **/ 1200 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1201 u32 device_type, u32 *phy_data) 1202 { 1203 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, 1204 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1205 } 1206 1207 /** 1208 * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband 1209 * @hw: pointer to hardware structure 1210 * @reg_addr: 32 bit PHY register to write 1211 * @device_type: type of device you want to communicate with 1212 * @phy_data: Data to write to the PHY register 1213 * 1214 * Writes a value to specified PHY register 1215 **/ 1216 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1217 u32 device_type, u32 phy_data) 1218 { 1219 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, 1220 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1221 } 1222 1223 /** 1224 * ixgbe_disable_mdd - Disable malicious driver detection 1225 * @hw: pointer to hardware structure 1226 * 1227 **/ 1228 void ixgbe_disable_mdd(struct ixgbe_hw *hw) 1229 { 1230 if (hw->mac.ops.disable_mdd) 1231 hw->mac.ops.disable_mdd(hw); 1232 } 1233 1234 /** 1235 * ixgbe_enable_mdd - Enable malicious driver detection 1236 * @hw: pointer to hardware structure 1237 * 1238 **/ 1239 void ixgbe_enable_mdd(struct ixgbe_hw *hw) 1240 { 1241 if (hw->mac.ops.enable_mdd) 1242 hw->mac.ops.enable_mdd(hw); 1243 } 1244 1245 /** 1246 * ixgbe_mdd_event - Handle malicious driver detection event 1247 * @hw: pointer to hardware structure 1248 * @vf_bitmap: vf bitmap of malicious vfs 1249 * 1250 **/ 1251 void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap) 1252 { 1253 if (hw->mac.ops.mdd_event) 1254 hw->mac.ops.mdd_event(hw, vf_bitmap); 1255 } 1256 1257 /** 1258 * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver 1259 * detection event 1260 * @hw: pointer to hardware structure 1261 * @vf: vf index 1262 * 1263 **/ 1264 void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf) 1265 { 1266 if (hw->mac.ops.restore_mdd_vf) 1267 hw->mac.ops.restore_mdd_vf(hw, vf); 1268 } 1269 1270 /** 1271 * ixgbe_enter_lplu - Transition to low power states 1272 * @hw: pointer to hardware structure 1273 * 1274 * Configures Low Power Link Up on transition to low power states 1275 * (from D0 to non-D0). 1276 **/ 1277 s32 ixgbe_enter_lplu(struct ixgbe_hw *hw) 1278 { 1279 return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw), 1280 IXGBE_NOT_IMPLEMENTED); 1281 } 1282 1283 /** 1284 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 1285 * @hw: pointer to hardware structure 1286 * @reg: analog register to read 1287 * @val: read value 1288 * 1289 * Performs write operation to analog register specified. 1290 **/ 1291 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 1292 { 1293 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1294 val), IXGBE_NOT_IMPLEMENTED); 1295 } 1296 1297 /** 1298 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1299 * @hw: pointer to hardware structure 1300 * @reg: analog register to write 1301 * @val: value to write 1302 * 1303 * Performs write operation to Atlas analog register specified. 1304 **/ 1305 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1306 { 1307 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1308 val), IXGBE_NOT_IMPLEMENTED); 1309 } 1310 1311 /** 1312 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1313 * @hw: pointer to hardware structure 1314 * 1315 * Initializes the Unicast Table Arrays to zero on device load. This 1316 * is part of the Rx init addr execution path. 1317 **/ 1318 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1319 { 1320 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1321 IXGBE_NOT_IMPLEMENTED); 1322 } 1323 1324 /** 1325 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1326 * @hw: pointer to hardware structure 1327 * @byte_offset: byte offset to read 1328 * @dev_addr: I2C bus address to read from 1329 * @data: value read 1330 * 1331 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1332 **/ 1333 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1334 u8 *data) 1335 { 1336 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1337 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1338 } 1339 1340 /** 1341 * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address 1342 * @hw: pointer to hardware structure 1343 * @byte_offset: byte offset to read 1344 * @dev_addr: I2C bus address to read from 1345 * @data: value read 1346 * 1347 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1348 **/ 1349 s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1350 u8 dev_addr, u8 *data) 1351 { 1352 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked, 1353 (hw, byte_offset, dev_addr, data), 1354 IXGBE_NOT_IMPLEMENTED); 1355 } 1356 1357 /** 1358 * ixgbe_read_i2c_combined - Perform I2C read combined operation 1359 * @hw: pointer to the hardware structure 1360 * @addr: I2C bus address to read from 1361 * @reg: I2C device register to read from 1362 * @val: pointer to location to receive read value 1363 * 1364 * Returns an error code on error. 1365 */ 1366 s32 ixgbe_read_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1367 { 1368 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined, (hw, addr, 1369 reg, val), IXGBE_NOT_IMPLEMENTED); 1370 } 1371 1372 /** 1373 * ixgbe_read_i2c_combined_unlocked - Perform I2C read combined operation 1374 * @hw: pointer to the hardware structure 1375 * @addr: I2C bus address to read from 1376 * @reg: I2C device register to read from 1377 * @val: pointer to location to receive read value 1378 * 1379 * Returns an error code on error. 1380 **/ 1381 s32 ixgbe_read_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, 1382 u16 *val) 1383 { 1384 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined_unlocked, 1385 (hw, addr, reg, val), 1386 IXGBE_NOT_IMPLEMENTED); 1387 } 1388 1389 /** 1390 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1391 * @hw: pointer to hardware structure 1392 * @byte_offset: byte offset to write 1393 * @dev_addr: I2C bus address to write to 1394 * @data: value to write 1395 * 1396 * Performs byte write operation to SFP module's EEPROM over I2C interface 1397 * at a specified device address. 1398 **/ 1399 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1400 u8 data) 1401 { 1402 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1403 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1404 } 1405 1406 /** 1407 * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1408 * @hw: pointer to hardware structure 1409 * @byte_offset: byte offset to write 1410 * @dev_addr: I2C bus address to write to 1411 * @data: value to write 1412 * 1413 * Performs byte write operation to SFP module's EEPROM over I2C interface 1414 * at a specified device address. 1415 **/ 1416 s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1417 u8 dev_addr, u8 data) 1418 { 1419 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked, 1420 (hw, byte_offset, dev_addr, data), 1421 IXGBE_NOT_IMPLEMENTED); 1422 } 1423 1424 /** 1425 * ixgbe_write_i2c_combined - Perform I2C write combined operation 1426 * @hw: pointer to the hardware structure 1427 * @addr: I2C bus address to write to 1428 * @reg: I2C device register to write to 1429 * @val: value to write 1430 * 1431 * Returns an error code on error. 1432 */ 1433 s32 ixgbe_write_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1434 { 1435 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined, (hw, addr, 1436 reg, val), IXGBE_NOT_IMPLEMENTED); 1437 } 1438 1439 /** 1440 * ixgbe_write_i2c_combined_unlocked - Perform I2C write combined operation 1441 * @hw: pointer to the hardware structure 1442 * @addr: I2C bus address to write to 1443 * @reg: I2C device register to write to 1444 * @val: value to write 1445 * 1446 * Returns an error code on error. 1447 **/ 1448 s32 ixgbe_write_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, 1449 u16 val) 1450 { 1451 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined_unlocked, 1452 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1453 } 1454 1455 /** 1456 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1457 * @hw: pointer to hardware structure 1458 * @byte_offset: EEPROM byte offset to write 1459 * @eeprom_data: value to write 1460 * 1461 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1462 **/ 1463 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1464 u8 byte_offset, u8 eeprom_data) 1465 { 1466 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1467 (hw, byte_offset, eeprom_data), 1468 IXGBE_NOT_IMPLEMENTED); 1469 } 1470 1471 /** 1472 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1473 * @hw: pointer to hardware structure 1474 * @byte_offset: EEPROM byte offset to read 1475 * @eeprom_data: value read 1476 * 1477 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1478 **/ 1479 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1480 { 1481 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1482 (hw, byte_offset, eeprom_data), 1483 IXGBE_NOT_IMPLEMENTED); 1484 } 1485 1486 /** 1487 * ixgbe_get_supported_physical_layer - Returns physical layer type 1488 * @hw: pointer to hardware structure 1489 * 1490 * Determines physical layer capabilities of the current configuration. 1491 **/ 1492 u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1493 { 1494 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1495 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1496 } 1497 1498 /** 1499 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics 1500 * @hw: pointer to hardware structure 1501 * @regval: bitfield to write to the Rx DMA register 1502 * 1503 * Enables the Rx DMA unit of the device. 1504 **/ 1505 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1506 { 1507 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1508 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1509 } 1510 1511 /** 1512 * ixgbe_disable_sec_rx_path - Stops the receive data path 1513 * @hw: pointer to hardware structure 1514 * 1515 * Stops the receive data path. 1516 **/ 1517 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1518 { 1519 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1520 (hw), IXGBE_NOT_IMPLEMENTED); 1521 } 1522 1523 /** 1524 * ixgbe_enable_sec_rx_path - Enables the receive data path 1525 * @hw: pointer to hardware structure 1526 * 1527 * Enables the receive data path. 1528 **/ 1529 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1530 { 1531 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1532 (hw), IXGBE_NOT_IMPLEMENTED); 1533 } 1534 1535 /** 1536 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1537 * @hw: pointer to hardware structure 1538 * @mask: Mask to specify which semaphore to acquire 1539 * 1540 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1541 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1542 **/ 1543 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1544 { 1545 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1546 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1547 } 1548 1549 /** 1550 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1551 * @hw: pointer to hardware structure 1552 * @mask: Mask to specify which semaphore to release 1553 * 1554 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1555 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1556 **/ 1557 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1558 { 1559 if (hw->mac.ops.release_swfw_sync) 1560 hw->mac.ops.release_swfw_sync(hw, mask); 1561 } 1562 1563 1564 void ixgbe_disable_rx(struct ixgbe_hw *hw) 1565 { 1566 if (hw->mac.ops.disable_rx) 1567 hw->mac.ops.disable_rx(hw); 1568 } 1569 1570 void ixgbe_enable_rx(struct ixgbe_hw *hw) 1571 { 1572 if (hw->mac.ops.enable_rx) 1573 hw->mac.ops.enable_rx(hw); 1574 } 1575 1576 /** 1577 * ixgbe_set_rate_select_speed - Set module link speed 1578 * @hw: pointer to hardware structure 1579 * @speed: link speed to set 1580 * 1581 * Set module link speed via the rate select. 1582 */ 1583 void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 1584 { 1585 if (hw->mac.ops.set_rate_select_speed) 1586 hw->mac.ops.set_rate_select_speed(hw, speed); 1587 } 1588