1 /******************************************************************************* 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 #include "ixgbe_api.h" 35 #include "ixgbe_common.h" 36 37 #define IXGBE_EMPTY_PARAM 38 39 static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = { 40 IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM) 41 }; 42 43 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = { 44 IXGBE_MVALS_INIT(_X540) 45 }; 46 47 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 48 IXGBE_MVALS_INIT(_X550) 49 }; 50 51 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 52 IXGBE_MVALS_INIT(_X550EM_x) 53 }; 54 55 /** 56 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg 57 * @hw: pointer to hardware structure 58 * @map: pointer to u8 arr for returning map 59 * 60 * Read the rtrup2tc HW register and resolve its content into map 61 **/ 62 void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map) 63 { 64 if (hw->mac.ops.get_rtrup2tc) 65 hw->mac.ops.get_rtrup2tc(hw, map); 66 } 67 68 /** 69 * ixgbe_init_shared_code - Initialize the shared code 70 * @hw: pointer to hardware structure 71 * 72 * This will assign function pointers and assign the MAC type and PHY code. 73 * Does not touch the hardware. This function must be called prior to any 74 * other function in the shared code. The ixgbe_hw structure should be 75 * memset to 0 prior to calling this function. The following fields in 76 * hw structure should be filled in prior to calling this function: 77 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 78 * subsystem_vendor_id, and revision_id 79 **/ 80 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 81 { 82 s32 status; 83 84 DEBUGFUNC("ixgbe_init_shared_code"); 85 86 /* 87 * Set the mac type 88 */ 89 ixgbe_set_mac_type(hw); 90 91 switch (hw->mac.type) { 92 case ixgbe_mac_82598EB: 93 status = ixgbe_init_ops_82598(hw); 94 break; 95 case ixgbe_mac_82599EB: 96 status = ixgbe_init_ops_82599(hw); 97 break; 98 case ixgbe_mac_X540: 99 status = ixgbe_init_ops_X540(hw); 100 break; 101 case ixgbe_mac_X550: 102 status = ixgbe_init_ops_X550(hw); 103 break; 104 case ixgbe_mac_X550EM_x: 105 status = ixgbe_init_ops_X550EM(hw); 106 break; 107 case ixgbe_mac_82599_vf: 108 case ixgbe_mac_X540_vf: 109 case ixgbe_mac_X550_vf: 110 case ixgbe_mac_X550EM_x_vf: 111 status = ixgbe_init_ops_vf(hw); 112 break; 113 default: 114 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 115 break; 116 } 117 118 return status; 119 } 120 121 /** 122 * ixgbe_set_mac_type - Sets MAC type 123 * @hw: pointer to the HW structure 124 * 125 * This function sets the mac type of the adapter based on the 126 * vendor ID and device ID stored in the hw structure. 127 **/ 128 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 129 { 130 s32 ret_val = IXGBE_SUCCESS; 131 132 DEBUGFUNC("ixgbe_set_mac_type\n"); 133 134 if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { 135 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 136 "Unsupported vendor id: %x", hw->vendor_id); 137 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 138 } 139 140 hw->mvals = ixgbe_mvals_base; 141 142 switch (hw->device_id) { 143 case IXGBE_DEV_ID_82598: 144 case IXGBE_DEV_ID_82598_BX: 145 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 146 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 147 case IXGBE_DEV_ID_82598AT: 148 case IXGBE_DEV_ID_82598AT2: 149 case IXGBE_DEV_ID_82598EB_CX4: 150 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 151 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 152 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 153 case IXGBE_DEV_ID_82598EB_XF_LR: 154 case IXGBE_DEV_ID_82598EB_SFP_LOM: 155 hw->mac.type = ixgbe_mac_82598EB; 156 break; 157 case IXGBE_DEV_ID_82599_KX4: 158 case IXGBE_DEV_ID_82599_KX4_MEZZ: 159 case IXGBE_DEV_ID_82599_XAUI_LOM: 160 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 161 case IXGBE_DEV_ID_82599_KR: 162 case IXGBE_DEV_ID_82599_SFP: 163 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 164 case IXGBE_DEV_ID_82599_SFP_FCOE: 165 case IXGBE_DEV_ID_82599_SFP_EM: 166 case IXGBE_DEV_ID_82599_SFP_SF2: 167 case IXGBE_DEV_ID_82599_SFP_SF_QP: 168 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 169 case IXGBE_DEV_ID_82599EN_SFP: 170 case IXGBE_DEV_ID_82599_CX4: 171 case IXGBE_DEV_ID_82599_LS: 172 case IXGBE_DEV_ID_82599_T3_LOM: 173 hw->mac.type = ixgbe_mac_82599EB; 174 break; 175 case IXGBE_DEV_ID_82599_VF: 176 case IXGBE_DEV_ID_82599_VF_HV: 177 hw->mac.type = ixgbe_mac_82599_vf; 178 break; 179 case IXGBE_DEV_ID_X540_VF: 180 case IXGBE_DEV_ID_X540_VF_HV: 181 hw->mac.type = ixgbe_mac_X540_vf; 182 hw->mvals = ixgbe_mvals_X540; 183 break; 184 case IXGBE_DEV_ID_X540T: 185 case IXGBE_DEV_ID_X540T1: 186 hw->mac.type = ixgbe_mac_X540; 187 hw->mvals = ixgbe_mvals_X540; 188 break; 189 case IXGBE_DEV_ID_X550T: 190 hw->mac.type = ixgbe_mac_X550; 191 hw->mvals = ixgbe_mvals_X550; 192 break; 193 case IXGBE_DEV_ID_X550EM_X_KX4: 194 case IXGBE_DEV_ID_X550EM_X_KR: 195 case IXGBE_DEV_ID_X550EM_X_10G_T: 196 case IXGBE_DEV_ID_X550EM_X_1G_T: 197 case IXGBE_DEV_ID_X550EM_X_SFP: 198 hw->mac.type = ixgbe_mac_X550EM_x; 199 hw->mvals = ixgbe_mvals_X550EM_x; 200 break; 201 case IXGBE_DEV_ID_X550_VF: 202 case IXGBE_DEV_ID_X550_VF_HV: 203 hw->mac.type = ixgbe_mac_X550_vf; 204 hw->mvals = ixgbe_mvals_X550; 205 break; 206 case IXGBE_DEV_ID_X550EM_X_VF: 207 case IXGBE_DEV_ID_X550EM_X_VF_HV: 208 hw->mac.type = ixgbe_mac_X550EM_x_vf; 209 hw->mvals = ixgbe_mvals_X550EM_x; 210 break; 211 default: 212 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 213 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 214 "Unsupported device id: %x", 215 hw->device_id); 216 break; 217 } 218 219 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 220 hw->mac.type, ret_val); 221 return ret_val; 222 } 223 224 /** 225 * ixgbe_init_hw - Initialize the hardware 226 * @hw: pointer to hardware structure 227 * 228 * Initialize the hardware by resetting and then starting the hardware 229 **/ 230 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 231 { 232 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 233 IXGBE_NOT_IMPLEMENTED); 234 } 235 236 /** 237 * ixgbe_reset_hw - Performs a hardware reset 238 * @hw: pointer to hardware structure 239 * 240 * Resets the hardware by resetting the transmit and receive units, masks and 241 * clears all interrupts, performs a PHY reset, and performs a MAC reset 242 **/ 243 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 244 { 245 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 246 IXGBE_NOT_IMPLEMENTED); 247 } 248 249 /** 250 * ixgbe_start_hw - Prepares hardware for Rx/Tx 251 * @hw: pointer to hardware structure 252 * 253 * Starts the hardware by filling the bus info structure and media type, 254 * clears all on chip counters, initializes receive address registers, 255 * multicast table, VLAN filter table, calls routine to setup link and 256 * flow control settings, and leaves transmit and receive units disabled 257 * and uninitialized. 258 **/ 259 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 260 { 261 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 262 IXGBE_NOT_IMPLEMENTED); 263 } 264 265 /** 266 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 267 * which is disabled by default in ixgbe_start_hw(); 268 * 269 * @hw: pointer to hardware structure 270 * 271 * Enable relaxed ordering; 272 **/ 273 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 274 { 275 if (hw->mac.ops.enable_relaxed_ordering) 276 hw->mac.ops.enable_relaxed_ordering(hw); 277 } 278 279 /** 280 * ixgbe_clear_hw_cntrs - Clear hardware counters 281 * @hw: pointer to hardware structure 282 * 283 * Clears all hardware statistics counters by reading them from the hardware 284 * Statistics counters are clear on read. 285 **/ 286 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 287 { 288 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 289 IXGBE_NOT_IMPLEMENTED); 290 } 291 292 /** 293 * ixgbe_get_media_type - Get media type 294 * @hw: pointer to hardware structure 295 * 296 * Returns the media type (fiber, copper, backplane) 297 **/ 298 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 299 { 300 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 301 ixgbe_media_type_unknown); 302 } 303 304 /** 305 * ixgbe_get_mac_addr - Get MAC address 306 * @hw: pointer to hardware structure 307 * @mac_addr: Adapter MAC address 308 * 309 * Reads the adapter's MAC address from the first Receive Address Register 310 * (RAR0) A reset of the adapter must have been performed prior to calling 311 * this function in order for the MAC address to have been loaded from the 312 * EEPROM into RAR0 313 **/ 314 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 315 { 316 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 317 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 318 } 319 320 /** 321 * ixgbe_get_san_mac_addr - Get SAN MAC address 322 * @hw: pointer to hardware structure 323 * @san_mac_addr: SAN MAC address 324 * 325 * Reads the SAN MAC address from the EEPROM, if it's available. This is 326 * per-port, so set_lan_id() must be called before reading the addresses. 327 **/ 328 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 329 { 330 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 331 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 332 } 333 334 /** 335 * ixgbe_set_san_mac_addr - Write a SAN MAC address 336 * @hw: pointer to hardware structure 337 * @san_mac_addr: SAN MAC address 338 * 339 * Writes A SAN MAC address to the EEPROM. 340 **/ 341 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 342 { 343 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 344 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 345 } 346 347 /** 348 * ixgbe_get_device_caps - Get additional device capabilities 349 * @hw: pointer to hardware structure 350 * @device_caps: the EEPROM word for device capabilities 351 * 352 * Reads the extra device capabilities from the EEPROM 353 **/ 354 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 355 { 356 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 357 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 358 } 359 360 /** 361 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 362 * @hw: pointer to hardware structure 363 * @wwnn_prefix: the alternative WWNN prefix 364 * @wwpn_prefix: the alternative WWPN prefix 365 * 366 * This function will read the EEPROM from the alternative SAN MAC address 367 * block to check the support for the alternative WWNN/WWPN prefix support. 368 **/ 369 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 370 u16 *wwpn_prefix) 371 { 372 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 373 (hw, wwnn_prefix, wwpn_prefix), 374 IXGBE_NOT_IMPLEMENTED); 375 } 376 377 /** 378 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 379 * @hw: pointer to hardware structure 380 * @bs: the fcoe boot status 381 * 382 * This function will read the FCOE boot status from the iSCSI FCOE block 383 **/ 384 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 385 { 386 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 387 (hw, bs), 388 IXGBE_NOT_IMPLEMENTED); 389 } 390 391 /** 392 * ixgbe_get_bus_info - Set PCI bus info 393 * @hw: pointer to hardware structure 394 * 395 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 396 **/ 397 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 398 { 399 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 400 IXGBE_NOT_IMPLEMENTED); 401 } 402 403 /** 404 * ixgbe_get_num_of_tx_queues - Get Tx queues 405 * @hw: pointer to hardware structure 406 * 407 * Returns the number of transmit queues for the given adapter. 408 **/ 409 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 410 { 411 return hw->mac.max_tx_queues; 412 } 413 414 /** 415 * ixgbe_get_num_of_rx_queues - Get Rx queues 416 * @hw: pointer to hardware structure 417 * 418 * Returns the number of receive queues for the given adapter. 419 **/ 420 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 421 { 422 return hw->mac.max_rx_queues; 423 } 424 425 /** 426 * ixgbe_stop_adapter - Disable Rx/Tx units 427 * @hw: pointer to hardware structure 428 * 429 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 430 * disables transmit and receive units. The adapter_stopped flag is used by 431 * the shared code and drivers to determine if the adapter is in a stopped 432 * state and should not touch the hardware. 433 **/ 434 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 435 { 436 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 437 IXGBE_NOT_IMPLEMENTED); 438 } 439 440 /** 441 * ixgbe_read_pba_string - Reads part number string from EEPROM 442 * @hw: pointer to hardware structure 443 * @pba_num: stores the part number string from the EEPROM 444 * @pba_num_size: part number string buffer length 445 * 446 * Reads the part number string from the EEPROM. 447 **/ 448 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 449 { 450 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 451 } 452 453 /** 454 * ixgbe_read_pba_num - Reads part number from EEPROM 455 * @hw: pointer to hardware structure 456 * @pba_num: stores the part number from the EEPROM 457 * 458 * Reads the part number from the EEPROM. 459 **/ 460 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 461 { 462 return ixgbe_read_pba_num_generic(hw, pba_num); 463 } 464 465 /** 466 * ixgbe_identify_phy - Get PHY type 467 * @hw: pointer to hardware structure 468 * 469 * Determines the physical layer module found on the current adapter. 470 **/ 471 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 472 { 473 s32 status = IXGBE_SUCCESS; 474 475 if (hw->phy.type == ixgbe_phy_unknown) { 476 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 477 IXGBE_NOT_IMPLEMENTED); 478 } 479 480 return status; 481 } 482 483 /** 484 * ixgbe_reset_phy - Perform a PHY reset 485 * @hw: pointer to hardware structure 486 **/ 487 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 488 { 489 s32 status = IXGBE_SUCCESS; 490 491 if (hw->phy.type == ixgbe_phy_unknown) { 492 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 493 status = IXGBE_ERR_PHY; 494 } 495 496 if (status == IXGBE_SUCCESS) { 497 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 498 IXGBE_NOT_IMPLEMENTED); 499 } 500 return status; 501 } 502 503 /** 504 * ixgbe_get_phy_firmware_version - 505 * @hw: pointer to hardware structure 506 * @firmware_version: pointer to firmware version 507 **/ 508 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 509 { 510 s32 status = IXGBE_SUCCESS; 511 512 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 513 (hw, firmware_version), 514 IXGBE_NOT_IMPLEMENTED); 515 return status; 516 } 517 518 /** 519 * ixgbe_read_phy_reg - Read PHY register 520 * @hw: pointer to hardware structure 521 * @reg_addr: 32 bit address of PHY register to read 522 * @phy_data: Pointer to read data from PHY register 523 * 524 * Reads a value from a specified PHY register 525 **/ 526 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 527 u16 *phy_data) 528 { 529 if (hw->phy.id == 0) 530 ixgbe_identify_phy(hw); 531 532 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 533 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 534 } 535 536 /** 537 * ixgbe_write_phy_reg - Write PHY register 538 * @hw: pointer to hardware structure 539 * @reg_addr: 32 bit PHY register to write 540 * @phy_data: Data to write to the PHY register 541 * 542 * Writes a value to specified PHY register 543 **/ 544 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 545 u16 phy_data) 546 { 547 if (hw->phy.id == 0) 548 ixgbe_identify_phy(hw); 549 550 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 551 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 552 } 553 554 /** 555 * ixgbe_setup_phy_link - Restart PHY autoneg 556 * @hw: pointer to hardware structure 557 * 558 * Restart autonegotiation and PHY and waits for completion. 559 **/ 560 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 561 { 562 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 563 IXGBE_NOT_IMPLEMENTED); 564 } 565 566 /** 567 * ixgbe_setup_internal_phy - Configure integrated PHY 568 * @hw: pointer to hardware structure 569 * 570 * Reconfigure the integrated PHY in order to enable talk to the external PHY. 571 * Returns success if not implemented, since nothing needs to be done in this 572 * case. 573 */ 574 s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw) 575 { 576 return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw), 577 IXGBE_SUCCESS); 578 } 579 580 /** 581 * ixgbe_check_phy_link - Determine link and speed status 582 * @hw: pointer to hardware structure 583 * 584 * Reads a PHY register to determine if link is up and the current speed for 585 * the PHY. 586 **/ 587 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 588 bool *link_up) 589 { 590 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 591 link_up), IXGBE_NOT_IMPLEMENTED); 592 } 593 594 /** 595 * ixgbe_setup_phy_link_speed - Set auto advertise 596 * @hw: pointer to hardware structure 597 * @speed: new link speed 598 * 599 * Sets the auto advertised capabilities 600 **/ 601 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 602 bool autoneg_wait_to_complete) 603 { 604 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 605 autoneg_wait_to_complete), 606 IXGBE_NOT_IMPLEMENTED); 607 } 608 609 /** 610 * ixgbe_set_phy_power - Control the phy power state 611 * @hw: pointer to hardware structure 612 * @on: true for on, false for off 613 */ 614 s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on) 615 { 616 return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on), 617 IXGBE_NOT_IMPLEMENTED); 618 } 619 620 /** 621 * ixgbe_check_link - Get link and speed status 622 * @hw: pointer to hardware structure 623 * 624 * Reads the links register to determine if link is up and the current speed 625 **/ 626 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 627 bool *link_up, bool link_up_wait_to_complete) 628 { 629 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 630 link_up, link_up_wait_to_complete), 631 IXGBE_NOT_IMPLEMENTED); 632 } 633 634 /** 635 * ixgbe_disable_tx_laser - Disable Tx laser 636 * @hw: pointer to hardware structure 637 * 638 * If the driver needs to disable the laser on SFI optics. 639 **/ 640 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 641 { 642 if (hw->mac.ops.disable_tx_laser) 643 hw->mac.ops.disable_tx_laser(hw); 644 } 645 646 /** 647 * ixgbe_enable_tx_laser - Enable Tx laser 648 * @hw: pointer to hardware structure 649 * 650 * If the driver needs to enable the laser on SFI optics. 651 **/ 652 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 653 { 654 if (hw->mac.ops.enable_tx_laser) 655 hw->mac.ops.enable_tx_laser(hw); 656 } 657 658 /** 659 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 660 * @hw: pointer to hardware structure 661 * 662 * When the driver changes the link speeds that it can support then 663 * flap the tx laser to alert the link partner to start autotry 664 * process on its end. 665 **/ 666 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 667 { 668 if (hw->mac.ops.flap_tx_laser) 669 hw->mac.ops.flap_tx_laser(hw); 670 } 671 672 /** 673 * ixgbe_setup_link - Set link speed 674 * @hw: pointer to hardware structure 675 * @speed: new link speed 676 * 677 * Configures link settings. Restarts the link. 678 * Performs autonegotiation if needed. 679 **/ 680 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 681 bool autoneg_wait_to_complete) 682 { 683 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 684 autoneg_wait_to_complete), 685 IXGBE_NOT_IMPLEMENTED); 686 } 687 688 /** 689 * ixgbe_setup_mac_link - Set link speed 690 * @hw: pointer to hardware structure 691 * @speed: new link speed 692 * 693 * Configures link settings. Restarts the link. 694 * Performs autonegotiation if needed. 695 **/ 696 s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 697 bool autoneg_wait_to_complete) 698 { 699 return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed, 700 autoneg_wait_to_complete), 701 IXGBE_NOT_IMPLEMENTED); 702 } 703 704 /** 705 * ixgbe_get_link_capabilities - Returns link capabilities 706 * @hw: pointer to hardware structure 707 * 708 * Determines the link capabilities of the current configuration. 709 **/ 710 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 711 bool *autoneg) 712 { 713 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 714 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 715 } 716 717 /** 718 * ixgbe_led_on - Turn on LEDs 719 * @hw: pointer to hardware structure 720 * @index: led number to turn on 721 * 722 * Turns on the software controllable LEDs. 723 **/ 724 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 725 { 726 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 727 IXGBE_NOT_IMPLEMENTED); 728 } 729 730 /** 731 * ixgbe_led_off - Turn off LEDs 732 * @hw: pointer to hardware structure 733 * @index: led number to turn off 734 * 735 * Turns off the software controllable LEDs. 736 **/ 737 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 738 { 739 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 740 IXGBE_NOT_IMPLEMENTED); 741 } 742 743 /** 744 * ixgbe_blink_led_start - Blink LEDs 745 * @hw: pointer to hardware structure 746 * @index: led number to blink 747 * 748 * Blink LED based on index. 749 **/ 750 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 751 { 752 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 753 IXGBE_NOT_IMPLEMENTED); 754 } 755 756 /** 757 * ixgbe_blink_led_stop - Stop blinking LEDs 758 * @hw: pointer to hardware structure 759 * 760 * Stop blinking LED based on index. 761 **/ 762 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 763 { 764 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 765 IXGBE_NOT_IMPLEMENTED); 766 } 767 768 /** 769 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 770 * @hw: pointer to hardware structure 771 * 772 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 773 * ixgbe_hw struct in order to set up EEPROM access. 774 **/ 775 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 776 { 777 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 778 IXGBE_NOT_IMPLEMENTED); 779 } 780 781 782 /** 783 * ixgbe_write_eeprom - Write word to EEPROM 784 * @hw: pointer to hardware structure 785 * @offset: offset within the EEPROM to be written to 786 * @data: 16 bit word to be written to the EEPROM 787 * 788 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 789 * called after this function, the EEPROM will most likely contain an 790 * invalid checksum. 791 **/ 792 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 793 { 794 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 795 IXGBE_NOT_IMPLEMENTED); 796 } 797 798 /** 799 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 800 * @hw: pointer to hardware structure 801 * @offset: offset within the EEPROM to be written to 802 * @data: 16 bit word(s) to be written to the EEPROM 803 * @words: number of words 804 * 805 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 806 * called after this function, the EEPROM will most likely contain an 807 * invalid checksum. 808 **/ 809 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 810 u16 *data) 811 { 812 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 813 (hw, offset, words, data), 814 IXGBE_NOT_IMPLEMENTED); 815 } 816 817 /** 818 * ixgbe_read_eeprom - Read word from EEPROM 819 * @hw: pointer to hardware structure 820 * @offset: offset within the EEPROM to be read 821 * @data: read 16 bit value from EEPROM 822 * 823 * Reads 16 bit value from EEPROM 824 **/ 825 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 826 { 827 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 828 IXGBE_NOT_IMPLEMENTED); 829 } 830 831 /** 832 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 833 * @hw: pointer to hardware structure 834 * @offset: offset within the EEPROM to be read 835 * @data: read 16 bit word(s) from EEPROM 836 * @words: number of words 837 * 838 * Reads 16 bit word(s) from EEPROM 839 **/ 840 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 841 u16 words, u16 *data) 842 { 843 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 844 (hw, offset, words, data), 845 IXGBE_NOT_IMPLEMENTED); 846 } 847 848 /** 849 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 850 * @hw: pointer to hardware structure 851 * @checksum_val: calculated checksum 852 * 853 * Performs checksum calculation and validates the EEPROM checksum 854 **/ 855 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 856 { 857 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 858 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 859 } 860 861 /** 862 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 863 * @hw: pointer to hardware structure 864 **/ 865 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 866 { 867 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 868 IXGBE_NOT_IMPLEMENTED); 869 } 870 871 /** 872 * ixgbe_insert_mac_addr - Find a RAR for this mac address 873 * @hw: pointer to hardware structure 874 * @addr: Address to put into receive address register 875 * @vmdq: VMDq pool to assign 876 * 877 * Puts an ethernet address into a receive address register, or 878 * finds the rar that it is aleady in; adds to the pool list 879 **/ 880 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 881 { 882 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 883 (hw, addr, vmdq), 884 IXGBE_NOT_IMPLEMENTED); 885 } 886 887 /** 888 * ixgbe_set_rar - Set Rx address register 889 * @hw: pointer to hardware structure 890 * @index: Receive address register to write 891 * @addr: Address to put into receive address register 892 * @vmdq: VMDq "set" 893 * @enable_addr: set flag that address is active 894 * 895 * Puts an ethernet address into a receive address register. 896 **/ 897 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 898 u32 enable_addr) 899 { 900 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 901 enable_addr), IXGBE_NOT_IMPLEMENTED); 902 } 903 904 /** 905 * ixgbe_clear_rar - Clear Rx address register 906 * @hw: pointer to hardware structure 907 * @index: Receive address register to write 908 * 909 * Puts an ethernet address into a receive address register. 910 **/ 911 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 912 { 913 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 914 IXGBE_NOT_IMPLEMENTED); 915 } 916 917 /** 918 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 919 * @hw: pointer to hardware structure 920 * @rar: receive address register index to associate with VMDq index 921 * @vmdq: VMDq set or pool index 922 **/ 923 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 924 { 925 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 926 IXGBE_NOT_IMPLEMENTED); 927 928 } 929 930 /** 931 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address 932 * @hw: pointer to hardware structure 933 * @vmdq: VMDq default pool index 934 **/ 935 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) 936 { 937 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac, 938 (hw, vmdq), IXGBE_NOT_IMPLEMENTED); 939 } 940 941 /** 942 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 943 * @hw: pointer to hardware structure 944 * @rar: receive address register index to disassociate with VMDq index 945 * @vmdq: VMDq set or pool index 946 **/ 947 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 948 { 949 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 950 IXGBE_NOT_IMPLEMENTED); 951 } 952 953 /** 954 * ixgbe_init_rx_addrs - Initializes receive address filters. 955 * @hw: pointer to hardware structure 956 * 957 * Places the MAC address in receive address register 0 and clears the rest 958 * of the receive address registers. Clears the multicast table. Assumes 959 * the receiver is in reset when the routine is called. 960 **/ 961 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 962 { 963 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 964 IXGBE_NOT_IMPLEMENTED); 965 } 966 967 /** 968 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 969 * @hw: pointer to hardware structure 970 **/ 971 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 972 { 973 return hw->mac.num_rar_entries; 974 } 975 976 /** 977 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 978 * @hw: pointer to hardware structure 979 * @addr_list: the list of new multicast addresses 980 * @addr_count: number of addresses 981 * @func: iterator function to walk the multicast address list 982 * 983 * The given list replaces any existing list. Clears the secondary addrs from 984 * receive address registers. Uses unused receive address registers for the 985 * first secondary addresses, and falls back to promiscuous mode as needed. 986 **/ 987 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 988 u32 addr_count, ixgbe_mc_addr_itr func) 989 { 990 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 991 addr_list, addr_count, func), 992 IXGBE_NOT_IMPLEMENTED); 993 } 994 995 /** 996 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 997 * @hw: pointer to hardware structure 998 * @mc_addr_list: the list of new multicast addresses 999 * @mc_addr_count: number of addresses 1000 * @func: iterator function to walk the multicast address list 1001 * 1002 * The given list replaces any existing list. Clears the MC addrs from receive 1003 * address registers and the multicast table. Uses unused receive address 1004 * registers for the first multicast addresses, and hashes the rest into the 1005 * multicast table. 1006 **/ 1007 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 1008 u32 mc_addr_count, ixgbe_mc_addr_itr func, 1009 bool clear) 1010 { 1011 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 1012 mc_addr_list, mc_addr_count, func, clear), 1013 IXGBE_NOT_IMPLEMENTED); 1014 } 1015 1016 /** 1017 * ixgbe_enable_mc - Enable multicast address in RAR 1018 * @hw: pointer to hardware structure 1019 * 1020 * Enables multicast address in RAR and the use of the multicast hash table. 1021 **/ 1022 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 1023 { 1024 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 1025 IXGBE_NOT_IMPLEMENTED); 1026 } 1027 1028 /** 1029 * ixgbe_disable_mc - Disable multicast address in RAR 1030 * @hw: pointer to hardware structure 1031 * 1032 * Disables multicast address in RAR and the use of the multicast hash table. 1033 **/ 1034 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 1035 { 1036 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 1037 IXGBE_NOT_IMPLEMENTED); 1038 } 1039 1040 /** 1041 * ixgbe_clear_vfta - Clear VLAN filter table 1042 * @hw: pointer to hardware structure 1043 * 1044 * Clears the VLAN filer table, and the VMDq index associated with the filter 1045 **/ 1046 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 1047 { 1048 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 1049 IXGBE_NOT_IMPLEMENTED); 1050 } 1051 1052 /** 1053 * ixgbe_set_vfta - Set VLAN filter table 1054 * @hw: pointer to hardware structure 1055 * @vlan: VLAN id to write to VLAN filter 1056 * @vind: VMDq output index that maps queue to VLAN id in VFTA 1057 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 1058 * 1059 * Turn on/off specified VLAN in the VLAN filter table. 1060 **/ 1061 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 1062 { 1063 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 1064 vlan_on), IXGBE_NOT_IMPLEMENTED); 1065 } 1066 1067 /** 1068 * ixgbe_set_vlvf - Set VLAN Pool Filter 1069 * @hw: pointer to hardware structure 1070 * @vlan: VLAN id to write to VLAN filter 1071 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 1072 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 1073 * @vfta_changed: pointer to boolean flag which indicates whether VFTA 1074 * should be changed 1075 * 1076 * Turn on/off specified bit in VLVF table. 1077 **/ 1078 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1079 bool *vfta_changed) 1080 { 1081 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 1082 vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED); 1083 } 1084 1085 /** 1086 * ixgbe_fc_enable - Enable flow control 1087 * @hw: pointer to hardware structure 1088 * 1089 * Configures the flow control settings based on SW configuration. 1090 **/ 1091 s32 ixgbe_fc_enable(struct ixgbe_hw *hw) 1092 { 1093 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), 1094 IXGBE_NOT_IMPLEMENTED); 1095 } 1096 1097 /** 1098 * ixgbe_setup_fc - Set up flow control 1099 * @hw: pointer to hardware structure 1100 * 1101 * Called at init time to set up flow control. 1102 **/ 1103 s32 ixgbe_setup_fc(struct ixgbe_hw *hw) 1104 { 1105 return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw), 1106 IXGBE_NOT_IMPLEMENTED); 1107 } 1108 1109 /** 1110 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 1111 * @hw: pointer to hardware structure 1112 * @maj: driver major number to be sent to firmware 1113 * @min: driver minor number to be sent to firmware 1114 * @build: driver build number to be sent to firmware 1115 * @ver: driver version number to be sent to firmware 1116 **/ 1117 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, 1118 u8 ver) 1119 { 1120 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min, 1121 build, ver), IXGBE_NOT_IMPLEMENTED); 1122 } 1123 1124 1125 /** 1126 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data 1127 * @hw: pointer to hardware structure 1128 * 1129 * Updates the temperatures in mac.thermal_sensor_data 1130 **/ 1131 s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw) 1132 { 1133 return ixgbe_call_func(hw, hw->mac.ops.get_thermal_sensor_data, (hw), 1134 IXGBE_NOT_IMPLEMENTED); 1135 } 1136 1137 /** 1138 * ixgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds 1139 * @hw: pointer to hardware structure 1140 * 1141 * Inits the thermal sensor thresholds according to the NVM map 1142 **/ 1143 s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw) 1144 { 1145 return ixgbe_call_func(hw, hw->mac.ops.init_thermal_sensor_thresh, (hw), 1146 IXGBE_NOT_IMPLEMENTED); 1147 } 1148 1149 /** 1150 * ixgbe_dmac_config - Configure DMA Coalescing registers. 1151 * @hw: pointer to hardware structure 1152 * 1153 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1154 * When disabling dmac, dmac enable dmac bit is cleared. 1155 **/ 1156 s32 ixgbe_dmac_config(struct ixgbe_hw *hw) 1157 { 1158 return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw), 1159 IXGBE_NOT_IMPLEMENTED); 1160 } 1161 1162 /** 1163 * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers. 1164 * @hw: pointer to hardware structure 1165 * 1166 * Disables dmac, updates per TC settings, and then enable dmac. 1167 **/ 1168 s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw) 1169 { 1170 return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw), 1171 IXGBE_NOT_IMPLEMENTED); 1172 } 1173 1174 /** 1175 * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers. 1176 * @hw: pointer to hardware structure 1177 * 1178 * Configure DMA coalescing threshold per TC and set high priority bit for 1179 * FCOE TC. The dmac enable bit must be cleared before configuring. 1180 **/ 1181 s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw) 1182 { 1183 return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw), 1184 IXGBE_NOT_IMPLEMENTED); 1185 } 1186 1187 /** 1188 * ixgbe_setup_eee - Enable/disable EEE support 1189 * @hw: pointer to the HW structure 1190 * @enable_eee: boolean flag to enable EEE 1191 * 1192 * Enable/disable EEE based on enable_ee flag. 1193 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 1194 * are modified. 1195 * 1196 **/ 1197 s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee) 1198 { 1199 return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee), 1200 IXGBE_NOT_IMPLEMENTED); 1201 } 1202 1203 /** 1204 * ixgbe_set_source_address_pruning - Enable/Disable source address pruning 1205 * @hw: pointer to hardware structure 1206 * @enbale: enable or disable source address pruning 1207 * @pool: Rx pool - Rx pool to toggle source address pruning 1208 **/ 1209 void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, 1210 unsigned int pool) 1211 { 1212 if (hw->mac.ops.set_source_address_pruning) 1213 hw->mac.ops.set_source_address_pruning(hw, enable, pool); 1214 } 1215 1216 /** 1217 * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing 1218 * @hw: pointer to hardware structure 1219 * @enable: enable or disable switch for Ethertype anti-spoofing 1220 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1221 * 1222 **/ 1223 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 1224 { 1225 if (hw->mac.ops.set_ethertype_anti_spoofing) 1226 hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf); 1227 } 1228 1229 /** 1230 * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register 1231 * @hw: pointer to hardware structure 1232 * @reg_addr: 32 bit address of PHY register to read 1233 * @device_type: type of device you want to communicate with 1234 * @phy_data: Pointer to read data from PHY register 1235 * 1236 * Reads a value from a specified PHY register 1237 **/ 1238 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1239 u32 device_type, u32 *phy_data) 1240 { 1241 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, 1242 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1243 } 1244 1245 /** 1246 * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband 1247 * @hw: pointer to hardware structure 1248 * @reg_addr: 32 bit PHY register to write 1249 * @device_type: type of device you want to communicate with 1250 * @phy_data: Data to write to the PHY register 1251 * 1252 * Writes a value to specified PHY register 1253 **/ 1254 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1255 u32 device_type, u32 phy_data) 1256 { 1257 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, 1258 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1259 } 1260 1261 /** 1262 * ixgbe_disable_mdd - Disable malicious driver detection 1263 * @hw: pointer to hardware structure 1264 * 1265 **/ 1266 void ixgbe_disable_mdd(struct ixgbe_hw *hw) 1267 { 1268 if (hw->mac.ops.disable_mdd) 1269 hw->mac.ops.disable_mdd(hw); 1270 } 1271 1272 /** 1273 * ixgbe_enable_mdd - Enable malicious driver detection 1274 * @hw: pointer to hardware structure 1275 * 1276 **/ 1277 void ixgbe_enable_mdd(struct ixgbe_hw *hw) 1278 { 1279 if (hw->mac.ops.enable_mdd) 1280 hw->mac.ops.enable_mdd(hw); 1281 } 1282 1283 /** 1284 * ixgbe_mdd_event - Handle malicious driver detection event 1285 * @hw: pointer to hardware structure 1286 * @vf_bitmap: vf bitmap of malicious vfs 1287 * 1288 **/ 1289 void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap) 1290 { 1291 if (hw->mac.ops.mdd_event) 1292 hw->mac.ops.mdd_event(hw, vf_bitmap); 1293 } 1294 1295 /** 1296 * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver 1297 * detection event 1298 * @hw: pointer to hardware structure 1299 * @vf: vf index 1300 * 1301 **/ 1302 void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf) 1303 { 1304 if (hw->mac.ops.restore_mdd_vf) 1305 hw->mac.ops.restore_mdd_vf(hw, vf); 1306 } 1307 1308 /** 1309 * ixgbe_enter_lplu - Transition to low power states 1310 * @hw: pointer to hardware structure 1311 * 1312 * Configures Low Power Link Up on transition to low power states 1313 * (from D0 to non-D0). 1314 **/ 1315 s32 ixgbe_enter_lplu(struct ixgbe_hw *hw) 1316 { 1317 return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw), 1318 IXGBE_NOT_IMPLEMENTED); 1319 } 1320 1321 /** 1322 * ixgbe_handle_lasi - Handle external Base T PHY interrupt 1323 * @hw: pointer to hardware structure 1324 * 1325 * Handle external Base T PHY interrupt. If high temperature 1326 * failure alarm then return error, else if link status change 1327 * then setup internal/external PHY link 1328 * 1329 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1330 * failure alarm, else return PHY access status. 1331 */ 1332 s32 ixgbe_handle_lasi(struct ixgbe_hw *hw) 1333 { 1334 return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw), 1335 IXGBE_NOT_IMPLEMENTED); 1336 } 1337 1338 /** 1339 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 1340 * @hw: pointer to hardware structure 1341 * @reg: analog register to read 1342 * @val: read value 1343 * 1344 * Performs write operation to analog register specified. 1345 **/ 1346 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 1347 { 1348 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1349 val), IXGBE_NOT_IMPLEMENTED); 1350 } 1351 1352 /** 1353 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1354 * @hw: pointer to hardware structure 1355 * @reg: analog register to write 1356 * @val: value to write 1357 * 1358 * Performs write operation to Atlas analog register specified. 1359 **/ 1360 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1361 { 1362 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1363 val), IXGBE_NOT_IMPLEMENTED); 1364 } 1365 1366 /** 1367 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1368 * @hw: pointer to hardware structure 1369 * 1370 * Initializes the Unicast Table Arrays to zero on device load. This 1371 * is part of the Rx init addr execution path. 1372 **/ 1373 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1374 { 1375 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1376 IXGBE_NOT_IMPLEMENTED); 1377 } 1378 1379 /** 1380 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1381 * @hw: pointer to hardware structure 1382 * @byte_offset: byte offset to read 1383 * @dev_addr: I2C bus address to read from 1384 * @data: value read 1385 * 1386 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1387 **/ 1388 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1389 u8 *data) 1390 { 1391 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1392 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1393 } 1394 1395 /** 1396 * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address 1397 * @hw: pointer to hardware structure 1398 * @byte_offset: byte offset to read 1399 * @dev_addr: I2C bus address to read from 1400 * @data: value read 1401 * 1402 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1403 **/ 1404 s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1405 u8 dev_addr, u8 *data) 1406 { 1407 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked, 1408 (hw, byte_offset, dev_addr, data), 1409 IXGBE_NOT_IMPLEMENTED); 1410 } 1411 1412 /** 1413 * ixgbe_read_i2c_combined - Perform I2C read combined operation 1414 * @hw: pointer to the hardware structure 1415 * @addr: I2C bus address to read from 1416 * @reg: I2C device register to read from 1417 * @val: pointer to location to receive read value 1418 * 1419 * Returns an error code on error. 1420 */ 1421 s32 ixgbe_read_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1422 { 1423 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined, (hw, addr, 1424 reg, val), IXGBE_NOT_IMPLEMENTED); 1425 } 1426 1427 /** 1428 * ixgbe_read_i2c_combined_unlocked - Perform I2C read combined operation 1429 * @hw: pointer to the hardware structure 1430 * @addr: I2C bus address to read from 1431 * @reg: I2C device register to read from 1432 * @val: pointer to location to receive read value 1433 * 1434 * Returns an error code on error. 1435 **/ 1436 s32 ixgbe_read_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, 1437 u16 *val) 1438 { 1439 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined_unlocked, 1440 (hw, addr, reg, val), 1441 IXGBE_NOT_IMPLEMENTED); 1442 } 1443 1444 /** 1445 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1446 * @hw: pointer to hardware structure 1447 * @byte_offset: byte offset to write 1448 * @dev_addr: I2C bus address to write to 1449 * @data: value to write 1450 * 1451 * Performs byte write operation to SFP module's EEPROM over I2C interface 1452 * at a specified device address. 1453 **/ 1454 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1455 u8 data) 1456 { 1457 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1458 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1459 } 1460 1461 /** 1462 * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1463 * @hw: pointer to hardware structure 1464 * @byte_offset: byte offset to write 1465 * @dev_addr: I2C bus address to write to 1466 * @data: value to write 1467 * 1468 * Performs byte write operation to SFP module's EEPROM over I2C interface 1469 * at a specified device address. 1470 **/ 1471 s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1472 u8 dev_addr, u8 data) 1473 { 1474 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked, 1475 (hw, byte_offset, dev_addr, data), 1476 IXGBE_NOT_IMPLEMENTED); 1477 } 1478 1479 /** 1480 * ixgbe_write_i2c_combined - Perform I2C write combined operation 1481 * @hw: pointer to the hardware structure 1482 * @addr: I2C bus address to write to 1483 * @reg: I2C device register to write to 1484 * @val: value to write 1485 * 1486 * Returns an error code on error. 1487 */ 1488 s32 ixgbe_write_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1489 { 1490 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined, (hw, addr, 1491 reg, val), IXGBE_NOT_IMPLEMENTED); 1492 } 1493 1494 /** 1495 * ixgbe_write_i2c_combined_unlocked - Perform I2C write combined operation 1496 * @hw: pointer to the hardware structure 1497 * @addr: I2C bus address to write to 1498 * @reg: I2C device register to write to 1499 * @val: value to write 1500 * 1501 * Returns an error code on error. 1502 **/ 1503 s32 ixgbe_write_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, 1504 u16 val) 1505 { 1506 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined_unlocked, 1507 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1508 } 1509 1510 /** 1511 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1512 * @hw: pointer to hardware structure 1513 * @byte_offset: EEPROM byte offset to write 1514 * @eeprom_data: value to write 1515 * 1516 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1517 **/ 1518 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1519 u8 byte_offset, u8 eeprom_data) 1520 { 1521 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1522 (hw, byte_offset, eeprom_data), 1523 IXGBE_NOT_IMPLEMENTED); 1524 } 1525 1526 /** 1527 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1528 * @hw: pointer to hardware structure 1529 * @byte_offset: EEPROM byte offset to read 1530 * @eeprom_data: value read 1531 * 1532 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1533 **/ 1534 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1535 { 1536 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1537 (hw, byte_offset, eeprom_data), 1538 IXGBE_NOT_IMPLEMENTED); 1539 } 1540 1541 /** 1542 * ixgbe_get_supported_physical_layer - Returns physical layer type 1543 * @hw: pointer to hardware structure 1544 * 1545 * Determines physical layer capabilities of the current configuration. 1546 **/ 1547 u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1548 { 1549 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1550 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1551 } 1552 1553 /** 1554 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics 1555 * @hw: pointer to hardware structure 1556 * @regval: bitfield to write to the Rx DMA register 1557 * 1558 * Enables the Rx DMA unit of the device. 1559 **/ 1560 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1561 { 1562 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1563 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1564 } 1565 1566 /** 1567 * ixgbe_disable_sec_rx_path - Stops the receive data path 1568 * @hw: pointer to hardware structure 1569 * 1570 * Stops the receive data path. 1571 **/ 1572 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1573 { 1574 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1575 (hw), IXGBE_NOT_IMPLEMENTED); 1576 } 1577 1578 /** 1579 * ixgbe_enable_sec_rx_path - Enables the receive data path 1580 * @hw: pointer to hardware structure 1581 * 1582 * Enables the receive data path. 1583 **/ 1584 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1585 { 1586 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1587 (hw), IXGBE_NOT_IMPLEMENTED); 1588 } 1589 1590 /** 1591 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1592 * @hw: pointer to hardware structure 1593 * @mask: Mask to specify which semaphore to acquire 1594 * 1595 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1596 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1597 **/ 1598 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1599 { 1600 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1601 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1602 } 1603 1604 /** 1605 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1606 * @hw: pointer to hardware structure 1607 * @mask: Mask to specify which semaphore to release 1608 * 1609 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1610 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1611 **/ 1612 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1613 { 1614 if (hw->mac.ops.release_swfw_sync) 1615 hw->mac.ops.release_swfw_sync(hw, mask); 1616 } 1617 1618 1619 void ixgbe_disable_rx(struct ixgbe_hw *hw) 1620 { 1621 if (hw->mac.ops.disable_rx) 1622 hw->mac.ops.disable_rx(hw); 1623 } 1624 1625 void ixgbe_enable_rx(struct ixgbe_hw *hw) 1626 { 1627 if (hw->mac.ops.enable_rx) 1628 hw->mac.ops.enable_rx(hw); 1629 } 1630 1631 /** 1632 * ixgbe_set_rate_select_speed - Set module link speed 1633 * @hw: pointer to hardware structure 1634 * @speed: link speed to set 1635 * 1636 * Set module link speed via the rate select. 1637 */ 1638 void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 1639 { 1640 if (hw->mac.ops.set_rate_select_speed) 1641 hw->mac.ops.set_rate_select_speed(hw, speed); 1642 } 1643