1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2019 Intel Corporation 3 */ 4 5 #include <stdint.h> 6 7 #include <rte_bus_pci.h> 8 #include <rte_ethdev.h> 9 #include <rte_pci.h> 10 #include <rte_malloc.h> 11 12 #include <rte_mbuf.h> 13 #include <rte_sched.h> 14 #include <ethdev_driver.h> 15 16 #include <rte_io.h> 17 #include <rte_rawdev.h> 18 #include <rte_rawdev_pmd.h> 19 #include <rte_bus_ifpga.h> 20 #include <ifpga_common.h> 21 #include <ifpga_logs.h> 22 #include <ifpga_rawdev.h> 23 24 #include "ipn3ke_rawdev_api.h" 25 #include "ipn3ke_flow.h" 26 #include "ipn3ke_logs.h" 27 #include "ipn3ke_ethdev.h" 28 29 static const struct rte_afu_uuid afu_uuid_ipn3ke_map[] = { 30 { MAP_UUID_10G_LOW, MAP_UUID_10G_HIGH }, 31 { IPN3KE_UUID_10G_LOW, IPN3KE_UUID_10G_HIGH }, 32 { IPN3KE_UUID_VBNG_LOW, IPN3KE_UUID_VBNG_HIGH}, 33 { IPN3KE_UUID_25G_LOW, IPN3KE_UUID_25G_HIGH }, 34 { 0, 0 /* sentinel */ }, 35 }; 36 37 struct ipn3ke_pub_func ipn3ke_bridge_func; 38 39 static int 40 ipn3ke_indirect_read(struct ipn3ke_hw *hw, uint32_t *rd_data, 41 uint32_t addr, uint32_t dev_sel, uint32_t eth_group_sel) 42 { 43 uint32_t i, try_cnt; 44 uint64_t indirect_value; 45 volatile void *indirect_addrs; 46 uint64_t target_addr; 47 uint64_t read_data = 0; 48 49 if (eth_group_sel != 0 && eth_group_sel != 1) 50 return -1; 51 52 target_addr = addr | dev_sel << 17; 53 54 indirect_value = RCMD | target_addr << 32; 55 indirect_addrs = hw->eth_group_bar[eth_group_sel] + 0x10; 56 57 rte_delay_us(10); 58 59 rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs); 60 61 i = 0; 62 try_cnt = 10; 63 indirect_addrs = hw->eth_group_bar[eth_group_sel] + 64 0x18; 65 do { 66 read_data = rte_read64(indirect_addrs); 67 if ((read_data >> 32) == 1) 68 break; 69 i++; 70 } while (i <= try_cnt); 71 if (i > try_cnt) 72 return -1; 73 74 *rd_data = rte_le_to_cpu_32(read_data); 75 return 0; 76 } 77 78 static int 79 ipn3ke_indirect_write(struct ipn3ke_hw *hw, uint32_t wr_data, 80 uint32_t addr, uint32_t dev_sel, uint32_t eth_group_sel) 81 { 82 volatile void *indirect_addrs; 83 uint64_t indirect_value; 84 uint64_t target_addr; 85 86 if (eth_group_sel != 0 && eth_group_sel != 1) 87 return -1; 88 89 target_addr = addr | dev_sel << 17; 90 91 indirect_value = WCMD | target_addr << 32 | wr_data; 92 indirect_addrs = hw->eth_group_bar[eth_group_sel] + 0x10; 93 94 rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs); 95 return 0; 96 } 97 98 static int 99 ipn3ke_indirect_mac_read(struct ipn3ke_hw *hw, uint32_t *rd_data, 100 uint32_t addr, uint32_t mac_num, uint32_t eth_group_sel) 101 { 102 uint32_t dev_sel; 103 104 if (mac_num >= hw->port_num) 105 return -1; 106 107 mac_num &= 0x7; 108 dev_sel = mac_num * 2 + 3; 109 110 return ipn3ke_indirect_read(hw, rd_data, addr, dev_sel, eth_group_sel); 111 } 112 113 static int 114 ipn3ke_indirect_mac_write(struct ipn3ke_hw *hw, uint32_t wr_data, 115 uint32_t addr, uint32_t mac_num, uint32_t eth_group_sel) 116 { 117 uint32_t dev_sel; 118 119 if (mac_num >= hw->port_num) 120 return -1; 121 122 mac_num &= 0x7; 123 dev_sel = mac_num * 2 + 3; 124 125 return ipn3ke_indirect_write(hw, wr_data, addr, dev_sel, eth_group_sel); 126 } 127 128 static void 129 ipn3ke_hw_cap_init(struct ipn3ke_hw *hw) 130 { 131 hw->hw_cap.version_number = IPN3KE_MASK_READ_REG(hw, 132 (IPN3KE_HW_BASE + 0), 0, 0xFFFF); 133 hw->hw_cap.capability_registers_block_offset = IPN3KE_MASK_READ_REG(hw, 134 (IPN3KE_HW_BASE + 0x8), 0, 0xFFFFFFFF); 135 hw->hw_cap.status_registers_block_offset = IPN3KE_MASK_READ_REG(hw, 136 (IPN3KE_HW_BASE + 0x10), 0, 0xFFFFFFFF); 137 hw->hw_cap.control_registers_block_offset = IPN3KE_MASK_READ_REG(hw, 138 (IPN3KE_HW_BASE + 0x18), 0, 0xFFFFFFFF); 139 hw->hw_cap.classify_offset = IPN3KE_MASK_READ_REG(hw, 140 (IPN3KE_HW_BASE + 0x20), 0, 0xFFFFFFFF); 141 hw->hw_cap.classy_size = IPN3KE_MASK_READ_REG(hw, 142 (IPN3KE_HW_BASE + 0x24), 0, 0xFFFF); 143 hw->hw_cap.policer_offset = IPN3KE_MASK_READ_REG(hw, 144 (IPN3KE_HW_BASE + 0x28), 0, 0xFFFFFFFF); 145 hw->hw_cap.policer_entry_size = IPN3KE_MASK_READ_REG(hw, 146 (IPN3KE_HW_BASE + 0x2C), 0, 0xFFFF); 147 hw->hw_cap.rss_key_array_offset = IPN3KE_MASK_READ_REG(hw, 148 (IPN3KE_HW_BASE + 0x30), 0, 0xFFFFFFFF); 149 hw->hw_cap.rss_key_entry_size = IPN3KE_MASK_READ_REG(hw, 150 (IPN3KE_HW_BASE + 0x34), 0, 0xFFFF); 151 hw->hw_cap.rss_indirection_table_array_offset = IPN3KE_MASK_READ_REG(hw, 152 (IPN3KE_HW_BASE + 0x38), 0, 0xFFFFFFFF); 153 hw->hw_cap.rss_indirection_table_entry_size = IPN3KE_MASK_READ_REG(hw, 154 (IPN3KE_HW_BASE + 0x3C), 0, 0xFFFF); 155 hw->hw_cap.dmac_map_offset = IPN3KE_MASK_READ_REG(hw, 156 (IPN3KE_HW_BASE + 0x40), 0, 0xFFFFFFFF); 157 hw->hw_cap.dmac_map_size = IPN3KE_MASK_READ_REG(hw, 158 (IPN3KE_HW_BASE + 0x44), 0, 0xFFFF); 159 hw->hw_cap.qm_offset = IPN3KE_MASK_READ_REG(hw, 160 (IPN3KE_HW_BASE + 0x48), 0, 0xFFFFFFFF); 161 hw->hw_cap.qm_size = IPN3KE_MASK_READ_REG(hw, 162 (IPN3KE_HW_BASE + 0x4C), 0, 0xFFFF); 163 hw->hw_cap.ccb_offset = IPN3KE_MASK_READ_REG(hw, 164 (IPN3KE_HW_BASE + 0x50), 0, 0xFFFFFFFF); 165 hw->hw_cap.ccb_entry_size = IPN3KE_MASK_READ_REG(hw, 166 (IPN3KE_HW_BASE + 0x54), 0, 0xFFFF); 167 hw->hw_cap.qos_offset = IPN3KE_MASK_READ_REG(hw, 168 (IPN3KE_HW_BASE + 0x58), 0, 0xFFFFFFFF); 169 hw->hw_cap.qos_size = IPN3KE_MASK_READ_REG(hw, 170 (IPN3KE_HW_BASE + 0x5C), 0, 0xFFFF); 171 172 hw->hw_cap.num_rx_flow = IPN3KE_MASK_READ_REG(hw, 173 IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET, 174 0, 0xFFFF); 175 hw->hw_cap.num_rss_blocks = IPN3KE_MASK_READ_REG(hw, 176 IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET, 177 4, 0xFFFF); 178 hw->hw_cap.num_dmac_map = IPN3KE_MASK_READ_REG(hw, 179 IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET, 180 8, 0xFFFF); 181 hw->hw_cap.num_tx_flow = IPN3KE_MASK_READ_REG(hw, 182 IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET, 183 0xC, 0xFFFF); 184 hw->hw_cap.num_smac_map = IPN3KE_MASK_READ_REG(hw, 185 IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET, 186 0x10, 0xFFFF); 187 188 hw->hw_cap.link_speed_mbps = IPN3KE_MASK_READ_REG(hw, 189 IPN3KE_STATUS_REGISTERS_BLOCK_OFFSET, 190 0, 0xFFFFF); 191 } 192 193 static int 194 ipn3ke_vbng_init_done(struct ipn3ke_hw *hw) 195 { 196 uint32_t timeout = 10000; 197 while (timeout > 0) { 198 if (IPN3KE_READ_REG(hw, IPN3KE_VBNG_INIT_STS) 199 == IPN3KE_VBNG_INIT_DONE) 200 break; 201 rte_delay_us(1000); 202 timeout--; 203 } 204 205 if (!timeout) { 206 IPN3KE_AFU_PMD_ERR("IPN3KE vBNG INIT timeout.\n"); 207 return -1; 208 } 209 210 return 0; 211 } 212 213 static uint32_t 214 ipn3ke_mtu_cal(uint32_t tx, uint32_t rx) 215 { 216 uint32_t tmp; 217 tmp = RTE_MIN(tx, rx); 218 tmp = RTE_MAX(tmp, (uint32_t)RTE_ETHER_MIN_MTU); 219 tmp = RTE_MIN(tmp, (uint32_t)(IPN3KE_MAC_FRAME_SIZE_MAX - 220 IPN3KE_ETH_OVERHEAD)); 221 return tmp; 222 } 223 224 static void 225 ipn3ke_mtu_set(struct ipn3ke_hw *hw, uint32_t mac_num, 226 uint32_t eth_group_sel, uint32_t txaddr, uint32_t rxaddr) 227 { 228 uint32_t tx; 229 uint32_t rx; 230 uint32_t tmp; 231 232 if (!(*hw->f_mac_read) || !(*hw->f_mac_write)) 233 return; 234 235 (*hw->f_mac_read)(hw, 236 &tx, 237 txaddr, 238 mac_num, 239 eth_group_sel); 240 241 (*hw->f_mac_read)(hw, 242 &rx, 243 rxaddr, 244 mac_num, 245 eth_group_sel); 246 247 tmp = ipn3ke_mtu_cal(tx, rx); 248 249 (*hw->f_mac_write)(hw, 250 tmp, 251 txaddr, 252 mac_num, 253 eth_group_sel); 254 255 (*hw->f_mac_write)(hw, 256 tmp, 257 rxaddr, 258 mac_num, 259 eth_group_sel); 260 } 261 262 static void 263 ipn3ke_10G_mtu_setup(struct ipn3ke_hw *hw, uint32_t mac_num, 264 uint32_t eth_group_sel) 265 { 266 ipn3ke_mtu_set(hw, mac_num, eth_group_sel, 267 IPN3KE_10G_TX_FRAME_MAXLENGTH, IPN3KE_10G_RX_FRAME_MAXLENGTH); 268 } 269 270 static void 271 ipn3ke_25G_mtu_setup(struct ipn3ke_hw *hw, uint32_t mac_num, 272 uint32_t eth_group_sel) 273 { 274 ipn3ke_mtu_set(hw, mac_num, eth_group_sel, 275 IPN3KE_25G_MAX_TX_SIZE_CONFIG, IPN3KE_25G_MAX_RX_SIZE_CONFIG); 276 } 277 278 static void 279 ipn3ke_mtu_setup(struct ipn3ke_hw *hw) 280 { 281 int i; 282 if (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) { 283 for (i = 0; i < hw->port_num; i++) { 284 ipn3ke_10G_mtu_setup(hw, i, 0); 285 ipn3ke_10G_mtu_setup(hw, i, 1); 286 } 287 } else if (hw->retimer.mac_type == 288 IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) { 289 for (i = 0; i < hw->port_num; i++) { 290 ipn3ke_25G_mtu_setup(hw, i, 0); 291 ipn3ke_25G_mtu_setup(hw, i, 1); 292 } 293 } 294 } 295 296 static int 297 ipn3ke_hw_init(struct rte_afu_device *afu_dev, 298 struct ipn3ke_hw *hw) 299 { 300 struct rte_rawdev *rawdev; 301 int ret; 302 int i; 303 uint64_t port_num, mac_type, index; 304 305 rawdev = afu_dev->rawdev; 306 307 hw->afu_id.uuid.uuid_low = afu_dev->id.uuid.uuid_low; 308 hw->afu_id.uuid.uuid_high = afu_dev->id.uuid.uuid_high; 309 hw->afu_id.port = afu_dev->id.port; 310 hw->hw_addr = (uint8_t *)(afu_dev->mem_resource[0].addr); 311 hw->f_mac_read = ipn3ke_indirect_mac_read; 312 hw->f_mac_write = ipn3ke_indirect_mac_write; 313 hw->rawdev = rawdev; 314 rawdev->dev_ops->attr_get(rawdev, 315 "LineSideBARIndex", &index); 316 hw->eth_group_bar[0] = (uint8_t *)(afu_dev->mem_resource[index].addr); 317 rawdev->dev_ops->attr_get(rawdev, 318 "NICSideBARIndex", &index); 319 hw->eth_group_bar[1] = (uint8_t *)(afu_dev->mem_resource[index].addr); 320 rawdev->dev_ops->attr_get(rawdev, 321 "LineSideLinkPortNum", &port_num); 322 hw->retimer.port_num = (int)port_num; 323 hw->port_num = hw->retimer.port_num; 324 rawdev->dev_ops->attr_get(rawdev, 325 "LineSideMACType", &mac_type); 326 hw->retimer.mac_type = (int)mac_type; 327 328 hw->acc_tm = 0; 329 hw->acc_flow = 0; 330 331 if (afu_dev->id.uuid.uuid_low == IPN3KE_UUID_VBNG_LOW && 332 afu_dev->id.uuid.uuid_high == IPN3KE_UUID_VBNG_HIGH) { 333 /* After power on, wait until init done */ 334 if (ipn3ke_vbng_init_done(hw)) 335 return -1; 336 337 ipn3ke_hw_cap_init(hw); 338 339 /* Reset vBNG IP */ 340 IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 1); 341 rte_delay_us(10); 342 IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 0); 343 344 /* After reset, wait until init done */ 345 if (ipn3ke_vbng_init_done(hw)) 346 return -1; 347 348 hw->acc_tm = 1; 349 hw->acc_flow = 1; 350 351 IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n", 352 IPN3KE_READ_REG(hw, 0)); 353 } 354 355 if (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) { 356 /* Enable inter connect channel */ 357 for (i = 0; i < hw->port_num; i++) { 358 /* Enable the TX path */ 359 ipn3ke_xmac_tx_enable(hw, i, 1); 360 361 /* Disables source address override */ 362 ipn3ke_xmac_smac_ovd_dis(hw, i, 1); 363 364 /* Enable the RX path */ 365 ipn3ke_xmac_rx_enable(hw, i, 1); 366 367 /* Clear NIC side TX statistics counters */ 368 ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 1); 369 370 /* Clear NIC side RX statistics counters */ 371 ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 1); 372 373 /* Clear line side TX statistics counters */ 374 ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 0); 375 376 /* Clear line RX statistics counters */ 377 ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 0); 378 } 379 } else if (hw->retimer.mac_type == 380 IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) { 381 /* Enable inter connect channel */ 382 for (i = 0; i < hw->port_num; i++) { 383 /* Clear NIC side TX statistics counters */ 384 ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 1); 385 386 /* Clear NIC side RX statistics counters */ 387 ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 1); 388 389 /* Clear line side TX statistics counters */ 390 ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 0); 391 392 /* Clear line side RX statistics counters */ 393 ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 0); 394 } 395 } 396 397 /* init mtu */ 398 ipn3ke_mtu_setup(hw); 399 400 ret = rte_eth_switch_domain_alloc(&hw->switch_domain_id); 401 if (ret) 402 IPN3KE_AFU_PMD_WARN("failed to allocate switch domain for device %d", 403 ret); 404 405 hw->tm_hw_enable = 0; 406 hw->flow_hw_enable = 0; 407 if (afu_dev->id.uuid.uuid_low == IPN3KE_UUID_VBNG_LOW && 408 afu_dev->id.uuid.uuid_high == IPN3KE_UUID_VBNG_HIGH) { 409 ret = ipn3ke_hw_tm_init(hw); 410 if (ret) 411 return ret; 412 hw->tm_hw_enable = 1; 413 414 ret = ipn3ke_flow_init(hw); 415 if (ret) 416 return ret; 417 hw->flow_hw_enable = 1; 418 } 419 420 return 0; 421 } 422 423 static void 424 ipn3ke_hw_uninit(struct ipn3ke_hw *hw) 425 { 426 int i; 427 428 if (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) { 429 for (i = 0; i < hw->port_num; i++) { 430 /* Disable the TX path */ 431 ipn3ke_xmac_tx_disable(hw, i, 1); 432 433 /* Disable the RX path */ 434 ipn3ke_xmac_rx_disable(hw, i, 1); 435 436 /* Clear NIC side TX statistics counters */ 437 ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 1); 438 439 /* Clear NIC side RX statistics counters */ 440 ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 1); 441 442 /* Clear line side TX statistics counters */ 443 ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 0); 444 445 /* Clear line side RX statistics counters */ 446 ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 0); 447 } 448 } else if (hw->retimer.mac_type == 449 IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) { 450 for (i = 0; i < hw->port_num; i++) { 451 /* Clear NIC side TX statistics counters */ 452 ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 1); 453 454 /* Clear NIC side RX statistics counters */ 455 ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 1); 456 457 /* Clear line side TX statistics counters */ 458 ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 0); 459 460 /* Clear line side RX statistics counters */ 461 ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 0); 462 } 463 } 464 } 465 466 static int ipn3ke_vswitch_probe(struct rte_afu_device *afu_dev) 467 { 468 char name[RTE_ETH_NAME_MAX_LEN]; 469 struct ipn3ke_hw *hw; 470 struct rte_eth_dev *i40e_eth; 471 struct ifpga_rawdev *ifpga_dev; 472 int i, j, retval; 473 char *fvl_bdf; 474 475 /* check if the AFU device has been probed already */ 476 /* allocate shared mcp_vswitch structure */ 477 if (!afu_dev->shared.data) { 478 snprintf(name, sizeof(name), "net_%s_hw", 479 afu_dev->device.name); 480 hw = rte_zmalloc_socket(name, 481 sizeof(struct ipn3ke_hw), 482 RTE_CACHE_LINE_SIZE, 483 afu_dev->device.numa_node); 484 if (!hw) { 485 IPN3KE_AFU_PMD_ERR("failed to allocate hardware data"); 486 retval = -ENOMEM; 487 return -ENOMEM; 488 } 489 afu_dev->shared.data = hw; 490 491 rte_spinlock_init(&afu_dev->shared.lock); 492 } else { 493 hw = afu_dev->shared.data; 494 } 495 496 retval = ipn3ke_hw_init(afu_dev, hw); 497 if (retval) 498 return retval; 499 500 if (ipn3ke_bridge_func.get_ifpga_rawdev == NULL) 501 return -ENOMEM; 502 ifpga_dev = ipn3ke_bridge_func.get_ifpga_rawdev(hw->rawdev); 503 if (!ifpga_dev) 504 IPN3KE_AFU_PMD_ERR("failed to find ifpga_device."); 505 506 /* probe representor ports */ 507 j = 0; 508 for (i = 0; i < hw->port_num; i++) { 509 struct ipn3ke_rpst rpst = { 510 .port_id = i, 511 .switch_domain_id = hw->switch_domain_id, 512 .hw = hw 513 }; 514 515 /* representor port net_bdf_port */ 516 snprintf(name, sizeof(name), "net_%s_representor_%d", 517 afu_dev->device.name, i); 518 519 for (; j < 8; j++) { 520 fvl_bdf = ifpga_dev->fvl_bdf[j]; 521 i40e_eth = rte_eth_dev_get_by_name(fvl_bdf); 522 if (!i40e_eth) { 523 continue; 524 } else { 525 rpst.i40e_pf_eth = i40e_eth; 526 rpst.i40e_pf_eth_port_id = i40e_eth->data->port_id; 527 528 j++; 529 break; 530 } 531 } 532 533 retval = rte_eth_dev_create(&afu_dev->device, name, 534 sizeof(struct ipn3ke_rpst), NULL, NULL, 535 ipn3ke_rpst_init, &rpst); 536 537 if (retval) 538 IPN3KE_AFU_PMD_ERR("failed to create ipn3ke representor %s.", 539 name); 540 541 } 542 543 return 0; 544 } 545 546 static int ipn3ke_vswitch_remove(struct rte_afu_device *afu_dev) 547 { 548 char name[RTE_ETH_NAME_MAX_LEN]; 549 struct ipn3ke_hw *hw; 550 struct rte_eth_dev *ethdev; 551 int i, ret; 552 553 hw = afu_dev->shared.data; 554 555 /* remove representor ports */ 556 for (i = 0; i < hw->port_num; i++) { 557 /* representor port net_bdf_port */ 558 snprintf(name, sizeof(name), "net_%s_representor_%d", 559 afu_dev->device.name, i); 560 561 ethdev = rte_eth_dev_allocated(afu_dev->device.name); 562 if (ethdev != NULL) 563 rte_eth_dev_destroy(ethdev, ipn3ke_rpst_uninit); 564 } 565 566 ret = rte_eth_switch_domain_free(hw->switch_domain_id); 567 if (ret) 568 IPN3KE_AFU_PMD_WARN("failed to free switch domain: %d", ret); 569 570 /* hw uninit*/ 571 ipn3ke_hw_uninit(hw); 572 573 return 0; 574 } 575 576 static struct rte_afu_driver afu_ipn3ke_driver = { 577 .id_table = afu_uuid_ipn3ke_map, 578 .probe = ipn3ke_vswitch_probe, 579 .remove = ipn3ke_vswitch_remove, 580 }; 581 582 RTE_PMD_REGISTER_AFU(net_ipn3ke_afu, afu_ipn3ke_driver); 583 RTE_LOG_REGISTER_DEFAULT(ipn3ke_afu_logtype, NOTICE); 584