1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved. 3 */ 4 5 #ifndef _IONIC_REGS_H_ 6 #define _IONIC_REGS_H_ 7 8 /** struct ionic_intr - interrupt control register set. 9 * @coal_init: coalesce timer initial value. 10 * @mask: interrupt mask value. 11 * @credits: interrupt credit count and return. 12 * @mask_assert: interrupt mask value on assert. 13 * @coal: coalesce timer time remaining. 14 */ 15 struct ionic_intr { 16 uint32_t coal_init; 17 uint32_t mask; 18 uint32_t credits; 19 uint32_t mask_assert; 20 uint32_t coal; 21 uint32_t rsvd[3]; 22 }; 23 24 /** enum ionic_intr_mask_vals - valid values for mask and mask_assert. 25 * @IONIC_INTR_MASK_CLEAR: unmask interrupt. 26 * @IONIC_INTR_MASK_SET: mask interrupt. 27 */ 28 enum ionic_intr_mask_vals { 29 IONIC_INTR_MASK_CLEAR = 0, 30 IONIC_INTR_MASK_SET = 1, 31 }; 32 33 /** enum ionic_intr_credits_bits - bitwise composition of credits values. 34 * @IONIC_INTR_CRED_COUNT: bit mask of credit count, no shift needed. 35 * @IONIC_INTR_CRED_COUNT_SIGNED: bit mask of credit count, including sign bit. 36 * @IONIC_INTR_CRED_UNMASK: unmask the interrupt. 37 * @IONIC_INTR_CRED_RESET_COALESCE: reset the coalesce timer. 38 * @IONIC_INTR_CRED_REARM: unmask the and reset the timer. 39 */ 40 enum ionic_intr_credits_bits { 41 IONIC_INTR_CRED_COUNT = 0x7fffu, 42 IONIC_INTR_CRED_COUNT_SIGNED = 0xffffu, 43 IONIC_INTR_CRED_UNMASK = 0x10000u, 44 IONIC_INTR_CRED_RESET_COALESCE = 0x20000u, 45 IONIC_INTR_CRED_REARM = (IONIC_INTR_CRED_UNMASK | 46 IONIC_INTR_CRED_RESET_COALESCE), 47 }; 48 49 static inline void 50 ionic_intr_coal_init(struct ionic_intr __iomem *intr_ctrl, 51 int intr_idx, uint32_t coal) 52 { 53 iowrite32(coal, &intr_ctrl[intr_idx].coal_init); 54 } 55 56 static inline void 57 ionic_intr_mask(struct ionic_intr __iomem *intr_ctrl, 58 int intr_idx, uint32_t mask) 59 { 60 iowrite32(mask, &intr_ctrl[intr_idx].mask); 61 } 62 63 static inline void 64 ionic_intr_credits(struct ionic_intr __iomem *intr_ctrl, 65 int intr_idx, uint32_t cred, uint32_t flags) 66 { 67 if (cred > IONIC_INTR_CRED_COUNT) { 68 IONIC_WARN_ON(cred > IONIC_INTR_CRED_COUNT); 69 cred = ioread32(&intr_ctrl[intr_idx].credits); 70 cred &= IONIC_INTR_CRED_COUNT_SIGNED; 71 } 72 73 iowrite32(cred | flags, &intr_ctrl[intr_idx].credits); 74 } 75 76 static inline void 77 ionic_intr_clean(struct ionic_intr __iomem *intr_ctrl, 78 int intr_idx) 79 { 80 uint32_t cred; 81 82 cred = ioread32(&intr_ctrl[intr_idx].credits); 83 cred &= IONIC_INTR_CRED_COUNT_SIGNED; 84 cred |= IONIC_INTR_CRED_RESET_COALESCE; 85 iowrite32(cred, &intr_ctrl[intr_idx].credits); 86 } 87 88 static inline void 89 ionic_intr_mask_assert(struct ionic_intr __iomem *intr_ctrl, 90 int intr_idx, uint32_t mask) 91 { 92 iowrite32(mask, &intr_ctrl[intr_idx].mask_assert); 93 } 94 95 /** enum ionic_dbell_bits - bitwise composition of dbell values. 96 * 97 * @IONIC_DBELL_QID_MASK: unshifted mask of valid queue id bits. 98 * @IONIC_DBELL_QID_SHIFT: queue id shift amount in dbell value. 99 * @IONIC_DBELL_QID: macro to build QID component of dbell value. 100 * 101 * @IONIC_DBELL_RING_MASK: unshifted mask of valid ring bits. 102 * @IONIC_DBELL_RING_SHIFT: ring shift amount in dbell value. 103 * @IONIC_DBELL_RING: macro to build ring component of dbell value. 104 * 105 * @IONIC_DBELL_RING_0: ring zero dbell component value. 106 * @IONIC_DBELL_RING_1: ring one dbell component value. 107 * @IONIC_DBELL_RING_2: ring two dbell component value. 108 * @IONIC_DBELL_RING_3: ring three dbell component value. 109 * 110 * @IONIC_DBELL_INDEX_MASK: bit mask of valid index bits, no shift needed. 111 */ 112 enum ionic_dbell_bits { 113 IONIC_DBELL_QID_MASK = 0xffffff, 114 IONIC_DBELL_QID_SHIFT = 24, 115 116 #define IONIC_DBELL_QID(n) \ 117 (((u64)(n) & IONIC_DBELL_QID_MASK) << IONIC_DBELL_QID_SHIFT) 118 119 IONIC_DBELL_RING_MASK = 0x7, 120 IONIC_DBELL_RING_SHIFT = 16, 121 122 #define IONIC_DBELL_RING(n) \ 123 (((u64)(n) & IONIC_DBELL_RING_MASK) << IONIC_DBELL_RING_SHIFT) 124 125 IONIC_DBELL_RING_0 = 0, 126 IONIC_DBELL_RING_1 = IONIC_DBELL_RING(1), 127 IONIC_DBELL_RING_2 = IONIC_DBELL_RING(2), 128 IONIC_DBELL_RING_3 = IONIC_DBELL_RING(3), 129 130 IONIC_DBELL_INDEX_MASK = 0xffff, 131 }; 132 133 #endif /* _IONIC_REGS_H_ */ 134