1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved. 3 */ 4 5 #include <rte_malloc.h> 6 #include <ethdev_driver.h> 7 8 #include "ionic.h" 9 #include "ionic_logs.h" 10 #include "ionic_lif.h" 11 #include "ionic_ethdev.h" 12 #include "ionic_rx_filter.h" 13 #include "ionic_rxtx.h" 14 15 /* queuetype support level */ 16 static const uint8_t ionic_qtype_vers[IONIC_QTYPE_MAX] = { 17 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ 18 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ 19 [IONIC_QTYPE_RXQ] = 2, /* 0 = Base version with CQ+SG support 20 * 1 = ... with EQ 21 * 2 = ... with CMB 22 */ 23 [IONIC_QTYPE_TXQ] = 3, /* 0 = Base version with CQ+SG support 24 * 1 = ... with Tx SG version 1 25 * 2 = ... with EQ 26 * 3 = ... with CMB 27 */ 28 }; 29 30 static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr); 31 static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr); 32 33 int 34 ionic_qcq_enable(struct ionic_qcq *qcq) 35 { 36 struct ionic_queue *q = &qcq->q; 37 struct ionic_lif *lif = qcq->lif; 38 struct ionic_admin_ctx ctx = { 39 .pending_work = true, 40 .cmd.q_control = { 41 .opcode = IONIC_CMD_Q_CONTROL, 42 .type = q->type, 43 .index = rte_cpu_to_le_32(q->index), 44 .oper = IONIC_Q_ENABLE, 45 }, 46 }; 47 48 return ionic_adminq_post_wait(lif, &ctx); 49 } 50 51 int 52 ionic_qcq_disable(struct ionic_qcq *qcq) 53 { 54 struct ionic_queue *q = &qcq->q; 55 struct ionic_lif *lif = qcq->lif; 56 struct ionic_admin_ctx ctx = { 57 .pending_work = true, 58 .cmd.q_control = { 59 .opcode = IONIC_CMD_Q_CONTROL, 60 .type = q->type, 61 .index = rte_cpu_to_le_32(q->index), 62 .oper = IONIC_Q_DISABLE, 63 }, 64 }; 65 66 return ionic_adminq_post_wait(lif, &ctx); 67 } 68 69 void 70 ionic_lif_stop(struct ionic_lif *lif) 71 { 72 uint32_t i; 73 74 IONIC_PRINT_CALL(); 75 76 lif->state &= ~IONIC_LIF_F_UP; 77 78 for (i = 0; i < lif->nrxqcqs; i++) { 79 struct ionic_rx_qcq *rxq = lif->rxqcqs[i]; 80 if (rxq->flags & IONIC_QCQ_F_INITED) 81 (void)ionic_dev_rx_queue_stop(lif->eth_dev, i); 82 } 83 84 for (i = 0; i < lif->ntxqcqs; i++) { 85 struct ionic_tx_qcq *txq = lif->txqcqs[i]; 86 if (txq->flags & IONIC_QCQ_F_INITED) 87 (void)ionic_dev_tx_queue_stop(lif->eth_dev, i); 88 } 89 } 90 91 void 92 ionic_lif_reset(struct ionic_lif *lif) 93 { 94 struct ionic_dev *idev = &lif->adapter->idev; 95 int err; 96 97 IONIC_PRINT_CALL(); 98 99 ionic_dev_cmd_lif_reset(idev); 100 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 101 if (err) 102 IONIC_PRINT(WARNING, "Failed to reset %s", lif->name); 103 } 104 105 static void 106 ionic_lif_get_abs_stats(const struct ionic_lif *lif, struct rte_eth_stats *stats) 107 { 108 struct ionic_lif_stats *ls = &lif->info->stats; 109 uint32_t i; 110 uint32_t num_rx_q_counters = RTE_MIN(lif->nrxqcqs, (uint32_t) 111 RTE_ETHDEV_QUEUE_STAT_CNTRS); 112 uint32_t num_tx_q_counters = RTE_MIN(lif->ntxqcqs, (uint32_t) 113 RTE_ETHDEV_QUEUE_STAT_CNTRS); 114 115 memset(stats, 0, sizeof(*stats)); 116 117 if (ls == NULL) { 118 IONIC_PRINT(DEBUG, "Stats on port %u not yet initialized", 119 lif->port_id); 120 return; 121 } 122 123 /* RX */ 124 125 stats->ipackets = ls->rx_ucast_packets + 126 ls->rx_mcast_packets + 127 ls->rx_bcast_packets; 128 129 stats->ibytes = ls->rx_ucast_bytes + 130 ls->rx_mcast_bytes + 131 ls->rx_bcast_bytes; 132 133 for (i = 0; i < lif->nrxqcqs; i++) { 134 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats; 135 stats->imissed += 136 rx_stats->no_cb_arg + 137 rx_stats->bad_cq_status + 138 rx_stats->no_room + 139 rx_stats->bad_len; 140 } 141 142 stats->imissed += 143 ls->rx_ucast_drop_packets + 144 ls->rx_mcast_drop_packets + 145 ls->rx_bcast_drop_packets; 146 147 stats->imissed += 148 ls->rx_queue_empty + 149 ls->rx_dma_error + 150 ls->rx_queue_disabled + 151 ls->rx_desc_fetch_error + 152 ls->rx_desc_data_error; 153 154 for (i = 0; i < num_rx_q_counters; i++) { 155 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats; 156 stats->q_ipackets[i] = rx_stats->packets; 157 stats->q_ibytes[i] = rx_stats->bytes; 158 stats->q_errors[i] = 159 rx_stats->no_cb_arg + 160 rx_stats->bad_cq_status + 161 rx_stats->no_room + 162 rx_stats->bad_len; 163 } 164 165 /* TX */ 166 167 stats->opackets = ls->tx_ucast_packets + 168 ls->tx_mcast_packets + 169 ls->tx_bcast_packets; 170 171 stats->obytes = ls->tx_ucast_bytes + 172 ls->tx_mcast_bytes + 173 ls->tx_bcast_bytes; 174 175 for (i = 0; i < lif->ntxqcqs; i++) { 176 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats; 177 stats->oerrors += tx_stats->drop; 178 } 179 180 stats->oerrors += 181 ls->tx_ucast_drop_packets + 182 ls->tx_mcast_drop_packets + 183 ls->tx_bcast_drop_packets; 184 185 stats->oerrors += 186 ls->tx_dma_error + 187 ls->tx_queue_disabled + 188 ls->tx_desc_fetch_error + 189 ls->tx_desc_data_error; 190 191 for (i = 0; i < num_tx_q_counters; i++) { 192 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats; 193 stats->q_opackets[i] = tx_stats->packets; 194 stats->q_obytes[i] = tx_stats->bytes; 195 } 196 } 197 198 void 199 ionic_lif_get_stats(const struct ionic_lif *lif, 200 struct rte_eth_stats *stats) 201 { 202 ionic_lif_get_abs_stats(lif, stats); 203 204 stats->ipackets -= lif->stats_base.ipackets; 205 stats->opackets -= lif->stats_base.opackets; 206 stats->ibytes -= lif->stats_base.ibytes; 207 stats->obytes -= lif->stats_base.obytes; 208 stats->imissed -= lif->stats_base.imissed; 209 stats->ierrors -= lif->stats_base.ierrors; 210 stats->oerrors -= lif->stats_base.oerrors; 211 stats->rx_nombuf -= lif->stats_base.rx_nombuf; 212 } 213 214 void 215 ionic_lif_reset_stats(struct ionic_lif *lif) 216 { 217 uint32_t i; 218 219 for (i = 0; i < lif->nrxqcqs; i++) { 220 memset(&lif->rxqcqs[i]->stats, 0, 221 sizeof(struct ionic_rx_stats)); 222 memset(&lif->txqcqs[i]->stats, 0, 223 sizeof(struct ionic_tx_stats)); 224 } 225 226 ionic_lif_get_abs_stats(lif, &lif->stats_base); 227 } 228 229 void 230 ionic_lif_get_hw_stats(struct ionic_lif *lif, struct ionic_lif_stats *stats) 231 { 232 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t); 233 uint64_t *stats64 = (uint64_t *)stats; 234 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats; 235 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base; 236 237 for (i = 0; i < count; i++) 238 stats64[i] = lif_stats64[i] - lif_stats64_base[i]; 239 } 240 241 void 242 ionic_lif_reset_hw_stats(struct ionic_lif *lif) 243 { 244 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t); 245 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats; 246 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base; 247 248 for (i = 0; i < count; i++) 249 lif_stats64_base[i] = lif_stats64[i]; 250 } 251 252 static int 253 ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr) 254 { 255 struct ionic_admin_ctx ctx = { 256 .pending_work = true, 257 .cmd.rx_filter_add = { 258 .opcode = IONIC_CMD_RX_FILTER_ADD, 259 .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_MAC), 260 }, 261 }; 262 int err; 263 264 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, RTE_ETHER_ADDR_LEN); 265 266 err = ionic_adminq_post_wait(lif, &ctx); 267 if (err) 268 return err; 269 270 IONIC_PRINT(INFO, "rx_filter add (id %d)", 271 rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id)); 272 273 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx); 274 } 275 276 static int 277 ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr) 278 { 279 struct ionic_admin_ctx ctx = { 280 .pending_work = true, 281 .cmd.rx_filter_del = { 282 .opcode = IONIC_CMD_RX_FILTER_DEL, 283 }, 284 }; 285 struct ionic_rx_filter *f; 286 int err; 287 288 IONIC_PRINT_CALL(); 289 290 rte_spinlock_lock(&lif->rx_filters.lock); 291 292 f = ionic_rx_filter_by_addr(lif, addr); 293 if (!f) { 294 rte_spinlock_unlock(&lif->rx_filters.lock); 295 return -ENOENT; 296 } 297 298 ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id); 299 ionic_rx_filter_free(f); 300 301 rte_spinlock_unlock(&lif->rx_filters.lock); 302 303 err = ionic_adminq_post_wait(lif, &ctx); 304 if (err) 305 return err; 306 307 IONIC_PRINT(INFO, "rx_filter del (id %d)", 308 rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id)); 309 310 return 0; 311 } 312 313 int 314 ionic_dev_add_mac(struct rte_eth_dev *eth_dev, 315 struct rte_ether_addr *mac_addr, 316 uint32_t index __rte_unused, uint32_t pool __rte_unused) 317 { 318 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 319 320 IONIC_PRINT_CALL(); 321 322 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr); 323 } 324 325 void 326 ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index) 327 { 328 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 329 struct ionic_adapter *adapter = lif->adapter; 330 struct rte_ether_addr *mac_addr; 331 332 IONIC_PRINT_CALL(); 333 334 if (index >= adapter->max_mac_addrs) { 335 IONIC_PRINT(WARNING, 336 "Index %u is above MAC filter limit %u", 337 index, adapter->max_mac_addrs); 338 return; 339 } 340 341 mac_addr = ð_dev->data->mac_addrs[index]; 342 343 if (!rte_is_valid_assigned_ether_addr(mac_addr)) 344 return; 345 346 ionic_lif_addr_del(lif, (const uint8_t *)mac_addr); 347 } 348 349 int 350 ionic_dev_set_mac(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr) 351 { 352 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 353 354 IONIC_PRINT_CALL(); 355 356 if (mac_addr == NULL) { 357 IONIC_PRINT(NOTICE, "New mac is null"); 358 return -1; 359 } 360 361 if (!rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) { 362 IONIC_PRINT(INFO, "Deleting mac addr %pM", 363 lif->mac_addr); 364 ionic_lif_addr_del(lif, lif->mac_addr); 365 memset(lif->mac_addr, 0, RTE_ETHER_ADDR_LEN); 366 } 367 368 IONIC_PRINT(INFO, "Updating mac addr"); 369 370 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)lif->mac_addr); 371 372 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr); 373 } 374 375 static int 376 ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid) 377 { 378 struct ionic_admin_ctx ctx = { 379 .pending_work = true, 380 .cmd.rx_filter_add = { 381 .opcode = IONIC_CMD_RX_FILTER_ADD, 382 .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_VLAN), 383 .vlan.vlan = rte_cpu_to_le_16(vid), 384 }, 385 }; 386 int err; 387 388 err = ionic_adminq_post_wait(lif, &ctx); 389 if (err) 390 return err; 391 392 IONIC_PRINT(INFO, "rx_filter add VLAN %d (id %d)", vid, 393 rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id)); 394 395 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx); 396 } 397 398 static int 399 ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid) 400 { 401 struct ionic_admin_ctx ctx = { 402 .pending_work = true, 403 .cmd.rx_filter_del = { 404 .opcode = IONIC_CMD_RX_FILTER_DEL, 405 }, 406 }; 407 struct ionic_rx_filter *f; 408 int err; 409 410 IONIC_PRINT_CALL(); 411 412 rte_spinlock_lock(&lif->rx_filters.lock); 413 414 f = ionic_rx_filter_by_vlan(lif, vid); 415 if (!f) { 416 rte_spinlock_unlock(&lif->rx_filters.lock); 417 return -ENOENT; 418 } 419 420 ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id); 421 ionic_rx_filter_free(f); 422 rte_spinlock_unlock(&lif->rx_filters.lock); 423 424 err = ionic_adminq_post_wait(lif, &ctx); 425 if (err) 426 return err; 427 428 IONIC_PRINT(INFO, "rx_filter del VLAN %d (id %d)", vid, 429 rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id)); 430 431 return 0; 432 } 433 434 int 435 ionic_dev_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id, 436 int on) 437 { 438 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 439 int err; 440 441 if (on) 442 err = ionic_vlan_rx_add_vid(lif, vlan_id); 443 else 444 err = ionic_vlan_rx_kill_vid(lif, vlan_id); 445 446 return err; 447 } 448 449 static void 450 ionic_lif_rx_mode(struct ionic_lif *lif, uint32_t rx_mode) 451 { 452 struct ionic_admin_ctx ctx = { 453 .pending_work = true, 454 .cmd.rx_mode_set = { 455 .opcode = IONIC_CMD_RX_MODE_SET, 456 .rx_mode = rte_cpu_to_le_16(rx_mode), 457 }, 458 }; 459 int err; 460 461 if (rx_mode & IONIC_RX_MODE_F_UNICAST) 462 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_UNICAST"); 463 if (rx_mode & IONIC_RX_MODE_F_MULTICAST) 464 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_MULTICAST"); 465 if (rx_mode & IONIC_RX_MODE_F_BROADCAST) 466 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_BROADCAST"); 467 if (rx_mode & IONIC_RX_MODE_F_PROMISC) 468 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_PROMISC"); 469 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI) 470 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_ALLMULTI"); 471 472 err = ionic_adminq_post_wait(lif, &ctx); 473 if (err) 474 IONIC_PRINT(ERR, "Failure setting RX mode"); 475 } 476 477 static void 478 ionic_set_rx_mode(struct ionic_lif *lif, uint32_t rx_mode) 479 { 480 if (lif->rx_mode != rx_mode) { 481 lif->rx_mode = rx_mode; 482 ionic_lif_rx_mode(lif, rx_mode); 483 } 484 } 485 486 int 487 ionic_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 488 { 489 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 490 uint32_t rx_mode = lif->rx_mode; 491 492 IONIC_PRINT_CALL(); 493 494 rx_mode |= IONIC_RX_MODE_F_PROMISC; 495 496 ionic_set_rx_mode(lif, rx_mode); 497 498 return 0; 499 } 500 501 int 502 ionic_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 503 { 504 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 505 uint32_t rx_mode = lif->rx_mode; 506 507 rx_mode &= ~IONIC_RX_MODE_F_PROMISC; 508 509 ionic_set_rx_mode(lif, rx_mode); 510 511 return 0; 512 } 513 514 int 515 ionic_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 516 { 517 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 518 uint32_t rx_mode = lif->rx_mode; 519 520 rx_mode |= IONIC_RX_MODE_F_ALLMULTI; 521 522 ionic_set_rx_mode(lif, rx_mode); 523 524 return 0; 525 } 526 527 int 528 ionic_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 529 { 530 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 531 uint32_t rx_mode = lif->rx_mode; 532 533 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI; 534 535 ionic_set_rx_mode(lif, rx_mode); 536 537 return 0; 538 } 539 540 int 541 ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu) 542 { 543 struct ionic_admin_ctx ctx = { 544 .pending_work = true, 545 .cmd.lif_setattr = { 546 .opcode = IONIC_CMD_LIF_SETATTR, 547 .attr = IONIC_LIF_ATTR_MTU, 548 .mtu = rte_cpu_to_le_32(new_mtu), 549 }, 550 }; 551 int err; 552 553 err = ionic_adminq_post_wait(lif, &ctx); 554 if (err) 555 return err; 556 557 return 0; 558 } 559 560 int 561 ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) 562 { 563 struct ionic_adapter *adapter = lif->adapter; 564 struct ionic_dev *idev = &adapter->idev; 565 unsigned long index; 566 567 /* 568 * Note: interrupt handler is called for index = 0 only 569 * (we use interrupts for the notifyq only anyway, 570 * which has index = 0) 571 */ 572 573 for (index = 0; index < adapter->nintrs; index++) 574 if (!adapter->intrs[index]) 575 break; 576 577 if (index == adapter->nintrs) 578 return -ENOSPC; 579 580 adapter->intrs[index] = true; 581 582 ionic_intr_init(idev, intr, index); 583 584 return 0; 585 } 586 587 static int 588 ionic_qcq_alloc(struct ionic_lif *lif, 589 uint8_t type, 590 size_t struct_size, 591 uint32_t index, 592 const char *type_name, 593 uint16_t flags, 594 uint16_t num_descs, 595 uint16_t desc_size, 596 uint16_t cq_desc_size, 597 uint16_t sg_desc_size, 598 struct ionic_qcq **qcq) 599 { 600 struct ionic_qcq *new; 601 uint32_t q_size, cq_size, sg_size, total_size; 602 void *q_base, *cq_base, *sg_base; 603 rte_iova_t q_base_pa = 0; 604 rte_iova_t cq_base_pa = 0; 605 rte_iova_t sg_base_pa = 0; 606 uint32_t socket_id = rte_socket_id(); 607 int err; 608 609 *qcq = NULL; 610 611 q_size = num_descs * desc_size; 612 cq_size = num_descs * cq_desc_size; 613 sg_size = num_descs * sg_desc_size; 614 615 total_size = RTE_ALIGN(q_size, PAGE_SIZE) + 616 RTE_ALIGN(cq_size, PAGE_SIZE); 617 /* 618 * Note: aligning q_size/cq_size is not enough due to cq_base address 619 * aligning as q_base could be not aligned to the page. 620 * Adding PAGE_SIZE. 621 */ 622 total_size += PAGE_SIZE; 623 624 if (flags & IONIC_QCQ_F_SG) { 625 total_size += RTE_ALIGN(sg_size, PAGE_SIZE); 626 total_size += PAGE_SIZE; 627 } 628 629 new = rte_zmalloc("ionic", struct_size, 0); 630 if (!new) { 631 IONIC_PRINT(ERR, "Cannot allocate queue structure"); 632 return -ENOMEM; 633 } 634 635 new->lif = lif; 636 637 new->q.info = rte_calloc_socket("ionic", 638 num_descs, sizeof(void *), 639 PAGE_SIZE, socket_id); 640 if (!new->q.info) { 641 IONIC_PRINT(ERR, "Cannot allocate queue info"); 642 err = -ENOMEM; 643 goto err_out_free_qcq; 644 } 645 646 new->q.type = type; 647 648 err = ionic_q_init(&new->q, index, num_descs); 649 if (err) { 650 IONIC_PRINT(ERR, "Queue initialization failed"); 651 goto err_out_free_info; 652 } 653 654 err = ionic_cq_init(&new->cq, num_descs); 655 if (err) { 656 IONIC_PRINT(ERR, "Completion queue initialization failed"); 657 goto err_out_free_info; 658 } 659 660 new->base_z = rte_eth_dma_zone_reserve(lif->eth_dev, 661 type_name, index /* queue_idx */, 662 total_size, IONIC_ALIGN, socket_id); 663 664 if (!new->base_z) { 665 IONIC_PRINT(ERR, "Cannot reserve queue DMA memory"); 666 err = -ENOMEM; 667 goto err_out_free_info; 668 } 669 670 new->base = new->base_z->addr; 671 new->base_pa = new->base_z->iova; 672 673 q_base = new->base; 674 q_base_pa = new->base_pa; 675 676 cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE); 677 cq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE); 678 679 if (flags & IONIC_QCQ_F_SG) { 680 sg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size, 681 PAGE_SIZE); 682 sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE); 683 ionic_q_sg_map(&new->q, sg_base, sg_base_pa); 684 } 685 686 IONIC_PRINT(DEBUG, "Q-Base-PA = %#jx CQ-Base-PA = %#jx " 687 "SG-base-PA = %#jx", 688 q_base_pa, cq_base_pa, sg_base_pa); 689 690 ionic_q_map(&new->q, q_base, q_base_pa); 691 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 692 693 *qcq = new; 694 695 return 0; 696 697 err_out_free_info: 698 rte_free(new->q.info); 699 err_out_free_qcq: 700 rte_free(new); 701 702 return err; 703 } 704 705 void 706 ionic_qcq_free(struct ionic_qcq *qcq) 707 { 708 if (qcq->base_z) { 709 qcq->base = NULL; 710 qcq->base_pa = 0; 711 rte_memzone_free(qcq->base_z); 712 qcq->base_z = NULL; 713 } 714 715 if (qcq->q.info) { 716 rte_free(qcq->q.info); 717 qcq->q.info = NULL; 718 } 719 720 rte_free(qcq); 721 } 722 723 int 724 ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t index, 725 uint16_t nrxq_descs, struct ionic_rx_qcq **rxq_out) 726 { 727 struct ionic_rx_qcq *rxq; 728 uint16_t flags; 729 int err; 730 731 flags = IONIC_QCQ_F_SG; 732 err = ionic_qcq_alloc(lif, 733 IONIC_QTYPE_RXQ, 734 sizeof(struct ionic_rx_qcq), 735 index, 736 "rx", 737 flags, 738 nrxq_descs, 739 sizeof(struct ionic_rxq_desc), 740 sizeof(struct ionic_rxq_comp), 741 sizeof(struct ionic_rxq_sg_desc), 742 (struct ionic_qcq **)&rxq); 743 if (err) 744 return err; 745 746 rxq->flags = flags; 747 748 lif->rxqcqs[index] = rxq; 749 *rxq_out = rxq; 750 751 return 0; 752 } 753 754 int 755 ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t index, 756 uint16_t ntxq_descs, struct ionic_tx_qcq **txq_out) 757 { 758 struct ionic_tx_qcq *txq; 759 uint16_t flags; 760 int err; 761 762 flags = IONIC_QCQ_F_SG; 763 err = ionic_qcq_alloc(lif, 764 IONIC_QTYPE_TXQ, 765 sizeof(struct ionic_tx_qcq), 766 index, 767 "tx", 768 flags, 769 ntxq_descs, 770 sizeof(struct ionic_txq_desc), 771 sizeof(struct ionic_txq_comp), 772 sizeof(struct ionic_txq_sg_desc_v1), 773 (struct ionic_qcq **)&txq); 774 if (err) 775 return err; 776 777 txq->flags = flags; 778 779 lif->txqcqs[index] = txq; 780 *txq_out = txq; 781 782 return 0; 783 } 784 785 static int 786 ionic_admin_qcq_alloc(struct ionic_lif *lif) 787 { 788 uint16_t flags = 0; 789 int err; 790 791 err = ionic_qcq_alloc(lif, 792 IONIC_QTYPE_ADMINQ, 793 sizeof(struct ionic_admin_qcq), 794 0, 795 "admin", 796 flags, 797 IONIC_ADMINQ_LENGTH, 798 sizeof(struct ionic_admin_cmd), 799 sizeof(struct ionic_admin_comp), 800 0, 801 (struct ionic_qcq **)&lif->adminqcq); 802 if (err) 803 return err; 804 805 return 0; 806 } 807 808 static int 809 ionic_notify_qcq_alloc(struct ionic_lif *lif) 810 { 811 struct ionic_notify_qcq *nqcq; 812 struct ionic_dev *idev = &lif->adapter->idev; 813 uint16_t flags = 0; 814 int err; 815 816 err = ionic_qcq_alloc(lif, 817 IONIC_QTYPE_NOTIFYQ, 818 sizeof(struct ionic_notify_qcq), 819 0, 820 "notify", 821 flags, 822 IONIC_NOTIFYQ_LENGTH, 823 sizeof(struct ionic_notifyq_cmd), 824 sizeof(union ionic_notifyq_comp), 825 0, 826 (struct ionic_qcq **)&nqcq); 827 if (err) 828 return err; 829 830 err = ionic_intr_alloc(lif, &nqcq->intr); 831 if (err) { 832 ionic_qcq_free(&nqcq->qcq); 833 return err; 834 } 835 836 ionic_intr_mask_assert(idev->intr_ctrl, nqcq->intr.index, 837 IONIC_INTR_MASK_SET); 838 839 lif->notifyqcq = nqcq; 840 841 return 0; 842 } 843 844 static void * 845 ionic_bus_map_dbpage(struct ionic_adapter *adapter, int page_num) 846 { 847 char *vaddr = adapter->bars[IONIC_PCI_BAR_DBELL].vaddr; 848 849 if (adapter->num_bars <= IONIC_PCI_BAR_DBELL) 850 return NULL; 851 852 return (void *)&vaddr[page_num << PAGE_SHIFT]; 853 } 854 855 static void 856 ionic_lif_queue_identify(struct ionic_lif *lif) 857 { 858 struct ionic_adapter *adapter = lif->adapter; 859 struct ionic_dev *idev = &adapter->idev; 860 union ionic_q_identity *q_ident = &adapter->ident.txq; 861 uint32_t q_words = RTE_DIM(q_ident->words); 862 uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data); 863 uint32_t i, nwords, qtype; 864 int err; 865 866 for (qtype = 0; qtype < RTE_DIM(ionic_qtype_vers); qtype++) { 867 struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; 868 869 /* Filter out the types this driver knows about */ 870 switch (qtype) { 871 case IONIC_QTYPE_ADMINQ: 872 case IONIC_QTYPE_NOTIFYQ: 873 case IONIC_QTYPE_RXQ: 874 case IONIC_QTYPE_TXQ: 875 break; 876 default: 877 continue; 878 } 879 880 memset(qti, 0, sizeof(*qti)); 881 882 ionic_dev_cmd_queue_identify(idev, IONIC_LIF_TYPE_CLASSIC, 883 qtype, ionic_qtype_vers[qtype]); 884 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 885 if (err == -EINVAL) { 886 IONIC_PRINT(ERR, "qtype %d not supported\n", qtype); 887 continue; 888 } else if (err == -EIO) { 889 IONIC_PRINT(ERR, "q_ident failed, older FW\n"); 890 return; 891 } else if (err) { 892 IONIC_PRINT(ERR, "q_ident failed, qtype %d: %d\n", 893 qtype, err); 894 return; 895 } 896 897 nwords = RTE_MIN(q_words, cmd_words); 898 for (i = 0; i < nwords; i++) 899 q_ident->words[i] = ioread32(&idev->dev_cmd->data[i]); 900 901 qti->version = q_ident->version; 902 qti->supported = q_ident->supported; 903 qti->features = rte_le_to_cpu_64(q_ident->features); 904 qti->desc_sz = rte_le_to_cpu_16(q_ident->desc_sz); 905 qti->comp_sz = rte_le_to_cpu_16(q_ident->comp_sz); 906 qti->sg_desc_sz = rte_le_to_cpu_16(q_ident->sg_desc_sz); 907 qti->max_sg_elems = rte_le_to_cpu_16(q_ident->max_sg_elems); 908 qti->sg_desc_stride = 909 rte_le_to_cpu_16(q_ident->sg_desc_stride); 910 911 IONIC_PRINT(DEBUG, " qtype[%d].version = %d", 912 qtype, qti->version); 913 IONIC_PRINT(DEBUG, " qtype[%d].supported = %#x", 914 qtype, qti->supported); 915 IONIC_PRINT(DEBUG, " qtype[%d].features = %#jx", 916 qtype, qti->features); 917 IONIC_PRINT(DEBUG, " qtype[%d].desc_sz = %d", 918 qtype, qti->desc_sz); 919 IONIC_PRINT(DEBUG, " qtype[%d].comp_sz = %d", 920 qtype, qti->comp_sz); 921 IONIC_PRINT(DEBUG, " qtype[%d].sg_desc_sz = %d", 922 qtype, qti->sg_desc_sz); 923 IONIC_PRINT(DEBUG, " qtype[%d].max_sg_elems = %d", 924 qtype, qti->max_sg_elems); 925 IONIC_PRINT(DEBUG, " qtype[%d].sg_desc_stride = %d", 926 qtype, qti->sg_desc_stride); 927 } 928 } 929 930 int 931 ionic_lif_alloc(struct ionic_lif *lif) 932 { 933 struct ionic_adapter *adapter = lif->adapter; 934 uint32_t socket_id = rte_socket_id(); 935 int err; 936 937 /* 938 * lif->name was zeroed on allocation. 939 * Copy (sizeof() - 1) bytes to ensure that it is NULL terminated. 940 */ 941 memcpy(lif->name, lif->eth_dev->data->name, sizeof(lif->name) - 1); 942 943 IONIC_PRINT(DEBUG, "LIF: %s", lif->name); 944 945 ionic_lif_queue_identify(lif); 946 947 if (lif->qtype_info[IONIC_QTYPE_TXQ].version < 1) { 948 IONIC_PRINT(ERR, "FW too old, please upgrade"); 949 return -ENXIO; 950 } 951 952 IONIC_PRINT(DEBUG, "Allocating Lif Info"); 953 954 rte_spinlock_init(&lif->adminq_lock); 955 rte_spinlock_init(&lif->adminq_service_lock); 956 957 lif->kern_dbpage = ionic_bus_map_dbpage(adapter, 0); 958 if (!lif->kern_dbpage) { 959 IONIC_PRINT(ERR, "Cannot map dbpage, aborting"); 960 return -ENOMEM; 961 } 962 963 lif->txqcqs = rte_zmalloc("ionic", sizeof(*lif->txqcqs) * 964 adapter->max_ntxqs_per_lif, 0); 965 966 if (!lif->txqcqs) { 967 IONIC_PRINT(ERR, "Cannot allocate tx queues array"); 968 return -ENOMEM; 969 } 970 971 lif->rxqcqs = rte_zmalloc("ionic", sizeof(*lif->rxqcqs) * 972 adapter->max_nrxqs_per_lif, 0); 973 974 if (!lif->rxqcqs) { 975 IONIC_PRINT(ERR, "Cannot allocate rx queues array"); 976 return -ENOMEM; 977 } 978 979 IONIC_PRINT(DEBUG, "Allocating Notify Queue"); 980 981 err = ionic_notify_qcq_alloc(lif); 982 if (err) { 983 IONIC_PRINT(ERR, "Cannot allocate notify queue"); 984 return err; 985 } 986 987 IONIC_PRINT(DEBUG, "Allocating Admin Queue"); 988 989 err = ionic_admin_qcq_alloc(lif); 990 if (err) { 991 IONIC_PRINT(ERR, "Cannot allocate admin queue"); 992 return err; 993 } 994 995 IONIC_PRINT(DEBUG, "Allocating Lif Info"); 996 997 lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE); 998 999 lif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev, 1000 "lif_info", 0 /* queue_idx*/, 1001 lif->info_sz, IONIC_ALIGN, socket_id); 1002 if (!lif->info_z) { 1003 IONIC_PRINT(ERR, "Cannot allocate lif info memory"); 1004 return -ENOMEM; 1005 } 1006 1007 lif->info = lif->info_z->addr; 1008 lif->info_pa = lif->info_z->iova; 1009 1010 return 0; 1011 } 1012 1013 void 1014 ionic_lif_free(struct ionic_lif *lif) 1015 { 1016 if (lif->notifyqcq) { 1017 ionic_qcq_free(&lif->notifyqcq->qcq); 1018 lif->notifyqcq = NULL; 1019 } 1020 1021 if (lif->adminqcq) { 1022 ionic_qcq_free(&lif->adminqcq->qcq); 1023 lif->adminqcq = NULL; 1024 } 1025 1026 if (lif->txqcqs) { 1027 rte_free(lif->txqcqs); 1028 lif->txqcqs = NULL; 1029 } 1030 1031 if (lif->rxqcqs) { 1032 rte_free(lif->rxqcqs); 1033 lif->rxqcqs = NULL; 1034 } 1035 1036 if (lif->info) { 1037 rte_memzone_free(lif->info_z); 1038 lif->info = NULL; 1039 } 1040 } 1041 1042 void 1043 ionic_lif_free_queues(struct ionic_lif *lif) 1044 { 1045 uint32_t i; 1046 1047 for (i = 0; i < lif->ntxqcqs; i++) { 1048 ionic_dev_tx_queue_release(lif->eth_dev->data->tx_queues[i]); 1049 lif->eth_dev->data->tx_queues[i] = NULL; 1050 } 1051 for (i = 0; i < lif->nrxqcqs; i++) { 1052 ionic_dev_rx_queue_release(lif->eth_dev->data->rx_queues[i]); 1053 lif->eth_dev->data->rx_queues[i] = NULL; 1054 } 1055 } 1056 1057 int 1058 ionic_lif_rss_config(struct ionic_lif *lif, 1059 const uint16_t types, const uint8_t *key, const uint32_t *indir) 1060 { 1061 struct ionic_adapter *adapter = lif->adapter; 1062 struct ionic_admin_ctx ctx = { 1063 .pending_work = true, 1064 .cmd.lif_setattr = { 1065 .opcode = IONIC_CMD_LIF_SETATTR, 1066 .attr = IONIC_LIF_ATTR_RSS, 1067 .rss.types = rte_cpu_to_le_16(types), 1068 .rss.addr = rte_cpu_to_le_64(lif->rss_ind_tbl_pa), 1069 }, 1070 }; 1071 unsigned int i; 1072 uint16_t tbl_sz = 1073 rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz); 1074 1075 IONIC_PRINT_CALL(); 1076 1077 lif->rss_types = types; 1078 1079 if (key) 1080 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); 1081 1082 if (indir) 1083 for (i = 0; i < tbl_sz; i++) 1084 lif->rss_ind_tbl[i] = indir[i]; 1085 1086 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, 1087 IONIC_RSS_HASH_KEY_SIZE); 1088 1089 return ionic_adminq_post_wait(lif, &ctx); 1090 } 1091 1092 static int 1093 ionic_lif_rss_setup(struct ionic_lif *lif) 1094 { 1095 struct ionic_adapter *adapter = lif->adapter; 1096 static const uint8_t toeplitz_symmetric_key[] = { 1097 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 1098 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 1099 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 1100 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 1101 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 1102 }; 1103 uint32_t i; 1104 uint16_t tbl_sz = 1105 rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz); 1106 1107 IONIC_PRINT_CALL(); 1108 1109 if (!lif->rss_ind_tbl_z) { 1110 lif->rss_ind_tbl_z = rte_eth_dma_zone_reserve(lif->eth_dev, 1111 "rss_ind_tbl", 0 /* queue_idx */, 1112 sizeof(*lif->rss_ind_tbl) * tbl_sz, 1113 IONIC_ALIGN, rte_socket_id()); 1114 if (!lif->rss_ind_tbl_z) { 1115 IONIC_PRINT(ERR, "OOM"); 1116 return -ENOMEM; 1117 } 1118 1119 lif->rss_ind_tbl = lif->rss_ind_tbl_z->addr; 1120 lif->rss_ind_tbl_pa = lif->rss_ind_tbl_z->iova; 1121 } 1122 1123 if (lif->rss_ind_tbl_nrxqcqs != lif->nrxqcqs) { 1124 lif->rss_ind_tbl_nrxqcqs = lif->nrxqcqs; 1125 1126 /* Fill indirection table with 'default' values */ 1127 for (i = 0; i < tbl_sz; i++) 1128 lif->rss_ind_tbl[i] = i % lif->nrxqcqs; 1129 } 1130 1131 return ionic_lif_rss_config(lif, IONIC_RSS_OFFLOAD_ALL, 1132 toeplitz_symmetric_key, NULL); 1133 } 1134 1135 static void 1136 ionic_lif_rss_teardown(struct ionic_lif *lif) 1137 { 1138 if (!lif->rss_ind_tbl) 1139 return; 1140 1141 if (lif->rss_ind_tbl_z) { 1142 /* Disable RSS on the NIC */ 1143 ionic_lif_rss_config(lif, 0x0, NULL, NULL); 1144 1145 lif->rss_ind_tbl = NULL; 1146 lif->rss_ind_tbl_pa = 0; 1147 rte_memzone_free(lif->rss_ind_tbl_z); 1148 lif->rss_ind_tbl_z = NULL; 1149 } 1150 } 1151 1152 void 1153 ionic_lif_txq_deinit(struct ionic_tx_qcq *txq) 1154 { 1155 txq->flags &= ~IONIC_QCQ_F_INITED; 1156 } 1157 1158 void 1159 ionic_lif_rxq_deinit(struct ionic_rx_qcq *rxq) 1160 { 1161 rxq->flags &= ~IONIC_QCQ_F_INITED; 1162 } 1163 1164 static void 1165 ionic_lif_adminq_deinit(struct ionic_lif *lif) 1166 { 1167 lif->adminqcq->flags &= ~IONIC_QCQ_F_INITED; 1168 } 1169 1170 static void 1171 ionic_lif_notifyq_deinit(struct ionic_lif *lif) 1172 { 1173 struct ionic_notify_qcq *nqcq = lif->notifyqcq; 1174 struct ionic_dev *idev = &lif->adapter->idev; 1175 1176 if (!(nqcq->flags & IONIC_QCQ_F_INITED)) 1177 return; 1178 1179 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index, 1180 IONIC_INTR_MASK_SET); 1181 1182 nqcq->flags &= ~IONIC_QCQ_F_INITED; 1183 } 1184 1185 /* This acts like ionic_napi */ 1186 int 1187 ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb, 1188 void *cb_arg) 1189 { 1190 struct ionic_cq *cq = &qcq->cq; 1191 uint32_t work_done; 1192 1193 work_done = ionic_cq_service(cq, budget, cb, cb_arg); 1194 1195 return work_done; 1196 } 1197 1198 static void 1199 ionic_link_status_check(struct ionic_lif *lif) 1200 { 1201 struct ionic_adapter *adapter = lif->adapter; 1202 bool link_up; 1203 1204 lif->state &= ~IONIC_LIF_F_LINK_CHECK_NEEDED; 1205 1206 if (!lif->info) 1207 return; 1208 1209 link_up = (lif->info->status.link_status == IONIC_PORT_OPER_STATUS_UP); 1210 1211 if ((link_up && adapter->link_up) || 1212 (!link_up && !adapter->link_up)) 1213 return; 1214 1215 if (link_up) { 1216 adapter->link_speed = 1217 rte_le_to_cpu_32(lif->info->status.link_speed); 1218 IONIC_PRINT(DEBUG, "Link up - %d Gbps", 1219 adapter->link_speed); 1220 } else { 1221 IONIC_PRINT(DEBUG, "Link down"); 1222 } 1223 1224 adapter->link_up = link_up; 1225 ionic_dev_link_update(lif->eth_dev, 0); 1226 } 1227 1228 static void 1229 ionic_lif_handle_fw_down(struct ionic_lif *lif) 1230 { 1231 if (lif->state & IONIC_LIF_F_FW_RESET) 1232 return; 1233 1234 lif->state |= IONIC_LIF_F_FW_RESET; 1235 1236 if (lif->state & IONIC_LIF_F_UP) { 1237 IONIC_PRINT(NOTICE, 1238 "Surprise FW stop, stopping %s\n", lif->name); 1239 ionic_lif_stop(lif); 1240 } 1241 1242 IONIC_PRINT(NOTICE, "FW down, %s stopped", lif->name); 1243 } 1244 1245 static bool 1246 ionic_notifyq_cb(struct ionic_cq *cq, uint16_t cq_desc_index, void *cb_arg) 1247 { 1248 union ionic_notifyq_comp *cq_desc_base = cq->base; 1249 union ionic_notifyq_comp *cq_desc = &cq_desc_base[cq_desc_index]; 1250 struct ionic_lif *lif = cb_arg; 1251 1252 IONIC_PRINT(DEBUG, "Notifyq callback eid = %jd ecode = %d", 1253 cq_desc->event.eid, cq_desc->event.ecode); 1254 1255 /* Have we run out of new completions to process? */ 1256 if (!(cq_desc->event.eid > lif->last_eid)) 1257 return false; 1258 1259 lif->last_eid = cq_desc->event.eid; 1260 1261 switch (cq_desc->event.ecode) { 1262 case IONIC_EVENT_LINK_CHANGE: 1263 IONIC_PRINT(DEBUG, 1264 "Notifyq IONIC_EVENT_LINK_CHANGE %s " 1265 "eid=%jd link_status=%d link_speed=%d", 1266 lif->name, 1267 cq_desc->event.eid, 1268 cq_desc->link_change.link_status, 1269 cq_desc->link_change.link_speed); 1270 1271 lif->state |= IONIC_LIF_F_LINK_CHECK_NEEDED; 1272 break; 1273 1274 case IONIC_EVENT_RESET: 1275 IONIC_PRINT(NOTICE, 1276 "Notifyq IONIC_EVENT_RESET %s " 1277 "eid=%jd, reset_code=%d state=%d", 1278 lif->name, 1279 cq_desc->event.eid, 1280 cq_desc->reset.reset_code, 1281 cq_desc->reset.state); 1282 ionic_lif_handle_fw_down(lif); 1283 break; 1284 1285 default: 1286 IONIC_PRINT(WARNING, "Notifyq bad event ecode=%d eid=%jd", 1287 cq_desc->event.ecode, cq_desc->event.eid); 1288 break; 1289 } 1290 1291 return true; 1292 } 1293 1294 int 1295 ionic_notifyq_handler(struct ionic_lif *lif, int budget) 1296 { 1297 struct ionic_dev *idev = &lif->adapter->idev; 1298 struct ionic_notify_qcq *nqcq = lif->notifyqcq; 1299 uint32_t work_done; 1300 1301 if (!(nqcq->flags & IONIC_QCQ_F_INITED)) { 1302 IONIC_PRINT(DEBUG, "Notifyq not yet initialized"); 1303 return -1; 1304 } 1305 1306 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index, 1307 IONIC_INTR_MASK_SET); 1308 1309 work_done = ionic_qcq_service(&nqcq->qcq, budget, 1310 ionic_notifyq_cb, lif); 1311 1312 if (lif->state & IONIC_LIF_F_LINK_CHECK_NEEDED) 1313 ionic_link_status_check(lif); 1314 1315 ionic_intr_credits(idev->intr_ctrl, nqcq->intr.index, 1316 work_done, IONIC_INTR_CRED_RESET_COALESCE); 1317 1318 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index, 1319 IONIC_INTR_MASK_CLEAR); 1320 1321 return 0; 1322 } 1323 1324 static int 1325 ionic_lif_adminq_init(struct ionic_lif *lif) 1326 { 1327 struct ionic_dev *idev = &lif->adapter->idev; 1328 struct ionic_admin_qcq *aqcq = lif->adminqcq; 1329 struct ionic_queue *q = &aqcq->qcq.q; 1330 struct ionic_q_init_comp comp; 1331 int err; 1332 1333 ionic_dev_cmd_adminq_init(idev, &aqcq->qcq); 1334 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 1335 if (err) 1336 return err; 1337 1338 ionic_dev_cmd_comp(idev, &comp); 1339 1340 q->hw_type = comp.hw_type; 1341 q->hw_index = rte_le_to_cpu_32(comp.hw_index); 1342 q->db = ionic_db_map(lif, q); 1343 1344 IONIC_PRINT(DEBUG, "adminq->hw_type %d", q->hw_type); 1345 IONIC_PRINT(DEBUG, "adminq->hw_index %d", q->hw_index); 1346 IONIC_PRINT(DEBUG, "adminq->db %p", q->db); 1347 1348 aqcq->flags |= IONIC_QCQ_F_INITED; 1349 1350 return 0; 1351 } 1352 1353 static int 1354 ionic_lif_notifyq_init(struct ionic_lif *lif) 1355 { 1356 struct ionic_dev *idev = &lif->adapter->idev; 1357 struct ionic_notify_qcq *nqcq = lif->notifyqcq; 1358 struct ionic_queue *q = &nqcq->qcq.q; 1359 int err; 1360 1361 struct ionic_admin_ctx ctx = { 1362 .pending_work = true, 1363 .cmd.q_init = { 1364 .opcode = IONIC_CMD_Q_INIT, 1365 .type = q->type, 1366 .ver = lif->qtype_info[q->type].version, 1367 .index = rte_cpu_to_le_32(q->index), 1368 .intr_index = rte_cpu_to_le_16(nqcq->intr.index), 1369 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_IRQ | 1370 IONIC_QINIT_F_ENA), 1371 .ring_size = rte_log2_u32(q->num_descs), 1372 .ring_base = rte_cpu_to_le_64(q->base_pa), 1373 } 1374 }; 1375 1376 IONIC_PRINT(DEBUG, "notifyq_init.index %d", q->index); 1377 IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "", q->base_pa); 1378 IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d", 1379 ctx.cmd.q_init.ring_size); 1380 IONIC_PRINT(DEBUG, "notifyq_init.ver %u", ctx.cmd.q_init.ver); 1381 1382 err = ionic_adminq_post_wait(lif, &ctx); 1383 if (err) 1384 return err; 1385 1386 q->hw_type = ctx.comp.q_init.hw_type; 1387 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index); 1388 q->db = NULL; 1389 1390 IONIC_PRINT(DEBUG, "notifyq->hw_type %d", q->hw_type); 1391 IONIC_PRINT(DEBUG, "notifyq->hw_index %d", q->hw_index); 1392 IONIC_PRINT(DEBUG, "notifyq->db %p", q->db); 1393 1394 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index, 1395 IONIC_INTR_MASK_CLEAR); 1396 1397 nqcq->flags |= IONIC_QCQ_F_INITED; 1398 1399 return 0; 1400 } 1401 1402 int 1403 ionic_lif_set_features(struct ionic_lif *lif) 1404 { 1405 struct ionic_admin_ctx ctx = { 1406 .pending_work = true, 1407 .cmd.lif_setattr = { 1408 .opcode = IONIC_CMD_LIF_SETATTR, 1409 .attr = IONIC_LIF_ATTR_FEATURES, 1410 .features = rte_cpu_to_le_64(lif->features), 1411 }, 1412 }; 1413 int err; 1414 1415 err = ionic_adminq_post_wait(lif, &ctx); 1416 if (err) 1417 return err; 1418 1419 lif->hw_features = rte_le_to_cpu_64(ctx.cmd.lif_setattr.features & 1420 ctx.comp.lif_setattr.features); 1421 1422 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1423 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_TX_TAG"); 1424 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1425 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_STRIP"); 1426 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1427 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_FILTER"); 1428 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1429 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_HASH"); 1430 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1431 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_SG"); 1432 if (lif->hw_features & IONIC_ETH_HW_RX_SG) 1433 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_SG"); 1434 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1435 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_CSUM"); 1436 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1437 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_CSUM"); 1438 if (lif->hw_features & IONIC_ETH_HW_TSO) 1439 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO"); 1440 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1441 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPV6"); 1442 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1443 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_ECN"); 1444 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1445 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE"); 1446 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1447 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE_CSUM"); 1448 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1449 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP4"); 1450 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1451 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP6"); 1452 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1453 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP"); 1454 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1455 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP_CSUM"); 1456 1457 return 0; 1458 } 1459 1460 int 1461 ionic_lif_txq_init(struct ionic_tx_qcq *txq) 1462 { 1463 struct ionic_qcq *qcq = &txq->qcq; 1464 struct ionic_queue *q = &qcq->q; 1465 struct ionic_lif *lif = qcq->lif; 1466 struct ionic_cq *cq = &qcq->cq; 1467 struct ionic_admin_ctx ctx = { 1468 .pending_work = true, 1469 .cmd.q_init = { 1470 .opcode = IONIC_CMD_Q_INIT, 1471 .type = q->type, 1472 .ver = lif->qtype_info[q->type].version, 1473 .index = rte_cpu_to_le_32(q->index), 1474 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG | 1475 IONIC_QINIT_F_ENA), 1476 .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE), 1477 .ring_size = rte_log2_u32(q->num_descs), 1478 .ring_base = rte_cpu_to_le_64(q->base_pa), 1479 .cq_ring_base = rte_cpu_to_le_64(cq->base_pa), 1480 .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa), 1481 }, 1482 }; 1483 int err; 1484 1485 IONIC_PRINT(DEBUG, "txq_init.index %d", q->index); 1486 IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "", q->base_pa); 1487 IONIC_PRINT(DEBUG, "txq_init.ring_size %d", 1488 ctx.cmd.q_init.ring_size); 1489 IONIC_PRINT(DEBUG, "txq_init.ver %u", ctx.cmd.q_init.ver); 1490 1491 err = ionic_adminq_post_wait(lif, &ctx); 1492 if (err) 1493 return err; 1494 1495 q->hw_type = ctx.comp.q_init.hw_type; 1496 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index); 1497 q->db = ionic_db_map(lif, q); 1498 1499 IONIC_PRINT(DEBUG, "txq->hw_type %d", q->hw_type); 1500 IONIC_PRINT(DEBUG, "txq->hw_index %d", q->hw_index); 1501 IONIC_PRINT(DEBUG, "txq->db %p", q->db); 1502 1503 txq->flags |= IONIC_QCQ_F_INITED; 1504 1505 return 0; 1506 } 1507 1508 int 1509 ionic_lif_rxq_init(struct ionic_rx_qcq *rxq) 1510 { 1511 struct ionic_qcq *qcq = &rxq->qcq; 1512 struct ionic_queue *q = &qcq->q; 1513 struct ionic_lif *lif = qcq->lif; 1514 struct ionic_cq *cq = &qcq->cq; 1515 struct ionic_admin_ctx ctx = { 1516 .pending_work = true, 1517 .cmd.q_init = { 1518 .opcode = IONIC_CMD_Q_INIT, 1519 .type = q->type, 1520 .ver = lif->qtype_info[q->type].version, 1521 .index = rte_cpu_to_le_32(q->index), 1522 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG | 1523 IONIC_QINIT_F_ENA), 1524 .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE), 1525 .ring_size = rte_log2_u32(q->num_descs), 1526 .ring_base = rte_cpu_to_le_64(q->base_pa), 1527 .cq_ring_base = rte_cpu_to_le_64(cq->base_pa), 1528 .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa), 1529 }, 1530 }; 1531 int err; 1532 1533 IONIC_PRINT(DEBUG, "rxq_init.index %d", q->index); 1534 IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "", q->base_pa); 1535 IONIC_PRINT(DEBUG, "rxq_init.ring_size %d", 1536 ctx.cmd.q_init.ring_size); 1537 IONIC_PRINT(DEBUG, "rxq_init.ver %u", ctx.cmd.q_init.ver); 1538 1539 err = ionic_adminq_post_wait(lif, &ctx); 1540 if (err) 1541 return err; 1542 1543 q->hw_type = ctx.comp.q_init.hw_type; 1544 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index); 1545 q->db = ionic_db_map(lif, q); 1546 1547 rxq->flags |= IONIC_QCQ_F_INITED; 1548 1549 IONIC_PRINT(DEBUG, "rxq->hw_type %d", q->hw_type); 1550 IONIC_PRINT(DEBUG, "rxq->hw_index %d", q->hw_index); 1551 IONIC_PRINT(DEBUG, "rxq->db %p", q->db); 1552 1553 return 0; 1554 } 1555 1556 static int 1557 ionic_station_set(struct ionic_lif *lif) 1558 { 1559 struct ionic_admin_ctx ctx = { 1560 .pending_work = true, 1561 .cmd.lif_getattr = { 1562 .opcode = IONIC_CMD_LIF_GETATTR, 1563 .attr = IONIC_LIF_ATTR_MAC, 1564 }, 1565 }; 1566 int err; 1567 1568 IONIC_PRINT_CALL(); 1569 1570 err = ionic_adminq_post_wait(lif, &ctx); 1571 if (err) 1572 return err; 1573 1574 memcpy(lif->mac_addr, ctx.comp.lif_getattr.mac, RTE_ETHER_ADDR_LEN); 1575 1576 return 0; 1577 } 1578 1579 static void 1580 ionic_lif_set_name(struct ionic_lif *lif) 1581 { 1582 struct ionic_admin_ctx ctx = { 1583 .pending_work = true, 1584 .cmd.lif_setattr = { 1585 .opcode = IONIC_CMD_LIF_SETATTR, 1586 .attr = IONIC_LIF_ATTR_NAME, 1587 }, 1588 }; 1589 1590 memcpy(ctx.cmd.lif_setattr.name, lif->name, 1591 sizeof(ctx.cmd.lif_setattr.name) - 1); 1592 1593 ionic_adminq_post_wait(lif, &ctx); 1594 } 1595 1596 int 1597 ionic_lif_init(struct ionic_lif *lif) 1598 { 1599 struct ionic_dev *idev = &lif->adapter->idev; 1600 struct ionic_q_init_comp comp; 1601 int err; 1602 1603 memset(&lif->stats_base, 0, sizeof(lif->stats_base)); 1604 1605 ionic_dev_cmd_lif_init(idev, lif->info_pa); 1606 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 1607 ionic_dev_cmd_comp(idev, &comp); 1608 if (err) 1609 return err; 1610 1611 lif->hw_index = rte_cpu_to_le_16(comp.hw_index); 1612 1613 err = ionic_lif_adminq_init(lif); 1614 if (err) 1615 return err; 1616 1617 err = ionic_lif_notifyq_init(lif); 1618 if (err) 1619 goto err_out_adminq_deinit; 1620 1621 /* 1622 * Configure initial feature set 1623 * This will be updated later by the dev_configure() step 1624 */ 1625 lif->features = IONIC_ETH_HW_RX_HASH | IONIC_ETH_HW_VLAN_RX_FILTER; 1626 1627 err = ionic_lif_set_features(lif); 1628 if (err) 1629 goto err_out_notifyq_deinit; 1630 1631 err = ionic_rx_filters_init(lif); 1632 if (err) 1633 goto err_out_notifyq_deinit; 1634 1635 err = ionic_station_set(lif); 1636 if (err) 1637 goto err_out_rx_filter_deinit; 1638 1639 ionic_lif_set_name(lif); 1640 1641 lif->state |= IONIC_LIF_F_INITED; 1642 1643 return 0; 1644 1645 err_out_rx_filter_deinit: 1646 ionic_rx_filters_deinit(lif); 1647 1648 err_out_notifyq_deinit: 1649 ionic_lif_notifyq_deinit(lif); 1650 1651 err_out_adminq_deinit: 1652 ionic_lif_adminq_deinit(lif); 1653 1654 return err; 1655 } 1656 1657 void 1658 ionic_lif_deinit(struct ionic_lif *lif) 1659 { 1660 if (!(lif->state & IONIC_LIF_F_INITED)) 1661 return; 1662 1663 ionic_rx_filters_deinit(lif); 1664 ionic_lif_rss_teardown(lif); 1665 ionic_lif_notifyq_deinit(lif); 1666 ionic_lif_adminq_deinit(lif); 1667 1668 lif->state &= ~IONIC_LIF_F_INITED; 1669 } 1670 1671 void 1672 ionic_lif_configure_vlan_offload(struct ionic_lif *lif, int mask) 1673 { 1674 struct rte_eth_dev *eth_dev = lif->eth_dev; 1675 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 1676 1677 /* 1678 * IONIC_ETH_HW_VLAN_RX_FILTER cannot be turned off, so 1679 * set DEV_RX_OFFLOAD_VLAN_FILTER and ignore ETH_VLAN_FILTER_MASK 1680 */ 1681 rxmode->offloads |= DEV_RX_OFFLOAD_VLAN_FILTER; 1682 1683 if (mask & ETH_VLAN_STRIP_MASK) { 1684 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1685 lif->features |= IONIC_ETH_HW_VLAN_RX_STRIP; 1686 else 1687 lif->features &= ~IONIC_ETH_HW_VLAN_RX_STRIP; 1688 } 1689 } 1690 1691 void 1692 ionic_lif_configure(struct ionic_lif *lif) 1693 { 1694 struct rte_eth_rxmode *rxmode = &lif->eth_dev->data->dev_conf.rxmode; 1695 struct rte_eth_txmode *txmode = &lif->eth_dev->data->dev_conf.txmode; 1696 struct ionic_identity *ident = &lif->adapter->ident; 1697 union ionic_lif_config *cfg = &ident->lif.eth.config; 1698 uint32_t ntxqs_per_lif = 1699 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); 1700 uint32_t nrxqs_per_lif = 1701 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); 1702 uint32_t nrxqs = lif->eth_dev->data->nb_rx_queues; 1703 uint32_t ntxqs = lif->eth_dev->data->nb_tx_queues; 1704 1705 lif->port_id = lif->eth_dev->data->port_id; 1706 1707 IONIC_PRINT(DEBUG, "Configuring LIF on port %u", 1708 lif->port_id); 1709 1710 if (nrxqs > 0) 1711 nrxqs_per_lif = RTE_MIN(nrxqs_per_lif, nrxqs); 1712 1713 if (ntxqs > 0) 1714 ntxqs_per_lif = RTE_MIN(ntxqs_per_lif, ntxqs); 1715 1716 lif->nrxqcqs = nrxqs_per_lif; 1717 lif->ntxqcqs = ntxqs_per_lif; 1718 1719 /* Update the LIF configuration based on the eth_dev */ 1720 1721 /* 1722 * NB: While it is true that RSS_HASH is always enabled on ionic, 1723 * setting this flag unconditionally causes problems in DTS. 1724 * rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1725 */ 1726 1727 /* RX per-port */ 1728 1729 if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM || 1730 rxmode->offloads & DEV_RX_OFFLOAD_UDP_CKSUM || 1731 rxmode->offloads & DEV_RX_OFFLOAD_TCP_CKSUM) 1732 lif->features |= IONIC_ETH_HW_RX_CSUM; 1733 else 1734 lif->features &= ~IONIC_ETH_HW_RX_CSUM; 1735 1736 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) { 1737 lif->features |= IONIC_ETH_HW_RX_SG; 1738 lif->eth_dev->data->scattered_rx = 1; 1739 } else { 1740 lif->features &= ~IONIC_ETH_HW_RX_SG; 1741 lif->eth_dev->data->scattered_rx = 0; 1742 } 1743 1744 /* Covers VLAN_STRIP */ 1745 ionic_lif_configure_vlan_offload(lif, ETH_VLAN_STRIP_MASK); 1746 1747 /* TX per-port */ 1748 1749 if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM || 1750 txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM || 1751 txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM || 1752 txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM || 1753 txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM) 1754 lif->features |= IONIC_ETH_HW_TX_CSUM; 1755 else 1756 lif->features &= ~IONIC_ETH_HW_TX_CSUM; 1757 1758 if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT) 1759 lif->features |= IONIC_ETH_HW_VLAN_TX_TAG; 1760 else 1761 lif->features &= ~IONIC_ETH_HW_VLAN_TX_TAG; 1762 1763 if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS) 1764 lif->features |= IONIC_ETH_HW_TX_SG; 1765 else 1766 lif->features &= ~IONIC_ETH_HW_TX_SG; 1767 1768 if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) { 1769 lif->features |= IONIC_ETH_HW_TSO; 1770 lif->features |= IONIC_ETH_HW_TSO_IPV6; 1771 lif->features |= IONIC_ETH_HW_TSO_ECN; 1772 } else { 1773 lif->features &= ~IONIC_ETH_HW_TSO; 1774 lif->features &= ~IONIC_ETH_HW_TSO_IPV6; 1775 lif->features &= ~IONIC_ETH_HW_TSO_ECN; 1776 } 1777 } 1778 1779 int 1780 ionic_lif_start(struct ionic_lif *lif) 1781 { 1782 uint32_t rx_mode; 1783 uint32_t i; 1784 int err; 1785 1786 err = ionic_lif_rss_setup(lif); 1787 if (err) 1788 return err; 1789 1790 if (!lif->rx_mode) { 1791 IONIC_PRINT(DEBUG, "Setting RX mode on %s", 1792 lif->name); 1793 1794 rx_mode = IONIC_RX_MODE_F_UNICAST; 1795 rx_mode |= IONIC_RX_MODE_F_MULTICAST; 1796 rx_mode |= IONIC_RX_MODE_F_BROADCAST; 1797 1798 ionic_set_rx_mode(lif, rx_mode); 1799 } 1800 1801 IONIC_PRINT(DEBUG, "Starting %u RX queues and %u TX queues " 1802 "on port %u", 1803 lif->nrxqcqs, lif->ntxqcqs, lif->port_id); 1804 1805 for (i = 0; i < lif->nrxqcqs; i++) { 1806 struct ionic_rx_qcq *rxq = lif->rxqcqs[i]; 1807 if (!(rxq->flags & IONIC_QCQ_F_DEFERRED)) { 1808 err = ionic_dev_rx_queue_start(lif->eth_dev, i); 1809 1810 if (err) 1811 return err; 1812 } 1813 } 1814 1815 for (i = 0; i < lif->ntxqcqs; i++) { 1816 struct ionic_tx_qcq *txq = lif->txqcqs[i]; 1817 if (!(txq->flags & IONIC_QCQ_F_DEFERRED)) { 1818 err = ionic_dev_tx_queue_start(lif->eth_dev, i); 1819 1820 if (err) 1821 return err; 1822 } 1823 } 1824 1825 /* Carrier ON here */ 1826 lif->state |= IONIC_LIF_F_UP; 1827 1828 ionic_link_status_check(lif); 1829 1830 return 0; 1831 } 1832 1833 int 1834 ionic_lif_identify(struct ionic_adapter *adapter) 1835 { 1836 struct ionic_dev *idev = &adapter->idev; 1837 struct ionic_identity *ident = &adapter->ident; 1838 union ionic_lif_config *cfg = &ident->lif.eth.config; 1839 uint32_t lif_words = RTE_DIM(ident->lif.words); 1840 uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data); 1841 uint32_t i, nwords; 1842 int err; 1843 1844 ionic_dev_cmd_lif_identify(idev, IONIC_LIF_TYPE_CLASSIC, 1845 IONIC_IDENTITY_VERSION_1); 1846 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 1847 if (err) 1848 return (err); 1849 1850 nwords = RTE_MIN(lif_words, cmd_words); 1851 for (i = 0; i < nwords; i++) 1852 ident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]); 1853 1854 IONIC_PRINT(INFO, "capabilities 0x%" PRIx64 " ", 1855 rte_le_to_cpu_64(ident->lif.capabilities)); 1856 1857 IONIC_PRINT(INFO, "eth.max_ucast_filters 0x%" PRIx32 " ", 1858 rte_le_to_cpu_32(ident->lif.eth.max_ucast_filters)); 1859 IONIC_PRINT(INFO, "eth.max_mcast_filters 0x%" PRIx32 " ", 1860 rte_le_to_cpu_32(ident->lif.eth.max_mcast_filters)); 1861 1862 IONIC_PRINT(INFO, "eth.features 0x%" PRIx64 " ", 1863 rte_le_to_cpu_64(cfg->features)); 1864 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%" PRIx32 " ", 1865 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_ADMINQ])); 1866 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%" PRIx32 " ", 1867 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_NOTIFYQ])); 1868 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_RXQ] 0x%" PRIx32 " ", 1869 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ])); 1870 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_TXQ] 0x%" PRIx32 " ", 1871 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ])); 1872 1873 return 0; 1874 } 1875 1876 int 1877 ionic_lifs_size(struct ionic_adapter *adapter) 1878 { 1879 struct ionic_identity *ident = &adapter->ident; 1880 union ionic_lif_config *cfg = &ident->lif.eth.config; 1881 uint32_t nintrs, dev_nintrs = rte_le_to_cpu_32(ident->dev.nintrs); 1882 1883 adapter->max_ntxqs_per_lif = 1884 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); 1885 adapter->max_nrxqs_per_lif = 1886 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); 1887 1888 nintrs = 1 /* notifyq */; 1889 1890 if (nintrs > dev_nintrs) { 1891 IONIC_PRINT(ERR, 1892 "At most %d intr supported, minimum req'd is %u", 1893 dev_nintrs, nintrs); 1894 return -ENOSPC; 1895 } 1896 1897 adapter->nintrs = nintrs; 1898 1899 return 0; 1900 } 1901