1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved. 3 */ 4 5 #include <rte_malloc.h> 6 #include <ethdev_driver.h> 7 8 #include "ionic.h" 9 #include "ionic_logs.h" 10 #include "ionic_lif.h" 11 #include "ionic_ethdev.h" 12 #include "ionic_rx_filter.h" 13 #include "ionic_rxtx.h" 14 15 /* queuetype support level */ 16 static const uint8_t ionic_qtype_vers[IONIC_QTYPE_MAX] = { 17 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ 18 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ 19 [IONIC_QTYPE_RXQ] = 2, /* 0 = Base version with CQ+SG support 20 * 1 = ... with EQ 21 * 2 = ... with CMB 22 */ 23 [IONIC_QTYPE_TXQ] = 3, /* 0 = Base version with CQ+SG support 24 * 1 = ... with Tx SG version 1 25 * 2 = ... with EQ 26 * 3 = ... with CMB 27 */ 28 }; 29 30 static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr); 31 static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr); 32 33 int 34 ionic_qcq_enable(struct ionic_qcq *qcq) 35 { 36 struct ionic_queue *q = &qcq->q; 37 struct ionic_lif *lif = qcq->lif; 38 struct ionic_admin_ctx ctx = { 39 .pending_work = true, 40 .cmd.q_control = { 41 .opcode = IONIC_CMD_Q_CONTROL, 42 .type = q->type, 43 .index = rte_cpu_to_le_32(q->index), 44 .oper = IONIC_Q_ENABLE, 45 }, 46 }; 47 48 return ionic_adminq_post_wait(lif, &ctx); 49 } 50 51 int 52 ionic_qcq_disable(struct ionic_qcq *qcq) 53 { 54 struct ionic_queue *q = &qcq->q; 55 struct ionic_lif *lif = qcq->lif; 56 struct ionic_admin_ctx ctx = { 57 .pending_work = true, 58 .cmd.q_control = { 59 .opcode = IONIC_CMD_Q_CONTROL, 60 .type = q->type, 61 .index = rte_cpu_to_le_32(q->index), 62 .oper = IONIC_Q_DISABLE, 63 }, 64 }; 65 66 return ionic_adminq_post_wait(lif, &ctx); 67 } 68 69 void 70 ionic_lif_stop(struct ionic_lif *lif) 71 { 72 uint32_t i; 73 74 IONIC_PRINT_CALL(); 75 76 lif->state &= ~IONIC_LIF_F_UP; 77 78 for (i = 0; i < lif->nrxqcqs; i++) { 79 struct ionic_rx_qcq *rxq = lif->rxqcqs[i]; 80 if (rxq->flags & IONIC_QCQ_F_INITED) 81 (void)ionic_dev_rx_queue_stop(lif->eth_dev, i); 82 } 83 84 for (i = 0; i < lif->ntxqcqs; i++) { 85 struct ionic_tx_qcq *txq = lif->txqcqs[i]; 86 if (txq->flags & IONIC_QCQ_F_INITED) 87 (void)ionic_dev_tx_queue_stop(lif->eth_dev, i); 88 } 89 } 90 91 void 92 ionic_lif_reset(struct ionic_lif *lif) 93 { 94 struct ionic_dev *idev = &lif->adapter->idev; 95 int err; 96 97 IONIC_PRINT_CALL(); 98 99 ionic_dev_cmd_lif_reset(idev); 100 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 101 if (err) 102 IONIC_PRINT(WARNING, "Failed to reset %s", lif->name); 103 } 104 105 static void 106 ionic_lif_get_abs_stats(const struct ionic_lif *lif, struct rte_eth_stats *stats) 107 { 108 struct ionic_lif_stats *ls = &lif->info->stats; 109 uint32_t i; 110 uint32_t num_rx_q_counters = RTE_MIN(lif->nrxqcqs, (uint32_t) 111 RTE_ETHDEV_QUEUE_STAT_CNTRS); 112 uint32_t num_tx_q_counters = RTE_MIN(lif->ntxqcqs, (uint32_t) 113 RTE_ETHDEV_QUEUE_STAT_CNTRS); 114 115 memset(stats, 0, sizeof(*stats)); 116 117 if (ls == NULL) { 118 IONIC_PRINT(DEBUG, "Stats on port %u not yet initialized", 119 lif->port_id); 120 return; 121 } 122 123 /* RX */ 124 125 stats->ipackets = ls->rx_ucast_packets + 126 ls->rx_mcast_packets + 127 ls->rx_bcast_packets; 128 129 stats->ibytes = ls->rx_ucast_bytes + 130 ls->rx_mcast_bytes + 131 ls->rx_bcast_bytes; 132 133 for (i = 0; i < lif->nrxqcqs; i++) { 134 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats; 135 stats->imissed += 136 rx_stats->no_cb_arg + 137 rx_stats->bad_cq_status + 138 rx_stats->no_room + 139 rx_stats->bad_len; 140 } 141 142 stats->imissed += 143 ls->rx_ucast_drop_packets + 144 ls->rx_mcast_drop_packets + 145 ls->rx_bcast_drop_packets; 146 147 stats->imissed += 148 ls->rx_queue_empty + 149 ls->rx_dma_error + 150 ls->rx_queue_disabled + 151 ls->rx_desc_fetch_error + 152 ls->rx_desc_data_error; 153 154 for (i = 0; i < num_rx_q_counters; i++) { 155 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats; 156 stats->q_ipackets[i] = rx_stats->packets; 157 stats->q_ibytes[i] = rx_stats->bytes; 158 stats->q_errors[i] = 159 rx_stats->no_cb_arg + 160 rx_stats->bad_cq_status + 161 rx_stats->no_room + 162 rx_stats->bad_len; 163 } 164 165 /* TX */ 166 167 stats->opackets = ls->tx_ucast_packets + 168 ls->tx_mcast_packets + 169 ls->tx_bcast_packets; 170 171 stats->obytes = ls->tx_ucast_bytes + 172 ls->tx_mcast_bytes + 173 ls->tx_bcast_bytes; 174 175 for (i = 0; i < lif->ntxqcqs; i++) { 176 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats; 177 stats->oerrors += tx_stats->drop; 178 } 179 180 stats->oerrors += 181 ls->tx_ucast_drop_packets + 182 ls->tx_mcast_drop_packets + 183 ls->tx_bcast_drop_packets; 184 185 stats->oerrors += 186 ls->tx_dma_error + 187 ls->tx_queue_disabled + 188 ls->tx_desc_fetch_error + 189 ls->tx_desc_data_error; 190 191 for (i = 0; i < num_tx_q_counters; i++) { 192 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats; 193 stats->q_opackets[i] = tx_stats->packets; 194 stats->q_obytes[i] = tx_stats->bytes; 195 } 196 } 197 198 void 199 ionic_lif_get_stats(const struct ionic_lif *lif, 200 struct rte_eth_stats *stats) 201 { 202 ionic_lif_get_abs_stats(lif, stats); 203 204 stats->ipackets -= lif->stats_base.ipackets; 205 stats->opackets -= lif->stats_base.opackets; 206 stats->ibytes -= lif->stats_base.ibytes; 207 stats->obytes -= lif->stats_base.obytes; 208 stats->imissed -= lif->stats_base.imissed; 209 stats->ierrors -= lif->stats_base.ierrors; 210 stats->oerrors -= lif->stats_base.oerrors; 211 stats->rx_nombuf -= lif->stats_base.rx_nombuf; 212 } 213 214 void 215 ionic_lif_reset_stats(struct ionic_lif *lif) 216 { 217 uint32_t i; 218 219 for (i = 0; i < lif->nrxqcqs; i++) { 220 memset(&lif->rxqcqs[i]->stats, 0, 221 sizeof(struct ionic_rx_stats)); 222 memset(&lif->txqcqs[i]->stats, 0, 223 sizeof(struct ionic_tx_stats)); 224 } 225 226 ionic_lif_get_abs_stats(lif, &lif->stats_base); 227 } 228 229 void 230 ionic_lif_get_hw_stats(struct ionic_lif *lif, struct ionic_lif_stats *stats) 231 { 232 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t); 233 uint64_t *stats64 = (uint64_t *)stats; 234 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats; 235 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base; 236 237 for (i = 0; i < count; i++) 238 stats64[i] = lif_stats64[i] - lif_stats64_base[i]; 239 } 240 241 void 242 ionic_lif_reset_hw_stats(struct ionic_lif *lif) 243 { 244 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t); 245 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats; 246 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base; 247 248 for (i = 0; i < count; i++) 249 lif_stats64_base[i] = lif_stats64[i]; 250 } 251 252 static int 253 ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr) 254 { 255 struct ionic_admin_ctx ctx = { 256 .pending_work = true, 257 .cmd.rx_filter_add = { 258 .opcode = IONIC_CMD_RX_FILTER_ADD, 259 .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_MAC), 260 }, 261 }; 262 int err; 263 264 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, RTE_ETHER_ADDR_LEN); 265 266 err = ionic_adminq_post_wait(lif, &ctx); 267 if (err) 268 return err; 269 270 IONIC_PRINT(INFO, "rx_filter add (id %d)", 271 rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id)); 272 273 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx); 274 } 275 276 static int 277 ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr) 278 { 279 struct ionic_admin_ctx ctx = { 280 .pending_work = true, 281 .cmd.rx_filter_del = { 282 .opcode = IONIC_CMD_RX_FILTER_DEL, 283 }, 284 }; 285 struct ionic_rx_filter *f; 286 int err; 287 288 IONIC_PRINT_CALL(); 289 290 rte_spinlock_lock(&lif->rx_filters.lock); 291 292 f = ionic_rx_filter_by_addr(lif, addr); 293 if (!f) { 294 rte_spinlock_unlock(&lif->rx_filters.lock); 295 return -ENOENT; 296 } 297 298 ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id); 299 ionic_rx_filter_free(f); 300 301 rte_spinlock_unlock(&lif->rx_filters.lock); 302 303 err = ionic_adminq_post_wait(lif, &ctx); 304 if (err) 305 return err; 306 307 IONIC_PRINT(INFO, "rx_filter del (id %d)", 308 rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id)); 309 310 return 0; 311 } 312 313 int 314 ionic_dev_add_mac(struct rte_eth_dev *eth_dev, 315 struct rte_ether_addr *mac_addr, 316 uint32_t index __rte_unused, uint32_t pool __rte_unused) 317 { 318 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 319 320 IONIC_PRINT_CALL(); 321 322 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr); 323 } 324 325 void 326 ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index) 327 { 328 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 329 struct ionic_adapter *adapter = lif->adapter; 330 struct rte_ether_addr *mac_addr; 331 332 IONIC_PRINT_CALL(); 333 334 if (index >= adapter->max_mac_addrs) { 335 IONIC_PRINT(WARNING, 336 "Index %u is above MAC filter limit %u", 337 index, adapter->max_mac_addrs); 338 return; 339 } 340 341 mac_addr = ð_dev->data->mac_addrs[index]; 342 343 if (!rte_is_valid_assigned_ether_addr(mac_addr)) 344 return; 345 346 ionic_lif_addr_del(lif, (const uint8_t *)mac_addr); 347 } 348 349 int 350 ionic_dev_set_mac(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr) 351 { 352 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 353 354 IONIC_PRINT_CALL(); 355 356 if (mac_addr == NULL) { 357 IONIC_PRINT(NOTICE, "New mac is null"); 358 return -1; 359 } 360 361 if (!rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) { 362 IONIC_PRINT(INFO, "Deleting mac addr %pM", 363 lif->mac_addr); 364 ionic_lif_addr_del(lif, lif->mac_addr); 365 memset(lif->mac_addr, 0, RTE_ETHER_ADDR_LEN); 366 } 367 368 IONIC_PRINT(INFO, "Updating mac addr"); 369 370 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)lif->mac_addr); 371 372 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr); 373 } 374 375 static int 376 ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid) 377 { 378 struct ionic_admin_ctx ctx = { 379 .pending_work = true, 380 .cmd.rx_filter_add = { 381 .opcode = IONIC_CMD_RX_FILTER_ADD, 382 .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_VLAN), 383 .vlan.vlan = rte_cpu_to_le_16(vid), 384 }, 385 }; 386 int err; 387 388 err = ionic_adminq_post_wait(lif, &ctx); 389 if (err) 390 return err; 391 392 IONIC_PRINT(INFO, "rx_filter add VLAN %d (id %d)", vid, 393 rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id)); 394 395 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx); 396 } 397 398 static int 399 ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid) 400 { 401 struct ionic_admin_ctx ctx = { 402 .pending_work = true, 403 .cmd.rx_filter_del = { 404 .opcode = IONIC_CMD_RX_FILTER_DEL, 405 }, 406 }; 407 struct ionic_rx_filter *f; 408 int err; 409 410 IONIC_PRINT_CALL(); 411 412 rte_spinlock_lock(&lif->rx_filters.lock); 413 414 f = ionic_rx_filter_by_vlan(lif, vid); 415 if (!f) { 416 rte_spinlock_unlock(&lif->rx_filters.lock); 417 return -ENOENT; 418 } 419 420 ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id); 421 ionic_rx_filter_free(f); 422 rte_spinlock_unlock(&lif->rx_filters.lock); 423 424 err = ionic_adminq_post_wait(lif, &ctx); 425 if (err) 426 return err; 427 428 IONIC_PRINT(INFO, "rx_filter del VLAN %d (id %d)", vid, 429 rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id)); 430 431 return 0; 432 } 433 434 int 435 ionic_dev_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id, 436 int on) 437 { 438 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 439 int err; 440 441 if (on) 442 err = ionic_vlan_rx_add_vid(lif, vlan_id); 443 else 444 err = ionic_vlan_rx_kill_vid(lif, vlan_id); 445 446 return err; 447 } 448 449 static void 450 ionic_lif_rx_mode(struct ionic_lif *lif, uint32_t rx_mode) 451 { 452 struct ionic_admin_ctx ctx = { 453 .pending_work = true, 454 .cmd.rx_mode_set = { 455 .opcode = IONIC_CMD_RX_MODE_SET, 456 .rx_mode = rte_cpu_to_le_16(rx_mode), 457 }, 458 }; 459 int err; 460 461 if (rx_mode & IONIC_RX_MODE_F_UNICAST) 462 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_UNICAST"); 463 if (rx_mode & IONIC_RX_MODE_F_MULTICAST) 464 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_MULTICAST"); 465 if (rx_mode & IONIC_RX_MODE_F_BROADCAST) 466 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_BROADCAST"); 467 if (rx_mode & IONIC_RX_MODE_F_PROMISC) 468 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_PROMISC"); 469 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI) 470 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_ALLMULTI"); 471 472 err = ionic_adminq_post_wait(lif, &ctx); 473 if (err) 474 IONIC_PRINT(ERR, "Failure setting RX mode"); 475 } 476 477 static void 478 ionic_set_rx_mode(struct ionic_lif *lif, uint32_t rx_mode) 479 { 480 if (lif->rx_mode != rx_mode) { 481 lif->rx_mode = rx_mode; 482 ionic_lif_rx_mode(lif, rx_mode); 483 } 484 } 485 486 int 487 ionic_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 488 { 489 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 490 uint32_t rx_mode = lif->rx_mode; 491 492 IONIC_PRINT_CALL(); 493 494 rx_mode |= IONIC_RX_MODE_F_PROMISC; 495 496 ionic_set_rx_mode(lif, rx_mode); 497 498 return 0; 499 } 500 501 int 502 ionic_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 503 { 504 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 505 uint32_t rx_mode = lif->rx_mode; 506 507 rx_mode &= ~IONIC_RX_MODE_F_PROMISC; 508 509 ionic_set_rx_mode(lif, rx_mode); 510 511 return 0; 512 } 513 514 int 515 ionic_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 516 { 517 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 518 uint32_t rx_mode = lif->rx_mode; 519 520 rx_mode |= IONIC_RX_MODE_F_ALLMULTI; 521 522 ionic_set_rx_mode(lif, rx_mode); 523 524 return 0; 525 } 526 527 int 528 ionic_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 529 { 530 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 531 uint32_t rx_mode = lif->rx_mode; 532 533 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI; 534 535 ionic_set_rx_mode(lif, rx_mode); 536 537 return 0; 538 } 539 540 int 541 ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu) 542 { 543 struct ionic_admin_ctx ctx = { 544 .pending_work = true, 545 .cmd.lif_setattr = { 546 .opcode = IONIC_CMD_LIF_SETATTR, 547 .attr = IONIC_LIF_ATTR_MTU, 548 .mtu = rte_cpu_to_le_32(new_mtu), 549 }, 550 }; 551 int err; 552 553 err = ionic_adminq_post_wait(lif, &ctx); 554 if (err) 555 return err; 556 557 return 0; 558 } 559 560 int 561 ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) 562 { 563 struct ionic_adapter *adapter = lif->adapter; 564 struct ionic_dev *idev = &adapter->idev; 565 unsigned long index; 566 567 /* 568 * Note: interrupt handler is called for index = 0 only 569 * (we use interrupts for the notifyq only anyway, 570 * which has index = 0) 571 */ 572 573 for (index = 0; index < adapter->nintrs; index++) 574 if (!adapter->intrs[index]) 575 break; 576 577 if (index == adapter->nintrs) 578 return -ENOSPC; 579 580 adapter->intrs[index] = true; 581 582 ionic_intr_init(idev, intr, index); 583 584 return 0; 585 } 586 587 static int 588 ionic_qcq_alloc(struct ionic_lif *lif, 589 uint8_t type, 590 size_t struct_size, 591 uint32_t socket_id, 592 uint32_t index, 593 const char *type_name, 594 uint16_t flags, 595 uint16_t num_descs, 596 uint16_t desc_size, 597 uint16_t cq_desc_size, 598 uint16_t sg_desc_size, 599 struct ionic_qcq **qcq) 600 { 601 struct ionic_qcq *new; 602 uint32_t q_size, cq_size, sg_size, total_size; 603 void *q_base, *cq_base, *sg_base; 604 rte_iova_t q_base_pa = 0; 605 rte_iova_t cq_base_pa = 0; 606 rte_iova_t sg_base_pa = 0; 607 int err; 608 609 *qcq = NULL; 610 611 q_size = num_descs * desc_size; 612 cq_size = num_descs * cq_desc_size; 613 sg_size = num_descs * sg_desc_size; 614 615 total_size = RTE_ALIGN(q_size, PAGE_SIZE) + 616 RTE_ALIGN(cq_size, PAGE_SIZE); 617 /* 618 * Note: aligning q_size/cq_size is not enough due to cq_base address 619 * aligning as q_base could be not aligned to the page. 620 * Adding PAGE_SIZE. 621 */ 622 total_size += PAGE_SIZE; 623 624 if (flags & IONIC_QCQ_F_SG) { 625 total_size += RTE_ALIGN(sg_size, PAGE_SIZE); 626 total_size += PAGE_SIZE; 627 } 628 629 new = rte_zmalloc("ionic", struct_size, 0); 630 if (!new) { 631 IONIC_PRINT(ERR, "Cannot allocate queue structure"); 632 return -ENOMEM; 633 } 634 635 new->lif = lif; 636 637 new->q.info = rte_calloc_socket("ionic", 638 num_descs, sizeof(void *), 639 PAGE_SIZE, socket_id); 640 if (!new->q.info) { 641 IONIC_PRINT(ERR, "Cannot allocate queue info"); 642 err = -ENOMEM; 643 goto err_out_free_qcq; 644 } 645 646 new->q.type = type; 647 648 err = ionic_q_init(&new->q, index, num_descs); 649 if (err) { 650 IONIC_PRINT(ERR, "Queue initialization failed"); 651 goto err_out_free_info; 652 } 653 654 err = ionic_cq_init(&new->cq, num_descs); 655 if (err) { 656 IONIC_PRINT(ERR, "Completion queue initialization failed"); 657 goto err_out_free_info; 658 } 659 660 new->base_z = rte_eth_dma_zone_reserve(lif->eth_dev, 661 type_name, index /* queue_idx */, 662 total_size, IONIC_ALIGN, socket_id); 663 664 if (!new->base_z) { 665 IONIC_PRINT(ERR, "Cannot reserve queue DMA memory"); 666 err = -ENOMEM; 667 goto err_out_free_info; 668 } 669 670 new->base = new->base_z->addr; 671 new->base_pa = new->base_z->iova; 672 673 q_base = new->base; 674 q_base_pa = new->base_pa; 675 676 cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE); 677 cq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE); 678 679 if (flags & IONIC_QCQ_F_SG) { 680 sg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size, 681 PAGE_SIZE); 682 sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE); 683 ionic_q_sg_map(&new->q, sg_base, sg_base_pa); 684 } 685 686 IONIC_PRINT(DEBUG, "Q-Base-PA = %#jx CQ-Base-PA = %#jx " 687 "SG-base-PA = %#jx", 688 q_base_pa, cq_base_pa, sg_base_pa); 689 690 ionic_q_map(&new->q, q_base, q_base_pa); 691 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 692 693 *qcq = new; 694 695 return 0; 696 697 err_out_free_info: 698 rte_free(new->q.info); 699 err_out_free_qcq: 700 rte_free(new); 701 702 return err; 703 } 704 705 void 706 ionic_qcq_free(struct ionic_qcq *qcq) 707 { 708 if (qcq->base_z) { 709 qcq->base = NULL; 710 qcq->base_pa = 0; 711 rte_memzone_free(qcq->base_z); 712 qcq->base_z = NULL; 713 } 714 715 if (qcq->q.info) { 716 rte_free(qcq->q.info); 717 qcq->q.info = NULL; 718 } 719 720 rte_free(qcq); 721 } 722 723 int 724 ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, uint32_t index, 725 uint16_t nrxq_descs, struct ionic_rx_qcq **rxq_out) 726 { 727 struct ionic_rx_qcq *rxq; 728 uint16_t flags; 729 int err; 730 731 flags = IONIC_QCQ_F_SG; 732 err = ionic_qcq_alloc(lif, 733 IONIC_QTYPE_RXQ, 734 sizeof(struct ionic_rx_qcq), 735 socket_id, 736 index, 737 "rx", 738 flags, 739 nrxq_descs, 740 sizeof(struct ionic_rxq_desc), 741 sizeof(struct ionic_rxq_comp), 742 sizeof(struct ionic_rxq_sg_desc), 743 (struct ionic_qcq **)&rxq); 744 if (err) 745 return err; 746 747 rxq->flags = flags; 748 749 lif->rxqcqs[index] = rxq; 750 *rxq_out = rxq; 751 752 return 0; 753 } 754 755 int 756 ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, uint32_t index, 757 uint16_t ntxq_descs, struct ionic_tx_qcq **txq_out) 758 { 759 struct ionic_tx_qcq *txq; 760 uint16_t flags; 761 int err; 762 763 flags = IONIC_QCQ_F_SG; 764 err = ionic_qcq_alloc(lif, 765 IONIC_QTYPE_TXQ, 766 sizeof(struct ionic_tx_qcq), 767 socket_id, 768 index, 769 "tx", 770 flags, 771 ntxq_descs, 772 sizeof(struct ionic_txq_desc), 773 sizeof(struct ionic_txq_comp), 774 sizeof(struct ionic_txq_sg_desc_v1), 775 (struct ionic_qcq **)&txq); 776 if (err) 777 return err; 778 779 txq->flags = flags; 780 781 lif->txqcqs[index] = txq; 782 *txq_out = txq; 783 784 return 0; 785 } 786 787 static int 788 ionic_admin_qcq_alloc(struct ionic_lif *lif) 789 { 790 uint16_t flags = 0; 791 int err; 792 793 err = ionic_qcq_alloc(lif, 794 IONIC_QTYPE_ADMINQ, 795 sizeof(struct ionic_admin_qcq), 796 rte_socket_id(), 797 0, 798 "admin", 799 flags, 800 IONIC_ADMINQ_LENGTH, 801 sizeof(struct ionic_admin_cmd), 802 sizeof(struct ionic_admin_comp), 803 0, 804 (struct ionic_qcq **)&lif->adminqcq); 805 if (err) 806 return err; 807 808 return 0; 809 } 810 811 static int 812 ionic_notify_qcq_alloc(struct ionic_lif *lif) 813 { 814 struct ionic_notify_qcq *nqcq; 815 struct ionic_dev *idev = &lif->adapter->idev; 816 uint16_t flags = 0; 817 int err; 818 819 err = ionic_qcq_alloc(lif, 820 IONIC_QTYPE_NOTIFYQ, 821 sizeof(struct ionic_notify_qcq), 822 rte_socket_id(), 823 0, 824 "notify", 825 flags, 826 IONIC_NOTIFYQ_LENGTH, 827 sizeof(struct ionic_notifyq_cmd), 828 sizeof(union ionic_notifyq_comp), 829 0, 830 (struct ionic_qcq **)&nqcq); 831 if (err) 832 return err; 833 834 err = ionic_intr_alloc(lif, &nqcq->intr); 835 if (err) { 836 ionic_qcq_free(&nqcq->qcq); 837 return err; 838 } 839 840 ionic_intr_mask_assert(idev->intr_ctrl, nqcq->intr.index, 841 IONIC_INTR_MASK_SET); 842 843 lif->notifyqcq = nqcq; 844 845 return 0; 846 } 847 848 static void * 849 ionic_bus_map_dbpage(struct ionic_adapter *adapter, int page_num) 850 { 851 char *vaddr = adapter->bars[IONIC_PCI_BAR_DBELL].vaddr; 852 853 if (adapter->num_bars <= IONIC_PCI_BAR_DBELL) 854 return NULL; 855 856 return (void *)&vaddr[page_num << PAGE_SHIFT]; 857 } 858 859 static void 860 ionic_lif_queue_identify(struct ionic_lif *lif) 861 { 862 struct ionic_adapter *adapter = lif->adapter; 863 struct ionic_dev *idev = &adapter->idev; 864 union ionic_q_identity *q_ident = &adapter->ident.txq; 865 uint32_t q_words = RTE_DIM(q_ident->words); 866 uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data); 867 uint32_t i, nwords, qtype; 868 int err; 869 870 for (qtype = 0; qtype < RTE_DIM(ionic_qtype_vers); qtype++) { 871 struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; 872 873 /* Filter out the types this driver knows about */ 874 switch (qtype) { 875 case IONIC_QTYPE_ADMINQ: 876 case IONIC_QTYPE_NOTIFYQ: 877 case IONIC_QTYPE_RXQ: 878 case IONIC_QTYPE_TXQ: 879 break; 880 default: 881 continue; 882 } 883 884 memset(qti, 0, sizeof(*qti)); 885 886 ionic_dev_cmd_queue_identify(idev, IONIC_LIF_TYPE_CLASSIC, 887 qtype, ionic_qtype_vers[qtype]); 888 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 889 if (err == -EINVAL) { 890 IONIC_PRINT(ERR, "qtype %d not supported\n", qtype); 891 continue; 892 } else if (err == -EIO) { 893 IONIC_PRINT(ERR, "q_ident failed, older FW\n"); 894 return; 895 } else if (err) { 896 IONIC_PRINT(ERR, "q_ident failed, qtype %d: %d\n", 897 qtype, err); 898 return; 899 } 900 901 nwords = RTE_MIN(q_words, cmd_words); 902 for (i = 0; i < nwords; i++) 903 q_ident->words[i] = ioread32(&idev->dev_cmd->data[i]); 904 905 qti->version = q_ident->version; 906 qti->supported = q_ident->supported; 907 qti->features = rte_le_to_cpu_64(q_ident->features); 908 qti->desc_sz = rte_le_to_cpu_16(q_ident->desc_sz); 909 qti->comp_sz = rte_le_to_cpu_16(q_ident->comp_sz); 910 qti->sg_desc_sz = rte_le_to_cpu_16(q_ident->sg_desc_sz); 911 qti->max_sg_elems = rte_le_to_cpu_16(q_ident->max_sg_elems); 912 qti->sg_desc_stride = 913 rte_le_to_cpu_16(q_ident->sg_desc_stride); 914 915 IONIC_PRINT(DEBUG, " qtype[%d].version = %d", 916 qtype, qti->version); 917 IONIC_PRINT(DEBUG, " qtype[%d].supported = %#x", 918 qtype, qti->supported); 919 IONIC_PRINT(DEBUG, " qtype[%d].features = %#jx", 920 qtype, qti->features); 921 IONIC_PRINT(DEBUG, " qtype[%d].desc_sz = %d", 922 qtype, qti->desc_sz); 923 IONIC_PRINT(DEBUG, " qtype[%d].comp_sz = %d", 924 qtype, qti->comp_sz); 925 IONIC_PRINT(DEBUG, " qtype[%d].sg_desc_sz = %d", 926 qtype, qti->sg_desc_sz); 927 IONIC_PRINT(DEBUG, " qtype[%d].max_sg_elems = %d", 928 qtype, qti->max_sg_elems); 929 IONIC_PRINT(DEBUG, " qtype[%d].sg_desc_stride = %d", 930 qtype, qti->sg_desc_stride); 931 } 932 } 933 934 int 935 ionic_lif_alloc(struct ionic_lif *lif) 936 { 937 struct ionic_adapter *adapter = lif->adapter; 938 uint32_t socket_id = rte_socket_id(); 939 int err; 940 941 /* 942 * lif->name was zeroed on allocation. 943 * Copy (sizeof() - 1) bytes to ensure that it is NULL terminated. 944 */ 945 memcpy(lif->name, lif->eth_dev->data->name, sizeof(lif->name) - 1); 946 947 IONIC_PRINT(DEBUG, "LIF: %s", lif->name); 948 949 ionic_lif_queue_identify(lif); 950 951 if (lif->qtype_info[IONIC_QTYPE_TXQ].version < 1) { 952 IONIC_PRINT(ERR, "FW too old, please upgrade"); 953 return -ENXIO; 954 } 955 956 IONIC_PRINT(DEBUG, "Allocating Lif Info"); 957 958 rte_spinlock_init(&lif->adminq_lock); 959 rte_spinlock_init(&lif->adminq_service_lock); 960 961 lif->kern_dbpage = ionic_bus_map_dbpage(adapter, 0); 962 if (!lif->kern_dbpage) { 963 IONIC_PRINT(ERR, "Cannot map dbpage, aborting"); 964 return -ENOMEM; 965 } 966 967 lif->txqcqs = rte_zmalloc("ionic", sizeof(*lif->txqcqs) * 968 adapter->max_ntxqs_per_lif, 0); 969 970 if (!lif->txqcqs) { 971 IONIC_PRINT(ERR, "Cannot allocate tx queues array"); 972 return -ENOMEM; 973 } 974 975 lif->rxqcqs = rte_zmalloc("ionic", sizeof(*lif->rxqcqs) * 976 adapter->max_nrxqs_per_lif, 0); 977 978 if (!lif->rxqcqs) { 979 IONIC_PRINT(ERR, "Cannot allocate rx queues array"); 980 return -ENOMEM; 981 } 982 983 IONIC_PRINT(DEBUG, "Allocating Notify Queue"); 984 985 err = ionic_notify_qcq_alloc(lif); 986 if (err) { 987 IONIC_PRINT(ERR, "Cannot allocate notify queue"); 988 return err; 989 } 990 991 IONIC_PRINT(DEBUG, "Allocating Admin Queue"); 992 993 err = ionic_admin_qcq_alloc(lif); 994 if (err) { 995 IONIC_PRINT(ERR, "Cannot allocate admin queue"); 996 return err; 997 } 998 999 IONIC_PRINT(DEBUG, "Allocating Lif Info"); 1000 1001 lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE); 1002 1003 lif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev, 1004 "lif_info", 0 /* queue_idx*/, 1005 lif->info_sz, IONIC_ALIGN, socket_id); 1006 if (!lif->info_z) { 1007 IONIC_PRINT(ERR, "Cannot allocate lif info memory"); 1008 return -ENOMEM; 1009 } 1010 1011 lif->info = lif->info_z->addr; 1012 lif->info_pa = lif->info_z->iova; 1013 1014 return 0; 1015 } 1016 1017 void 1018 ionic_lif_free(struct ionic_lif *lif) 1019 { 1020 if (lif->notifyqcq) { 1021 ionic_qcq_free(&lif->notifyqcq->qcq); 1022 lif->notifyqcq = NULL; 1023 } 1024 1025 if (lif->adminqcq) { 1026 ionic_qcq_free(&lif->adminqcq->qcq); 1027 lif->adminqcq = NULL; 1028 } 1029 1030 if (lif->txqcqs) { 1031 rte_free(lif->txqcqs); 1032 lif->txqcqs = NULL; 1033 } 1034 1035 if (lif->rxqcqs) { 1036 rte_free(lif->rxqcqs); 1037 lif->rxqcqs = NULL; 1038 } 1039 1040 if (lif->info) { 1041 rte_memzone_free(lif->info_z); 1042 lif->info = NULL; 1043 } 1044 } 1045 1046 void 1047 ionic_lif_free_queues(struct ionic_lif *lif) 1048 { 1049 uint32_t i; 1050 1051 for (i = 0; i < lif->ntxqcqs; i++) { 1052 ionic_dev_tx_queue_release(lif->eth_dev->data->tx_queues[i]); 1053 lif->eth_dev->data->tx_queues[i] = NULL; 1054 } 1055 for (i = 0; i < lif->nrxqcqs; i++) { 1056 ionic_dev_rx_queue_release(lif->eth_dev->data->rx_queues[i]); 1057 lif->eth_dev->data->rx_queues[i] = NULL; 1058 } 1059 } 1060 1061 int 1062 ionic_lif_rss_config(struct ionic_lif *lif, 1063 const uint16_t types, const uint8_t *key, const uint32_t *indir) 1064 { 1065 struct ionic_adapter *adapter = lif->adapter; 1066 struct ionic_admin_ctx ctx = { 1067 .pending_work = true, 1068 .cmd.lif_setattr = { 1069 .opcode = IONIC_CMD_LIF_SETATTR, 1070 .attr = IONIC_LIF_ATTR_RSS, 1071 .rss.types = rte_cpu_to_le_16(types), 1072 .rss.addr = rte_cpu_to_le_64(lif->rss_ind_tbl_pa), 1073 }, 1074 }; 1075 unsigned int i; 1076 uint16_t tbl_sz = 1077 rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz); 1078 1079 IONIC_PRINT_CALL(); 1080 1081 lif->rss_types = types; 1082 1083 if (key) 1084 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); 1085 1086 if (indir) 1087 for (i = 0; i < tbl_sz; i++) 1088 lif->rss_ind_tbl[i] = indir[i]; 1089 1090 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, 1091 IONIC_RSS_HASH_KEY_SIZE); 1092 1093 return ionic_adminq_post_wait(lif, &ctx); 1094 } 1095 1096 static int 1097 ionic_lif_rss_setup(struct ionic_lif *lif) 1098 { 1099 struct ionic_adapter *adapter = lif->adapter; 1100 static const uint8_t toeplitz_symmetric_key[] = { 1101 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 1102 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 1103 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 1104 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 1105 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 1106 }; 1107 uint32_t i; 1108 uint16_t tbl_sz = 1109 rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz); 1110 1111 IONIC_PRINT_CALL(); 1112 1113 if (!lif->rss_ind_tbl_z) { 1114 lif->rss_ind_tbl_z = rte_eth_dma_zone_reserve(lif->eth_dev, 1115 "rss_ind_tbl", 0 /* queue_idx */, 1116 sizeof(*lif->rss_ind_tbl) * tbl_sz, 1117 IONIC_ALIGN, rte_socket_id()); 1118 if (!lif->rss_ind_tbl_z) { 1119 IONIC_PRINT(ERR, "OOM"); 1120 return -ENOMEM; 1121 } 1122 1123 lif->rss_ind_tbl = lif->rss_ind_tbl_z->addr; 1124 lif->rss_ind_tbl_pa = lif->rss_ind_tbl_z->iova; 1125 } 1126 1127 if (lif->rss_ind_tbl_nrxqcqs != lif->nrxqcqs) { 1128 lif->rss_ind_tbl_nrxqcqs = lif->nrxqcqs; 1129 1130 /* Fill indirection table with 'default' values */ 1131 for (i = 0; i < tbl_sz; i++) 1132 lif->rss_ind_tbl[i] = i % lif->nrxqcqs; 1133 } 1134 1135 return ionic_lif_rss_config(lif, IONIC_RSS_OFFLOAD_ALL, 1136 toeplitz_symmetric_key, NULL); 1137 } 1138 1139 static void 1140 ionic_lif_rss_teardown(struct ionic_lif *lif) 1141 { 1142 if (!lif->rss_ind_tbl) 1143 return; 1144 1145 if (lif->rss_ind_tbl_z) { 1146 /* Disable RSS on the NIC */ 1147 ionic_lif_rss_config(lif, 0x0, NULL, NULL); 1148 1149 lif->rss_ind_tbl = NULL; 1150 lif->rss_ind_tbl_pa = 0; 1151 rte_memzone_free(lif->rss_ind_tbl_z); 1152 lif->rss_ind_tbl_z = NULL; 1153 } 1154 } 1155 1156 void 1157 ionic_lif_txq_deinit(struct ionic_tx_qcq *txq) 1158 { 1159 txq->flags &= ~IONIC_QCQ_F_INITED; 1160 } 1161 1162 void 1163 ionic_lif_rxq_deinit(struct ionic_rx_qcq *rxq) 1164 { 1165 rxq->flags &= ~IONIC_QCQ_F_INITED; 1166 } 1167 1168 static void 1169 ionic_lif_adminq_deinit(struct ionic_lif *lif) 1170 { 1171 lif->adminqcq->flags &= ~IONIC_QCQ_F_INITED; 1172 } 1173 1174 static void 1175 ionic_lif_notifyq_deinit(struct ionic_lif *lif) 1176 { 1177 struct ionic_notify_qcq *nqcq = lif->notifyqcq; 1178 struct ionic_dev *idev = &lif->adapter->idev; 1179 1180 if (!(nqcq->flags & IONIC_QCQ_F_INITED)) 1181 return; 1182 1183 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index, 1184 IONIC_INTR_MASK_SET); 1185 1186 nqcq->flags &= ~IONIC_QCQ_F_INITED; 1187 } 1188 1189 /* This acts like ionic_napi */ 1190 int 1191 ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb, 1192 void *cb_arg) 1193 { 1194 struct ionic_cq *cq = &qcq->cq; 1195 uint32_t work_done; 1196 1197 work_done = ionic_cq_service(cq, budget, cb, cb_arg); 1198 1199 return work_done; 1200 } 1201 1202 static void 1203 ionic_link_status_check(struct ionic_lif *lif) 1204 { 1205 struct ionic_adapter *adapter = lif->adapter; 1206 bool link_up; 1207 1208 lif->state &= ~IONIC_LIF_F_LINK_CHECK_NEEDED; 1209 1210 if (!lif->info) 1211 return; 1212 1213 link_up = (lif->info->status.link_status == IONIC_PORT_OPER_STATUS_UP); 1214 1215 if ((link_up && adapter->link_up) || 1216 (!link_up && !adapter->link_up)) 1217 return; 1218 1219 if (link_up) { 1220 adapter->link_speed = 1221 rte_le_to_cpu_32(lif->info->status.link_speed); 1222 IONIC_PRINT(DEBUG, "Link up - %d Gbps", 1223 adapter->link_speed); 1224 } else { 1225 IONIC_PRINT(DEBUG, "Link down"); 1226 } 1227 1228 adapter->link_up = link_up; 1229 ionic_dev_link_update(lif->eth_dev, 0); 1230 } 1231 1232 static void 1233 ionic_lif_handle_fw_down(struct ionic_lif *lif) 1234 { 1235 if (lif->state & IONIC_LIF_F_FW_RESET) 1236 return; 1237 1238 lif->state |= IONIC_LIF_F_FW_RESET; 1239 1240 if (lif->state & IONIC_LIF_F_UP) { 1241 IONIC_PRINT(NOTICE, 1242 "Surprise FW stop, stopping %s\n", lif->name); 1243 ionic_lif_stop(lif); 1244 } 1245 1246 IONIC_PRINT(NOTICE, "FW down, %s stopped", lif->name); 1247 } 1248 1249 static bool 1250 ionic_notifyq_cb(struct ionic_cq *cq, uint16_t cq_desc_index, void *cb_arg) 1251 { 1252 union ionic_notifyq_comp *cq_desc_base = cq->base; 1253 union ionic_notifyq_comp *cq_desc = &cq_desc_base[cq_desc_index]; 1254 struct ionic_lif *lif = cb_arg; 1255 1256 IONIC_PRINT(DEBUG, "Notifyq callback eid = %jd ecode = %d", 1257 cq_desc->event.eid, cq_desc->event.ecode); 1258 1259 /* Have we run out of new completions to process? */ 1260 if (!(cq_desc->event.eid > lif->last_eid)) 1261 return false; 1262 1263 lif->last_eid = cq_desc->event.eid; 1264 1265 switch (cq_desc->event.ecode) { 1266 case IONIC_EVENT_LINK_CHANGE: 1267 IONIC_PRINT(DEBUG, 1268 "Notifyq IONIC_EVENT_LINK_CHANGE %s " 1269 "eid=%jd link_status=%d link_speed=%d", 1270 lif->name, 1271 cq_desc->event.eid, 1272 cq_desc->link_change.link_status, 1273 cq_desc->link_change.link_speed); 1274 1275 lif->state |= IONIC_LIF_F_LINK_CHECK_NEEDED; 1276 break; 1277 1278 case IONIC_EVENT_RESET: 1279 IONIC_PRINT(NOTICE, 1280 "Notifyq IONIC_EVENT_RESET %s " 1281 "eid=%jd, reset_code=%d state=%d", 1282 lif->name, 1283 cq_desc->event.eid, 1284 cq_desc->reset.reset_code, 1285 cq_desc->reset.state); 1286 ionic_lif_handle_fw_down(lif); 1287 break; 1288 1289 default: 1290 IONIC_PRINT(WARNING, "Notifyq bad event ecode=%d eid=%jd", 1291 cq_desc->event.ecode, cq_desc->event.eid); 1292 break; 1293 } 1294 1295 return true; 1296 } 1297 1298 int 1299 ionic_notifyq_handler(struct ionic_lif *lif, int budget) 1300 { 1301 struct ionic_dev *idev = &lif->adapter->idev; 1302 struct ionic_notify_qcq *nqcq = lif->notifyqcq; 1303 uint32_t work_done; 1304 1305 if (!(nqcq->flags & IONIC_QCQ_F_INITED)) { 1306 IONIC_PRINT(DEBUG, "Notifyq not yet initialized"); 1307 return -1; 1308 } 1309 1310 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index, 1311 IONIC_INTR_MASK_SET); 1312 1313 work_done = ionic_qcq_service(&nqcq->qcq, budget, 1314 ionic_notifyq_cb, lif); 1315 1316 if (lif->state & IONIC_LIF_F_LINK_CHECK_NEEDED) 1317 ionic_link_status_check(lif); 1318 1319 ionic_intr_credits(idev->intr_ctrl, nqcq->intr.index, 1320 work_done, IONIC_INTR_CRED_RESET_COALESCE); 1321 1322 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index, 1323 IONIC_INTR_MASK_CLEAR); 1324 1325 return 0; 1326 } 1327 1328 static int 1329 ionic_lif_adminq_init(struct ionic_lif *lif) 1330 { 1331 struct ionic_dev *idev = &lif->adapter->idev; 1332 struct ionic_admin_qcq *aqcq = lif->adminqcq; 1333 struct ionic_queue *q = &aqcq->qcq.q; 1334 struct ionic_q_init_comp comp; 1335 int err; 1336 1337 ionic_dev_cmd_adminq_init(idev, &aqcq->qcq); 1338 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 1339 if (err) 1340 return err; 1341 1342 ionic_dev_cmd_comp(idev, &comp); 1343 1344 q->hw_type = comp.hw_type; 1345 q->hw_index = rte_le_to_cpu_32(comp.hw_index); 1346 q->db = ionic_db_map(lif, q); 1347 1348 IONIC_PRINT(DEBUG, "adminq->hw_type %d", q->hw_type); 1349 IONIC_PRINT(DEBUG, "adminq->hw_index %d", q->hw_index); 1350 IONIC_PRINT(DEBUG, "adminq->db %p", q->db); 1351 1352 aqcq->flags |= IONIC_QCQ_F_INITED; 1353 1354 return 0; 1355 } 1356 1357 static int 1358 ionic_lif_notifyq_init(struct ionic_lif *lif) 1359 { 1360 struct ionic_dev *idev = &lif->adapter->idev; 1361 struct ionic_notify_qcq *nqcq = lif->notifyqcq; 1362 struct ionic_queue *q = &nqcq->qcq.q; 1363 int err; 1364 1365 struct ionic_admin_ctx ctx = { 1366 .pending_work = true, 1367 .cmd.q_init = { 1368 .opcode = IONIC_CMD_Q_INIT, 1369 .type = q->type, 1370 .ver = lif->qtype_info[q->type].version, 1371 .index = rte_cpu_to_le_32(q->index), 1372 .intr_index = rte_cpu_to_le_16(nqcq->intr.index), 1373 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_IRQ | 1374 IONIC_QINIT_F_ENA), 1375 .ring_size = rte_log2_u32(q->num_descs), 1376 .ring_base = rte_cpu_to_le_64(q->base_pa), 1377 } 1378 }; 1379 1380 IONIC_PRINT(DEBUG, "notifyq_init.index %d", q->index); 1381 IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "", q->base_pa); 1382 IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d", 1383 ctx.cmd.q_init.ring_size); 1384 IONIC_PRINT(DEBUG, "notifyq_init.ver %u", ctx.cmd.q_init.ver); 1385 1386 err = ionic_adminq_post_wait(lif, &ctx); 1387 if (err) 1388 return err; 1389 1390 q->hw_type = ctx.comp.q_init.hw_type; 1391 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index); 1392 q->db = NULL; 1393 1394 IONIC_PRINT(DEBUG, "notifyq->hw_type %d", q->hw_type); 1395 IONIC_PRINT(DEBUG, "notifyq->hw_index %d", q->hw_index); 1396 IONIC_PRINT(DEBUG, "notifyq->db %p", q->db); 1397 1398 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index, 1399 IONIC_INTR_MASK_CLEAR); 1400 1401 nqcq->flags |= IONIC_QCQ_F_INITED; 1402 1403 return 0; 1404 } 1405 1406 int 1407 ionic_lif_set_features(struct ionic_lif *lif) 1408 { 1409 struct ionic_admin_ctx ctx = { 1410 .pending_work = true, 1411 .cmd.lif_setattr = { 1412 .opcode = IONIC_CMD_LIF_SETATTR, 1413 .attr = IONIC_LIF_ATTR_FEATURES, 1414 .features = rte_cpu_to_le_64(lif->features), 1415 }, 1416 }; 1417 int err; 1418 1419 err = ionic_adminq_post_wait(lif, &ctx); 1420 if (err) 1421 return err; 1422 1423 lif->hw_features = rte_le_to_cpu_64(ctx.cmd.lif_setattr.features & 1424 ctx.comp.lif_setattr.features); 1425 1426 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1427 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_TX_TAG"); 1428 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1429 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_STRIP"); 1430 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1431 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_FILTER"); 1432 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1433 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_HASH"); 1434 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1435 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_SG"); 1436 if (lif->hw_features & IONIC_ETH_HW_RX_SG) 1437 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_SG"); 1438 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1439 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_CSUM"); 1440 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1441 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_CSUM"); 1442 if (lif->hw_features & IONIC_ETH_HW_TSO) 1443 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO"); 1444 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1445 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPV6"); 1446 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1447 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_ECN"); 1448 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1449 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE"); 1450 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1451 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE_CSUM"); 1452 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1453 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP4"); 1454 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1455 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP6"); 1456 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1457 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP"); 1458 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1459 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP_CSUM"); 1460 1461 return 0; 1462 } 1463 1464 int 1465 ionic_lif_txq_init(struct ionic_tx_qcq *txq) 1466 { 1467 struct ionic_qcq *qcq = &txq->qcq; 1468 struct ionic_queue *q = &qcq->q; 1469 struct ionic_lif *lif = qcq->lif; 1470 struct ionic_cq *cq = &qcq->cq; 1471 struct ionic_admin_ctx ctx = { 1472 .pending_work = true, 1473 .cmd.q_init = { 1474 .opcode = IONIC_CMD_Q_INIT, 1475 .type = q->type, 1476 .ver = lif->qtype_info[q->type].version, 1477 .index = rte_cpu_to_le_32(q->index), 1478 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG | 1479 IONIC_QINIT_F_ENA), 1480 .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE), 1481 .ring_size = rte_log2_u32(q->num_descs), 1482 .ring_base = rte_cpu_to_le_64(q->base_pa), 1483 .cq_ring_base = rte_cpu_to_le_64(cq->base_pa), 1484 .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa), 1485 }, 1486 }; 1487 int err; 1488 1489 IONIC_PRINT(DEBUG, "txq_init.index %d", q->index); 1490 IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "", q->base_pa); 1491 IONIC_PRINT(DEBUG, "txq_init.ring_size %d", 1492 ctx.cmd.q_init.ring_size); 1493 IONIC_PRINT(DEBUG, "txq_init.ver %u", ctx.cmd.q_init.ver); 1494 1495 err = ionic_adminq_post_wait(lif, &ctx); 1496 if (err) 1497 return err; 1498 1499 q->hw_type = ctx.comp.q_init.hw_type; 1500 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index); 1501 q->db = ionic_db_map(lif, q); 1502 1503 IONIC_PRINT(DEBUG, "txq->hw_type %d", q->hw_type); 1504 IONIC_PRINT(DEBUG, "txq->hw_index %d", q->hw_index); 1505 IONIC_PRINT(DEBUG, "txq->db %p", q->db); 1506 1507 txq->flags |= IONIC_QCQ_F_INITED; 1508 1509 return 0; 1510 } 1511 1512 int 1513 ionic_lif_rxq_init(struct ionic_rx_qcq *rxq) 1514 { 1515 struct ionic_qcq *qcq = &rxq->qcq; 1516 struct ionic_queue *q = &qcq->q; 1517 struct ionic_lif *lif = qcq->lif; 1518 struct ionic_cq *cq = &qcq->cq; 1519 struct ionic_admin_ctx ctx = { 1520 .pending_work = true, 1521 .cmd.q_init = { 1522 .opcode = IONIC_CMD_Q_INIT, 1523 .type = q->type, 1524 .ver = lif->qtype_info[q->type].version, 1525 .index = rte_cpu_to_le_32(q->index), 1526 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG | 1527 IONIC_QINIT_F_ENA), 1528 .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE), 1529 .ring_size = rte_log2_u32(q->num_descs), 1530 .ring_base = rte_cpu_to_le_64(q->base_pa), 1531 .cq_ring_base = rte_cpu_to_le_64(cq->base_pa), 1532 .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa), 1533 }, 1534 }; 1535 int err; 1536 1537 IONIC_PRINT(DEBUG, "rxq_init.index %d", q->index); 1538 IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "", q->base_pa); 1539 IONIC_PRINT(DEBUG, "rxq_init.ring_size %d", 1540 ctx.cmd.q_init.ring_size); 1541 IONIC_PRINT(DEBUG, "rxq_init.ver %u", ctx.cmd.q_init.ver); 1542 1543 err = ionic_adminq_post_wait(lif, &ctx); 1544 if (err) 1545 return err; 1546 1547 q->hw_type = ctx.comp.q_init.hw_type; 1548 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index); 1549 q->db = ionic_db_map(lif, q); 1550 1551 rxq->flags |= IONIC_QCQ_F_INITED; 1552 1553 IONIC_PRINT(DEBUG, "rxq->hw_type %d", q->hw_type); 1554 IONIC_PRINT(DEBUG, "rxq->hw_index %d", q->hw_index); 1555 IONIC_PRINT(DEBUG, "rxq->db %p", q->db); 1556 1557 return 0; 1558 } 1559 1560 static int 1561 ionic_station_set(struct ionic_lif *lif) 1562 { 1563 struct ionic_admin_ctx ctx = { 1564 .pending_work = true, 1565 .cmd.lif_getattr = { 1566 .opcode = IONIC_CMD_LIF_GETATTR, 1567 .attr = IONIC_LIF_ATTR_MAC, 1568 }, 1569 }; 1570 int err; 1571 1572 IONIC_PRINT_CALL(); 1573 1574 err = ionic_adminq_post_wait(lif, &ctx); 1575 if (err) 1576 return err; 1577 1578 memcpy(lif->mac_addr, ctx.comp.lif_getattr.mac, RTE_ETHER_ADDR_LEN); 1579 1580 return 0; 1581 } 1582 1583 static void 1584 ionic_lif_set_name(struct ionic_lif *lif) 1585 { 1586 struct ionic_admin_ctx ctx = { 1587 .pending_work = true, 1588 .cmd.lif_setattr = { 1589 .opcode = IONIC_CMD_LIF_SETATTR, 1590 .attr = IONIC_LIF_ATTR_NAME, 1591 }, 1592 }; 1593 1594 memcpy(ctx.cmd.lif_setattr.name, lif->name, 1595 sizeof(ctx.cmd.lif_setattr.name) - 1); 1596 1597 ionic_adminq_post_wait(lif, &ctx); 1598 } 1599 1600 int 1601 ionic_lif_init(struct ionic_lif *lif) 1602 { 1603 struct ionic_dev *idev = &lif->adapter->idev; 1604 struct ionic_q_init_comp comp; 1605 int err; 1606 1607 memset(&lif->stats_base, 0, sizeof(lif->stats_base)); 1608 1609 ionic_dev_cmd_lif_init(idev, lif->info_pa); 1610 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 1611 ionic_dev_cmd_comp(idev, &comp); 1612 if (err) 1613 return err; 1614 1615 lif->hw_index = rte_cpu_to_le_16(comp.hw_index); 1616 1617 err = ionic_lif_adminq_init(lif); 1618 if (err) 1619 return err; 1620 1621 err = ionic_lif_notifyq_init(lif); 1622 if (err) 1623 goto err_out_adminq_deinit; 1624 1625 /* 1626 * Configure initial feature set 1627 * This will be updated later by the dev_configure() step 1628 */ 1629 lif->features = IONIC_ETH_HW_RX_HASH | IONIC_ETH_HW_VLAN_RX_FILTER; 1630 1631 err = ionic_lif_set_features(lif); 1632 if (err) 1633 goto err_out_notifyq_deinit; 1634 1635 err = ionic_rx_filters_init(lif); 1636 if (err) 1637 goto err_out_notifyq_deinit; 1638 1639 err = ionic_station_set(lif); 1640 if (err) 1641 goto err_out_rx_filter_deinit; 1642 1643 ionic_lif_set_name(lif); 1644 1645 lif->state |= IONIC_LIF_F_INITED; 1646 1647 return 0; 1648 1649 err_out_rx_filter_deinit: 1650 ionic_rx_filters_deinit(lif); 1651 1652 err_out_notifyq_deinit: 1653 ionic_lif_notifyq_deinit(lif); 1654 1655 err_out_adminq_deinit: 1656 ionic_lif_adminq_deinit(lif); 1657 1658 return err; 1659 } 1660 1661 void 1662 ionic_lif_deinit(struct ionic_lif *lif) 1663 { 1664 if (!(lif->state & IONIC_LIF_F_INITED)) 1665 return; 1666 1667 ionic_rx_filters_deinit(lif); 1668 ionic_lif_rss_teardown(lif); 1669 ionic_lif_notifyq_deinit(lif); 1670 ionic_lif_adminq_deinit(lif); 1671 1672 lif->state &= ~IONIC_LIF_F_INITED; 1673 } 1674 1675 void 1676 ionic_lif_configure_vlan_offload(struct ionic_lif *lif, int mask) 1677 { 1678 struct rte_eth_dev *eth_dev = lif->eth_dev; 1679 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 1680 1681 /* 1682 * IONIC_ETH_HW_VLAN_RX_FILTER cannot be turned off, so 1683 * set DEV_RX_OFFLOAD_VLAN_FILTER and ignore ETH_VLAN_FILTER_MASK 1684 */ 1685 rxmode->offloads |= DEV_RX_OFFLOAD_VLAN_FILTER; 1686 1687 if (mask & ETH_VLAN_STRIP_MASK) { 1688 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1689 lif->features |= IONIC_ETH_HW_VLAN_RX_STRIP; 1690 else 1691 lif->features &= ~IONIC_ETH_HW_VLAN_RX_STRIP; 1692 } 1693 } 1694 1695 void 1696 ionic_lif_configure(struct ionic_lif *lif) 1697 { 1698 struct rte_eth_rxmode *rxmode = &lif->eth_dev->data->dev_conf.rxmode; 1699 struct rte_eth_txmode *txmode = &lif->eth_dev->data->dev_conf.txmode; 1700 struct ionic_identity *ident = &lif->adapter->ident; 1701 union ionic_lif_config *cfg = &ident->lif.eth.config; 1702 uint32_t ntxqs_per_lif = 1703 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); 1704 uint32_t nrxqs_per_lif = 1705 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); 1706 uint32_t nrxqs = lif->eth_dev->data->nb_rx_queues; 1707 uint32_t ntxqs = lif->eth_dev->data->nb_tx_queues; 1708 1709 lif->port_id = lif->eth_dev->data->port_id; 1710 1711 IONIC_PRINT(DEBUG, "Configuring LIF on port %u", 1712 lif->port_id); 1713 1714 if (nrxqs > 0) 1715 nrxqs_per_lif = RTE_MIN(nrxqs_per_lif, nrxqs); 1716 1717 if (ntxqs > 0) 1718 ntxqs_per_lif = RTE_MIN(ntxqs_per_lif, ntxqs); 1719 1720 lif->nrxqcqs = nrxqs_per_lif; 1721 lif->ntxqcqs = ntxqs_per_lif; 1722 1723 /* Update the LIF configuration based on the eth_dev */ 1724 1725 /* 1726 * NB: While it is true that RSS_HASH is always enabled on ionic, 1727 * setting this flag unconditionally causes problems in DTS. 1728 * rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1729 */ 1730 1731 /* RX per-port */ 1732 1733 if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM || 1734 rxmode->offloads & DEV_RX_OFFLOAD_UDP_CKSUM || 1735 rxmode->offloads & DEV_RX_OFFLOAD_TCP_CKSUM) 1736 lif->features |= IONIC_ETH_HW_RX_CSUM; 1737 else 1738 lif->features &= ~IONIC_ETH_HW_RX_CSUM; 1739 1740 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) { 1741 lif->features |= IONIC_ETH_HW_RX_SG; 1742 lif->eth_dev->data->scattered_rx = 1; 1743 } else { 1744 lif->features &= ~IONIC_ETH_HW_RX_SG; 1745 lif->eth_dev->data->scattered_rx = 0; 1746 } 1747 1748 /* Covers VLAN_STRIP */ 1749 ionic_lif_configure_vlan_offload(lif, ETH_VLAN_STRIP_MASK); 1750 1751 /* TX per-port */ 1752 1753 if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM || 1754 txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM || 1755 txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM || 1756 txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM || 1757 txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM) 1758 lif->features |= IONIC_ETH_HW_TX_CSUM; 1759 else 1760 lif->features &= ~IONIC_ETH_HW_TX_CSUM; 1761 1762 if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT) 1763 lif->features |= IONIC_ETH_HW_VLAN_TX_TAG; 1764 else 1765 lif->features &= ~IONIC_ETH_HW_VLAN_TX_TAG; 1766 1767 if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS) 1768 lif->features |= IONIC_ETH_HW_TX_SG; 1769 else 1770 lif->features &= ~IONIC_ETH_HW_TX_SG; 1771 1772 if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) { 1773 lif->features |= IONIC_ETH_HW_TSO; 1774 lif->features |= IONIC_ETH_HW_TSO_IPV6; 1775 lif->features |= IONIC_ETH_HW_TSO_ECN; 1776 } else { 1777 lif->features &= ~IONIC_ETH_HW_TSO; 1778 lif->features &= ~IONIC_ETH_HW_TSO_IPV6; 1779 lif->features &= ~IONIC_ETH_HW_TSO_ECN; 1780 } 1781 } 1782 1783 int 1784 ionic_lif_start(struct ionic_lif *lif) 1785 { 1786 uint32_t rx_mode; 1787 uint32_t i; 1788 int err; 1789 1790 err = ionic_lif_rss_setup(lif); 1791 if (err) 1792 return err; 1793 1794 if (!lif->rx_mode) { 1795 IONIC_PRINT(DEBUG, "Setting RX mode on %s", 1796 lif->name); 1797 1798 rx_mode = IONIC_RX_MODE_F_UNICAST; 1799 rx_mode |= IONIC_RX_MODE_F_MULTICAST; 1800 rx_mode |= IONIC_RX_MODE_F_BROADCAST; 1801 1802 ionic_set_rx_mode(lif, rx_mode); 1803 } 1804 1805 IONIC_PRINT(DEBUG, "Starting %u RX queues and %u TX queues " 1806 "on port %u", 1807 lif->nrxqcqs, lif->ntxqcqs, lif->port_id); 1808 1809 for (i = 0; i < lif->nrxqcqs; i++) { 1810 struct ionic_rx_qcq *rxq = lif->rxqcqs[i]; 1811 if (!(rxq->flags & IONIC_QCQ_F_DEFERRED)) { 1812 err = ionic_dev_rx_queue_start(lif->eth_dev, i); 1813 1814 if (err) 1815 return err; 1816 } 1817 } 1818 1819 for (i = 0; i < lif->ntxqcqs; i++) { 1820 struct ionic_tx_qcq *txq = lif->txqcqs[i]; 1821 if (!(txq->flags & IONIC_QCQ_F_DEFERRED)) { 1822 err = ionic_dev_tx_queue_start(lif->eth_dev, i); 1823 1824 if (err) 1825 return err; 1826 } 1827 } 1828 1829 /* Carrier ON here */ 1830 lif->state |= IONIC_LIF_F_UP; 1831 1832 ionic_link_status_check(lif); 1833 1834 return 0; 1835 } 1836 1837 int 1838 ionic_lif_identify(struct ionic_adapter *adapter) 1839 { 1840 struct ionic_dev *idev = &adapter->idev; 1841 struct ionic_identity *ident = &adapter->ident; 1842 union ionic_lif_config *cfg = &ident->lif.eth.config; 1843 uint32_t lif_words = RTE_DIM(ident->lif.words); 1844 uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data); 1845 uint32_t i, nwords; 1846 int err; 1847 1848 ionic_dev_cmd_lif_identify(idev, IONIC_LIF_TYPE_CLASSIC, 1849 IONIC_IDENTITY_VERSION_1); 1850 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 1851 if (err) 1852 return (err); 1853 1854 nwords = RTE_MIN(lif_words, cmd_words); 1855 for (i = 0; i < nwords; i++) 1856 ident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]); 1857 1858 IONIC_PRINT(INFO, "capabilities 0x%" PRIx64 " ", 1859 rte_le_to_cpu_64(ident->lif.capabilities)); 1860 1861 IONIC_PRINT(INFO, "eth.max_ucast_filters 0x%" PRIx32 " ", 1862 rte_le_to_cpu_32(ident->lif.eth.max_ucast_filters)); 1863 IONIC_PRINT(INFO, "eth.max_mcast_filters 0x%" PRIx32 " ", 1864 rte_le_to_cpu_32(ident->lif.eth.max_mcast_filters)); 1865 1866 IONIC_PRINT(INFO, "eth.features 0x%" PRIx64 " ", 1867 rte_le_to_cpu_64(cfg->features)); 1868 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%" PRIx32 " ", 1869 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_ADMINQ])); 1870 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%" PRIx32 " ", 1871 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_NOTIFYQ])); 1872 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_RXQ] 0x%" PRIx32 " ", 1873 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ])); 1874 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_TXQ] 0x%" PRIx32 " ", 1875 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ])); 1876 1877 return 0; 1878 } 1879 1880 int 1881 ionic_lifs_size(struct ionic_adapter *adapter) 1882 { 1883 struct ionic_identity *ident = &adapter->ident; 1884 union ionic_lif_config *cfg = &ident->lif.eth.config; 1885 uint32_t nintrs, dev_nintrs = rte_le_to_cpu_32(ident->dev.nintrs); 1886 1887 adapter->max_ntxqs_per_lif = 1888 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); 1889 adapter->max_nrxqs_per_lif = 1890 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); 1891 1892 nintrs = 1 /* notifyq */; 1893 1894 if (nintrs > dev_nintrs) { 1895 IONIC_PRINT(ERR, 1896 "At most %d intr supported, minimum req'd is %u", 1897 dev_nintrs, nintrs); 1898 return -ENOSPC; 1899 } 1900 1901 adapter->nintrs = nintrs; 1902 1903 return 0; 1904 } 1905