1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved. 3 */ 4 5 #include <rte_malloc.h> 6 #include <ethdev_driver.h> 7 8 #include "ionic.h" 9 #include "ionic_logs.h" 10 #include "ionic_lif.h" 11 #include "ionic_ethdev.h" 12 #include "ionic_rx_filter.h" 13 #include "ionic_rxtx.h" 14 15 /* queuetype support level */ 16 static const uint8_t ionic_qtype_vers[IONIC_QTYPE_MAX] = { 17 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ 18 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ 19 [IONIC_QTYPE_RXQ] = 2, /* 0 = Base version with CQ+SG support 20 * 1 = ... with EQ 21 * 2 = ... with CMB 22 */ 23 [IONIC_QTYPE_TXQ] = 3, /* 0 = Base version with CQ+SG support 24 * 1 = ... with Tx SG version 1 25 * 2 = ... with EQ 26 * 3 = ... with CMB 27 */ 28 }; 29 30 static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr); 31 static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr); 32 33 int 34 ionic_qcq_enable(struct ionic_qcq *qcq) 35 { 36 struct ionic_queue *q = &qcq->q; 37 struct ionic_lif *lif = qcq->lif; 38 struct ionic_admin_ctx ctx = { 39 .pending_work = true, 40 .cmd.q_control = { 41 .opcode = IONIC_CMD_Q_CONTROL, 42 .type = q->type, 43 .index = rte_cpu_to_le_32(q->index), 44 .oper = IONIC_Q_ENABLE, 45 }, 46 }; 47 48 return ionic_adminq_post_wait(lif, &ctx); 49 } 50 51 int 52 ionic_qcq_disable(struct ionic_qcq *qcq) 53 { 54 struct ionic_queue *q = &qcq->q; 55 struct ionic_lif *lif = qcq->lif; 56 struct ionic_admin_ctx ctx = { 57 .pending_work = true, 58 .cmd.q_control = { 59 .opcode = IONIC_CMD_Q_CONTROL, 60 .type = q->type, 61 .index = rte_cpu_to_le_32(q->index), 62 .oper = IONIC_Q_DISABLE, 63 }, 64 }; 65 66 return ionic_adminq_post_wait(lif, &ctx); 67 } 68 69 void 70 ionic_lif_stop(struct ionic_lif *lif) 71 { 72 uint32_t i; 73 74 IONIC_PRINT_CALL(); 75 76 lif->state &= ~IONIC_LIF_F_UP; 77 78 for (i = 0; i < lif->nrxqcqs; i++) { 79 struct ionic_qcq *rxq = lif->rxqcqs[i]; 80 if (rxq->flags & IONIC_QCQ_F_INITED) 81 (void)ionic_dev_rx_queue_stop(lif->eth_dev, i); 82 } 83 84 for (i = 0; i < lif->ntxqcqs; i++) { 85 struct ionic_qcq *txq = lif->txqcqs[i]; 86 if (txq->flags & IONIC_QCQ_F_INITED) 87 (void)ionic_dev_tx_queue_stop(lif->eth_dev, i); 88 } 89 } 90 91 void 92 ionic_lif_reset(struct ionic_lif *lif) 93 { 94 struct ionic_dev *idev = &lif->adapter->idev; 95 int err; 96 97 IONIC_PRINT_CALL(); 98 99 ionic_dev_cmd_lif_reset(idev); 100 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 101 if (err) 102 IONIC_PRINT(WARNING, "Failed to reset %s", lif->name); 103 } 104 105 static void 106 ionic_lif_get_abs_stats(const struct ionic_lif *lif, struct rte_eth_stats *stats) 107 { 108 struct ionic_lif_stats *ls = &lif->info->stats; 109 uint32_t i; 110 uint32_t num_rx_q_counters = RTE_MIN(lif->nrxqcqs, (uint32_t) 111 RTE_ETHDEV_QUEUE_STAT_CNTRS); 112 uint32_t num_tx_q_counters = RTE_MIN(lif->ntxqcqs, (uint32_t) 113 RTE_ETHDEV_QUEUE_STAT_CNTRS); 114 115 memset(stats, 0, sizeof(*stats)); 116 117 if (ls == NULL) { 118 IONIC_PRINT(DEBUG, "Stats on port %u not yet initialized", 119 lif->port_id); 120 return; 121 } 122 123 /* RX */ 124 125 stats->ipackets = ls->rx_ucast_packets + 126 ls->rx_mcast_packets + 127 ls->rx_bcast_packets; 128 129 stats->ibytes = ls->rx_ucast_bytes + 130 ls->rx_mcast_bytes + 131 ls->rx_bcast_bytes; 132 133 for (i = 0; i < lif->nrxqcqs; i++) { 134 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats.rx; 135 stats->imissed += 136 rx_stats->no_cb_arg + 137 rx_stats->bad_cq_status + 138 rx_stats->no_room + 139 rx_stats->bad_len; 140 } 141 142 stats->imissed += 143 ls->rx_ucast_drop_packets + 144 ls->rx_mcast_drop_packets + 145 ls->rx_bcast_drop_packets; 146 147 stats->imissed += 148 ls->rx_queue_empty + 149 ls->rx_dma_error + 150 ls->rx_queue_disabled + 151 ls->rx_desc_fetch_error + 152 ls->rx_desc_data_error; 153 154 for (i = 0; i < num_rx_q_counters; i++) { 155 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats.rx; 156 stats->q_ipackets[i] = rx_stats->packets; 157 stats->q_ibytes[i] = rx_stats->bytes; 158 stats->q_errors[i] = 159 rx_stats->no_cb_arg + 160 rx_stats->bad_cq_status + 161 rx_stats->no_room + 162 rx_stats->bad_len; 163 } 164 165 /* TX */ 166 167 stats->opackets = ls->tx_ucast_packets + 168 ls->tx_mcast_packets + 169 ls->tx_bcast_packets; 170 171 stats->obytes = ls->tx_ucast_bytes + 172 ls->tx_mcast_bytes + 173 ls->tx_bcast_bytes; 174 175 for (i = 0; i < lif->ntxqcqs; i++) { 176 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats.tx; 177 stats->oerrors += tx_stats->drop; 178 } 179 180 stats->oerrors += 181 ls->tx_ucast_drop_packets + 182 ls->tx_mcast_drop_packets + 183 ls->tx_bcast_drop_packets; 184 185 stats->oerrors += 186 ls->tx_dma_error + 187 ls->tx_queue_disabled + 188 ls->tx_desc_fetch_error + 189 ls->tx_desc_data_error; 190 191 for (i = 0; i < num_tx_q_counters; i++) { 192 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats.tx; 193 stats->q_opackets[i] = tx_stats->packets; 194 stats->q_obytes[i] = tx_stats->bytes; 195 } 196 } 197 198 void 199 ionic_lif_get_stats(const struct ionic_lif *lif, 200 struct rte_eth_stats *stats) 201 { 202 ionic_lif_get_abs_stats(lif, stats); 203 204 stats->ipackets -= lif->stats_base.ipackets; 205 stats->opackets -= lif->stats_base.opackets; 206 stats->ibytes -= lif->stats_base.ibytes; 207 stats->obytes -= lif->stats_base.obytes; 208 stats->imissed -= lif->stats_base.imissed; 209 stats->ierrors -= lif->stats_base.ierrors; 210 stats->oerrors -= lif->stats_base.oerrors; 211 stats->rx_nombuf -= lif->stats_base.rx_nombuf; 212 } 213 214 void 215 ionic_lif_reset_stats(struct ionic_lif *lif) 216 { 217 uint32_t i; 218 219 for (i = 0; i < lif->nrxqcqs; i++) { 220 memset(&lif->rxqcqs[i]->stats.rx, 0, 221 sizeof(struct ionic_rx_stats)); 222 memset(&lif->txqcqs[i]->stats.tx, 0, 223 sizeof(struct ionic_tx_stats)); 224 } 225 226 ionic_lif_get_abs_stats(lif, &lif->stats_base); 227 } 228 229 void 230 ionic_lif_get_hw_stats(struct ionic_lif *lif, struct ionic_lif_stats *stats) 231 { 232 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t); 233 uint64_t *stats64 = (uint64_t *)stats; 234 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats; 235 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base; 236 237 for (i = 0; i < count; i++) 238 stats64[i] = lif_stats64[i] - lif_stats64_base[i]; 239 } 240 241 void 242 ionic_lif_reset_hw_stats(struct ionic_lif *lif) 243 { 244 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t); 245 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats; 246 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base; 247 248 for (i = 0; i < count; i++) 249 lif_stats64_base[i] = lif_stats64[i]; 250 } 251 252 static int 253 ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr) 254 { 255 struct ionic_admin_ctx ctx = { 256 .pending_work = true, 257 .cmd.rx_filter_add = { 258 .opcode = IONIC_CMD_RX_FILTER_ADD, 259 .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_MAC), 260 }, 261 }; 262 int err; 263 264 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, RTE_ETHER_ADDR_LEN); 265 266 err = ionic_adminq_post_wait(lif, &ctx); 267 if (err) 268 return err; 269 270 IONIC_PRINT(INFO, "rx_filter add (id %d)", 271 rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id)); 272 273 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx); 274 } 275 276 static int 277 ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr) 278 { 279 struct ionic_admin_ctx ctx = { 280 .pending_work = true, 281 .cmd.rx_filter_del = { 282 .opcode = IONIC_CMD_RX_FILTER_DEL, 283 }, 284 }; 285 struct ionic_rx_filter *f; 286 int err; 287 288 IONIC_PRINT_CALL(); 289 290 rte_spinlock_lock(&lif->rx_filters.lock); 291 292 f = ionic_rx_filter_by_addr(lif, addr); 293 if (!f) { 294 rte_spinlock_unlock(&lif->rx_filters.lock); 295 return -ENOENT; 296 } 297 298 ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id); 299 ionic_rx_filter_free(f); 300 301 rte_spinlock_unlock(&lif->rx_filters.lock); 302 303 err = ionic_adminq_post_wait(lif, &ctx); 304 if (err) 305 return err; 306 307 IONIC_PRINT(INFO, "rx_filter del (id %d)", 308 rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id)); 309 310 return 0; 311 } 312 313 int 314 ionic_dev_add_mac(struct rte_eth_dev *eth_dev, 315 struct rte_ether_addr *mac_addr, 316 uint32_t index __rte_unused, uint32_t pool __rte_unused) 317 { 318 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 319 320 IONIC_PRINT_CALL(); 321 322 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr); 323 } 324 325 void 326 ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index) 327 { 328 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 329 struct ionic_adapter *adapter = lif->adapter; 330 struct rte_ether_addr *mac_addr; 331 332 IONIC_PRINT_CALL(); 333 334 if (index >= adapter->max_mac_addrs) { 335 IONIC_PRINT(WARNING, 336 "Index %u is above MAC filter limit %u", 337 index, adapter->max_mac_addrs); 338 return; 339 } 340 341 mac_addr = ð_dev->data->mac_addrs[index]; 342 343 if (!rte_is_valid_assigned_ether_addr(mac_addr)) 344 return; 345 346 ionic_lif_addr_del(lif, (const uint8_t *)mac_addr); 347 } 348 349 int 350 ionic_dev_set_mac(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr) 351 { 352 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 353 354 IONIC_PRINT_CALL(); 355 356 if (mac_addr == NULL) { 357 IONIC_PRINT(NOTICE, "New mac is null"); 358 return -1; 359 } 360 361 if (!rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) { 362 IONIC_PRINT(INFO, "Deleting mac addr %pM", 363 lif->mac_addr); 364 ionic_lif_addr_del(lif, lif->mac_addr); 365 memset(lif->mac_addr, 0, RTE_ETHER_ADDR_LEN); 366 } 367 368 IONIC_PRINT(INFO, "Updating mac addr"); 369 370 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)lif->mac_addr); 371 372 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr); 373 } 374 375 static int 376 ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid) 377 { 378 struct ionic_admin_ctx ctx = { 379 .pending_work = true, 380 .cmd.rx_filter_add = { 381 .opcode = IONIC_CMD_RX_FILTER_ADD, 382 .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_VLAN), 383 .vlan.vlan = rte_cpu_to_le_16(vid), 384 }, 385 }; 386 int err; 387 388 err = ionic_adminq_post_wait(lif, &ctx); 389 if (err) 390 return err; 391 392 IONIC_PRINT(INFO, "rx_filter add VLAN %d (id %d)", vid, 393 rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id)); 394 395 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx); 396 } 397 398 static int 399 ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid) 400 { 401 struct ionic_admin_ctx ctx = { 402 .pending_work = true, 403 .cmd.rx_filter_del = { 404 .opcode = IONIC_CMD_RX_FILTER_DEL, 405 }, 406 }; 407 struct ionic_rx_filter *f; 408 int err; 409 410 IONIC_PRINT_CALL(); 411 412 rte_spinlock_lock(&lif->rx_filters.lock); 413 414 f = ionic_rx_filter_by_vlan(lif, vid); 415 if (!f) { 416 rte_spinlock_unlock(&lif->rx_filters.lock); 417 return -ENOENT; 418 } 419 420 ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id); 421 ionic_rx_filter_free(f); 422 rte_spinlock_unlock(&lif->rx_filters.lock); 423 424 err = ionic_adminq_post_wait(lif, &ctx); 425 if (err) 426 return err; 427 428 IONIC_PRINT(INFO, "rx_filter del VLAN %d (id %d)", vid, 429 rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id)); 430 431 return 0; 432 } 433 434 int 435 ionic_dev_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id, 436 int on) 437 { 438 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 439 int err; 440 441 if (on) 442 err = ionic_vlan_rx_add_vid(lif, vlan_id); 443 else 444 err = ionic_vlan_rx_kill_vid(lif, vlan_id); 445 446 return err; 447 } 448 449 static void 450 ionic_lif_rx_mode(struct ionic_lif *lif, uint32_t rx_mode) 451 { 452 struct ionic_admin_ctx ctx = { 453 .pending_work = true, 454 .cmd.rx_mode_set = { 455 .opcode = IONIC_CMD_RX_MODE_SET, 456 .rx_mode = rte_cpu_to_le_16(rx_mode), 457 }, 458 }; 459 int err; 460 461 if (rx_mode & IONIC_RX_MODE_F_UNICAST) 462 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_UNICAST"); 463 if (rx_mode & IONIC_RX_MODE_F_MULTICAST) 464 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_MULTICAST"); 465 if (rx_mode & IONIC_RX_MODE_F_BROADCAST) 466 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_BROADCAST"); 467 if (rx_mode & IONIC_RX_MODE_F_PROMISC) 468 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_PROMISC"); 469 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI) 470 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_ALLMULTI"); 471 472 err = ionic_adminq_post_wait(lif, &ctx); 473 if (err) 474 IONIC_PRINT(ERR, "Failure setting RX mode"); 475 } 476 477 static void 478 ionic_set_rx_mode(struct ionic_lif *lif, uint32_t rx_mode) 479 { 480 if (lif->rx_mode != rx_mode) { 481 lif->rx_mode = rx_mode; 482 ionic_lif_rx_mode(lif, rx_mode); 483 } 484 } 485 486 int 487 ionic_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 488 { 489 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 490 uint32_t rx_mode = lif->rx_mode; 491 492 IONIC_PRINT_CALL(); 493 494 rx_mode |= IONIC_RX_MODE_F_PROMISC; 495 496 ionic_set_rx_mode(lif, rx_mode); 497 498 return 0; 499 } 500 501 int 502 ionic_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 503 { 504 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 505 uint32_t rx_mode = lif->rx_mode; 506 507 rx_mode &= ~IONIC_RX_MODE_F_PROMISC; 508 509 ionic_set_rx_mode(lif, rx_mode); 510 511 return 0; 512 } 513 514 int 515 ionic_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 516 { 517 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 518 uint32_t rx_mode = lif->rx_mode; 519 520 rx_mode |= IONIC_RX_MODE_F_ALLMULTI; 521 522 ionic_set_rx_mode(lif, rx_mode); 523 524 return 0; 525 } 526 527 int 528 ionic_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 529 { 530 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 531 uint32_t rx_mode = lif->rx_mode; 532 533 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI; 534 535 ionic_set_rx_mode(lif, rx_mode); 536 537 return 0; 538 } 539 540 int 541 ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu) 542 { 543 struct ionic_admin_ctx ctx = { 544 .pending_work = true, 545 .cmd.lif_setattr = { 546 .opcode = IONIC_CMD_LIF_SETATTR, 547 .attr = IONIC_LIF_ATTR_MTU, 548 .mtu = rte_cpu_to_le_32(new_mtu), 549 }, 550 }; 551 int err; 552 553 err = ionic_adminq_post_wait(lif, &ctx); 554 if (err) 555 return err; 556 557 return 0; 558 } 559 560 int 561 ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) 562 { 563 struct ionic_adapter *adapter = lif->adapter; 564 struct ionic_dev *idev = &adapter->idev; 565 unsigned long index; 566 567 /* 568 * Note: interrupt handler is called for index = 0 only 569 * (we use interrupts for the notifyq only anyway, 570 * which has index = 0) 571 */ 572 573 for (index = 0; index < adapter->nintrs; index++) 574 if (!adapter->intrs[index]) 575 break; 576 577 if (index == adapter->nintrs) 578 return -ENOSPC; 579 580 adapter->intrs[index] = true; 581 582 ionic_intr_init(idev, intr, index); 583 584 return 0; 585 } 586 587 static int 588 ionic_qcq_alloc(struct ionic_lif *lif, 589 uint8_t type, 590 uint32_t index, 591 const char *type_name, 592 uint16_t flags, 593 uint16_t num_descs, 594 uint16_t desc_size, 595 uint16_t cq_desc_size, 596 uint16_t sg_desc_size, 597 struct ionic_qcq **qcq) 598 { 599 struct ionic_qcq *new; 600 uint32_t q_size, cq_size, sg_size, total_size; 601 void *q_base, *cq_base, *sg_base; 602 rte_iova_t q_base_pa = 0; 603 rte_iova_t cq_base_pa = 0; 604 rte_iova_t sg_base_pa = 0; 605 uint32_t socket_id = rte_socket_id(); 606 int err; 607 608 *qcq = NULL; 609 610 q_size = num_descs * desc_size; 611 cq_size = num_descs * cq_desc_size; 612 sg_size = num_descs * sg_desc_size; 613 614 total_size = RTE_ALIGN(q_size, PAGE_SIZE) + 615 RTE_ALIGN(cq_size, PAGE_SIZE); 616 /* 617 * Note: aligning q_size/cq_size is not enough due to cq_base address 618 * aligning as q_base could be not aligned to the page. 619 * Adding PAGE_SIZE. 620 */ 621 total_size += PAGE_SIZE; 622 623 if (flags & IONIC_QCQ_F_SG) { 624 total_size += RTE_ALIGN(sg_size, PAGE_SIZE); 625 total_size += PAGE_SIZE; 626 } 627 628 new = rte_zmalloc("ionic", sizeof(*new), 0); 629 if (!new) { 630 IONIC_PRINT(ERR, "Cannot allocate queue structure"); 631 return -ENOMEM; 632 } 633 634 new->lif = lif; 635 new->flags = flags; 636 637 new->q.info = rte_zmalloc("ionic", sizeof(*new->q.info) * num_descs, 0); 638 if (!new->q.info) { 639 IONIC_PRINT(ERR, "Cannot allocate queue info"); 640 err = -ENOMEM; 641 goto err_out_free_qcq; 642 } 643 644 new->q.type = type; 645 646 err = ionic_q_init(&new->q, index, num_descs); 647 if (err) { 648 IONIC_PRINT(ERR, "Queue initialization failed"); 649 goto err_out_free_info; 650 } 651 652 err = ionic_cq_init(&new->cq, num_descs); 653 if (err) { 654 IONIC_PRINT(ERR, "Completion queue initialization failed"); 655 goto err_out_free_info; 656 } 657 658 new->base_z = rte_eth_dma_zone_reserve(lif->eth_dev, 659 type_name, index /* queue_idx */, 660 total_size, IONIC_ALIGN, socket_id); 661 662 if (!new->base_z) { 663 IONIC_PRINT(ERR, "Cannot reserve queue DMA memory"); 664 err = -ENOMEM; 665 goto err_out_free_info; 666 } 667 668 new->base = new->base_z->addr; 669 new->base_pa = new->base_z->iova; 670 new->total_size = total_size; 671 672 q_base = new->base; 673 q_base_pa = new->base_pa; 674 675 cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE); 676 cq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE); 677 678 if (flags & IONIC_QCQ_F_SG) { 679 sg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size, 680 PAGE_SIZE); 681 sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE); 682 ionic_q_sg_map(&new->q, sg_base, sg_base_pa); 683 } 684 685 IONIC_PRINT(DEBUG, "Q-Base-PA = %#jx CQ-Base-PA = %#jx " 686 "SG-base-PA = %#jx", 687 q_base_pa, cq_base_pa, sg_base_pa); 688 689 ionic_q_map(&new->q, q_base, q_base_pa); 690 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 691 692 *qcq = new; 693 694 return 0; 695 696 err_out_free_info: 697 rte_free(new->q.info); 698 err_out_free_qcq: 699 rte_free(new); 700 701 return err; 702 } 703 704 void 705 ionic_qcq_free(struct ionic_qcq *qcq) 706 { 707 if (qcq->base_z) { 708 qcq->base = NULL; 709 qcq->base_pa = 0; 710 rte_memzone_free(qcq->base_z); 711 qcq->base_z = NULL; 712 } 713 714 if (qcq->q.info) { 715 rte_free(qcq->q.info); 716 qcq->q.info = NULL; 717 } 718 719 rte_free(qcq); 720 } 721 722 int 723 ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t nrxq_descs, 724 struct ionic_qcq **qcq) 725 { 726 uint32_t flags; 727 int err = -ENOMEM; 728 729 flags = IONIC_QCQ_F_SG; 730 err = ionic_qcq_alloc(lif, 731 IONIC_QTYPE_RXQ, 732 index, 733 "rx", 734 flags, 735 nrxq_descs, 736 sizeof(struct ionic_rxq_desc), 737 sizeof(struct ionic_rxq_comp), 738 sizeof(struct ionic_rxq_sg_desc), 739 &lif->rxqcqs[index]); 740 if (err) 741 return err; 742 743 *qcq = lif->rxqcqs[index]; 744 745 return 0; 746 } 747 748 int 749 ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t ntxq_descs, 750 struct ionic_qcq **qcq) 751 { 752 uint32_t flags; 753 int err = -ENOMEM; 754 755 flags = IONIC_QCQ_F_SG; 756 err = ionic_qcq_alloc(lif, 757 IONIC_QTYPE_TXQ, 758 index, 759 "tx", 760 flags, 761 ntxq_descs, 762 sizeof(struct ionic_txq_desc), 763 sizeof(struct ionic_txq_comp), 764 sizeof(struct ionic_txq_sg_desc_v1), 765 &lif->txqcqs[index]); 766 if (err) 767 return err; 768 769 *qcq = lif->txqcqs[index]; 770 771 return 0; 772 } 773 774 static int 775 ionic_admin_qcq_alloc(struct ionic_lif *lif) 776 { 777 uint32_t flags; 778 int err = -ENOMEM; 779 780 flags = 0; 781 err = ionic_qcq_alloc(lif, 782 IONIC_QTYPE_ADMINQ, 783 0, 784 "admin", 785 flags, 786 IONIC_ADMINQ_LENGTH, 787 sizeof(struct ionic_admin_cmd), 788 sizeof(struct ionic_admin_comp), 789 0, 790 &lif->adminqcq); 791 if (err) 792 return err; 793 794 return 0; 795 } 796 797 static int 798 ionic_notify_qcq_alloc(struct ionic_lif *lif) 799 { 800 struct ionic_qcq *nqcq; 801 struct ionic_dev *idev = &lif->adapter->idev; 802 uint32_t flags = 0; 803 int err = -ENOMEM; 804 805 err = ionic_qcq_alloc(lif, 806 IONIC_QTYPE_NOTIFYQ, 807 0, 808 "notify", 809 flags, 810 IONIC_NOTIFYQ_LENGTH, 811 sizeof(struct ionic_notifyq_cmd), 812 sizeof(union ionic_notifyq_comp), 813 0, 814 &nqcq); 815 if (err) 816 return err; 817 818 err = ionic_intr_alloc(lif, &nqcq->intr); 819 if (err) { 820 ionic_qcq_free(nqcq); 821 return err; 822 } 823 824 ionic_intr_mask_assert(idev->intr_ctrl, nqcq->intr.index, 825 IONIC_INTR_MASK_SET); 826 827 lif->notifyqcq = nqcq; 828 829 return 0; 830 } 831 832 static void * 833 ionic_bus_map_dbpage(struct ionic_adapter *adapter, int page_num) 834 { 835 char *vaddr = adapter->bars[IONIC_PCI_BAR_DBELL].vaddr; 836 837 if (adapter->num_bars <= IONIC_PCI_BAR_DBELL) 838 return NULL; 839 840 return (void *)&vaddr[page_num << PAGE_SHIFT]; 841 } 842 843 static void 844 ionic_lif_queue_identify(struct ionic_lif *lif) 845 { 846 struct ionic_adapter *adapter = lif->adapter; 847 struct ionic_dev *idev = &adapter->idev; 848 union ionic_q_identity *q_ident = &adapter->ident.txq; 849 uint32_t q_words = RTE_DIM(q_ident->words); 850 uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data); 851 uint32_t i, nwords, qtype; 852 int err; 853 854 for (qtype = 0; qtype < RTE_DIM(ionic_qtype_vers); qtype++) { 855 struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; 856 857 /* Filter out the types this driver knows about */ 858 switch (qtype) { 859 case IONIC_QTYPE_ADMINQ: 860 case IONIC_QTYPE_NOTIFYQ: 861 case IONIC_QTYPE_RXQ: 862 case IONIC_QTYPE_TXQ: 863 break; 864 default: 865 continue; 866 } 867 868 memset(qti, 0, sizeof(*qti)); 869 870 ionic_dev_cmd_queue_identify(idev, IONIC_LIF_TYPE_CLASSIC, 871 qtype, ionic_qtype_vers[qtype]); 872 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 873 if (err == -EINVAL) { 874 IONIC_PRINT(ERR, "qtype %d not supported\n", qtype); 875 continue; 876 } else if (err == -EIO) { 877 IONIC_PRINT(ERR, "q_ident failed, older FW\n"); 878 return; 879 } else if (err) { 880 IONIC_PRINT(ERR, "q_ident failed, qtype %d: %d\n", 881 qtype, err); 882 return; 883 } 884 885 nwords = RTE_MIN(q_words, cmd_words); 886 for (i = 0; i < nwords; i++) 887 q_ident->words[i] = ioread32(&idev->dev_cmd->data[i]); 888 889 qti->version = q_ident->version; 890 qti->supported = q_ident->supported; 891 qti->features = rte_le_to_cpu_64(q_ident->features); 892 qti->desc_sz = rte_le_to_cpu_16(q_ident->desc_sz); 893 qti->comp_sz = rte_le_to_cpu_16(q_ident->comp_sz); 894 qti->sg_desc_sz = rte_le_to_cpu_16(q_ident->sg_desc_sz); 895 qti->max_sg_elems = rte_le_to_cpu_16(q_ident->max_sg_elems); 896 qti->sg_desc_stride = 897 rte_le_to_cpu_16(q_ident->sg_desc_stride); 898 899 IONIC_PRINT(DEBUG, " qtype[%d].version = %d", 900 qtype, qti->version); 901 IONIC_PRINT(DEBUG, " qtype[%d].supported = %#x", 902 qtype, qti->supported); 903 IONIC_PRINT(DEBUG, " qtype[%d].features = %#jx", 904 qtype, qti->features); 905 IONIC_PRINT(DEBUG, " qtype[%d].desc_sz = %d", 906 qtype, qti->desc_sz); 907 IONIC_PRINT(DEBUG, " qtype[%d].comp_sz = %d", 908 qtype, qti->comp_sz); 909 IONIC_PRINT(DEBUG, " qtype[%d].sg_desc_sz = %d", 910 qtype, qti->sg_desc_sz); 911 IONIC_PRINT(DEBUG, " qtype[%d].max_sg_elems = %d", 912 qtype, qti->max_sg_elems); 913 IONIC_PRINT(DEBUG, " qtype[%d].sg_desc_stride = %d", 914 qtype, qti->sg_desc_stride); 915 } 916 } 917 918 int 919 ionic_lif_alloc(struct ionic_lif *lif) 920 { 921 struct ionic_adapter *adapter = lif->adapter; 922 uint32_t socket_id = rte_socket_id(); 923 int err; 924 925 /* 926 * lif->name was zeroed on allocation. 927 * Copy (sizeof() - 1) bytes to ensure that it is NULL terminated. 928 */ 929 memcpy(lif->name, lif->eth_dev->data->name, sizeof(lif->name) - 1); 930 931 IONIC_PRINT(DEBUG, "LIF: %s", lif->name); 932 933 ionic_lif_queue_identify(lif); 934 935 if (lif->qtype_info[IONIC_QTYPE_TXQ].version < 1) { 936 IONIC_PRINT(ERR, "FW too old, please upgrade"); 937 return -ENXIO; 938 } 939 940 IONIC_PRINT(DEBUG, "Allocating Lif Info"); 941 942 rte_spinlock_init(&lif->adminq_lock); 943 rte_spinlock_init(&lif->adminq_service_lock); 944 945 lif->kern_dbpage = ionic_bus_map_dbpage(adapter, 0); 946 if (!lif->kern_dbpage) { 947 IONIC_PRINT(ERR, "Cannot map dbpage, aborting"); 948 return -ENOMEM; 949 } 950 951 lif->txqcqs = rte_zmalloc("ionic", sizeof(*lif->txqcqs) * 952 adapter->max_ntxqs_per_lif, 0); 953 954 if (!lif->txqcqs) { 955 IONIC_PRINT(ERR, "Cannot allocate tx queues array"); 956 return -ENOMEM; 957 } 958 959 lif->rxqcqs = rte_zmalloc("ionic", sizeof(*lif->rxqcqs) * 960 adapter->max_nrxqs_per_lif, 0); 961 962 if (!lif->rxqcqs) { 963 IONIC_PRINT(ERR, "Cannot allocate rx queues array"); 964 return -ENOMEM; 965 } 966 967 IONIC_PRINT(DEBUG, "Allocating Notify Queue"); 968 969 err = ionic_notify_qcq_alloc(lif); 970 if (err) { 971 IONIC_PRINT(ERR, "Cannot allocate notify queue"); 972 return err; 973 } 974 975 IONIC_PRINT(DEBUG, "Allocating Admin Queue"); 976 977 err = ionic_admin_qcq_alloc(lif); 978 if (err) { 979 IONIC_PRINT(ERR, "Cannot allocate admin queue"); 980 return err; 981 } 982 983 IONIC_PRINT(DEBUG, "Allocating Lif Info"); 984 985 lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE); 986 987 lif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev, 988 "lif_info", 0 /* queue_idx*/, 989 lif->info_sz, IONIC_ALIGN, socket_id); 990 if (!lif->info_z) { 991 IONIC_PRINT(ERR, "Cannot allocate lif info memory"); 992 return -ENOMEM; 993 } 994 995 lif->info = lif->info_z->addr; 996 lif->info_pa = lif->info_z->iova; 997 998 return 0; 999 } 1000 1001 void 1002 ionic_lif_free(struct ionic_lif *lif) 1003 { 1004 if (lif->notifyqcq) { 1005 ionic_qcq_free(lif->notifyqcq); 1006 lif->notifyqcq = NULL; 1007 } 1008 1009 if (lif->adminqcq) { 1010 ionic_qcq_free(lif->adminqcq); 1011 lif->adminqcq = NULL; 1012 } 1013 1014 if (lif->txqcqs) { 1015 rte_free(lif->txqcqs); 1016 lif->txqcqs = NULL; 1017 } 1018 1019 if (lif->rxqcqs) { 1020 rte_free(lif->rxqcqs); 1021 lif->rxqcqs = NULL; 1022 } 1023 1024 if (lif->info) { 1025 rte_memzone_free(lif->info_z); 1026 lif->info = NULL; 1027 } 1028 } 1029 1030 void 1031 ionic_lif_free_queues(struct ionic_lif *lif) 1032 { 1033 uint32_t i; 1034 1035 for (i = 0; i < lif->ntxqcqs; i++) { 1036 ionic_dev_tx_queue_release(lif->eth_dev->data->tx_queues[i]); 1037 lif->eth_dev->data->tx_queues[i] = NULL; 1038 } 1039 for (i = 0; i < lif->nrxqcqs; i++) { 1040 ionic_dev_rx_queue_release(lif->eth_dev->data->rx_queues[i]); 1041 lif->eth_dev->data->rx_queues[i] = NULL; 1042 } 1043 } 1044 1045 int 1046 ionic_lif_rss_config(struct ionic_lif *lif, 1047 const uint16_t types, const uint8_t *key, const uint32_t *indir) 1048 { 1049 struct ionic_adapter *adapter = lif->adapter; 1050 struct ionic_admin_ctx ctx = { 1051 .pending_work = true, 1052 .cmd.lif_setattr = { 1053 .opcode = IONIC_CMD_LIF_SETATTR, 1054 .attr = IONIC_LIF_ATTR_RSS, 1055 .rss.types = rte_cpu_to_le_16(types), 1056 .rss.addr = rte_cpu_to_le_64(lif->rss_ind_tbl_pa), 1057 }, 1058 }; 1059 unsigned int i; 1060 uint16_t tbl_sz = 1061 rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz); 1062 1063 IONIC_PRINT_CALL(); 1064 1065 lif->rss_types = types; 1066 1067 if (key) 1068 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); 1069 1070 if (indir) 1071 for (i = 0; i < tbl_sz; i++) 1072 lif->rss_ind_tbl[i] = indir[i]; 1073 1074 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, 1075 IONIC_RSS_HASH_KEY_SIZE); 1076 1077 return ionic_adminq_post_wait(lif, &ctx); 1078 } 1079 1080 static int 1081 ionic_lif_rss_setup(struct ionic_lif *lif) 1082 { 1083 struct ionic_adapter *adapter = lif->adapter; 1084 static const uint8_t toeplitz_symmetric_key[] = { 1085 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 1086 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 1087 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 1088 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 1089 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 1090 }; 1091 uint32_t i; 1092 uint16_t tbl_sz = 1093 rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz); 1094 1095 IONIC_PRINT_CALL(); 1096 1097 if (!lif->rss_ind_tbl_z) { 1098 lif->rss_ind_tbl_z = rte_eth_dma_zone_reserve(lif->eth_dev, 1099 "rss_ind_tbl", 0 /* queue_idx */, 1100 sizeof(*lif->rss_ind_tbl) * tbl_sz, 1101 IONIC_ALIGN, rte_socket_id()); 1102 if (!lif->rss_ind_tbl_z) { 1103 IONIC_PRINT(ERR, "OOM"); 1104 return -ENOMEM; 1105 } 1106 1107 lif->rss_ind_tbl = lif->rss_ind_tbl_z->addr; 1108 lif->rss_ind_tbl_pa = lif->rss_ind_tbl_z->iova; 1109 } 1110 1111 if (lif->rss_ind_tbl_nrxqcqs != lif->nrxqcqs) { 1112 lif->rss_ind_tbl_nrxqcqs = lif->nrxqcqs; 1113 1114 /* Fill indirection table with 'default' values */ 1115 for (i = 0; i < tbl_sz; i++) 1116 lif->rss_ind_tbl[i] = i % lif->nrxqcqs; 1117 } 1118 1119 return ionic_lif_rss_config(lif, IONIC_RSS_OFFLOAD_ALL, 1120 toeplitz_symmetric_key, NULL); 1121 } 1122 1123 static void 1124 ionic_lif_rss_teardown(struct ionic_lif *lif) 1125 { 1126 if (!lif->rss_ind_tbl) 1127 return; 1128 1129 if (lif->rss_ind_tbl_z) { 1130 /* Disable RSS on the NIC */ 1131 ionic_lif_rss_config(lif, 0x0, NULL, NULL); 1132 1133 lif->rss_ind_tbl = NULL; 1134 lif->rss_ind_tbl_pa = 0; 1135 rte_memzone_free(lif->rss_ind_tbl_z); 1136 lif->rss_ind_tbl_z = NULL; 1137 } 1138 } 1139 1140 static void 1141 ionic_lif_qcq_deinit(struct ionic_qcq *qcq) 1142 { 1143 qcq->flags &= ~IONIC_QCQ_F_INITED; 1144 } 1145 1146 void 1147 ionic_lif_txq_deinit(struct ionic_qcq *qcq) 1148 { 1149 ionic_lif_qcq_deinit(qcq); 1150 } 1151 1152 void 1153 ionic_lif_rxq_deinit(struct ionic_qcq *qcq) 1154 { 1155 ionic_lif_qcq_deinit(qcq); 1156 } 1157 1158 static void 1159 ionic_lif_notifyq_deinit(struct ionic_lif *lif) 1160 { 1161 struct ionic_qcq *nqcq = lif->notifyqcq; 1162 struct ionic_dev *idev = &lif->adapter->idev; 1163 1164 if (!(nqcq->flags & IONIC_QCQ_F_INITED)) 1165 return; 1166 1167 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index, 1168 IONIC_INTR_MASK_SET); 1169 1170 nqcq->flags &= ~IONIC_QCQ_F_INITED; 1171 } 1172 1173 /* This acts like ionic_napi */ 1174 int 1175 ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb, 1176 void *cb_arg) 1177 { 1178 struct ionic_cq *cq = &qcq->cq; 1179 uint32_t work_done; 1180 1181 work_done = ionic_cq_service(cq, budget, cb, cb_arg); 1182 1183 return work_done; 1184 } 1185 1186 static void 1187 ionic_link_status_check(struct ionic_lif *lif) 1188 { 1189 struct ionic_adapter *adapter = lif->adapter; 1190 bool link_up; 1191 1192 lif->state &= ~IONIC_LIF_F_LINK_CHECK_NEEDED; 1193 1194 if (!lif->info) 1195 return; 1196 1197 link_up = (lif->info->status.link_status == IONIC_PORT_OPER_STATUS_UP); 1198 1199 if ((link_up && adapter->link_up) || 1200 (!link_up && !adapter->link_up)) 1201 return; 1202 1203 if (link_up) { 1204 adapter->link_speed = 1205 rte_le_to_cpu_32(lif->info->status.link_speed); 1206 IONIC_PRINT(DEBUG, "Link up - %d Gbps", 1207 adapter->link_speed); 1208 } else { 1209 IONIC_PRINT(DEBUG, "Link down"); 1210 } 1211 1212 adapter->link_up = link_up; 1213 ionic_dev_link_update(lif->eth_dev, 0); 1214 } 1215 1216 static void 1217 ionic_lif_handle_fw_down(struct ionic_lif *lif) 1218 { 1219 if (lif->state & IONIC_LIF_F_FW_RESET) 1220 return; 1221 1222 lif->state |= IONIC_LIF_F_FW_RESET; 1223 1224 if (lif->state & IONIC_LIF_F_UP) { 1225 IONIC_PRINT(NOTICE, 1226 "Surprise FW stop, stopping %s\n", lif->name); 1227 ionic_lif_stop(lif); 1228 } 1229 1230 IONIC_PRINT(NOTICE, "FW down, %s stopped", lif->name); 1231 } 1232 1233 static bool 1234 ionic_notifyq_cb(struct ionic_cq *cq, uint16_t cq_desc_index, void *cb_arg) 1235 { 1236 union ionic_notifyq_comp *cq_desc_base = cq->base; 1237 union ionic_notifyq_comp *cq_desc = &cq_desc_base[cq_desc_index]; 1238 struct ionic_lif *lif = cb_arg; 1239 1240 IONIC_PRINT(DEBUG, "Notifyq callback eid = %jd ecode = %d", 1241 cq_desc->event.eid, cq_desc->event.ecode); 1242 1243 /* Have we run out of new completions to process? */ 1244 if (!(cq_desc->event.eid > lif->last_eid)) 1245 return false; 1246 1247 lif->last_eid = cq_desc->event.eid; 1248 1249 switch (cq_desc->event.ecode) { 1250 case IONIC_EVENT_LINK_CHANGE: 1251 IONIC_PRINT(DEBUG, 1252 "Notifyq IONIC_EVENT_LINK_CHANGE %s " 1253 "eid=%jd link_status=%d link_speed=%d", 1254 lif->name, 1255 cq_desc->event.eid, 1256 cq_desc->link_change.link_status, 1257 cq_desc->link_change.link_speed); 1258 1259 lif->state |= IONIC_LIF_F_LINK_CHECK_NEEDED; 1260 break; 1261 1262 case IONIC_EVENT_RESET: 1263 IONIC_PRINT(NOTICE, 1264 "Notifyq IONIC_EVENT_RESET %s " 1265 "eid=%jd, reset_code=%d state=%d", 1266 lif->name, 1267 cq_desc->event.eid, 1268 cq_desc->reset.reset_code, 1269 cq_desc->reset.state); 1270 ionic_lif_handle_fw_down(lif); 1271 break; 1272 1273 default: 1274 IONIC_PRINT(WARNING, "Notifyq bad event ecode=%d eid=%jd", 1275 cq_desc->event.ecode, cq_desc->event.eid); 1276 break; 1277 } 1278 1279 return true; 1280 } 1281 1282 int 1283 ionic_notifyq_handler(struct ionic_lif *lif, int budget) 1284 { 1285 struct ionic_dev *idev = &lif->adapter->idev; 1286 struct ionic_qcq *qcq = lif->notifyqcq; 1287 uint32_t work_done; 1288 1289 if (!(qcq->flags & IONIC_QCQ_F_INITED)) { 1290 IONIC_PRINT(DEBUG, "Notifyq not yet initialized"); 1291 return -1; 1292 } 1293 1294 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 1295 IONIC_INTR_MASK_SET); 1296 1297 work_done = ionic_qcq_service(qcq, budget, ionic_notifyq_cb, lif); 1298 1299 if (lif->state & IONIC_LIF_F_LINK_CHECK_NEEDED) 1300 ionic_link_status_check(lif); 1301 1302 ionic_intr_credits(idev->intr_ctrl, qcq->intr.index, 1303 work_done, IONIC_INTR_CRED_RESET_COALESCE); 1304 1305 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 1306 IONIC_INTR_MASK_CLEAR); 1307 1308 return 0; 1309 } 1310 1311 static int 1312 ionic_lif_adminq_init(struct ionic_lif *lif) 1313 { 1314 struct ionic_dev *idev = &lif->adapter->idev; 1315 struct ionic_qcq *qcq = lif->adminqcq; 1316 struct ionic_queue *q = &qcq->q; 1317 struct ionic_q_init_comp comp; 1318 int err; 1319 1320 ionic_dev_cmd_adminq_init(idev, qcq); 1321 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 1322 if (err) 1323 return err; 1324 1325 ionic_dev_cmd_comp(idev, &comp); 1326 1327 q->hw_type = comp.hw_type; 1328 q->hw_index = rte_le_to_cpu_32(comp.hw_index); 1329 q->db = ionic_db_map(lif, q); 1330 1331 IONIC_PRINT(DEBUG, "adminq->hw_type %d", q->hw_type); 1332 IONIC_PRINT(DEBUG, "adminq->hw_index %d", q->hw_index); 1333 IONIC_PRINT(DEBUG, "adminq->db %p", q->db); 1334 1335 qcq->flags |= IONIC_QCQ_F_INITED; 1336 1337 return 0; 1338 } 1339 1340 static int 1341 ionic_lif_notifyq_init(struct ionic_lif *lif) 1342 { 1343 struct ionic_dev *idev = &lif->adapter->idev; 1344 struct ionic_qcq *qcq = lif->notifyqcq; 1345 struct ionic_queue *q = &qcq->q; 1346 int err; 1347 1348 struct ionic_admin_ctx ctx = { 1349 .pending_work = true, 1350 .cmd.q_init = { 1351 .opcode = IONIC_CMD_Q_INIT, 1352 .type = q->type, 1353 .ver = lif->qtype_info[q->type].version, 1354 .index = rte_cpu_to_le_32(q->index), 1355 .intr_index = rte_cpu_to_le_16(qcq->intr.index), 1356 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_IRQ | 1357 IONIC_QINIT_F_ENA), 1358 .ring_size = rte_log2_u32(q->num_descs), 1359 .ring_base = rte_cpu_to_le_64(q->base_pa), 1360 } 1361 }; 1362 1363 IONIC_PRINT(DEBUG, "notifyq_init.index %d", q->index); 1364 IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "", q->base_pa); 1365 IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d", 1366 ctx.cmd.q_init.ring_size); 1367 IONIC_PRINT(DEBUG, "notifyq_init.ver %u", ctx.cmd.q_init.ver); 1368 1369 err = ionic_adminq_post_wait(lif, &ctx); 1370 if (err) 1371 return err; 1372 1373 q->hw_type = ctx.comp.q_init.hw_type; 1374 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index); 1375 q->db = NULL; 1376 1377 IONIC_PRINT(DEBUG, "notifyq->hw_type %d", q->hw_type); 1378 IONIC_PRINT(DEBUG, "notifyq->hw_index %d", q->hw_index); 1379 IONIC_PRINT(DEBUG, "notifyq->db %p", q->db); 1380 1381 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 1382 IONIC_INTR_MASK_CLEAR); 1383 1384 qcq->flags |= IONIC_QCQ_F_INITED; 1385 1386 return 0; 1387 } 1388 1389 int 1390 ionic_lif_set_features(struct ionic_lif *lif) 1391 { 1392 struct ionic_admin_ctx ctx = { 1393 .pending_work = true, 1394 .cmd.lif_setattr = { 1395 .opcode = IONIC_CMD_LIF_SETATTR, 1396 .attr = IONIC_LIF_ATTR_FEATURES, 1397 .features = rte_cpu_to_le_64(lif->features), 1398 }, 1399 }; 1400 int err; 1401 1402 err = ionic_adminq_post_wait(lif, &ctx); 1403 if (err) 1404 return err; 1405 1406 lif->hw_features = rte_le_to_cpu_64(ctx.cmd.lif_setattr.features & 1407 ctx.comp.lif_setattr.features); 1408 1409 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1410 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_TX_TAG"); 1411 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1412 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_STRIP"); 1413 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1414 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_FILTER"); 1415 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1416 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_HASH"); 1417 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1418 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_SG"); 1419 if (lif->hw_features & IONIC_ETH_HW_RX_SG) 1420 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_SG"); 1421 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1422 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_CSUM"); 1423 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1424 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_CSUM"); 1425 if (lif->hw_features & IONIC_ETH_HW_TSO) 1426 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO"); 1427 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1428 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPV6"); 1429 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1430 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_ECN"); 1431 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1432 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE"); 1433 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1434 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE_CSUM"); 1435 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1436 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP4"); 1437 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1438 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP6"); 1439 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1440 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP"); 1441 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1442 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP_CSUM"); 1443 1444 return 0; 1445 } 1446 1447 int 1448 ionic_lif_txq_init(struct ionic_qcq *qcq) 1449 { 1450 struct ionic_queue *q = &qcq->q; 1451 struct ionic_lif *lif = qcq->lif; 1452 struct ionic_cq *cq = &qcq->cq; 1453 struct ionic_admin_ctx ctx = { 1454 .pending_work = true, 1455 .cmd.q_init = { 1456 .opcode = IONIC_CMD_Q_INIT, 1457 .type = q->type, 1458 .ver = lif->qtype_info[q->type].version, 1459 .index = rte_cpu_to_le_32(q->index), 1460 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG | 1461 IONIC_QINIT_F_ENA), 1462 .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE), 1463 .ring_size = rte_log2_u32(q->num_descs), 1464 .ring_base = rte_cpu_to_le_64(q->base_pa), 1465 .cq_ring_base = rte_cpu_to_le_64(cq->base_pa), 1466 .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa), 1467 }, 1468 }; 1469 int err; 1470 1471 IONIC_PRINT(DEBUG, "txq_init.index %d", q->index); 1472 IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "", q->base_pa); 1473 IONIC_PRINT(DEBUG, "txq_init.ring_size %d", 1474 ctx.cmd.q_init.ring_size); 1475 IONIC_PRINT(DEBUG, "txq_init.ver %u", ctx.cmd.q_init.ver); 1476 1477 err = ionic_adminq_post_wait(qcq->lif, &ctx); 1478 if (err) 1479 return err; 1480 1481 q->hw_type = ctx.comp.q_init.hw_type; 1482 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index); 1483 q->db = ionic_db_map(lif, q); 1484 1485 IONIC_PRINT(DEBUG, "txq->hw_type %d", q->hw_type); 1486 IONIC_PRINT(DEBUG, "txq->hw_index %d", q->hw_index); 1487 IONIC_PRINT(DEBUG, "txq->db %p", q->db); 1488 1489 qcq->flags |= IONIC_QCQ_F_INITED; 1490 1491 return 0; 1492 } 1493 1494 int 1495 ionic_lif_rxq_init(struct ionic_qcq *qcq) 1496 { 1497 struct ionic_queue *q = &qcq->q; 1498 struct ionic_lif *lif = qcq->lif; 1499 struct ionic_cq *cq = &qcq->cq; 1500 struct ionic_admin_ctx ctx = { 1501 .pending_work = true, 1502 .cmd.q_init = { 1503 .opcode = IONIC_CMD_Q_INIT, 1504 .type = q->type, 1505 .ver = lif->qtype_info[q->type].version, 1506 .index = rte_cpu_to_le_32(q->index), 1507 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG | 1508 IONIC_QINIT_F_ENA), 1509 .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE), 1510 .ring_size = rte_log2_u32(q->num_descs), 1511 .ring_base = rte_cpu_to_le_64(q->base_pa), 1512 .cq_ring_base = rte_cpu_to_le_64(cq->base_pa), 1513 .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa), 1514 }, 1515 }; 1516 int err; 1517 1518 IONIC_PRINT(DEBUG, "rxq_init.index %d", q->index); 1519 IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "", q->base_pa); 1520 IONIC_PRINT(DEBUG, "rxq_init.ring_size %d", 1521 ctx.cmd.q_init.ring_size); 1522 IONIC_PRINT(DEBUG, "rxq_init.ver %u", ctx.cmd.q_init.ver); 1523 1524 err = ionic_adminq_post_wait(qcq->lif, &ctx); 1525 if (err) 1526 return err; 1527 1528 q->hw_type = ctx.comp.q_init.hw_type; 1529 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index); 1530 q->db = ionic_db_map(lif, q); 1531 1532 qcq->flags |= IONIC_QCQ_F_INITED; 1533 1534 IONIC_PRINT(DEBUG, "rxq->hw_type %d", q->hw_type); 1535 IONIC_PRINT(DEBUG, "rxq->hw_index %d", q->hw_index); 1536 IONIC_PRINT(DEBUG, "rxq->db %p", q->db); 1537 1538 return 0; 1539 } 1540 1541 static int 1542 ionic_station_set(struct ionic_lif *lif) 1543 { 1544 struct ionic_admin_ctx ctx = { 1545 .pending_work = true, 1546 .cmd.lif_getattr = { 1547 .opcode = IONIC_CMD_LIF_GETATTR, 1548 .attr = IONIC_LIF_ATTR_MAC, 1549 }, 1550 }; 1551 int err; 1552 1553 IONIC_PRINT_CALL(); 1554 1555 err = ionic_adminq_post_wait(lif, &ctx); 1556 if (err) 1557 return err; 1558 1559 memcpy(lif->mac_addr, ctx.comp.lif_getattr.mac, RTE_ETHER_ADDR_LEN); 1560 1561 return 0; 1562 } 1563 1564 static void 1565 ionic_lif_set_name(struct ionic_lif *lif) 1566 { 1567 struct ionic_admin_ctx ctx = { 1568 .pending_work = true, 1569 .cmd.lif_setattr = { 1570 .opcode = IONIC_CMD_LIF_SETATTR, 1571 .attr = IONIC_LIF_ATTR_NAME, 1572 }, 1573 }; 1574 1575 memcpy(ctx.cmd.lif_setattr.name, lif->name, 1576 sizeof(ctx.cmd.lif_setattr.name) - 1); 1577 1578 ionic_adminq_post_wait(lif, &ctx); 1579 } 1580 1581 int 1582 ionic_lif_init(struct ionic_lif *lif) 1583 { 1584 struct ionic_dev *idev = &lif->adapter->idev; 1585 struct ionic_q_init_comp comp; 1586 int err; 1587 1588 memset(&lif->stats_base, 0, sizeof(lif->stats_base)); 1589 1590 ionic_dev_cmd_lif_init(idev, lif->info_pa); 1591 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 1592 ionic_dev_cmd_comp(idev, &comp); 1593 if (err) 1594 return err; 1595 1596 lif->hw_index = rte_cpu_to_le_16(comp.hw_index); 1597 1598 err = ionic_lif_adminq_init(lif); 1599 if (err) 1600 return err; 1601 1602 err = ionic_lif_notifyq_init(lif); 1603 if (err) 1604 goto err_out_adminq_deinit; 1605 1606 /* 1607 * Configure initial feature set 1608 * This will be updated later by the dev_configure() step 1609 */ 1610 lif->features = IONIC_ETH_HW_RX_HASH | IONIC_ETH_HW_VLAN_RX_FILTER; 1611 1612 err = ionic_lif_set_features(lif); 1613 if (err) 1614 goto err_out_notifyq_deinit; 1615 1616 err = ionic_rx_filters_init(lif); 1617 if (err) 1618 goto err_out_notifyq_deinit; 1619 1620 err = ionic_station_set(lif); 1621 if (err) 1622 goto err_out_rx_filter_deinit; 1623 1624 ionic_lif_set_name(lif); 1625 1626 lif->state |= IONIC_LIF_F_INITED; 1627 1628 return 0; 1629 1630 err_out_rx_filter_deinit: 1631 ionic_rx_filters_deinit(lif); 1632 1633 err_out_notifyq_deinit: 1634 ionic_lif_notifyq_deinit(lif); 1635 1636 err_out_adminq_deinit: 1637 ionic_lif_qcq_deinit(lif->adminqcq); 1638 1639 return err; 1640 } 1641 1642 void 1643 ionic_lif_deinit(struct ionic_lif *lif) 1644 { 1645 if (!(lif->state & IONIC_LIF_F_INITED)) 1646 return; 1647 1648 ionic_rx_filters_deinit(lif); 1649 ionic_lif_rss_teardown(lif); 1650 ionic_lif_notifyq_deinit(lif); 1651 ionic_lif_qcq_deinit(lif->adminqcq); 1652 1653 lif->state &= ~IONIC_LIF_F_INITED; 1654 } 1655 1656 void 1657 ionic_lif_configure_vlan_offload(struct ionic_lif *lif, int mask) 1658 { 1659 struct rte_eth_dev *eth_dev = lif->eth_dev; 1660 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 1661 1662 /* 1663 * IONIC_ETH_HW_VLAN_RX_FILTER cannot be turned off, so 1664 * set DEV_RX_OFFLOAD_VLAN_FILTER and ignore ETH_VLAN_FILTER_MASK 1665 */ 1666 rxmode->offloads |= DEV_RX_OFFLOAD_VLAN_FILTER; 1667 1668 if (mask & ETH_VLAN_STRIP_MASK) { 1669 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1670 lif->features |= IONIC_ETH_HW_VLAN_RX_STRIP; 1671 else 1672 lif->features &= ~IONIC_ETH_HW_VLAN_RX_STRIP; 1673 } 1674 } 1675 1676 void 1677 ionic_lif_configure(struct ionic_lif *lif) 1678 { 1679 struct rte_eth_rxmode *rxmode = &lif->eth_dev->data->dev_conf.rxmode; 1680 struct rte_eth_txmode *txmode = &lif->eth_dev->data->dev_conf.txmode; 1681 struct ionic_identity *ident = &lif->adapter->ident; 1682 union ionic_lif_config *cfg = &ident->lif.eth.config; 1683 uint32_t ntxqs_per_lif = 1684 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); 1685 uint32_t nrxqs_per_lif = 1686 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); 1687 uint32_t nrxqs = lif->eth_dev->data->nb_rx_queues; 1688 uint32_t ntxqs = lif->eth_dev->data->nb_tx_queues; 1689 1690 lif->port_id = lif->eth_dev->data->port_id; 1691 1692 IONIC_PRINT(DEBUG, "Configuring LIF on port %u", 1693 lif->port_id); 1694 1695 if (nrxqs > 0) 1696 nrxqs_per_lif = RTE_MIN(nrxqs_per_lif, nrxqs); 1697 1698 if (ntxqs > 0) 1699 ntxqs_per_lif = RTE_MIN(ntxqs_per_lif, ntxqs); 1700 1701 lif->nrxqcqs = nrxqs_per_lif; 1702 lif->ntxqcqs = ntxqs_per_lif; 1703 1704 /* Update the LIF configuration based on the eth_dev */ 1705 1706 /* 1707 * NB: While it is true that RSS_HASH is always enabled on ionic, 1708 * setting this flag unconditionally causes problems in DTS. 1709 * rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1710 */ 1711 1712 /* RX per-port */ 1713 1714 if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM || 1715 rxmode->offloads & DEV_RX_OFFLOAD_UDP_CKSUM || 1716 rxmode->offloads & DEV_RX_OFFLOAD_TCP_CKSUM) 1717 lif->features |= IONIC_ETH_HW_RX_CSUM; 1718 else 1719 lif->features &= ~IONIC_ETH_HW_RX_CSUM; 1720 1721 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) { 1722 lif->features |= IONIC_ETH_HW_RX_SG; 1723 lif->eth_dev->data->scattered_rx = 1; 1724 } else { 1725 lif->features &= ~IONIC_ETH_HW_RX_SG; 1726 lif->eth_dev->data->scattered_rx = 0; 1727 } 1728 1729 /* Covers VLAN_STRIP */ 1730 ionic_lif_configure_vlan_offload(lif, ETH_VLAN_STRIP_MASK); 1731 1732 /* TX per-port */ 1733 1734 if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM || 1735 txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM || 1736 txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM || 1737 txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM || 1738 txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM) 1739 lif->features |= IONIC_ETH_HW_TX_CSUM; 1740 else 1741 lif->features &= ~IONIC_ETH_HW_TX_CSUM; 1742 1743 if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT) 1744 lif->features |= IONIC_ETH_HW_VLAN_TX_TAG; 1745 else 1746 lif->features &= ~IONIC_ETH_HW_VLAN_TX_TAG; 1747 1748 if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS) 1749 lif->features |= IONIC_ETH_HW_TX_SG; 1750 else 1751 lif->features &= ~IONIC_ETH_HW_TX_SG; 1752 1753 if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) { 1754 lif->features |= IONIC_ETH_HW_TSO; 1755 lif->features |= IONIC_ETH_HW_TSO_IPV6; 1756 lif->features |= IONIC_ETH_HW_TSO_ECN; 1757 } else { 1758 lif->features &= ~IONIC_ETH_HW_TSO; 1759 lif->features &= ~IONIC_ETH_HW_TSO_IPV6; 1760 lif->features &= ~IONIC_ETH_HW_TSO_ECN; 1761 } 1762 } 1763 1764 int 1765 ionic_lif_start(struct ionic_lif *lif) 1766 { 1767 uint32_t rx_mode; 1768 uint32_t i; 1769 int err; 1770 1771 err = ionic_lif_rss_setup(lif); 1772 if (err) 1773 return err; 1774 1775 if (!lif->rx_mode) { 1776 IONIC_PRINT(DEBUG, "Setting RX mode on %s", 1777 lif->name); 1778 1779 rx_mode = IONIC_RX_MODE_F_UNICAST; 1780 rx_mode |= IONIC_RX_MODE_F_MULTICAST; 1781 rx_mode |= IONIC_RX_MODE_F_BROADCAST; 1782 1783 ionic_set_rx_mode(lif, rx_mode); 1784 } 1785 1786 IONIC_PRINT(DEBUG, "Starting %u RX queues and %u TX queues " 1787 "on port %u", 1788 lif->nrxqcqs, lif->ntxqcqs, lif->port_id); 1789 1790 for (i = 0; i < lif->nrxqcqs; i++) { 1791 struct ionic_qcq *rxq = lif->rxqcqs[i]; 1792 if (!(rxq->flags & IONIC_QCQ_F_DEFERRED)) { 1793 err = ionic_dev_rx_queue_start(lif->eth_dev, i); 1794 1795 if (err) 1796 return err; 1797 } 1798 } 1799 1800 for (i = 0; i < lif->ntxqcqs; i++) { 1801 struct ionic_qcq *txq = lif->txqcqs[i]; 1802 if (!(txq->flags & IONIC_QCQ_F_DEFERRED)) { 1803 err = ionic_dev_tx_queue_start(lif->eth_dev, i); 1804 1805 if (err) 1806 return err; 1807 } 1808 } 1809 1810 /* Carrier ON here */ 1811 lif->state |= IONIC_LIF_F_UP; 1812 1813 ionic_link_status_check(lif); 1814 1815 return 0; 1816 } 1817 1818 int 1819 ionic_lif_identify(struct ionic_adapter *adapter) 1820 { 1821 struct ionic_dev *idev = &adapter->idev; 1822 struct ionic_identity *ident = &adapter->ident; 1823 union ionic_lif_config *cfg = &ident->lif.eth.config; 1824 uint32_t lif_words = RTE_DIM(ident->lif.words); 1825 uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data); 1826 uint32_t i, nwords; 1827 int err; 1828 1829 ionic_dev_cmd_lif_identify(idev, IONIC_LIF_TYPE_CLASSIC, 1830 IONIC_IDENTITY_VERSION_1); 1831 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 1832 if (err) 1833 return (err); 1834 1835 nwords = RTE_MIN(lif_words, cmd_words); 1836 for (i = 0; i < nwords; i++) 1837 ident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]); 1838 1839 IONIC_PRINT(INFO, "capabilities 0x%" PRIx64 " ", 1840 rte_le_to_cpu_64(ident->lif.capabilities)); 1841 1842 IONIC_PRINT(INFO, "eth.max_ucast_filters 0x%" PRIx32 " ", 1843 rte_le_to_cpu_32(ident->lif.eth.max_ucast_filters)); 1844 IONIC_PRINT(INFO, "eth.max_mcast_filters 0x%" PRIx32 " ", 1845 rte_le_to_cpu_32(ident->lif.eth.max_mcast_filters)); 1846 1847 IONIC_PRINT(INFO, "eth.features 0x%" PRIx64 " ", 1848 rte_le_to_cpu_64(cfg->features)); 1849 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%" PRIx32 " ", 1850 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_ADMINQ])); 1851 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%" PRIx32 " ", 1852 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_NOTIFYQ])); 1853 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_RXQ] 0x%" PRIx32 " ", 1854 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ])); 1855 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_TXQ] 0x%" PRIx32 " ", 1856 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ])); 1857 1858 return 0; 1859 } 1860 1861 int 1862 ionic_lifs_size(struct ionic_adapter *adapter) 1863 { 1864 struct ionic_identity *ident = &adapter->ident; 1865 union ionic_lif_config *cfg = &ident->lif.eth.config; 1866 uint32_t nintrs, dev_nintrs = rte_le_to_cpu_32(ident->dev.nintrs); 1867 1868 adapter->max_ntxqs_per_lif = 1869 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); 1870 adapter->max_nrxqs_per_lif = 1871 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); 1872 1873 nintrs = 1 /* notifyq */; 1874 1875 if (nintrs > dev_nintrs) { 1876 IONIC_PRINT(ERR, 1877 "At most %d intr supported, minimum req'd is %u", 1878 dev_nintrs, nintrs); 1879 return -ENOSPC; 1880 } 1881 1882 adapter->nintrs = nintrs; 1883 1884 return 0; 1885 } 1886