1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved. 3 */ 4 5 #include <rte_pci.h> 6 #include <rte_bus_pci.h> 7 #include <rte_ethdev.h> 8 #include <rte_ethdev_driver.h> 9 #include <rte_malloc.h> 10 #include <rte_ethdev_pci.h> 11 12 #include "ionic_logs.h" 13 #include "ionic.h" 14 #include "ionic_dev.h" 15 #include "ionic_mac_api.h" 16 #include "ionic_lif.h" 17 #include "ionic_ethdev.h" 18 #include "ionic_rxtx.h" 19 20 static int eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 21 static int eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev); 22 static int ionic_dev_info_get(struct rte_eth_dev *eth_dev, 23 struct rte_eth_dev_info *dev_info); 24 static int ionic_dev_configure(struct rte_eth_dev *dev); 25 static int ionic_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 26 static int ionic_dev_start(struct rte_eth_dev *dev); 27 static int ionic_dev_stop(struct rte_eth_dev *dev); 28 static int ionic_dev_close(struct rte_eth_dev *dev); 29 static int ionic_dev_set_link_up(struct rte_eth_dev *dev); 30 static int ionic_dev_set_link_down(struct rte_eth_dev *dev); 31 static int ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 32 struct rte_eth_fc_conf *fc_conf); 33 static int ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 34 struct rte_eth_fc_conf *fc_conf); 35 static int ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask); 36 static int ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 37 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 38 static int ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 39 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 40 static int ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 41 struct rte_eth_rss_conf *rss_conf); 42 static int ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 43 struct rte_eth_rss_conf *rss_conf); 44 static int ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 45 struct rte_eth_stats *stats); 46 static int ionic_dev_stats_reset(struct rte_eth_dev *eth_dev); 47 static int ionic_dev_xstats_get(struct rte_eth_dev *dev, 48 struct rte_eth_xstat *xstats, unsigned int n); 49 static int ionic_dev_xstats_get_by_id(struct rte_eth_dev *dev, 50 const uint64_t *ids, uint64_t *values, unsigned int n); 51 static int ionic_dev_xstats_reset(struct rte_eth_dev *dev); 52 static int ionic_dev_xstats_get_names(struct rte_eth_dev *dev, 53 struct rte_eth_xstat_name *xstats_names, unsigned int size); 54 static int ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 55 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, 56 unsigned int limit); 57 static int ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 58 char *fw_version, size_t fw_size); 59 60 static const struct rte_pci_id pci_id_ionic_map[] = { 61 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_PF) }, 62 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_VF) }, 63 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_MGMT) }, 64 { .vendor_id = 0, /* sentinel */ }, 65 }; 66 67 static const struct rte_eth_desc_lim rx_desc_lim = { 68 .nb_max = IONIC_MAX_RING_DESC, 69 .nb_min = IONIC_MIN_RING_DESC, 70 .nb_align = 1, 71 }; 72 73 static const struct rte_eth_desc_lim tx_desc_lim = { 74 .nb_max = IONIC_MAX_RING_DESC, 75 .nb_min = IONIC_MIN_RING_DESC, 76 .nb_align = 1, 77 .nb_seg_max = IONIC_TX_MAX_SG_ELEMS, 78 .nb_mtu_seg_max = IONIC_TX_MAX_SG_ELEMS, 79 }; 80 81 static const struct eth_dev_ops ionic_eth_dev_ops = { 82 .dev_infos_get = ionic_dev_info_get, 83 .dev_configure = ionic_dev_configure, 84 .mtu_set = ionic_dev_mtu_set, 85 .dev_start = ionic_dev_start, 86 .dev_stop = ionic_dev_stop, 87 .dev_close = ionic_dev_close, 88 .link_update = ionic_dev_link_update, 89 .dev_set_link_up = ionic_dev_set_link_up, 90 .dev_set_link_down = ionic_dev_set_link_down, 91 .mac_addr_add = ionic_dev_add_mac, 92 .mac_addr_remove = ionic_dev_remove_mac, 93 .mac_addr_set = ionic_dev_set_mac, 94 .vlan_filter_set = ionic_dev_vlan_filter_set, 95 .promiscuous_enable = ionic_dev_promiscuous_enable, 96 .promiscuous_disable = ionic_dev_promiscuous_disable, 97 .allmulticast_enable = ionic_dev_allmulticast_enable, 98 .allmulticast_disable = ionic_dev_allmulticast_disable, 99 .flow_ctrl_get = ionic_flow_ctrl_get, 100 .flow_ctrl_set = ionic_flow_ctrl_set, 101 .rxq_info_get = ionic_rxq_info_get, 102 .txq_info_get = ionic_txq_info_get, 103 .rx_queue_setup = ionic_dev_rx_queue_setup, 104 .rx_queue_release = ionic_dev_rx_queue_release, 105 .rx_queue_start = ionic_dev_rx_queue_start, 106 .rx_queue_stop = ionic_dev_rx_queue_stop, 107 .tx_queue_setup = ionic_dev_tx_queue_setup, 108 .tx_queue_release = ionic_dev_tx_queue_release, 109 .tx_queue_start = ionic_dev_tx_queue_start, 110 .tx_queue_stop = ionic_dev_tx_queue_stop, 111 .vlan_offload_set = ionic_vlan_offload_set, 112 .reta_update = ionic_dev_rss_reta_update, 113 .reta_query = ionic_dev_rss_reta_query, 114 .rss_hash_conf_get = ionic_dev_rss_hash_conf_get, 115 .rss_hash_update = ionic_dev_rss_hash_update, 116 .stats_get = ionic_dev_stats_get, 117 .stats_reset = ionic_dev_stats_reset, 118 .xstats_get = ionic_dev_xstats_get, 119 .xstats_get_by_id = ionic_dev_xstats_get_by_id, 120 .xstats_reset = ionic_dev_xstats_reset, 121 .xstats_get_names = ionic_dev_xstats_get_names, 122 .xstats_get_names_by_id = ionic_dev_xstats_get_names_by_id, 123 .fw_version_get = ionic_dev_fw_version_get, 124 }; 125 126 struct rte_ionic_xstats_name_off { 127 char name[RTE_ETH_XSTATS_NAME_SIZE]; 128 unsigned int offset; 129 }; 130 131 static const struct rte_ionic_xstats_name_off rte_ionic_xstats_strings[] = { 132 /* RX */ 133 {"rx_ucast_bytes", offsetof(struct ionic_lif_stats, 134 rx_ucast_bytes)}, 135 {"rx_ucast_packets", offsetof(struct ionic_lif_stats, 136 rx_ucast_packets)}, 137 {"rx_mcast_bytes", offsetof(struct ionic_lif_stats, 138 rx_mcast_bytes)}, 139 {"rx_mcast_packets", offsetof(struct ionic_lif_stats, 140 rx_mcast_packets)}, 141 {"rx_bcast_bytes", offsetof(struct ionic_lif_stats, 142 rx_bcast_bytes)}, 143 {"rx_bcast_packets", offsetof(struct ionic_lif_stats, 144 rx_bcast_packets)}, 145 /* RX drops */ 146 {"rx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 147 rx_ucast_drop_bytes)}, 148 {"rx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 149 rx_ucast_drop_packets)}, 150 {"rx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 151 rx_mcast_drop_bytes)}, 152 {"rx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 153 rx_mcast_drop_packets)}, 154 {"rx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 155 rx_bcast_drop_bytes)}, 156 {"rx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 157 rx_bcast_drop_packets)}, 158 {"rx_dma_error", offsetof(struct ionic_lif_stats, 159 rx_dma_error)}, 160 /* TX */ 161 {"tx_ucast_bytes", offsetof(struct ionic_lif_stats, 162 tx_ucast_bytes)}, 163 {"tx_ucast_packets", offsetof(struct ionic_lif_stats, 164 tx_ucast_packets)}, 165 {"tx_mcast_bytes", offsetof(struct ionic_lif_stats, 166 tx_mcast_bytes)}, 167 {"tx_mcast_packets", offsetof(struct ionic_lif_stats, 168 tx_mcast_packets)}, 169 {"tx_bcast_bytes", offsetof(struct ionic_lif_stats, 170 tx_bcast_bytes)}, 171 {"tx_bcast_packets", offsetof(struct ionic_lif_stats, 172 tx_bcast_packets)}, 173 /* TX drops */ 174 {"tx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 175 tx_ucast_drop_bytes)}, 176 {"tx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 177 tx_ucast_drop_packets)}, 178 {"tx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 179 tx_mcast_drop_bytes)}, 180 {"tx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 181 tx_mcast_drop_packets)}, 182 {"tx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 183 tx_bcast_drop_bytes)}, 184 {"tx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 185 tx_bcast_drop_packets)}, 186 {"tx_dma_error", offsetof(struct ionic_lif_stats, 187 tx_dma_error)}, 188 /* Rx Queue/Ring drops */ 189 {"rx_queue_disabled", offsetof(struct ionic_lif_stats, 190 rx_queue_disabled)}, 191 {"rx_queue_empty", offsetof(struct ionic_lif_stats, 192 rx_queue_empty)}, 193 {"rx_queue_error", offsetof(struct ionic_lif_stats, 194 rx_queue_error)}, 195 {"rx_desc_fetch_error", offsetof(struct ionic_lif_stats, 196 rx_desc_fetch_error)}, 197 {"rx_desc_data_error", offsetof(struct ionic_lif_stats, 198 rx_desc_data_error)}, 199 /* Tx Queue/Ring drops */ 200 {"tx_queue_disabled", offsetof(struct ionic_lif_stats, 201 tx_queue_disabled)}, 202 {"tx_queue_error", offsetof(struct ionic_lif_stats, 203 tx_queue_error)}, 204 {"tx_desc_fetch_error", offsetof(struct ionic_lif_stats, 205 tx_desc_fetch_error)}, 206 {"tx_desc_data_error", offsetof(struct ionic_lif_stats, 207 tx_desc_data_error)}, 208 }; 209 210 #define IONIC_NB_HW_STATS (sizeof(rte_ionic_xstats_strings) / \ 211 sizeof(rte_ionic_xstats_strings[0])) 212 213 static int 214 ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 215 char *fw_version, size_t fw_size) 216 { 217 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 218 struct ionic_adapter *adapter = lif->adapter; 219 220 if (fw_version == NULL || fw_size <= 0) 221 return -EINVAL; 222 223 snprintf(fw_version, fw_size, "%s", 224 adapter->fw_version); 225 fw_version[fw_size - 1] = '\0'; 226 227 return 0; 228 } 229 230 /* 231 * Set device link up, enable tx. 232 */ 233 static int 234 ionic_dev_set_link_up(struct rte_eth_dev *eth_dev) 235 { 236 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 237 int err; 238 239 IONIC_PRINT_CALL(); 240 241 err = ionic_lif_start(lif); 242 if (err) 243 IONIC_PRINT(ERR, "Could not start lif to set link up"); 244 245 ionic_dev_link_update(lif->eth_dev, 0); 246 247 return err; 248 } 249 250 /* 251 * Set device link down, disable tx. 252 */ 253 static int 254 ionic_dev_set_link_down(struct rte_eth_dev *eth_dev) 255 { 256 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 257 258 IONIC_PRINT_CALL(); 259 260 ionic_lif_stop(lif); 261 262 ionic_dev_link_update(lif->eth_dev, 0); 263 264 return 0; 265 } 266 267 int 268 ionic_dev_link_update(struct rte_eth_dev *eth_dev, 269 int wait_to_complete __rte_unused) 270 { 271 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 272 struct ionic_adapter *adapter = lif->adapter; 273 struct rte_eth_link link; 274 275 IONIC_PRINT_CALL(); 276 277 /* Initialize */ 278 memset(&link, 0, sizeof(link)); 279 link.link_autoneg = ETH_LINK_AUTONEG; 280 281 if (!adapter->link_up || 282 !(lif->state & IONIC_LIF_F_UP)) { 283 /* Interface is down */ 284 link.link_status = ETH_LINK_DOWN; 285 link.link_duplex = ETH_LINK_HALF_DUPLEX; 286 link.link_speed = ETH_SPEED_NUM_NONE; 287 } else { 288 /* Interface is up */ 289 link.link_status = ETH_LINK_UP; 290 link.link_duplex = ETH_LINK_FULL_DUPLEX; 291 switch (adapter->link_speed) { 292 case 10000: 293 link.link_speed = ETH_SPEED_NUM_10G; 294 break; 295 case 25000: 296 link.link_speed = ETH_SPEED_NUM_25G; 297 break; 298 case 40000: 299 link.link_speed = ETH_SPEED_NUM_40G; 300 break; 301 case 50000: 302 link.link_speed = ETH_SPEED_NUM_50G; 303 break; 304 case 100000: 305 link.link_speed = ETH_SPEED_NUM_100G; 306 break; 307 default: 308 link.link_speed = ETH_SPEED_NUM_NONE; 309 break; 310 } 311 } 312 313 return rte_eth_linkstatus_set(eth_dev, &link); 314 } 315 316 /** 317 * Interrupt handler triggered by NIC for handling 318 * specific interrupt. 319 * 320 * @param param 321 * The address of parameter registered before. 322 * 323 * @return 324 * void 325 */ 326 static void 327 ionic_dev_interrupt_handler(void *param) 328 { 329 struct ionic_adapter *adapter = (struct ionic_adapter *)param; 330 331 IONIC_PRINT(DEBUG, "->"); 332 333 if (adapter->lif) 334 ionic_notifyq_handler(adapter->lif, -1); 335 } 336 337 static int 338 ionic_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 339 { 340 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 341 uint32_t max_frame_size; 342 int err; 343 344 IONIC_PRINT_CALL(); 345 346 /* 347 * Note: mtu check against IONIC_MIN_MTU, IONIC_MAX_MTU 348 * is done by the the API. 349 */ 350 351 /* 352 * Max frame size is MTU + Ethernet header + VLAN + QinQ 353 * (plus ETHER_CRC_LEN if the adapter is able to keep CRC) 354 */ 355 max_frame_size = mtu + RTE_ETHER_HDR_LEN + 4 + 4; 356 357 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len < max_frame_size) 358 return -EINVAL; 359 360 err = ionic_lif_change_mtu(lif, mtu); 361 if (err) 362 return err; 363 364 return 0; 365 } 366 367 static int 368 ionic_dev_info_get(struct rte_eth_dev *eth_dev, 369 struct rte_eth_dev_info *dev_info) 370 { 371 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 372 struct ionic_adapter *adapter = lif->adapter; 373 struct ionic_identity *ident = &adapter->ident; 374 375 IONIC_PRINT_CALL(); 376 377 dev_info->max_rx_queues = (uint16_t) 378 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]; 379 dev_info->max_tx_queues = (uint16_t) 380 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]; 381 /* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */ 382 dev_info->min_rx_bufsize = IONIC_MIN_MTU + RTE_ETHER_HDR_LEN; 383 dev_info->max_rx_pktlen = IONIC_MAX_MTU + RTE_ETHER_HDR_LEN; 384 dev_info->max_mac_addrs = adapter->max_mac_addrs; 385 dev_info->min_mtu = IONIC_MIN_MTU; 386 dev_info->max_mtu = IONIC_MAX_MTU; 387 388 dev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE; 389 dev_info->reta_size = ident->lif.eth.rss_ind_tbl_sz; 390 dev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL; 391 392 dev_info->speed_capa = 393 ETH_LINK_SPEED_10G | 394 ETH_LINK_SPEED_25G | 395 ETH_LINK_SPEED_40G | 396 ETH_LINK_SPEED_50G | 397 ETH_LINK_SPEED_100G; 398 399 /* 400 * Per-queue capabilities 401 * RTE does not support disabling a feature on a queue if it is 402 * enabled globally on the device. Thus the driver does not advertise 403 * capabilities like DEV_TX_OFFLOAD_IPV4_CKSUM as per-queue even 404 * though the driver would be otherwise capable of disabling it on 405 * a per-queue basis. 406 */ 407 408 dev_info->rx_queue_offload_capa = 0; 409 dev_info->tx_queue_offload_capa = 0; 410 411 /* 412 * Per-port capabilities 413 * See ionic_set_features to request and check supported features 414 */ 415 416 dev_info->rx_offload_capa = dev_info->rx_queue_offload_capa | 417 DEV_RX_OFFLOAD_IPV4_CKSUM | 418 DEV_RX_OFFLOAD_UDP_CKSUM | 419 DEV_RX_OFFLOAD_TCP_CKSUM | 420 DEV_RX_OFFLOAD_JUMBO_FRAME | 421 DEV_RX_OFFLOAD_VLAN_FILTER | 422 DEV_RX_OFFLOAD_VLAN_STRIP | 423 DEV_RX_OFFLOAD_SCATTER | 424 DEV_RX_OFFLOAD_RSS_HASH | 425 0; 426 427 dev_info->tx_offload_capa = dev_info->tx_queue_offload_capa | 428 DEV_TX_OFFLOAD_IPV4_CKSUM | 429 DEV_TX_OFFLOAD_UDP_CKSUM | 430 DEV_TX_OFFLOAD_TCP_CKSUM | 431 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 432 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | 433 DEV_TX_OFFLOAD_MULTI_SEGS | 434 DEV_TX_OFFLOAD_TCP_TSO | 435 DEV_TX_OFFLOAD_VLAN_INSERT | 436 0; 437 438 dev_info->rx_desc_lim = rx_desc_lim; 439 dev_info->tx_desc_lim = tx_desc_lim; 440 441 /* Driver-preferred Rx/Tx parameters */ 442 dev_info->default_rxportconf.burst_size = 32; 443 dev_info->default_txportconf.burst_size = 32; 444 dev_info->default_rxportconf.nb_queues = 1; 445 dev_info->default_txportconf.nb_queues = 1; 446 dev_info->default_rxportconf.ring_size = IONIC_DEF_TXRX_DESC; 447 dev_info->default_txportconf.ring_size = IONIC_DEF_TXRX_DESC; 448 449 dev_info->default_rxconf = (struct rte_eth_rxconf) { 450 /* Packets are always dropped if no desc are available */ 451 .rx_drop_en = 1, 452 }; 453 454 return 0; 455 } 456 457 static int 458 ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 459 struct rte_eth_fc_conf *fc_conf) 460 { 461 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 462 struct ionic_adapter *adapter = lif->adapter; 463 struct ionic_dev *idev = &adapter->idev; 464 465 if (idev->port_info) { 466 /* Flow control autoneg not supported */ 467 fc_conf->autoneg = 0; 468 469 if (idev->port_info->config.pause_type) 470 fc_conf->mode = RTE_FC_FULL; 471 else 472 fc_conf->mode = RTE_FC_NONE; 473 } 474 475 return 0; 476 } 477 478 static int 479 ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 480 struct rte_eth_fc_conf *fc_conf) 481 { 482 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 483 struct ionic_adapter *adapter = lif->adapter; 484 struct ionic_dev *idev = &adapter->idev; 485 uint8_t pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 486 int err; 487 488 if (fc_conf->autoneg) { 489 IONIC_PRINT(WARNING, "Flow control autoneg not supported"); 490 return -ENOTSUP; 491 } 492 493 switch (fc_conf->mode) { 494 case RTE_FC_NONE: 495 pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 496 break; 497 case RTE_FC_FULL: 498 pause_type = IONIC_PORT_PAUSE_TYPE_LINK; 499 break; 500 case RTE_FC_RX_PAUSE: 501 case RTE_FC_TX_PAUSE: 502 return -ENOTSUP; 503 } 504 505 ionic_dev_cmd_port_pause(idev, pause_type); 506 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 507 if (err) 508 IONIC_PRINT(WARNING, "Failed to configure flow control"); 509 510 return err; 511 } 512 513 static int 514 ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 515 { 516 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 517 518 ionic_lif_configure_vlan_offload(lif, mask); 519 520 ionic_lif_set_features(lif); 521 522 return 0; 523 } 524 525 static int 526 ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 527 struct rte_eth_rss_reta_entry64 *reta_conf, 528 uint16_t reta_size) 529 { 530 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 531 struct ionic_adapter *adapter = lif->adapter; 532 struct ionic_identity *ident = &adapter->ident; 533 uint32_t i, j, index, num; 534 535 IONIC_PRINT_CALL(); 536 537 if (!lif->rss_ind_tbl) { 538 IONIC_PRINT(ERR, "RSS RETA not initialized, " 539 "can't update the table"); 540 return -EINVAL; 541 } 542 543 if (reta_size != ident->lif.eth.rss_ind_tbl_sz) { 544 IONIC_PRINT(ERR, "The size of hash lookup table configured " 545 "(%d) does not match the number hardware can support " 546 "(%d)", 547 reta_size, ident->lif.eth.rss_ind_tbl_sz); 548 return -EINVAL; 549 } 550 551 num = lif->adapter->ident.lif.eth.rss_ind_tbl_sz / RTE_RETA_GROUP_SIZE; 552 553 for (i = 0; i < num; i++) { 554 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) { 555 if (reta_conf[i].mask & ((uint64_t)1 << j)) { 556 index = (i * RTE_RETA_GROUP_SIZE) + j; 557 lif->rss_ind_tbl[index] = reta_conf[i].reta[j]; 558 } 559 } 560 } 561 562 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 563 } 564 565 static int 566 ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 567 struct rte_eth_rss_reta_entry64 *reta_conf, 568 uint16_t reta_size) 569 { 570 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 571 struct ionic_adapter *adapter = lif->adapter; 572 struct ionic_identity *ident = &adapter->ident; 573 int i, num; 574 575 IONIC_PRINT_CALL(); 576 577 if (reta_size != ident->lif.eth.rss_ind_tbl_sz) { 578 IONIC_PRINT(ERR, "The size of hash lookup table configured " 579 "(%d) does not match the number hardware can support " 580 "(%d)", 581 reta_size, ident->lif.eth.rss_ind_tbl_sz); 582 return -EINVAL; 583 } 584 585 if (!lif->rss_ind_tbl) { 586 IONIC_PRINT(ERR, "RSS RETA has not been built yet"); 587 return -EINVAL; 588 } 589 590 num = reta_size / RTE_RETA_GROUP_SIZE; 591 592 for (i = 0; i < num; i++) { 593 memcpy(reta_conf->reta, 594 &lif->rss_ind_tbl[i * RTE_RETA_GROUP_SIZE], 595 RTE_RETA_GROUP_SIZE); 596 reta_conf++; 597 } 598 599 return 0; 600 } 601 602 static int 603 ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 604 struct rte_eth_rss_conf *rss_conf) 605 { 606 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 607 uint64_t rss_hf = 0; 608 609 IONIC_PRINT_CALL(); 610 611 if (!lif->rss_ind_tbl) { 612 IONIC_PRINT(NOTICE, "RSS not enabled"); 613 return 0; 614 } 615 616 /* Get key value (if not null, rss_key is 40-byte) */ 617 if (rss_conf->rss_key != NULL && 618 rss_conf->rss_key_len >= IONIC_RSS_HASH_KEY_SIZE) 619 memcpy(rss_conf->rss_key, lif->rss_hash_key, 620 IONIC_RSS_HASH_KEY_SIZE); 621 622 if (lif->rss_types & IONIC_RSS_TYPE_IPV4) 623 rss_hf |= ETH_RSS_IPV4; 624 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_TCP) 625 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 626 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_UDP) 627 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 628 if (lif->rss_types & IONIC_RSS_TYPE_IPV6) 629 rss_hf |= ETH_RSS_IPV6; 630 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_TCP) 631 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 632 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_UDP) 633 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 634 635 rss_conf->rss_hf = rss_hf; 636 637 return 0; 638 } 639 640 static int 641 ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 642 struct rte_eth_rss_conf *rss_conf) 643 { 644 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 645 uint32_t rss_types = 0; 646 uint8_t *key = NULL; 647 648 IONIC_PRINT_CALL(); 649 650 if (rss_conf->rss_key) 651 key = rss_conf->rss_key; 652 653 if ((rss_conf->rss_hf & IONIC_ETH_RSS_OFFLOAD_ALL) == 0) { 654 /* 655 * Can't disable rss through hash flags, 656 * if it is enabled by default during init 657 */ 658 if (lif->rss_ind_tbl) 659 return -EINVAL; 660 } else { 661 /* Can't enable rss if disabled by default during init */ 662 if (!lif->rss_ind_tbl) 663 return -EINVAL; 664 665 if (rss_conf->rss_hf & ETH_RSS_IPV4) 666 rss_types |= IONIC_RSS_TYPE_IPV4; 667 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) 668 rss_types |= IONIC_RSS_TYPE_IPV4_TCP; 669 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) 670 rss_types |= IONIC_RSS_TYPE_IPV4_UDP; 671 if (rss_conf->rss_hf & ETH_RSS_IPV6) 672 rss_types |= IONIC_RSS_TYPE_IPV6; 673 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) 674 rss_types |= IONIC_RSS_TYPE_IPV6_TCP; 675 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) 676 rss_types |= IONIC_RSS_TYPE_IPV6_UDP; 677 678 ionic_lif_rss_config(lif, rss_types, key, NULL); 679 } 680 681 return 0; 682 } 683 684 static int 685 ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 686 struct rte_eth_stats *stats) 687 { 688 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 689 690 ionic_lif_get_stats(lif, stats); 691 692 return 0; 693 } 694 695 static int 696 ionic_dev_stats_reset(struct rte_eth_dev *eth_dev) 697 { 698 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 699 700 IONIC_PRINT_CALL(); 701 702 ionic_lif_reset_stats(lif); 703 704 return 0; 705 } 706 707 static int 708 ionic_dev_xstats_get_names(__rte_unused struct rte_eth_dev *eth_dev, 709 struct rte_eth_xstat_name *xstats_names, 710 __rte_unused unsigned int size) 711 { 712 unsigned int i; 713 714 if (xstats_names != NULL) { 715 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 716 snprintf(xstats_names[i].name, 717 sizeof(xstats_names[i].name), 718 "%s", rte_ionic_xstats_strings[i].name); 719 } 720 } 721 722 return IONIC_NB_HW_STATS; 723 } 724 725 static int 726 ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *eth_dev, 727 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, 728 unsigned int limit) 729 { 730 struct rte_eth_xstat_name xstats_names_copy[IONIC_NB_HW_STATS]; 731 uint16_t i; 732 733 if (!ids) { 734 if (xstats_names != NULL) { 735 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 736 snprintf(xstats_names[i].name, 737 sizeof(xstats_names[i].name), 738 "%s", rte_ionic_xstats_strings[i].name); 739 } 740 } 741 742 return IONIC_NB_HW_STATS; 743 } 744 745 ionic_dev_xstats_get_names_by_id(eth_dev, xstats_names_copy, NULL, 746 IONIC_NB_HW_STATS); 747 748 for (i = 0; i < limit; i++) { 749 if (ids[i] >= IONIC_NB_HW_STATS) { 750 IONIC_PRINT(ERR, "id value isn't valid"); 751 return -1; 752 } 753 754 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 755 } 756 757 return limit; 758 } 759 760 static int 761 ionic_dev_xstats_get(struct rte_eth_dev *eth_dev, struct rte_eth_xstat *xstats, 762 unsigned int n) 763 { 764 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 765 struct ionic_lif_stats hw_stats; 766 uint16_t i; 767 768 if (n < IONIC_NB_HW_STATS) 769 return IONIC_NB_HW_STATS; 770 771 ionic_lif_get_hw_stats(lif, &hw_stats); 772 773 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 774 xstats[i].value = *(uint64_t *)(((char *)&hw_stats) + 775 rte_ionic_xstats_strings[i].offset); 776 xstats[i].id = i; 777 } 778 779 return IONIC_NB_HW_STATS; 780 } 781 782 static int 783 ionic_dev_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids, 784 uint64_t *values, unsigned int n) 785 { 786 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 787 struct ionic_lif_stats hw_stats; 788 uint64_t values_copy[IONIC_NB_HW_STATS]; 789 uint16_t i; 790 791 if (!ids) { 792 if (!ids && n < IONIC_NB_HW_STATS) 793 return IONIC_NB_HW_STATS; 794 795 ionic_lif_get_hw_stats(lif, &hw_stats); 796 797 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 798 values[i] = *(uint64_t *)(((char *)&hw_stats) + 799 rte_ionic_xstats_strings[i].offset); 800 } 801 802 return IONIC_NB_HW_STATS; 803 } 804 805 ionic_dev_xstats_get_by_id(eth_dev, NULL, values_copy, 806 IONIC_NB_HW_STATS); 807 808 for (i = 0; i < n; i++) { 809 if (ids[i] >= IONIC_NB_HW_STATS) { 810 IONIC_PRINT(ERR, "id value isn't valid"); 811 return -1; 812 } 813 814 values[i] = values_copy[ids[i]]; 815 } 816 817 return n; 818 } 819 820 static int 821 ionic_dev_xstats_reset(struct rte_eth_dev *eth_dev) 822 { 823 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 824 825 ionic_lif_reset_hw_stats(lif); 826 827 return 0; 828 } 829 830 static int 831 ionic_dev_configure(struct rte_eth_dev *eth_dev) 832 { 833 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 834 835 IONIC_PRINT_CALL(); 836 837 ionic_lif_configure(lif); 838 839 ionic_lif_set_features(lif); 840 841 return 0; 842 } 843 844 static inline uint32_t 845 ionic_parse_link_speeds(uint16_t link_speeds) 846 { 847 if (link_speeds & ETH_LINK_SPEED_100G) 848 return 100000; 849 else if (link_speeds & ETH_LINK_SPEED_50G) 850 return 50000; 851 else if (link_speeds & ETH_LINK_SPEED_40G) 852 return 40000; 853 else if (link_speeds & ETH_LINK_SPEED_25G) 854 return 25000; 855 else if (link_speeds & ETH_LINK_SPEED_10G) 856 return 10000; 857 else 858 return 0; 859 } 860 861 /* 862 * Configure device link speed and setup link. 863 * It returns 0 on success. 864 */ 865 static int 866 ionic_dev_start(struct rte_eth_dev *eth_dev) 867 { 868 struct rte_eth_conf *dev_conf = ð_dev->data->dev_conf; 869 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 870 struct ionic_adapter *adapter = lif->adapter; 871 struct ionic_dev *idev = &adapter->idev; 872 uint32_t allowed_speeds; 873 int err; 874 875 IONIC_PRINT_CALL(); 876 877 allowed_speeds = 878 ETH_LINK_SPEED_FIXED | 879 ETH_LINK_SPEED_10G | 880 ETH_LINK_SPEED_25G | 881 ETH_LINK_SPEED_40G | 882 ETH_LINK_SPEED_50G | 883 ETH_LINK_SPEED_100G; 884 885 if (dev_conf->link_speeds & ~allowed_speeds) { 886 IONIC_PRINT(ERR, "Invalid link setting"); 887 return -EINVAL; 888 } 889 890 if (dev_conf->lpbk_mode) 891 IONIC_PRINT(WARNING, "Loopback mode not supported"); 892 893 err = ionic_lif_start(lif); 894 if (err) { 895 IONIC_PRINT(ERR, "Cannot start LIF: %d", err); 896 return err; 897 } 898 899 if (eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) { 900 uint32_t speed = ionic_parse_link_speeds(dev_conf->link_speeds); 901 902 if (speed) 903 ionic_dev_cmd_port_speed(idev, speed); 904 } 905 906 ionic_dev_link_update(eth_dev, 0); 907 908 return 0; 909 } 910 911 /* 912 * Stop device: disable rx and tx functions to allow for reconfiguring. 913 */ 914 static int 915 ionic_dev_stop(struct rte_eth_dev *eth_dev) 916 { 917 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 918 919 IONIC_PRINT_CALL(); 920 921 ionic_lif_stop(lif); 922 923 return 0; 924 } 925 926 static void ionic_unconfigure_intr(struct ionic_adapter *adapter); 927 928 /* 929 * Reset and stop device. 930 */ 931 static int 932 ionic_dev_close(struct rte_eth_dev *eth_dev) 933 { 934 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 935 struct ionic_adapter *adapter = lif->adapter; 936 937 IONIC_PRINT_CALL(); 938 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 939 return 0; 940 941 ionic_lif_stop(lif); 942 943 ionic_lif_free_queues(lif); 944 945 IONIC_PRINT(NOTICE, "Removing device %s", eth_dev->device->name); 946 ionic_unconfigure_intr(adapter); 947 948 rte_eth_dev_destroy(eth_dev, eth_ionic_dev_uninit); 949 950 ionic_port_reset(adapter); 951 ionic_reset(adapter); 952 953 rte_free(adapter); 954 955 return 0; 956 } 957 958 static int 959 eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params) 960 { 961 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 962 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 963 struct ionic_adapter *adapter = (struct ionic_adapter *)init_params; 964 int err; 965 966 IONIC_PRINT_CALL(); 967 968 eth_dev->dev_ops = &ionic_eth_dev_ops; 969 eth_dev->rx_pkt_burst = &ionic_recv_pkts; 970 eth_dev->tx_pkt_burst = &ionic_xmit_pkts; 971 eth_dev->tx_pkt_prepare = &ionic_prep_pkts; 972 973 /* Multi-process not supported, primary does initialization anyway */ 974 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 975 return 0; 976 977 rte_eth_copy_pci_info(eth_dev, pci_dev); 978 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 979 980 lif->eth_dev = eth_dev; 981 lif->adapter = adapter; 982 adapter->lif = lif; 983 984 IONIC_PRINT(DEBUG, "Up to %u MAC addresses supported", 985 adapter->max_mac_addrs); 986 987 /* Allocate memory for storing MAC addresses */ 988 eth_dev->data->mac_addrs = rte_zmalloc("ionic", 989 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs, 0); 990 991 if (eth_dev->data->mac_addrs == NULL) { 992 IONIC_PRINT(ERR, "Failed to allocate %u bytes needed to " 993 "store MAC addresses", 994 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs); 995 err = -ENOMEM; 996 goto err; 997 } 998 999 err = ionic_lif_alloc(lif); 1000 if (err) { 1001 IONIC_PRINT(ERR, "Cannot allocate LIFs: %d, aborting", 1002 err); 1003 goto err; 1004 } 1005 1006 err = ionic_lif_init(lif); 1007 if (err) { 1008 IONIC_PRINT(ERR, "Cannot init LIFs: %d, aborting", err); 1009 goto err_free_lif; 1010 } 1011 1012 /* Copy the MAC address */ 1013 rte_ether_addr_copy((struct rte_ether_addr *)lif->mac_addr, 1014 ð_dev->data->mac_addrs[0]); 1015 1016 IONIC_PRINT(DEBUG, "Port %u initialized", eth_dev->data->port_id); 1017 1018 return 0; 1019 1020 err_free_lif: 1021 ionic_lif_free(lif); 1022 err: 1023 return err; 1024 } 1025 1026 static int 1027 eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev) 1028 { 1029 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 1030 struct ionic_adapter *adapter = lif->adapter; 1031 1032 IONIC_PRINT_CALL(); 1033 1034 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1035 return 0; 1036 1037 adapter->lif = NULL; 1038 1039 ionic_lif_deinit(lif); 1040 ionic_lif_free(lif); 1041 1042 if (!(lif->state & IONIC_LIF_F_FW_RESET)) 1043 ionic_lif_reset(lif); 1044 1045 return 0; 1046 } 1047 1048 static int 1049 ionic_configure_intr(struct ionic_adapter *adapter) 1050 { 1051 struct rte_pci_device *pci_dev = adapter->pci_dev; 1052 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1053 int err; 1054 1055 IONIC_PRINT(DEBUG, "Configuring %u intrs", adapter->nintrs); 1056 1057 if (rte_intr_efd_enable(intr_handle, adapter->nintrs)) { 1058 IONIC_PRINT(ERR, "Fail to create eventfd"); 1059 return -1; 1060 } 1061 1062 if (rte_intr_dp_is_en(intr_handle)) 1063 IONIC_PRINT(DEBUG, 1064 "Packet I/O interrupt on datapath is enabled"); 1065 1066 if (!intr_handle->intr_vec) { 1067 intr_handle->intr_vec = rte_zmalloc("intr_vec", 1068 adapter->nintrs * sizeof(int), 0); 1069 1070 if (!intr_handle->intr_vec) { 1071 IONIC_PRINT(ERR, "Failed to allocate %u vectors", 1072 adapter->nintrs); 1073 return -ENOMEM; 1074 } 1075 } 1076 1077 err = rte_intr_callback_register(intr_handle, 1078 ionic_dev_interrupt_handler, 1079 adapter); 1080 1081 if (err) { 1082 IONIC_PRINT(ERR, 1083 "Failure registering interrupts handler (%d)", 1084 err); 1085 return err; 1086 } 1087 1088 /* enable intr mapping */ 1089 err = rte_intr_enable(intr_handle); 1090 1091 if (err) { 1092 IONIC_PRINT(ERR, "Failure enabling interrupts (%d)", err); 1093 return err; 1094 } 1095 1096 return 0; 1097 } 1098 1099 static void 1100 ionic_unconfigure_intr(struct ionic_adapter *adapter) 1101 { 1102 struct rte_pci_device *pci_dev = adapter->pci_dev; 1103 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1104 1105 rte_intr_disable(intr_handle); 1106 1107 rte_intr_callback_unregister(intr_handle, 1108 ionic_dev_interrupt_handler, 1109 adapter); 1110 } 1111 1112 static int 1113 eth_ionic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1114 struct rte_pci_device *pci_dev) 1115 { 1116 char name[RTE_ETH_NAME_MAX_LEN]; 1117 struct rte_mem_resource *resource; 1118 struct ionic_adapter *adapter; 1119 struct ionic_hw *hw; 1120 unsigned long i; 1121 int err; 1122 1123 /* Check structs (trigger error at compilation time) */ 1124 ionic_struct_size_checks(); 1125 1126 /* Multi-process not supported */ 1127 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1128 err = -EPERM; 1129 goto err; 1130 } 1131 1132 IONIC_PRINT(DEBUG, "Initializing device %s", 1133 pci_dev->device.name); 1134 1135 adapter = rte_zmalloc("ionic", sizeof(*adapter), 0); 1136 if (!adapter) { 1137 IONIC_PRINT(ERR, "OOM"); 1138 err = -ENOMEM; 1139 goto err; 1140 } 1141 1142 adapter->pci_dev = pci_dev; 1143 hw = &adapter->hw; 1144 1145 hw->device_id = pci_dev->id.device_id; 1146 hw->vendor_id = pci_dev->id.vendor_id; 1147 1148 err = ionic_init_mac(hw); 1149 if (err != 0) { 1150 IONIC_PRINT(ERR, "Mac init failed: %d", err); 1151 err = -EIO; 1152 goto err_free_adapter; 1153 } 1154 1155 adapter->num_bars = 0; 1156 for (i = 0; i < PCI_MAX_RESOURCE && i < IONIC_BARS_MAX; i++) { 1157 resource = &pci_dev->mem_resource[i]; 1158 if (resource->phys_addr == 0 || resource->len == 0) 1159 continue; 1160 adapter->bars[adapter->num_bars].vaddr = resource->addr; 1161 adapter->bars[adapter->num_bars].bus_addr = resource->phys_addr; 1162 adapter->bars[adapter->num_bars].len = resource->len; 1163 adapter->num_bars++; 1164 } 1165 1166 /* Discover ionic dev resources */ 1167 1168 err = ionic_setup(adapter); 1169 if (err) { 1170 IONIC_PRINT(ERR, "Cannot setup device: %d, aborting", err); 1171 goto err_free_adapter; 1172 } 1173 1174 err = ionic_identify(adapter); 1175 if (err) { 1176 IONIC_PRINT(ERR, "Cannot identify device: %d, aborting", 1177 err); 1178 goto err_free_adapter; 1179 } 1180 1181 err = ionic_init(adapter); 1182 if (err) { 1183 IONIC_PRINT(ERR, "Cannot init device: %d, aborting", err); 1184 goto err_free_adapter; 1185 } 1186 1187 /* Configure the ports */ 1188 err = ionic_port_identify(adapter); 1189 if (err) { 1190 IONIC_PRINT(ERR, "Cannot identify port: %d, aborting", 1191 err); 1192 goto err_free_adapter; 1193 } 1194 1195 err = ionic_port_init(adapter); 1196 if (err) { 1197 IONIC_PRINT(ERR, "Cannot init port: %d, aborting", err); 1198 goto err_free_adapter; 1199 } 1200 1201 /* Configure LIFs */ 1202 err = ionic_lif_identify(adapter); 1203 if (err) { 1204 IONIC_PRINT(ERR, "Cannot identify lif: %d, aborting", err); 1205 goto err_free_adapter; 1206 } 1207 1208 /* Allocate and init LIFs */ 1209 err = ionic_lifs_size(adapter); 1210 if (err) { 1211 IONIC_PRINT(ERR, "Cannot size LIFs: %d, aborting", err); 1212 goto err_free_adapter; 1213 } 1214 1215 adapter->max_mac_addrs = adapter->ident.lif.eth.max_ucast_filters; 1216 1217 if (adapter->ident.dev.nlifs != 1) { 1218 IONIC_PRINT(ERR, "Unexpected request for %d LIFs", 1219 adapter->ident.dev.nlifs); 1220 goto err_free_adapter; 1221 } 1222 1223 snprintf(name, sizeof(name), "%s_lif", pci_dev->device.name); 1224 err = rte_eth_dev_create(&pci_dev->device, 1225 name, sizeof(struct ionic_lif), 1226 NULL, NULL, eth_ionic_dev_init, adapter); 1227 if (err) { 1228 IONIC_PRINT(ERR, "Cannot create eth device for %s", name); 1229 goto err_free_adapter; 1230 } 1231 1232 err = ionic_configure_intr(adapter); 1233 1234 if (err) { 1235 IONIC_PRINT(ERR, "Failed to configure interrupts"); 1236 goto err_free_adapter; 1237 } 1238 1239 return 0; 1240 1241 err_free_adapter: 1242 rte_free(adapter); 1243 err: 1244 return err; 1245 } 1246 1247 static int 1248 eth_ionic_pci_remove(struct rte_pci_device *pci_dev) 1249 { 1250 char name[RTE_ETH_NAME_MAX_LEN]; 1251 struct rte_eth_dev *eth_dev; 1252 1253 /* Adapter lookup is using the eth_dev name */ 1254 snprintf(name, sizeof(name), "%s_lif", pci_dev->device.name); 1255 1256 eth_dev = rte_eth_dev_allocated(name); 1257 if (eth_dev) 1258 ionic_dev_close(eth_dev); 1259 else 1260 IONIC_PRINT(DEBUG, "Cannot find device %s", 1261 pci_dev->device.name); 1262 1263 return 0; 1264 } 1265 1266 static struct rte_pci_driver rte_ionic_pmd = { 1267 .id_table = pci_id_ionic_map, 1268 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1269 .probe = eth_ionic_pci_probe, 1270 .remove = eth_ionic_pci_remove, 1271 }; 1272 1273 RTE_PMD_REGISTER_PCI(net_ionic, rte_ionic_pmd); 1274 RTE_PMD_REGISTER_PCI_TABLE(net_ionic, pci_id_ionic_map); 1275 RTE_PMD_REGISTER_KMOD_DEP(net_ionic, "* igb_uio | uio_pci_generic | vfio-pci"); 1276 RTE_LOG_REGISTER(ionic_logtype, pmd.net.ionic, NOTICE); 1277