1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved. 3 */ 4 5 #include <rte_pci.h> 6 #include <rte_bus_pci.h> 7 #include <rte_ethdev.h> 8 #include <rte_ethdev_driver.h> 9 #include <rte_malloc.h> 10 #include <rte_ethdev_pci.h> 11 12 #include "ionic_logs.h" 13 #include "ionic.h" 14 #include "ionic_dev.h" 15 #include "ionic_mac_api.h" 16 #include "ionic_lif.h" 17 #include "ionic_ethdev.h" 18 #include "ionic_rxtx.h" 19 20 static int eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 21 static int eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev); 22 static int ionic_dev_info_get(struct rte_eth_dev *eth_dev, 23 struct rte_eth_dev_info *dev_info); 24 static int ionic_dev_configure(struct rte_eth_dev *dev); 25 static int ionic_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 26 static int ionic_dev_start(struct rte_eth_dev *dev); 27 static int ionic_dev_stop(struct rte_eth_dev *dev); 28 static int ionic_dev_close(struct rte_eth_dev *dev); 29 static int ionic_dev_set_link_up(struct rte_eth_dev *dev); 30 static int ionic_dev_set_link_down(struct rte_eth_dev *dev); 31 static int ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 32 struct rte_eth_fc_conf *fc_conf); 33 static int ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 34 struct rte_eth_fc_conf *fc_conf); 35 static int ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask); 36 static int ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 37 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 38 static int ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 39 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 40 static int ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 41 struct rte_eth_rss_conf *rss_conf); 42 static int ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 43 struct rte_eth_rss_conf *rss_conf); 44 static int ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 45 struct rte_eth_stats *stats); 46 static int ionic_dev_stats_reset(struct rte_eth_dev *eth_dev); 47 static int ionic_dev_xstats_get(struct rte_eth_dev *dev, 48 struct rte_eth_xstat *xstats, unsigned int n); 49 static int ionic_dev_xstats_get_by_id(struct rte_eth_dev *dev, 50 const uint64_t *ids, uint64_t *values, unsigned int n); 51 static int ionic_dev_xstats_reset(struct rte_eth_dev *dev); 52 static int ionic_dev_xstats_get_names(struct rte_eth_dev *dev, 53 struct rte_eth_xstat_name *xstats_names, unsigned int size); 54 static int ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 55 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, 56 unsigned int limit); 57 static int ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 58 char *fw_version, size_t fw_size); 59 60 static const struct rte_pci_id pci_id_ionic_map[] = { 61 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_PF) }, 62 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_VF) }, 63 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_MGMT) }, 64 { .vendor_id = 0, /* sentinel */ }, 65 }; 66 67 static const struct rte_eth_desc_lim rx_desc_lim = { 68 .nb_max = IONIC_MAX_RING_DESC, 69 .nb_min = IONIC_MIN_RING_DESC, 70 .nb_align = 1, 71 }; 72 73 static const struct rte_eth_desc_lim tx_desc_lim = { 74 .nb_max = IONIC_MAX_RING_DESC, 75 .nb_min = IONIC_MIN_RING_DESC, 76 .nb_align = 1, 77 .nb_seg_max = IONIC_TX_MAX_SG_ELEMS, 78 .nb_mtu_seg_max = IONIC_TX_MAX_SG_ELEMS, 79 }; 80 81 static const struct eth_dev_ops ionic_eth_dev_ops = { 82 .dev_infos_get = ionic_dev_info_get, 83 .dev_configure = ionic_dev_configure, 84 .mtu_set = ionic_dev_mtu_set, 85 .dev_start = ionic_dev_start, 86 .dev_stop = ionic_dev_stop, 87 .dev_close = ionic_dev_close, 88 .link_update = ionic_dev_link_update, 89 .dev_set_link_up = ionic_dev_set_link_up, 90 .dev_set_link_down = ionic_dev_set_link_down, 91 .mac_addr_add = ionic_dev_add_mac, 92 .mac_addr_remove = ionic_dev_remove_mac, 93 .mac_addr_set = ionic_dev_set_mac, 94 .vlan_filter_set = ionic_dev_vlan_filter_set, 95 .promiscuous_enable = ionic_dev_promiscuous_enable, 96 .promiscuous_disable = ionic_dev_promiscuous_disable, 97 .allmulticast_enable = ionic_dev_allmulticast_enable, 98 .allmulticast_disable = ionic_dev_allmulticast_disable, 99 .flow_ctrl_get = ionic_flow_ctrl_get, 100 .flow_ctrl_set = ionic_flow_ctrl_set, 101 .rxq_info_get = ionic_rxq_info_get, 102 .txq_info_get = ionic_txq_info_get, 103 .rx_queue_setup = ionic_dev_rx_queue_setup, 104 .rx_queue_release = ionic_dev_rx_queue_release, 105 .rx_queue_start = ionic_dev_rx_queue_start, 106 .rx_queue_stop = ionic_dev_rx_queue_stop, 107 .tx_queue_setup = ionic_dev_tx_queue_setup, 108 .tx_queue_release = ionic_dev_tx_queue_release, 109 .tx_queue_start = ionic_dev_tx_queue_start, 110 .tx_queue_stop = ionic_dev_tx_queue_stop, 111 .vlan_offload_set = ionic_vlan_offload_set, 112 .reta_update = ionic_dev_rss_reta_update, 113 .reta_query = ionic_dev_rss_reta_query, 114 .rss_hash_conf_get = ionic_dev_rss_hash_conf_get, 115 .rss_hash_update = ionic_dev_rss_hash_update, 116 .stats_get = ionic_dev_stats_get, 117 .stats_reset = ionic_dev_stats_reset, 118 .xstats_get = ionic_dev_xstats_get, 119 .xstats_get_by_id = ionic_dev_xstats_get_by_id, 120 .xstats_reset = ionic_dev_xstats_reset, 121 .xstats_get_names = ionic_dev_xstats_get_names, 122 .xstats_get_names_by_id = ionic_dev_xstats_get_names_by_id, 123 .fw_version_get = ionic_dev_fw_version_get, 124 }; 125 126 struct rte_ionic_xstats_name_off { 127 char name[RTE_ETH_XSTATS_NAME_SIZE]; 128 unsigned int offset; 129 }; 130 131 static const struct rte_ionic_xstats_name_off rte_ionic_xstats_strings[] = { 132 /* RX */ 133 {"rx_ucast_bytes", offsetof(struct ionic_lif_stats, 134 rx_ucast_bytes)}, 135 {"rx_ucast_packets", offsetof(struct ionic_lif_stats, 136 rx_ucast_packets)}, 137 {"rx_mcast_bytes", offsetof(struct ionic_lif_stats, 138 rx_mcast_bytes)}, 139 {"rx_mcast_packets", offsetof(struct ionic_lif_stats, 140 rx_mcast_packets)}, 141 {"rx_bcast_bytes", offsetof(struct ionic_lif_stats, 142 rx_bcast_bytes)}, 143 {"rx_bcast_packets", offsetof(struct ionic_lif_stats, 144 rx_bcast_packets)}, 145 /* RX drops */ 146 {"rx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 147 rx_ucast_drop_bytes)}, 148 {"rx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 149 rx_ucast_drop_packets)}, 150 {"rx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 151 rx_mcast_drop_bytes)}, 152 {"rx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 153 rx_mcast_drop_packets)}, 154 {"rx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 155 rx_bcast_drop_bytes)}, 156 {"rx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 157 rx_bcast_drop_packets)}, 158 {"rx_dma_error", offsetof(struct ionic_lif_stats, 159 rx_dma_error)}, 160 /* TX */ 161 {"tx_ucast_bytes", offsetof(struct ionic_lif_stats, 162 tx_ucast_bytes)}, 163 {"tx_ucast_packets", offsetof(struct ionic_lif_stats, 164 tx_ucast_packets)}, 165 {"tx_mcast_bytes", offsetof(struct ionic_lif_stats, 166 tx_mcast_bytes)}, 167 {"tx_mcast_packets", offsetof(struct ionic_lif_stats, 168 tx_mcast_packets)}, 169 {"tx_bcast_bytes", offsetof(struct ionic_lif_stats, 170 tx_bcast_bytes)}, 171 {"tx_bcast_packets", offsetof(struct ionic_lif_stats, 172 tx_bcast_packets)}, 173 /* TX drops */ 174 {"tx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 175 tx_ucast_drop_bytes)}, 176 {"tx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 177 tx_ucast_drop_packets)}, 178 {"tx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 179 tx_mcast_drop_bytes)}, 180 {"tx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 181 tx_mcast_drop_packets)}, 182 {"tx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 183 tx_bcast_drop_bytes)}, 184 {"tx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 185 tx_bcast_drop_packets)}, 186 {"tx_dma_error", offsetof(struct ionic_lif_stats, 187 tx_dma_error)}, 188 /* Rx Queue/Ring drops */ 189 {"rx_queue_disabled", offsetof(struct ionic_lif_stats, 190 rx_queue_disabled)}, 191 {"rx_queue_empty", offsetof(struct ionic_lif_stats, 192 rx_queue_empty)}, 193 {"rx_queue_error", offsetof(struct ionic_lif_stats, 194 rx_queue_error)}, 195 {"rx_desc_fetch_error", offsetof(struct ionic_lif_stats, 196 rx_desc_fetch_error)}, 197 {"rx_desc_data_error", offsetof(struct ionic_lif_stats, 198 rx_desc_data_error)}, 199 /* Tx Queue/Ring drops */ 200 {"tx_queue_disabled", offsetof(struct ionic_lif_stats, 201 tx_queue_disabled)}, 202 {"tx_queue_error", offsetof(struct ionic_lif_stats, 203 tx_queue_error)}, 204 {"tx_desc_fetch_error", offsetof(struct ionic_lif_stats, 205 tx_desc_fetch_error)}, 206 {"tx_desc_data_error", offsetof(struct ionic_lif_stats, 207 tx_desc_data_error)}, 208 }; 209 210 #define IONIC_NB_HW_STATS (sizeof(rte_ionic_xstats_strings) / \ 211 sizeof(rte_ionic_xstats_strings[0])) 212 213 static int 214 ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 215 char *fw_version, size_t fw_size) 216 { 217 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 218 struct ionic_adapter *adapter = lif->adapter; 219 220 if (fw_version == NULL || fw_size <= 0) 221 return -EINVAL; 222 223 snprintf(fw_version, fw_size, "%s", 224 adapter->fw_version); 225 fw_version[fw_size - 1] = '\0'; 226 227 return 0; 228 } 229 230 /* 231 * Set device link up, enable tx. 232 */ 233 static int 234 ionic_dev_set_link_up(struct rte_eth_dev *eth_dev) 235 { 236 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 237 int err; 238 239 IONIC_PRINT_CALL(); 240 241 err = ionic_lif_start(lif); 242 if (err) 243 IONIC_PRINT(ERR, "Could not start lif to set link up"); 244 245 ionic_dev_link_update(lif->eth_dev, 0); 246 247 return err; 248 } 249 250 /* 251 * Set device link down, disable tx. 252 */ 253 static int 254 ionic_dev_set_link_down(struct rte_eth_dev *eth_dev) 255 { 256 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 257 258 IONIC_PRINT_CALL(); 259 260 ionic_lif_stop(lif); 261 262 ionic_dev_link_update(lif->eth_dev, 0); 263 264 return 0; 265 } 266 267 int 268 ionic_dev_link_update(struct rte_eth_dev *eth_dev, 269 int wait_to_complete __rte_unused) 270 { 271 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 272 struct ionic_adapter *adapter = lif->adapter; 273 struct rte_eth_link link; 274 275 IONIC_PRINT_CALL(); 276 277 /* Initialize */ 278 memset(&link, 0, sizeof(link)); 279 link.link_autoneg = ETH_LINK_AUTONEG; 280 281 if (!adapter->link_up || 282 !(lif->state & IONIC_LIF_F_UP)) { 283 /* Interface is down */ 284 link.link_status = ETH_LINK_DOWN; 285 link.link_duplex = ETH_LINK_HALF_DUPLEX; 286 link.link_speed = ETH_SPEED_NUM_NONE; 287 } else { 288 /* Interface is up */ 289 link.link_status = ETH_LINK_UP; 290 link.link_duplex = ETH_LINK_FULL_DUPLEX; 291 switch (adapter->link_speed) { 292 case 10000: 293 link.link_speed = ETH_SPEED_NUM_10G; 294 break; 295 case 25000: 296 link.link_speed = ETH_SPEED_NUM_25G; 297 break; 298 case 40000: 299 link.link_speed = ETH_SPEED_NUM_40G; 300 break; 301 case 50000: 302 link.link_speed = ETH_SPEED_NUM_50G; 303 break; 304 case 100000: 305 link.link_speed = ETH_SPEED_NUM_100G; 306 break; 307 default: 308 link.link_speed = ETH_SPEED_NUM_NONE; 309 break; 310 } 311 } 312 313 return rte_eth_linkstatus_set(eth_dev, &link); 314 } 315 316 /** 317 * Interrupt handler triggered by NIC for handling 318 * specific interrupt. 319 * 320 * @param param 321 * The address of parameter registered before. 322 * 323 * @return 324 * void 325 */ 326 static void 327 ionic_dev_interrupt_handler(void *param) 328 { 329 struct ionic_adapter *adapter = (struct ionic_adapter *)param; 330 331 IONIC_PRINT(DEBUG, "->"); 332 333 if (adapter->lif) 334 ionic_notifyq_handler(adapter->lif, -1); 335 } 336 337 static int 338 ionic_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 339 { 340 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 341 uint32_t max_frame_size; 342 int err; 343 344 IONIC_PRINT_CALL(); 345 346 /* 347 * Note: mtu check against IONIC_MIN_MTU, IONIC_MAX_MTU 348 * is done by the the API. 349 */ 350 351 /* 352 * Max frame size is MTU + Ethernet header + VLAN + QinQ 353 * (plus ETHER_CRC_LEN if the adapter is able to keep CRC) 354 */ 355 max_frame_size = mtu + RTE_ETHER_HDR_LEN + 4 + 4; 356 357 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len < max_frame_size) 358 return -EINVAL; 359 360 err = ionic_lif_change_mtu(lif, mtu); 361 if (err) 362 return err; 363 364 return 0; 365 } 366 367 static int 368 ionic_dev_info_get(struct rte_eth_dev *eth_dev, 369 struct rte_eth_dev_info *dev_info) 370 { 371 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 372 struct ionic_adapter *adapter = lif->adapter; 373 struct ionic_identity *ident = &adapter->ident; 374 375 IONIC_PRINT_CALL(); 376 377 dev_info->max_rx_queues = (uint16_t) 378 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]; 379 dev_info->max_tx_queues = (uint16_t) 380 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]; 381 /* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */ 382 dev_info->min_rx_bufsize = IONIC_MIN_MTU + RTE_ETHER_HDR_LEN; 383 dev_info->max_rx_pktlen = IONIC_MAX_MTU + RTE_ETHER_HDR_LEN; 384 dev_info->max_mac_addrs = adapter->max_mac_addrs; 385 dev_info->min_mtu = IONIC_MIN_MTU; 386 dev_info->max_mtu = IONIC_MAX_MTU; 387 388 dev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE; 389 dev_info->reta_size = ident->lif.eth.rss_ind_tbl_sz; 390 dev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL; 391 392 dev_info->speed_capa = 393 ETH_LINK_SPEED_10G | 394 ETH_LINK_SPEED_25G | 395 ETH_LINK_SPEED_40G | 396 ETH_LINK_SPEED_50G | 397 ETH_LINK_SPEED_100G; 398 399 /* 400 * Per-queue capabilities 401 * RTE does not support disabling a feature on a queue if it is 402 * enabled globally on the device. Thus the driver does not advertise 403 * capabilities like DEV_TX_OFFLOAD_IPV4_CKSUM as per-queue even 404 * though the driver would be otherwise capable of disabling it on 405 * a per-queue basis. 406 */ 407 408 dev_info->rx_queue_offload_capa = 0; 409 dev_info->tx_queue_offload_capa = 0; 410 411 /* 412 * Per-port capabilities 413 * See ionic_set_features to request and check supported features 414 */ 415 416 dev_info->rx_offload_capa = dev_info->rx_queue_offload_capa | 417 DEV_RX_OFFLOAD_IPV4_CKSUM | 418 DEV_RX_OFFLOAD_UDP_CKSUM | 419 DEV_RX_OFFLOAD_TCP_CKSUM | 420 DEV_RX_OFFLOAD_JUMBO_FRAME | 421 DEV_RX_OFFLOAD_VLAN_FILTER | 422 DEV_RX_OFFLOAD_VLAN_STRIP | 423 DEV_RX_OFFLOAD_SCATTER | 424 DEV_RX_OFFLOAD_RSS_HASH | 425 0; 426 427 dev_info->tx_offload_capa = dev_info->tx_queue_offload_capa | 428 DEV_TX_OFFLOAD_IPV4_CKSUM | 429 DEV_TX_OFFLOAD_UDP_CKSUM | 430 DEV_TX_OFFLOAD_TCP_CKSUM | 431 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 432 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | 433 DEV_TX_OFFLOAD_MULTI_SEGS | 434 DEV_TX_OFFLOAD_TCP_TSO | 435 DEV_TX_OFFLOAD_VLAN_INSERT | 436 0; 437 438 dev_info->rx_desc_lim = rx_desc_lim; 439 dev_info->tx_desc_lim = tx_desc_lim; 440 441 /* Driver-preferred Rx/Tx parameters */ 442 dev_info->default_rxportconf.burst_size = 32; 443 dev_info->default_txportconf.burst_size = 32; 444 dev_info->default_rxportconf.nb_queues = 1; 445 dev_info->default_txportconf.nb_queues = 1; 446 dev_info->default_rxportconf.ring_size = IONIC_DEF_TXRX_DESC; 447 dev_info->default_txportconf.ring_size = IONIC_DEF_TXRX_DESC; 448 449 dev_info->default_rxconf = (struct rte_eth_rxconf) { 450 /* Packets are always dropped if no desc are available */ 451 .rx_drop_en = 1, 452 }; 453 454 return 0; 455 } 456 457 static int 458 ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 459 struct rte_eth_fc_conf *fc_conf) 460 { 461 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 462 struct ionic_adapter *adapter = lif->adapter; 463 struct ionic_dev *idev = &adapter->idev; 464 465 if (idev->port_info) { 466 fc_conf->autoneg = idev->port_info->config.an_enable; 467 468 if (idev->port_info->config.pause_type) 469 fc_conf->mode = RTE_FC_FULL; 470 else 471 fc_conf->mode = RTE_FC_NONE; 472 } 473 474 return 0; 475 } 476 477 static int 478 ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 479 struct rte_eth_fc_conf *fc_conf) 480 { 481 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 482 struct ionic_adapter *adapter = lif->adapter; 483 struct ionic_dev *idev = &adapter->idev; 484 uint8_t pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 485 uint8_t an_enable; 486 487 switch (fc_conf->mode) { 488 case RTE_FC_NONE: 489 pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 490 break; 491 case RTE_FC_FULL: 492 pause_type = IONIC_PORT_PAUSE_TYPE_LINK; 493 break; 494 case RTE_FC_RX_PAUSE: 495 case RTE_FC_TX_PAUSE: 496 return -ENOTSUP; 497 } 498 499 an_enable = fc_conf->autoneg; 500 501 ionic_dev_cmd_port_pause(idev, pause_type); 502 ionic_dev_cmd_port_autoneg(idev, an_enable); 503 504 return 0; 505 } 506 507 static int 508 ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 509 { 510 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 511 512 ionic_lif_configure_vlan_offload(lif, mask); 513 514 ionic_lif_set_features(lif); 515 516 return 0; 517 } 518 519 static int 520 ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 521 struct rte_eth_rss_reta_entry64 *reta_conf, 522 uint16_t reta_size) 523 { 524 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 525 struct ionic_adapter *adapter = lif->adapter; 526 struct ionic_identity *ident = &adapter->ident; 527 uint32_t i, j, index, num; 528 529 IONIC_PRINT_CALL(); 530 531 if (!lif->rss_ind_tbl) { 532 IONIC_PRINT(ERR, "RSS RETA not initialized, " 533 "can't update the table"); 534 return -EINVAL; 535 } 536 537 if (reta_size != ident->lif.eth.rss_ind_tbl_sz) { 538 IONIC_PRINT(ERR, "The size of hash lookup table configured " 539 "(%d) does not match the number hardware can support " 540 "(%d)", 541 reta_size, ident->lif.eth.rss_ind_tbl_sz); 542 return -EINVAL; 543 } 544 545 num = lif->adapter->ident.lif.eth.rss_ind_tbl_sz / RTE_RETA_GROUP_SIZE; 546 547 for (i = 0; i < num; i++) { 548 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) { 549 if (reta_conf[i].mask & ((uint64_t)1 << j)) { 550 index = (i * RTE_RETA_GROUP_SIZE) + j; 551 lif->rss_ind_tbl[index] = reta_conf[i].reta[j]; 552 } 553 } 554 } 555 556 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 557 } 558 559 static int 560 ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 561 struct rte_eth_rss_reta_entry64 *reta_conf, 562 uint16_t reta_size) 563 { 564 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 565 struct ionic_adapter *adapter = lif->adapter; 566 struct ionic_identity *ident = &adapter->ident; 567 int i, num; 568 569 IONIC_PRINT_CALL(); 570 571 if (reta_size != ident->lif.eth.rss_ind_tbl_sz) { 572 IONIC_PRINT(ERR, "The size of hash lookup table configured " 573 "(%d) does not match the number hardware can support " 574 "(%d)", 575 reta_size, ident->lif.eth.rss_ind_tbl_sz); 576 return -EINVAL; 577 } 578 579 if (!lif->rss_ind_tbl) { 580 IONIC_PRINT(ERR, "RSS RETA has not been built yet"); 581 return -EINVAL; 582 } 583 584 num = reta_size / RTE_RETA_GROUP_SIZE; 585 586 for (i = 0; i < num; i++) { 587 memcpy(reta_conf->reta, 588 &lif->rss_ind_tbl[i * RTE_RETA_GROUP_SIZE], 589 RTE_RETA_GROUP_SIZE); 590 reta_conf++; 591 } 592 593 return 0; 594 } 595 596 static int 597 ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 598 struct rte_eth_rss_conf *rss_conf) 599 { 600 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 601 uint64_t rss_hf = 0; 602 603 IONIC_PRINT_CALL(); 604 605 if (!lif->rss_ind_tbl) { 606 IONIC_PRINT(NOTICE, "RSS not enabled"); 607 return 0; 608 } 609 610 /* Get key value (if not null, rss_key is 40-byte) */ 611 if (rss_conf->rss_key != NULL && 612 rss_conf->rss_key_len >= IONIC_RSS_HASH_KEY_SIZE) 613 memcpy(rss_conf->rss_key, lif->rss_hash_key, 614 IONIC_RSS_HASH_KEY_SIZE); 615 616 if (lif->rss_types & IONIC_RSS_TYPE_IPV4) 617 rss_hf |= ETH_RSS_IPV4; 618 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_TCP) 619 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 620 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_UDP) 621 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 622 if (lif->rss_types & IONIC_RSS_TYPE_IPV6) 623 rss_hf |= ETH_RSS_IPV6; 624 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_TCP) 625 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 626 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_UDP) 627 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 628 629 rss_conf->rss_hf = rss_hf; 630 631 return 0; 632 } 633 634 static int 635 ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 636 struct rte_eth_rss_conf *rss_conf) 637 { 638 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 639 uint32_t rss_types = 0; 640 uint8_t *key = NULL; 641 642 IONIC_PRINT_CALL(); 643 644 if (rss_conf->rss_key) 645 key = rss_conf->rss_key; 646 647 if ((rss_conf->rss_hf & IONIC_ETH_RSS_OFFLOAD_ALL) == 0) { 648 /* 649 * Can't disable rss through hash flags, 650 * if it is enabled by default during init 651 */ 652 if (lif->rss_ind_tbl) 653 return -EINVAL; 654 } else { 655 /* Can't enable rss if disabled by default during init */ 656 if (!lif->rss_ind_tbl) 657 return -EINVAL; 658 659 if (rss_conf->rss_hf & ETH_RSS_IPV4) 660 rss_types |= IONIC_RSS_TYPE_IPV4; 661 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) 662 rss_types |= IONIC_RSS_TYPE_IPV4_TCP; 663 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) 664 rss_types |= IONIC_RSS_TYPE_IPV4_UDP; 665 if (rss_conf->rss_hf & ETH_RSS_IPV6) 666 rss_types |= IONIC_RSS_TYPE_IPV6; 667 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) 668 rss_types |= IONIC_RSS_TYPE_IPV6_TCP; 669 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) 670 rss_types |= IONIC_RSS_TYPE_IPV6_UDP; 671 672 ionic_lif_rss_config(lif, rss_types, key, NULL); 673 } 674 675 return 0; 676 } 677 678 static int 679 ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 680 struct rte_eth_stats *stats) 681 { 682 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 683 684 ionic_lif_get_stats(lif, stats); 685 686 return 0; 687 } 688 689 static int 690 ionic_dev_stats_reset(struct rte_eth_dev *eth_dev) 691 { 692 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 693 694 IONIC_PRINT_CALL(); 695 696 ionic_lif_reset_stats(lif); 697 698 return 0; 699 } 700 701 static int 702 ionic_dev_xstats_get_names(__rte_unused struct rte_eth_dev *eth_dev, 703 struct rte_eth_xstat_name *xstats_names, 704 __rte_unused unsigned int size) 705 { 706 unsigned int i; 707 708 if (xstats_names != NULL) { 709 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 710 snprintf(xstats_names[i].name, 711 sizeof(xstats_names[i].name), 712 "%s", rte_ionic_xstats_strings[i].name); 713 } 714 } 715 716 return IONIC_NB_HW_STATS; 717 } 718 719 static int 720 ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *eth_dev, 721 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, 722 unsigned int limit) 723 { 724 struct rte_eth_xstat_name xstats_names_copy[IONIC_NB_HW_STATS]; 725 uint16_t i; 726 727 if (!ids) { 728 if (xstats_names != NULL) { 729 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 730 snprintf(xstats_names[i].name, 731 sizeof(xstats_names[i].name), 732 "%s", rte_ionic_xstats_strings[i].name); 733 } 734 } 735 736 return IONIC_NB_HW_STATS; 737 } 738 739 ionic_dev_xstats_get_names_by_id(eth_dev, xstats_names_copy, NULL, 740 IONIC_NB_HW_STATS); 741 742 for (i = 0; i < limit; i++) { 743 if (ids[i] >= IONIC_NB_HW_STATS) { 744 IONIC_PRINT(ERR, "id value isn't valid"); 745 return -1; 746 } 747 748 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 749 } 750 751 return limit; 752 } 753 754 static int 755 ionic_dev_xstats_get(struct rte_eth_dev *eth_dev, struct rte_eth_xstat *xstats, 756 unsigned int n) 757 { 758 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 759 struct ionic_lif_stats hw_stats; 760 uint16_t i; 761 762 if (n < IONIC_NB_HW_STATS) 763 return IONIC_NB_HW_STATS; 764 765 ionic_lif_get_hw_stats(lif, &hw_stats); 766 767 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 768 xstats[i].value = *(uint64_t *)(((char *)&hw_stats) + 769 rte_ionic_xstats_strings[i].offset); 770 xstats[i].id = i; 771 } 772 773 return IONIC_NB_HW_STATS; 774 } 775 776 static int 777 ionic_dev_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids, 778 uint64_t *values, unsigned int n) 779 { 780 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 781 struct ionic_lif_stats hw_stats; 782 uint64_t values_copy[IONIC_NB_HW_STATS]; 783 uint16_t i; 784 785 if (!ids) { 786 if (!ids && n < IONIC_NB_HW_STATS) 787 return IONIC_NB_HW_STATS; 788 789 ionic_lif_get_hw_stats(lif, &hw_stats); 790 791 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 792 values[i] = *(uint64_t *)(((char *)&hw_stats) + 793 rte_ionic_xstats_strings[i].offset); 794 } 795 796 return IONIC_NB_HW_STATS; 797 } 798 799 ionic_dev_xstats_get_by_id(eth_dev, NULL, values_copy, 800 IONIC_NB_HW_STATS); 801 802 for (i = 0; i < n; i++) { 803 if (ids[i] >= IONIC_NB_HW_STATS) { 804 IONIC_PRINT(ERR, "id value isn't valid"); 805 return -1; 806 } 807 808 values[i] = values_copy[ids[i]]; 809 } 810 811 return n; 812 } 813 814 static int 815 ionic_dev_xstats_reset(struct rte_eth_dev *eth_dev) 816 { 817 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 818 819 ionic_lif_reset_hw_stats(lif); 820 821 return 0; 822 } 823 824 static int 825 ionic_dev_configure(struct rte_eth_dev *eth_dev) 826 { 827 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 828 829 IONIC_PRINT_CALL(); 830 831 ionic_lif_configure(lif); 832 833 ionic_lif_set_features(lif); 834 835 return 0; 836 } 837 838 static inline uint32_t 839 ionic_parse_link_speeds(uint16_t link_speeds) 840 { 841 if (link_speeds & ETH_LINK_SPEED_100G) 842 return 100000; 843 else if (link_speeds & ETH_LINK_SPEED_50G) 844 return 50000; 845 else if (link_speeds & ETH_LINK_SPEED_40G) 846 return 40000; 847 else if (link_speeds & ETH_LINK_SPEED_25G) 848 return 25000; 849 else if (link_speeds & ETH_LINK_SPEED_10G) 850 return 10000; 851 else 852 return 0; 853 } 854 855 /* 856 * Configure device link speed and setup link. 857 * It returns 0 on success. 858 */ 859 static int 860 ionic_dev_start(struct rte_eth_dev *eth_dev) 861 { 862 struct rte_eth_conf *dev_conf = ð_dev->data->dev_conf; 863 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 864 struct ionic_adapter *adapter = lif->adapter; 865 struct ionic_dev *idev = &adapter->idev; 866 uint32_t allowed_speeds; 867 int err; 868 869 IONIC_PRINT_CALL(); 870 871 allowed_speeds = 872 ETH_LINK_SPEED_FIXED | 873 ETH_LINK_SPEED_10G | 874 ETH_LINK_SPEED_25G | 875 ETH_LINK_SPEED_40G | 876 ETH_LINK_SPEED_50G | 877 ETH_LINK_SPEED_100G; 878 879 if (dev_conf->link_speeds & ~allowed_speeds) { 880 IONIC_PRINT(ERR, "Invalid link setting"); 881 return -EINVAL; 882 } 883 884 if (dev_conf->lpbk_mode) 885 IONIC_PRINT(WARNING, "Loopback mode not supported"); 886 887 err = ionic_lif_start(lif); 888 if (err) { 889 IONIC_PRINT(ERR, "Cannot start LIF: %d", err); 890 return err; 891 } 892 893 if (eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) { 894 uint32_t speed = ionic_parse_link_speeds(dev_conf->link_speeds); 895 896 if (speed) 897 ionic_dev_cmd_port_speed(idev, speed); 898 } 899 900 ionic_dev_link_update(eth_dev, 0); 901 902 return 0; 903 } 904 905 /* 906 * Stop device: disable rx and tx functions to allow for reconfiguring. 907 */ 908 static int 909 ionic_dev_stop(struct rte_eth_dev *eth_dev) 910 { 911 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 912 913 IONIC_PRINT_CALL(); 914 915 ionic_lif_stop(lif); 916 917 return 0; 918 } 919 920 static void ionic_unconfigure_intr(struct ionic_adapter *adapter); 921 922 /* 923 * Reset and stop device. 924 */ 925 static int 926 ionic_dev_close(struct rte_eth_dev *eth_dev) 927 { 928 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 929 struct ionic_adapter *adapter = lif->adapter; 930 931 IONIC_PRINT_CALL(); 932 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 933 return 0; 934 935 ionic_lif_stop(lif); 936 937 ionic_lif_free_queues(lif); 938 939 IONIC_PRINT(NOTICE, "Removing device %s", eth_dev->device->name); 940 ionic_unconfigure_intr(adapter); 941 942 rte_eth_dev_destroy(eth_dev, eth_ionic_dev_uninit); 943 944 ionic_port_reset(adapter); 945 ionic_reset(adapter); 946 947 rte_free(adapter); 948 949 return 0; 950 } 951 952 static int 953 eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params) 954 { 955 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 956 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 957 struct ionic_adapter *adapter = (struct ionic_adapter *)init_params; 958 int err; 959 960 IONIC_PRINT_CALL(); 961 962 eth_dev->dev_ops = &ionic_eth_dev_ops; 963 eth_dev->rx_pkt_burst = &ionic_recv_pkts; 964 eth_dev->tx_pkt_burst = &ionic_xmit_pkts; 965 eth_dev->tx_pkt_prepare = &ionic_prep_pkts; 966 967 /* Multi-process not supported, primary does initialization anyway */ 968 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 969 return 0; 970 971 rte_eth_copy_pci_info(eth_dev, pci_dev); 972 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 973 974 lif->eth_dev = eth_dev; 975 lif->adapter = adapter; 976 adapter->lif = lif; 977 978 IONIC_PRINT(DEBUG, "Up to %u MAC addresses supported", 979 adapter->max_mac_addrs); 980 981 /* Allocate memory for storing MAC addresses */ 982 eth_dev->data->mac_addrs = rte_zmalloc("ionic", 983 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs, 0); 984 985 if (eth_dev->data->mac_addrs == NULL) { 986 IONIC_PRINT(ERR, "Failed to allocate %u bytes needed to " 987 "store MAC addresses", 988 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs); 989 err = -ENOMEM; 990 goto err; 991 } 992 993 err = ionic_lif_alloc(lif); 994 if (err) { 995 IONIC_PRINT(ERR, "Cannot allocate LIFs: %d, aborting", 996 err); 997 goto err; 998 } 999 1000 err = ionic_lif_init(lif); 1001 if (err) { 1002 IONIC_PRINT(ERR, "Cannot init LIFs: %d, aborting", err); 1003 goto err_free_lif; 1004 } 1005 1006 /* Copy the MAC address */ 1007 rte_ether_addr_copy((struct rte_ether_addr *)lif->mac_addr, 1008 ð_dev->data->mac_addrs[0]); 1009 1010 IONIC_PRINT(DEBUG, "Port %u initialized", eth_dev->data->port_id); 1011 1012 return 0; 1013 1014 err_free_lif: 1015 ionic_lif_free(lif); 1016 err: 1017 return err; 1018 } 1019 1020 static int 1021 eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev) 1022 { 1023 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 1024 struct ionic_adapter *adapter = lif->adapter; 1025 1026 IONIC_PRINT_CALL(); 1027 1028 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1029 return 0; 1030 1031 adapter->lif = NULL; 1032 1033 ionic_lif_deinit(lif); 1034 ionic_lif_free(lif); 1035 1036 if (!(lif->state & IONIC_LIF_F_FW_RESET)) 1037 ionic_lif_reset(lif); 1038 1039 return 0; 1040 } 1041 1042 static int 1043 ionic_configure_intr(struct ionic_adapter *adapter) 1044 { 1045 struct rte_pci_device *pci_dev = adapter->pci_dev; 1046 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1047 int err; 1048 1049 IONIC_PRINT(DEBUG, "Configuring %u intrs", adapter->nintrs); 1050 1051 if (rte_intr_efd_enable(intr_handle, adapter->nintrs)) { 1052 IONIC_PRINT(ERR, "Fail to create eventfd"); 1053 return -1; 1054 } 1055 1056 if (rte_intr_dp_is_en(intr_handle)) 1057 IONIC_PRINT(DEBUG, 1058 "Packet I/O interrupt on datapath is enabled"); 1059 1060 if (!intr_handle->intr_vec) { 1061 intr_handle->intr_vec = rte_zmalloc("intr_vec", 1062 adapter->nintrs * sizeof(int), 0); 1063 1064 if (!intr_handle->intr_vec) { 1065 IONIC_PRINT(ERR, "Failed to allocate %u vectors", 1066 adapter->nintrs); 1067 return -ENOMEM; 1068 } 1069 } 1070 1071 err = rte_intr_callback_register(intr_handle, 1072 ionic_dev_interrupt_handler, 1073 adapter); 1074 1075 if (err) { 1076 IONIC_PRINT(ERR, 1077 "Failure registering interrupts handler (%d)", 1078 err); 1079 return err; 1080 } 1081 1082 /* enable intr mapping */ 1083 err = rte_intr_enable(intr_handle); 1084 1085 if (err) { 1086 IONIC_PRINT(ERR, "Failure enabling interrupts (%d)", err); 1087 return err; 1088 } 1089 1090 return 0; 1091 } 1092 1093 static void 1094 ionic_unconfigure_intr(struct ionic_adapter *adapter) 1095 { 1096 struct rte_pci_device *pci_dev = adapter->pci_dev; 1097 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1098 1099 rte_intr_disable(intr_handle); 1100 1101 rte_intr_callback_unregister(intr_handle, 1102 ionic_dev_interrupt_handler, 1103 adapter); 1104 } 1105 1106 static int 1107 eth_ionic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1108 struct rte_pci_device *pci_dev) 1109 { 1110 char name[RTE_ETH_NAME_MAX_LEN]; 1111 struct rte_mem_resource *resource; 1112 struct ionic_adapter *adapter; 1113 struct ionic_hw *hw; 1114 unsigned long i; 1115 int err; 1116 1117 /* Check structs (trigger error at compilation time) */ 1118 ionic_struct_size_checks(); 1119 1120 /* Multi-process not supported */ 1121 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1122 err = -EPERM; 1123 goto err; 1124 } 1125 1126 IONIC_PRINT(DEBUG, "Initializing device %s", 1127 pci_dev->device.name); 1128 1129 adapter = rte_zmalloc("ionic", sizeof(*adapter), 0); 1130 if (!adapter) { 1131 IONIC_PRINT(ERR, "OOM"); 1132 err = -ENOMEM; 1133 goto err; 1134 } 1135 1136 adapter->pci_dev = pci_dev; 1137 hw = &adapter->hw; 1138 1139 hw->device_id = pci_dev->id.device_id; 1140 hw->vendor_id = pci_dev->id.vendor_id; 1141 1142 err = ionic_init_mac(hw); 1143 if (err != 0) { 1144 IONIC_PRINT(ERR, "Mac init failed: %d", err); 1145 err = -EIO; 1146 goto err_free_adapter; 1147 } 1148 1149 adapter->num_bars = 0; 1150 for (i = 0; i < PCI_MAX_RESOURCE && i < IONIC_BARS_MAX; i++) { 1151 resource = &pci_dev->mem_resource[i]; 1152 if (resource->phys_addr == 0 || resource->len == 0) 1153 continue; 1154 adapter->bars[adapter->num_bars].vaddr = resource->addr; 1155 adapter->bars[adapter->num_bars].bus_addr = resource->phys_addr; 1156 adapter->bars[adapter->num_bars].len = resource->len; 1157 adapter->num_bars++; 1158 } 1159 1160 /* Discover ionic dev resources */ 1161 1162 err = ionic_setup(adapter); 1163 if (err) { 1164 IONIC_PRINT(ERR, "Cannot setup device: %d, aborting", err); 1165 goto err_free_adapter; 1166 } 1167 1168 err = ionic_identify(adapter); 1169 if (err) { 1170 IONIC_PRINT(ERR, "Cannot identify device: %d, aborting", 1171 err); 1172 goto err_free_adapter; 1173 } 1174 1175 err = ionic_init(adapter); 1176 if (err) { 1177 IONIC_PRINT(ERR, "Cannot init device: %d, aborting", err); 1178 goto err_free_adapter; 1179 } 1180 1181 /* Configure the ports */ 1182 err = ionic_port_identify(adapter); 1183 if (err) { 1184 IONIC_PRINT(ERR, "Cannot identify port: %d, aborting", 1185 err); 1186 goto err_free_adapter; 1187 } 1188 1189 err = ionic_port_init(adapter); 1190 if (err) { 1191 IONIC_PRINT(ERR, "Cannot init port: %d, aborting", err); 1192 goto err_free_adapter; 1193 } 1194 1195 /* Configure LIFs */ 1196 err = ionic_lif_identify(adapter); 1197 if (err) { 1198 IONIC_PRINT(ERR, "Cannot identify lif: %d, aborting", err); 1199 goto err_free_adapter; 1200 } 1201 1202 /* Allocate and init LIFs */ 1203 err = ionic_lifs_size(adapter); 1204 if (err) { 1205 IONIC_PRINT(ERR, "Cannot size LIFs: %d, aborting", err); 1206 goto err_free_adapter; 1207 } 1208 1209 adapter->max_mac_addrs = adapter->ident.lif.eth.max_ucast_filters; 1210 1211 if (adapter->ident.dev.nlifs != 1) { 1212 IONIC_PRINT(ERR, "Unexpected request for %d LIFs", 1213 adapter->ident.dev.nlifs); 1214 goto err_free_adapter; 1215 } 1216 1217 snprintf(name, sizeof(name), "%s_lif", pci_dev->device.name); 1218 err = rte_eth_dev_create(&pci_dev->device, 1219 name, sizeof(struct ionic_lif), 1220 NULL, NULL, eth_ionic_dev_init, adapter); 1221 if (err) { 1222 IONIC_PRINT(ERR, "Cannot create eth device for %s", name); 1223 goto err_free_adapter; 1224 } 1225 1226 err = ionic_configure_intr(adapter); 1227 1228 if (err) { 1229 IONIC_PRINT(ERR, "Failed to configure interrupts"); 1230 goto err_free_adapter; 1231 } 1232 1233 return 0; 1234 1235 err_free_adapter: 1236 rte_free(adapter); 1237 err: 1238 return err; 1239 } 1240 1241 static int 1242 eth_ionic_pci_remove(struct rte_pci_device *pci_dev) 1243 { 1244 char name[RTE_ETH_NAME_MAX_LEN]; 1245 struct rte_eth_dev *eth_dev; 1246 1247 /* Adapter lookup is using the eth_dev name */ 1248 snprintf(name, sizeof(name), "%s_lif", pci_dev->device.name); 1249 1250 eth_dev = rte_eth_dev_allocated(name); 1251 if (eth_dev) 1252 ionic_dev_close(eth_dev); 1253 else 1254 IONIC_PRINT(DEBUG, "Cannot find device %s", 1255 pci_dev->device.name); 1256 1257 return 0; 1258 } 1259 1260 static struct rte_pci_driver rte_ionic_pmd = { 1261 .id_table = pci_id_ionic_map, 1262 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1263 .probe = eth_ionic_pci_probe, 1264 .remove = eth_ionic_pci_remove, 1265 }; 1266 1267 RTE_PMD_REGISTER_PCI(net_ionic, rte_ionic_pmd); 1268 RTE_PMD_REGISTER_PCI_TABLE(net_ionic, pci_id_ionic_map); 1269 RTE_PMD_REGISTER_KMOD_DEP(net_ionic, "* igb_uio | uio_pci_generic | vfio-pci"); 1270 RTE_LOG_REGISTER(ionic_logtype, pmd.net.ionic, NOTICE); 1271