1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved. 3 */ 4 5 #include <stdbool.h> 6 7 #include <rte_malloc.h> 8 9 #include "ionic_dev.h" 10 #include "ionic_lif.h" 11 #include "ionic.h" 12 13 int 14 ionic_dev_setup(struct ionic_adapter *adapter) 15 { 16 struct ionic_dev_bar *bar = adapter->bars; 17 unsigned int num_bars = adapter->num_bars; 18 struct ionic_dev *idev = &adapter->idev; 19 uint32_t sig; 20 u_char *bar0_base; 21 unsigned int i; 22 23 /* BAR0: dev_cmd and interrupts */ 24 if (num_bars < 1) { 25 IONIC_PRINT(ERR, "No bars found, aborting"); 26 return -EFAULT; 27 } 28 29 if (bar->len < IONIC_BAR0_SIZE) { 30 IONIC_PRINT(ERR, 31 "Resource bar size %lu too small, aborting", 32 bar->len); 33 return -EFAULT; 34 } 35 36 bar0_base = bar->vaddr; 37 idev->dev_info = (union ionic_dev_info_regs *) 38 &bar0_base[IONIC_BAR0_DEV_INFO_REGS_OFFSET]; 39 idev->dev_cmd = (union ionic_dev_cmd_regs *) 40 &bar0_base[IONIC_BAR0_DEV_CMD_REGS_OFFSET]; 41 idev->intr_status = (struct ionic_intr_status *) 42 &bar0_base[IONIC_BAR0_INTR_STATUS_OFFSET]; 43 idev->intr_ctrl = (struct ionic_intr *) 44 &bar0_base[IONIC_BAR0_INTR_CTRL_OFFSET]; 45 46 sig = ioread32(&idev->dev_info->signature); 47 if (sig != IONIC_DEV_INFO_SIGNATURE) { 48 IONIC_PRINT(ERR, "Incompatible firmware signature %" PRIx32 "", 49 sig); 50 return -EFAULT; 51 } 52 53 for (i = 0; i < IONIC_DEVINFO_FWVERS_BUFLEN; i++) 54 adapter->fw_version[i] = 55 ioread8(&idev->dev_info->fw_version[i]); 56 adapter->fw_version[IONIC_DEVINFO_FWVERS_BUFLEN - 1] = '\0'; 57 58 IONIC_PRINT(DEBUG, "Firmware version: %s", adapter->fw_version); 59 60 /* BAR1: doorbells */ 61 bar++; 62 if (num_bars < 2) { 63 IONIC_PRINT(ERR, "Doorbell bar missing, aborting"); 64 return -EFAULT; 65 } 66 67 idev->db_pages = bar->vaddr; 68 69 return 0; 70 } 71 72 /* Devcmd Interface */ 73 74 uint8_t 75 ionic_dev_cmd_status(struct ionic_dev *idev) 76 { 77 return ioread8(&idev->dev_cmd->comp.comp.status); 78 } 79 80 bool 81 ionic_dev_cmd_done(struct ionic_dev *idev) 82 { 83 return ioread32(&idev->dev_cmd->done) & IONIC_DEV_CMD_DONE; 84 } 85 86 void 87 ionic_dev_cmd_comp(struct ionic_dev *idev, void *mem) 88 { 89 union ionic_dev_cmd_comp *comp = mem; 90 unsigned int i; 91 uint32_t comp_size = sizeof(comp->words) / 92 sizeof(comp->words[0]); 93 94 for (i = 0; i < comp_size; i++) 95 comp->words[i] = ioread32(&idev->dev_cmd->comp.words[i]); 96 } 97 98 void 99 ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd) 100 { 101 unsigned int i; 102 uint32_t cmd_size = sizeof(cmd->words) / 103 sizeof(cmd->words[0]); 104 105 IONIC_PRINT(DEBUG, "Sending %s (%d) via dev_cmd", 106 ionic_opcode_to_str(cmd->cmd.opcode), cmd->cmd.opcode); 107 108 for (i = 0; i < cmd_size; i++) 109 iowrite32(cmd->words[i], &idev->dev_cmd->cmd.words[i]); 110 111 iowrite32(0, &idev->dev_cmd->done); 112 iowrite32(1, &idev->dev_cmd->doorbell); 113 } 114 115 /* Device commands */ 116 117 void 118 ionic_dev_cmd_identify(struct ionic_dev *idev, uint8_t ver) 119 { 120 union ionic_dev_cmd cmd = { 121 .identify.opcode = IONIC_CMD_IDENTIFY, 122 .identify.ver = ver, 123 }; 124 125 ionic_dev_cmd_go(idev, &cmd); 126 } 127 128 void 129 ionic_dev_cmd_init(struct ionic_dev *idev) 130 { 131 union ionic_dev_cmd cmd = { 132 .init.opcode = IONIC_CMD_INIT, 133 .init.type = 0, 134 }; 135 136 ionic_dev_cmd_go(idev, &cmd); 137 } 138 139 void 140 ionic_dev_cmd_reset(struct ionic_dev *idev) 141 { 142 union ionic_dev_cmd cmd = { 143 .reset.opcode = IONIC_CMD_RESET, 144 }; 145 146 ionic_dev_cmd_go(idev, &cmd); 147 } 148 149 /* Port commands */ 150 151 void 152 ionic_dev_cmd_port_identify(struct ionic_dev *idev) 153 { 154 union ionic_dev_cmd cmd = { 155 .port_init.opcode = IONIC_CMD_PORT_IDENTIFY, 156 .port_init.index = 0, 157 }; 158 159 ionic_dev_cmd_go(idev, &cmd); 160 } 161 162 void 163 ionic_dev_cmd_port_init(struct ionic_dev *idev) 164 { 165 union ionic_dev_cmd cmd = { 166 .port_init.opcode = IONIC_CMD_PORT_INIT, 167 .port_init.index = 0, 168 .port_init.info_pa = idev->port_info_pa, 169 }; 170 171 ionic_dev_cmd_go(idev, &cmd); 172 } 173 174 void 175 ionic_dev_cmd_port_reset(struct ionic_dev *idev) 176 { 177 union ionic_dev_cmd cmd = { 178 .port_reset.opcode = IONIC_CMD_PORT_RESET, 179 .port_reset.index = 0, 180 }; 181 182 ionic_dev_cmd_go(idev, &cmd); 183 } 184 185 void 186 ionic_dev_cmd_port_state(struct ionic_dev *idev, uint8_t state) 187 { 188 union ionic_dev_cmd cmd = { 189 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 190 .port_setattr.index = 0, 191 .port_setattr.attr = IONIC_PORT_ATTR_STATE, 192 .port_setattr.state = state, 193 }; 194 195 ionic_dev_cmd_go(idev, &cmd); 196 } 197 198 void 199 ionic_dev_cmd_port_speed(struct ionic_dev *idev, uint32_t speed) 200 { 201 union ionic_dev_cmd cmd = { 202 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 203 .port_setattr.index = 0, 204 .port_setattr.attr = IONIC_PORT_ATTR_SPEED, 205 .port_setattr.speed = speed, 206 }; 207 208 ionic_dev_cmd_go(idev, &cmd); 209 } 210 211 void 212 ionic_dev_cmd_port_mtu(struct ionic_dev *idev, uint32_t mtu) 213 { 214 union ionic_dev_cmd cmd = { 215 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 216 .port_setattr.index = 0, 217 .port_setattr.attr = IONIC_PORT_ATTR_MTU, 218 .port_setattr.mtu = mtu, 219 }; 220 221 ionic_dev_cmd_go(idev, &cmd); 222 } 223 224 void 225 ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, uint8_t an_enable) 226 { 227 union ionic_dev_cmd cmd = { 228 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 229 .port_setattr.index = 0, 230 .port_setattr.attr = IONIC_PORT_ATTR_AUTONEG, 231 .port_setattr.an_enable = an_enable, 232 }; 233 234 ionic_dev_cmd_go(idev, &cmd); 235 } 236 237 void 238 ionic_dev_cmd_port_fec(struct ionic_dev *idev, uint8_t fec_type) 239 { 240 union ionic_dev_cmd cmd = { 241 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 242 .port_setattr.index = 0, 243 .port_setattr.attr = IONIC_PORT_ATTR_FEC, 244 .port_setattr.fec_type = fec_type, 245 }; 246 247 ionic_dev_cmd_go(idev, &cmd); 248 } 249 250 void 251 ionic_dev_cmd_port_pause(struct ionic_dev *idev, uint8_t pause_type) 252 { 253 union ionic_dev_cmd cmd = { 254 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 255 .port_setattr.index = 0, 256 .port_setattr.attr = IONIC_PORT_ATTR_PAUSE, 257 .port_setattr.pause_type = pause_type, 258 }; 259 260 ionic_dev_cmd_go(idev, &cmd); 261 } 262 263 void 264 ionic_dev_cmd_port_loopback(struct ionic_dev *idev, uint8_t loopback_mode) 265 { 266 union ionic_dev_cmd cmd = { 267 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 268 .port_setattr.index = 0, 269 .port_setattr.attr = IONIC_PORT_ATTR_LOOPBACK, 270 .port_setattr.loopback_mode = loopback_mode, 271 }; 272 273 ionic_dev_cmd_go(idev, &cmd); 274 } 275 276 /* LIF commands */ 277 278 void 279 ionic_dev_cmd_lif_identify(struct ionic_dev *idev, uint8_t type, uint8_t ver) 280 { 281 union ionic_dev_cmd cmd = { 282 .lif_identify.opcode = IONIC_CMD_LIF_IDENTIFY, 283 .lif_identify.type = type, 284 .lif_identify.ver = ver, 285 }; 286 287 ionic_dev_cmd_go(idev, &cmd); 288 } 289 290 void 291 ionic_dev_cmd_lif_init(struct ionic_dev *idev, rte_iova_t info_pa) 292 { 293 union ionic_dev_cmd cmd = { 294 .lif_init.opcode = IONIC_CMD_LIF_INIT, 295 .lif_init.info_pa = info_pa, 296 }; 297 298 ionic_dev_cmd_go(idev, &cmd); 299 } 300 301 void 302 ionic_dev_cmd_lif_reset(struct ionic_dev *idev) 303 { 304 union ionic_dev_cmd cmd = { 305 .lif_init.opcode = IONIC_CMD_LIF_RESET, 306 }; 307 308 ionic_dev_cmd_go(idev, &cmd); 309 } 310 311 struct ionic_doorbell * 312 ionic_db_map(struct ionic_lif *lif, struct ionic_queue *q) 313 { 314 return lif->kern_dbpage + q->hw_type; 315 } 316 317 void 318 ionic_intr_init(struct ionic_dev *idev, struct ionic_intr_info *intr, 319 unsigned long index) 320 { 321 ionic_intr_clean(idev->intr_ctrl, index); 322 intr->index = index; 323 } 324 325 void 326 ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq) 327 { 328 struct ionic_queue *q = &qcq->q; 329 struct ionic_cq *cq = &qcq->cq; 330 331 union ionic_dev_cmd cmd = { 332 .q_init.opcode = IONIC_CMD_Q_INIT, 333 .q_init.type = q->type, 334 .q_init.index = q->index, 335 .q_init.flags = IONIC_QINIT_F_ENA, 336 .q_init.intr_index = IONIC_INTR_NONE, 337 .q_init.ring_size = rte_log2_u32(q->num_descs), 338 .q_init.ring_base = q->base_pa, 339 .q_init.cq_ring_base = cq->base_pa, 340 }; 341 342 IONIC_PRINT(DEBUG, "adminq.q_init.ver %u", cmd.q_init.ver); 343 344 ionic_dev_cmd_go(idev, &cmd); 345 } 346 347 int 348 ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq, 349 uint32_t num_descs, size_t desc_size) 350 { 351 if (desc_size == 0) { 352 IONIC_PRINT(ERR, "Descriptor size is %zu", desc_size); 353 return -EINVAL; 354 } 355 356 if (!rte_is_power_of_2(num_descs) || 357 num_descs < IONIC_MIN_RING_DESC || 358 num_descs > IONIC_MAX_RING_DESC) { 359 IONIC_PRINT(ERR, "%u descriptors (min: %u max: %u)", 360 num_descs, IONIC_MIN_RING_DESC, IONIC_MAX_RING_DESC); 361 return -EINVAL; 362 } 363 364 cq->lif = lif; 365 cq->num_descs = num_descs; 366 cq->desc_size = desc_size; 367 cq->tail_idx = 0; 368 cq->done_color = 1; 369 370 return 0; 371 } 372 373 void 374 ionic_cq_map(struct ionic_cq *cq, void *base, rte_iova_t base_pa) 375 { 376 cq->base = base; 377 cq->base_pa = base_pa; 378 } 379 380 void 381 ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q) 382 { 383 cq->bound_q = q; 384 q->bound_cq = cq; 385 } 386 387 uint32_t 388 ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do, 389 ionic_cq_cb cb, void *cb_arg) 390 { 391 uint32_t work_done = 0; 392 393 if (work_to_do == 0) 394 return 0; 395 396 while (cb(cq, cq->tail_idx, cb_arg)) { 397 cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1); 398 if (cq->tail_idx == 0) 399 cq->done_color = !cq->done_color; 400 401 if (++work_done == work_to_do) 402 break; 403 } 404 405 return work_done; 406 } 407 408 int 409 ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev, 410 struct ionic_queue *q, uint32_t index, uint32_t num_descs, 411 size_t desc_size, size_t sg_desc_size) 412 { 413 uint32_t ring_size; 414 415 if (desc_size == 0 || !rte_is_power_of_2(num_descs)) 416 return -EINVAL; 417 418 ring_size = rte_log2_u32(num_descs); 419 420 if (ring_size < 2 || ring_size > 16) 421 return -EINVAL; 422 423 q->lif = lif; 424 q->idev = idev; 425 q->index = index; 426 q->num_descs = num_descs; 427 q->desc_size = desc_size; 428 q->sg_desc_size = sg_desc_size; 429 q->head_idx = 0; 430 q->tail_idx = 0; 431 432 return 0; 433 } 434 435 void 436 ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa) 437 { 438 q->base = base; 439 q->base_pa = base_pa; 440 } 441 442 void 443 ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa) 444 { 445 q->sg_base = base; 446 q->sg_base_pa = base_pa; 447 } 448 449 void 450 ionic_q_flush(struct ionic_queue *q) 451 { 452 writeq(IONIC_DBELL_QID(q->hw_index) | q->head_idx, q->db); 453 } 454 455 void 456 ionic_q_post(struct ionic_queue *q, bool ring_doorbell, desc_cb cb, 457 void *cb_arg) 458 { 459 struct ionic_desc_info *head = &q->info[q->head_idx]; 460 461 head->cb = cb; 462 head->cb_arg = cb_arg; 463 464 q->head_idx = (q->head_idx + 1) & (q->num_descs - 1); 465 466 if (ring_doorbell) 467 ionic_q_flush(q); 468 } 469 470 uint32_t 471 ionic_q_space_avail(struct ionic_queue *q) 472 { 473 uint32_t avail = q->tail_idx; 474 475 if (q->head_idx >= avail) 476 avail += q->num_descs - q->head_idx - 1; 477 else 478 avail -= q->head_idx + 1; 479 480 return avail; 481 } 482 483 bool 484 ionic_q_has_space(struct ionic_queue *q, uint32_t want) 485 { 486 return ionic_q_space_avail(q) >= want; 487 } 488 489 void 490 ionic_q_service(struct ionic_queue *q, uint32_t cq_desc_index, 491 uint32_t stop_index, void *service_cb_arg) 492 { 493 struct ionic_desc_info *desc_info; 494 uint32_t curr_q_tail_idx; 495 496 do { 497 desc_info = &q->info[q->tail_idx]; 498 499 if (desc_info->cb) 500 desc_info->cb(q, q->tail_idx, cq_desc_index, 501 desc_info->cb_arg, service_cb_arg); 502 503 desc_info->cb = NULL; 504 desc_info->cb_arg = NULL; 505 506 curr_q_tail_idx = q->tail_idx; 507 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 508 509 } while (curr_q_tail_idx != stop_index); 510 } 511 512 static void 513 ionic_adminq_cb(struct ionic_queue *q, 514 uint32_t q_desc_index, uint32_t cq_desc_index, 515 void *cb_arg, void *service_cb_arg __rte_unused) 516 { 517 struct ionic_admin_ctx *ctx = cb_arg; 518 struct ionic_admin_comp *cq_desc_base = q->bound_cq->base; 519 struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index]; 520 521 if (unlikely(cq_desc->comp_index != q_desc_index)) { 522 IONIC_WARN_ON(cq_desc->comp_index != q_desc_index); 523 return; 524 } 525 526 memcpy(&ctx->comp, cq_desc, sizeof(*cq_desc)); 527 528 ctx->pending_work = false; /* done */ 529 } 530 531 /** ionic_adminq_post - Post an admin command. 532 * @lif: Handle to lif. 533 * @cmd_ctx: Api admin command context. 534 * 535 * Post the command to an admin queue in the ethernet driver. If this command 536 * succeeds, then the command has been posted, but that does not indicate a 537 * completion. If this command returns success, then the completion callback 538 * will eventually be called. 539 * 540 * Return: zero or negative error status. 541 */ 542 int 543 ionic_adminq_post(struct ionic_lif *lif, struct ionic_admin_ctx *ctx) 544 { 545 struct ionic_queue *adminq = &lif->adminqcq->q; 546 struct ionic_admin_cmd *q_desc_base = adminq->base; 547 struct ionic_admin_cmd *q_desc; 548 int err = 0; 549 550 rte_spinlock_lock(&lif->adminq_lock); 551 552 if (!ionic_q_has_space(adminq, 1)) { 553 err = -ENOSPC; 554 goto err_out; 555 } 556 557 q_desc = &q_desc_base[adminq->head_idx]; 558 559 memcpy(q_desc, &ctx->cmd, sizeof(ctx->cmd)); 560 561 ionic_q_post(adminq, true, ionic_adminq_cb, ctx); 562 563 err_out: 564 rte_spinlock_unlock(&lif->adminq_lock); 565 566 return err; 567 } 568