1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved. 3 */ 4 5 #include <rte_malloc.h> 6 7 #include "ionic_dev.h" 8 #include "ionic_lif.h" 9 #include "ionic.h" 10 11 int 12 ionic_dev_setup(struct ionic_adapter *adapter) 13 { 14 struct ionic_dev_bar *bar = adapter->bars; 15 unsigned int num_bars = adapter->num_bars; 16 struct ionic_dev *idev = &adapter->idev; 17 uint32_t sig; 18 u_char *bar0_base; 19 20 /* BAR0: dev_cmd and interrupts */ 21 if (num_bars < 1) { 22 IONIC_PRINT(ERR, "No bars found, aborting"); 23 return -EFAULT; 24 } 25 26 if (bar->len < IONIC_BAR0_SIZE) { 27 IONIC_PRINT(ERR, 28 "Resource bar size %lu too small, aborting", 29 bar->len); 30 return -EFAULT; 31 } 32 33 bar0_base = bar->vaddr; 34 idev->dev_info = (union ionic_dev_info_regs *) 35 &bar0_base[IONIC_BAR0_DEV_INFO_REGS_OFFSET]; 36 idev->dev_cmd = (union ionic_dev_cmd_regs *) 37 &bar0_base[IONIC_BAR0_DEV_CMD_REGS_OFFSET]; 38 idev->intr_status = (struct ionic_intr_status *) 39 &bar0_base[IONIC_BAR0_INTR_STATUS_OFFSET]; 40 idev->intr_ctrl = (struct ionic_intr *) 41 &bar0_base[IONIC_BAR0_INTR_CTRL_OFFSET]; 42 43 sig = ioread32(&idev->dev_info->signature); 44 if (sig != IONIC_DEV_INFO_SIGNATURE) { 45 IONIC_PRINT(ERR, "Incompatible firmware signature %" PRIx32 "", 46 sig); 47 return -EFAULT; 48 } 49 50 /* BAR1: doorbells */ 51 bar++; 52 if (num_bars < 2) { 53 IONIC_PRINT(ERR, "Doorbell bar missing, aborting"); 54 return -EFAULT; 55 } 56 57 idev->db_pages = bar->vaddr; 58 idev->phy_db_pages = bar->bus_addr; 59 60 return 0; 61 } 62 63 /* Devcmd Interface */ 64 65 uint8_t 66 ionic_dev_cmd_status(struct ionic_dev *idev) 67 { 68 return ioread8(&idev->dev_cmd->comp.comp.status); 69 } 70 71 bool 72 ionic_dev_cmd_done(struct ionic_dev *idev) 73 { 74 return ioread32(&idev->dev_cmd->done) & IONIC_DEV_CMD_DONE; 75 } 76 77 void 78 ionic_dev_cmd_comp(struct ionic_dev *idev, void *mem) 79 { 80 union ionic_dev_cmd_comp *comp = mem; 81 unsigned int i; 82 uint32_t comp_size = sizeof(comp->words) / 83 sizeof(comp->words[0]); 84 85 for (i = 0; i < comp_size; i++) 86 comp->words[i] = ioread32(&idev->dev_cmd->comp.words[i]); 87 } 88 89 void 90 ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd) 91 { 92 unsigned int i; 93 uint32_t cmd_size = sizeof(cmd->words) / 94 sizeof(cmd->words[0]); 95 96 for (i = 0; i < cmd_size; i++) 97 iowrite32(cmd->words[i], &idev->dev_cmd->cmd.words[i]); 98 99 iowrite32(0, &idev->dev_cmd->done); 100 iowrite32(1, &idev->dev_cmd->doorbell); 101 } 102 103 /* Device commands */ 104 105 void 106 ionic_dev_cmd_identify(struct ionic_dev *idev, uint8_t ver) 107 { 108 union ionic_dev_cmd cmd = { 109 .identify.opcode = IONIC_CMD_IDENTIFY, 110 .identify.ver = ver, 111 }; 112 113 ionic_dev_cmd_go(idev, &cmd); 114 } 115 116 void 117 ionic_dev_cmd_init(struct ionic_dev *idev) 118 { 119 union ionic_dev_cmd cmd = { 120 .init.opcode = IONIC_CMD_INIT, 121 .init.type = 0, 122 }; 123 124 ionic_dev_cmd_go(idev, &cmd); 125 } 126 127 void 128 ionic_dev_cmd_reset(struct ionic_dev *idev) 129 { 130 union ionic_dev_cmd cmd = { 131 .reset.opcode = IONIC_CMD_RESET, 132 }; 133 134 ionic_dev_cmd_go(idev, &cmd); 135 } 136 137 /* Port commands */ 138 139 void 140 ionic_dev_cmd_port_identify(struct ionic_dev *idev) 141 { 142 union ionic_dev_cmd cmd = { 143 .port_init.opcode = IONIC_CMD_PORT_IDENTIFY, 144 .port_init.index = 0, 145 }; 146 147 ionic_dev_cmd_go(idev, &cmd); 148 } 149 150 void 151 ionic_dev_cmd_port_init(struct ionic_dev *idev) 152 { 153 union ionic_dev_cmd cmd = { 154 .port_init.opcode = IONIC_CMD_PORT_INIT, 155 .port_init.index = 0, 156 .port_init.info_pa = idev->port_info_pa, 157 }; 158 159 ionic_dev_cmd_go(idev, &cmd); 160 } 161 162 void 163 ionic_dev_cmd_port_reset(struct ionic_dev *idev) 164 { 165 union ionic_dev_cmd cmd = { 166 .port_reset.opcode = IONIC_CMD_PORT_RESET, 167 .port_reset.index = 0, 168 }; 169 170 ionic_dev_cmd_go(idev, &cmd); 171 } 172 173 void 174 ionic_dev_cmd_port_state(struct ionic_dev *idev, uint8_t state) 175 { 176 union ionic_dev_cmd cmd = { 177 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 178 .port_setattr.index = 0, 179 .port_setattr.attr = IONIC_PORT_ATTR_STATE, 180 .port_setattr.state = state, 181 }; 182 183 ionic_dev_cmd_go(idev, &cmd); 184 } 185 186 void 187 ionic_dev_cmd_port_speed(struct ionic_dev *idev, uint32_t speed) 188 { 189 union ionic_dev_cmd cmd = { 190 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 191 .port_setattr.index = 0, 192 .port_setattr.attr = IONIC_PORT_ATTR_SPEED, 193 .port_setattr.speed = speed, 194 }; 195 196 ionic_dev_cmd_go(idev, &cmd); 197 } 198 199 void 200 ionic_dev_cmd_port_mtu(struct ionic_dev *idev, uint32_t mtu) 201 { 202 union ionic_dev_cmd cmd = { 203 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 204 .port_setattr.index = 0, 205 .port_setattr.attr = IONIC_PORT_ATTR_MTU, 206 .port_setattr.mtu = mtu, 207 }; 208 209 ionic_dev_cmd_go(idev, &cmd); 210 } 211 212 void 213 ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, uint8_t an_enable) 214 { 215 union ionic_dev_cmd cmd = { 216 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 217 .port_setattr.index = 0, 218 .port_setattr.attr = IONIC_PORT_ATTR_AUTONEG, 219 .port_setattr.an_enable = an_enable, 220 }; 221 222 ionic_dev_cmd_go(idev, &cmd); 223 } 224 225 void 226 ionic_dev_cmd_port_fec(struct ionic_dev *idev, uint8_t fec_type) 227 { 228 union ionic_dev_cmd cmd = { 229 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 230 .port_setattr.index = 0, 231 .port_setattr.attr = IONIC_PORT_ATTR_FEC, 232 .port_setattr.fec_type = fec_type, 233 }; 234 235 ionic_dev_cmd_go(idev, &cmd); 236 } 237 238 void 239 ionic_dev_cmd_port_pause(struct ionic_dev *idev, uint8_t pause_type) 240 { 241 union ionic_dev_cmd cmd = { 242 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 243 .port_setattr.index = 0, 244 .port_setattr.attr = IONIC_PORT_ATTR_PAUSE, 245 .port_setattr.pause_type = pause_type, 246 }; 247 248 ionic_dev_cmd_go(idev, &cmd); 249 } 250 251 void 252 ionic_dev_cmd_port_loopback(struct ionic_dev *idev, uint8_t loopback_mode) 253 { 254 union ionic_dev_cmd cmd = { 255 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 256 .port_setattr.index = 0, 257 .port_setattr.attr = IONIC_PORT_ATTR_LOOPBACK, 258 .port_setattr.loopback_mode = loopback_mode, 259 }; 260 261 ionic_dev_cmd_go(idev, &cmd); 262 } 263 264 /* LIF commands */ 265 266 void 267 ionic_dev_cmd_lif_identify(struct ionic_dev *idev, uint8_t type, uint8_t ver) 268 { 269 union ionic_dev_cmd cmd = { 270 .lif_identify.opcode = IONIC_CMD_LIF_IDENTIFY, 271 .lif_identify.type = type, 272 .lif_identify.ver = ver, 273 }; 274 275 ionic_dev_cmd_go(idev, &cmd); 276 } 277 278 void 279 ionic_dev_cmd_lif_init(struct ionic_dev *idev, uint16_t lif_index, 280 rte_iova_t info_pa) 281 { 282 union ionic_dev_cmd cmd = { 283 .lif_init.opcode = IONIC_CMD_LIF_INIT, 284 .lif_init.index = lif_index, 285 .lif_init.info_pa = info_pa, 286 }; 287 288 ionic_dev_cmd_go(idev, &cmd); 289 } 290 291 void 292 ionic_dev_cmd_lif_reset(struct ionic_dev *idev, uint16_t lif_index) 293 { 294 union ionic_dev_cmd cmd = { 295 .lif_init.opcode = IONIC_CMD_LIF_RESET, 296 .lif_init.index = lif_index, 297 }; 298 299 ionic_dev_cmd_go(idev, &cmd); 300 } 301 302 struct ionic_doorbell * 303 ionic_db_map(struct ionic_lif *lif, struct ionic_queue *q) 304 { 305 return lif->kern_dbpage + q->hw_type; 306 } 307 308 int 309 ionic_db_page_num(struct ionic_lif *lif, int pid) 310 { 311 return (lif->index * 0) + pid; 312 } 313 314 void 315 ionic_intr_init(struct ionic_dev *idev, struct ionic_intr_info *intr, 316 unsigned long index) 317 { 318 ionic_intr_clean(idev->intr_ctrl, index); 319 intr->index = index; 320 } 321 322 void 323 ionic_dev_cmd_adminq_init(struct ionic_dev *idev, 324 struct ionic_qcq *qcq, 325 uint16_t lif_index, uint16_t intr_index) 326 { 327 struct ionic_queue *q = &qcq->q; 328 struct ionic_cq *cq = &qcq->cq; 329 330 union ionic_dev_cmd cmd = { 331 .q_init.opcode = IONIC_CMD_Q_INIT, 332 .q_init.lif_index = lif_index, 333 .q_init.type = q->type, 334 .q_init.index = q->index, 335 .q_init.flags = IONIC_QINIT_F_ENA, 336 .q_init.pid = q->pid, 337 .q_init.intr_index = intr_index, 338 .q_init.ring_size = rte_log2_u32(q->num_descs), 339 .q_init.ring_base = q->base_pa, 340 .q_init.cq_ring_base = cq->base_pa, 341 }; 342 343 ionic_dev_cmd_go(idev, &cmd); 344 } 345 346 int 347 ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq, 348 struct ionic_intr_info *intr, 349 uint32_t num_descs, size_t desc_size) 350 { 351 if (desc_size == 0) { 352 IONIC_PRINT(ERR, "Descriptor size is %zu", desc_size); 353 return -EINVAL; 354 } 355 356 if (!rte_is_power_of_2(num_descs) || 357 num_descs < IONIC_MIN_RING_DESC || 358 num_descs > IONIC_MAX_RING_DESC) { 359 IONIC_PRINT(ERR, "%u descriptors (min: %u max: %u)", 360 num_descs, IONIC_MIN_RING_DESC, IONIC_MAX_RING_DESC); 361 return -EINVAL; 362 } 363 364 cq->lif = lif; 365 cq->bound_intr = intr; 366 cq->num_descs = num_descs; 367 cq->desc_size = desc_size; 368 cq->tail_idx = 0; 369 cq->done_color = 1; 370 371 return 0; 372 } 373 374 void 375 ionic_cq_map(struct ionic_cq *cq, void *base, rte_iova_t base_pa) 376 { 377 cq->base = base; 378 cq->base_pa = base_pa; 379 } 380 381 void 382 ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q) 383 { 384 cq->bound_q = q; 385 q->bound_cq = cq; 386 } 387 388 uint32_t 389 ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do, 390 ionic_cq_cb cb, void *cb_arg) 391 { 392 uint32_t work_done = 0; 393 394 if (work_to_do == 0) 395 return 0; 396 397 while (cb(cq, cq->tail_idx, cb_arg)) { 398 cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1); 399 if (cq->tail_idx == 0) 400 cq->done_color = !cq->done_color; 401 402 if (++work_done == work_to_do) 403 break; 404 } 405 406 return work_done; 407 } 408 409 int 410 ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev, 411 struct ionic_queue *q, uint32_t index, uint32_t num_descs, 412 size_t desc_size, size_t sg_desc_size, uint32_t pid) 413 { 414 uint32_t ring_size; 415 416 if (desc_size == 0 || !rte_is_power_of_2(num_descs)) 417 return -EINVAL; 418 419 ring_size = rte_log2_u32(num_descs); 420 421 if (ring_size < 2 || ring_size > 16) 422 return -EINVAL; 423 424 q->lif = lif; 425 q->idev = idev; 426 q->index = index; 427 q->num_descs = num_descs; 428 q->desc_size = desc_size; 429 q->sg_desc_size = sg_desc_size; 430 q->head_idx = 0; 431 q->tail_idx = 0; 432 q->pid = pid; 433 434 return 0; 435 } 436 437 void 438 ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa) 439 { 440 q->base = base; 441 q->base_pa = base_pa; 442 } 443 444 void 445 ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa) 446 { 447 q->sg_base = base; 448 q->sg_base_pa = base_pa; 449 } 450 451 void 452 ionic_q_flush(struct ionic_queue *q) 453 { 454 writeq(IONIC_DBELL_QID(q->hw_index) | q->head_idx, q->db); 455 } 456 457 void 458 ionic_q_post(struct ionic_queue *q, bool ring_doorbell, desc_cb cb, 459 void *cb_arg) 460 { 461 struct ionic_desc_info *head = &q->info[q->head_idx]; 462 463 head->cb = cb; 464 head->cb_arg = cb_arg; 465 466 q->head_idx = (q->head_idx + 1) & (q->num_descs - 1); 467 468 if (ring_doorbell) 469 ionic_q_flush(q); 470 } 471 472 uint32_t 473 ionic_q_space_avail(struct ionic_queue *q) 474 { 475 uint32_t avail = q->tail_idx; 476 477 if (q->head_idx >= avail) 478 avail += q->num_descs - q->head_idx - 1; 479 else 480 avail -= q->head_idx + 1; 481 482 return avail; 483 } 484 485 bool 486 ionic_q_has_space(struct ionic_queue *q, uint32_t want) 487 { 488 return ionic_q_space_avail(q) >= want; 489 } 490 491 void 492 ionic_q_service(struct ionic_queue *q, uint32_t cq_desc_index, 493 uint32_t stop_index, void *service_cb_arg) 494 { 495 struct ionic_desc_info *desc_info; 496 uint32_t curr_q_tail_idx; 497 498 do { 499 desc_info = &q->info[q->tail_idx]; 500 501 if (desc_info->cb) 502 desc_info->cb(q, q->tail_idx, cq_desc_index, 503 desc_info->cb_arg, service_cb_arg); 504 505 desc_info->cb = NULL; 506 desc_info->cb_arg = NULL; 507 508 curr_q_tail_idx = q->tail_idx; 509 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 510 511 } while (curr_q_tail_idx != stop_index); 512 } 513 514 static void 515 ionic_adminq_cb(struct ionic_queue *q, 516 uint32_t q_desc_index, uint32_t cq_desc_index, 517 void *cb_arg, void *service_cb_arg __rte_unused) 518 { 519 struct ionic_admin_ctx *ctx = cb_arg; 520 struct ionic_admin_comp *cq_desc_base = q->bound_cq->base; 521 struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index]; 522 523 if (unlikely(cq_desc->comp_index != q_desc_index)) { 524 IONIC_WARN_ON(cq_desc->comp_index != q_desc_index); 525 return; 526 } 527 528 memcpy(&ctx->comp, cq_desc, sizeof(*cq_desc)); 529 530 ctx->pending_work = false; /* done */ 531 } 532 533 /** ionic_adminq_post - Post an admin command. 534 * @lif: Handle to lif. 535 * @cmd_ctx: Api admin command context. 536 * 537 * Post the command to an admin queue in the ethernet driver. If this command 538 * succeeds, then the command has been posted, but that does not indicate a 539 * completion. If this command returns success, then the completion callback 540 * will eventually be called. 541 * 542 * Return: zero or negative error status. 543 */ 544 int 545 ionic_adminq_post(struct ionic_lif *lif, struct ionic_admin_ctx *ctx) 546 { 547 struct ionic_queue *adminq = &lif->adminqcq->q; 548 struct ionic_admin_cmd *q_desc_base = adminq->base; 549 struct ionic_admin_cmd *q_desc; 550 int err = 0; 551 552 rte_spinlock_lock(&lif->adminq_lock); 553 554 if (!ionic_q_has_space(adminq, 1)) { 555 err = -ENOSPC; 556 goto err_out; 557 } 558 559 q_desc = &q_desc_base[adminq->head_idx]; 560 561 memcpy(q_desc, &ctx->cmd, sizeof(ctx->cmd)); 562 563 ionic_q_post(adminq, true, ionic_adminq_cb, ctx); 564 565 err_out: 566 rte_spinlock_unlock(&lif->adminq_lock); 567 568 return err; 569 } 570