1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2019-2020 Intel Corporation 3 */ 4 5 #ifndef _IGC_ETHDEV_H_ 6 #define _IGC_ETHDEV_H_ 7 8 #include <rte_ethdev.h> 9 10 #include "base/igc_osdep.h" 11 #include "base/igc_hw.h" 12 #include "base/igc_i225.h" 13 #include "base/igc_api.h" 14 15 #ifdef __cplusplus 16 extern "C" { 17 #endif 18 19 #define IGC_QUEUE_PAIRS_NUM 4 20 21 #define IGC_HKEY_MAX_INDEX 10 22 #define IGC_RSS_RDT_SIZD 128 23 24 /* 25 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 26 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. 27 * This will also optimize cache line size effect. 28 * H/W supports up to cache line size 128. 29 */ 30 #define IGC_ALIGN 128 31 32 #define IGC_TX_DESCRIPTOR_MULTIPLE 8 33 #define IGC_RX_DESCRIPTOR_MULTIPLE 8 34 35 #define IGC_RXD_ALIGN ((uint16_t)(IGC_ALIGN / \ 36 sizeof(union igc_adv_rx_desc))) 37 #define IGC_TXD_ALIGN ((uint16_t)(IGC_ALIGN / \ 38 sizeof(union igc_adv_tx_desc))) 39 #define IGC_MIN_TXD IGC_TX_DESCRIPTOR_MULTIPLE 40 #define IGC_MAX_TXD ((uint16_t)(0x80000 / sizeof(union igc_adv_tx_desc))) 41 #define IGC_MIN_RXD IGC_RX_DESCRIPTOR_MULTIPLE 42 #define IGC_MAX_RXD ((uint16_t)(0x80000 / sizeof(union igc_adv_rx_desc))) 43 44 #define IGC_TX_MAX_SEG UINT8_MAX 45 #define IGC_TX_MAX_MTU_SEG UINT8_MAX 46 47 #define IGC_RX_OFFLOAD_ALL ( \ 48 DEV_RX_OFFLOAD_IPV4_CKSUM | \ 49 DEV_RX_OFFLOAD_UDP_CKSUM | \ 50 DEV_RX_OFFLOAD_TCP_CKSUM | \ 51 DEV_RX_OFFLOAD_SCTP_CKSUM | \ 52 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 53 DEV_RX_OFFLOAD_KEEP_CRC | \ 54 DEV_RX_OFFLOAD_SCATTER) 55 56 #define IGC_TX_OFFLOAD_ALL ( \ 57 DEV_TX_OFFLOAD_VLAN_INSERT | \ 58 DEV_TX_OFFLOAD_IPV4_CKSUM | \ 59 DEV_TX_OFFLOAD_UDP_CKSUM | \ 60 DEV_TX_OFFLOAD_TCP_CKSUM | \ 61 DEV_TX_OFFLOAD_SCTP_CKSUM | \ 62 DEV_TX_OFFLOAD_TCP_TSO | \ 63 DEV_TX_OFFLOAD_UDP_TSO | \ 64 DEV_TX_OFFLOAD_MULTI_SEGS) 65 66 #define IGC_RSS_OFFLOAD_ALL ( \ 67 ETH_RSS_IPV4 | \ 68 ETH_RSS_NONFRAG_IPV4_TCP | \ 69 ETH_RSS_NONFRAG_IPV4_UDP | \ 70 ETH_RSS_IPV6 | \ 71 ETH_RSS_NONFRAG_IPV6_TCP | \ 72 ETH_RSS_NONFRAG_IPV6_UDP | \ 73 ETH_RSS_IPV6_EX | \ 74 ETH_RSS_IPV6_TCP_EX | \ 75 ETH_RSS_IPV6_UDP_EX) 76 77 /* structure for interrupt relative data */ 78 struct igc_interrupt { 79 uint32_t flags; 80 uint32_t mask; 81 }; 82 83 /* Union of RSS redirect table register */ 84 union igc_rss_reta_reg { 85 uint32_t dword; 86 uint8_t bytes[4]; 87 }; 88 89 /* Structure to per-queue statics */ 90 struct igc_hw_queue_stats { 91 u64 pqgprc[IGC_QUEUE_PAIRS_NUM]; 92 /* per queue good packets received count */ 93 u64 pqgptc[IGC_QUEUE_PAIRS_NUM]; 94 /* per queue good packets transmitted count */ 95 u64 pqgorc[IGC_QUEUE_PAIRS_NUM]; 96 /* per queue good octets received count */ 97 u64 pqgotc[IGC_QUEUE_PAIRS_NUM]; 98 /* per queue good octets transmitted count */ 99 u64 pqmprc[IGC_QUEUE_PAIRS_NUM]; 100 /* per queue multicast packets received count */ 101 u64 rqdpc[IGC_QUEUE_PAIRS_NUM]; 102 /* per receive queue drop packet count */ 103 u64 tqdpc[IGC_QUEUE_PAIRS_NUM]; 104 /* per transmit queue drop packet count */ 105 }; 106 107 /* 108 * Structure to store private data for each driver instance (for each port). 109 */ 110 struct igc_adapter { 111 struct igc_hw hw; 112 struct igc_hw_stats stats; 113 struct igc_hw_queue_stats queue_stats; 114 int16_t txq_stats_map[IGC_QUEUE_PAIRS_NUM]; 115 int16_t rxq_stats_map[IGC_QUEUE_PAIRS_NUM]; 116 117 struct igc_interrupt intr; 118 bool stopped; 119 }; 120 121 #define IGC_DEV_PRIVATE(_dev) ((_dev)->data->dev_private) 122 123 #define IGC_DEV_PRIVATE_HW(_dev) \ 124 (&((struct igc_adapter *)(_dev)->data->dev_private)->hw) 125 126 #define IGC_DEV_PRIVATE_STATS(_dev) \ 127 (&((struct igc_adapter *)(_dev)->data->dev_private)->stats) 128 129 #define IGC_DEV_PRIVATE_QUEUE_STATS(_dev) \ 130 (&((struct igc_adapter *)(_dev)->data->dev_private)->queue_stats) 131 132 #define IGC_DEV_PRIVATE_INTR(_dev) \ 133 (&((struct igc_adapter *)(_dev)->data->dev_private)->intr) 134 135 static inline void 136 igc_read_reg_check_set_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits) 137 { 138 uint32_t reg_val = IGC_READ_REG(hw, reg); 139 140 bits |= reg_val; 141 if (bits == reg_val) 142 return; /* no need to write back */ 143 144 IGC_WRITE_REG(hw, reg, bits); 145 } 146 147 static inline void 148 igc_read_reg_check_clear_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits) 149 { 150 uint32_t reg_val = IGC_READ_REG(hw, reg); 151 152 bits = reg_val & ~bits; 153 if (bits == reg_val) 154 return; /* no need to write back */ 155 156 IGC_WRITE_REG(hw, reg, bits); 157 } 158 159 #ifdef __cplusplus 160 } 161 #endif 162 163 #endif /* _IGC_ETHDEV_H_ */ 164