1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2019-2020 Intel Corporation 3 */ 4 5 #ifndef _IGC_ETHDEV_H_ 6 #define _IGC_ETHDEV_H_ 7 8 #include <rte_ethdev.h> 9 #include <rte_flow.h> 10 11 #include "base/igc_osdep.h" 12 #include "base/igc_hw.h" 13 #include "base/igc_i225.h" 14 #include "base/igc_api.h" 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 #define IGC_RSS_RDT_SIZD 128 21 22 /* VLAN filter table size */ 23 #define IGC_VFTA_SIZE 128 24 25 #define IGC_QUEUE_PAIRS_NUM 4 26 27 #define IGC_HKEY_MAX_INDEX 10 28 #define IGC_RSS_RDT_SIZD 128 29 30 #define IGC_DEFAULT_REG_SIZE 4 31 #define IGC_DEFAULT_REG_SIZE_MASK 0xf 32 33 #define IGC_RSS_RDT_REG_SIZE IGC_DEFAULT_REG_SIZE 34 #define IGC_RSS_RDT_REG_SIZE_MASK IGC_DEFAULT_REG_SIZE_MASK 35 #define IGC_HKEY_REG_SIZE IGC_DEFAULT_REG_SIZE 36 #define IGC_HKEY_SIZE (IGC_HKEY_REG_SIZE * IGC_HKEY_MAX_INDEX) 37 38 /* 39 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 40 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. 41 * This will also optimize cache line size effect. 42 * H/W supports up to cache line size 128. 43 */ 44 #define IGC_ALIGN 128 45 46 #define IGC_TX_DESCRIPTOR_MULTIPLE 8 47 #define IGC_RX_DESCRIPTOR_MULTIPLE 8 48 49 #define IGC_RXD_ALIGN ((uint16_t)(IGC_ALIGN / \ 50 sizeof(union igc_adv_rx_desc))) 51 #define IGC_TXD_ALIGN ((uint16_t)(IGC_ALIGN / \ 52 sizeof(union igc_adv_tx_desc))) 53 #define IGC_MIN_TXD IGC_TX_DESCRIPTOR_MULTIPLE 54 #define IGC_MAX_TXD ((uint16_t)(0x80000 / sizeof(union igc_adv_tx_desc))) 55 #define IGC_MIN_RXD IGC_RX_DESCRIPTOR_MULTIPLE 56 #define IGC_MAX_RXD ((uint16_t)(0x80000 / sizeof(union igc_adv_rx_desc))) 57 58 #define IGC_TX_MAX_SEG UINT8_MAX 59 #define IGC_TX_MAX_MTU_SEG UINT8_MAX 60 61 #define IGC_RX_OFFLOAD_ALL ( \ 62 DEV_RX_OFFLOAD_VLAN_STRIP | \ 63 DEV_RX_OFFLOAD_VLAN_FILTER | \ 64 DEV_RX_OFFLOAD_VLAN_EXTEND | \ 65 DEV_RX_OFFLOAD_IPV4_CKSUM | \ 66 DEV_RX_OFFLOAD_UDP_CKSUM | \ 67 DEV_RX_OFFLOAD_TCP_CKSUM | \ 68 DEV_RX_OFFLOAD_SCTP_CKSUM | \ 69 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 70 DEV_RX_OFFLOAD_KEEP_CRC | \ 71 DEV_RX_OFFLOAD_SCATTER | \ 72 DEV_RX_OFFLOAD_RSS_HASH) 73 74 #define IGC_TX_OFFLOAD_ALL ( \ 75 DEV_TX_OFFLOAD_VLAN_INSERT | \ 76 DEV_TX_OFFLOAD_IPV4_CKSUM | \ 77 DEV_TX_OFFLOAD_UDP_CKSUM | \ 78 DEV_TX_OFFLOAD_TCP_CKSUM | \ 79 DEV_TX_OFFLOAD_SCTP_CKSUM | \ 80 DEV_TX_OFFLOAD_TCP_TSO | \ 81 DEV_TX_OFFLOAD_UDP_TSO | \ 82 DEV_TX_OFFLOAD_MULTI_SEGS) 83 84 #define IGC_RSS_OFFLOAD_ALL ( \ 85 ETH_RSS_IPV4 | \ 86 ETH_RSS_NONFRAG_IPV4_TCP | \ 87 ETH_RSS_NONFRAG_IPV4_UDP | \ 88 ETH_RSS_IPV6 | \ 89 ETH_RSS_NONFRAG_IPV6_TCP | \ 90 ETH_RSS_NONFRAG_IPV6_UDP | \ 91 ETH_RSS_IPV6_EX | \ 92 ETH_RSS_IPV6_TCP_EX | \ 93 ETH_RSS_IPV6_UDP_EX) 94 95 #define IGC_MAX_ETQF_FILTERS 3 /* etqf(3) is used for 1588 */ 96 #define IGC_ETQF_FILTER_1588 3 97 #define IGC_ETQF_QUEUE_SHIFT 16 98 #define IGC_ETQF_QUEUE_MASK (7u << IGC_ETQF_QUEUE_SHIFT) 99 100 #define IGC_MAX_NTUPLE_FILTERS 8 101 #define IGC_NTUPLE_MAX_PRI 7 102 103 #define IGC_SYN_FILTER_ENABLE 0x01 /* syn filter enable field */ 104 #define IGC_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field */ 105 #define IGC_SYN_FILTER_QUEUE 0x0000000E /* syn filter queue field */ 106 #define IGC_RFCTL_SYNQFP 0x00080000 /* SYNQFP in RFCTL register */ 107 108 /* structure for interrupt relative data */ 109 struct igc_interrupt { 110 uint32_t flags; 111 uint32_t mask; 112 }; 113 114 /* Union of RSS redirect table register */ 115 union igc_rss_reta_reg { 116 uint32_t dword; 117 uint8_t bytes[4]; 118 }; 119 120 /* Structure to per-queue statics */ 121 struct igc_hw_queue_stats { 122 u64 pqgprc[IGC_QUEUE_PAIRS_NUM]; 123 /* per queue good packets received count */ 124 u64 pqgptc[IGC_QUEUE_PAIRS_NUM]; 125 /* per queue good packets transmitted count */ 126 u64 pqgorc[IGC_QUEUE_PAIRS_NUM]; 127 /* per queue good octets received count */ 128 u64 pqgotc[IGC_QUEUE_PAIRS_NUM]; 129 /* per queue good octets transmitted count */ 130 u64 pqmprc[IGC_QUEUE_PAIRS_NUM]; 131 /* per queue multicast packets received count */ 132 u64 rqdpc[IGC_QUEUE_PAIRS_NUM]; 133 /* per receive queue drop packet count */ 134 u64 tqdpc[IGC_QUEUE_PAIRS_NUM]; 135 /* per transmit queue drop packet count */ 136 }; 137 138 /* local vfta copy */ 139 struct igc_vfta { 140 uint32_t vfta[IGC_VFTA_SIZE]; 141 }; 142 143 /* ethertype filter structure */ 144 struct igc_ethertype_filter { 145 uint16_t ether_type; 146 uint16_t queue; 147 }; 148 149 /* Structure of ntuple filter info. */ 150 struct igc_ntuple_info { 151 uint16_t dst_port; 152 uint8_t proto; /* l4 protocol. */ 153 154 /* 155 * the packet matched above 2tuple and contain any set bit will hit 156 * this filter. 157 */ 158 uint8_t tcp_flags; 159 160 /* 161 * seven levels (001b-111b), 111b is highest, used when more than one 162 * filter matches. 163 */ 164 uint8_t priority; 165 uint8_t dst_port_mask:1, /* if mask is 1b, do compare dst port. */ 166 proto_mask:1; /* if mask is 1b, do compare protocol. */ 167 }; 168 169 /* Structure of n-tuple filter */ 170 struct igc_ntuple_filter { 171 RTE_STD_C11 172 union { 173 uint64_t hash_val; 174 struct igc_ntuple_info tuple_info; 175 }; 176 177 uint8_t queue; 178 }; 179 180 /* Structure of TCP SYN filter */ 181 struct igc_syn_filter { 182 uint8_t queue; 183 184 uint8_t hig_pri:1, /* 1 - higher priority than other filters, */ 185 /* 0 - lower priority. */ 186 enable:1; /* 1-enable; 0-disable */ 187 }; 188 189 /* Structure to store RTE flow RSS configure. */ 190 struct igc_rss_filter { 191 struct rte_flow_action_rss conf; /* RSS parameters. */ 192 uint8_t key[IGC_HKEY_MAX_INDEX * sizeof(uint32_t)]; /* Hash key. */ 193 uint16_t queue[IGC_RSS_RDT_SIZD];/* Queues indices to use. */ 194 uint8_t enable; /* 1-enabled, 0-disabled */ 195 }; 196 197 /* Feature filter types */ 198 enum igc_filter_type { 199 IGC_FILTER_TYPE_ETHERTYPE, 200 IGC_FILTER_TYPE_NTUPLE, 201 IGC_FILTER_TYPE_SYN, 202 IGC_FILTER_TYPE_HASH 203 }; 204 205 /* Structure to store flow */ 206 struct rte_flow { 207 TAILQ_ENTRY(rte_flow) node; 208 enum igc_filter_type filter_type; 209 RTE_STD_C11 210 char filter[0]; /* filter data */ 211 }; 212 213 /* Flow list header */ 214 TAILQ_HEAD(igc_flow_list, rte_flow); 215 216 /* 217 * Structure to store private data for each driver instance (for each port). 218 */ 219 struct igc_adapter { 220 struct igc_hw hw; 221 struct igc_hw_stats stats; 222 struct igc_hw_queue_stats queue_stats; 223 int16_t txq_stats_map[IGC_QUEUE_PAIRS_NUM]; 224 int16_t rxq_stats_map[IGC_QUEUE_PAIRS_NUM]; 225 226 struct igc_interrupt intr; 227 struct igc_vfta shadow_vfta; 228 bool stopped; 229 230 struct igc_ethertype_filter ethertype_filters[IGC_MAX_ETQF_FILTERS]; 231 struct igc_ntuple_filter ntuple_filters[IGC_MAX_NTUPLE_FILTERS]; 232 struct igc_syn_filter syn_filter; 233 struct igc_rss_filter rss_filter; 234 struct igc_flow_list flow_list; 235 }; 236 237 #define IGC_DEV_PRIVATE(_dev) ((_dev)->data->dev_private) 238 239 #define IGC_DEV_PRIVATE_HW(_dev) \ 240 (&((struct igc_adapter *)(_dev)->data->dev_private)->hw) 241 242 #define IGC_DEV_PRIVATE_STATS(_dev) \ 243 (&((struct igc_adapter *)(_dev)->data->dev_private)->stats) 244 245 #define IGC_DEV_PRIVATE_QUEUE_STATS(_dev) \ 246 (&((struct igc_adapter *)(_dev)->data->dev_private)->queue_stats) 247 248 #define IGC_DEV_PRIVATE_INTR(_dev) \ 249 (&((struct igc_adapter *)(_dev)->data->dev_private)->intr) 250 251 #define IGC_DEV_PRIVATE_VFTA(_dev) \ 252 (&((struct igc_adapter *)(_dev)->data->dev_private)->shadow_vfta) 253 254 #define IGC_DEV_PRIVATE_RSS_FILTER(_dev) \ 255 (&((struct igc_adapter *)(_dev)->data->dev_private)->rss_filter) 256 257 #define IGC_DEV_PRIVATE_FLOW_LIST(_dev) \ 258 (&((struct igc_adapter *)(_dev)->data->dev_private)->flow_list) 259 260 static inline void 261 igc_read_reg_check_set_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits) 262 { 263 uint32_t reg_val = IGC_READ_REG(hw, reg); 264 265 bits |= reg_val; 266 if (bits == reg_val) 267 return; /* no need to write back */ 268 269 IGC_WRITE_REG(hw, reg, bits); 270 } 271 272 static inline void 273 igc_read_reg_check_clear_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits) 274 { 275 uint32_t reg_val = IGC_READ_REG(hw, reg); 276 277 bits = reg_val & ~bits; 278 if (bits == reg_val) 279 return; /* no need to write back */ 280 281 IGC_WRITE_REG(hw, reg, bits); 282 } 283 284 #ifdef __cplusplus 285 } 286 #endif 287 288 #endif /* _IGC_ETHDEV_H_ */ 289