1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2019-2020 Intel Corporation 3 */ 4 5 #include <stdint.h> 6 #include <string.h> 7 8 #include <rte_string_fns.h> 9 #include <rte_pci.h> 10 #include <rte_bus_pci.h> 11 #include <ethdev_driver.h> 12 #include <ethdev_pci.h> 13 #include <rte_malloc.h> 14 #include <rte_alarm.h> 15 16 #include "igc_logs.h" 17 #include "igc_txrx.h" 18 #include "igc_filter.h" 19 #include "igc_flow.h" 20 21 #define IGC_INTEL_VENDOR_ID 0x8086 22 23 #define IGC_FC_PAUSE_TIME 0x0680 24 #define IGC_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */ 25 #define IGC_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */ 26 27 #define IGC_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 28 #define IGC_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 29 #define IGC_MSIX_OTHER_INTR_VEC 0 /* MSI-X other interrupt vector */ 30 #define IGC_FLAG_NEED_LINK_UPDATE (1u << 0) /* need update link */ 31 32 #define IGC_DEFAULT_RX_FREE_THRESH 32 33 34 #define IGC_DEFAULT_RX_PTHRESH 8 35 #define IGC_DEFAULT_RX_HTHRESH 8 36 #define IGC_DEFAULT_RX_WTHRESH 4 37 38 #define IGC_DEFAULT_TX_PTHRESH 8 39 #define IGC_DEFAULT_TX_HTHRESH 1 40 #define IGC_DEFAULT_TX_WTHRESH 16 41 42 /* MSI-X other interrupt vector */ 43 #define IGC_MSIX_OTHER_INTR_VEC 0 44 45 /* External VLAN Enable bit mask */ 46 #define IGC_CTRL_EXT_EXT_VLAN (1u << 26) 47 48 /* Speed select */ 49 #define IGC_CTRL_SPEED_MASK (7u << 8) 50 #define IGC_CTRL_SPEED_2500 (6u << 8) 51 52 /* External VLAN Ether Type bit mask and shift */ 53 #define IGC_VET_EXT 0xFFFF0000 54 #define IGC_VET_EXT_SHIFT 16 55 56 /* Force EEE Auto-negotiation */ 57 #define IGC_EEER_EEE_FRC_AN (1u << 28) 58 59 /* Per Queue Good Packets Received Count */ 60 #define IGC_PQGPRC(idx) (0x10010 + 0x100 * (idx)) 61 /* Per Queue Good Octets Received Count */ 62 #define IGC_PQGORC(idx) (0x10018 + 0x100 * (idx)) 63 /* Per Queue Good Octets Transmitted Count */ 64 #define IGC_PQGOTC(idx) (0x10034 + 0x100 * (idx)) 65 /* Per Queue Multicast Packets Received Count */ 66 #define IGC_PQMPRC(idx) (0x10038 + 0x100 * (idx)) 67 /* Transmit Queue Drop Packet Count */ 68 #define IGC_TQDPC(idx) (0xe030 + 0x40 * (idx)) 69 70 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 71 #define U32_0_IN_U64 0 /* lower bytes of u64 */ 72 #define U32_1_IN_U64 1 /* higher bytes of u64 */ 73 #else 74 #define U32_0_IN_U64 1 75 #define U32_1_IN_U64 0 76 #endif 77 78 #define IGC_ALARM_INTERVAL 8000000u 79 /* us, about 13.6s some per-queue registers will wrap around back to 0. */ 80 81 static const struct rte_eth_desc_lim rx_desc_lim = { 82 .nb_max = IGC_MAX_RXD, 83 .nb_min = IGC_MIN_RXD, 84 .nb_align = IGC_RXD_ALIGN, 85 }; 86 87 static const struct rte_eth_desc_lim tx_desc_lim = { 88 .nb_max = IGC_MAX_TXD, 89 .nb_min = IGC_MIN_TXD, 90 .nb_align = IGC_TXD_ALIGN, 91 .nb_seg_max = IGC_TX_MAX_SEG, 92 .nb_mtu_seg_max = IGC_TX_MAX_MTU_SEG, 93 }; 94 95 static const struct rte_pci_id pci_id_igc_map[] = { 96 { RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_LM) }, 97 { RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_V) }, 98 { RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_I) }, 99 { RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_K) }, 100 { .vendor_id = 0, /* sentinel */ }, 101 }; 102 103 /* store statistics names and its offset in stats structure */ 104 struct rte_igc_xstats_name_off { 105 char name[RTE_ETH_XSTATS_NAME_SIZE]; 106 unsigned int offset; 107 }; 108 109 static const struct rte_igc_xstats_name_off rte_igc_stats_strings[] = { 110 {"rx_crc_errors", offsetof(struct igc_hw_stats, crcerrs)}, 111 {"rx_align_errors", offsetof(struct igc_hw_stats, algnerrc)}, 112 {"rx_errors", offsetof(struct igc_hw_stats, rxerrc)}, 113 {"rx_missed_packets", offsetof(struct igc_hw_stats, mpc)}, 114 {"tx_single_collision_packets", offsetof(struct igc_hw_stats, scc)}, 115 {"tx_multiple_collision_packets", offsetof(struct igc_hw_stats, mcc)}, 116 {"tx_excessive_collision_packets", offsetof(struct igc_hw_stats, 117 ecol)}, 118 {"tx_late_collisions", offsetof(struct igc_hw_stats, latecol)}, 119 {"tx_total_collisions", offsetof(struct igc_hw_stats, colc)}, 120 {"tx_deferred_packets", offsetof(struct igc_hw_stats, dc)}, 121 {"tx_no_carrier_sense_packets", offsetof(struct igc_hw_stats, tncrs)}, 122 {"tx_discarded_packets", offsetof(struct igc_hw_stats, htdpmc)}, 123 {"rx_length_errors", offsetof(struct igc_hw_stats, rlec)}, 124 {"rx_xon_packets", offsetof(struct igc_hw_stats, xonrxc)}, 125 {"tx_xon_packets", offsetof(struct igc_hw_stats, xontxc)}, 126 {"rx_xoff_packets", offsetof(struct igc_hw_stats, xoffrxc)}, 127 {"tx_xoff_packets", offsetof(struct igc_hw_stats, xofftxc)}, 128 {"rx_flow_control_unsupported_packets", offsetof(struct igc_hw_stats, 129 fcruc)}, 130 {"rx_size_64_packets", offsetof(struct igc_hw_stats, prc64)}, 131 {"rx_size_65_to_127_packets", offsetof(struct igc_hw_stats, prc127)}, 132 {"rx_size_128_to_255_packets", offsetof(struct igc_hw_stats, prc255)}, 133 {"rx_size_256_to_511_packets", offsetof(struct igc_hw_stats, prc511)}, 134 {"rx_size_512_to_1023_packets", offsetof(struct igc_hw_stats, 135 prc1023)}, 136 {"rx_size_1024_to_max_packets", offsetof(struct igc_hw_stats, 137 prc1522)}, 138 {"rx_broadcast_packets", offsetof(struct igc_hw_stats, bprc)}, 139 {"rx_multicast_packets", offsetof(struct igc_hw_stats, mprc)}, 140 {"rx_undersize_errors", offsetof(struct igc_hw_stats, ruc)}, 141 {"rx_fragment_errors", offsetof(struct igc_hw_stats, rfc)}, 142 {"rx_oversize_errors", offsetof(struct igc_hw_stats, roc)}, 143 {"rx_jabber_errors", offsetof(struct igc_hw_stats, rjc)}, 144 {"rx_no_buffers", offsetof(struct igc_hw_stats, rnbc)}, 145 {"rx_management_packets", offsetof(struct igc_hw_stats, mgprc)}, 146 {"rx_management_dropped", offsetof(struct igc_hw_stats, mgpdc)}, 147 {"tx_management_packets", offsetof(struct igc_hw_stats, mgptc)}, 148 {"rx_total_packets", offsetof(struct igc_hw_stats, tpr)}, 149 {"tx_total_packets", offsetof(struct igc_hw_stats, tpt)}, 150 {"rx_total_bytes", offsetof(struct igc_hw_stats, tor)}, 151 {"tx_total_bytes", offsetof(struct igc_hw_stats, tot)}, 152 {"tx_size_64_packets", offsetof(struct igc_hw_stats, ptc64)}, 153 {"tx_size_65_to_127_packets", offsetof(struct igc_hw_stats, ptc127)}, 154 {"tx_size_128_to_255_packets", offsetof(struct igc_hw_stats, ptc255)}, 155 {"tx_size_256_to_511_packets", offsetof(struct igc_hw_stats, ptc511)}, 156 {"tx_size_512_to_1023_packets", offsetof(struct igc_hw_stats, 157 ptc1023)}, 158 {"tx_size_1023_to_max_packets", offsetof(struct igc_hw_stats, 159 ptc1522)}, 160 {"tx_multicast_packets", offsetof(struct igc_hw_stats, mptc)}, 161 {"tx_broadcast_packets", offsetof(struct igc_hw_stats, bptc)}, 162 {"tx_tso_packets", offsetof(struct igc_hw_stats, tsctc)}, 163 {"rx_sent_to_host_packets", offsetof(struct igc_hw_stats, rpthc)}, 164 {"tx_sent_by_host_packets", offsetof(struct igc_hw_stats, hgptc)}, 165 {"interrupt_assert_count", offsetof(struct igc_hw_stats, iac)}, 166 {"rx_descriptor_lower_threshold", 167 offsetof(struct igc_hw_stats, icrxdmtc)}, 168 }; 169 170 #define IGC_NB_XSTATS (sizeof(rte_igc_stats_strings) / \ 171 sizeof(rte_igc_stats_strings[0])) 172 173 static int eth_igc_configure(struct rte_eth_dev *dev); 174 static int eth_igc_link_update(struct rte_eth_dev *dev, int wait_to_complete); 175 static int eth_igc_stop(struct rte_eth_dev *dev); 176 static int eth_igc_start(struct rte_eth_dev *dev); 177 static int eth_igc_set_link_up(struct rte_eth_dev *dev); 178 static int eth_igc_set_link_down(struct rte_eth_dev *dev); 179 static int eth_igc_close(struct rte_eth_dev *dev); 180 static int eth_igc_reset(struct rte_eth_dev *dev); 181 static int eth_igc_promiscuous_enable(struct rte_eth_dev *dev); 182 static int eth_igc_promiscuous_disable(struct rte_eth_dev *dev); 183 static int eth_igc_fw_version_get(struct rte_eth_dev *dev, 184 char *fw_version, size_t fw_size); 185 static int eth_igc_infos_get(struct rte_eth_dev *dev, 186 struct rte_eth_dev_info *dev_info); 187 static int eth_igc_led_on(struct rte_eth_dev *dev); 188 static int eth_igc_led_off(struct rte_eth_dev *dev); 189 static const uint32_t *eth_igc_supported_ptypes_get(struct rte_eth_dev *dev); 190 static int eth_igc_rar_set(struct rte_eth_dev *dev, 191 struct rte_ether_addr *mac_addr, uint32_t index, uint32_t pool); 192 static void eth_igc_rar_clear(struct rte_eth_dev *dev, uint32_t index); 193 static int eth_igc_default_mac_addr_set(struct rte_eth_dev *dev, 194 struct rte_ether_addr *addr); 195 static int eth_igc_set_mc_addr_list(struct rte_eth_dev *dev, 196 struct rte_ether_addr *mc_addr_set, 197 uint32_t nb_mc_addr); 198 static int eth_igc_allmulticast_enable(struct rte_eth_dev *dev); 199 static int eth_igc_allmulticast_disable(struct rte_eth_dev *dev); 200 static int eth_igc_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 201 static int eth_igc_stats_get(struct rte_eth_dev *dev, 202 struct rte_eth_stats *rte_stats); 203 static int eth_igc_xstats_get(struct rte_eth_dev *dev, 204 struct rte_eth_xstat *xstats, unsigned int n); 205 static int eth_igc_xstats_get_by_id(struct rte_eth_dev *dev, 206 const uint64_t *ids, 207 uint64_t *values, unsigned int n); 208 static int eth_igc_xstats_get_names(struct rte_eth_dev *dev, 209 struct rte_eth_xstat_name *xstats_names, 210 unsigned int size); 211 static int eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev, 212 const uint64_t *ids, struct rte_eth_xstat_name *xstats_names, 213 unsigned int limit); 214 static int eth_igc_xstats_reset(struct rte_eth_dev *dev); 215 static int 216 eth_igc_queue_stats_mapping_set(struct rte_eth_dev *dev, 217 uint16_t queue_id, uint8_t stat_idx, uint8_t is_rx); 218 static int 219 eth_igc_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id); 220 static int 221 eth_igc_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id); 222 static int 223 eth_igc_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); 224 static int 225 eth_igc_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); 226 static int eth_igc_rss_reta_update(struct rte_eth_dev *dev, 227 struct rte_eth_rss_reta_entry64 *reta_conf, 228 uint16_t reta_size); 229 static int eth_igc_rss_reta_query(struct rte_eth_dev *dev, 230 struct rte_eth_rss_reta_entry64 *reta_conf, 231 uint16_t reta_size); 232 static int eth_igc_rss_hash_update(struct rte_eth_dev *dev, 233 struct rte_eth_rss_conf *rss_conf); 234 static int eth_igc_rss_hash_conf_get(struct rte_eth_dev *dev, 235 struct rte_eth_rss_conf *rss_conf); 236 static int 237 eth_igc_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 238 static int eth_igc_vlan_offload_set(struct rte_eth_dev *dev, int mask); 239 static int eth_igc_vlan_tpid_set(struct rte_eth_dev *dev, 240 enum rte_vlan_type vlan_type, uint16_t tpid); 241 242 static const struct eth_dev_ops eth_igc_ops = { 243 .dev_configure = eth_igc_configure, 244 .link_update = eth_igc_link_update, 245 .dev_stop = eth_igc_stop, 246 .dev_start = eth_igc_start, 247 .dev_close = eth_igc_close, 248 .dev_reset = eth_igc_reset, 249 .dev_set_link_up = eth_igc_set_link_up, 250 .dev_set_link_down = eth_igc_set_link_down, 251 .promiscuous_enable = eth_igc_promiscuous_enable, 252 .promiscuous_disable = eth_igc_promiscuous_disable, 253 .allmulticast_enable = eth_igc_allmulticast_enable, 254 .allmulticast_disable = eth_igc_allmulticast_disable, 255 .fw_version_get = eth_igc_fw_version_get, 256 .dev_infos_get = eth_igc_infos_get, 257 .dev_led_on = eth_igc_led_on, 258 .dev_led_off = eth_igc_led_off, 259 .dev_supported_ptypes_get = eth_igc_supported_ptypes_get, 260 .mtu_set = eth_igc_mtu_set, 261 .mac_addr_add = eth_igc_rar_set, 262 .mac_addr_remove = eth_igc_rar_clear, 263 .mac_addr_set = eth_igc_default_mac_addr_set, 264 .set_mc_addr_list = eth_igc_set_mc_addr_list, 265 266 .rx_queue_setup = eth_igc_rx_queue_setup, 267 .rx_queue_release = eth_igc_rx_queue_release, 268 .tx_queue_setup = eth_igc_tx_queue_setup, 269 .tx_queue_release = eth_igc_tx_queue_release, 270 .tx_done_cleanup = eth_igc_tx_done_cleanup, 271 .rxq_info_get = eth_igc_rxq_info_get, 272 .txq_info_get = eth_igc_txq_info_get, 273 .stats_get = eth_igc_stats_get, 274 .xstats_get = eth_igc_xstats_get, 275 .xstats_get_by_id = eth_igc_xstats_get_by_id, 276 .xstats_get_names_by_id = eth_igc_xstats_get_names_by_id, 277 .xstats_get_names = eth_igc_xstats_get_names, 278 .stats_reset = eth_igc_xstats_reset, 279 .xstats_reset = eth_igc_xstats_reset, 280 .queue_stats_mapping_set = eth_igc_queue_stats_mapping_set, 281 .rx_queue_intr_enable = eth_igc_rx_queue_intr_enable, 282 .rx_queue_intr_disable = eth_igc_rx_queue_intr_disable, 283 .flow_ctrl_get = eth_igc_flow_ctrl_get, 284 .flow_ctrl_set = eth_igc_flow_ctrl_set, 285 .reta_update = eth_igc_rss_reta_update, 286 .reta_query = eth_igc_rss_reta_query, 287 .rss_hash_update = eth_igc_rss_hash_update, 288 .rss_hash_conf_get = eth_igc_rss_hash_conf_get, 289 .vlan_filter_set = eth_igc_vlan_filter_set, 290 .vlan_offload_set = eth_igc_vlan_offload_set, 291 .vlan_tpid_set = eth_igc_vlan_tpid_set, 292 .vlan_strip_queue_set = eth_igc_vlan_strip_queue_set, 293 .flow_ops_get = eth_igc_flow_ops_get, 294 }; 295 296 /* 297 * multiple queue mode checking 298 */ 299 static int 300 igc_check_mq_mode(struct rte_eth_dev *dev) 301 { 302 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode; 303 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode; 304 305 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 306 PMD_INIT_LOG(ERR, "SRIOV is not supported."); 307 return -EINVAL; 308 } 309 310 if (rx_mq_mode != RTE_ETH_MQ_RX_NONE && 311 rx_mq_mode != RTE_ETH_MQ_RX_RSS) { 312 /* RSS together with VMDq not supported*/ 313 PMD_INIT_LOG(ERR, "RX mode %d is not supported.", 314 rx_mq_mode); 315 return -EINVAL; 316 } 317 318 /* To no break software that set invalid mode, only display 319 * warning if invalid mode is used. 320 */ 321 if (tx_mq_mode != RTE_ETH_MQ_TX_NONE) 322 PMD_INIT_LOG(WARNING, 323 "TX mode %d is not supported. Due to meaningless in this driver, just ignore", 324 tx_mq_mode); 325 326 return 0; 327 } 328 329 static int 330 eth_igc_configure(struct rte_eth_dev *dev) 331 { 332 struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev); 333 int ret; 334 335 PMD_INIT_FUNC_TRACE(); 336 337 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 338 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; 339 340 ret = igc_check_mq_mode(dev); 341 if (ret != 0) 342 return ret; 343 344 intr->flags |= IGC_FLAG_NEED_LINK_UPDATE; 345 return 0; 346 } 347 348 static int 349 eth_igc_set_link_up(struct rte_eth_dev *dev) 350 { 351 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 352 353 if (hw->phy.media_type == igc_media_type_copper) 354 igc_power_up_phy(hw); 355 else 356 igc_power_up_fiber_serdes_link(hw); 357 return 0; 358 } 359 360 static int 361 eth_igc_set_link_down(struct rte_eth_dev *dev) 362 { 363 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 364 365 if (hw->phy.media_type == igc_media_type_copper) 366 igc_power_down_phy(hw); 367 else 368 igc_shutdown_fiber_serdes_link(hw); 369 return 0; 370 } 371 372 /* 373 * disable other interrupt 374 */ 375 static void 376 igc_intr_other_disable(struct rte_eth_dev *dev) 377 { 378 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 379 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 380 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 381 382 if (rte_intr_allow_others(intr_handle) && 383 dev->data->dev_conf.intr_conf.lsc) { 384 IGC_WRITE_REG(hw, IGC_EIMC, 1u << IGC_MSIX_OTHER_INTR_VEC); 385 } 386 387 IGC_WRITE_REG(hw, IGC_IMC, ~0); 388 IGC_WRITE_FLUSH(hw); 389 } 390 391 /* 392 * enable other interrupt 393 */ 394 static inline void 395 igc_intr_other_enable(struct rte_eth_dev *dev) 396 { 397 struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev); 398 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 399 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 400 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 401 402 if (rte_intr_allow_others(intr_handle) && 403 dev->data->dev_conf.intr_conf.lsc) { 404 IGC_WRITE_REG(hw, IGC_EIMS, 1u << IGC_MSIX_OTHER_INTR_VEC); 405 } 406 407 IGC_WRITE_REG(hw, IGC_IMS, intr->mask); 408 IGC_WRITE_FLUSH(hw); 409 } 410 411 /* 412 * It reads ICR and gets interrupt causes, check it and set a bit flag 413 * to update link status. 414 */ 415 static void 416 eth_igc_interrupt_get_status(struct rte_eth_dev *dev) 417 { 418 uint32_t icr; 419 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 420 struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev); 421 422 /* read-on-clear nic registers here */ 423 icr = IGC_READ_REG(hw, IGC_ICR); 424 425 intr->flags = 0; 426 if (icr & IGC_ICR_LSC) 427 intr->flags |= IGC_FLAG_NEED_LINK_UPDATE; 428 } 429 430 /* return 0 means link status changed, -1 means not changed */ 431 static int 432 eth_igc_link_update(struct rte_eth_dev *dev, int wait_to_complete) 433 { 434 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 435 struct rte_eth_link link; 436 int link_check, count; 437 438 link_check = 0; 439 hw->mac.get_link_status = 1; 440 441 /* possible wait-to-complete in up to 9 seconds */ 442 for (count = 0; count < IGC_LINK_UPDATE_CHECK_TIMEOUT; count++) { 443 /* Read the real link status */ 444 switch (hw->phy.media_type) { 445 case igc_media_type_copper: 446 /* Do the work to read phy */ 447 igc_check_for_link(hw); 448 link_check = !hw->mac.get_link_status; 449 break; 450 451 case igc_media_type_fiber: 452 igc_check_for_link(hw); 453 link_check = (IGC_READ_REG(hw, IGC_STATUS) & 454 IGC_STATUS_LU); 455 break; 456 457 case igc_media_type_internal_serdes: 458 igc_check_for_link(hw); 459 link_check = hw->mac.serdes_has_link; 460 break; 461 462 default: 463 break; 464 } 465 if (link_check || wait_to_complete == 0) 466 break; 467 rte_delay_ms(IGC_LINK_UPDATE_CHECK_INTERVAL); 468 } 469 memset(&link, 0, sizeof(link)); 470 471 /* Now we check if a transition has happened */ 472 if (link_check) { 473 uint16_t duplex, speed; 474 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 475 link.link_duplex = (duplex == FULL_DUPLEX) ? 476 RTE_ETH_LINK_FULL_DUPLEX : 477 RTE_ETH_LINK_HALF_DUPLEX; 478 link.link_speed = speed; 479 link.link_status = RTE_ETH_LINK_UP; 480 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 481 RTE_ETH_LINK_SPEED_FIXED); 482 483 if (speed == SPEED_2500) { 484 uint32_t tipg = IGC_READ_REG(hw, IGC_TIPG); 485 if ((tipg & IGC_TIPG_IPGT_MASK) != 0x0b) { 486 tipg &= ~IGC_TIPG_IPGT_MASK; 487 tipg |= 0x0b; 488 IGC_WRITE_REG(hw, IGC_TIPG, tipg); 489 } 490 } 491 } else { 492 link.link_speed = 0; 493 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX; 494 link.link_status = RTE_ETH_LINK_DOWN; 495 link.link_autoneg = RTE_ETH_LINK_FIXED; 496 } 497 498 return rte_eth_linkstatus_set(dev, &link); 499 } 500 501 /* 502 * It executes link_update after knowing an interrupt is present. 503 */ 504 static void 505 eth_igc_interrupt_action(struct rte_eth_dev *dev) 506 { 507 struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev); 508 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 509 struct rte_eth_link link; 510 int ret; 511 512 if (intr->flags & IGC_FLAG_NEED_LINK_UPDATE) { 513 intr->flags &= ~IGC_FLAG_NEED_LINK_UPDATE; 514 515 /* set get_link_status to check register later */ 516 ret = eth_igc_link_update(dev, 0); 517 518 /* check if link has changed */ 519 if (ret < 0) 520 return; 521 522 rte_eth_linkstatus_get(dev, &link); 523 if (link.link_status) 524 PMD_DRV_LOG(INFO, 525 " Port %d: Link Up - speed %u Mbps - %s", 526 dev->data->port_id, 527 (unsigned int)link.link_speed, 528 link.link_duplex == RTE_ETH_LINK_FULL_DUPLEX ? 529 "full-duplex" : "half-duplex"); 530 else 531 PMD_DRV_LOG(INFO, " Port %d: Link Down", 532 dev->data->port_id); 533 534 PMD_DRV_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 535 pci_dev->addr.domain, 536 pci_dev->addr.bus, 537 pci_dev->addr.devid, 538 pci_dev->addr.function); 539 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 540 } 541 } 542 543 /* 544 * Interrupt handler which shall be registered at first. 545 * 546 * @handle 547 * Pointer to interrupt handle. 548 * @param 549 * The address of parameter (struct rte_eth_dev *) registered before. 550 */ 551 static void 552 eth_igc_interrupt_handler(void *param) 553 { 554 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 555 556 eth_igc_interrupt_get_status(dev); 557 eth_igc_interrupt_action(dev); 558 } 559 560 static void igc_read_queue_stats_register(struct rte_eth_dev *dev); 561 562 /* 563 * Update the queue status every IGC_ALARM_INTERVAL time. 564 * @param 565 * The address of parameter (struct rte_eth_dev *) registered before. 566 */ 567 static void 568 igc_update_queue_stats_handler(void *param) 569 { 570 struct rte_eth_dev *dev = param; 571 igc_read_queue_stats_register(dev); 572 rte_eal_alarm_set(IGC_ALARM_INTERVAL, 573 igc_update_queue_stats_handler, dev); 574 } 575 576 /* 577 * rx,tx enable/disable 578 */ 579 static void 580 eth_igc_rxtx_control(struct rte_eth_dev *dev, bool enable) 581 { 582 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 583 uint32_t tctl, rctl; 584 585 tctl = IGC_READ_REG(hw, IGC_TCTL); 586 rctl = IGC_READ_REG(hw, IGC_RCTL); 587 588 if (enable) { 589 /* enable Tx/Rx */ 590 tctl |= IGC_TCTL_EN; 591 rctl |= IGC_RCTL_EN; 592 } else { 593 /* disable Tx/Rx */ 594 tctl &= ~IGC_TCTL_EN; 595 rctl &= ~IGC_RCTL_EN; 596 } 597 IGC_WRITE_REG(hw, IGC_TCTL, tctl); 598 IGC_WRITE_REG(hw, IGC_RCTL, rctl); 599 IGC_WRITE_FLUSH(hw); 600 } 601 602 /* 603 * This routine disables all traffic on the adapter by issuing a 604 * global reset on the MAC. 605 */ 606 static int 607 eth_igc_stop(struct rte_eth_dev *dev) 608 { 609 struct igc_adapter *adapter = IGC_DEV_PRIVATE(dev); 610 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 611 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 612 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 613 struct rte_eth_link link; 614 615 dev->data->dev_started = 0; 616 adapter->stopped = 1; 617 618 /* disable receive and transmit */ 619 eth_igc_rxtx_control(dev, false); 620 621 /* disable all MSI-X interrupts */ 622 IGC_WRITE_REG(hw, IGC_EIMC, 0x1f); 623 IGC_WRITE_FLUSH(hw); 624 625 /* clear all MSI-X interrupts */ 626 IGC_WRITE_REG(hw, IGC_EICR, 0x1f); 627 628 igc_intr_other_disable(dev); 629 630 rte_eal_alarm_cancel(igc_update_queue_stats_handler, dev); 631 632 /* disable intr eventfd mapping */ 633 rte_intr_disable(intr_handle); 634 635 igc_reset_hw(hw); 636 637 /* disable all wake up */ 638 IGC_WRITE_REG(hw, IGC_WUC, 0); 639 640 /* disable checking EEE operation in MAC loopback mode */ 641 igc_read_reg_check_clear_bits(hw, IGC_EEER, IGC_EEER_EEE_FRC_AN); 642 643 /* Set bit for Go Link disconnect */ 644 igc_read_reg_check_set_bits(hw, IGC_82580_PHY_POWER_MGMT, 645 IGC_82580_PM_GO_LINKD); 646 647 /* Power down the phy. Needed to make the link go Down */ 648 eth_igc_set_link_down(dev); 649 650 igc_dev_clear_queues(dev); 651 652 /* clear the recorded link status */ 653 memset(&link, 0, sizeof(link)); 654 rte_eth_linkstatus_set(dev, &link); 655 656 if (!rte_intr_allow_others(intr_handle)) 657 /* resume to the default handler */ 658 rte_intr_callback_register(intr_handle, 659 eth_igc_interrupt_handler, 660 (void *)dev); 661 662 /* Clean datapath event and queue/vec mapping */ 663 rte_intr_efd_disable(intr_handle); 664 rte_intr_vec_list_free(intr_handle); 665 666 return 0; 667 } 668 669 /* 670 * write interrupt vector allocation register 671 * @hw 672 * board private structure 673 * @queue_index 674 * queue index, valid 0,1,2,3 675 * @tx 676 * tx:1, rx:0 677 * @msix_vector 678 * msix-vector, valid 0,1,2,3,4 679 */ 680 static void 681 igc_write_ivar(struct igc_hw *hw, uint8_t queue_index, 682 bool tx, uint8_t msix_vector) 683 { 684 uint8_t offset = 0; 685 uint8_t reg_index = queue_index >> 1; 686 uint32_t val; 687 688 /* 689 * IVAR(0) 690 * bit31...24 bit23...16 bit15...8 bit7...0 691 * TX1 RX1 TX0 RX0 692 * 693 * IVAR(1) 694 * bit31...24 bit23...16 bit15...8 bit7...0 695 * TX3 RX3 TX2 RX2 696 */ 697 698 if (tx) 699 offset = 8; 700 701 if (queue_index & 1) 702 offset += 16; 703 704 val = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, reg_index); 705 706 /* clear bits */ 707 val &= ~((uint32_t)0xFF << offset); 708 709 /* write vector and valid bit */ 710 val |= (uint32_t)(msix_vector | IGC_IVAR_VALID) << offset; 711 712 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, reg_index, val); 713 } 714 715 /* Sets up the hardware to generate MSI-X interrupts properly 716 * @hw 717 * board private structure 718 */ 719 static void 720 igc_configure_msix_intr(struct rte_eth_dev *dev) 721 { 722 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 723 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 724 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 725 726 uint32_t intr_mask; 727 uint32_t vec = IGC_MISC_VEC_ID; 728 uint32_t base = IGC_MISC_VEC_ID; 729 uint32_t misc_shift = 0; 730 int i; 731 732 /* won't configure msix register if no mapping is done 733 * between intr vector and event fd 734 */ 735 if (!rte_intr_dp_is_en(intr_handle)) 736 return; 737 738 if (rte_intr_allow_others(intr_handle)) { 739 base = IGC_RX_VEC_START; 740 vec = base; 741 misc_shift = 1; 742 } 743 744 /* turn on MSI-X capability first */ 745 IGC_WRITE_REG(hw, IGC_GPIE, IGC_GPIE_MSIX_MODE | 746 IGC_GPIE_PBA | IGC_GPIE_EIAME | 747 IGC_GPIE_NSICR); 748 intr_mask = RTE_LEN2MASK(rte_intr_nb_efd_get(intr_handle), 749 uint32_t) << misc_shift; 750 751 if (dev->data->dev_conf.intr_conf.lsc) 752 intr_mask |= (1u << IGC_MSIX_OTHER_INTR_VEC); 753 754 /* enable msix auto-clear */ 755 igc_read_reg_check_set_bits(hw, IGC_EIAC, intr_mask); 756 757 /* set other cause interrupt vector */ 758 igc_read_reg_check_set_bits(hw, IGC_IVAR_MISC, 759 (uint32_t)(IGC_MSIX_OTHER_INTR_VEC | IGC_IVAR_VALID) << 8); 760 761 /* enable auto-mask */ 762 igc_read_reg_check_set_bits(hw, IGC_EIAM, intr_mask); 763 764 for (i = 0; i < dev->data->nb_rx_queues; i++) { 765 igc_write_ivar(hw, i, 0, vec); 766 rte_intr_vec_list_index_set(intr_handle, i, vec); 767 if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1) 768 vec++; 769 } 770 771 IGC_WRITE_FLUSH(hw); 772 } 773 774 /** 775 * It enables the interrupt mask and then enable the interrupt. 776 * 777 * @dev 778 * Pointer to struct rte_eth_dev. 779 * @on 780 * Enable or Disable 781 */ 782 static void 783 igc_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 784 { 785 struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev); 786 787 if (on) 788 intr->mask |= IGC_ICR_LSC; 789 else 790 intr->mask &= ~IGC_ICR_LSC; 791 } 792 793 /* 794 * It enables the interrupt. 795 * It will be called once only during nic initialized. 796 */ 797 static void 798 igc_rxq_interrupt_setup(struct rte_eth_dev *dev) 799 { 800 uint32_t mask; 801 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 802 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 803 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 804 int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0; 805 806 /* won't configure msix register if no mapping is done 807 * between intr vector and event fd 808 */ 809 if (!rte_intr_dp_is_en(intr_handle)) 810 return; 811 812 mask = RTE_LEN2MASK(rte_intr_nb_efd_get(intr_handle), uint32_t) 813 << misc_shift; 814 IGC_WRITE_REG(hw, IGC_EIMS, mask); 815 } 816 817 /* 818 * Get hardware rx-buffer size. 819 */ 820 static inline int 821 igc_get_rx_buffer_size(struct igc_hw *hw) 822 { 823 return (IGC_READ_REG(hw, IGC_RXPBS) & 0x3f) << 10; 824 } 825 826 /* 827 * igc_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit. 828 * For ASF and Pass Through versions of f/w this means 829 * that the driver is loaded. 830 */ 831 static void 832 igc_hw_control_acquire(struct igc_hw *hw) 833 { 834 uint32_t ctrl_ext; 835 836 /* Let firmware know the driver has taken over */ 837 ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT); 838 IGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext | IGC_CTRL_EXT_DRV_LOAD); 839 } 840 841 /* 842 * igc_hw_control_release resets CTRL_EXT:DRV_LOAD bit. 843 * For ASF and Pass Through versions of f/w this means that the 844 * driver is no longer loaded. 845 */ 846 static void 847 igc_hw_control_release(struct igc_hw *hw) 848 { 849 uint32_t ctrl_ext; 850 851 /* Let firmware taken over control of h/w */ 852 ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT); 853 IGC_WRITE_REG(hw, IGC_CTRL_EXT, 854 ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD); 855 } 856 857 static int 858 igc_hardware_init(struct igc_hw *hw) 859 { 860 uint32_t rx_buf_size; 861 int diag; 862 863 /* Let the firmware know the OS is in control */ 864 igc_hw_control_acquire(hw); 865 866 /* Issue a global reset */ 867 igc_reset_hw(hw); 868 869 /* disable all wake up */ 870 IGC_WRITE_REG(hw, IGC_WUC, 0); 871 872 /* 873 * Hardware flow control 874 * - High water mark should allow for at least two standard size (1518) 875 * frames to be received after sending an XOFF. 876 * - Low water mark works best when it is very near the high water mark. 877 * This allows the receiver to restart by sending XON when it has 878 * drained a bit. Here we use an arbitrary value of 1500 which will 879 * restart after one full frame is pulled from the buffer. There 880 * could be several smaller frames in the buffer and if so they will 881 * not trigger the XON until their total number reduces the buffer 882 * by 1500. 883 */ 884 rx_buf_size = igc_get_rx_buffer_size(hw); 885 hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2); 886 hw->fc.low_water = hw->fc.high_water - 1500; 887 hw->fc.pause_time = IGC_FC_PAUSE_TIME; 888 hw->fc.send_xon = 1; 889 hw->fc.requested_mode = igc_fc_full; 890 891 diag = igc_init_hw(hw); 892 if (diag < 0) 893 return diag; 894 895 igc_get_phy_info(hw); 896 igc_check_for_link(hw); 897 898 return 0; 899 } 900 901 static int 902 eth_igc_start(struct rte_eth_dev *dev) 903 { 904 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 905 struct igc_adapter *adapter = IGC_DEV_PRIVATE(dev); 906 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 907 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 908 uint32_t *speeds; 909 int ret; 910 911 PMD_INIT_FUNC_TRACE(); 912 913 /* disable all MSI-X interrupts */ 914 IGC_WRITE_REG(hw, IGC_EIMC, 0x1f); 915 IGC_WRITE_FLUSH(hw); 916 917 /* clear all MSI-X interrupts */ 918 IGC_WRITE_REG(hw, IGC_EICR, 0x1f); 919 920 /* disable uio/vfio intr/eventfd mapping */ 921 if (!adapter->stopped) 922 rte_intr_disable(intr_handle); 923 924 /* Power up the phy. Needed to make the link go Up */ 925 eth_igc_set_link_up(dev); 926 927 /* Put the address into the Receive Address Array */ 928 igc_rar_set(hw, hw->mac.addr, 0); 929 930 /* Initialize the hardware */ 931 if (igc_hardware_init(hw)) { 932 PMD_DRV_LOG(ERR, "Unable to initialize the hardware"); 933 return -EIO; 934 } 935 adapter->stopped = 0; 936 937 /* check and configure queue intr-vector mapping */ 938 if (rte_intr_cap_multiple(intr_handle) && 939 dev->data->dev_conf.intr_conf.rxq) { 940 uint32_t intr_vector = dev->data->nb_rx_queues; 941 if (rte_intr_efd_enable(intr_handle, intr_vector)) 942 return -1; 943 } 944 945 if (rte_intr_dp_is_en(intr_handle)) { 946 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec", 947 dev->data->nb_rx_queues)) { 948 PMD_DRV_LOG(ERR, 949 "Failed to allocate %d rx_queues intr_vec", 950 dev->data->nb_rx_queues); 951 return -ENOMEM; 952 } 953 } 954 955 /* configure msix for rx interrupt */ 956 igc_configure_msix_intr(dev); 957 958 igc_tx_init(dev); 959 960 /* This can fail when allocating mbufs for descriptor rings */ 961 ret = igc_rx_init(dev); 962 if (ret) { 963 PMD_DRV_LOG(ERR, "Unable to initialize RX hardware"); 964 igc_dev_clear_queues(dev); 965 return ret; 966 } 967 968 igc_clear_hw_cntrs_base_generic(hw); 969 970 /* VLAN Offload Settings */ 971 eth_igc_vlan_offload_set(dev, 972 RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK | 973 RTE_ETH_VLAN_EXTEND_MASK); 974 975 /* Setup link speed and duplex */ 976 speeds = &dev->data->dev_conf.link_speeds; 977 if (*speeds == RTE_ETH_LINK_SPEED_AUTONEG) { 978 hw->phy.autoneg_advertised = IGC_ALL_SPEED_DUPLEX_2500; 979 hw->mac.autoneg = 1; 980 } else { 981 int num_speeds = 0; 982 983 if (*speeds & RTE_ETH_LINK_SPEED_FIXED) { 984 PMD_DRV_LOG(ERR, 985 "Force speed mode currently not supported"); 986 igc_dev_clear_queues(dev); 987 return -EINVAL; 988 } 989 990 hw->phy.autoneg_advertised = 0; 991 hw->mac.autoneg = 1; 992 993 if (*speeds & ~(RTE_ETH_LINK_SPEED_10M_HD | RTE_ETH_LINK_SPEED_10M | 994 RTE_ETH_LINK_SPEED_100M_HD | RTE_ETH_LINK_SPEED_100M | 995 RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_2_5G)) { 996 num_speeds = -1; 997 goto error_invalid_config; 998 } 999 if (*speeds & RTE_ETH_LINK_SPEED_10M_HD) { 1000 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF; 1001 num_speeds++; 1002 } 1003 if (*speeds & RTE_ETH_LINK_SPEED_10M) { 1004 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL; 1005 num_speeds++; 1006 } 1007 if (*speeds & RTE_ETH_LINK_SPEED_100M_HD) { 1008 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF; 1009 num_speeds++; 1010 } 1011 if (*speeds & RTE_ETH_LINK_SPEED_100M) { 1012 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL; 1013 num_speeds++; 1014 } 1015 if (*speeds & RTE_ETH_LINK_SPEED_1G) { 1016 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL; 1017 num_speeds++; 1018 } 1019 if (*speeds & RTE_ETH_LINK_SPEED_2_5G) { 1020 hw->phy.autoneg_advertised |= ADVERTISE_2500_FULL; 1021 num_speeds++; 1022 } 1023 if (num_speeds == 0) 1024 goto error_invalid_config; 1025 } 1026 1027 igc_setup_link(hw); 1028 1029 if (rte_intr_allow_others(intr_handle)) { 1030 /* check if lsc interrupt is enabled */ 1031 if (dev->data->dev_conf.intr_conf.lsc) 1032 igc_lsc_interrupt_setup(dev, 1); 1033 else 1034 igc_lsc_interrupt_setup(dev, 0); 1035 } else { 1036 rte_intr_callback_unregister(intr_handle, 1037 eth_igc_interrupt_handler, 1038 (void *)dev); 1039 if (dev->data->dev_conf.intr_conf.lsc) 1040 PMD_DRV_LOG(INFO, 1041 "LSC won't enable because of no intr multiplex"); 1042 } 1043 1044 /* enable uio/vfio intr/eventfd mapping */ 1045 rte_intr_enable(intr_handle); 1046 1047 rte_eal_alarm_set(IGC_ALARM_INTERVAL, 1048 igc_update_queue_stats_handler, dev); 1049 1050 /* check if rxq interrupt is enabled */ 1051 if (dev->data->dev_conf.intr_conf.rxq && 1052 rte_intr_dp_is_en(intr_handle)) 1053 igc_rxq_interrupt_setup(dev); 1054 1055 /* resume enabled intr since hw reset */ 1056 igc_intr_other_enable(dev); 1057 1058 eth_igc_rxtx_control(dev, true); 1059 eth_igc_link_update(dev, 0); 1060 1061 /* configure MAC-loopback mode */ 1062 if (dev->data->dev_conf.lpbk_mode == 1) { 1063 uint32_t reg_val; 1064 1065 reg_val = IGC_READ_REG(hw, IGC_CTRL); 1066 reg_val &= ~IGC_CTRL_SPEED_MASK; 1067 reg_val |= IGC_CTRL_SLU | IGC_CTRL_FRCSPD | 1068 IGC_CTRL_FRCDPX | IGC_CTRL_FD | IGC_CTRL_SPEED_2500; 1069 IGC_WRITE_REG(hw, IGC_CTRL, reg_val); 1070 1071 igc_read_reg_check_set_bits(hw, IGC_EEER, IGC_EEER_EEE_FRC_AN); 1072 } 1073 1074 return 0; 1075 1076 error_invalid_config: 1077 PMD_DRV_LOG(ERR, "Invalid advertised speeds (%u) for port %u", 1078 dev->data->dev_conf.link_speeds, dev->data->port_id); 1079 igc_dev_clear_queues(dev); 1080 return -EINVAL; 1081 } 1082 1083 static int 1084 igc_reset_swfw_lock(struct igc_hw *hw) 1085 { 1086 int ret_val; 1087 1088 /* 1089 * Do mac ops initialization manually here, since we will need 1090 * some function pointers set by this call. 1091 */ 1092 ret_val = igc_init_mac_params(hw); 1093 if (ret_val) 1094 return ret_val; 1095 1096 /* 1097 * SMBI lock should not fail in this early stage. If this is the case, 1098 * it is due to an improper exit of the application. 1099 * So force the release of the faulty lock. 1100 */ 1101 if (igc_get_hw_semaphore_generic(hw) < 0) 1102 PMD_DRV_LOG(DEBUG, "SMBI lock released"); 1103 1104 igc_put_hw_semaphore_generic(hw); 1105 1106 if (hw->mac.ops.acquire_swfw_sync != NULL) { 1107 uint16_t mask; 1108 1109 /* 1110 * Phy lock should not fail in this early stage. 1111 * If this is the case, it is due to an improper exit of the 1112 * application. So force the release of the faulty lock. 1113 */ 1114 mask = IGC_SWFW_PHY0_SM; 1115 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) { 1116 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", 1117 hw->bus.func); 1118 } 1119 hw->mac.ops.release_swfw_sync(hw, mask); 1120 1121 /* 1122 * This one is more tricky since it is common to all ports; but 1123 * swfw_sync retries last long enough (1s) to be almost sure 1124 * that if lock can not be taken it is due to an improper lock 1125 * of the semaphore. 1126 */ 1127 mask = IGC_SWFW_EEP_SM; 1128 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) 1129 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 1130 1131 hw->mac.ops.release_swfw_sync(hw, mask); 1132 } 1133 1134 return IGC_SUCCESS; 1135 } 1136 1137 /* 1138 * free all rx/tx queues. 1139 */ 1140 static void 1141 igc_dev_free_queues(struct rte_eth_dev *dev) 1142 { 1143 uint16_t i; 1144 1145 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1146 eth_igc_rx_queue_release(dev, i); 1147 dev->data->rx_queues[i] = NULL; 1148 } 1149 dev->data->nb_rx_queues = 0; 1150 1151 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1152 eth_igc_tx_queue_release(dev, i); 1153 dev->data->tx_queues[i] = NULL; 1154 } 1155 dev->data->nb_tx_queues = 0; 1156 } 1157 1158 static int 1159 eth_igc_close(struct rte_eth_dev *dev) 1160 { 1161 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1162 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 1163 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 1164 struct igc_adapter *adapter = IGC_DEV_PRIVATE(dev); 1165 int retry = 0; 1166 int ret = 0; 1167 1168 PMD_INIT_FUNC_TRACE(); 1169 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1170 return 0; 1171 1172 if (!adapter->stopped) 1173 ret = eth_igc_stop(dev); 1174 1175 igc_flow_flush(dev, NULL); 1176 igc_clear_all_filter(dev); 1177 1178 igc_intr_other_disable(dev); 1179 do { 1180 int ret = rte_intr_callback_unregister(intr_handle, 1181 eth_igc_interrupt_handler, dev); 1182 if (ret >= 0 || ret == -ENOENT || ret == -EINVAL) 1183 break; 1184 1185 PMD_DRV_LOG(ERR, "intr callback unregister failed: %d", ret); 1186 DELAY(200 * 1000); /* delay 200ms */ 1187 } while (retry++ < 5); 1188 1189 igc_phy_hw_reset(hw); 1190 igc_hw_control_release(hw); 1191 igc_dev_free_queues(dev); 1192 1193 /* Reset any pending lock */ 1194 igc_reset_swfw_lock(hw); 1195 1196 return ret; 1197 } 1198 1199 static void 1200 igc_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev) 1201 { 1202 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 1203 1204 hw->vendor_id = pci_dev->id.vendor_id; 1205 hw->device_id = pci_dev->id.device_id; 1206 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 1207 hw->subsystem_device_id = pci_dev->id.subsystem_device_id; 1208 } 1209 1210 static int 1211 eth_igc_dev_init(struct rte_eth_dev *dev) 1212 { 1213 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1214 struct igc_adapter *igc = IGC_DEV_PRIVATE(dev); 1215 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 1216 int i, error = 0; 1217 1218 PMD_INIT_FUNC_TRACE(); 1219 dev->dev_ops = ð_igc_ops; 1220 dev->rx_queue_count = eth_igc_rx_queue_count; 1221 dev->rx_descriptor_status = eth_igc_rx_descriptor_status; 1222 dev->tx_descriptor_status = eth_igc_tx_descriptor_status; 1223 1224 /* 1225 * for secondary processes, we don't initialize any further as primary 1226 * has already done this work. Only check we don't need a different 1227 * RX function. 1228 */ 1229 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1230 return 0; 1231 1232 rte_eth_copy_pci_info(dev, pci_dev); 1233 dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1234 1235 hw->back = pci_dev; 1236 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1237 1238 igc_identify_hardware(dev, pci_dev); 1239 if (igc_setup_init_funcs(hw, false) != IGC_SUCCESS) { 1240 error = -EIO; 1241 goto err_late; 1242 } 1243 1244 igc_get_bus_info(hw); 1245 1246 /* Reset any pending lock */ 1247 if (igc_reset_swfw_lock(hw) != IGC_SUCCESS) { 1248 error = -EIO; 1249 goto err_late; 1250 } 1251 1252 /* Finish initialization */ 1253 if (igc_setup_init_funcs(hw, true) != IGC_SUCCESS) { 1254 error = -EIO; 1255 goto err_late; 1256 } 1257 1258 hw->mac.autoneg = 1; 1259 hw->phy.autoneg_wait_to_complete = 0; 1260 hw->phy.autoneg_advertised = IGC_ALL_SPEED_DUPLEX_2500; 1261 1262 /* Copper options */ 1263 if (hw->phy.media_type == igc_media_type_copper) { 1264 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 1265 hw->phy.disable_polarity_correction = 0; 1266 hw->phy.ms_type = igc_ms_hw_default; 1267 } 1268 1269 /* 1270 * Start from a known state, this is important in reading the nvm 1271 * and mac from that. 1272 */ 1273 igc_reset_hw(hw); 1274 1275 /* Make sure we have a good EEPROM before we read from it */ 1276 if (igc_validate_nvm_checksum(hw) < 0) { 1277 /* 1278 * Some PCI-E parts fail the first check due to 1279 * the link being in sleep state, call it again, 1280 * if it fails a second time its a real issue. 1281 */ 1282 if (igc_validate_nvm_checksum(hw) < 0) { 1283 PMD_INIT_LOG(ERR, "EEPROM checksum invalid"); 1284 error = -EIO; 1285 goto err_late; 1286 } 1287 } 1288 1289 /* Read the permanent MAC address out of the EEPROM */ 1290 if (igc_read_mac_addr(hw) != 0) { 1291 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address"); 1292 error = -EIO; 1293 goto err_late; 1294 } 1295 1296 /* Allocate memory for storing MAC addresses */ 1297 dev->data->mac_addrs = rte_zmalloc("igc", 1298 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0); 1299 if (dev->data->mac_addrs == NULL) { 1300 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes for storing MAC", 1301 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count); 1302 error = -ENOMEM; 1303 goto err_late; 1304 } 1305 1306 /* Copy the permanent MAC address */ 1307 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr, 1308 &dev->data->mac_addrs[0]); 1309 1310 /* Now initialize the hardware */ 1311 if (igc_hardware_init(hw) != 0) { 1312 PMD_INIT_LOG(ERR, "Hardware initialization failed"); 1313 rte_free(dev->data->mac_addrs); 1314 dev->data->mac_addrs = NULL; 1315 error = -ENODEV; 1316 goto err_late; 1317 } 1318 1319 hw->mac.get_link_status = 1; 1320 igc->stopped = 0; 1321 1322 /* Indicate SOL/IDER usage */ 1323 if (igc_check_reset_block(hw) < 0) 1324 PMD_INIT_LOG(ERR, 1325 "PHY reset is blocked due to SOL/IDER session."); 1326 1327 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x", 1328 dev->data->port_id, pci_dev->id.vendor_id, 1329 pci_dev->id.device_id); 1330 1331 rte_intr_callback_register(pci_dev->intr_handle, 1332 eth_igc_interrupt_handler, (void *)dev); 1333 1334 /* enable uio/vfio intr/eventfd mapping */ 1335 rte_intr_enable(pci_dev->intr_handle); 1336 1337 /* enable support intr */ 1338 igc_intr_other_enable(dev); 1339 1340 /* initiate queue status */ 1341 for (i = 0; i < IGC_QUEUE_PAIRS_NUM; i++) { 1342 igc->txq_stats_map[i] = -1; 1343 igc->rxq_stats_map[i] = -1; 1344 } 1345 1346 igc_flow_init(dev); 1347 igc_clear_all_filter(dev); 1348 return 0; 1349 1350 err_late: 1351 igc_hw_control_release(hw); 1352 return error; 1353 } 1354 1355 static int 1356 eth_igc_dev_uninit(__rte_unused struct rte_eth_dev *eth_dev) 1357 { 1358 PMD_INIT_FUNC_TRACE(); 1359 eth_igc_close(eth_dev); 1360 return 0; 1361 } 1362 1363 static int 1364 eth_igc_reset(struct rte_eth_dev *dev) 1365 { 1366 int ret; 1367 1368 PMD_INIT_FUNC_TRACE(); 1369 1370 ret = eth_igc_dev_uninit(dev); 1371 if (ret) 1372 return ret; 1373 1374 return eth_igc_dev_init(dev); 1375 } 1376 1377 static int 1378 eth_igc_promiscuous_enable(struct rte_eth_dev *dev) 1379 { 1380 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 1381 uint32_t rctl; 1382 1383 rctl = IGC_READ_REG(hw, IGC_RCTL); 1384 rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE); 1385 IGC_WRITE_REG(hw, IGC_RCTL, rctl); 1386 return 0; 1387 } 1388 1389 static int 1390 eth_igc_promiscuous_disable(struct rte_eth_dev *dev) 1391 { 1392 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 1393 uint32_t rctl; 1394 1395 rctl = IGC_READ_REG(hw, IGC_RCTL); 1396 rctl &= (~IGC_RCTL_UPE); 1397 if (dev->data->all_multicast == 1) 1398 rctl |= IGC_RCTL_MPE; 1399 else 1400 rctl &= (~IGC_RCTL_MPE); 1401 IGC_WRITE_REG(hw, IGC_RCTL, rctl); 1402 return 0; 1403 } 1404 1405 static int 1406 eth_igc_allmulticast_enable(struct rte_eth_dev *dev) 1407 { 1408 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 1409 uint32_t rctl; 1410 1411 rctl = IGC_READ_REG(hw, IGC_RCTL); 1412 rctl |= IGC_RCTL_MPE; 1413 IGC_WRITE_REG(hw, IGC_RCTL, rctl); 1414 return 0; 1415 } 1416 1417 static int 1418 eth_igc_allmulticast_disable(struct rte_eth_dev *dev) 1419 { 1420 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 1421 uint32_t rctl; 1422 1423 if (dev->data->promiscuous == 1) 1424 return 0; /* must remain in all_multicast mode */ 1425 1426 rctl = IGC_READ_REG(hw, IGC_RCTL); 1427 rctl &= (~IGC_RCTL_MPE); 1428 IGC_WRITE_REG(hw, IGC_RCTL, rctl); 1429 return 0; 1430 } 1431 1432 static int 1433 eth_igc_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 1434 size_t fw_size) 1435 { 1436 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 1437 struct igc_fw_version fw; 1438 int ret; 1439 1440 igc_get_fw_version(hw, &fw); 1441 1442 /* if option rom is valid, display its version too */ 1443 if (fw.or_valid) { 1444 ret = snprintf(fw_version, fw_size, 1445 "%d.%d, 0x%08x, %d.%d.%d", 1446 fw.eep_major, fw.eep_minor, fw.etrack_id, 1447 fw.or_major, fw.or_build, fw.or_patch); 1448 /* no option rom */ 1449 } else { 1450 if (fw.etrack_id != 0X0000) { 1451 ret = snprintf(fw_version, fw_size, 1452 "%d.%d, 0x%08x", 1453 fw.eep_major, fw.eep_minor, 1454 fw.etrack_id); 1455 } else { 1456 ret = snprintf(fw_version, fw_size, 1457 "%d.%d.%d", 1458 fw.eep_major, fw.eep_minor, 1459 fw.eep_build); 1460 } 1461 } 1462 if (ret < 0) 1463 return -EINVAL; 1464 1465 ret += 1; /* add the size of '\0' */ 1466 if (fw_size < (size_t)ret) 1467 return ret; 1468 else 1469 return 0; 1470 } 1471 1472 static int 1473 eth_igc_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1474 { 1475 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 1476 1477 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */ 1478 dev_info->max_rx_pktlen = MAX_RX_JUMBO_FRAME_SIZE; 1479 dev_info->max_mac_addrs = hw->mac.rar_entry_count; 1480 dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; 1481 dev_info->rx_offload_capa = IGC_RX_OFFLOAD_ALL; 1482 dev_info->tx_offload_capa = IGC_TX_OFFLOAD_ALL; 1483 dev_info->rx_queue_offload_capa = RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 1484 1485 dev_info->max_rx_queues = IGC_QUEUE_PAIRS_NUM; 1486 dev_info->max_tx_queues = IGC_QUEUE_PAIRS_NUM; 1487 dev_info->max_vmdq_pools = 0; 1488 1489 dev_info->hash_key_size = IGC_HKEY_MAX_INDEX * sizeof(uint32_t); 1490 dev_info->reta_size = RTE_ETH_RSS_RETA_SIZE_128; 1491 dev_info->flow_type_rss_offloads = IGC_RSS_OFFLOAD_ALL; 1492 1493 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1494 .rx_thresh = { 1495 .pthresh = IGC_DEFAULT_RX_PTHRESH, 1496 .hthresh = IGC_DEFAULT_RX_HTHRESH, 1497 .wthresh = IGC_DEFAULT_RX_WTHRESH, 1498 }, 1499 .rx_free_thresh = IGC_DEFAULT_RX_FREE_THRESH, 1500 .rx_drop_en = 0, 1501 .offloads = 0, 1502 }; 1503 1504 dev_info->default_txconf = (struct rte_eth_txconf) { 1505 .tx_thresh = { 1506 .pthresh = IGC_DEFAULT_TX_PTHRESH, 1507 .hthresh = IGC_DEFAULT_TX_HTHRESH, 1508 .wthresh = IGC_DEFAULT_TX_WTHRESH, 1509 }, 1510 .offloads = 0, 1511 }; 1512 1513 dev_info->rx_desc_lim = rx_desc_lim; 1514 dev_info->tx_desc_lim = tx_desc_lim; 1515 1516 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD | RTE_ETH_LINK_SPEED_10M | 1517 RTE_ETH_LINK_SPEED_100M_HD | RTE_ETH_LINK_SPEED_100M | 1518 RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_2_5G; 1519 1520 dev_info->max_mtu = dev_info->max_rx_pktlen - IGC_ETH_OVERHEAD; 1521 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 1522 return 0; 1523 } 1524 1525 static int 1526 eth_igc_led_on(struct rte_eth_dev *dev) 1527 { 1528 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 1529 1530 return igc_led_on(hw) == IGC_SUCCESS ? 0 : -ENOTSUP; 1531 } 1532 1533 static int 1534 eth_igc_led_off(struct rte_eth_dev *dev) 1535 { 1536 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 1537 1538 return igc_led_off(hw) == IGC_SUCCESS ? 0 : -ENOTSUP; 1539 } 1540 1541 static const uint32_t * 1542 eth_igc_supported_ptypes_get(__rte_unused struct rte_eth_dev *dev) 1543 { 1544 static const uint32_t ptypes[] = { 1545 /* refers to rx_desc_pkt_info_to_pkt_type() */ 1546 RTE_PTYPE_L2_ETHER, 1547 RTE_PTYPE_L3_IPV4, 1548 RTE_PTYPE_L3_IPV4_EXT, 1549 RTE_PTYPE_L3_IPV6, 1550 RTE_PTYPE_L3_IPV6_EXT, 1551 RTE_PTYPE_L4_TCP, 1552 RTE_PTYPE_L4_UDP, 1553 RTE_PTYPE_L4_SCTP, 1554 RTE_PTYPE_TUNNEL_IP, 1555 RTE_PTYPE_INNER_L3_IPV6, 1556 RTE_PTYPE_INNER_L3_IPV6_EXT, 1557 RTE_PTYPE_INNER_L4_TCP, 1558 RTE_PTYPE_INNER_L4_UDP, 1559 RTE_PTYPE_UNKNOWN 1560 }; 1561 1562 return ptypes; 1563 } 1564 1565 static int 1566 eth_igc_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1567 { 1568 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 1569 uint32_t frame_size = mtu + IGC_ETH_OVERHEAD; 1570 uint32_t rctl; 1571 1572 /* if extend vlan has been enabled */ 1573 if (IGC_READ_REG(hw, IGC_CTRL_EXT) & IGC_CTRL_EXT_EXT_VLAN) 1574 frame_size += VLAN_TAG_SIZE; 1575 1576 /* 1577 * If device is started, refuse mtu that requires the support of 1578 * scattered packets when this feature has not been enabled before. 1579 */ 1580 if (dev->data->dev_started && !dev->data->scattered_rx && 1581 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) { 1582 PMD_INIT_LOG(ERR, "Stop port first."); 1583 return -EINVAL; 1584 } 1585 1586 rctl = IGC_READ_REG(hw, IGC_RCTL); 1587 if (mtu > RTE_ETHER_MTU) 1588 rctl |= IGC_RCTL_LPE; 1589 else 1590 rctl &= ~IGC_RCTL_LPE; 1591 IGC_WRITE_REG(hw, IGC_RCTL, rctl); 1592 1593 IGC_WRITE_REG(hw, IGC_RLPML, frame_size); 1594 1595 return 0; 1596 } 1597 1598 static int 1599 eth_igc_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 1600 uint32_t index, uint32_t pool) 1601 { 1602 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 1603 1604 igc_rar_set(hw, mac_addr->addr_bytes, index); 1605 RTE_SET_USED(pool); 1606 return 0; 1607 } 1608 1609 static void 1610 eth_igc_rar_clear(struct rte_eth_dev *dev, uint32_t index) 1611 { 1612 uint8_t addr[RTE_ETHER_ADDR_LEN]; 1613 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 1614 1615 memset(addr, 0, sizeof(addr)); 1616 igc_rar_set(hw, addr, index); 1617 } 1618 1619 static int 1620 eth_igc_default_mac_addr_set(struct rte_eth_dev *dev, 1621 struct rte_ether_addr *addr) 1622 { 1623 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 1624 igc_rar_set(hw, addr->addr_bytes, 0); 1625 return 0; 1626 } 1627 1628 static int 1629 eth_igc_set_mc_addr_list(struct rte_eth_dev *dev, 1630 struct rte_ether_addr *mc_addr_set, 1631 uint32_t nb_mc_addr) 1632 { 1633 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 1634 igc_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr); 1635 return 0; 1636 } 1637 1638 /* 1639 * Read hardware registers 1640 */ 1641 static void 1642 igc_read_stats_registers(struct igc_hw *hw, struct igc_hw_stats *stats) 1643 { 1644 int pause_frames; 1645 1646 uint64_t old_gprc = stats->gprc; 1647 uint64_t old_gptc = stats->gptc; 1648 uint64_t old_tpr = stats->tpr; 1649 uint64_t old_tpt = stats->tpt; 1650 uint64_t old_rpthc = stats->rpthc; 1651 uint64_t old_hgptc = stats->hgptc; 1652 1653 stats->crcerrs += IGC_READ_REG(hw, IGC_CRCERRS); 1654 stats->algnerrc += IGC_READ_REG(hw, IGC_ALGNERRC); 1655 stats->rxerrc += IGC_READ_REG(hw, IGC_RXERRC); 1656 stats->mpc += IGC_READ_REG(hw, IGC_MPC); 1657 stats->scc += IGC_READ_REG(hw, IGC_SCC); 1658 stats->ecol += IGC_READ_REG(hw, IGC_ECOL); 1659 1660 stats->mcc += IGC_READ_REG(hw, IGC_MCC); 1661 stats->latecol += IGC_READ_REG(hw, IGC_LATECOL); 1662 stats->colc += IGC_READ_REG(hw, IGC_COLC); 1663 1664 stats->dc += IGC_READ_REG(hw, IGC_DC); 1665 stats->tncrs += IGC_READ_REG(hw, IGC_TNCRS); 1666 stats->htdpmc += IGC_READ_REG(hw, IGC_HTDPMC); 1667 stats->rlec += IGC_READ_REG(hw, IGC_RLEC); 1668 stats->xonrxc += IGC_READ_REG(hw, IGC_XONRXC); 1669 stats->xontxc += IGC_READ_REG(hw, IGC_XONTXC); 1670 1671 /* 1672 * For watchdog management we need to know if we have been 1673 * paused during the last interval, so capture that here. 1674 */ 1675 pause_frames = IGC_READ_REG(hw, IGC_XOFFRXC); 1676 stats->xoffrxc += pause_frames; 1677 stats->xofftxc += IGC_READ_REG(hw, IGC_XOFFTXC); 1678 stats->fcruc += IGC_READ_REG(hw, IGC_FCRUC); 1679 stats->prc64 += IGC_READ_REG(hw, IGC_PRC64); 1680 stats->prc127 += IGC_READ_REG(hw, IGC_PRC127); 1681 stats->prc255 += IGC_READ_REG(hw, IGC_PRC255); 1682 stats->prc511 += IGC_READ_REG(hw, IGC_PRC511); 1683 stats->prc1023 += IGC_READ_REG(hw, IGC_PRC1023); 1684 stats->prc1522 += IGC_READ_REG(hw, IGC_PRC1522); 1685 stats->gprc += IGC_READ_REG(hw, IGC_GPRC); 1686 stats->bprc += IGC_READ_REG(hw, IGC_BPRC); 1687 stats->mprc += IGC_READ_REG(hw, IGC_MPRC); 1688 stats->gptc += IGC_READ_REG(hw, IGC_GPTC); 1689 1690 /* For the 64-bit byte counters the low dword must be read first. */ 1691 /* Both registers clear on the read of the high dword */ 1692 1693 /* Workaround CRC bytes included in size, take away 4 bytes/packet */ 1694 stats->gorc += IGC_READ_REG(hw, IGC_GORCL); 1695 stats->gorc += ((uint64_t)IGC_READ_REG(hw, IGC_GORCH) << 32); 1696 stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN; 1697 stats->gotc += IGC_READ_REG(hw, IGC_GOTCL); 1698 stats->gotc += ((uint64_t)IGC_READ_REG(hw, IGC_GOTCH) << 32); 1699 stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN; 1700 1701 stats->rnbc += IGC_READ_REG(hw, IGC_RNBC); 1702 stats->ruc += IGC_READ_REG(hw, IGC_RUC); 1703 stats->rfc += IGC_READ_REG(hw, IGC_RFC); 1704 stats->roc += IGC_READ_REG(hw, IGC_ROC); 1705 stats->rjc += IGC_READ_REG(hw, IGC_RJC); 1706 1707 stats->mgprc += IGC_READ_REG(hw, IGC_MGTPRC); 1708 stats->mgpdc += IGC_READ_REG(hw, IGC_MGTPDC); 1709 stats->mgptc += IGC_READ_REG(hw, IGC_MGTPTC); 1710 stats->b2ospc += IGC_READ_REG(hw, IGC_B2OSPC); 1711 stats->b2ogprc += IGC_READ_REG(hw, IGC_B2OGPRC); 1712 stats->o2bgptc += IGC_READ_REG(hw, IGC_O2BGPTC); 1713 stats->o2bspc += IGC_READ_REG(hw, IGC_O2BSPC); 1714 1715 stats->tpr += IGC_READ_REG(hw, IGC_TPR); 1716 stats->tpt += IGC_READ_REG(hw, IGC_TPT); 1717 1718 stats->tor += IGC_READ_REG(hw, IGC_TORL); 1719 stats->tor += ((uint64_t)IGC_READ_REG(hw, IGC_TORH) << 32); 1720 stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN; 1721 stats->tot += IGC_READ_REG(hw, IGC_TOTL); 1722 stats->tot += ((uint64_t)IGC_READ_REG(hw, IGC_TOTH) << 32); 1723 stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN; 1724 1725 stats->ptc64 += IGC_READ_REG(hw, IGC_PTC64); 1726 stats->ptc127 += IGC_READ_REG(hw, IGC_PTC127); 1727 stats->ptc255 += IGC_READ_REG(hw, IGC_PTC255); 1728 stats->ptc511 += IGC_READ_REG(hw, IGC_PTC511); 1729 stats->ptc1023 += IGC_READ_REG(hw, IGC_PTC1023); 1730 stats->ptc1522 += IGC_READ_REG(hw, IGC_PTC1522); 1731 stats->mptc += IGC_READ_REG(hw, IGC_MPTC); 1732 stats->bptc += IGC_READ_REG(hw, IGC_BPTC); 1733 stats->tsctc += IGC_READ_REG(hw, IGC_TSCTC); 1734 1735 stats->iac += IGC_READ_REG(hw, IGC_IAC); 1736 stats->rpthc += IGC_READ_REG(hw, IGC_RPTHC); 1737 stats->hgptc += IGC_READ_REG(hw, IGC_HGPTC); 1738 stats->icrxdmtc += IGC_READ_REG(hw, IGC_ICRXDMTC); 1739 1740 /* Host to Card Statistics */ 1741 stats->hgorc += IGC_READ_REG(hw, IGC_HGORCL); 1742 stats->hgorc += ((uint64_t)IGC_READ_REG(hw, IGC_HGORCH) << 32); 1743 stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN; 1744 stats->hgotc += IGC_READ_REG(hw, IGC_HGOTCL); 1745 stats->hgotc += ((uint64_t)IGC_READ_REG(hw, IGC_HGOTCH) << 32); 1746 stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN; 1747 stats->lenerrs += IGC_READ_REG(hw, IGC_LENERRS); 1748 } 1749 1750 /* 1751 * Write 0 to all queue status registers 1752 */ 1753 static void 1754 igc_reset_queue_stats_register(struct igc_hw *hw) 1755 { 1756 int i; 1757 1758 for (i = 0; i < IGC_QUEUE_PAIRS_NUM; i++) { 1759 IGC_WRITE_REG(hw, IGC_PQGPRC(i), 0); 1760 IGC_WRITE_REG(hw, IGC_PQGPTC(i), 0); 1761 IGC_WRITE_REG(hw, IGC_PQGORC(i), 0); 1762 IGC_WRITE_REG(hw, IGC_PQGOTC(i), 0); 1763 IGC_WRITE_REG(hw, IGC_PQMPRC(i), 0); 1764 IGC_WRITE_REG(hw, IGC_RQDPC(i), 0); 1765 IGC_WRITE_REG(hw, IGC_TQDPC(i), 0); 1766 } 1767 } 1768 1769 /* 1770 * Read all hardware queue status registers 1771 */ 1772 static void 1773 igc_read_queue_stats_register(struct rte_eth_dev *dev) 1774 { 1775 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 1776 struct igc_hw_queue_stats *queue_stats = 1777 IGC_DEV_PRIVATE_QUEUE_STATS(dev); 1778 int i; 1779 1780 /* 1781 * This register is not cleared on read. Furthermore, the register wraps 1782 * around back to 0x00000000 on the next increment when reaching a value 1783 * of 0xFFFFFFFF and then continues normal count operation. 1784 */ 1785 for (i = 0; i < IGC_QUEUE_PAIRS_NUM; i++) { 1786 union { 1787 u64 ddword; 1788 u32 dword[2]; 1789 } value; 1790 u32 tmp; 1791 1792 /* 1793 * Read the register first, if the value is smaller than that 1794 * previous read, that mean the register has been overflowed, 1795 * then we add the high 4 bytes by 1 and replace the low 4 1796 * bytes by the new value. 1797 */ 1798 tmp = IGC_READ_REG(hw, IGC_PQGPRC(i)); 1799 value.ddword = queue_stats->pqgprc[i]; 1800 if (value.dword[U32_0_IN_U64] > tmp) 1801 value.dword[U32_1_IN_U64]++; 1802 value.dword[U32_0_IN_U64] = tmp; 1803 queue_stats->pqgprc[i] = value.ddword; 1804 1805 tmp = IGC_READ_REG(hw, IGC_PQGPTC(i)); 1806 value.ddword = queue_stats->pqgptc[i]; 1807 if (value.dword[U32_0_IN_U64] > tmp) 1808 value.dword[U32_1_IN_U64]++; 1809 value.dword[U32_0_IN_U64] = tmp; 1810 queue_stats->pqgptc[i] = value.ddword; 1811 1812 tmp = IGC_READ_REG(hw, IGC_PQGORC(i)); 1813 value.ddword = queue_stats->pqgorc[i]; 1814 if (value.dword[U32_0_IN_U64] > tmp) 1815 value.dword[U32_1_IN_U64]++; 1816 value.dword[U32_0_IN_U64] = tmp; 1817 queue_stats->pqgorc[i] = value.ddword; 1818 1819 tmp = IGC_READ_REG(hw, IGC_PQGOTC(i)); 1820 value.ddword = queue_stats->pqgotc[i]; 1821 if (value.dword[U32_0_IN_U64] > tmp) 1822 value.dword[U32_1_IN_U64]++; 1823 value.dword[U32_0_IN_U64] = tmp; 1824 queue_stats->pqgotc[i] = value.ddword; 1825 1826 tmp = IGC_READ_REG(hw, IGC_PQMPRC(i)); 1827 value.ddword = queue_stats->pqmprc[i]; 1828 if (value.dword[U32_0_IN_U64] > tmp) 1829 value.dword[U32_1_IN_U64]++; 1830 value.dword[U32_0_IN_U64] = tmp; 1831 queue_stats->pqmprc[i] = value.ddword; 1832 1833 tmp = IGC_READ_REG(hw, IGC_RQDPC(i)); 1834 value.ddword = queue_stats->rqdpc[i]; 1835 if (value.dword[U32_0_IN_U64] > tmp) 1836 value.dword[U32_1_IN_U64]++; 1837 value.dword[U32_0_IN_U64] = tmp; 1838 queue_stats->rqdpc[i] = value.ddword; 1839 1840 tmp = IGC_READ_REG(hw, IGC_TQDPC(i)); 1841 value.ddword = queue_stats->tqdpc[i]; 1842 if (value.dword[U32_0_IN_U64] > tmp) 1843 value.dword[U32_1_IN_U64]++; 1844 value.dword[U32_0_IN_U64] = tmp; 1845 queue_stats->tqdpc[i] = value.ddword; 1846 } 1847 } 1848 1849 static int 1850 eth_igc_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats) 1851 { 1852 struct igc_adapter *igc = IGC_DEV_PRIVATE(dev); 1853 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 1854 struct igc_hw_stats *stats = IGC_DEV_PRIVATE_STATS(dev); 1855 struct igc_hw_queue_stats *queue_stats = 1856 IGC_DEV_PRIVATE_QUEUE_STATS(dev); 1857 int i; 1858 1859 /* 1860 * Cancel status handler since it will read the queue status registers 1861 */ 1862 rte_eal_alarm_cancel(igc_update_queue_stats_handler, dev); 1863 1864 /* Read status register */ 1865 igc_read_queue_stats_register(dev); 1866 igc_read_stats_registers(hw, stats); 1867 1868 if (rte_stats == NULL) { 1869 /* Restart queue status handler */ 1870 rte_eal_alarm_set(IGC_ALARM_INTERVAL, 1871 igc_update_queue_stats_handler, dev); 1872 return -EINVAL; 1873 } 1874 1875 /* Rx Errors */ 1876 rte_stats->imissed = stats->mpc; 1877 rte_stats->ierrors = stats->crcerrs + stats->rlec + 1878 stats->rxerrc + stats->algnerrc; 1879 1880 /* Tx Errors */ 1881 rte_stats->oerrors = stats->ecol + stats->latecol; 1882 1883 rte_stats->ipackets = stats->gprc; 1884 rte_stats->opackets = stats->gptc; 1885 rte_stats->ibytes = stats->gorc; 1886 rte_stats->obytes = stats->gotc; 1887 1888 /* Get per-queue statuses */ 1889 for (i = 0; i < IGC_QUEUE_PAIRS_NUM; i++) { 1890 /* GET TX queue statuses */ 1891 int map_id = igc->txq_stats_map[i]; 1892 if (map_id >= 0) { 1893 rte_stats->q_opackets[map_id] += queue_stats->pqgptc[i]; 1894 rte_stats->q_obytes[map_id] += queue_stats->pqgotc[i]; 1895 } 1896 /* Get RX queue statuses */ 1897 map_id = igc->rxq_stats_map[i]; 1898 if (map_id >= 0) { 1899 rte_stats->q_ipackets[map_id] += queue_stats->pqgprc[i]; 1900 rte_stats->q_ibytes[map_id] += queue_stats->pqgorc[i]; 1901 rte_stats->q_errors[map_id] += queue_stats->rqdpc[i]; 1902 } 1903 } 1904 1905 /* Restart queue status handler */ 1906 rte_eal_alarm_set(IGC_ALARM_INTERVAL, 1907 igc_update_queue_stats_handler, dev); 1908 return 0; 1909 } 1910 1911 static int 1912 eth_igc_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1913 unsigned int n) 1914 { 1915 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 1916 struct igc_hw_stats *hw_stats = 1917 IGC_DEV_PRIVATE_STATS(dev); 1918 unsigned int i; 1919 1920 igc_read_stats_registers(hw, hw_stats); 1921 1922 if (n < IGC_NB_XSTATS) 1923 return IGC_NB_XSTATS; 1924 1925 /* If this is a reset xstats is NULL, and we have cleared the 1926 * registers by reading them. 1927 */ 1928 if (!xstats) 1929 return 0; 1930 1931 /* Extended stats */ 1932 for (i = 0; i < IGC_NB_XSTATS; i++) { 1933 xstats[i].id = i; 1934 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + 1935 rte_igc_stats_strings[i].offset); 1936 } 1937 1938 return IGC_NB_XSTATS; 1939 } 1940 1941 static int 1942 eth_igc_xstats_reset(struct rte_eth_dev *dev) 1943 { 1944 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 1945 struct igc_hw_stats *hw_stats = IGC_DEV_PRIVATE_STATS(dev); 1946 struct igc_hw_queue_stats *queue_stats = 1947 IGC_DEV_PRIVATE_QUEUE_STATS(dev); 1948 1949 /* Cancel queue status handler for avoid conflict */ 1950 rte_eal_alarm_cancel(igc_update_queue_stats_handler, dev); 1951 1952 /* HW registers are cleared on read */ 1953 igc_reset_queue_stats_register(hw); 1954 igc_read_stats_registers(hw, hw_stats); 1955 1956 /* Reset software totals */ 1957 memset(hw_stats, 0, sizeof(*hw_stats)); 1958 memset(queue_stats, 0, sizeof(*queue_stats)); 1959 1960 /* Restart the queue status handler */ 1961 rte_eal_alarm_set(IGC_ALARM_INTERVAL, igc_update_queue_stats_handler, 1962 dev); 1963 1964 return 0; 1965 } 1966 1967 static int 1968 eth_igc_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1969 struct rte_eth_xstat_name *xstats_names, unsigned int size) 1970 { 1971 unsigned int i; 1972 1973 if (xstats_names == NULL) 1974 return IGC_NB_XSTATS; 1975 1976 if (size < IGC_NB_XSTATS) { 1977 PMD_DRV_LOG(ERR, "not enough buffers!"); 1978 return IGC_NB_XSTATS; 1979 } 1980 1981 for (i = 0; i < IGC_NB_XSTATS; i++) 1982 strlcpy(xstats_names[i].name, rte_igc_stats_strings[i].name, 1983 sizeof(xstats_names[i].name)); 1984 1985 return IGC_NB_XSTATS; 1986 } 1987 1988 static int 1989 eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev, 1990 const uint64_t *ids, struct rte_eth_xstat_name *xstats_names, 1991 unsigned int limit) 1992 { 1993 unsigned int i; 1994 1995 if (!ids) 1996 return eth_igc_xstats_get_names(dev, xstats_names, limit); 1997 1998 for (i = 0; i < limit; i++) { 1999 if (ids[i] >= IGC_NB_XSTATS) { 2000 PMD_DRV_LOG(ERR, "id value isn't valid"); 2001 return -EINVAL; 2002 } 2003 strlcpy(xstats_names[i].name, 2004 rte_igc_stats_strings[ids[i]].name, 2005 sizeof(xstats_names[i].name)); 2006 } 2007 return limit; 2008 } 2009 2010 static int 2011 eth_igc_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 2012 uint64_t *values, unsigned int n) 2013 { 2014 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 2015 struct igc_hw_stats *hw_stats = IGC_DEV_PRIVATE_STATS(dev); 2016 unsigned int i; 2017 2018 igc_read_stats_registers(hw, hw_stats); 2019 2020 if (!ids) { 2021 if (n < IGC_NB_XSTATS) 2022 return IGC_NB_XSTATS; 2023 2024 /* If this is a reset xstats is NULL, and we have cleared the 2025 * registers by reading them. 2026 */ 2027 if (!values) 2028 return 0; 2029 2030 /* Extended stats */ 2031 for (i = 0; i < IGC_NB_XSTATS; i++) 2032 values[i] = *(uint64_t *)(((char *)hw_stats) + 2033 rte_igc_stats_strings[i].offset); 2034 2035 return IGC_NB_XSTATS; 2036 2037 } else { 2038 for (i = 0; i < n; i++) { 2039 if (ids[i] >= IGC_NB_XSTATS) { 2040 PMD_DRV_LOG(ERR, "id value isn't valid"); 2041 return -EINVAL; 2042 } 2043 values[i] = *(uint64_t *)(((char *)hw_stats) + 2044 rte_igc_stats_strings[ids[i]].offset); 2045 } 2046 return n; 2047 } 2048 } 2049 2050 static int 2051 eth_igc_queue_stats_mapping_set(struct rte_eth_dev *dev, 2052 uint16_t queue_id, uint8_t stat_idx, uint8_t is_rx) 2053 { 2054 struct igc_adapter *igc = IGC_DEV_PRIVATE(dev); 2055 2056 /* check queue id is valid */ 2057 if (queue_id >= IGC_QUEUE_PAIRS_NUM) { 2058 PMD_DRV_LOG(ERR, "queue id(%u) error, max is %u", 2059 queue_id, IGC_QUEUE_PAIRS_NUM - 1); 2060 return -EINVAL; 2061 } 2062 2063 /* store the mapping status id */ 2064 if (is_rx) 2065 igc->rxq_stats_map[queue_id] = stat_idx; 2066 else 2067 igc->txq_stats_map[queue_id] = stat_idx; 2068 2069 return 0; 2070 } 2071 2072 static int 2073 eth_igc_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 2074 { 2075 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 2076 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2077 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 2078 uint32_t vec = IGC_MISC_VEC_ID; 2079 2080 if (rte_intr_allow_others(intr_handle)) 2081 vec = IGC_RX_VEC_START; 2082 2083 uint32_t mask = 1u << (queue_id + vec); 2084 2085 IGC_WRITE_REG(hw, IGC_EIMC, mask); 2086 IGC_WRITE_FLUSH(hw); 2087 2088 return 0; 2089 } 2090 2091 static int 2092 eth_igc_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 2093 { 2094 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 2095 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2096 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 2097 uint32_t vec = IGC_MISC_VEC_ID; 2098 2099 if (rte_intr_allow_others(intr_handle)) 2100 vec = IGC_RX_VEC_START; 2101 2102 uint32_t mask = 1u << (queue_id + vec); 2103 2104 IGC_WRITE_REG(hw, IGC_EIMS, mask); 2105 IGC_WRITE_FLUSH(hw); 2106 2107 rte_intr_enable(intr_handle); 2108 2109 return 0; 2110 } 2111 2112 static int 2113 eth_igc_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2114 { 2115 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 2116 uint32_t ctrl; 2117 int tx_pause; 2118 int rx_pause; 2119 2120 fc_conf->pause_time = hw->fc.pause_time; 2121 fc_conf->high_water = hw->fc.high_water; 2122 fc_conf->low_water = hw->fc.low_water; 2123 fc_conf->send_xon = hw->fc.send_xon; 2124 fc_conf->autoneg = hw->mac.autoneg; 2125 2126 /* 2127 * Return rx_pause and tx_pause status according to actual setting of 2128 * the TFCE and RFCE bits in the CTRL register. 2129 */ 2130 ctrl = IGC_READ_REG(hw, IGC_CTRL); 2131 if (ctrl & IGC_CTRL_TFCE) 2132 tx_pause = 1; 2133 else 2134 tx_pause = 0; 2135 2136 if (ctrl & IGC_CTRL_RFCE) 2137 rx_pause = 1; 2138 else 2139 rx_pause = 0; 2140 2141 if (rx_pause && tx_pause) 2142 fc_conf->mode = RTE_ETH_FC_FULL; 2143 else if (rx_pause) 2144 fc_conf->mode = RTE_ETH_FC_RX_PAUSE; 2145 else if (tx_pause) 2146 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 2147 else 2148 fc_conf->mode = RTE_ETH_FC_NONE; 2149 2150 return 0; 2151 } 2152 2153 static int 2154 eth_igc_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2155 { 2156 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 2157 uint32_t rx_buf_size; 2158 uint32_t max_high_water; 2159 uint32_t rctl; 2160 int err; 2161 2162 if (fc_conf->autoneg != hw->mac.autoneg) 2163 return -ENOTSUP; 2164 2165 rx_buf_size = igc_get_rx_buffer_size(hw); 2166 PMD_DRV_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 2167 2168 /* At least reserve one Ethernet frame for watermark */ 2169 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN; 2170 if (fc_conf->high_water > max_high_water || 2171 fc_conf->high_water < fc_conf->low_water) { 2172 PMD_DRV_LOG(ERR, 2173 "Incorrect high(%u)/low(%u) water value, max is %u", 2174 fc_conf->high_water, fc_conf->low_water, 2175 max_high_water); 2176 return -EINVAL; 2177 } 2178 2179 switch (fc_conf->mode) { 2180 case RTE_ETH_FC_NONE: 2181 hw->fc.requested_mode = igc_fc_none; 2182 break; 2183 case RTE_ETH_FC_RX_PAUSE: 2184 hw->fc.requested_mode = igc_fc_rx_pause; 2185 break; 2186 case RTE_ETH_FC_TX_PAUSE: 2187 hw->fc.requested_mode = igc_fc_tx_pause; 2188 break; 2189 case RTE_ETH_FC_FULL: 2190 hw->fc.requested_mode = igc_fc_full; 2191 break; 2192 default: 2193 PMD_DRV_LOG(ERR, "unsupported fc mode: %u", fc_conf->mode); 2194 return -EINVAL; 2195 } 2196 2197 hw->fc.pause_time = fc_conf->pause_time; 2198 hw->fc.high_water = fc_conf->high_water; 2199 hw->fc.low_water = fc_conf->low_water; 2200 hw->fc.send_xon = fc_conf->send_xon; 2201 2202 err = igc_setup_link_generic(hw); 2203 if (err == IGC_SUCCESS) { 2204 /** 2205 * check if we want to forward MAC frames - driver doesn't have 2206 * native capability to do that, so we'll write the registers 2207 * ourselves 2208 **/ 2209 rctl = IGC_READ_REG(hw, IGC_RCTL); 2210 2211 /* set or clear MFLCN.PMCF bit depending on configuration */ 2212 if (fc_conf->mac_ctrl_frame_fwd != 0) 2213 rctl |= IGC_RCTL_PMCF; 2214 else 2215 rctl &= ~IGC_RCTL_PMCF; 2216 2217 IGC_WRITE_REG(hw, IGC_RCTL, rctl); 2218 IGC_WRITE_FLUSH(hw); 2219 2220 return 0; 2221 } 2222 2223 PMD_DRV_LOG(ERR, "igc_setup_link_generic = 0x%x", err); 2224 return -EIO; 2225 } 2226 2227 static int 2228 eth_igc_rss_reta_update(struct rte_eth_dev *dev, 2229 struct rte_eth_rss_reta_entry64 *reta_conf, 2230 uint16_t reta_size) 2231 { 2232 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 2233 uint16_t i; 2234 2235 if (reta_size != RTE_ETH_RSS_RETA_SIZE_128) { 2236 PMD_DRV_LOG(ERR, 2237 "The size of RSS redirection table configured(%d) doesn't match the number hardware can supported(%d)", 2238 reta_size, RTE_ETH_RSS_RETA_SIZE_128); 2239 return -EINVAL; 2240 } 2241 2242 RTE_BUILD_BUG_ON(RTE_ETH_RSS_RETA_SIZE_128 % IGC_RSS_RDT_REG_SIZE); 2243 2244 /* set redirection table */ 2245 for (i = 0; i < RTE_ETH_RSS_RETA_SIZE_128; i += IGC_RSS_RDT_REG_SIZE) { 2246 union igc_rss_reta_reg reta, reg; 2247 uint16_t idx, shift; 2248 uint8_t j, mask; 2249 2250 idx = i / RTE_ETH_RETA_GROUP_SIZE; 2251 shift = i % RTE_ETH_RETA_GROUP_SIZE; 2252 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 2253 IGC_RSS_RDT_REG_SIZE_MASK); 2254 2255 /* if no need to update the register */ 2256 if (!mask || 2257 shift > (RTE_ETH_RETA_GROUP_SIZE - IGC_RSS_RDT_REG_SIZE)) 2258 continue; 2259 2260 /* check mask whether need to read the register value first */ 2261 if (mask == IGC_RSS_RDT_REG_SIZE_MASK) 2262 reg.dword = 0; 2263 else 2264 reg.dword = IGC_READ_REG_LE_VALUE(hw, 2265 IGC_RETA(i / IGC_RSS_RDT_REG_SIZE)); 2266 2267 /* update the register */ 2268 RTE_BUILD_BUG_ON(sizeof(reta.bytes) != IGC_RSS_RDT_REG_SIZE); 2269 for (j = 0; j < IGC_RSS_RDT_REG_SIZE; j++) { 2270 if (mask & (1u << j)) 2271 reta.bytes[j] = 2272 (uint8_t)reta_conf[idx].reta[shift + j]; 2273 else 2274 reta.bytes[j] = reg.bytes[j]; 2275 } 2276 IGC_WRITE_REG_LE_VALUE(hw, 2277 IGC_RETA(i / IGC_RSS_RDT_REG_SIZE), reta.dword); 2278 } 2279 2280 return 0; 2281 } 2282 2283 static int 2284 eth_igc_rss_reta_query(struct rte_eth_dev *dev, 2285 struct rte_eth_rss_reta_entry64 *reta_conf, 2286 uint16_t reta_size) 2287 { 2288 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 2289 uint16_t i; 2290 2291 if (reta_size != RTE_ETH_RSS_RETA_SIZE_128) { 2292 PMD_DRV_LOG(ERR, 2293 "The size of RSS redirection table configured(%d) doesn't match the number hardware can supported(%d)", 2294 reta_size, RTE_ETH_RSS_RETA_SIZE_128); 2295 return -EINVAL; 2296 } 2297 2298 RTE_BUILD_BUG_ON(RTE_ETH_RSS_RETA_SIZE_128 % IGC_RSS_RDT_REG_SIZE); 2299 2300 /* read redirection table */ 2301 for (i = 0; i < RTE_ETH_RSS_RETA_SIZE_128; i += IGC_RSS_RDT_REG_SIZE) { 2302 union igc_rss_reta_reg reta; 2303 uint16_t idx, shift; 2304 uint8_t j, mask; 2305 2306 idx = i / RTE_ETH_RETA_GROUP_SIZE; 2307 shift = i % RTE_ETH_RETA_GROUP_SIZE; 2308 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 2309 IGC_RSS_RDT_REG_SIZE_MASK); 2310 2311 /* if no need to read register */ 2312 if (!mask || 2313 shift > (RTE_ETH_RETA_GROUP_SIZE - IGC_RSS_RDT_REG_SIZE)) 2314 continue; 2315 2316 /* read register and get the queue index */ 2317 RTE_BUILD_BUG_ON(sizeof(reta.bytes) != IGC_RSS_RDT_REG_SIZE); 2318 reta.dword = IGC_READ_REG_LE_VALUE(hw, 2319 IGC_RETA(i / IGC_RSS_RDT_REG_SIZE)); 2320 for (j = 0; j < IGC_RSS_RDT_REG_SIZE; j++) { 2321 if (mask & (1u << j)) 2322 reta_conf[idx].reta[shift + j] = reta.bytes[j]; 2323 } 2324 } 2325 2326 return 0; 2327 } 2328 2329 static int 2330 eth_igc_rss_hash_update(struct rte_eth_dev *dev, 2331 struct rte_eth_rss_conf *rss_conf) 2332 { 2333 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 2334 igc_hw_rss_hash_set(hw, rss_conf); 2335 return 0; 2336 } 2337 2338 static int 2339 eth_igc_rss_hash_conf_get(struct rte_eth_dev *dev, 2340 struct rte_eth_rss_conf *rss_conf) 2341 { 2342 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 2343 uint32_t *hash_key = (uint32_t *)rss_conf->rss_key; 2344 uint32_t mrqc; 2345 uint64_t rss_hf; 2346 2347 if (hash_key != NULL) { 2348 int i; 2349 2350 /* if not enough space for store hash key */ 2351 if (rss_conf->rss_key_len != IGC_HKEY_SIZE) { 2352 PMD_DRV_LOG(ERR, 2353 "RSS hash key size %u in parameter doesn't match the hardware hash key size %u", 2354 rss_conf->rss_key_len, IGC_HKEY_SIZE); 2355 return -EINVAL; 2356 } 2357 2358 /* read RSS key from register */ 2359 for (i = 0; i < IGC_HKEY_MAX_INDEX; i++) 2360 hash_key[i] = IGC_READ_REG_LE_VALUE(hw, IGC_RSSRK(i)); 2361 } 2362 2363 /* get RSS functions configured in MRQC register */ 2364 mrqc = IGC_READ_REG(hw, IGC_MRQC); 2365 if ((mrqc & IGC_MRQC_ENABLE_RSS_4Q) == 0) 2366 return 0; 2367 2368 rss_hf = 0; 2369 if (mrqc & IGC_MRQC_RSS_FIELD_IPV4) 2370 rss_hf |= RTE_ETH_RSS_IPV4; 2371 if (mrqc & IGC_MRQC_RSS_FIELD_IPV4_TCP) 2372 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP; 2373 if (mrqc & IGC_MRQC_RSS_FIELD_IPV6) 2374 rss_hf |= RTE_ETH_RSS_IPV6; 2375 if (mrqc & IGC_MRQC_RSS_FIELD_IPV6_EX) 2376 rss_hf |= RTE_ETH_RSS_IPV6_EX; 2377 if (mrqc & IGC_MRQC_RSS_FIELD_IPV6_TCP) 2378 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_TCP; 2379 if (mrqc & IGC_MRQC_RSS_FIELD_IPV6_TCP_EX) 2380 rss_hf |= RTE_ETH_RSS_IPV6_TCP_EX; 2381 if (mrqc & IGC_MRQC_RSS_FIELD_IPV4_UDP) 2382 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP; 2383 if (mrqc & IGC_MRQC_RSS_FIELD_IPV6_UDP) 2384 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_UDP; 2385 if (mrqc & IGC_MRQC_RSS_FIELD_IPV6_UDP_EX) 2386 rss_hf |= RTE_ETH_RSS_IPV6_UDP_EX; 2387 2388 rss_conf->rss_hf |= rss_hf; 2389 return 0; 2390 } 2391 2392 static int 2393 eth_igc_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 2394 { 2395 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 2396 struct igc_vfta *shadow_vfta = IGC_DEV_PRIVATE_VFTA(dev); 2397 uint32_t vfta; 2398 uint32_t vid_idx; 2399 uint32_t vid_bit; 2400 2401 vid_idx = (vlan_id >> IGC_VFTA_ENTRY_SHIFT) & IGC_VFTA_ENTRY_MASK; 2402 vid_bit = 1u << (vlan_id & IGC_VFTA_ENTRY_BIT_SHIFT_MASK); 2403 vfta = shadow_vfta->vfta[vid_idx]; 2404 if (on) 2405 vfta |= vid_bit; 2406 else 2407 vfta &= ~vid_bit; 2408 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, vid_idx, vfta); 2409 2410 /* update local VFTA copy */ 2411 shadow_vfta->vfta[vid_idx] = vfta; 2412 2413 return 0; 2414 } 2415 2416 static void 2417 igc_vlan_hw_filter_disable(struct rte_eth_dev *dev) 2418 { 2419 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 2420 igc_read_reg_check_clear_bits(hw, IGC_RCTL, 2421 IGC_RCTL_CFIEN | IGC_RCTL_VFE); 2422 } 2423 2424 static void 2425 igc_vlan_hw_filter_enable(struct rte_eth_dev *dev) 2426 { 2427 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 2428 struct igc_vfta *shadow_vfta = IGC_DEV_PRIVATE_VFTA(dev); 2429 uint32_t reg_val; 2430 int i; 2431 2432 /* Filter Table Enable, CFI not used for packet acceptance */ 2433 reg_val = IGC_READ_REG(hw, IGC_RCTL); 2434 reg_val &= ~IGC_RCTL_CFIEN; 2435 reg_val |= IGC_RCTL_VFE; 2436 IGC_WRITE_REG(hw, IGC_RCTL, reg_val); 2437 2438 /* restore VFTA table */ 2439 for (i = 0; i < IGC_VFTA_SIZE; i++) 2440 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, i, shadow_vfta->vfta[i]); 2441 } 2442 2443 static void 2444 igc_vlan_hw_strip_disable(struct rte_eth_dev *dev) 2445 { 2446 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 2447 2448 igc_read_reg_check_clear_bits(hw, IGC_CTRL, IGC_CTRL_VME); 2449 } 2450 2451 static void 2452 igc_vlan_hw_strip_enable(struct rte_eth_dev *dev) 2453 { 2454 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 2455 2456 igc_read_reg_check_set_bits(hw, IGC_CTRL, IGC_CTRL_VME); 2457 } 2458 2459 static int 2460 igc_vlan_hw_extend_disable(struct rte_eth_dev *dev) 2461 { 2462 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 2463 uint32_t frame_size = dev->data->mtu + IGC_ETH_OVERHEAD; 2464 uint32_t ctrl_ext; 2465 2466 ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT); 2467 2468 /* if extend vlan hasn't been enabled */ 2469 if ((ctrl_ext & IGC_CTRL_EXT_EXT_VLAN) == 0) 2470 return 0; 2471 2472 /* Update maximum packet length */ 2473 if (frame_size < RTE_ETHER_MIN_MTU + VLAN_TAG_SIZE) { 2474 PMD_DRV_LOG(ERR, "Maximum packet length %u error, min is %u", 2475 frame_size, VLAN_TAG_SIZE + RTE_ETHER_MIN_MTU); 2476 return -EINVAL; 2477 } 2478 IGC_WRITE_REG(hw, IGC_RLPML, frame_size - VLAN_TAG_SIZE); 2479 2480 IGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext & ~IGC_CTRL_EXT_EXT_VLAN); 2481 return 0; 2482 } 2483 2484 static int 2485 igc_vlan_hw_extend_enable(struct rte_eth_dev *dev) 2486 { 2487 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 2488 uint32_t frame_size = dev->data->mtu + IGC_ETH_OVERHEAD; 2489 uint32_t ctrl_ext; 2490 2491 ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT); 2492 2493 /* if extend vlan has been enabled */ 2494 if (ctrl_ext & IGC_CTRL_EXT_EXT_VLAN) 2495 return 0; 2496 2497 /* Update maximum packet length */ 2498 if (frame_size > MAX_RX_JUMBO_FRAME_SIZE) { 2499 PMD_DRV_LOG(ERR, "Maximum packet length %u error, max is %u", 2500 frame_size, MAX_RX_JUMBO_FRAME_SIZE); 2501 return -EINVAL; 2502 } 2503 IGC_WRITE_REG(hw, IGC_RLPML, frame_size); 2504 2505 IGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext | IGC_CTRL_EXT_EXT_VLAN); 2506 return 0; 2507 } 2508 2509 static int 2510 eth_igc_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2511 { 2512 struct rte_eth_rxmode *rxmode; 2513 2514 rxmode = &dev->data->dev_conf.rxmode; 2515 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 2516 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 2517 igc_vlan_hw_strip_enable(dev); 2518 else 2519 igc_vlan_hw_strip_disable(dev); 2520 } 2521 2522 if (mask & RTE_ETH_VLAN_FILTER_MASK) { 2523 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) 2524 igc_vlan_hw_filter_enable(dev); 2525 else 2526 igc_vlan_hw_filter_disable(dev); 2527 } 2528 2529 if (mask & RTE_ETH_VLAN_EXTEND_MASK) { 2530 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) 2531 return igc_vlan_hw_extend_enable(dev); 2532 else 2533 return igc_vlan_hw_extend_disable(dev); 2534 } 2535 2536 return 0; 2537 } 2538 2539 static int 2540 eth_igc_vlan_tpid_set(struct rte_eth_dev *dev, 2541 enum rte_vlan_type vlan_type, 2542 uint16_t tpid) 2543 { 2544 struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev); 2545 uint32_t reg_val; 2546 2547 /* only outer TPID of double VLAN can be configured*/ 2548 if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) { 2549 reg_val = IGC_READ_REG(hw, IGC_VET); 2550 reg_val = (reg_val & (~IGC_VET_EXT)) | 2551 ((uint32_t)tpid << IGC_VET_EXT_SHIFT); 2552 IGC_WRITE_REG(hw, IGC_VET, reg_val); 2553 2554 return 0; 2555 } 2556 2557 /* all other TPID values are read-only*/ 2558 PMD_DRV_LOG(ERR, "Not supported"); 2559 return -ENOTSUP; 2560 } 2561 2562 static int 2563 eth_igc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2564 struct rte_pci_device *pci_dev) 2565 { 2566 PMD_INIT_FUNC_TRACE(); 2567 return rte_eth_dev_pci_generic_probe(pci_dev, 2568 sizeof(struct igc_adapter), eth_igc_dev_init); 2569 } 2570 2571 static int 2572 eth_igc_pci_remove(struct rte_pci_device *pci_dev) 2573 { 2574 PMD_INIT_FUNC_TRACE(); 2575 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igc_dev_uninit); 2576 } 2577 2578 static struct rte_pci_driver rte_igc_pmd = { 2579 .id_table = pci_id_igc_map, 2580 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 2581 .probe = eth_igc_pci_probe, 2582 .remove = eth_igc_pci_remove, 2583 }; 2584 2585 RTE_PMD_REGISTER_PCI(net_igc, rte_igc_pmd); 2586 RTE_PMD_REGISTER_PCI_TABLE(net_igc, pci_id_igc_map); 2587 RTE_PMD_REGISTER_KMOD_DEP(net_igc, "* igb_uio | uio_pci_generic | vfio-pci"); 2588