1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 5 #ifndef _ICE_ETHDEV_H_ 6 #define _ICE_ETHDEV_H_ 7 8 #include <rte_kvargs.h> 9 #include <rte_time.h> 10 11 #include <ethdev_driver.h> 12 13 #include "base/ice_common.h" 14 #include "base/ice_adminq_cmd.h" 15 #include "base/ice_flow.h" 16 17 #define ICE_VLAN_TAG_SIZE 4 18 19 #define ICE_ADMINQ_LEN 32 20 #define ICE_SBIOQ_LEN 32 21 #define ICE_MAILBOXQ_LEN 32 22 #define ICE_SBQ_LEN 64 23 #define ICE_ADMINQ_BUF_SZ 4096 24 #define ICE_SBIOQ_BUF_SZ 4096 25 #define ICE_MAILBOXQ_BUF_SZ 4096 26 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ 27 #define ICE_MAX_Q_PER_TC 64 28 #define ICE_NUM_DESC_DEFAULT 512 29 #define ICE_BUF_SIZE_MIN 1024 30 #define ICE_FRAME_SIZE_MAX 9728 31 #define ICE_QUEUE_BASE_ADDR_UNIT 128 32 /* number of VSIs and queue default setting */ 33 #define ICE_MAX_QP_NUM_PER_VF 16 34 #define ICE_DEFAULT_QP_NUM_FDIR 1 35 #define ICE_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) 36 #define ICE_VFTA_SIZE (4096 / ICE_UINT32_BIT_SIZE) 37 /* Maximun number of MAC addresses */ 38 #define ICE_NUM_MACADDR_MAX 64 39 /* Maximum number of VFs */ 40 #define ICE_MAX_VF 128 41 #define ICE_MAX_INTR_QUEUE_NUM 256 42 43 #define ICE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 44 #define ICE_RX_VEC_ID RTE_INTR_VEC_RXTX_OFFSET 45 46 #define ICE_MAX_PKT_TYPE 1024 47 48 /* DDP package search path */ 49 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg" 50 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg" 51 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/" 52 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/" 53 #define ICE_MAX_PKG_FILENAME_SIZE 256 54 55 #define MAX_ACL_NORMAL_ENTRIES 256 56 57 /** 58 * vlan_id is a 12 bit number. 59 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 60 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 61 * The higher 7 bit val specifies VFTA array index. 62 */ 63 #define ICE_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 64 #define ICE_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 65 66 /* Default TC traffic in case DCB is not enabled */ 67 #define ICE_DEFAULT_TCMAP 0x1 68 #define ICE_FDIR_QUEUE_ID 0 69 70 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ 71 #define ICE_VMDQ_POOL_BASE 1 72 73 #define ICE_DEFAULT_RX_FREE_THRESH 32 74 #define ICE_DEFAULT_RX_PTHRESH 8 75 #define ICE_DEFAULT_RX_HTHRESH 8 76 #define ICE_DEFAULT_RX_WTHRESH 0 77 78 #define ICE_DEFAULT_TX_FREE_THRESH 32 79 #define ICE_DEFAULT_TX_PTHRESH 32 80 #define ICE_DEFAULT_TX_HTHRESH 0 81 #define ICE_DEFAULT_TX_WTHRESH 0 82 #define ICE_DEFAULT_TX_RSBIT_THRESH 32 83 84 /* Bit shift and mask */ 85 #define ICE_4_BIT_WIDTH (CHAR_BIT / 2) 86 #define ICE_4_BIT_MASK RTE_LEN2MASK(ICE_4_BIT_WIDTH, uint8_t) 87 #define ICE_8_BIT_WIDTH CHAR_BIT 88 #define ICE_8_BIT_MASK UINT8_MAX 89 #define ICE_16_BIT_WIDTH (CHAR_BIT * 2) 90 #define ICE_16_BIT_MASK UINT16_MAX 91 #define ICE_32_BIT_WIDTH (CHAR_BIT * 4) 92 #define ICE_32_BIT_MASK UINT32_MAX 93 #define ICE_40_BIT_WIDTH (CHAR_BIT * 5) 94 #define ICE_40_BIT_MASK RTE_LEN2MASK(ICE_40_BIT_WIDTH, uint64_t) 95 #define ICE_48_BIT_WIDTH (CHAR_BIT * 6) 96 #define ICE_48_BIT_MASK RTE_LEN2MASK(ICE_48_BIT_WIDTH, uint64_t) 97 98 #define ICE_FLAG_RSS BIT_ULL(0) 99 #define ICE_FLAG_DCB BIT_ULL(1) 100 #define ICE_FLAG_VMDQ BIT_ULL(2) 101 #define ICE_FLAG_SRIOV BIT_ULL(3) 102 #define ICE_FLAG_HEADER_SPLIT_DISABLED BIT_ULL(4) 103 #define ICE_FLAG_HEADER_SPLIT_ENABLED BIT_ULL(5) 104 #define ICE_FLAG_FDIR BIT_ULL(6) 105 #define ICE_FLAG_VXLAN BIT_ULL(7) 106 #define ICE_FLAG_RSS_AQ_CAPABLE BIT_ULL(8) 107 #define ICE_FLAG_VF_MAC_BY_PF BIT_ULL(9) 108 #define ICE_FLAG_ALL (ICE_FLAG_RSS | \ 109 ICE_FLAG_DCB | \ 110 ICE_FLAG_VMDQ | \ 111 ICE_FLAG_SRIOV | \ 112 ICE_FLAG_HEADER_SPLIT_DISABLED | \ 113 ICE_FLAG_HEADER_SPLIT_ENABLED | \ 114 ICE_FLAG_FDIR | \ 115 ICE_FLAG_VXLAN | \ 116 ICE_FLAG_RSS_AQ_CAPABLE | \ 117 ICE_FLAG_VF_MAC_BY_PF) 118 119 #define ICE_RSS_OFFLOAD_ALL ( \ 120 RTE_ETH_RSS_IPV4 | \ 121 RTE_ETH_RSS_FRAG_IPV4 | \ 122 RTE_ETH_RSS_NONFRAG_IPV4_TCP | \ 123 RTE_ETH_RSS_NONFRAG_IPV4_UDP | \ 124 RTE_ETH_RSS_NONFRAG_IPV4_SCTP | \ 125 RTE_ETH_RSS_NONFRAG_IPV4_OTHER | \ 126 RTE_ETH_RSS_IPV6 | \ 127 RTE_ETH_RSS_FRAG_IPV6 | \ 128 RTE_ETH_RSS_NONFRAG_IPV6_TCP | \ 129 RTE_ETH_RSS_NONFRAG_IPV6_UDP | \ 130 RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \ 131 RTE_ETH_RSS_NONFRAG_IPV6_OTHER | \ 132 RTE_ETH_RSS_L2_PAYLOAD) 133 134 /** 135 * The overhead from MTU to max frame size. 136 * Considering QinQ packet, the VLAN tag needs to be counted twice. 137 */ 138 #define ICE_ETH_OVERHEAD \ 139 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE * 2) 140 #define ICE_ETH_MAX_LEN (RTE_ETHER_MTU + ICE_ETH_OVERHEAD) 141 142 #define ICE_RXTX_BYTES_HIGH(bytes) ((bytes) & ~ICE_40_BIT_MASK) 143 #define ICE_RXTX_BYTES_LOW(bytes) ((bytes) & ICE_40_BIT_MASK) 144 145 /* Max number of flexible descriptor rxdid */ 146 #define ICE_FLEX_DESC_RXDID_MAX_NUM 64 147 148 /* Per-channel register definitions */ 149 #define GLTSYN_AUX_OUT(_chan, _idx) (GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8)) 150 #define GLTSYN_CLKO(_chan, _idx) (GLTSYN_CLKO_0(_idx) + ((_chan) * 8)) 151 #define GLTSYN_TGT_L(_chan, _idx) (GLTSYN_TGT_L_0(_idx) + ((_chan) * 16)) 152 #define GLTSYN_TGT_H(_chan, _idx) (GLTSYN_TGT_H_0(_idx) + ((_chan) * 16)) 153 154 /* DDP package type */ 155 enum ice_pkg_type { 156 ICE_PKG_TYPE_UNKNOWN, 157 ICE_PKG_TYPE_OS_DEFAULT, 158 ICE_PKG_TYPE_COMMS, 159 }; 160 161 enum pps_type { 162 PPS_NONE, 163 PPS_PIN, 164 PPS_MAX, 165 }; 166 167 struct ice_adapter; 168 169 /** 170 * MAC filter structure 171 */ 172 struct ice_mac_filter_info { 173 struct rte_ether_addr mac_addr; 174 }; 175 176 TAILQ_HEAD(ice_mac_filter_list, ice_mac_filter); 177 178 /* MAC filter list structure */ 179 struct ice_mac_filter { 180 TAILQ_ENTRY(ice_mac_filter) next; 181 struct ice_mac_filter_info mac_info; 182 }; 183 184 struct ice_vlan { 185 uint16_t tpid; 186 uint16_t vid; 187 }; 188 189 #define ICE_VLAN(tpid, vid) \ 190 ((struct ice_vlan){ tpid, vid }) 191 192 /** 193 * VLAN filter structure 194 */ 195 struct ice_vlan_filter_info { 196 struct ice_vlan vlan; 197 }; 198 199 TAILQ_HEAD(ice_vlan_filter_list, ice_vlan_filter); 200 201 /* VLAN filter list structure */ 202 struct ice_vlan_filter { 203 TAILQ_ENTRY(ice_vlan_filter) next; 204 struct ice_vlan_filter_info vlan_info; 205 }; 206 207 struct pool_entry { 208 LIST_ENTRY(pool_entry) next; 209 uint16_t base; 210 uint16_t len; 211 }; 212 213 LIST_HEAD(res_list, pool_entry); 214 215 struct ice_res_pool_info { 216 uint32_t base; /* Resource start index */ 217 uint32_t num_alloc; /* Allocated resource number */ 218 uint32_t num_free; /* Total available resource number */ 219 struct res_list alloc_list; /* Allocated resource list */ 220 struct res_list free_list; /* Available resource list */ 221 }; 222 223 TAILQ_HEAD(ice_vsi_list_head, ice_vsi_list); 224 225 struct ice_vsi; 226 227 /* VSI list structure */ 228 struct ice_vsi_list { 229 TAILQ_ENTRY(ice_vsi_list) list; 230 struct ice_vsi *vsi; 231 }; 232 233 struct ice_rx_queue; 234 struct ice_tx_queue; 235 236 /** 237 * Structure that defines a VSI, associated with a adapter. 238 */ 239 struct ice_vsi { 240 struct ice_adapter *adapter; /* Backreference to associated adapter */ 241 struct ice_aqc_vsi_props info; /* VSI properties */ 242 /** 243 * When drivers loaded, only a default main VSI exists. In case new VSI 244 * needs to add, HW needs to know the layout that VSIs are organized. 245 * Besides that, VSI isan element and can't switch packets, which needs 246 * to add new component VEB to perform switching. So, a new VSI needs 247 * to specify the the uplink VSI (Parent VSI) before created. The 248 * uplink VSI will check whether it had a VEB to switch packets. If no, 249 * it will try to create one. Then, uplink VSI will move the new VSI 250 * into its' sib_vsi_list to manage all the downlink VSI. 251 * sib_vsi_list: the VSI list that shared the same uplink VSI. 252 * parent_vsi : the uplink VSI. It's NULL for main VSI. 253 * veb : the VEB associates with the VSI. 254 */ 255 struct ice_vsi_list sib_vsi_list; /* sibling vsi list */ 256 struct ice_vsi *parent_vsi; 257 enum ice_vsi_type type; /* VSI types */ 258 uint16_t vlan_num; /* Total VLAN number */ 259 uint16_t mac_num; /* Total mac number */ 260 struct ice_mac_filter_list mac_list; /* macvlan filter list */ 261 struct ice_vlan_filter_list vlan_list; /* vlan filter list */ 262 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ 263 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ 264 uint16_t max_macaddrs; /* Maximum number of MAC addresses */ 265 uint16_t base_queue; /* The first queue index of this VSI */ 266 uint16_t vsi_id; /* Hardware Id */ 267 uint16_t idx; /* vsi_handle: SW index in hw->vsi_ctx */ 268 /* VF number to which the VSI connects, valid when VSI is VF type */ 269 uint8_t vf_num; 270 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ 271 uint16_t nb_msix; /* The max number of msix vector */ 272 uint8_t enabled_tc; /* The traffic class enabled */ 273 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ 274 uint8_t vlan_filter_on; /* The VLAN filter enabled */ 275 /* information about rss configuration */ 276 u32 rss_key_size; 277 u32 rss_lut_size; 278 uint8_t *rss_lut; 279 uint8_t *rss_key; 280 struct ice_eth_stats eth_stats_offset; 281 struct ice_eth_stats eth_stats; 282 bool offset_loaded; 283 uint64_t old_rx_bytes; 284 uint64_t old_tx_bytes; 285 }; 286 287 enum proto_xtr_type { 288 PROTO_XTR_NONE, 289 PROTO_XTR_VLAN, 290 PROTO_XTR_IPV4, 291 PROTO_XTR_IPV6, 292 PROTO_XTR_IPV6_FLOW, 293 PROTO_XTR_TCP, 294 PROTO_XTR_IP_OFFSET, 295 PROTO_XTR_MAX /* The last one */ 296 }; 297 298 enum ice_fdir_tunnel_type { 299 ICE_FDIR_TUNNEL_TYPE_NONE = 0, 300 ICE_FDIR_TUNNEL_TYPE_VXLAN, 301 ICE_FDIR_TUNNEL_TYPE_GTPU, 302 ICE_FDIR_TUNNEL_TYPE_GTPU_EH, 303 }; 304 305 struct rte_flow; 306 TAILQ_HEAD(ice_flow_list, rte_flow); 307 308 struct ice_flow_parser_node; 309 TAILQ_HEAD(ice_parser_list, ice_flow_parser_node); 310 311 struct ice_fdir_filter_conf { 312 struct ice_fdir_fltr input; 313 enum ice_fdir_tunnel_type tunnel_type; 314 315 struct ice_fdir_counter *counter; /* flow specific counter context */ 316 struct rte_flow_action_count act_count; 317 318 uint64_t input_set_o; /* used for non-tunnel or tunnel outer fields */ 319 uint64_t input_set_i; /* only for tunnel inner fields */ 320 uint32_t mark_flag; 321 322 struct ice_parser_profile *prof; 323 bool parser_ena; 324 u8 *pkt_buf; 325 u8 pkt_len; 326 }; 327 328 #define ICE_MAX_FDIR_FILTER_NUM (1024 * 16) 329 330 struct ice_fdir_fltr_pattern { 331 enum ice_fltr_ptype flow_type; 332 333 union { 334 struct ice_fdir_v4 v4; 335 struct ice_fdir_v6 v6; 336 } ip, mask; 337 338 struct ice_fdir_udp_gtp gtpu_data; 339 struct ice_fdir_udp_gtp gtpu_mask; 340 341 struct ice_fdir_extra ext_data; 342 struct ice_fdir_extra ext_mask; 343 344 enum ice_fdir_tunnel_type tunnel_type; 345 }; 346 347 #define ICE_FDIR_COUNTER_DEFAULT_POOL_SIZE 1 348 #define ICE_FDIR_COUNTER_MAX_POOL_SIZE 32 349 #define ICE_FDIR_COUNTERS_PER_BLOCK 256 350 #define ICE_FDIR_COUNTER_INDEX(base_idx) \ 351 ((base_idx) * ICE_FDIR_COUNTERS_PER_BLOCK) 352 struct ice_fdir_counter_pool; 353 354 struct ice_fdir_counter { 355 TAILQ_ENTRY(ice_fdir_counter) next; 356 struct ice_fdir_counter_pool *pool; 357 uint8_t shared; 358 uint32_t ref_cnt; 359 uint32_t id; 360 uint64_t hits; 361 uint64_t bytes; 362 uint32_t hw_index; 363 }; 364 365 TAILQ_HEAD(ice_fdir_counter_list, ice_fdir_counter); 366 367 struct ice_fdir_counter_pool { 368 TAILQ_ENTRY(ice_fdir_counter_pool) next; 369 struct ice_fdir_counter_list counter_list; 370 struct ice_fdir_counter counters[0]; 371 }; 372 373 TAILQ_HEAD(ice_fdir_counter_pool_list, ice_fdir_counter_pool); 374 375 struct ice_fdir_counter_pool_container { 376 struct ice_fdir_counter_pool_list pool_list; 377 struct ice_fdir_counter_pool *pools[ICE_FDIR_COUNTER_MAX_POOL_SIZE]; 378 uint8_t index_free; 379 }; 380 381 /** 382 * A structure used to define fields of a FDIR related info. 383 */ 384 struct ice_fdir_info { 385 struct ice_vsi *fdir_vsi; /* pointer to fdir VSI structure */ 386 struct ice_tx_queue *txq; 387 struct ice_rx_queue *rxq; 388 void *prg_pkt; /* memory for fdir program packet */ 389 uint64_t dma_addr; /* physic address of packet memory*/ 390 const struct rte_memzone *mz; 391 struct ice_fdir_filter_conf conf; 392 393 struct ice_fdir_filter_conf **hash_map; 394 struct rte_hash *hash_table; 395 396 struct ice_fdir_counter_pool_container counter; 397 }; 398 399 #define ICE_HASH_GTPU_CTX_EH_IP 0 400 #define ICE_HASH_GTPU_CTX_EH_IP_UDP 1 401 #define ICE_HASH_GTPU_CTX_EH_IP_TCP 2 402 #define ICE_HASH_GTPU_CTX_UP_IP 3 403 #define ICE_HASH_GTPU_CTX_UP_IP_UDP 4 404 #define ICE_HASH_GTPU_CTX_UP_IP_TCP 5 405 #define ICE_HASH_GTPU_CTX_DW_IP 6 406 #define ICE_HASH_GTPU_CTX_DW_IP_UDP 7 407 #define ICE_HASH_GTPU_CTX_DW_IP_TCP 8 408 #define ICE_HASH_GTPU_CTX_MAX 9 409 410 struct ice_hash_gtpu_ctx { 411 struct ice_rss_hash_cfg ctx[ICE_HASH_GTPU_CTX_MAX]; 412 }; 413 414 struct ice_hash_ctx { 415 struct ice_hash_gtpu_ctx gtpu4; 416 struct ice_hash_gtpu_ctx gtpu6; 417 }; 418 419 struct ice_acl_conf { 420 struct ice_fdir_fltr input; 421 uint64_t input_set; 422 }; 423 424 /** 425 * A structure used to define fields of ACL related info. 426 */ 427 struct ice_acl_info { 428 struct ice_acl_conf conf; 429 struct rte_bitmap *slots; 430 uint64_t hw_entry_id[MAX_ACL_NORMAL_ENTRIES]; 431 }; 432 433 struct ice_pf { 434 struct ice_adapter *adapter; /* The adapter this PF associate to */ 435 struct ice_vsi *main_vsi; /* pointer to main VSI structure */ 436 /* Used for next free software vsi idx. 437 * To save the effort, we don't recycle the index. 438 * Suppose the indexes are more than enough. 439 */ 440 uint16_t next_vsi_idx; 441 uint16_t vsis_allocated; 442 uint16_t vsis_unallocated; 443 struct ice_res_pool_info qp_pool; /*Queue pair pool */ 444 struct ice_res_pool_info msix_pool; /* MSIX interrupt pool */ 445 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 446 struct rte_ether_addr dev_addr; /* PF device mac address */ 447 uint64_t flags; /* PF feature flags */ 448 uint16_t hash_lut_size; /* The size of hash lookup table */ 449 uint16_t lan_nb_qp_max; 450 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ 451 uint16_t base_queue; /* The base queue pairs index in the device */ 452 uint8_t *proto_xtr; /* Protocol extraction type for all queues */ 453 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ 454 uint16_t fdir_qp_offset; 455 struct ice_fdir_info fdir; /* flow director info */ 456 struct ice_acl_info acl; /* ACL info */ 457 struct ice_hash_ctx hash_ctx; 458 uint16_t hw_prof_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX]; 459 uint16_t fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX]; 460 struct ice_hw_port_stats stats_offset; 461 struct ice_hw_port_stats stats; 462 /* internal packet statistics, it should be excluded from the total */ 463 struct ice_eth_stats internal_stats_offset; 464 struct ice_eth_stats internal_stats; 465 bool offset_loaded; 466 bool adapter_stopped; 467 struct ice_flow_list flow_list; 468 rte_spinlock_t flow_ops_lock; 469 struct ice_parser_list rss_parser_list; 470 struct ice_parser_list perm_parser_list; 471 struct ice_parser_list dist_parser_list; 472 bool init_link_up; 473 uint64_t old_rx_bytes; 474 uint64_t old_tx_bytes; 475 uint64_t supported_rxdid; /* bitmap for supported RXDID */ 476 uint64_t rss_hf; 477 }; 478 479 #define ICE_MAX_QUEUE_NUM 2048 480 #define ICE_MAX_PIN_NUM 4 481 482 /** 483 * Cache devargs parse result. 484 */ 485 struct ice_devargs { 486 int rx_low_latency; 487 int safe_mode_support; 488 uint8_t proto_xtr_dflt; 489 int pipe_mode_support; 490 uint8_t proto_xtr[ICE_MAX_QUEUE_NUM]; 491 uint8_t pin_idx; 492 uint8_t pps_out_ena; 493 }; 494 495 /** 496 * Structure to store fdir fv entry. 497 */ 498 struct ice_fdir_prof_info { 499 struct ice_parser_profile prof; 500 u64 fdir_actived_cnt; 501 }; 502 503 /** 504 * Structure to store rss fv entry. 505 */ 506 struct ice_rss_prof_info { 507 struct ice_parser_profile prof; 508 bool symm; 509 }; 510 511 /** 512 * Structure to store private data for each PF/VF instance. 513 */ 514 struct ice_adapter { 515 /* Common for both PF and VF */ 516 struct ice_hw hw; 517 struct ice_pf pf; 518 bool rx_bulk_alloc_allowed; 519 bool rx_vec_allowed; 520 bool tx_vec_allowed; 521 bool tx_simple_allowed; 522 /* ptype mapping table */ 523 uint32_t ptype_tbl[ICE_MAX_PKT_TYPE] __rte_cache_min_aligned; 524 bool is_safe_mode; 525 struct ice_devargs devargs; 526 enum ice_pkg_type active_pkg_type; /* loaded ddp package type */ 527 uint16_t fdir_ref_cnt; 528 /* For PTP */ 529 struct rte_timecounter systime_tc; 530 struct rte_timecounter rx_tstamp_tc; 531 struct rte_timecounter tx_tstamp_tc; 532 bool ptp_ena; 533 uint64_t time_hw; 534 struct ice_fdir_prof_info fdir_prof_info[ICE_MAX_PTGS]; 535 struct ice_rss_prof_info rss_prof_info[ICE_MAX_PTGS]; 536 #ifdef RTE_ARCH_X86 537 bool rx_use_avx2; 538 bool rx_use_avx512; 539 bool tx_use_avx2; 540 bool tx_use_avx512; 541 #endif 542 }; 543 544 struct ice_vsi_vlan_pvid_info { 545 uint16_t on; /* Enable or disable pvid */ 546 union { 547 uint16_t pvid; /* Valid in case 'on' is set to set pvid */ 548 struct { 549 /* Valid in case 'on' is cleared. 'tagged' will reject 550 * tagged packets, while 'untagged' will reject 551 * untagged packets. 552 */ 553 uint8_t tagged; 554 uint8_t untagged; 555 } reject; 556 } config; 557 }; 558 559 #define ICE_DEV_TO_PCI(eth_dev) \ 560 RTE_DEV_TO_PCI((eth_dev)->device) 561 562 /* ICE_DEV_PRIVATE_TO */ 563 #define ICE_DEV_PRIVATE_TO_PF(adapter) \ 564 (&((struct ice_adapter *)adapter)->pf) 565 #define ICE_DEV_PRIVATE_TO_HW(adapter) \ 566 (&((struct ice_adapter *)adapter)->hw) 567 #define ICE_DEV_PRIVATE_TO_ADAPTER(adapter) \ 568 ((struct ice_adapter *)adapter) 569 570 /* ICE_VSI_TO */ 571 #define ICE_VSI_TO_HW(vsi) \ 572 (&(((struct ice_vsi *)vsi)->adapter->hw)) 573 #define ICE_VSI_TO_PF(vsi) \ 574 (&(((struct ice_vsi *)vsi)->adapter->pf)) 575 576 /* ICE_PF_TO */ 577 #define ICE_PF_TO_HW(pf) \ 578 (&(((struct ice_pf *)pf)->adapter->hw)) 579 #define ICE_PF_TO_ADAPTER(pf) \ 580 ((struct ice_adapter *)(pf)->adapter) 581 #define ICE_PF_TO_ETH_DEV(pf) \ 582 (((struct ice_pf *)pf)->adapter->eth_dev) 583 584 int 585 ice_load_pkg(struct ice_adapter *adapter, bool use_dsn, uint64_t dsn); 586 struct ice_vsi * 587 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type); 588 int 589 ice_release_vsi(struct ice_vsi *vsi); 590 void ice_vsi_enable_queues_intr(struct ice_vsi *vsi); 591 void ice_vsi_disable_queues_intr(struct ice_vsi *vsi); 592 void ice_vsi_queues_bind_intr(struct ice_vsi *vsi); 593 int ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, 594 struct ice_rss_hash_cfg *cfg); 595 int ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, 596 struct ice_rss_hash_cfg *cfg); 597 598 static inline int 599 ice_align_floor(int n) 600 { 601 if (n == 0) 602 return 0; 603 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); 604 } 605 606 #define ICE_PHY_TYPE_SUPPORT_50G(phy_type) \ 607 (((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CR2) || \ 608 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR2) || \ 609 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR2) || \ 610 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR2) || \ 611 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC) || \ 612 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2) || \ 613 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC) || \ 614 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2) || \ 615 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CP) || \ 616 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR) || \ 617 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_FR) || \ 618 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR) || \ 619 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4) || \ 620 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC) || \ 621 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1)) 622 623 #define ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type) \ 624 (((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR4) || \ 625 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR4) || \ 626 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_LR4) || \ 627 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR4) || \ 628 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC) || \ 629 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4) || \ 630 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC) || \ 631 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4) || \ 632 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4) || \ 633 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4) || \ 634 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CP2) || \ 635 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR2) || \ 636 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_DR)) 637 638 #define ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type) \ 639 (((phy_type) & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) || \ 640 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC) || \ 641 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2) || \ 642 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC) || \ 643 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2)) 644 645 #endif /* _ICE_ETHDEV_H_ */ 646