1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 5 #ifndef _ICE_ETHDEV_H_ 6 #define _ICE_ETHDEV_H_ 7 8 #include <rte_kvargs.h> 9 10 #include <rte_ethdev_driver.h> 11 12 #include "base/ice_common.h" 13 #include "base/ice_adminq_cmd.h" 14 15 #define ICE_VLAN_TAG_SIZE 4 16 17 #define ICE_ADMINQ_LEN 32 18 #define ICE_SBIOQ_LEN 32 19 #define ICE_MAILBOXQ_LEN 32 20 #define ICE_ADMINQ_BUF_SZ 4096 21 #define ICE_SBIOQ_BUF_SZ 4096 22 #define ICE_MAILBOXQ_BUF_SZ 4096 23 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ 24 #define ICE_MAX_Q_PER_TC 64 25 #define ICE_NUM_DESC_DEFAULT 512 26 #define ICE_BUF_SIZE_MIN 1024 27 #define ICE_FRAME_SIZE_MAX 9728 28 #define ICE_QUEUE_BASE_ADDR_UNIT 128 29 /* number of VSIs and queue default setting */ 30 #define ICE_MAX_QP_NUM_PER_VF 16 31 #define ICE_DEFAULT_QP_NUM_FDIR 1 32 #define ICE_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) 33 #define ICE_VFTA_SIZE (4096 / ICE_UINT32_BIT_SIZE) 34 /* Maximun number of MAC addresses */ 35 #define ICE_NUM_MACADDR_MAX 64 36 /* Maximum number of VFs */ 37 #define ICE_MAX_VF 128 38 #define ICE_MAX_INTR_QUEUE_NUM 256 39 40 #define ICE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 41 #define ICE_RX_VEC_ID RTE_INTR_VEC_RXTX_OFFSET 42 43 #define ICE_MAX_PKT_TYPE 1024 44 45 /** 46 * vlan_id is a 12 bit number. 47 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 48 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 49 * The higher 7 bit val specifies VFTA array index. 50 */ 51 #define ICE_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 52 #define ICE_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 53 54 /* Default TC traffic in case DCB is not enabled */ 55 #define ICE_DEFAULT_TCMAP 0x1 56 #define ICE_FDIR_QUEUE_ID 0 57 58 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ 59 #define ICE_VMDQ_POOL_BASE 1 60 61 #define ICE_DEFAULT_RX_FREE_THRESH 32 62 #define ICE_DEFAULT_RX_PTHRESH 8 63 #define ICE_DEFAULT_RX_HTHRESH 8 64 #define ICE_DEFAULT_RX_WTHRESH 0 65 66 #define ICE_DEFAULT_TX_FREE_THRESH 32 67 #define ICE_DEFAULT_TX_PTHRESH 32 68 #define ICE_DEFAULT_TX_HTHRESH 0 69 #define ICE_DEFAULT_TX_WTHRESH 0 70 #define ICE_DEFAULT_TX_RSBIT_THRESH 32 71 72 /* Bit shift and mask */ 73 #define ICE_4_BIT_WIDTH (CHAR_BIT / 2) 74 #define ICE_4_BIT_MASK RTE_LEN2MASK(ICE_4_BIT_WIDTH, uint8_t) 75 #define ICE_8_BIT_WIDTH CHAR_BIT 76 #define ICE_8_BIT_MASK UINT8_MAX 77 #define ICE_16_BIT_WIDTH (CHAR_BIT * 2) 78 #define ICE_16_BIT_MASK UINT16_MAX 79 #define ICE_32_BIT_WIDTH (CHAR_BIT * 4) 80 #define ICE_32_BIT_MASK UINT32_MAX 81 #define ICE_40_BIT_WIDTH (CHAR_BIT * 5) 82 #define ICE_40_BIT_MASK RTE_LEN2MASK(ICE_40_BIT_WIDTH, uint64_t) 83 #define ICE_48_BIT_WIDTH (CHAR_BIT * 6) 84 #define ICE_48_BIT_MASK RTE_LEN2MASK(ICE_48_BIT_WIDTH, uint64_t) 85 86 #define ICE_FLAG_RSS BIT_ULL(0) 87 #define ICE_FLAG_DCB BIT_ULL(1) 88 #define ICE_FLAG_VMDQ BIT_ULL(2) 89 #define ICE_FLAG_SRIOV BIT_ULL(3) 90 #define ICE_FLAG_HEADER_SPLIT_DISABLED BIT_ULL(4) 91 #define ICE_FLAG_HEADER_SPLIT_ENABLED BIT_ULL(5) 92 #define ICE_FLAG_FDIR BIT_ULL(6) 93 #define ICE_FLAG_VXLAN BIT_ULL(7) 94 #define ICE_FLAG_RSS_AQ_CAPABLE BIT_ULL(8) 95 #define ICE_FLAG_VF_MAC_BY_PF BIT_ULL(9) 96 #define ICE_FLAG_ALL (ICE_FLAG_RSS | \ 97 ICE_FLAG_DCB | \ 98 ICE_FLAG_VMDQ | \ 99 ICE_FLAG_SRIOV | \ 100 ICE_FLAG_HEADER_SPLIT_DISABLED | \ 101 ICE_FLAG_HEADER_SPLIT_ENABLED | \ 102 ICE_FLAG_FDIR | \ 103 ICE_FLAG_VXLAN | \ 104 ICE_FLAG_RSS_AQ_CAPABLE | \ 105 ICE_FLAG_VF_MAC_BY_PF) 106 107 #define ICE_RSS_OFFLOAD_ALL ( \ 108 ETH_RSS_FRAG_IPV4 | \ 109 ETH_RSS_NONFRAG_IPV4_TCP | \ 110 ETH_RSS_NONFRAG_IPV4_UDP | \ 111 ETH_RSS_NONFRAG_IPV4_SCTP | \ 112 ETH_RSS_NONFRAG_IPV4_OTHER | \ 113 ETH_RSS_FRAG_IPV6 | \ 114 ETH_RSS_NONFRAG_IPV6_TCP | \ 115 ETH_RSS_NONFRAG_IPV6_UDP | \ 116 ETH_RSS_NONFRAG_IPV6_SCTP | \ 117 ETH_RSS_NONFRAG_IPV6_OTHER | \ 118 ETH_RSS_L2_PAYLOAD) 119 120 struct ice_adapter; 121 122 /** 123 * MAC filter structure 124 */ 125 struct ice_mac_filter_info { 126 struct ether_addr mac_addr; 127 }; 128 129 TAILQ_HEAD(ice_mac_filter_list, ice_mac_filter); 130 131 /* MAC filter list structure */ 132 struct ice_mac_filter { 133 TAILQ_ENTRY(ice_mac_filter) next; 134 struct ice_mac_filter_info mac_info; 135 }; 136 137 /** 138 * VLAN filter structure 139 */ 140 struct ice_vlan_filter_info { 141 uint16_t vlan_id; 142 }; 143 144 TAILQ_HEAD(ice_vlan_filter_list, ice_vlan_filter); 145 146 /* VLAN filter list structure */ 147 struct ice_vlan_filter { 148 TAILQ_ENTRY(ice_vlan_filter) next; 149 struct ice_vlan_filter_info vlan_info; 150 }; 151 152 struct pool_entry { 153 LIST_ENTRY(pool_entry) next; 154 uint16_t base; 155 uint16_t len; 156 }; 157 158 LIST_HEAD(res_list, pool_entry); 159 160 struct ice_res_pool_info { 161 uint32_t base; /* Resource start index */ 162 uint32_t num_alloc; /* Allocated resource number */ 163 uint32_t num_free; /* Total available resource number */ 164 struct res_list alloc_list; /* Allocated resource list */ 165 struct res_list free_list; /* Available resource list */ 166 }; 167 168 TAILQ_HEAD(ice_vsi_list_head, ice_vsi_list); 169 170 struct ice_vsi; 171 172 /* VSI list structure */ 173 struct ice_vsi_list { 174 TAILQ_ENTRY(ice_vsi_list) list; 175 struct ice_vsi *vsi; 176 }; 177 178 struct ice_rx_queue; 179 struct ice_tx_queue; 180 181 /** 182 * Structure that defines a VSI, associated with a adapter. 183 */ 184 struct ice_vsi { 185 struct ice_adapter *adapter; /* Backreference to associated adapter */ 186 struct ice_aqc_vsi_props info; /* VSI properties */ 187 /** 188 * When drivers loaded, only a default main VSI exists. In case new VSI 189 * needs to add, HW needs to know the layout that VSIs are organized. 190 * Besides that, VSI isan element and can't switch packets, which needs 191 * to add new component VEB to perform switching. So, a new VSI needs 192 * to specify the the uplink VSI (Parent VSI) before created. The 193 * uplink VSI will check whether it had a VEB to switch packets. If no, 194 * it will try to create one. Then, uplink VSI will move the new VSI 195 * into its' sib_vsi_list to manage all the downlink VSI. 196 * sib_vsi_list: the VSI list that shared the same uplink VSI. 197 * parent_vsi : the uplink VSI. It's NULL for main VSI. 198 * veb : the VEB associates with the VSI. 199 */ 200 struct ice_vsi_list sib_vsi_list; /* sibling vsi list */ 201 struct ice_vsi *parent_vsi; 202 enum ice_vsi_type type; /* VSI types */ 203 uint16_t vlan_num; /* Total VLAN number */ 204 uint16_t mac_num; /* Total mac number */ 205 struct ice_mac_filter_list mac_list; /* macvlan filter list */ 206 struct ice_vlan_filter_list vlan_list; /* vlan filter list */ 207 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ 208 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ 209 uint16_t max_macaddrs; /* Maximum number of MAC addresses */ 210 uint16_t base_queue; /* The first queue index of this VSI */ 211 uint16_t vsi_id; /* Hardware Id */ 212 uint16_t idx; /* vsi_handle: SW index in hw->vsi_ctx */ 213 /* VF number to which the VSI connects, valid when VSI is VF type */ 214 uint8_t vf_num; 215 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ 216 uint16_t nb_msix; /* The max number of msix vector */ 217 uint8_t enabled_tc; /* The traffic class enabled */ 218 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ 219 uint8_t vlan_filter_on; /* The VLAN filter enabled */ 220 /* information about rss configuration */ 221 u32 rss_key_size; 222 u32 rss_lut_size; 223 uint8_t *rss_lut; 224 uint8_t *rss_key; 225 struct ice_eth_stats eth_stats_offset; 226 struct ice_eth_stats eth_stats; 227 bool offset_loaded; 228 }; 229 230 struct ice_pf { 231 struct ice_adapter *adapter; /* The adapter this PF associate to */ 232 struct ice_vsi *main_vsi; /* pointer to main VSI structure */ 233 /* Used for next free software vsi idx. 234 * To save the effort, we don't recycle the index. 235 * Suppose the indexes are more than enough. 236 */ 237 uint16_t next_vsi_idx; 238 uint16_t vsis_allocated; 239 uint16_t vsis_unallocated; 240 struct ice_res_pool_info qp_pool; /*Queue pair pool */ 241 struct ice_res_pool_info msix_pool; /* MSIX interrupt pool */ 242 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 243 struct ether_addr dev_addr; /* PF device mac address */ 244 uint64_t flags; /* PF feature flags */ 245 uint16_t hash_lut_size; /* The size of hash lookup table */ 246 uint16_t lan_nb_qp_max; 247 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ 248 struct ice_hw_port_stats stats_offset; 249 struct ice_hw_port_stats stats; 250 /* internal packet statistics, it should be excluded from the total */ 251 struct ice_eth_stats internal_stats_offset; 252 struct ice_eth_stats internal_stats; 253 bool offset_loaded; 254 bool adapter_stopped; 255 }; 256 257 /** 258 * Structure to store private data for each PF/VF instance. 259 */ 260 struct ice_adapter { 261 /* Common for both PF and VF */ 262 struct ice_hw hw; 263 struct rte_eth_dev *eth_dev; 264 struct ice_pf pf; 265 bool rx_bulk_alloc_allowed; 266 bool tx_simple_allowed; 267 /* ptype mapping table */ 268 uint32_t ptype_tbl[ICE_MAX_PKT_TYPE] __rte_cache_min_aligned; 269 bool is_safe_mode; 270 }; 271 272 struct ice_vsi_vlan_pvid_info { 273 uint16_t on; /* Enable or disable pvid */ 274 union { 275 uint16_t pvid; /* Valid in case 'on' is set to set pvid */ 276 struct { 277 /* Valid in case 'on' is cleared. 'tagged' will reject 278 * tagged packets, while 'untagged' will reject 279 * untagged packets. 280 */ 281 uint8_t tagged; 282 uint8_t untagged; 283 } reject; 284 } config; 285 }; 286 287 #define ICE_DEV_TO_PCI(eth_dev) \ 288 RTE_DEV_TO_PCI((eth_dev)->device) 289 290 /* ICE_DEV_PRIVATE_TO */ 291 #define ICE_DEV_PRIVATE_TO_PF(adapter) \ 292 (&((struct ice_adapter *)adapter)->pf) 293 #define ICE_DEV_PRIVATE_TO_HW(adapter) \ 294 (&((struct ice_adapter *)adapter)->hw) 295 #define ICE_DEV_PRIVATE_TO_ADAPTER(adapter) \ 296 ((struct ice_adapter *)adapter) 297 298 /* ICE_VSI_TO */ 299 #define ICE_VSI_TO_HW(vsi) \ 300 (&(((struct ice_vsi *)vsi)->adapter->hw)) 301 #define ICE_VSI_TO_PF(vsi) \ 302 (&(((struct ice_vsi *)vsi)->adapter->pf)) 303 #define ICE_VSI_TO_ETH_DEV(vsi) \ 304 (((struct ice_vsi *)vsi)->adapter->eth_dev) 305 306 /* ICE_PF_TO */ 307 #define ICE_PF_TO_HW(pf) \ 308 (&(((struct ice_pf *)pf)->adapter->hw)) 309 #define ICE_PF_TO_ADAPTER(pf) \ 310 ((struct ice_adapter *)(pf)->adapter) 311 #define ICE_PF_TO_ETH_DEV(pf) \ 312 (((struct ice_pf *)pf)->adapter->eth_dev) 313 314 static inline int 315 ice_align_floor(int n) 316 { 317 if (n == 0) 318 return 0; 319 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); 320 } 321 322 #define ICE_PHY_TYPE_SUPPORT_50G(phy_type) \ 323 (((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CR2) || \ 324 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR2) || \ 325 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR2) || \ 326 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR2) || \ 327 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC) || \ 328 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2) || \ 329 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC) || \ 330 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2) || \ 331 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CP) || \ 332 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR) || \ 333 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_FR) || \ 334 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR) || \ 335 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4) || \ 336 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC) || \ 337 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1)) 338 339 #define ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type) \ 340 (((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR4) || \ 341 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR4) || \ 342 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_LR4) || \ 343 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR4) || \ 344 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC) || \ 345 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4) || \ 346 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC) || \ 347 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4) || \ 348 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4) || \ 349 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4) || \ 350 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CP2) || \ 351 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR2) || \ 352 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_DR)) 353 354 #define ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type) \ 355 (((phy_type) & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) || \ 356 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC) || \ 357 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2) || \ 358 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC) || \ 359 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2)) 360 361 #endif /* _ICE_ETHDEV_H_ */ 362