1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 5 #ifndef _ICE_ETHDEV_H_ 6 #define _ICE_ETHDEV_H_ 7 8 #include <rte_kvargs.h> 9 10 #include <rte_ethdev_driver.h> 11 12 #include "base/ice_common.h" 13 #include "base/ice_adminq_cmd.h" 14 15 #define ICE_VLAN_TAG_SIZE 4 16 17 #define ICE_ADMINQ_LEN 32 18 #define ICE_SBIOQ_LEN 32 19 #define ICE_MAILBOXQ_LEN 32 20 #define ICE_ADMINQ_BUF_SZ 4096 21 #define ICE_SBIOQ_BUF_SZ 4096 22 #define ICE_MAILBOXQ_BUF_SZ 4096 23 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ 24 #define ICE_MAX_Q_PER_TC 64 25 #define ICE_NUM_DESC_DEFAULT 512 26 #define ICE_BUF_SIZE_MIN 1024 27 #define ICE_FRAME_SIZE_MAX 9728 28 #define ICE_QUEUE_BASE_ADDR_UNIT 128 29 /* number of VSIs and queue default setting */ 30 #define ICE_MAX_QP_NUM_PER_VF 16 31 #define ICE_DEFAULT_QP_NUM_FDIR 1 32 #define ICE_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) 33 #define ICE_VFTA_SIZE (4096 / ICE_UINT32_BIT_SIZE) 34 /* Maximun number of MAC addresses */ 35 #define ICE_NUM_MACADDR_MAX 64 36 /* Maximum number of VFs */ 37 #define ICE_MAX_VF 128 38 #define ICE_MAX_INTR_QUEUE_NUM 256 39 40 #define ICE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 41 #define ICE_RX_VEC_ID RTE_INTR_VEC_RXTX_OFFSET 42 43 #define ICE_MAX_PKT_TYPE 1024 44 45 /* DDP package search path */ 46 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg" 47 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg" 48 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/" 49 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/" 50 #define ICE_MAX_PKG_FILENAME_SIZE 256 51 52 /** 53 * vlan_id is a 12 bit number. 54 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 55 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 56 * The higher 7 bit val specifies VFTA array index. 57 */ 58 #define ICE_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 59 #define ICE_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 60 61 /* Default TC traffic in case DCB is not enabled */ 62 #define ICE_DEFAULT_TCMAP 0x1 63 #define ICE_FDIR_QUEUE_ID 0 64 65 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ 66 #define ICE_VMDQ_POOL_BASE 1 67 68 #define ICE_DEFAULT_RX_FREE_THRESH 32 69 #define ICE_DEFAULT_RX_PTHRESH 8 70 #define ICE_DEFAULT_RX_HTHRESH 8 71 #define ICE_DEFAULT_RX_WTHRESH 0 72 73 #define ICE_DEFAULT_TX_FREE_THRESH 32 74 #define ICE_DEFAULT_TX_PTHRESH 32 75 #define ICE_DEFAULT_TX_HTHRESH 0 76 #define ICE_DEFAULT_TX_WTHRESH 0 77 #define ICE_DEFAULT_TX_RSBIT_THRESH 32 78 79 /* Bit shift and mask */ 80 #define ICE_4_BIT_WIDTH (CHAR_BIT / 2) 81 #define ICE_4_BIT_MASK RTE_LEN2MASK(ICE_4_BIT_WIDTH, uint8_t) 82 #define ICE_8_BIT_WIDTH CHAR_BIT 83 #define ICE_8_BIT_MASK UINT8_MAX 84 #define ICE_16_BIT_WIDTH (CHAR_BIT * 2) 85 #define ICE_16_BIT_MASK UINT16_MAX 86 #define ICE_32_BIT_WIDTH (CHAR_BIT * 4) 87 #define ICE_32_BIT_MASK UINT32_MAX 88 #define ICE_40_BIT_WIDTH (CHAR_BIT * 5) 89 #define ICE_40_BIT_MASK RTE_LEN2MASK(ICE_40_BIT_WIDTH, uint64_t) 90 #define ICE_48_BIT_WIDTH (CHAR_BIT * 6) 91 #define ICE_48_BIT_MASK RTE_LEN2MASK(ICE_48_BIT_WIDTH, uint64_t) 92 93 #define ICE_FLAG_RSS BIT_ULL(0) 94 #define ICE_FLAG_DCB BIT_ULL(1) 95 #define ICE_FLAG_VMDQ BIT_ULL(2) 96 #define ICE_FLAG_SRIOV BIT_ULL(3) 97 #define ICE_FLAG_HEADER_SPLIT_DISABLED BIT_ULL(4) 98 #define ICE_FLAG_HEADER_SPLIT_ENABLED BIT_ULL(5) 99 #define ICE_FLAG_FDIR BIT_ULL(6) 100 #define ICE_FLAG_VXLAN BIT_ULL(7) 101 #define ICE_FLAG_RSS_AQ_CAPABLE BIT_ULL(8) 102 #define ICE_FLAG_VF_MAC_BY_PF BIT_ULL(9) 103 #define ICE_FLAG_ALL (ICE_FLAG_RSS | \ 104 ICE_FLAG_DCB | \ 105 ICE_FLAG_VMDQ | \ 106 ICE_FLAG_SRIOV | \ 107 ICE_FLAG_HEADER_SPLIT_DISABLED | \ 108 ICE_FLAG_HEADER_SPLIT_ENABLED | \ 109 ICE_FLAG_FDIR | \ 110 ICE_FLAG_VXLAN | \ 111 ICE_FLAG_RSS_AQ_CAPABLE | \ 112 ICE_FLAG_VF_MAC_BY_PF) 113 114 #define ICE_RSS_OFFLOAD_ALL ( \ 115 ETH_RSS_IPV4 | \ 116 ETH_RSS_FRAG_IPV4 | \ 117 ETH_RSS_NONFRAG_IPV4_TCP | \ 118 ETH_RSS_NONFRAG_IPV4_UDP | \ 119 ETH_RSS_NONFRAG_IPV4_SCTP | \ 120 ETH_RSS_NONFRAG_IPV4_OTHER | \ 121 ETH_RSS_IPV6 | \ 122 ETH_RSS_FRAG_IPV6 | \ 123 ETH_RSS_NONFRAG_IPV6_TCP | \ 124 ETH_RSS_NONFRAG_IPV6_UDP | \ 125 ETH_RSS_NONFRAG_IPV6_SCTP | \ 126 ETH_RSS_NONFRAG_IPV6_OTHER | \ 127 ETH_RSS_L2_PAYLOAD) 128 129 /** 130 * The overhead from MTU to max frame size. 131 * Considering QinQ packet, the VLAN tag needs to be counted twice. 132 */ 133 #define ICE_ETH_OVERHEAD \ 134 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE * 2) 135 136 /* DDP package type */ 137 enum ice_pkg_type { 138 ICE_PKG_TYPE_UNKNOWN, 139 ICE_PKG_TYPE_OS_DEFAULT, 140 ICE_PKG_TYPE_COMMS, 141 }; 142 143 struct ice_adapter; 144 145 /** 146 * MAC filter structure 147 */ 148 struct ice_mac_filter_info { 149 struct rte_ether_addr mac_addr; 150 }; 151 152 TAILQ_HEAD(ice_mac_filter_list, ice_mac_filter); 153 154 /* MAC filter list structure */ 155 struct ice_mac_filter { 156 TAILQ_ENTRY(ice_mac_filter) next; 157 struct ice_mac_filter_info mac_info; 158 }; 159 160 /** 161 * VLAN filter structure 162 */ 163 struct ice_vlan_filter_info { 164 uint16_t vlan_id; 165 }; 166 167 TAILQ_HEAD(ice_vlan_filter_list, ice_vlan_filter); 168 169 /* VLAN filter list structure */ 170 struct ice_vlan_filter { 171 TAILQ_ENTRY(ice_vlan_filter) next; 172 struct ice_vlan_filter_info vlan_info; 173 }; 174 175 struct pool_entry { 176 LIST_ENTRY(pool_entry) next; 177 uint16_t base; 178 uint16_t len; 179 }; 180 181 LIST_HEAD(res_list, pool_entry); 182 183 struct ice_res_pool_info { 184 uint32_t base; /* Resource start index */ 185 uint32_t num_alloc; /* Allocated resource number */ 186 uint32_t num_free; /* Total available resource number */ 187 struct res_list alloc_list; /* Allocated resource list */ 188 struct res_list free_list; /* Available resource list */ 189 }; 190 191 TAILQ_HEAD(ice_vsi_list_head, ice_vsi_list); 192 193 struct ice_vsi; 194 195 /* VSI list structure */ 196 struct ice_vsi_list { 197 TAILQ_ENTRY(ice_vsi_list) list; 198 struct ice_vsi *vsi; 199 }; 200 201 struct ice_rx_queue; 202 struct ice_tx_queue; 203 204 /** 205 * Structure that defines a VSI, associated with a adapter. 206 */ 207 struct ice_vsi { 208 struct ice_adapter *adapter; /* Backreference to associated adapter */ 209 struct ice_aqc_vsi_props info; /* VSI properties */ 210 /** 211 * When drivers loaded, only a default main VSI exists. In case new VSI 212 * needs to add, HW needs to know the layout that VSIs are organized. 213 * Besides that, VSI isan element and can't switch packets, which needs 214 * to add new component VEB to perform switching. So, a new VSI needs 215 * to specify the the uplink VSI (Parent VSI) before created. The 216 * uplink VSI will check whether it had a VEB to switch packets. If no, 217 * it will try to create one. Then, uplink VSI will move the new VSI 218 * into its' sib_vsi_list to manage all the downlink VSI. 219 * sib_vsi_list: the VSI list that shared the same uplink VSI. 220 * parent_vsi : the uplink VSI. It's NULL for main VSI. 221 * veb : the VEB associates with the VSI. 222 */ 223 struct ice_vsi_list sib_vsi_list; /* sibling vsi list */ 224 struct ice_vsi *parent_vsi; 225 enum ice_vsi_type type; /* VSI types */ 226 uint16_t vlan_num; /* Total VLAN number */ 227 uint16_t mac_num; /* Total mac number */ 228 struct ice_mac_filter_list mac_list; /* macvlan filter list */ 229 struct ice_vlan_filter_list vlan_list; /* vlan filter list */ 230 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ 231 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ 232 uint16_t max_macaddrs; /* Maximum number of MAC addresses */ 233 uint16_t base_queue; /* The first queue index of this VSI */ 234 uint16_t vsi_id; /* Hardware Id */ 235 uint16_t idx; /* vsi_handle: SW index in hw->vsi_ctx */ 236 /* VF number to which the VSI connects, valid when VSI is VF type */ 237 uint8_t vf_num; 238 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ 239 uint16_t nb_msix; /* The max number of msix vector */ 240 uint8_t enabled_tc; /* The traffic class enabled */ 241 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ 242 uint8_t vlan_filter_on; /* The VLAN filter enabled */ 243 /* information about rss configuration */ 244 u32 rss_key_size; 245 u32 rss_lut_size; 246 uint8_t *rss_lut; 247 uint8_t *rss_key; 248 struct ice_eth_stats eth_stats_offset; 249 struct ice_eth_stats eth_stats; 250 bool offset_loaded; 251 }; 252 253 enum proto_xtr_type { 254 PROTO_XTR_NONE, 255 PROTO_XTR_VLAN, 256 PROTO_XTR_IPV4, 257 PROTO_XTR_IPV6, 258 PROTO_XTR_IPV6_FLOW, 259 PROTO_XTR_TCP, 260 }; 261 262 enum ice_fdir_tunnel_type { 263 ICE_FDIR_TUNNEL_TYPE_NONE = 0, 264 ICE_FDIR_TUNNEL_TYPE_VXLAN, 265 ICE_FDIR_TUNNEL_TYPE_GTPU, 266 ICE_FDIR_TUNNEL_TYPE_GTPU_EH, 267 }; 268 269 struct rte_flow; 270 TAILQ_HEAD(ice_flow_list, rte_flow); 271 272 struct ice_flow_parser_node; 273 TAILQ_HEAD(ice_parser_list, ice_flow_parser_node); 274 275 struct ice_fdir_filter_conf { 276 struct ice_fdir_fltr input; 277 enum ice_fdir_tunnel_type tunnel_type; 278 279 struct ice_fdir_counter *counter; /* flow specific counter context */ 280 struct rte_flow_action_count act_count; 281 282 uint64_t input_set; 283 }; 284 285 #define ICE_MAX_FDIR_FILTER_NUM (1024 * 16) 286 287 struct ice_fdir_fltr_pattern { 288 enum ice_fltr_ptype flow_type; 289 290 union { 291 struct ice_fdir_v4 v4; 292 struct ice_fdir_v6 v6; 293 } ip, mask; 294 295 struct ice_fdir_udp_gtp gtpu_data; 296 struct ice_fdir_udp_gtp gtpu_mask; 297 298 struct ice_fdir_extra ext_data; 299 struct ice_fdir_extra ext_mask; 300 301 enum ice_fdir_tunnel_type tunnel_type; 302 }; 303 304 #define ICE_FDIR_COUNTER_DEFAULT_POOL_SIZE 1 305 #define ICE_FDIR_COUNTER_MAX_POOL_SIZE 32 306 #define ICE_FDIR_COUNTERS_PER_BLOCK 256 307 #define ICE_FDIR_COUNTER_INDEX(base_idx) \ 308 ((base_idx) * ICE_FDIR_COUNTERS_PER_BLOCK) 309 struct ice_fdir_counter_pool; 310 311 struct ice_fdir_counter { 312 TAILQ_ENTRY(ice_fdir_counter) next; 313 struct ice_fdir_counter_pool *pool; 314 uint8_t shared; 315 uint32_t ref_cnt; 316 uint32_t id; 317 uint64_t hits; 318 uint64_t bytes; 319 uint32_t hw_index; 320 }; 321 322 TAILQ_HEAD(ice_fdir_counter_list, ice_fdir_counter); 323 324 struct ice_fdir_counter_pool { 325 TAILQ_ENTRY(ice_fdir_counter_pool) next; 326 struct ice_fdir_counter_list counter_list; 327 struct ice_fdir_counter counters[0]; 328 }; 329 330 TAILQ_HEAD(ice_fdir_counter_pool_list, ice_fdir_counter_pool); 331 332 struct ice_fdir_counter_pool_container { 333 struct ice_fdir_counter_pool_list pool_list; 334 struct ice_fdir_counter_pool *pools[ICE_FDIR_COUNTER_MAX_POOL_SIZE]; 335 uint8_t index_free; 336 }; 337 338 /** 339 * A structure used to define fields of a FDIR related info. 340 */ 341 struct ice_fdir_info { 342 struct ice_vsi *fdir_vsi; /* pointer to fdir VSI structure */ 343 struct ice_tx_queue *txq; 344 struct ice_rx_queue *rxq; 345 void *prg_pkt; /* memory for fdir program packet */ 346 uint64_t dma_addr; /* physic address of packet memory*/ 347 const struct rte_memzone *mz; 348 struct ice_fdir_filter_conf conf; 349 350 struct ice_fdir_filter_conf **hash_map; 351 struct rte_hash *hash_table; 352 353 struct ice_fdir_counter_pool_container counter; 354 }; 355 356 struct ice_pf { 357 struct ice_adapter *adapter; /* The adapter this PF associate to */ 358 struct ice_vsi *main_vsi; /* pointer to main VSI structure */ 359 /* Used for next free software vsi idx. 360 * To save the effort, we don't recycle the index. 361 * Suppose the indexes are more than enough. 362 */ 363 uint16_t next_vsi_idx; 364 uint16_t vsis_allocated; 365 uint16_t vsis_unallocated; 366 struct ice_res_pool_info qp_pool; /*Queue pair pool */ 367 struct ice_res_pool_info msix_pool; /* MSIX interrupt pool */ 368 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 369 struct rte_ether_addr dev_addr; /* PF device mac address */ 370 uint64_t flags; /* PF feature flags */ 371 uint16_t hash_lut_size; /* The size of hash lookup table */ 372 uint16_t lan_nb_qp_max; 373 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ 374 uint16_t base_queue; /* The base queue pairs index in the device */ 375 uint8_t *proto_xtr; /* Protocol extraction type for all queues */ 376 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ 377 uint16_t fdir_qp_offset; 378 struct ice_fdir_info fdir; /* flow director info */ 379 uint16_t hw_prof_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX]; 380 uint16_t fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX]; 381 struct ice_hw_port_stats stats_offset; 382 struct ice_hw_port_stats stats; 383 /* internal packet statistics, it should be excluded from the total */ 384 struct ice_eth_stats internal_stats_offset; 385 struct ice_eth_stats internal_stats; 386 bool offset_loaded; 387 bool adapter_stopped; 388 struct ice_flow_list flow_list; 389 rte_spinlock_t flow_ops_lock; 390 struct ice_parser_list rss_parser_list; 391 struct ice_parser_list perm_parser_list; 392 struct ice_parser_list dist_parser_list; 393 bool init_link_up; 394 }; 395 396 #define ICE_MAX_QUEUE_NUM 2048 397 398 /** 399 * Cache devargs parse result. 400 */ 401 struct ice_devargs { 402 int safe_mode_support; 403 uint8_t proto_xtr_dflt; 404 int pipe_mode_support; 405 int flow_mark_support; 406 uint8_t proto_xtr[ICE_MAX_QUEUE_NUM]; 407 }; 408 409 /** 410 * Structure to store private data for each PF/VF instance. 411 */ 412 struct ice_adapter { 413 /* Common for both PF and VF */ 414 struct ice_hw hw; 415 struct rte_eth_dev *eth_dev; 416 struct ice_pf pf; 417 bool rx_bulk_alloc_allowed; 418 bool rx_vec_allowed; 419 bool tx_vec_allowed; 420 bool tx_simple_allowed; 421 /* ptype mapping table */ 422 uint32_t ptype_tbl[ICE_MAX_PKT_TYPE] __rte_cache_min_aligned; 423 bool is_safe_mode; 424 struct ice_devargs devargs; 425 enum ice_pkg_type active_pkg_type; /* loaded ddp package type */ 426 }; 427 428 struct ice_vsi_vlan_pvid_info { 429 uint16_t on; /* Enable or disable pvid */ 430 union { 431 uint16_t pvid; /* Valid in case 'on' is set to set pvid */ 432 struct { 433 /* Valid in case 'on' is cleared. 'tagged' will reject 434 * tagged packets, while 'untagged' will reject 435 * untagged packets. 436 */ 437 uint8_t tagged; 438 uint8_t untagged; 439 } reject; 440 } config; 441 }; 442 443 #define ICE_DEV_TO_PCI(eth_dev) \ 444 RTE_DEV_TO_PCI((eth_dev)->device) 445 446 /* ICE_DEV_PRIVATE_TO */ 447 #define ICE_DEV_PRIVATE_TO_PF(adapter) \ 448 (&((struct ice_adapter *)adapter)->pf) 449 #define ICE_DEV_PRIVATE_TO_HW(adapter) \ 450 (&((struct ice_adapter *)adapter)->hw) 451 #define ICE_DEV_PRIVATE_TO_ADAPTER(adapter) \ 452 ((struct ice_adapter *)adapter) 453 454 /* ICE_VSI_TO */ 455 #define ICE_VSI_TO_HW(vsi) \ 456 (&(((struct ice_vsi *)vsi)->adapter->hw)) 457 #define ICE_VSI_TO_PF(vsi) \ 458 (&(((struct ice_vsi *)vsi)->adapter->pf)) 459 #define ICE_VSI_TO_ETH_DEV(vsi) \ 460 (((struct ice_vsi *)vsi)->adapter->eth_dev) 461 462 /* ICE_PF_TO */ 463 #define ICE_PF_TO_HW(pf) \ 464 (&(((struct ice_pf *)pf)->adapter->hw)) 465 #define ICE_PF_TO_ADAPTER(pf) \ 466 ((struct ice_adapter *)(pf)->adapter) 467 #define ICE_PF_TO_ETH_DEV(pf) \ 468 (((struct ice_pf *)pf)->adapter->eth_dev) 469 470 enum ice_pkg_type ice_load_pkg_type(struct ice_hw *hw); 471 struct ice_vsi * 472 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type); 473 int 474 ice_release_vsi(struct ice_vsi *vsi); 475 void ice_vsi_enable_queues_intr(struct ice_vsi *vsi); 476 void ice_vsi_disable_queues_intr(struct ice_vsi *vsi); 477 void ice_vsi_queues_bind_intr(struct ice_vsi *vsi); 478 479 static inline int 480 ice_align_floor(int n) 481 { 482 if (n == 0) 483 return 0; 484 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); 485 } 486 487 #define ICE_PHY_TYPE_SUPPORT_50G(phy_type) \ 488 (((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CR2) || \ 489 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR2) || \ 490 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR2) || \ 491 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR2) || \ 492 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC) || \ 493 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2) || \ 494 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC) || \ 495 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2) || \ 496 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CP) || \ 497 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR) || \ 498 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_FR) || \ 499 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR) || \ 500 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4) || \ 501 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC) || \ 502 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1)) 503 504 #define ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type) \ 505 (((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR4) || \ 506 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR4) || \ 507 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_LR4) || \ 508 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR4) || \ 509 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC) || \ 510 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4) || \ 511 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC) || \ 512 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4) || \ 513 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4) || \ 514 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4) || \ 515 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CP2) || \ 516 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR2) || \ 517 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_DR)) 518 519 #define ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type) \ 520 (((phy_type) & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) || \ 521 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC) || \ 522 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2) || \ 523 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC) || \ 524 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2)) 525 526 #endif /* _ICE_ETHDEV_H_ */ 527