1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 5 #ifndef _ICE_ETHDEV_H_ 6 #define _ICE_ETHDEV_H_ 7 8 #include <rte_kvargs.h> 9 #include <rte_time.h> 10 11 #include <ethdev_driver.h> 12 13 #include "base/ice_common.h" 14 #include "base/ice_adminq_cmd.h" 15 #include "base/ice_flow.h" 16 17 #define ICE_VLAN_TAG_SIZE 4 18 19 #define ICE_ADMINQ_LEN 32 20 #define ICE_SBIOQ_LEN 32 21 #define ICE_MAILBOXQ_LEN 32 22 #define ICE_ADMINQ_BUF_SZ 4096 23 #define ICE_SBIOQ_BUF_SZ 4096 24 #define ICE_MAILBOXQ_BUF_SZ 4096 25 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ 26 #define ICE_MAX_Q_PER_TC 64 27 #define ICE_NUM_DESC_DEFAULT 512 28 #define ICE_BUF_SIZE_MIN 1024 29 #define ICE_FRAME_SIZE_MAX 9728 30 #define ICE_QUEUE_BASE_ADDR_UNIT 128 31 /* number of VSIs and queue default setting */ 32 #define ICE_MAX_QP_NUM_PER_VF 16 33 #define ICE_DEFAULT_QP_NUM_FDIR 1 34 #define ICE_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) 35 #define ICE_VFTA_SIZE (4096 / ICE_UINT32_BIT_SIZE) 36 /* Maximun number of MAC addresses */ 37 #define ICE_NUM_MACADDR_MAX 64 38 /* Maximum number of VFs */ 39 #define ICE_MAX_VF 128 40 #define ICE_MAX_INTR_QUEUE_NUM 256 41 42 #define ICE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 43 #define ICE_RX_VEC_ID RTE_INTR_VEC_RXTX_OFFSET 44 45 #define ICE_MAX_PKT_TYPE 1024 46 47 /* DDP package search path */ 48 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg" 49 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg" 50 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/" 51 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/" 52 #define ICE_MAX_PKG_FILENAME_SIZE 256 53 54 #define MAX_ACL_NORMAL_ENTRIES 256 55 56 /** 57 * vlan_id is a 12 bit number. 58 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 59 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 60 * The higher 7 bit val specifies VFTA array index. 61 */ 62 #define ICE_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 63 #define ICE_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 64 65 /* Default TC traffic in case DCB is not enabled */ 66 #define ICE_DEFAULT_TCMAP 0x1 67 #define ICE_FDIR_QUEUE_ID 0 68 69 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ 70 #define ICE_VMDQ_POOL_BASE 1 71 72 #define ICE_DEFAULT_RX_FREE_THRESH 32 73 #define ICE_DEFAULT_RX_PTHRESH 8 74 #define ICE_DEFAULT_RX_HTHRESH 8 75 #define ICE_DEFAULT_RX_WTHRESH 0 76 77 #define ICE_DEFAULT_TX_FREE_THRESH 32 78 #define ICE_DEFAULT_TX_PTHRESH 32 79 #define ICE_DEFAULT_TX_HTHRESH 0 80 #define ICE_DEFAULT_TX_WTHRESH 0 81 #define ICE_DEFAULT_TX_RSBIT_THRESH 32 82 83 /* Bit shift and mask */ 84 #define ICE_4_BIT_WIDTH (CHAR_BIT / 2) 85 #define ICE_4_BIT_MASK RTE_LEN2MASK(ICE_4_BIT_WIDTH, uint8_t) 86 #define ICE_8_BIT_WIDTH CHAR_BIT 87 #define ICE_8_BIT_MASK UINT8_MAX 88 #define ICE_16_BIT_WIDTH (CHAR_BIT * 2) 89 #define ICE_16_BIT_MASK UINT16_MAX 90 #define ICE_32_BIT_WIDTH (CHAR_BIT * 4) 91 #define ICE_32_BIT_MASK UINT32_MAX 92 #define ICE_40_BIT_WIDTH (CHAR_BIT * 5) 93 #define ICE_40_BIT_MASK RTE_LEN2MASK(ICE_40_BIT_WIDTH, uint64_t) 94 #define ICE_48_BIT_WIDTH (CHAR_BIT * 6) 95 #define ICE_48_BIT_MASK RTE_LEN2MASK(ICE_48_BIT_WIDTH, uint64_t) 96 97 #define ICE_FLAG_RSS BIT_ULL(0) 98 #define ICE_FLAG_DCB BIT_ULL(1) 99 #define ICE_FLAG_VMDQ BIT_ULL(2) 100 #define ICE_FLAG_SRIOV BIT_ULL(3) 101 #define ICE_FLAG_HEADER_SPLIT_DISABLED BIT_ULL(4) 102 #define ICE_FLAG_HEADER_SPLIT_ENABLED BIT_ULL(5) 103 #define ICE_FLAG_FDIR BIT_ULL(6) 104 #define ICE_FLAG_VXLAN BIT_ULL(7) 105 #define ICE_FLAG_RSS_AQ_CAPABLE BIT_ULL(8) 106 #define ICE_FLAG_VF_MAC_BY_PF BIT_ULL(9) 107 #define ICE_FLAG_ALL (ICE_FLAG_RSS | \ 108 ICE_FLAG_DCB | \ 109 ICE_FLAG_VMDQ | \ 110 ICE_FLAG_SRIOV | \ 111 ICE_FLAG_HEADER_SPLIT_DISABLED | \ 112 ICE_FLAG_HEADER_SPLIT_ENABLED | \ 113 ICE_FLAG_FDIR | \ 114 ICE_FLAG_VXLAN | \ 115 ICE_FLAG_RSS_AQ_CAPABLE | \ 116 ICE_FLAG_VF_MAC_BY_PF) 117 118 #define ICE_RSS_OFFLOAD_ALL ( \ 119 ETH_RSS_IPV4 | \ 120 ETH_RSS_FRAG_IPV4 | \ 121 ETH_RSS_NONFRAG_IPV4_TCP | \ 122 ETH_RSS_NONFRAG_IPV4_UDP | \ 123 ETH_RSS_NONFRAG_IPV4_SCTP | \ 124 ETH_RSS_NONFRAG_IPV4_OTHER | \ 125 ETH_RSS_IPV6 | \ 126 ETH_RSS_FRAG_IPV6 | \ 127 ETH_RSS_NONFRAG_IPV6_TCP | \ 128 ETH_RSS_NONFRAG_IPV6_UDP | \ 129 ETH_RSS_NONFRAG_IPV6_SCTP | \ 130 ETH_RSS_NONFRAG_IPV6_OTHER | \ 131 ETH_RSS_L2_PAYLOAD) 132 133 /** 134 * The overhead from MTU to max frame size. 135 * Considering QinQ packet, the VLAN tag needs to be counted twice. 136 */ 137 #define ICE_ETH_OVERHEAD \ 138 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE * 2) 139 #define ICE_ETH_MAX_LEN (RTE_ETHER_MTU + ICE_ETH_OVERHEAD) 140 141 #define ICE_RXTX_BYTES_HIGH(bytes) ((bytes) & ~ICE_40_BIT_MASK) 142 #define ICE_RXTX_BYTES_LOW(bytes) ((bytes) & ICE_40_BIT_MASK) 143 144 /* Max number of flexible descriptor rxdid */ 145 #define ICE_FLEX_DESC_RXDID_MAX_NUM 64 146 147 /* Per-channel register definitions */ 148 #define GLTSYN_AUX_OUT(_chan, _idx) (GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8)) 149 #define GLTSYN_CLKO(_chan, _idx) (GLTSYN_CLKO_0(_idx) + ((_chan) * 8)) 150 #define GLTSYN_TGT_L(_chan, _idx) (GLTSYN_TGT_L_0(_idx) + ((_chan) * 16)) 151 #define GLTSYN_TGT_H(_chan, _idx) (GLTSYN_TGT_H_0(_idx) + ((_chan) * 16)) 152 153 /* DDP package type */ 154 enum ice_pkg_type { 155 ICE_PKG_TYPE_UNKNOWN, 156 ICE_PKG_TYPE_OS_DEFAULT, 157 ICE_PKG_TYPE_COMMS, 158 }; 159 160 enum pps_type { 161 PPS_NONE, 162 PPS_PIN, 163 PPS_MAX, 164 }; 165 166 struct ice_adapter; 167 168 /** 169 * MAC filter structure 170 */ 171 struct ice_mac_filter_info { 172 struct rte_ether_addr mac_addr; 173 }; 174 175 TAILQ_HEAD(ice_mac_filter_list, ice_mac_filter); 176 177 /* MAC filter list structure */ 178 struct ice_mac_filter { 179 TAILQ_ENTRY(ice_mac_filter) next; 180 struct ice_mac_filter_info mac_info; 181 }; 182 183 struct ice_vlan { 184 uint16_t tpid; 185 uint16_t vid; 186 }; 187 188 #define ICE_VLAN(tpid, vid) \ 189 ((struct ice_vlan){ tpid, vid }) 190 191 /** 192 * VLAN filter structure 193 */ 194 struct ice_vlan_filter_info { 195 struct ice_vlan vlan; 196 }; 197 198 TAILQ_HEAD(ice_vlan_filter_list, ice_vlan_filter); 199 200 /* VLAN filter list structure */ 201 struct ice_vlan_filter { 202 TAILQ_ENTRY(ice_vlan_filter) next; 203 struct ice_vlan_filter_info vlan_info; 204 }; 205 206 struct pool_entry { 207 LIST_ENTRY(pool_entry) next; 208 uint16_t base; 209 uint16_t len; 210 }; 211 212 LIST_HEAD(res_list, pool_entry); 213 214 struct ice_res_pool_info { 215 uint32_t base; /* Resource start index */ 216 uint32_t num_alloc; /* Allocated resource number */ 217 uint32_t num_free; /* Total available resource number */ 218 struct res_list alloc_list; /* Allocated resource list */ 219 struct res_list free_list; /* Available resource list */ 220 }; 221 222 TAILQ_HEAD(ice_vsi_list_head, ice_vsi_list); 223 224 struct ice_vsi; 225 226 /* VSI list structure */ 227 struct ice_vsi_list { 228 TAILQ_ENTRY(ice_vsi_list) list; 229 struct ice_vsi *vsi; 230 }; 231 232 struct ice_rx_queue; 233 struct ice_tx_queue; 234 235 /** 236 * Structure that defines a VSI, associated with a adapter. 237 */ 238 struct ice_vsi { 239 struct ice_adapter *adapter; /* Backreference to associated adapter */ 240 struct ice_aqc_vsi_props info; /* VSI properties */ 241 /** 242 * When drivers loaded, only a default main VSI exists. In case new VSI 243 * needs to add, HW needs to know the layout that VSIs are organized. 244 * Besides that, VSI isan element and can't switch packets, which needs 245 * to add new component VEB to perform switching. So, a new VSI needs 246 * to specify the the uplink VSI (Parent VSI) before created. The 247 * uplink VSI will check whether it had a VEB to switch packets. If no, 248 * it will try to create one. Then, uplink VSI will move the new VSI 249 * into its' sib_vsi_list to manage all the downlink VSI. 250 * sib_vsi_list: the VSI list that shared the same uplink VSI. 251 * parent_vsi : the uplink VSI. It's NULL for main VSI. 252 * veb : the VEB associates with the VSI. 253 */ 254 struct ice_vsi_list sib_vsi_list; /* sibling vsi list */ 255 struct ice_vsi *parent_vsi; 256 enum ice_vsi_type type; /* VSI types */ 257 uint16_t vlan_num; /* Total VLAN number */ 258 uint16_t mac_num; /* Total mac number */ 259 struct ice_mac_filter_list mac_list; /* macvlan filter list */ 260 struct ice_vlan_filter_list vlan_list; /* vlan filter list */ 261 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ 262 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ 263 uint16_t max_macaddrs; /* Maximum number of MAC addresses */ 264 uint16_t base_queue; /* The first queue index of this VSI */ 265 uint16_t vsi_id; /* Hardware Id */ 266 uint16_t idx; /* vsi_handle: SW index in hw->vsi_ctx */ 267 /* VF number to which the VSI connects, valid when VSI is VF type */ 268 uint8_t vf_num; 269 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ 270 uint16_t nb_msix; /* The max number of msix vector */ 271 uint8_t enabled_tc; /* The traffic class enabled */ 272 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ 273 uint8_t vlan_filter_on; /* The VLAN filter enabled */ 274 /* information about rss configuration */ 275 u32 rss_key_size; 276 u32 rss_lut_size; 277 uint8_t *rss_lut; 278 uint8_t *rss_key; 279 struct ice_eth_stats eth_stats_offset; 280 struct ice_eth_stats eth_stats; 281 bool offset_loaded; 282 uint64_t old_rx_bytes; 283 uint64_t old_tx_bytes; 284 }; 285 286 enum proto_xtr_type { 287 PROTO_XTR_NONE, 288 PROTO_XTR_VLAN, 289 PROTO_XTR_IPV4, 290 PROTO_XTR_IPV6, 291 PROTO_XTR_IPV6_FLOW, 292 PROTO_XTR_TCP, 293 PROTO_XTR_IP_OFFSET, 294 PROTO_XTR_MAX /* The last one */ 295 }; 296 297 enum ice_fdir_tunnel_type { 298 ICE_FDIR_TUNNEL_TYPE_NONE = 0, 299 ICE_FDIR_TUNNEL_TYPE_VXLAN, 300 ICE_FDIR_TUNNEL_TYPE_GTPU, 301 ICE_FDIR_TUNNEL_TYPE_GTPU_EH, 302 }; 303 304 struct rte_flow; 305 TAILQ_HEAD(ice_flow_list, rte_flow); 306 307 struct ice_flow_parser_node; 308 TAILQ_HEAD(ice_parser_list, ice_flow_parser_node); 309 310 struct ice_fdir_filter_conf { 311 struct ice_fdir_fltr input; 312 enum ice_fdir_tunnel_type tunnel_type; 313 314 struct ice_fdir_counter *counter; /* flow specific counter context */ 315 struct rte_flow_action_count act_count; 316 317 uint64_t input_set_o; /* used for non-tunnel or tunnel outer fields */ 318 uint64_t input_set_i; /* only for tunnel inner fields */ 319 uint32_t mark_flag; 320 }; 321 322 #define ICE_MAX_FDIR_FILTER_NUM (1024 * 16) 323 324 struct ice_fdir_fltr_pattern { 325 enum ice_fltr_ptype flow_type; 326 327 union { 328 struct ice_fdir_v4 v4; 329 struct ice_fdir_v6 v6; 330 } ip, mask; 331 332 struct ice_fdir_udp_gtp gtpu_data; 333 struct ice_fdir_udp_gtp gtpu_mask; 334 335 struct ice_fdir_extra ext_data; 336 struct ice_fdir_extra ext_mask; 337 338 enum ice_fdir_tunnel_type tunnel_type; 339 }; 340 341 #define ICE_FDIR_COUNTER_DEFAULT_POOL_SIZE 1 342 #define ICE_FDIR_COUNTER_MAX_POOL_SIZE 32 343 #define ICE_FDIR_COUNTERS_PER_BLOCK 256 344 #define ICE_FDIR_COUNTER_INDEX(base_idx) \ 345 ((base_idx) * ICE_FDIR_COUNTERS_PER_BLOCK) 346 struct ice_fdir_counter_pool; 347 348 struct ice_fdir_counter { 349 TAILQ_ENTRY(ice_fdir_counter) next; 350 struct ice_fdir_counter_pool *pool; 351 uint8_t shared; 352 uint32_t ref_cnt; 353 uint32_t id; 354 uint64_t hits; 355 uint64_t bytes; 356 uint32_t hw_index; 357 }; 358 359 TAILQ_HEAD(ice_fdir_counter_list, ice_fdir_counter); 360 361 struct ice_fdir_counter_pool { 362 TAILQ_ENTRY(ice_fdir_counter_pool) next; 363 struct ice_fdir_counter_list counter_list; 364 struct ice_fdir_counter counters[0]; 365 }; 366 367 TAILQ_HEAD(ice_fdir_counter_pool_list, ice_fdir_counter_pool); 368 369 struct ice_fdir_counter_pool_container { 370 struct ice_fdir_counter_pool_list pool_list; 371 struct ice_fdir_counter_pool *pools[ICE_FDIR_COUNTER_MAX_POOL_SIZE]; 372 uint8_t index_free; 373 }; 374 375 /** 376 * A structure used to define fields of a FDIR related info. 377 */ 378 struct ice_fdir_info { 379 struct ice_vsi *fdir_vsi; /* pointer to fdir VSI structure */ 380 struct ice_tx_queue *txq; 381 struct ice_rx_queue *rxq; 382 void *prg_pkt; /* memory for fdir program packet */ 383 uint64_t dma_addr; /* physic address of packet memory*/ 384 const struct rte_memzone *mz; 385 struct ice_fdir_filter_conf conf; 386 387 struct ice_fdir_filter_conf **hash_map; 388 struct rte_hash *hash_table; 389 390 struct ice_fdir_counter_pool_container counter; 391 }; 392 393 #define ICE_HASH_GTPU_CTX_EH_IP 0 394 #define ICE_HASH_GTPU_CTX_EH_IP_UDP 1 395 #define ICE_HASH_GTPU_CTX_EH_IP_TCP 2 396 #define ICE_HASH_GTPU_CTX_UP_IP 3 397 #define ICE_HASH_GTPU_CTX_UP_IP_UDP 4 398 #define ICE_HASH_GTPU_CTX_UP_IP_TCP 5 399 #define ICE_HASH_GTPU_CTX_DW_IP 6 400 #define ICE_HASH_GTPU_CTX_DW_IP_UDP 7 401 #define ICE_HASH_GTPU_CTX_DW_IP_TCP 8 402 #define ICE_HASH_GTPU_CTX_MAX 9 403 404 struct ice_hash_gtpu_ctx { 405 struct ice_rss_hash_cfg ctx[ICE_HASH_GTPU_CTX_MAX]; 406 }; 407 408 struct ice_hash_ctx { 409 struct ice_hash_gtpu_ctx gtpu4; 410 struct ice_hash_gtpu_ctx gtpu6; 411 }; 412 413 struct ice_acl_conf { 414 struct ice_fdir_fltr input; 415 uint64_t input_set; 416 }; 417 418 /** 419 * A structure used to define fields of ACL related info. 420 */ 421 struct ice_acl_info { 422 struct ice_acl_conf conf; 423 struct rte_bitmap *slots; 424 uint64_t hw_entry_id[MAX_ACL_NORMAL_ENTRIES]; 425 }; 426 427 struct ice_pf { 428 struct ice_adapter *adapter; /* The adapter this PF associate to */ 429 struct ice_vsi *main_vsi; /* pointer to main VSI structure */ 430 /* Used for next free software vsi idx. 431 * To save the effort, we don't recycle the index. 432 * Suppose the indexes are more than enough. 433 */ 434 uint16_t next_vsi_idx; 435 uint16_t vsis_allocated; 436 uint16_t vsis_unallocated; 437 struct ice_res_pool_info qp_pool; /*Queue pair pool */ 438 struct ice_res_pool_info msix_pool; /* MSIX interrupt pool */ 439 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 440 struct rte_ether_addr dev_addr; /* PF device mac address */ 441 uint64_t flags; /* PF feature flags */ 442 uint16_t hash_lut_size; /* The size of hash lookup table */ 443 uint16_t lan_nb_qp_max; 444 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ 445 uint16_t base_queue; /* The base queue pairs index in the device */ 446 uint8_t *proto_xtr; /* Protocol extraction type for all queues */ 447 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ 448 uint16_t fdir_qp_offset; 449 struct ice_fdir_info fdir; /* flow director info */ 450 struct ice_acl_info acl; /* ACL info */ 451 struct ice_hash_ctx hash_ctx; 452 uint16_t hw_prof_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX]; 453 uint16_t fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX]; 454 struct ice_hw_port_stats stats_offset; 455 struct ice_hw_port_stats stats; 456 /* internal packet statistics, it should be excluded from the total */ 457 struct ice_eth_stats internal_stats_offset; 458 struct ice_eth_stats internal_stats; 459 bool offset_loaded; 460 bool adapter_stopped; 461 struct ice_flow_list flow_list; 462 rte_spinlock_t flow_ops_lock; 463 struct ice_parser_list rss_parser_list; 464 struct ice_parser_list perm_parser_list; 465 struct ice_parser_list dist_parser_list; 466 bool init_link_up; 467 uint64_t old_rx_bytes; 468 uint64_t old_tx_bytes; 469 uint64_t supported_rxdid; /* bitmap for supported RXDID */ 470 uint64_t rss_hf; 471 }; 472 473 #define ICE_MAX_QUEUE_NUM 2048 474 #define ICE_MAX_PIN_NUM 4 475 476 /** 477 * Cache devargs parse result. 478 */ 479 struct ice_devargs { 480 int rx_low_latency; 481 int safe_mode_support; 482 uint8_t proto_xtr_dflt; 483 int pipe_mode_support; 484 uint8_t proto_xtr[ICE_MAX_QUEUE_NUM]; 485 uint8_t pin_idx; 486 uint8_t pps_out_ena; 487 }; 488 489 /** 490 * Structure to store private data for each PF/VF instance. 491 */ 492 struct ice_adapter { 493 /* Common for both PF and VF */ 494 struct ice_hw hw; 495 struct ice_pf pf; 496 bool rx_bulk_alloc_allowed; 497 bool rx_vec_allowed; 498 bool tx_vec_allowed; 499 bool tx_simple_allowed; 500 /* ptype mapping table */ 501 uint32_t ptype_tbl[ICE_MAX_PKT_TYPE] __rte_cache_min_aligned; 502 bool is_safe_mode; 503 struct ice_devargs devargs; 504 enum ice_pkg_type active_pkg_type; /* loaded ddp package type */ 505 uint16_t fdir_ref_cnt; 506 /* For PTP */ 507 struct rte_timecounter systime_tc; 508 struct rte_timecounter rx_tstamp_tc; 509 struct rte_timecounter tx_tstamp_tc; 510 bool ptp_ena; 511 #ifdef RTE_ARCH_X86 512 bool rx_use_avx2; 513 bool rx_use_avx512; 514 bool tx_use_avx2; 515 bool tx_use_avx512; 516 #endif 517 }; 518 519 struct ice_vsi_vlan_pvid_info { 520 uint16_t on; /* Enable or disable pvid */ 521 union { 522 uint16_t pvid; /* Valid in case 'on' is set to set pvid */ 523 struct { 524 /* Valid in case 'on' is cleared. 'tagged' will reject 525 * tagged packets, while 'untagged' will reject 526 * untagged packets. 527 */ 528 uint8_t tagged; 529 uint8_t untagged; 530 } reject; 531 } config; 532 }; 533 534 #define ICE_DEV_TO_PCI(eth_dev) \ 535 RTE_DEV_TO_PCI((eth_dev)->device) 536 537 /* ICE_DEV_PRIVATE_TO */ 538 #define ICE_DEV_PRIVATE_TO_PF(adapter) \ 539 (&((struct ice_adapter *)adapter)->pf) 540 #define ICE_DEV_PRIVATE_TO_HW(adapter) \ 541 (&((struct ice_adapter *)adapter)->hw) 542 #define ICE_DEV_PRIVATE_TO_ADAPTER(adapter) \ 543 ((struct ice_adapter *)adapter) 544 545 /* ICE_VSI_TO */ 546 #define ICE_VSI_TO_HW(vsi) \ 547 (&(((struct ice_vsi *)vsi)->adapter->hw)) 548 #define ICE_VSI_TO_PF(vsi) \ 549 (&(((struct ice_vsi *)vsi)->adapter->pf)) 550 551 /* ICE_PF_TO */ 552 #define ICE_PF_TO_HW(pf) \ 553 (&(((struct ice_pf *)pf)->adapter->hw)) 554 #define ICE_PF_TO_ADAPTER(pf) \ 555 ((struct ice_adapter *)(pf)->adapter) 556 #define ICE_PF_TO_ETH_DEV(pf) \ 557 (((struct ice_pf *)pf)->adapter->eth_dev) 558 559 int 560 ice_load_pkg(struct ice_adapter *adapter, bool use_dsn, uint64_t dsn); 561 struct ice_vsi * 562 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type); 563 int 564 ice_release_vsi(struct ice_vsi *vsi); 565 void ice_vsi_enable_queues_intr(struct ice_vsi *vsi); 566 void ice_vsi_disable_queues_intr(struct ice_vsi *vsi); 567 void ice_vsi_queues_bind_intr(struct ice_vsi *vsi); 568 int ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, 569 struct ice_rss_hash_cfg *cfg); 570 int ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, 571 struct ice_rss_hash_cfg *cfg); 572 573 static inline int 574 ice_align_floor(int n) 575 { 576 if (n == 0) 577 return 0; 578 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); 579 } 580 581 #define ICE_PHY_TYPE_SUPPORT_50G(phy_type) \ 582 (((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CR2) || \ 583 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR2) || \ 584 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR2) || \ 585 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR2) || \ 586 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC) || \ 587 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2) || \ 588 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC) || \ 589 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2) || \ 590 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CP) || \ 591 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR) || \ 592 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_FR) || \ 593 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR) || \ 594 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4) || \ 595 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC) || \ 596 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1)) 597 598 #define ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type) \ 599 (((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR4) || \ 600 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR4) || \ 601 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_LR4) || \ 602 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR4) || \ 603 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC) || \ 604 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4) || \ 605 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC) || \ 606 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4) || \ 607 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4) || \ 608 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4) || \ 609 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CP2) || \ 610 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR2) || \ 611 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_DR)) 612 613 #define ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type) \ 614 (((phy_type) & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) || \ 615 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC) || \ 616 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2) || \ 617 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC) || \ 618 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2)) 619 620 #endif /* _ICE_ETHDEV_H_ */ 621