1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 5 #ifndef _ICE_ETHDEV_H_ 6 #define _ICE_ETHDEV_H_ 7 8 #include <rte_kvargs.h> 9 10 #include <rte_ethdev_driver.h> 11 12 #include "base/ice_common.h" 13 #include "base/ice_adminq_cmd.h" 14 #include "base/ice_flow.h" 15 16 #define ICE_VLAN_TAG_SIZE 4 17 18 #define ICE_ADMINQ_LEN 32 19 #define ICE_SBIOQ_LEN 32 20 #define ICE_MAILBOXQ_LEN 32 21 #define ICE_ADMINQ_BUF_SZ 4096 22 #define ICE_SBIOQ_BUF_SZ 4096 23 #define ICE_MAILBOXQ_BUF_SZ 4096 24 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ 25 #define ICE_MAX_Q_PER_TC 64 26 #define ICE_NUM_DESC_DEFAULT 512 27 #define ICE_BUF_SIZE_MIN 1024 28 #define ICE_FRAME_SIZE_MAX 9728 29 #define ICE_QUEUE_BASE_ADDR_UNIT 128 30 /* number of VSIs and queue default setting */ 31 #define ICE_MAX_QP_NUM_PER_VF 16 32 #define ICE_DEFAULT_QP_NUM_FDIR 1 33 #define ICE_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) 34 #define ICE_VFTA_SIZE (4096 / ICE_UINT32_BIT_SIZE) 35 /* Maximun number of MAC addresses */ 36 #define ICE_NUM_MACADDR_MAX 64 37 /* Maximum number of VFs */ 38 #define ICE_MAX_VF 128 39 #define ICE_MAX_INTR_QUEUE_NUM 256 40 41 #define ICE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 42 #define ICE_RX_VEC_ID RTE_INTR_VEC_RXTX_OFFSET 43 44 #define ICE_MAX_PKT_TYPE 1024 45 46 /* DDP package search path */ 47 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg" 48 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg" 49 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/" 50 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/" 51 #define ICE_MAX_PKG_FILENAME_SIZE 256 52 53 #define MAX_ACL_ENTRIES 512 54 55 /** 56 * vlan_id is a 12 bit number. 57 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 58 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 59 * The higher 7 bit val specifies VFTA array index. 60 */ 61 #define ICE_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 62 #define ICE_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 63 64 /* Default TC traffic in case DCB is not enabled */ 65 #define ICE_DEFAULT_TCMAP 0x1 66 #define ICE_FDIR_QUEUE_ID 0 67 68 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ 69 #define ICE_VMDQ_POOL_BASE 1 70 71 #define ICE_DEFAULT_RX_FREE_THRESH 32 72 #define ICE_DEFAULT_RX_PTHRESH 8 73 #define ICE_DEFAULT_RX_HTHRESH 8 74 #define ICE_DEFAULT_RX_WTHRESH 0 75 76 #define ICE_DEFAULT_TX_FREE_THRESH 32 77 #define ICE_DEFAULT_TX_PTHRESH 32 78 #define ICE_DEFAULT_TX_HTHRESH 0 79 #define ICE_DEFAULT_TX_WTHRESH 0 80 #define ICE_DEFAULT_TX_RSBIT_THRESH 32 81 82 /* Bit shift and mask */ 83 #define ICE_4_BIT_WIDTH (CHAR_BIT / 2) 84 #define ICE_4_BIT_MASK RTE_LEN2MASK(ICE_4_BIT_WIDTH, uint8_t) 85 #define ICE_8_BIT_WIDTH CHAR_BIT 86 #define ICE_8_BIT_MASK UINT8_MAX 87 #define ICE_16_BIT_WIDTH (CHAR_BIT * 2) 88 #define ICE_16_BIT_MASK UINT16_MAX 89 #define ICE_32_BIT_WIDTH (CHAR_BIT * 4) 90 #define ICE_32_BIT_MASK UINT32_MAX 91 #define ICE_40_BIT_WIDTH (CHAR_BIT * 5) 92 #define ICE_40_BIT_MASK RTE_LEN2MASK(ICE_40_BIT_WIDTH, uint64_t) 93 #define ICE_48_BIT_WIDTH (CHAR_BIT * 6) 94 #define ICE_48_BIT_MASK RTE_LEN2MASK(ICE_48_BIT_WIDTH, uint64_t) 95 96 #define ICE_FLAG_RSS BIT_ULL(0) 97 #define ICE_FLAG_DCB BIT_ULL(1) 98 #define ICE_FLAG_VMDQ BIT_ULL(2) 99 #define ICE_FLAG_SRIOV BIT_ULL(3) 100 #define ICE_FLAG_HEADER_SPLIT_DISABLED BIT_ULL(4) 101 #define ICE_FLAG_HEADER_SPLIT_ENABLED BIT_ULL(5) 102 #define ICE_FLAG_FDIR BIT_ULL(6) 103 #define ICE_FLAG_VXLAN BIT_ULL(7) 104 #define ICE_FLAG_RSS_AQ_CAPABLE BIT_ULL(8) 105 #define ICE_FLAG_VF_MAC_BY_PF BIT_ULL(9) 106 #define ICE_FLAG_ALL (ICE_FLAG_RSS | \ 107 ICE_FLAG_DCB | \ 108 ICE_FLAG_VMDQ | \ 109 ICE_FLAG_SRIOV | \ 110 ICE_FLAG_HEADER_SPLIT_DISABLED | \ 111 ICE_FLAG_HEADER_SPLIT_ENABLED | \ 112 ICE_FLAG_FDIR | \ 113 ICE_FLAG_VXLAN | \ 114 ICE_FLAG_RSS_AQ_CAPABLE | \ 115 ICE_FLAG_VF_MAC_BY_PF) 116 117 #define ICE_RSS_OFFLOAD_ALL ( \ 118 ETH_RSS_IPV4 | \ 119 ETH_RSS_FRAG_IPV4 | \ 120 ETH_RSS_NONFRAG_IPV4_TCP | \ 121 ETH_RSS_NONFRAG_IPV4_UDP | \ 122 ETH_RSS_NONFRAG_IPV4_SCTP | \ 123 ETH_RSS_NONFRAG_IPV4_OTHER | \ 124 ETH_RSS_IPV6 | \ 125 ETH_RSS_FRAG_IPV6 | \ 126 ETH_RSS_NONFRAG_IPV6_TCP | \ 127 ETH_RSS_NONFRAG_IPV6_UDP | \ 128 ETH_RSS_NONFRAG_IPV6_SCTP | \ 129 ETH_RSS_NONFRAG_IPV6_OTHER | \ 130 ETH_RSS_L2_PAYLOAD) 131 132 /** 133 * The overhead from MTU to max frame size. 134 * Considering QinQ packet, the VLAN tag needs to be counted twice. 135 */ 136 #define ICE_ETH_OVERHEAD \ 137 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE * 2) 138 139 #define ICE_RXTX_BYTES_HIGH(bytes) ((bytes) & ~ICE_40_BIT_MASK) 140 #define ICE_RXTX_BYTES_LOW(bytes) ((bytes) & ICE_40_BIT_MASK) 141 142 /* Max number of flexible descriptor rxdid */ 143 #define ICE_FLEX_DESC_RXDID_MAX_NUM 64 144 145 /* DDP package type */ 146 enum ice_pkg_type { 147 ICE_PKG_TYPE_UNKNOWN, 148 ICE_PKG_TYPE_OS_DEFAULT, 149 ICE_PKG_TYPE_COMMS, 150 }; 151 152 struct ice_adapter; 153 154 /** 155 * MAC filter structure 156 */ 157 struct ice_mac_filter_info { 158 struct rte_ether_addr mac_addr; 159 }; 160 161 TAILQ_HEAD(ice_mac_filter_list, ice_mac_filter); 162 163 /* MAC filter list structure */ 164 struct ice_mac_filter { 165 TAILQ_ENTRY(ice_mac_filter) next; 166 struct ice_mac_filter_info mac_info; 167 }; 168 169 /** 170 * VLAN filter structure 171 */ 172 struct ice_vlan_filter_info { 173 uint16_t vlan_id; 174 }; 175 176 TAILQ_HEAD(ice_vlan_filter_list, ice_vlan_filter); 177 178 /* VLAN filter list structure */ 179 struct ice_vlan_filter { 180 TAILQ_ENTRY(ice_vlan_filter) next; 181 struct ice_vlan_filter_info vlan_info; 182 }; 183 184 struct pool_entry { 185 LIST_ENTRY(pool_entry) next; 186 uint16_t base; 187 uint16_t len; 188 }; 189 190 LIST_HEAD(res_list, pool_entry); 191 192 struct ice_res_pool_info { 193 uint32_t base; /* Resource start index */ 194 uint32_t num_alloc; /* Allocated resource number */ 195 uint32_t num_free; /* Total available resource number */ 196 struct res_list alloc_list; /* Allocated resource list */ 197 struct res_list free_list; /* Available resource list */ 198 }; 199 200 TAILQ_HEAD(ice_vsi_list_head, ice_vsi_list); 201 202 struct ice_vsi; 203 204 /* VSI list structure */ 205 struct ice_vsi_list { 206 TAILQ_ENTRY(ice_vsi_list) list; 207 struct ice_vsi *vsi; 208 }; 209 210 struct ice_rx_queue; 211 struct ice_tx_queue; 212 213 /** 214 * Structure that defines a VSI, associated with a adapter. 215 */ 216 struct ice_vsi { 217 struct ice_adapter *adapter; /* Backreference to associated adapter */ 218 struct ice_aqc_vsi_props info; /* VSI properties */ 219 /** 220 * When drivers loaded, only a default main VSI exists. In case new VSI 221 * needs to add, HW needs to know the layout that VSIs are organized. 222 * Besides that, VSI isan element and can't switch packets, which needs 223 * to add new component VEB to perform switching. So, a new VSI needs 224 * to specify the the uplink VSI (Parent VSI) before created. The 225 * uplink VSI will check whether it had a VEB to switch packets. If no, 226 * it will try to create one. Then, uplink VSI will move the new VSI 227 * into its' sib_vsi_list to manage all the downlink VSI. 228 * sib_vsi_list: the VSI list that shared the same uplink VSI. 229 * parent_vsi : the uplink VSI. It's NULL for main VSI. 230 * veb : the VEB associates with the VSI. 231 */ 232 struct ice_vsi_list sib_vsi_list; /* sibling vsi list */ 233 struct ice_vsi *parent_vsi; 234 enum ice_vsi_type type; /* VSI types */ 235 uint16_t vlan_num; /* Total VLAN number */ 236 uint16_t mac_num; /* Total mac number */ 237 struct ice_mac_filter_list mac_list; /* macvlan filter list */ 238 struct ice_vlan_filter_list vlan_list; /* vlan filter list */ 239 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ 240 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ 241 uint16_t max_macaddrs; /* Maximum number of MAC addresses */ 242 uint16_t base_queue; /* The first queue index of this VSI */ 243 uint16_t vsi_id; /* Hardware Id */ 244 uint16_t idx; /* vsi_handle: SW index in hw->vsi_ctx */ 245 /* VF number to which the VSI connects, valid when VSI is VF type */ 246 uint8_t vf_num; 247 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ 248 uint16_t nb_msix; /* The max number of msix vector */ 249 uint8_t enabled_tc; /* The traffic class enabled */ 250 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ 251 uint8_t vlan_filter_on; /* The VLAN filter enabled */ 252 /* information about rss configuration */ 253 u32 rss_key_size; 254 u32 rss_lut_size; 255 uint8_t *rss_lut; 256 uint8_t *rss_key; 257 struct ice_eth_stats eth_stats_offset; 258 struct ice_eth_stats eth_stats; 259 bool offset_loaded; 260 uint64_t old_rx_bytes; 261 uint64_t old_tx_bytes; 262 }; 263 264 enum proto_xtr_type { 265 PROTO_XTR_NONE, 266 PROTO_XTR_VLAN, 267 PROTO_XTR_IPV4, 268 PROTO_XTR_IPV6, 269 PROTO_XTR_IPV6_FLOW, 270 PROTO_XTR_TCP, 271 PROTO_XTR_IP_OFFSET, 272 PROTO_XTR_MAX /* The last one */ 273 }; 274 275 enum ice_fdir_tunnel_type { 276 ICE_FDIR_TUNNEL_TYPE_NONE = 0, 277 ICE_FDIR_TUNNEL_TYPE_VXLAN, 278 ICE_FDIR_TUNNEL_TYPE_GTPU, 279 ICE_FDIR_TUNNEL_TYPE_GTPU_EH, 280 }; 281 282 struct rte_flow; 283 TAILQ_HEAD(ice_flow_list, rte_flow); 284 285 struct ice_flow_parser_node; 286 TAILQ_HEAD(ice_parser_list, ice_flow_parser_node); 287 288 struct ice_fdir_filter_conf { 289 struct ice_fdir_fltr input; 290 enum ice_fdir_tunnel_type tunnel_type; 291 292 struct ice_fdir_counter *counter; /* flow specific counter context */ 293 struct rte_flow_action_count act_count; 294 295 uint64_t input_set; 296 uint64_t outer_input_set; /* only for tunnel packets outer fields */ 297 uint32_t mark_flag; 298 }; 299 300 #define ICE_MAX_FDIR_FILTER_NUM (1024 * 16) 301 302 struct ice_fdir_fltr_pattern { 303 enum ice_fltr_ptype flow_type; 304 305 union { 306 struct ice_fdir_v4 v4; 307 struct ice_fdir_v6 v6; 308 } ip, mask; 309 310 struct ice_fdir_udp_gtp gtpu_data; 311 struct ice_fdir_udp_gtp gtpu_mask; 312 313 struct ice_fdir_extra ext_data; 314 struct ice_fdir_extra ext_mask; 315 316 enum ice_fdir_tunnel_type tunnel_type; 317 }; 318 319 #define ICE_FDIR_COUNTER_DEFAULT_POOL_SIZE 1 320 #define ICE_FDIR_COUNTER_MAX_POOL_SIZE 32 321 #define ICE_FDIR_COUNTERS_PER_BLOCK 256 322 #define ICE_FDIR_COUNTER_INDEX(base_idx) \ 323 ((base_idx) * ICE_FDIR_COUNTERS_PER_BLOCK) 324 struct ice_fdir_counter_pool; 325 326 struct ice_fdir_counter { 327 TAILQ_ENTRY(ice_fdir_counter) next; 328 struct ice_fdir_counter_pool *pool; 329 uint8_t shared; 330 uint32_t ref_cnt; 331 uint32_t id; 332 uint64_t hits; 333 uint64_t bytes; 334 uint32_t hw_index; 335 }; 336 337 TAILQ_HEAD(ice_fdir_counter_list, ice_fdir_counter); 338 339 struct ice_fdir_counter_pool { 340 TAILQ_ENTRY(ice_fdir_counter_pool) next; 341 struct ice_fdir_counter_list counter_list; 342 struct ice_fdir_counter counters[0]; 343 }; 344 345 TAILQ_HEAD(ice_fdir_counter_pool_list, ice_fdir_counter_pool); 346 347 struct ice_fdir_counter_pool_container { 348 struct ice_fdir_counter_pool_list pool_list; 349 struct ice_fdir_counter_pool *pools[ICE_FDIR_COUNTER_MAX_POOL_SIZE]; 350 uint8_t index_free; 351 }; 352 353 /** 354 * A structure used to define fields of a FDIR related info. 355 */ 356 struct ice_fdir_info { 357 struct ice_vsi *fdir_vsi; /* pointer to fdir VSI structure */ 358 struct ice_tx_queue *txq; 359 struct ice_rx_queue *rxq; 360 void *prg_pkt; /* memory for fdir program packet */ 361 uint64_t dma_addr; /* physic address of packet memory*/ 362 const struct rte_memzone *mz; 363 struct ice_fdir_filter_conf conf; 364 365 struct ice_fdir_filter_conf **hash_map; 366 struct rte_hash *hash_table; 367 368 struct ice_fdir_counter_pool_container counter; 369 }; 370 371 #define ICE_HASH_GTPU_CTX_EH_IP 0 372 #define ICE_HASH_GTPU_CTX_EH_IP_UDP 1 373 #define ICE_HASH_GTPU_CTX_EH_IP_TCP 2 374 #define ICE_HASH_GTPU_CTX_UP_IP 3 375 #define ICE_HASH_GTPU_CTX_UP_IP_UDP 4 376 #define ICE_HASH_GTPU_CTX_UP_IP_TCP 5 377 #define ICE_HASH_GTPU_CTX_DW_IP 6 378 #define ICE_HASH_GTPU_CTX_DW_IP_UDP 7 379 #define ICE_HASH_GTPU_CTX_DW_IP_TCP 8 380 #define ICE_HASH_GTPU_CTX_MAX 9 381 382 struct ice_hash_gtpu_ctx { 383 struct ice_rss_hash_cfg ctx[ICE_HASH_GTPU_CTX_MAX]; 384 }; 385 386 struct ice_hash_ctx { 387 struct ice_hash_gtpu_ctx gtpu4; 388 struct ice_hash_gtpu_ctx gtpu6; 389 }; 390 391 struct ice_acl_conf { 392 struct ice_fdir_fltr input; 393 uint64_t input_set; 394 }; 395 396 /** 397 * A structure used to define fields of ACL related info. 398 */ 399 struct ice_acl_info { 400 struct ice_acl_conf conf; 401 struct rte_bitmap *slots; 402 uint64_t hw_entry_id[MAX_ACL_ENTRIES]; 403 }; 404 405 struct ice_pf { 406 struct ice_adapter *adapter; /* The adapter this PF associate to */ 407 struct ice_vsi *main_vsi; /* pointer to main VSI structure */ 408 /* Used for next free software vsi idx. 409 * To save the effort, we don't recycle the index. 410 * Suppose the indexes are more than enough. 411 */ 412 uint16_t next_vsi_idx; 413 uint16_t vsis_allocated; 414 uint16_t vsis_unallocated; 415 struct ice_res_pool_info qp_pool; /*Queue pair pool */ 416 struct ice_res_pool_info msix_pool; /* MSIX interrupt pool */ 417 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 418 struct rte_ether_addr dev_addr; /* PF device mac address */ 419 uint64_t flags; /* PF feature flags */ 420 uint16_t hash_lut_size; /* The size of hash lookup table */ 421 uint16_t lan_nb_qp_max; 422 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ 423 uint16_t base_queue; /* The base queue pairs index in the device */ 424 uint8_t *proto_xtr; /* Protocol extraction type for all queues */ 425 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ 426 uint16_t fdir_qp_offset; 427 struct ice_fdir_info fdir; /* flow director info */ 428 struct ice_acl_info acl; /* ACL info */ 429 struct ice_hash_ctx hash_ctx; 430 uint16_t hw_prof_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX]; 431 uint16_t fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX]; 432 struct ice_hw_port_stats stats_offset; 433 struct ice_hw_port_stats stats; 434 /* internal packet statistics, it should be excluded from the total */ 435 struct ice_eth_stats internal_stats_offset; 436 struct ice_eth_stats internal_stats; 437 bool offset_loaded; 438 bool adapter_stopped; 439 struct ice_flow_list flow_list; 440 rte_spinlock_t flow_ops_lock; 441 struct ice_parser_list rss_parser_list; 442 struct ice_parser_list perm_parser_list; 443 struct ice_parser_list dist_parser_list; 444 bool init_link_up; 445 uint64_t old_rx_bytes; 446 uint64_t old_tx_bytes; 447 uint64_t supported_rxdid; /* bitmap for supported RXDID */ 448 uint64_t rss_hf; 449 }; 450 451 #define ICE_MAX_QUEUE_NUM 2048 452 453 /** 454 * Cache devargs parse result. 455 */ 456 struct ice_devargs { 457 int safe_mode_support; 458 uint8_t proto_xtr_dflt; 459 int pipe_mode_support; 460 uint8_t proto_xtr[ICE_MAX_QUEUE_NUM]; 461 }; 462 463 /** 464 * Structure to store private data for each PF/VF instance. 465 */ 466 struct ice_adapter { 467 /* Common for both PF and VF */ 468 struct ice_hw hw; 469 struct rte_eth_dev *eth_dev; 470 struct ice_pf pf; 471 bool rx_bulk_alloc_allowed; 472 bool rx_vec_allowed; 473 bool tx_vec_allowed; 474 bool tx_simple_allowed; 475 /* ptype mapping table */ 476 uint32_t ptype_tbl[ICE_MAX_PKT_TYPE] __rte_cache_min_aligned; 477 bool is_safe_mode; 478 struct ice_devargs devargs; 479 enum ice_pkg_type active_pkg_type; /* loaded ddp package type */ 480 uint16_t fdir_ref_cnt; 481 }; 482 483 struct ice_vsi_vlan_pvid_info { 484 uint16_t on; /* Enable or disable pvid */ 485 union { 486 uint16_t pvid; /* Valid in case 'on' is set to set pvid */ 487 struct { 488 /* Valid in case 'on' is cleared. 'tagged' will reject 489 * tagged packets, while 'untagged' will reject 490 * untagged packets. 491 */ 492 uint8_t tagged; 493 uint8_t untagged; 494 } reject; 495 } config; 496 }; 497 498 #define ICE_DEV_TO_PCI(eth_dev) \ 499 RTE_DEV_TO_PCI((eth_dev)->device) 500 501 /* ICE_DEV_PRIVATE_TO */ 502 #define ICE_DEV_PRIVATE_TO_PF(adapter) \ 503 (&((struct ice_adapter *)adapter)->pf) 504 #define ICE_DEV_PRIVATE_TO_HW(adapter) \ 505 (&((struct ice_adapter *)adapter)->hw) 506 #define ICE_DEV_PRIVATE_TO_ADAPTER(adapter) \ 507 ((struct ice_adapter *)adapter) 508 509 /* ICE_VSI_TO */ 510 #define ICE_VSI_TO_HW(vsi) \ 511 (&(((struct ice_vsi *)vsi)->adapter->hw)) 512 #define ICE_VSI_TO_PF(vsi) \ 513 (&(((struct ice_vsi *)vsi)->adapter->pf)) 514 #define ICE_VSI_TO_ETH_DEV(vsi) \ 515 (((struct ice_vsi *)vsi)->adapter->eth_dev) 516 517 /* ICE_PF_TO */ 518 #define ICE_PF_TO_HW(pf) \ 519 (&(((struct ice_pf *)pf)->adapter->hw)) 520 #define ICE_PF_TO_ADAPTER(pf) \ 521 ((struct ice_adapter *)(pf)->adapter) 522 #define ICE_PF_TO_ETH_DEV(pf) \ 523 (((struct ice_pf *)pf)->adapter->eth_dev) 524 525 enum ice_pkg_type ice_load_pkg_type(struct ice_hw *hw); 526 struct ice_vsi * 527 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type); 528 int 529 ice_release_vsi(struct ice_vsi *vsi); 530 void ice_vsi_enable_queues_intr(struct ice_vsi *vsi); 531 void ice_vsi_disable_queues_intr(struct ice_vsi *vsi); 532 void ice_vsi_queues_bind_intr(struct ice_vsi *vsi); 533 int ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, 534 struct ice_rss_hash_cfg *cfg); 535 int ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, 536 struct ice_rss_hash_cfg *cfg); 537 538 static inline int 539 ice_align_floor(int n) 540 { 541 if (n == 0) 542 return 0; 543 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); 544 } 545 546 #define ICE_PHY_TYPE_SUPPORT_50G(phy_type) \ 547 (((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CR2) || \ 548 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR2) || \ 549 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR2) || \ 550 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR2) || \ 551 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC) || \ 552 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2) || \ 553 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC) || \ 554 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2) || \ 555 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CP) || \ 556 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR) || \ 557 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_FR) || \ 558 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR) || \ 559 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4) || \ 560 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC) || \ 561 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1)) 562 563 #define ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type) \ 564 (((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR4) || \ 565 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR4) || \ 566 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_LR4) || \ 567 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR4) || \ 568 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC) || \ 569 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4) || \ 570 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC) || \ 571 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4) || \ 572 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4) || \ 573 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4) || \ 574 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CP2) || \ 575 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR2) || \ 576 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_DR)) 577 578 #define ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type) \ 579 (((phy_type) & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) || \ 580 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC) || \ 581 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2) || \ 582 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC) || \ 583 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2)) 584 585 #endif /* _ICE_ETHDEV_H_ */ 586