xref: /dpdk/drivers/net/ice/ice_ethdev.h (revision 742bde12)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2018 Intel Corporation
3  */
4 
5 #ifndef _ICE_ETHDEV_H_
6 #define _ICE_ETHDEV_H_
7 
8 #include <rte_kvargs.h>
9 
10 #include "base/ice_common.h"
11 #include "base/ice_adminq_cmd.h"
12 
13 #define ICE_VLAN_TAG_SIZE        4
14 
15 #define ICE_ADMINQ_LEN               32
16 #define ICE_SBIOQ_LEN                32
17 #define ICE_MAILBOXQ_LEN             32
18 #define ICE_ADMINQ_BUF_SZ            4096
19 #define ICE_SBIOQ_BUF_SZ             4096
20 #define ICE_MAILBOXQ_BUF_SZ          4096
21 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
22 #define ICE_MAX_Q_PER_TC         64
23 #define ICE_NUM_DESC_DEFAULT     512
24 #define ICE_BUF_SIZE_MIN         1024
25 #define ICE_FRAME_SIZE_MAX       9728
26 #define ICE_QUEUE_BASE_ADDR_UNIT 128
27 /* number of VSIs and queue default setting */
28 #define ICE_MAX_QP_NUM_PER_VF    16
29 #define ICE_DEFAULT_QP_NUM_FDIR  1
30 #define ICE_UINT32_BIT_SIZE      (CHAR_BIT * sizeof(uint32_t))
31 #define ICE_VFTA_SIZE            (4096 / ICE_UINT32_BIT_SIZE)
32 /* Maximun number of MAC addresses */
33 #define ICE_NUM_MACADDR_MAX       64
34 /* Maximum number of VFs */
35 #define ICE_MAX_VF               128
36 #define ICE_MAX_INTR_QUEUE_NUM   256
37 
38 #define ICE_MISC_VEC_ID          RTE_INTR_VEC_ZERO_OFFSET
39 #define ICE_RX_VEC_ID            RTE_INTR_VEC_RXTX_OFFSET
40 
41 #define ICE_MAX_PKT_TYPE  1024
42 
43 /**
44  * vlan_id is a 12 bit number.
45  * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
46  * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
47  * The higher 7 bit val specifies VFTA array index.
48  */
49 #define ICE_VFTA_BIT(vlan_id)    (1 << ((vlan_id) & 0x1F))
50 #define ICE_VFTA_IDX(vlan_id)    ((vlan_id) >> 5)
51 
52 /* Default TC traffic in case DCB is not enabled */
53 #define ICE_DEFAULT_TCMAP        0x1
54 #define ICE_FDIR_QUEUE_ID        0
55 
56 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
57 #define ICE_VMDQ_POOL_BASE       1
58 
59 #define ICE_DEFAULT_RX_FREE_THRESH  32
60 #define ICE_DEFAULT_RX_PTHRESH      8
61 #define ICE_DEFAULT_RX_HTHRESH      8
62 #define ICE_DEFAULT_RX_WTHRESH      0
63 
64 #define ICE_DEFAULT_TX_FREE_THRESH  32
65 #define ICE_DEFAULT_TX_PTHRESH      32
66 #define ICE_DEFAULT_TX_HTHRESH      0
67 #define ICE_DEFAULT_TX_WTHRESH      0
68 #define ICE_DEFAULT_TX_RSBIT_THRESH 32
69 
70 /* Bit shift and mask */
71 #define ICE_4_BIT_WIDTH  (CHAR_BIT / 2)
72 #define ICE_4_BIT_MASK   RTE_LEN2MASK(ICE_4_BIT_WIDTH, uint8_t)
73 #define ICE_8_BIT_WIDTH  CHAR_BIT
74 #define ICE_8_BIT_MASK   UINT8_MAX
75 #define ICE_16_BIT_WIDTH (CHAR_BIT * 2)
76 #define ICE_16_BIT_MASK  UINT16_MAX
77 #define ICE_32_BIT_WIDTH (CHAR_BIT * 4)
78 #define ICE_32_BIT_MASK  UINT32_MAX
79 #define ICE_40_BIT_WIDTH (CHAR_BIT * 5)
80 #define ICE_40_BIT_MASK  RTE_LEN2MASK(ICE_40_BIT_WIDTH, uint64_t)
81 #define ICE_48_BIT_WIDTH (CHAR_BIT * 6)
82 #define ICE_48_BIT_MASK  RTE_LEN2MASK(ICE_48_BIT_WIDTH, uint64_t)
83 
84 #define ICE_FLAG_RSS                   BIT_ULL(0)
85 #define ICE_FLAG_DCB                   BIT_ULL(1)
86 #define ICE_FLAG_VMDQ                  BIT_ULL(2)
87 #define ICE_FLAG_SRIOV                 BIT_ULL(3)
88 #define ICE_FLAG_HEADER_SPLIT_DISABLED BIT_ULL(4)
89 #define ICE_FLAG_HEADER_SPLIT_ENABLED  BIT_ULL(5)
90 #define ICE_FLAG_FDIR                  BIT_ULL(6)
91 #define ICE_FLAG_VXLAN                 BIT_ULL(7)
92 #define ICE_FLAG_RSS_AQ_CAPABLE        BIT_ULL(8)
93 #define ICE_FLAG_VF_MAC_BY_PF          BIT_ULL(9)
94 #define ICE_FLAG_ALL  (ICE_FLAG_RSS | \
95 		       ICE_FLAG_DCB | \
96 		       ICE_FLAG_VMDQ | \
97 		       ICE_FLAG_SRIOV | \
98 		       ICE_FLAG_HEADER_SPLIT_DISABLED | \
99 		       ICE_FLAG_HEADER_SPLIT_ENABLED | \
100 		       ICE_FLAG_FDIR | \
101 		       ICE_FLAG_VXLAN | \
102 		       ICE_FLAG_RSS_AQ_CAPABLE | \
103 		       ICE_FLAG_VF_MAC_BY_PF)
104 
105 #define ICE_RSS_OFFLOAD_ALL ( \
106 	ETH_RSS_FRAG_IPV4 | \
107 	ETH_RSS_NONFRAG_IPV4_TCP | \
108 	ETH_RSS_NONFRAG_IPV4_UDP | \
109 	ETH_RSS_NONFRAG_IPV4_SCTP | \
110 	ETH_RSS_NONFRAG_IPV4_OTHER | \
111 	ETH_RSS_FRAG_IPV6 | \
112 	ETH_RSS_NONFRAG_IPV6_TCP | \
113 	ETH_RSS_NONFRAG_IPV6_UDP | \
114 	ETH_RSS_NONFRAG_IPV6_SCTP | \
115 	ETH_RSS_NONFRAG_IPV6_OTHER | \
116 	ETH_RSS_L2_PAYLOAD)
117 
118 struct ice_adapter;
119 
120 /**
121  * MAC filter structure
122  */
123 struct ice_mac_filter_info {
124 	struct ether_addr mac_addr;
125 };
126 
127 TAILQ_HEAD(ice_mac_filter_list, ice_mac_filter);
128 
129 /* MAC filter list structure */
130 struct ice_mac_filter {
131 	TAILQ_ENTRY(ice_mac_filter) next;
132 	struct ice_mac_filter_info mac_info;
133 };
134 
135 /**
136  * VLAN filter structure
137  */
138 struct ice_vlan_filter_info {
139 	uint16_t vlan_id;
140 };
141 
142 TAILQ_HEAD(ice_vlan_filter_list, ice_vlan_filter);
143 
144 /* VLAN filter list structure */
145 struct ice_vlan_filter {
146 	TAILQ_ENTRY(ice_vlan_filter) next;
147 	struct ice_vlan_filter_info vlan_info;
148 };
149 
150 struct pool_entry {
151 	LIST_ENTRY(pool_entry) next;
152 	uint16_t base;
153 	uint16_t len;
154 };
155 
156 LIST_HEAD(res_list, pool_entry);
157 
158 struct ice_res_pool_info {
159 	uint32_t base;              /* Resource start index */
160 	uint32_t num_alloc;         /* Allocated resource number */
161 	uint32_t num_free;          /* Total available resource number */
162 	struct res_list alloc_list; /* Allocated resource list */
163 	struct res_list free_list;  /* Available resource list */
164 };
165 
166 TAILQ_HEAD(ice_vsi_list_head, ice_vsi_list);
167 
168 struct ice_vsi;
169 
170 /* VSI list structure */
171 struct ice_vsi_list {
172 	TAILQ_ENTRY(ice_vsi_list) list;
173 	struct ice_vsi *vsi;
174 };
175 
176 struct ice_rx_queue;
177 struct ice_tx_queue;
178 
179 /**
180  * Structure that defines a VSI, associated with a adapter.
181  */
182 struct ice_vsi {
183 	struct ice_adapter *adapter; /* Backreference to associated adapter */
184 	struct ice_aqc_vsi_props info; /* VSI properties */
185 	/**
186 	 * When drivers loaded, only a default main VSI exists. In case new VSI
187 	 * needs to add, HW needs to know the layout that VSIs are organized.
188 	 * Besides that, VSI isan element and can't switch packets, which needs
189 	 * to add new component VEB to perform switching. So, a new VSI needs
190 	 * to specify the the uplink VSI (Parent VSI) before created. The
191 	 * uplink VSI will check whether it had a VEB to switch packets. If no,
192 	 * it will try to create one. Then, uplink VSI will move the new VSI
193 	 * into its' sib_vsi_list to manage all the downlink VSI.
194 	 *  sib_vsi_list: the VSI list that shared the same uplink VSI.
195 	 *  parent_vsi  : the uplink VSI. It's NULL for main VSI.
196 	 *  veb         : the VEB associates with the VSI.
197 	 */
198 	struct ice_vsi_list sib_vsi_list; /* sibling vsi list */
199 	struct ice_vsi *parent_vsi;
200 	enum ice_vsi_type type; /* VSI types */
201 	uint16_t vlan_num;       /* Total VLAN number */
202 	uint16_t mac_num;        /* Total mac number */
203 	struct ice_mac_filter_list mac_list; /* macvlan filter list */
204 	struct ice_vlan_filter_list vlan_list; /* vlan filter list */
205 	uint16_t nb_qps;         /* Number of queue pairs VSI can occupy */
206 	uint16_t nb_used_qps;    /* Number of queue pairs VSI uses */
207 	uint16_t max_macaddrs;   /* Maximum number of MAC addresses */
208 	uint16_t base_queue;     /* The first queue index of this VSI */
209 	uint16_t vsi_id;         /* Hardware Id */
210 	uint16_t idx;            /* vsi_handle: SW index in hw->vsi_ctx */
211 	/* VF number to which the VSI connects, valid when VSI is VF type */
212 	uint8_t vf_num;
213 	uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
214 	uint16_t nb_msix;   /* The max number of msix vector */
215 	uint8_t enabled_tc; /* The traffic class enabled */
216 	uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
217 	uint8_t vlan_filter_on; /* The VLAN filter enabled */
218 	/* information about rss configuration */
219 	u32 rss_key_size;
220 	u32 rss_lut_size;
221 	uint8_t *rss_lut;
222 	uint8_t *rss_key;
223 	struct ice_eth_stats eth_stats_offset;
224 	struct ice_eth_stats eth_stats;
225 	bool offset_loaded;
226 };
227 
228 struct ice_pf {
229 	struct ice_adapter *adapter; /* The adapter this PF associate to */
230 	struct ice_vsi *main_vsi; /* pointer to main VSI structure */
231 	/* Used for next free software vsi idx.
232 	 * To save the effort, we don't recycle the index.
233 	 * Suppose the indexes are more than enough.
234 	 */
235 	uint16_t next_vsi_idx;
236 	uint16_t vsis_allocated;
237 	uint16_t vsis_unallocated;
238 	struct ice_res_pool_info qp_pool;    /*Queue pair pool */
239 	struct ice_res_pool_info msix_pool;  /* MSIX interrupt pool */
240 	struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
241 	struct ether_addr dev_addr; /* PF device mac address */
242 	uint64_t flags; /* PF feature flags */
243 	uint16_t hash_lut_size; /* The size of hash lookup table */
244 	uint16_t lan_nb_qp_max;
245 	uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
246 	struct ice_hw_port_stats stats_offset;
247 	struct ice_hw_port_stats stats;
248 	/* internal packet statistics, it should be excluded from the total */
249 	struct ice_eth_stats internal_stats_offset;
250 	struct ice_eth_stats internal_stats;
251 	bool offset_loaded;
252 	bool adapter_stopped;
253 };
254 
255 /**
256  * Structure to store private data for each PF/VF instance.
257  */
258 struct ice_adapter {
259 	/* Common for both PF and VF */
260 	struct ice_hw hw;
261 	struct rte_eth_dev *eth_dev;
262 	struct ice_pf pf;
263 	bool rx_bulk_alloc_allowed;
264 	bool tx_simple_allowed;
265 	/* ptype mapping table */
266 	uint32_t ptype_tbl[ICE_MAX_PKT_TYPE] __rte_cache_min_aligned;
267 };
268 
269 struct ice_vsi_vlan_pvid_info {
270 	uint16_t on;		/* Enable or disable pvid */
271 	union {
272 		uint16_t pvid;	/* Valid in case 'on' is set to set pvid */
273 		struct {
274 			/* Valid in case 'on' is cleared. 'tagged' will reject
275 			 * tagged packets, while 'untagged' will reject
276 			 * untagged packets.
277 			 */
278 			uint8_t tagged;
279 			uint8_t untagged;
280 		} reject;
281 	} config;
282 };
283 
284 #define ICE_DEV_TO_PCI(eth_dev) \
285 	RTE_DEV_TO_PCI((eth_dev)->device)
286 
287 /* ICE_DEV_PRIVATE_TO */
288 #define ICE_DEV_PRIVATE_TO_PF(adapter) \
289 	(&((struct ice_adapter *)adapter)->pf)
290 #define ICE_DEV_PRIVATE_TO_HW(adapter) \
291 	(&((struct ice_adapter *)adapter)->hw)
292 #define ICE_DEV_PRIVATE_TO_ADAPTER(adapter) \
293 	((struct ice_adapter *)adapter)
294 
295 /* ICE_VSI_TO */
296 #define ICE_VSI_TO_HW(vsi) \
297 	(&(((struct ice_vsi *)vsi)->adapter->hw))
298 #define ICE_VSI_TO_PF(vsi) \
299 	(&(((struct ice_vsi *)vsi)->adapter->pf))
300 #define ICE_VSI_TO_ETH_DEV(vsi) \
301 	(((struct ice_vsi *)vsi)->adapter->eth_dev)
302 
303 /* ICE_PF_TO */
304 #define ICE_PF_TO_HW(pf) \
305 	(&(((struct ice_pf *)pf)->adapter->hw))
306 #define ICE_PF_TO_ADAPTER(pf) \
307 	((struct ice_adapter *)(pf)->adapter)
308 #define ICE_PF_TO_ETH_DEV(pf) \
309 	(((struct ice_pf *)pf)->adapter->eth_dev)
310 
311 static inline int
312 ice_align_floor(int n)
313 {
314 	if (n == 0)
315 		return 0;
316 	return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
317 }
318 #endif /* _ICE_ETHDEV_H_ */
319