1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 5 #ifndef _ICE_ETHDEV_H_ 6 #define _ICE_ETHDEV_H_ 7 8 #include <rte_kvargs.h> 9 10 #include <ethdev_driver.h> 11 12 #include "base/ice_common.h" 13 #include "base/ice_adminq_cmd.h" 14 #include "base/ice_flow.h" 15 16 #define ICE_VLAN_TAG_SIZE 4 17 18 #define ICE_ADMINQ_LEN 32 19 #define ICE_SBIOQ_LEN 32 20 #define ICE_MAILBOXQ_LEN 32 21 #define ICE_ADMINQ_BUF_SZ 4096 22 #define ICE_SBIOQ_BUF_SZ 4096 23 #define ICE_MAILBOXQ_BUF_SZ 4096 24 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ 25 #define ICE_MAX_Q_PER_TC 64 26 #define ICE_NUM_DESC_DEFAULT 512 27 #define ICE_BUF_SIZE_MIN 1024 28 #define ICE_FRAME_SIZE_MAX 9728 29 #define ICE_QUEUE_BASE_ADDR_UNIT 128 30 /* number of VSIs and queue default setting */ 31 #define ICE_MAX_QP_NUM_PER_VF 16 32 #define ICE_DEFAULT_QP_NUM_FDIR 1 33 #define ICE_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) 34 #define ICE_VFTA_SIZE (4096 / ICE_UINT32_BIT_SIZE) 35 /* Maximun number of MAC addresses */ 36 #define ICE_NUM_MACADDR_MAX 64 37 /* Maximum number of VFs */ 38 #define ICE_MAX_VF 128 39 #define ICE_MAX_INTR_QUEUE_NUM 256 40 41 #define ICE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 42 #define ICE_RX_VEC_ID RTE_INTR_VEC_RXTX_OFFSET 43 44 #define ICE_MAX_PKT_TYPE 1024 45 46 /* DDP package search path */ 47 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg" 48 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg" 49 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/" 50 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/" 51 #define ICE_MAX_PKG_FILENAME_SIZE 256 52 53 #define MAX_ACL_NORMAL_ENTRIES 256 54 55 /** 56 * vlan_id is a 12 bit number. 57 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 58 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 59 * The higher 7 bit val specifies VFTA array index. 60 */ 61 #define ICE_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 62 #define ICE_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 63 64 /* Default TC traffic in case DCB is not enabled */ 65 #define ICE_DEFAULT_TCMAP 0x1 66 #define ICE_FDIR_QUEUE_ID 0 67 68 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ 69 #define ICE_VMDQ_POOL_BASE 1 70 71 #define ICE_DEFAULT_RX_FREE_THRESH 32 72 #define ICE_DEFAULT_RX_PTHRESH 8 73 #define ICE_DEFAULT_RX_HTHRESH 8 74 #define ICE_DEFAULT_RX_WTHRESH 0 75 76 #define ICE_DEFAULT_TX_FREE_THRESH 32 77 #define ICE_DEFAULT_TX_PTHRESH 32 78 #define ICE_DEFAULT_TX_HTHRESH 0 79 #define ICE_DEFAULT_TX_WTHRESH 0 80 #define ICE_DEFAULT_TX_RSBIT_THRESH 32 81 82 /* Bit shift and mask */ 83 #define ICE_4_BIT_WIDTH (CHAR_BIT / 2) 84 #define ICE_4_BIT_MASK RTE_LEN2MASK(ICE_4_BIT_WIDTH, uint8_t) 85 #define ICE_8_BIT_WIDTH CHAR_BIT 86 #define ICE_8_BIT_MASK UINT8_MAX 87 #define ICE_16_BIT_WIDTH (CHAR_BIT * 2) 88 #define ICE_16_BIT_MASK UINT16_MAX 89 #define ICE_32_BIT_WIDTH (CHAR_BIT * 4) 90 #define ICE_32_BIT_MASK UINT32_MAX 91 #define ICE_40_BIT_WIDTH (CHAR_BIT * 5) 92 #define ICE_40_BIT_MASK RTE_LEN2MASK(ICE_40_BIT_WIDTH, uint64_t) 93 #define ICE_48_BIT_WIDTH (CHAR_BIT * 6) 94 #define ICE_48_BIT_MASK RTE_LEN2MASK(ICE_48_BIT_WIDTH, uint64_t) 95 96 #define ICE_FLAG_RSS BIT_ULL(0) 97 #define ICE_FLAG_DCB BIT_ULL(1) 98 #define ICE_FLAG_VMDQ BIT_ULL(2) 99 #define ICE_FLAG_SRIOV BIT_ULL(3) 100 #define ICE_FLAG_HEADER_SPLIT_DISABLED BIT_ULL(4) 101 #define ICE_FLAG_HEADER_SPLIT_ENABLED BIT_ULL(5) 102 #define ICE_FLAG_FDIR BIT_ULL(6) 103 #define ICE_FLAG_VXLAN BIT_ULL(7) 104 #define ICE_FLAG_RSS_AQ_CAPABLE BIT_ULL(8) 105 #define ICE_FLAG_VF_MAC_BY_PF BIT_ULL(9) 106 #define ICE_FLAG_ALL (ICE_FLAG_RSS | \ 107 ICE_FLAG_DCB | \ 108 ICE_FLAG_VMDQ | \ 109 ICE_FLAG_SRIOV | \ 110 ICE_FLAG_HEADER_SPLIT_DISABLED | \ 111 ICE_FLAG_HEADER_SPLIT_ENABLED | \ 112 ICE_FLAG_FDIR | \ 113 ICE_FLAG_VXLAN | \ 114 ICE_FLAG_RSS_AQ_CAPABLE | \ 115 ICE_FLAG_VF_MAC_BY_PF) 116 117 #define ICE_RSS_OFFLOAD_ALL ( \ 118 ETH_RSS_IPV4 | \ 119 ETH_RSS_FRAG_IPV4 | \ 120 ETH_RSS_NONFRAG_IPV4_TCP | \ 121 ETH_RSS_NONFRAG_IPV4_UDP | \ 122 ETH_RSS_NONFRAG_IPV4_SCTP | \ 123 ETH_RSS_NONFRAG_IPV4_OTHER | \ 124 ETH_RSS_IPV6 | \ 125 ETH_RSS_FRAG_IPV6 | \ 126 ETH_RSS_NONFRAG_IPV6_TCP | \ 127 ETH_RSS_NONFRAG_IPV6_UDP | \ 128 ETH_RSS_NONFRAG_IPV6_SCTP | \ 129 ETH_RSS_NONFRAG_IPV6_OTHER | \ 130 ETH_RSS_L2_PAYLOAD) 131 132 /** 133 * The overhead from MTU to max frame size. 134 * Considering QinQ packet, the VLAN tag needs to be counted twice. 135 */ 136 #define ICE_ETH_OVERHEAD \ 137 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE * 2) 138 #define ICE_ETH_MAX_LEN (RTE_ETHER_MTU + ICE_ETH_OVERHEAD) 139 140 #define ICE_RXTX_BYTES_HIGH(bytes) ((bytes) & ~ICE_40_BIT_MASK) 141 #define ICE_RXTX_BYTES_LOW(bytes) ((bytes) & ICE_40_BIT_MASK) 142 143 /* Max number of flexible descriptor rxdid */ 144 #define ICE_FLEX_DESC_RXDID_MAX_NUM 64 145 146 /* Per-channel register definitions */ 147 #define GLTSYN_AUX_OUT(_chan, _idx) (GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8)) 148 #define GLTSYN_CLKO(_chan, _idx) (GLTSYN_CLKO_0(_idx) + ((_chan) * 8)) 149 #define GLTSYN_TGT_L(_chan, _idx) (GLTSYN_TGT_L_0(_idx) + ((_chan) * 16)) 150 #define GLTSYN_TGT_H(_chan, _idx) (GLTSYN_TGT_H_0(_idx) + ((_chan) * 16)) 151 152 /* DDP package type */ 153 enum ice_pkg_type { 154 ICE_PKG_TYPE_UNKNOWN, 155 ICE_PKG_TYPE_OS_DEFAULT, 156 ICE_PKG_TYPE_COMMS, 157 }; 158 159 enum pps_type { 160 PPS_NONE, 161 PPS_PIN, 162 PPS_MAX, 163 }; 164 165 struct ice_adapter; 166 167 /** 168 * MAC filter structure 169 */ 170 struct ice_mac_filter_info { 171 struct rte_ether_addr mac_addr; 172 }; 173 174 TAILQ_HEAD(ice_mac_filter_list, ice_mac_filter); 175 176 /* MAC filter list structure */ 177 struct ice_mac_filter { 178 TAILQ_ENTRY(ice_mac_filter) next; 179 struct ice_mac_filter_info mac_info; 180 }; 181 182 struct ice_vlan { 183 uint16_t tpid; 184 uint16_t vid; 185 }; 186 187 #define ICE_VLAN(tpid, vid) \ 188 ((struct ice_vlan){ tpid, vid }) 189 190 /** 191 * VLAN filter structure 192 */ 193 struct ice_vlan_filter_info { 194 struct ice_vlan vlan; 195 }; 196 197 TAILQ_HEAD(ice_vlan_filter_list, ice_vlan_filter); 198 199 /* VLAN filter list structure */ 200 struct ice_vlan_filter { 201 TAILQ_ENTRY(ice_vlan_filter) next; 202 struct ice_vlan_filter_info vlan_info; 203 }; 204 205 struct pool_entry { 206 LIST_ENTRY(pool_entry) next; 207 uint16_t base; 208 uint16_t len; 209 }; 210 211 LIST_HEAD(res_list, pool_entry); 212 213 struct ice_res_pool_info { 214 uint32_t base; /* Resource start index */ 215 uint32_t num_alloc; /* Allocated resource number */ 216 uint32_t num_free; /* Total available resource number */ 217 struct res_list alloc_list; /* Allocated resource list */ 218 struct res_list free_list; /* Available resource list */ 219 }; 220 221 TAILQ_HEAD(ice_vsi_list_head, ice_vsi_list); 222 223 struct ice_vsi; 224 225 /* VSI list structure */ 226 struct ice_vsi_list { 227 TAILQ_ENTRY(ice_vsi_list) list; 228 struct ice_vsi *vsi; 229 }; 230 231 struct ice_rx_queue; 232 struct ice_tx_queue; 233 234 /** 235 * Structure that defines a VSI, associated with a adapter. 236 */ 237 struct ice_vsi { 238 struct ice_adapter *adapter; /* Backreference to associated adapter */ 239 struct ice_aqc_vsi_props info; /* VSI properties */ 240 /** 241 * When drivers loaded, only a default main VSI exists. In case new VSI 242 * needs to add, HW needs to know the layout that VSIs are organized. 243 * Besides that, VSI isan element and can't switch packets, which needs 244 * to add new component VEB to perform switching. So, a new VSI needs 245 * to specify the the uplink VSI (Parent VSI) before created. The 246 * uplink VSI will check whether it had a VEB to switch packets. If no, 247 * it will try to create one. Then, uplink VSI will move the new VSI 248 * into its' sib_vsi_list to manage all the downlink VSI. 249 * sib_vsi_list: the VSI list that shared the same uplink VSI. 250 * parent_vsi : the uplink VSI. It's NULL for main VSI. 251 * veb : the VEB associates with the VSI. 252 */ 253 struct ice_vsi_list sib_vsi_list; /* sibling vsi list */ 254 struct ice_vsi *parent_vsi; 255 enum ice_vsi_type type; /* VSI types */ 256 uint16_t vlan_num; /* Total VLAN number */ 257 uint16_t mac_num; /* Total mac number */ 258 struct ice_mac_filter_list mac_list; /* macvlan filter list */ 259 struct ice_vlan_filter_list vlan_list; /* vlan filter list */ 260 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ 261 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ 262 uint16_t max_macaddrs; /* Maximum number of MAC addresses */ 263 uint16_t base_queue; /* The first queue index of this VSI */ 264 uint16_t vsi_id; /* Hardware Id */ 265 uint16_t idx; /* vsi_handle: SW index in hw->vsi_ctx */ 266 /* VF number to which the VSI connects, valid when VSI is VF type */ 267 uint8_t vf_num; 268 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ 269 uint16_t nb_msix; /* The max number of msix vector */ 270 uint8_t enabled_tc; /* The traffic class enabled */ 271 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ 272 uint8_t vlan_filter_on; /* The VLAN filter enabled */ 273 /* information about rss configuration */ 274 u32 rss_key_size; 275 u32 rss_lut_size; 276 uint8_t *rss_lut; 277 uint8_t *rss_key; 278 struct ice_eth_stats eth_stats_offset; 279 struct ice_eth_stats eth_stats; 280 bool offset_loaded; 281 uint64_t old_rx_bytes; 282 uint64_t old_tx_bytes; 283 }; 284 285 enum proto_xtr_type { 286 PROTO_XTR_NONE, 287 PROTO_XTR_VLAN, 288 PROTO_XTR_IPV4, 289 PROTO_XTR_IPV6, 290 PROTO_XTR_IPV6_FLOW, 291 PROTO_XTR_TCP, 292 PROTO_XTR_IP_OFFSET, 293 PROTO_XTR_MAX /* The last one */ 294 }; 295 296 enum ice_fdir_tunnel_type { 297 ICE_FDIR_TUNNEL_TYPE_NONE = 0, 298 ICE_FDIR_TUNNEL_TYPE_VXLAN, 299 ICE_FDIR_TUNNEL_TYPE_GTPU, 300 ICE_FDIR_TUNNEL_TYPE_GTPU_EH, 301 }; 302 303 struct rte_flow; 304 TAILQ_HEAD(ice_flow_list, rte_flow); 305 306 struct ice_flow_parser_node; 307 TAILQ_HEAD(ice_parser_list, ice_flow_parser_node); 308 309 struct ice_fdir_filter_conf { 310 struct ice_fdir_fltr input; 311 enum ice_fdir_tunnel_type tunnel_type; 312 313 struct ice_fdir_counter *counter; /* flow specific counter context */ 314 struct rte_flow_action_count act_count; 315 316 uint64_t input_set_o; /* used for non-tunnel or tunnel outer fields */ 317 uint64_t input_set_i; /* only for tunnel inner fields */ 318 uint32_t mark_flag; 319 }; 320 321 #define ICE_MAX_FDIR_FILTER_NUM (1024 * 16) 322 323 struct ice_fdir_fltr_pattern { 324 enum ice_fltr_ptype flow_type; 325 326 union { 327 struct ice_fdir_v4 v4; 328 struct ice_fdir_v6 v6; 329 } ip, mask; 330 331 struct ice_fdir_udp_gtp gtpu_data; 332 struct ice_fdir_udp_gtp gtpu_mask; 333 334 struct ice_fdir_extra ext_data; 335 struct ice_fdir_extra ext_mask; 336 337 enum ice_fdir_tunnel_type tunnel_type; 338 }; 339 340 #define ICE_FDIR_COUNTER_DEFAULT_POOL_SIZE 1 341 #define ICE_FDIR_COUNTER_MAX_POOL_SIZE 32 342 #define ICE_FDIR_COUNTERS_PER_BLOCK 256 343 #define ICE_FDIR_COUNTER_INDEX(base_idx) \ 344 ((base_idx) * ICE_FDIR_COUNTERS_PER_BLOCK) 345 struct ice_fdir_counter_pool; 346 347 struct ice_fdir_counter { 348 TAILQ_ENTRY(ice_fdir_counter) next; 349 struct ice_fdir_counter_pool *pool; 350 uint8_t shared; 351 uint32_t ref_cnt; 352 uint32_t id; 353 uint64_t hits; 354 uint64_t bytes; 355 uint32_t hw_index; 356 }; 357 358 TAILQ_HEAD(ice_fdir_counter_list, ice_fdir_counter); 359 360 struct ice_fdir_counter_pool { 361 TAILQ_ENTRY(ice_fdir_counter_pool) next; 362 struct ice_fdir_counter_list counter_list; 363 struct ice_fdir_counter counters[0]; 364 }; 365 366 TAILQ_HEAD(ice_fdir_counter_pool_list, ice_fdir_counter_pool); 367 368 struct ice_fdir_counter_pool_container { 369 struct ice_fdir_counter_pool_list pool_list; 370 struct ice_fdir_counter_pool *pools[ICE_FDIR_COUNTER_MAX_POOL_SIZE]; 371 uint8_t index_free; 372 }; 373 374 /** 375 * A structure used to define fields of a FDIR related info. 376 */ 377 struct ice_fdir_info { 378 struct ice_vsi *fdir_vsi; /* pointer to fdir VSI structure */ 379 struct ice_tx_queue *txq; 380 struct ice_rx_queue *rxq; 381 void *prg_pkt; /* memory for fdir program packet */ 382 uint64_t dma_addr; /* physic address of packet memory*/ 383 const struct rte_memzone *mz; 384 struct ice_fdir_filter_conf conf; 385 386 struct ice_fdir_filter_conf **hash_map; 387 struct rte_hash *hash_table; 388 389 struct ice_fdir_counter_pool_container counter; 390 }; 391 392 #define ICE_HASH_GTPU_CTX_EH_IP 0 393 #define ICE_HASH_GTPU_CTX_EH_IP_UDP 1 394 #define ICE_HASH_GTPU_CTX_EH_IP_TCP 2 395 #define ICE_HASH_GTPU_CTX_UP_IP 3 396 #define ICE_HASH_GTPU_CTX_UP_IP_UDP 4 397 #define ICE_HASH_GTPU_CTX_UP_IP_TCP 5 398 #define ICE_HASH_GTPU_CTX_DW_IP 6 399 #define ICE_HASH_GTPU_CTX_DW_IP_UDP 7 400 #define ICE_HASH_GTPU_CTX_DW_IP_TCP 8 401 #define ICE_HASH_GTPU_CTX_MAX 9 402 403 struct ice_hash_gtpu_ctx { 404 struct ice_rss_hash_cfg ctx[ICE_HASH_GTPU_CTX_MAX]; 405 }; 406 407 struct ice_hash_ctx { 408 struct ice_hash_gtpu_ctx gtpu4; 409 struct ice_hash_gtpu_ctx gtpu6; 410 }; 411 412 struct ice_acl_conf { 413 struct ice_fdir_fltr input; 414 uint64_t input_set; 415 }; 416 417 /** 418 * A structure used to define fields of ACL related info. 419 */ 420 struct ice_acl_info { 421 struct ice_acl_conf conf; 422 struct rte_bitmap *slots; 423 uint64_t hw_entry_id[MAX_ACL_NORMAL_ENTRIES]; 424 }; 425 426 struct ice_pf { 427 struct ice_adapter *adapter; /* The adapter this PF associate to */ 428 struct ice_vsi *main_vsi; /* pointer to main VSI structure */ 429 /* Used for next free software vsi idx. 430 * To save the effort, we don't recycle the index. 431 * Suppose the indexes are more than enough. 432 */ 433 uint16_t next_vsi_idx; 434 uint16_t vsis_allocated; 435 uint16_t vsis_unallocated; 436 struct ice_res_pool_info qp_pool; /*Queue pair pool */ 437 struct ice_res_pool_info msix_pool; /* MSIX interrupt pool */ 438 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 439 struct rte_ether_addr dev_addr; /* PF device mac address */ 440 uint64_t flags; /* PF feature flags */ 441 uint16_t hash_lut_size; /* The size of hash lookup table */ 442 uint16_t lan_nb_qp_max; 443 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ 444 uint16_t base_queue; /* The base queue pairs index in the device */ 445 uint8_t *proto_xtr; /* Protocol extraction type for all queues */ 446 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ 447 uint16_t fdir_qp_offset; 448 struct ice_fdir_info fdir; /* flow director info */ 449 struct ice_acl_info acl; /* ACL info */ 450 struct ice_hash_ctx hash_ctx; 451 uint16_t hw_prof_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX]; 452 uint16_t fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX]; 453 struct ice_hw_port_stats stats_offset; 454 struct ice_hw_port_stats stats; 455 /* internal packet statistics, it should be excluded from the total */ 456 struct ice_eth_stats internal_stats_offset; 457 struct ice_eth_stats internal_stats; 458 bool offset_loaded; 459 bool adapter_stopped; 460 struct ice_flow_list flow_list; 461 rte_spinlock_t flow_ops_lock; 462 struct ice_parser_list rss_parser_list; 463 struct ice_parser_list perm_parser_list; 464 struct ice_parser_list dist_parser_list; 465 bool init_link_up; 466 uint64_t old_rx_bytes; 467 uint64_t old_tx_bytes; 468 uint64_t supported_rxdid; /* bitmap for supported RXDID */ 469 uint64_t rss_hf; 470 }; 471 472 #define ICE_MAX_QUEUE_NUM 2048 473 #define ICE_MAX_PIN_NUM 4 474 475 /** 476 * Cache devargs parse result. 477 */ 478 struct ice_devargs { 479 int safe_mode_support; 480 uint8_t proto_xtr_dflt; 481 int pipe_mode_support; 482 uint8_t proto_xtr[ICE_MAX_QUEUE_NUM]; 483 uint8_t pin_idx; 484 uint8_t pps_out_ena; 485 }; 486 487 /** 488 * Structure to store private data for each PF/VF instance. 489 */ 490 struct ice_adapter { 491 /* Common for both PF and VF */ 492 struct ice_hw hw; 493 struct ice_pf pf; 494 bool rx_bulk_alloc_allowed; 495 bool rx_vec_allowed; 496 bool tx_vec_allowed; 497 bool tx_simple_allowed; 498 /* ptype mapping table */ 499 uint32_t ptype_tbl[ICE_MAX_PKT_TYPE] __rte_cache_min_aligned; 500 bool is_safe_mode; 501 struct ice_devargs devargs; 502 enum ice_pkg_type active_pkg_type; /* loaded ddp package type */ 503 uint16_t fdir_ref_cnt; 504 #ifdef RTE_ARCH_X86 505 bool rx_use_avx2; 506 bool rx_use_avx512; 507 bool tx_use_avx2; 508 bool tx_use_avx512; 509 #endif 510 }; 511 512 struct ice_vsi_vlan_pvid_info { 513 uint16_t on; /* Enable or disable pvid */ 514 union { 515 uint16_t pvid; /* Valid in case 'on' is set to set pvid */ 516 struct { 517 /* Valid in case 'on' is cleared. 'tagged' will reject 518 * tagged packets, while 'untagged' will reject 519 * untagged packets. 520 */ 521 uint8_t tagged; 522 uint8_t untagged; 523 } reject; 524 } config; 525 }; 526 527 #define ICE_DEV_TO_PCI(eth_dev) \ 528 RTE_DEV_TO_PCI((eth_dev)->device) 529 530 /* ICE_DEV_PRIVATE_TO */ 531 #define ICE_DEV_PRIVATE_TO_PF(adapter) \ 532 (&((struct ice_adapter *)adapter)->pf) 533 #define ICE_DEV_PRIVATE_TO_HW(adapter) \ 534 (&((struct ice_adapter *)adapter)->hw) 535 #define ICE_DEV_PRIVATE_TO_ADAPTER(adapter) \ 536 ((struct ice_adapter *)adapter) 537 538 /* ICE_VSI_TO */ 539 #define ICE_VSI_TO_HW(vsi) \ 540 (&(((struct ice_vsi *)vsi)->adapter->hw)) 541 #define ICE_VSI_TO_PF(vsi) \ 542 (&(((struct ice_vsi *)vsi)->adapter->pf)) 543 544 /* ICE_PF_TO */ 545 #define ICE_PF_TO_HW(pf) \ 546 (&(((struct ice_pf *)pf)->adapter->hw)) 547 #define ICE_PF_TO_ADAPTER(pf) \ 548 ((struct ice_adapter *)(pf)->adapter) 549 #define ICE_PF_TO_ETH_DEV(pf) \ 550 (((struct ice_pf *)pf)->adapter->eth_dev) 551 552 int 553 ice_load_pkg(struct ice_adapter *adapter, bool use_dsn, uint64_t dsn); 554 struct ice_vsi * 555 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type); 556 int 557 ice_release_vsi(struct ice_vsi *vsi); 558 void ice_vsi_enable_queues_intr(struct ice_vsi *vsi); 559 void ice_vsi_disable_queues_intr(struct ice_vsi *vsi); 560 void ice_vsi_queues_bind_intr(struct ice_vsi *vsi); 561 int ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, 562 struct ice_rss_hash_cfg *cfg); 563 int ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, 564 struct ice_rss_hash_cfg *cfg); 565 566 static inline int 567 ice_align_floor(int n) 568 { 569 if (n == 0) 570 return 0; 571 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); 572 } 573 574 #define ICE_PHY_TYPE_SUPPORT_50G(phy_type) \ 575 (((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CR2) || \ 576 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR2) || \ 577 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR2) || \ 578 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR2) || \ 579 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC) || \ 580 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2) || \ 581 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC) || \ 582 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2) || \ 583 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CP) || \ 584 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR) || \ 585 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_FR) || \ 586 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR) || \ 587 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4) || \ 588 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC) || \ 589 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1)) 590 591 #define ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type) \ 592 (((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR4) || \ 593 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR4) || \ 594 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_LR4) || \ 595 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR4) || \ 596 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC) || \ 597 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4) || \ 598 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC) || \ 599 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4) || \ 600 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4) || \ 601 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4) || \ 602 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CP2) || \ 603 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR2) || \ 604 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_DR)) 605 606 #define ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type) \ 607 (((phy_type) & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) || \ 608 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC) || \ 609 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2) || \ 610 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC) || \ 611 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2)) 612 613 #endif /* _ICE_ETHDEV_H_ */ 614