1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 5 #ifndef _ICE_ETHDEV_H_ 6 #define _ICE_ETHDEV_H_ 7 8 #include <rte_kvargs.h> 9 10 #include <rte_ethdev_driver.h> 11 12 #include "base/ice_common.h" 13 #include "base/ice_adminq_cmd.h" 14 15 #define ICE_VLAN_TAG_SIZE 4 16 17 #define ICE_ADMINQ_LEN 32 18 #define ICE_SBIOQ_LEN 32 19 #define ICE_MAILBOXQ_LEN 32 20 #define ICE_ADMINQ_BUF_SZ 4096 21 #define ICE_SBIOQ_BUF_SZ 4096 22 #define ICE_MAILBOXQ_BUF_SZ 4096 23 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ 24 #define ICE_MAX_Q_PER_TC 64 25 #define ICE_NUM_DESC_DEFAULT 512 26 #define ICE_BUF_SIZE_MIN 1024 27 #define ICE_FRAME_SIZE_MAX 9728 28 #define ICE_QUEUE_BASE_ADDR_UNIT 128 29 /* number of VSIs and queue default setting */ 30 #define ICE_MAX_QP_NUM_PER_VF 16 31 #define ICE_DEFAULT_QP_NUM_FDIR 1 32 #define ICE_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) 33 #define ICE_VFTA_SIZE (4096 / ICE_UINT32_BIT_SIZE) 34 /* Maximun number of MAC addresses */ 35 #define ICE_NUM_MACADDR_MAX 64 36 /* Maximum number of VFs */ 37 #define ICE_MAX_VF 128 38 #define ICE_MAX_INTR_QUEUE_NUM 256 39 40 #define ICE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 41 #define ICE_RX_VEC_ID RTE_INTR_VEC_RXTX_OFFSET 42 43 #define ICE_MAX_PKT_TYPE 1024 44 45 /* DDP package search path */ 46 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg" 47 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg" 48 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/" 49 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/" 50 #define ICE_MAX_PKG_FILENAME_SIZE 256 51 52 /** 53 * vlan_id is a 12 bit number. 54 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 55 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 56 * The higher 7 bit val specifies VFTA array index. 57 */ 58 #define ICE_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 59 #define ICE_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 60 61 /* Default TC traffic in case DCB is not enabled */ 62 #define ICE_DEFAULT_TCMAP 0x1 63 #define ICE_FDIR_QUEUE_ID 0 64 65 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ 66 #define ICE_VMDQ_POOL_BASE 1 67 68 #define ICE_DEFAULT_RX_FREE_THRESH 32 69 #define ICE_DEFAULT_RX_PTHRESH 8 70 #define ICE_DEFAULT_RX_HTHRESH 8 71 #define ICE_DEFAULT_RX_WTHRESH 0 72 73 #define ICE_DEFAULT_TX_FREE_THRESH 32 74 #define ICE_DEFAULT_TX_PTHRESH 32 75 #define ICE_DEFAULT_TX_HTHRESH 0 76 #define ICE_DEFAULT_TX_WTHRESH 0 77 #define ICE_DEFAULT_TX_RSBIT_THRESH 32 78 79 /* Bit shift and mask */ 80 #define ICE_4_BIT_WIDTH (CHAR_BIT / 2) 81 #define ICE_4_BIT_MASK RTE_LEN2MASK(ICE_4_BIT_WIDTH, uint8_t) 82 #define ICE_8_BIT_WIDTH CHAR_BIT 83 #define ICE_8_BIT_MASK UINT8_MAX 84 #define ICE_16_BIT_WIDTH (CHAR_BIT * 2) 85 #define ICE_16_BIT_MASK UINT16_MAX 86 #define ICE_32_BIT_WIDTH (CHAR_BIT * 4) 87 #define ICE_32_BIT_MASK UINT32_MAX 88 #define ICE_40_BIT_WIDTH (CHAR_BIT * 5) 89 #define ICE_40_BIT_MASK RTE_LEN2MASK(ICE_40_BIT_WIDTH, uint64_t) 90 #define ICE_48_BIT_WIDTH (CHAR_BIT * 6) 91 #define ICE_48_BIT_MASK RTE_LEN2MASK(ICE_48_BIT_WIDTH, uint64_t) 92 93 #define ICE_FLAG_RSS BIT_ULL(0) 94 #define ICE_FLAG_DCB BIT_ULL(1) 95 #define ICE_FLAG_VMDQ BIT_ULL(2) 96 #define ICE_FLAG_SRIOV BIT_ULL(3) 97 #define ICE_FLAG_HEADER_SPLIT_DISABLED BIT_ULL(4) 98 #define ICE_FLAG_HEADER_SPLIT_ENABLED BIT_ULL(5) 99 #define ICE_FLAG_FDIR BIT_ULL(6) 100 #define ICE_FLAG_VXLAN BIT_ULL(7) 101 #define ICE_FLAG_RSS_AQ_CAPABLE BIT_ULL(8) 102 #define ICE_FLAG_VF_MAC_BY_PF BIT_ULL(9) 103 #define ICE_FLAG_ALL (ICE_FLAG_RSS | \ 104 ICE_FLAG_DCB | \ 105 ICE_FLAG_VMDQ | \ 106 ICE_FLAG_SRIOV | \ 107 ICE_FLAG_HEADER_SPLIT_DISABLED | \ 108 ICE_FLAG_HEADER_SPLIT_ENABLED | \ 109 ICE_FLAG_FDIR | \ 110 ICE_FLAG_VXLAN | \ 111 ICE_FLAG_RSS_AQ_CAPABLE | \ 112 ICE_FLAG_VF_MAC_BY_PF) 113 114 #define ICE_RSS_OFFLOAD_ALL ( \ 115 ETH_RSS_IPV4 | \ 116 ETH_RSS_FRAG_IPV4 | \ 117 ETH_RSS_NONFRAG_IPV4_TCP | \ 118 ETH_RSS_NONFRAG_IPV4_UDP | \ 119 ETH_RSS_NONFRAG_IPV4_SCTP | \ 120 ETH_RSS_NONFRAG_IPV4_OTHER | \ 121 ETH_RSS_IPV6 | \ 122 ETH_RSS_FRAG_IPV6 | \ 123 ETH_RSS_NONFRAG_IPV6_TCP | \ 124 ETH_RSS_NONFRAG_IPV6_UDP | \ 125 ETH_RSS_NONFRAG_IPV6_SCTP | \ 126 ETH_RSS_NONFRAG_IPV6_OTHER | \ 127 ETH_RSS_L2_PAYLOAD) 128 129 /** 130 * The overhead from MTU to max frame size. 131 * Considering QinQ packet, the VLAN tag needs to be counted twice. 132 */ 133 #define ICE_ETH_OVERHEAD \ 134 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE * 2) 135 136 #define ICE_RXTX_BYTES_HIGH(bytes) ((bytes) & ~ICE_40_BIT_MASK) 137 #define ICE_RXTX_BYTES_LOW(bytes) ((bytes) & ICE_40_BIT_MASK) 138 139 /* Max number of flexible descriptor rxdid */ 140 #define ICE_FLEX_DESC_RXDID_MAX_NUM 64 141 142 /* DDP package type */ 143 enum ice_pkg_type { 144 ICE_PKG_TYPE_UNKNOWN, 145 ICE_PKG_TYPE_OS_DEFAULT, 146 ICE_PKG_TYPE_COMMS, 147 }; 148 149 struct ice_adapter; 150 151 /** 152 * MAC filter structure 153 */ 154 struct ice_mac_filter_info { 155 struct rte_ether_addr mac_addr; 156 }; 157 158 TAILQ_HEAD(ice_mac_filter_list, ice_mac_filter); 159 160 /* MAC filter list structure */ 161 struct ice_mac_filter { 162 TAILQ_ENTRY(ice_mac_filter) next; 163 struct ice_mac_filter_info mac_info; 164 }; 165 166 /** 167 * VLAN filter structure 168 */ 169 struct ice_vlan_filter_info { 170 uint16_t vlan_id; 171 }; 172 173 TAILQ_HEAD(ice_vlan_filter_list, ice_vlan_filter); 174 175 /* VLAN filter list structure */ 176 struct ice_vlan_filter { 177 TAILQ_ENTRY(ice_vlan_filter) next; 178 struct ice_vlan_filter_info vlan_info; 179 }; 180 181 struct pool_entry { 182 LIST_ENTRY(pool_entry) next; 183 uint16_t base; 184 uint16_t len; 185 }; 186 187 LIST_HEAD(res_list, pool_entry); 188 189 struct ice_res_pool_info { 190 uint32_t base; /* Resource start index */ 191 uint32_t num_alloc; /* Allocated resource number */ 192 uint32_t num_free; /* Total available resource number */ 193 struct res_list alloc_list; /* Allocated resource list */ 194 struct res_list free_list; /* Available resource list */ 195 }; 196 197 TAILQ_HEAD(ice_vsi_list_head, ice_vsi_list); 198 199 struct ice_vsi; 200 201 /* VSI list structure */ 202 struct ice_vsi_list { 203 TAILQ_ENTRY(ice_vsi_list) list; 204 struct ice_vsi *vsi; 205 }; 206 207 struct ice_rx_queue; 208 struct ice_tx_queue; 209 210 /** 211 * Structure that defines a VSI, associated with a adapter. 212 */ 213 struct ice_vsi { 214 struct ice_adapter *adapter; /* Backreference to associated adapter */ 215 struct ice_aqc_vsi_props info; /* VSI properties */ 216 /** 217 * When drivers loaded, only a default main VSI exists. In case new VSI 218 * needs to add, HW needs to know the layout that VSIs are organized. 219 * Besides that, VSI isan element and can't switch packets, which needs 220 * to add new component VEB to perform switching. So, a new VSI needs 221 * to specify the the uplink VSI (Parent VSI) before created. The 222 * uplink VSI will check whether it had a VEB to switch packets. If no, 223 * it will try to create one. Then, uplink VSI will move the new VSI 224 * into its' sib_vsi_list to manage all the downlink VSI. 225 * sib_vsi_list: the VSI list that shared the same uplink VSI. 226 * parent_vsi : the uplink VSI. It's NULL for main VSI. 227 * veb : the VEB associates with the VSI. 228 */ 229 struct ice_vsi_list sib_vsi_list; /* sibling vsi list */ 230 struct ice_vsi *parent_vsi; 231 enum ice_vsi_type type; /* VSI types */ 232 uint16_t vlan_num; /* Total VLAN number */ 233 uint16_t mac_num; /* Total mac number */ 234 struct ice_mac_filter_list mac_list; /* macvlan filter list */ 235 struct ice_vlan_filter_list vlan_list; /* vlan filter list */ 236 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ 237 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ 238 uint16_t max_macaddrs; /* Maximum number of MAC addresses */ 239 uint16_t base_queue; /* The first queue index of this VSI */ 240 uint16_t vsi_id; /* Hardware Id */ 241 uint16_t idx; /* vsi_handle: SW index in hw->vsi_ctx */ 242 /* VF number to which the VSI connects, valid when VSI is VF type */ 243 uint8_t vf_num; 244 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ 245 uint16_t nb_msix; /* The max number of msix vector */ 246 uint8_t enabled_tc; /* The traffic class enabled */ 247 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ 248 uint8_t vlan_filter_on; /* The VLAN filter enabled */ 249 /* information about rss configuration */ 250 u32 rss_key_size; 251 u32 rss_lut_size; 252 uint8_t *rss_lut; 253 uint8_t *rss_key; 254 struct ice_eth_stats eth_stats_offset; 255 struct ice_eth_stats eth_stats; 256 bool offset_loaded; 257 uint64_t old_rx_bytes; 258 uint64_t old_tx_bytes; 259 }; 260 261 enum proto_xtr_type { 262 PROTO_XTR_NONE, 263 PROTO_XTR_VLAN, 264 PROTO_XTR_IPV4, 265 PROTO_XTR_IPV6, 266 PROTO_XTR_IPV6_FLOW, 267 PROTO_XTR_TCP, 268 PROTO_XTR_IP_OFFSET, 269 PROTO_XTR_MAX /* The last one */ 270 }; 271 272 enum ice_fdir_tunnel_type { 273 ICE_FDIR_TUNNEL_TYPE_NONE = 0, 274 ICE_FDIR_TUNNEL_TYPE_VXLAN, 275 ICE_FDIR_TUNNEL_TYPE_GTPU, 276 ICE_FDIR_TUNNEL_TYPE_GTPU_EH, 277 }; 278 279 struct rte_flow; 280 TAILQ_HEAD(ice_flow_list, rte_flow); 281 282 struct ice_flow_parser_node; 283 TAILQ_HEAD(ice_parser_list, ice_flow_parser_node); 284 285 struct ice_fdir_filter_conf { 286 struct ice_fdir_fltr input; 287 enum ice_fdir_tunnel_type tunnel_type; 288 289 struct ice_fdir_counter *counter; /* flow specific counter context */ 290 struct rte_flow_action_count act_count; 291 292 uint64_t input_set; 293 uint64_t outer_input_set; /* only for tunnel packets outer fields */ 294 uint32_t mark_flag; 295 }; 296 297 #define ICE_MAX_FDIR_FILTER_NUM (1024 * 16) 298 299 struct ice_fdir_fltr_pattern { 300 enum ice_fltr_ptype flow_type; 301 302 union { 303 struct ice_fdir_v4 v4; 304 struct ice_fdir_v6 v6; 305 } ip, mask; 306 307 struct ice_fdir_udp_gtp gtpu_data; 308 struct ice_fdir_udp_gtp gtpu_mask; 309 310 struct ice_fdir_extra ext_data; 311 struct ice_fdir_extra ext_mask; 312 313 enum ice_fdir_tunnel_type tunnel_type; 314 }; 315 316 #define ICE_FDIR_COUNTER_DEFAULT_POOL_SIZE 1 317 #define ICE_FDIR_COUNTER_MAX_POOL_SIZE 32 318 #define ICE_FDIR_COUNTERS_PER_BLOCK 256 319 #define ICE_FDIR_COUNTER_INDEX(base_idx) \ 320 ((base_idx) * ICE_FDIR_COUNTERS_PER_BLOCK) 321 struct ice_fdir_counter_pool; 322 323 struct ice_fdir_counter { 324 TAILQ_ENTRY(ice_fdir_counter) next; 325 struct ice_fdir_counter_pool *pool; 326 uint8_t shared; 327 uint32_t ref_cnt; 328 uint32_t id; 329 uint64_t hits; 330 uint64_t bytes; 331 uint32_t hw_index; 332 }; 333 334 TAILQ_HEAD(ice_fdir_counter_list, ice_fdir_counter); 335 336 struct ice_fdir_counter_pool { 337 TAILQ_ENTRY(ice_fdir_counter_pool) next; 338 struct ice_fdir_counter_list counter_list; 339 struct ice_fdir_counter counters[0]; 340 }; 341 342 TAILQ_HEAD(ice_fdir_counter_pool_list, ice_fdir_counter_pool); 343 344 struct ice_fdir_counter_pool_container { 345 struct ice_fdir_counter_pool_list pool_list; 346 struct ice_fdir_counter_pool *pools[ICE_FDIR_COUNTER_MAX_POOL_SIZE]; 347 uint8_t index_free; 348 }; 349 350 /** 351 * A structure used to define fields of a FDIR related info. 352 */ 353 struct ice_fdir_info { 354 struct ice_vsi *fdir_vsi; /* pointer to fdir VSI structure */ 355 struct ice_tx_queue *txq; 356 struct ice_rx_queue *rxq; 357 void *prg_pkt; /* memory for fdir program packet */ 358 uint64_t dma_addr; /* physic address of packet memory*/ 359 const struct rte_memzone *mz; 360 struct ice_fdir_filter_conf conf; 361 362 struct ice_fdir_filter_conf **hash_map; 363 struct rte_hash *hash_table; 364 365 struct ice_fdir_counter_pool_container counter; 366 }; 367 368 #define ICE_HASH_CFG_VALID(p) \ 369 ((p)->hash_fld != 0 && (p)->pkt_hdr != 0) 370 371 #define ICE_HASH_CFG_RESET(p) do { \ 372 (p)->hash_fld = 0; \ 373 (p)->pkt_hdr = 0; \ 374 } while (0) 375 376 #define ICE_HASH_CFG_IS_ROTATING(p) \ 377 ((p)->rotate == true) 378 379 #define ICE_HASH_CFG_ROTATE_START(p) \ 380 ((p)->rotate = true) 381 382 #define ICE_HASH_CFG_ROTATE_STOP(p) \ 383 ((p)->rotate = false) 384 385 struct ice_hash_cfg { 386 uint32_t pkt_hdr; 387 uint64_t hash_fld; 388 bool rotate; /* rotate l3 rule after l4 rule. */ 389 bool symm; 390 }; 391 392 struct ice_hash_gtpu_ctx { 393 struct ice_hash_cfg ipv4; 394 struct ice_hash_cfg ipv6; 395 struct ice_hash_cfg ipv4_udp; 396 struct ice_hash_cfg ipv6_udp; 397 struct ice_hash_cfg ipv4_tcp; 398 struct ice_hash_cfg ipv6_tcp; 399 }; 400 401 struct ice_pf { 402 struct ice_adapter *adapter; /* The adapter this PF associate to */ 403 struct ice_vsi *main_vsi; /* pointer to main VSI structure */ 404 /* Used for next free software vsi idx. 405 * To save the effort, we don't recycle the index. 406 * Suppose the indexes are more than enough. 407 */ 408 uint16_t next_vsi_idx; 409 uint16_t vsis_allocated; 410 uint16_t vsis_unallocated; 411 struct ice_res_pool_info qp_pool; /*Queue pair pool */ 412 struct ice_res_pool_info msix_pool; /* MSIX interrupt pool */ 413 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 414 struct rte_ether_addr dev_addr; /* PF device mac address */ 415 uint64_t flags; /* PF feature flags */ 416 uint16_t hash_lut_size; /* The size of hash lookup table */ 417 uint16_t lan_nb_qp_max; 418 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ 419 uint16_t base_queue; /* The base queue pairs index in the device */ 420 uint8_t *proto_xtr; /* Protocol extraction type for all queues */ 421 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ 422 uint16_t fdir_qp_offset; 423 struct ice_fdir_info fdir; /* flow director info */ 424 struct ice_hash_gtpu_ctx gtpu_hash_ctx; 425 uint16_t hw_prof_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX]; 426 uint16_t fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX]; 427 struct ice_hw_port_stats stats_offset; 428 struct ice_hw_port_stats stats; 429 /* internal packet statistics, it should be excluded from the total */ 430 struct ice_eth_stats internal_stats_offset; 431 struct ice_eth_stats internal_stats; 432 bool offset_loaded; 433 bool adapter_stopped; 434 struct ice_flow_list flow_list; 435 rte_spinlock_t flow_ops_lock; 436 struct ice_parser_list rss_parser_list; 437 struct ice_parser_list perm_parser_list; 438 struct ice_parser_list dist_parser_list; 439 bool init_link_up; 440 uint64_t old_rx_bytes; 441 uint64_t old_tx_bytes; 442 uint64_t supported_rxdid; /* bitmap for supported RXDID */ 443 }; 444 445 #define ICE_MAX_QUEUE_NUM 2048 446 447 /** 448 * Cache devargs parse result. 449 */ 450 struct ice_devargs { 451 int safe_mode_support; 452 uint8_t proto_xtr_dflt; 453 int pipe_mode_support; 454 uint8_t proto_xtr[ICE_MAX_QUEUE_NUM]; 455 }; 456 457 /** 458 * Structure to store private data for each PF/VF instance. 459 */ 460 struct ice_adapter { 461 /* Common for both PF and VF */ 462 struct ice_hw hw; 463 struct rte_eth_dev *eth_dev; 464 struct ice_pf pf; 465 bool rx_bulk_alloc_allowed; 466 bool rx_vec_allowed; 467 bool tx_vec_allowed; 468 bool tx_simple_allowed; 469 /* ptype mapping table */ 470 uint32_t ptype_tbl[ICE_MAX_PKT_TYPE] __rte_cache_min_aligned; 471 bool is_safe_mode; 472 struct ice_devargs devargs; 473 enum ice_pkg_type active_pkg_type; /* loaded ddp package type */ 474 uint16_t fdir_ref_cnt; 475 }; 476 477 struct ice_vsi_vlan_pvid_info { 478 uint16_t on; /* Enable or disable pvid */ 479 union { 480 uint16_t pvid; /* Valid in case 'on' is set to set pvid */ 481 struct { 482 /* Valid in case 'on' is cleared. 'tagged' will reject 483 * tagged packets, while 'untagged' will reject 484 * untagged packets. 485 */ 486 uint8_t tagged; 487 uint8_t untagged; 488 } reject; 489 } config; 490 }; 491 492 #define ICE_DEV_TO_PCI(eth_dev) \ 493 RTE_DEV_TO_PCI((eth_dev)->device) 494 495 /* ICE_DEV_PRIVATE_TO */ 496 #define ICE_DEV_PRIVATE_TO_PF(adapter) \ 497 (&((struct ice_adapter *)adapter)->pf) 498 #define ICE_DEV_PRIVATE_TO_HW(adapter) \ 499 (&((struct ice_adapter *)adapter)->hw) 500 #define ICE_DEV_PRIVATE_TO_ADAPTER(adapter) \ 501 ((struct ice_adapter *)adapter) 502 503 /* ICE_VSI_TO */ 504 #define ICE_VSI_TO_HW(vsi) \ 505 (&(((struct ice_vsi *)vsi)->adapter->hw)) 506 #define ICE_VSI_TO_PF(vsi) \ 507 (&(((struct ice_vsi *)vsi)->adapter->pf)) 508 #define ICE_VSI_TO_ETH_DEV(vsi) \ 509 (((struct ice_vsi *)vsi)->adapter->eth_dev) 510 511 /* ICE_PF_TO */ 512 #define ICE_PF_TO_HW(pf) \ 513 (&(((struct ice_pf *)pf)->adapter->hw)) 514 #define ICE_PF_TO_ADAPTER(pf) \ 515 ((struct ice_adapter *)(pf)->adapter) 516 #define ICE_PF_TO_ETH_DEV(pf) \ 517 (((struct ice_pf *)pf)->adapter->eth_dev) 518 519 enum ice_pkg_type ice_load_pkg_type(struct ice_hw *hw); 520 struct ice_vsi * 521 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type); 522 int 523 ice_release_vsi(struct ice_vsi *vsi); 524 void ice_vsi_enable_queues_intr(struct ice_vsi *vsi); 525 void ice_vsi_disable_queues_intr(struct ice_vsi *vsi); 526 void ice_vsi_queues_bind_intr(struct ice_vsi *vsi); 527 int ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, 528 uint64_t hash_fld, uint32_t pkt_hdr, bool symm); 529 int ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, 530 uint64_t hash_fld, uint32_t pkt_hdr); 531 532 static inline int 533 ice_align_floor(int n) 534 { 535 if (n == 0) 536 return 0; 537 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); 538 } 539 540 #define ICE_PHY_TYPE_SUPPORT_50G(phy_type) \ 541 (((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CR2) || \ 542 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR2) || \ 543 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR2) || \ 544 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR2) || \ 545 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC) || \ 546 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2) || \ 547 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC) || \ 548 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2) || \ 549 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CP) || \ 550 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR) || \ 551 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_FR) || \ 552 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR) || \ 553 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4) || \ 554 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC) || \ 555 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1)) 556 557 #define ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type) \ 558 (((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR4) || \ 559 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR4) || \ 560 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_LR4) || \ 561 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR4) || \ 562 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC) || \ 563 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4) || \ 564 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC) || \ 565 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4) || \ 566 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4) || \ 567 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4) || \ 568 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CP2) || \ 569 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR2) || \ 570 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_DR)) 571 572 #define ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type) \ 573 (((phy_type) & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) || \ 574 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC) || \ 575 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2) || \ 576 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC) || \ 577 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2)) 578 579 #endif /* _ICE_ETHDEV_H_ */ 580