1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2020 Intel Corporation 3 */ 4 5 #include <errno.h> 6 #include <stdbool.h> 7 #include <sys/types.h> 8 #include <sys/ioctl.h> 9 #include <unistd.h> 10 11 #include <rte_interrupts.h> 12 #include <rte_debug.h> 13 #include <rte_pci.h> 14 #include <rte_atomic.h> 15 #include <rte_eal.h> 16 #include <rte_ether.h> 17 #include <rte_ethdev_pci.h> 18 #include <rte_kvargs.h> 19 #include <rte_malloc.h> 20 #include <rte_memzone.h> 21 #include <rte_dev.h> 22 23 #include <iavf_devids.h> 24 25 #include "ice_generic_flow.h" 26 #include "ice_dcf_ethdev.h" 27 #include "ice_rxtx.h" 28 29 static uint16_t 30 ice_dcf_recv_pkts(__rte_unused void *rx_queue, 31 __rte_unused struct rte_mbuf **bufs, 32 __rte_unused uint16_t nb_pkts) 33 { 34 return 0; 35 } 36 37 static uint16_t 38 ice_dcf_xmit_pkts(__rte_unused void *tx_queue, 39 __rte_unused struct rte_mbuf **bufs, 40 __rte_unused uint16_t nb_pkts) 41 { 42 return 0; 43 } 44 45 static int 46 ice_dcf_init_rxq(struct rte_eth_dev *dev, struct ice_rx_queue *rxq) 47 { 48 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private; 49 struct rte_eth_dev_data *dev_data = dev->data; 50 struct iavf_hw *hw = &dcf_ad->real_hw.avf; 51 uint16_t buf_size, max_pkt_len, len; 52 53 buf_size = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM; 54 rxq->rx_hdr_len = 0; 55 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S)); 56 len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len; 57 max_pkt_len = RTE_MIN(len, dev->data->dev_conf.rxmode.max_rx_pkt_len); 58 59 /* Check if the jumbo frame and maximum packet length are set 60 * correctly. 61 */ 62 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 63 if (max_pkt_len <= RTE_ETHER_MAX_LEN || 64 max_pkt_len > ICE_FRAME_SIZE_MAX) { 65 PMD_DRV_LOG(ERR, "maximum packet length must be " 66 "larger than %u and smaller than %u, " 67 "as jumbo frame is enabled", 68 (uint32_t)RTE_ETHER_MAX_LEN, 69 (uint32_t)ICE_FRAME_SIZE_MAX); 70 return -EINVAL; 71 } 72 } else { 73 if (max_pkt_len < RTE_ETHER_MIN_LEN || 74 max_pkt_len > RTE_ETHER_MAX_LEN) { 75 PMD_DRV_LOG(ERR, "maximum packet length must be " 76 "larger than %u and smaller than %u, " 77 "as jumbo frame is disabled", 78 (uint32_t)RTE_ETHER_MIN_LEN, 79 (uint32_t)RTE_ETHER_MAX_LEN); 80 return -EINVAL; 81 } 82 } 83 84 rxq->max_pkt_len = max_pkt_len; 85 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) || 86 (rxq->max_pkt_len + 2 * ICE_VLAN_TAG_SIZE) > buf_size) { 87 dev_data->scattered_rx = 1; 88 } 89 rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id); 90 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1); 91 IAVF_WRITE_FLUSH(hw); 92 93 return 0; 94 } 95 96 static int 97 ice_dcf_init_rx_queues(struct rte_eth_dev *dev) 98 { 99 struct ice_rx_queue **rxq = 100 (struct ice_rx_queue **)dev->data->rx_queues; 101 int i, ret; 102 103 for (i = 0; i < dev->data->nb_rx_queues; i++) { 104 if (!rxq[i] || !rxq[i]->q_set) 105 continue; 106 ret = ice_dcf_init_rxq(dev, rxq[i]); 107 if (ret) 108 return ret; 109 } 110 111 ice_set_rx_function(dev); 112 ice_set_tx_function(dev); 113 114 return 0; 115 } 116 117 #define IAVF_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 118 #define IAVF_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 119 120 #define IAVF_ITR_INDEX_DEFAULT 0 121 #define IAVF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 122 #define IAVF_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */ 123 124 static inline uint16_t 125 iavf_calc_itr_interval(int16_t interval) 126 { 127 if (interval < 0 || interval > IAVF_QUEUE_ITR_INTERVAL_MAX) 128 interval = IAVF_QUEUE_ITR_INTERVAL_DEFAULT; 129 130 /* Convert to hardware count, as writing each 1 represents 2 us */ 131 return interval / 2; 132 } 133 134 static int 135 ice_dcf_config_rx_queues_irqs(struct rte_eth_dev *dev, 136 struct rte_intr_handle *intr_handle) 137 { 138 struct ice_dcf_adapter *adapter = dev->data->dev_private; 139 struct ice_dcf_hw *hw = &adapter->real_hw; 140 uint16_t interval, i; 141 int vec; 142 143 if (rte_intr_cap_multiple(intr_handle) && 144 dev->data->dev_conf.intr_conf.rxq) { 145 if (rte_intr_efd_enable(intr_handle, dev->data->nb_rx_queues)) 146 return -1; 147 } 148 149 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 150 intr_handle->intr_vec = 151 rte_zmalloc("intr_vec", 152 dev->data->nb_rx_queues * sizeof(int), 0); 153 if (!intr_handle->intr_vec) { 154 PMD_DRV_LOG(ERR, "Failed to allocate %d rx intr_vec", 155 dev->data->nb_rx_queues); 156 return -1; 157 } 158 } 159 160 if (!dev->data->dev_conf.intr_conf.rxq || 161 !rte_intr_dp_is_en(intr_handle)) { 162 /* Rx interrupt disabled, Map interrupt only for writeback */ 163 hw->nb_msix = 1; 164 if (hw->vf_res->vf_cap_flags & 165 VIRTCHNL_VF_OFFLOAD_WB_ON_ITR) { 166 /* If WB_ON_ITR supports, enable it */ 167 hw->msix_base = IAVF_RX_VEC_START; 168 IAVF_WRITE_REG(&hw->avf, 169 IAVF_VFINT_DYN_CTLN1(hw->msix_base - 1), 170 IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK | 171 IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK); 172 } else { 173 /* If no WB_ON_ITR offload flags, need to set 174 * interrupt for descriptor write back. 175 */ 176 hw->msix_base = IAVF_MISC_VEC_ID; 177 178 /* set ITR to max */ 179 interval = 180 iavf_calc_itr_interval(IAVF_QUEUE_ITR_INTERVAL_MAX); 181 IAVF_WRITE_REG(&hw->avf, IAVF_VFINT_DYN_CTL01, 182 IAVF_VFINT_DYN_CTL01_INTENA_MASK | 183 (IAVF_ITR_INDEX_DEFAULT << 184 IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT) | 185 (interval << 186 IAVF_VFINT_DYN_CTL01_INTERVAL_SHIFT)); 187 } 188 IAVF_WRITE_FLUSH(&hw->avf); 189 /* map all queues to the same interrupt */ 190 for (i = 0; i < dev->data->nb_rx_queues; i++) 191 hw->rxq_map[hw->msix_base] |= 1 << i; 192 } else { 193 if (!rte_intr_allow_others(intr_handle)) { 194 hw->nb_msix = 1; 195 hw->msix_base = IAVF_MISC_VEC_ID; 196 for (i = 0; i < dev->data->nb_rx_queues; i++) { 197 hw->rxq_map[hw->msix_base] |= 1 << i; 198 intr_handle->intr_vec[i] = IAVF_MISC_VEC_ID; 199 } 200 PMD_DRV_LOG(DEBUG, 201 "vector %u are mapping to all Rx queues", 202 hw->msix_base); 203 } else { 204 /* If Rx interrupt is reuquired, and we can use 205 * multi interrupts, then the vec is from 1 206 */ 207 hw->nb_msix = RTE_MIN(hw->vf_res->max_vectors, 208 intr_handle->nb_efd); 209 hw->msix_base = IAVF_MISC_VEC_ID; 210 vec = IAVF_MISC_VEC_ID; 211 for (i = 0; i < dev->data->nb_rx_queues; i++) { 212 hw->rxq_map[vec] |= 1 << i; 213 intr_handle->intr_vec[i] = vec++; 214 if (vec >= hw->nb_msix) 215 vec = IAVF_RX_VEC_START; 216 } 217 PMD_DRV_LOG(DEBUG, 218 "%u vectors are mapping to %u Rx queues", 219 hw->nb_msix, dev->data->nb_rx_queues); 220 } 221 } 222 223 if (ice_dcf_config_irq_map(hw)) { 224 PMD_DRV_LOG(ERR, "config interrupt mapping failed"); 225 return -1; 226 } 227 return 0; 228 } 229 230 static int 231 alloc_rxq_mbufs(struct ice_rx_queue *rxq) 232 { 233 volatile union ice_32b_rx_flex_desc *rxd; 234 struct rte_mbuf *mbuf = NULL; 235 uint64_t dma_addr; 236 uint16_t i; 237 238 for (i = 0; i < rxq->nb_rx_desc; i++) { 239 mbuf = rte_mbuf_raw_alloc(rxq->mp); 240 if (unlikely(!mbuf)) { 241 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX"); 242 return -ENOMEM; 243 } 244 245 rte_mbuf_refcnt_set(mbuf, 1); 246 mbuf->next = NULL; 247 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 248 mbuf->nb_segs = 1; 249 mbuf->port = rxq->port_id; 250 251 dma_addr = 252 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf)); 253 254 rxd = &rxq->rx_ring[i]; 255 rxd->read.pkt_addr = dma_addr; 256 rxd->read.hdr_addr = 0; 257 rxd->read.rsvd1 = 0; 258 rxd->read.rsvd2 = 0; 259 260 rxq->sw_ring[i].mbuf = (void *)mbuf; 261 } 262 263 return 0; 264 } 265 266 static int 267 ice_dcf_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) 268 { 269 struct ice_dcf_adapter *ad = dev->data->dev_private; 270 struct iavf_hw *hw = &ad->real_hw.avf; 271 struct ice_rx_queue *rxq; 272 int err = 0; 273 274 if (rx_queue_id >= dev->data->nb_rx_queues) 275 return -EINVAL; 276 277 rxq = dev->data->rx_queues[rx_queue_id]; 278 279 err = alloc_rxq_mbufs(rxq); 280 if (err) { 281 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf"); 282 return err; 283 } 284 285 rte_wmb(); 286 287 /* Init the RX tail register. */ 288 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1); 289 IAVF_WRITE_FLUSH(hw); 290 291 /* Ready to switch the queue on */ 292 err = ice_dcf_switch_queue(&ad->real_hw, rx_queue_id, true, true); 293 if (err) { 294 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on", 295 rx_queue_id); 296 return err; 297 } 298 299 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 300 301 return 0; 302 } 303 304 static inline void 305 reset_rx_queue(struct ice_rx_queue *rxq) 306 { 307 uint16_t len; 308 uint32_t i; 309 310 if (!rxq) 311 return; 312 313 len = rxq->nb_rx_desc + ICE_RX_MAX_BURST; 314 315 for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++) 316 ((volatile char *)rxq->rx_ring)[i] = 0; 317 318 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf)); 319 320 for (i = 0; i < ICE_RX_MAX_BURST; i++) 321 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf; 322 323 /* for rx bulk */ 324 rxq->rx_nb_avail = 0; 325 rxq->rx_next_avail = 0; 326 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1); 327 328 rxq->rx_tail = 0; 329 rxq->nb_rx_hold = 0; 330 rxq->pkt_first_seg = NULL; 331 rxq->pkt_last_seg = NULL; 332 } 333 334 static inline void 335 reset_tx_queue(struct ice_tx_queue *txq) 336 { 337 struct ice_tx_entry *txe; 338 uint32_t i, size; 339 uint16_t prev; 340 341 if (!txq) { 342 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL"); 343 return; 344 } 345 346 txe = txq->sw_ring; 347 size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc; 348 for (i = 0; i < size; i++) 349 ((volatile char *)txq->tx_ring)[i] = 0; 350 351 prev = (uint16_t)(txq->nb_tx_desc - 1); 352 for (i = 0; i < txq->nb_tx_desc; i++) { 353 txq->tx_ring[i].cmd_type_offset_bsz = 354 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE); 355 txe[i].mbuf = NULL; 356 txe[i].last_id = i; 357 txe[prev].next_id = i; 358 prev = i; 359 } 360 361 txq->tx_tail = 0; 362 txq->nb_tx_used = 0; 363 364 txq->last_desc_cleaned = txq->nb_tx_desc - 1; 365 txq->nb_tx_free = txq->nb_tx_desc - 1; 366 367 txq->tx_next_dd = txq->tx_rs_thresh - 1; 368 txq->tx_next_rs = txq->tx_rs_thresh - 1; 369 } 370 371 static int 372 ice_dcf_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id) 373 { 374 struct ice_dcf_adapter *ad = dev->data->dev_private; 375 struct ice_dcf_hw *hw = &ad->real_hw; 376 struct ice_rx_queue *rxq; 377 int err; 378 379 if (rx_queue_id >= dev->data->nb_rx_queues) 380 return -EINVAL; 381 382 err = ice_dcf_switch_queue(hw, rx_queue_id, true, false); 383 if (err) { 384 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off", 385 rx_queue_id); 386 return err; 387 } 388 389 rxq = dev->data->rx_queues[rx_queue_id]; 390 rxq->rx_rel_mbufs(rxq); 391 reset_rx_queue(rxq); 392 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 393 394 return 0; 395 } 396 397 static int 398 ice_dcf_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) 399 { 400 struct ice_dcf_adapter *ad = dev->data->dev_private; 401 struct iavf_hw *hw = &ad->real_hw.avf; 402 struct ice_tx_queue *txq; 403 int err = 0; 404 405 if (tx_queue_id >= dev->data->nb_tx_queues) 406 return -EINVAL; 407 408 txq = dev->data->tx_queues[tx_queue_id]; 409 410 /* Init the RX tail register. */ 411 txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(tx_queue_id); 412 IAVF_PCI_REG_WRITE(txq->qtx_tail, 0); 413 IAVF_WRITE_FLUSH(hw); 414 415 /* Ready to switch the queue on */ 416 err = ice_dcf_switch_queue(&ad->real_hw, tx_queue_id, false, true); 417 418 if (err) { 419 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on", 420 tx_queue_id); 421 return err; 422 } 423 424 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 425 426 return 0; 427 } 428 429 static int 430 ice_dcf_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) 431 { 432 struct ice_dcf_adapter *ad = dev->data->dev_private; 433 struct ice_dcf_hw *hw = &ad->real_hw; 434 struct ice_tx_queue *txq; 435 int err; 436 437 if (tx_queue_id >= dev->data->nb_tx_queues) 438 return -EINVAL; 439 440 err = ice_dcf_switch_queue(hw, tx_queue_id, false, false); 441 if (err) { 442 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off", 443 tx_queue_id); 444 return err; 445 } 446 447 txq = dev->data->tx_queues[tx_queue_id]; 448 txq->tx_rel_mbufs(txq); 449 reset_tx_queue(txq); 450 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 451 452 return 0; 453 } 454 455 static int 456 ice_dcf_start_queues(struct rte_eth_dev *dev) 457 { 458 struct ice_rx_queue *rxq; 459 struct ice_tx_queue *txq; 460 int nb_rxq = 0; 461 int nb_txq, i; 462 463 for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) { 464 txq = dev->data->tx_queues[nb_txq]; 465 if (txq->tx_deferred_start) 466 continue; 467 if (ice_dcf_tx_queue_start(dev, nb_txq) != 0) { 468 PMD_DRV_LOG(ERR, "Fail to start queue %u", nb_txq); 469 goto tx_err; 470 } 471 } 472 473 for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) { 474 rxq = dev->data->rx_queues[nb_rxq]; 475 if (rxq->rx_deferred_start) 476 continue; 477 if (ice_dcf_rx_queue_start(dev, nb_rxq) != 0) { 478 PMD_DRV_LOG(ERR, "Fail to start queue %u", nb_rxq); 479 goto rx_err; 480 } 481 } 482 483 return 0; 484 485 /* stop the started queues if failed to start all queues */ 486 rx_err: 487 for (i = 0; i < nb_rxq; i++) 488 ice_dcf_rx_queue_stop(dev, i); 489 tx_err: 490 for (i = 0; i < nb_txq; i++) 491 ice_dcf_tx_queue_stop(dev, i); 492 493 return -1; 494 } 495 496 static int 497 ice_dcf_dev_start(struct rte_eth_dev *dev) 498 { 499 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private; 500 struct rte_intr_handle *intr_handle = dev->intr_handle; 501 struct ice_adapter *ad = &dcf_ad->parent; 502 struct ice_dcf_hw *hw = &dcf_ad->real_hw; 503 int ret; 504 505 ad->pf.adapter_stopped = 0; 506 507 hw->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues, 508 dev->data->nb_tx_queues); 509 510 ret = ice_dcf_init_rx_queues(dev); 511 if (ret) { 512 PMD_DRV_LOG(ERR, "Fail to init queues"); 513 return ret; 514 } 515 516 if (hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF) { 517 ret = ice_dcf_init_rss(hw); 518 if (ret) { 519 PMD_DRV_LOG(ERR, "Failed to configure RSS"); 520 return ret; 521 } 522 } 523 524 ret = ice_dcf_configure_queues(hw); 525 if (ret) { 526 PMD_DRV_LOG(ERR, "Fail to config queues"); 527 return ret; 528 } 529 530 ret = ice_dcf_config_rx_queues_irqs(dev, intr_handle); 531 if (ret) { 532 PMD_DRV_LOG(ERR, "Fail to config rx queues' irqs"); 533 return ret; 534 } 535 536 if (dev->data->dev_conf.intr_conf.rxq != 0) { 537 rte_intr_disable(intr_handle); 538 rte_intr_enable(intr_handle); 539 } 540 541 ret = ice_dcf_start_queues(dev); 542 if (ret) { 543 PMD_DRV_LOG(ERR, "Failed to enable queues"); 544 return ret; 545 } 546 547 ret = ice_dcf_add_del_all_mac_addr(hw, true); 548 if (ret) { 549 PMD_DRV_LOG(ERR, "Failed to add mac addr"); 550 return ret; 551 } 552 553 dev->data->dev_link.link_status = ETH_LINK_UP; 554 555 return 0; 556 } 557 558 static void 559 ice_dcf_stop_queues(struct rte_eth_dev *dev) 560 { 561 struct ice_dcf_adapter *ad = dev->data->dev_private; 562 struct ice_dcf_hw *hw = &ad->real_hw; 563 struct ice_rx_queue *rxq; 564 struct ice_tx_queue *txq; 565 int ret, i; 566 567 /* Stop All queues */ 568 ret = ice_dcf_disable_queues(hw); 569 if (ret) 570 PMD_DRV_LOG(WARNING, "Fail to stop queues"); 571 572 for (i = 0; i < dev->data->nb_tx_queues; i++) { 573 txq = dev->data->tx_queues[i]; 574 if (!txq) 575 continue; 576 txq->tx_rel_mbufs(txq); 577 reset_tx_queue(txq); 578 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 579 } 580 for (i = 0; i < dev->data->nb_rx_queues; i++) { 581 rxq = dev->data->rx_queues[i]; 582 if (!rxq) 583 continue; 584 rxq->rx_rel_mbufs(rxq); 585 reset_rx_queue(rxq); 586 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 587 } 588 } 589 590 static void 591 ice_dcf_dev_stop(struct rte_eth_dev *dev) 592 { 593 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private; 594 struct rte_intr_handle *intr_handle = dev->intr_handle; 595 struct ice_adapter *ad = &dcf_ad->parent; 596 597 if (ad->pf.adapter_stopped == 1) { 598 PMD_DRV_LOG(DEBUG, "Port is already stopped"); 599 return; 600 } 601 602 ice_dcf_stop_queues(dev); 603 604 rte_intr_efd_disable(intr_handle); 605 if (intr_handle->intr_vec) { 606 rte_free(intr_handle->intr_vec); 607 intr_handle->intr_vec = NULL; 608 } 609 610 ice_dcf_add_del_all_mac_addr(&dcf_ad->real_hw, false); 611 dev->data->dev_link.link_status = ETH_LINK_DOWN; 612 ad->pf.adapter_stopped = 1; 613 } 614 615 static int 616 ice_dcf_dev_configure(struct rte_eth_dev *dev) 617 { 618 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private; 619 struct ice_adapter *ad = &dcf_ad->parent; 620 621 ad->rx_bulk_alloc_allowed = true; 622 ad->tx_simple_allowed = true; 623 624 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 625 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 626 627 return 0; 628 } 629 630 static int 631 ice_dcf_dev_info_get(struct rte_eth_dev *dev, 632 struct rte_eth_dev_info *dev_info) 633 { 634 struct ice_dcf_adapter *adapter = dev->data->dev_private; 635 struct ice_dcf_hw *hw = &adapter->real_hw; 636 637 dev_info->max_mac_addrs = 1; 638 dev_info->max_rx_queues = hw->vsi_res->num_queue_pairs; 639 dev_info->max_tx_queues = hw->vsi_res->num_queue_pairs; 640 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN; 641 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX; 642 dev_info->hash_key_size = hw->vf_res->rss_key_size; 643 dev_info->reta_size = hw->vf_res->rss_lut_size; 644 dev_info->flow_type_rss_offloads = ICE_RSS_OFFLOAD_ALL; 645 646 dev_info->rx_offload_capa = 647 DEV_RX_OFFLOAD_VLAN_STRIP | 648 DEV_RX_OFFLOAD_IPV4_CKSUM | 649 DEV_RX_OFFLOAD_UDP_CKSUM | 650 DEV_RX_OFFLOAD_TCP_CKSUM | 651 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 652 DEV_RX_OFFLOAD_SCATTER | 653 DEV_RX_OFFLOAD_JUMBO_FRAME | 654 DEV_RX_OFFLOAD_VLAN_FILTER | 655 DEV_RX_OFFLOAD_RSS_HASH; 656 dev_info->tx_offload_capa = 657 DEV_TX_OFFLOAD_VLAN_INSERT | 658 DEV_TX_OFFLOAD_IPV4_CKSUM | 659 DEV_TX_OFFLOAD_UDP_CKSUM | 660 DEV_TX_OFFLOAD_TCP_CKSUM | 661 DEV_TX_OFFLOAD_SCTP_CKSUM | 662 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 663 DEV_TX_OFFLOAD_TCP_TSO | 664 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 665 DEV_TX_OFFLOAD_GRE_TNL_TSO | 666 DEV_TX_OFFLOAD_IPIP_TNL_TSO | 667 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | 668 DEV_TX_OFFLOAD_MULTI_SEGS; 669 670 dev_info->default_rxconf = (struct rte_eth_rxconf) { 671 .rx_thresh = { 672 .pthresh = ICE_DEFAULT_RX_PTHRESH, 673 .hthresh = ICE_DEFAULT_RX_HTHRESH, 674 .wthresh = ICE_DEFAULT_RX_WTHRESH, 675 }, 676 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH, 677 .rx_drop_en = 0, 678 .offloads = 0, 679 }; 680 681 dev_info->default_txconf = (struct rte_eth_txconf) { 682 .tx_thresh = { 683 .pthresh = ICE_DEFAULT_TX_PTHRESH, 684 .hthresh = ICE_DEFAULT_TX_HTHRESH, 685 .wthresh = ICE_DEFAULT_TX_WTHRESH, 686 }, 687 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH, 688 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH, 689 .offloads = 0, 690 }; 691 692 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 693 .nb_max = ICE_MAX_RING_DESC, 694 .nb_min = ICE_MIN_RING_DESC, 695 .nb_align = ICE_ALIGN_RING_DESC, 696 }; 697 698 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 699 .nb_max = ICE_MAX_RING_DESC, 700 .nb_min = ICE_MIN_RING_DESC, 701 .nb_align = ICE_ALIGN_RING_DESC, 702 }; 703 704 return 0; 705 } 706 707 static int 708 ice_dcf_dev_promiscuous_enable(__rte_unused struct rte_eth_dev *dev) 709 { 710 return 0; 711 } 712 713 static int 714 ice_dcf_dev_promiscuous_disable(__rte_unused struct rte_eth_dev *dev) 715 { 716 return 0; 717 } 718 719 static int 720 ice_dcf_dev_allmulticast_enable(__rte_unused struct rte_eth_dev *dev) 721 { 722 return 0; 723 } 724 725 static int 726 ice_dcf_dev_allmulticast_disable(__rte_unused struct rte_eth_dev *dev) 727 { 728 return 0; 729 } 730 731 static int 732 ice_dcf_dev_filter_ctrl(struct rte_eth_dev *dev, 733 enum rte_filter_type filter_type, 734 enum rte_filter_op filter_op, 735 void *arg) 736 { 737 int ret = 0; 738 739 if (!dev) 740 return -EINVAL; 741 742 switch (filter_type) { 743 case RTE_ETH_FILTER_GENERIC: 744 if (filter_op != RTE_ETH_FILTER_GET) 745 return -EINVAL; 746 *(const void **)arg = &ice_flow_ops; 747 break; 748 749 default: 750 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 751 filter_type); 752 ret = -EINVAL; 753 break; 754 } 755 756 return ret; 757 } 758 759 #define ICE_DCF_32_BIT_WIDTH (CHAR_BIT * 4) 760 #define ICE_DCF_48_BIT_WIDTH (CHAR_BIT * 6) 761 #define ICE_DCF_48_BIT_MASK RTE_LEN2MASK(ICE_DCF_48_BIT_WIDTH, uint64_t) 762 763 static void 764 ice_dcf_stat_update_48(uint64_t *offset, uint64_t *stat) 765 { 766 if (*stat >= *offset) 767 *stat = *stat - *offset; 768 else 769 *stat = (uint64_t)((*stat + 770 ((uint64_t)1 << ICE_DCF_48_BIT_WIDTH)) - *offset); 771 772 *stat &= ICE_DCF_48_BIT_MASK; 773 } 774 775 static void 776 ice_dcf_stat_update_32(uint64_t *offset, uint64_t *stat) 777 { 778 if (*stat >= *offset) 779 *stat = (uint64_t)(*stat - *offset); 780 else 781 *stat = (uint64_t)((*stat + 782 ((uint64_t)1 << ICE_DCF_32_BIT_WIDTH)) - *offset); 783 } 784 785 static void 786 ice_dcf_update_stats(struct virtchnl_eth_stats *oes, 787 struct virtchnl_eth_stats *nes) 788 { 789 ice_dcf_stat_update_48(&oes->rx_bytes, &nes->rx_bytes); 790 ice_dcf_stat_update_48(&oes->rx_unicast, &nes->rx_unicast); 791 ice_dcf_stat_update_48(&oes->rx_multicast, &nes->rx_multicast); 792 ice_dcf_stat_update_48(&oes->rx_broadcast, &nes->rx_broadcast); 793 ice_dcf_stat_update_32(&oes->rx_discards, &nes->rx_discards); 794 ice_dcf_stat_update_48(&oes->tx_bytes, &nes->tx_bytes); 795 ice_dcf_stat_update_48(&oes->tx_unicast, &nes->tx_unicast); 796 ice_dcf_stat_update_48(&oes->tx_multicast, &nes->tx_multicast); 797 ice_dcf_stat_update_48(&oes->tx_broadcast, &nes->tx_broadcast); 798 ice_dcf_stat_update_32(&oes->tx_errors, &nes->tx_errors); 799 ice_dcf_stat_update_32(&oes->tx_discards, &nes->tx_discards); 800 } 801 802 803 static int 804 ice_dcf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 805 { 806 struct ice_dcf_adapter *ad = dev->data->dev_private; 807 struct ice_dcf_hw *hw = &ad->real_hw; 808 struct virtchnl_eth_stats pstats; 809 int ret; 810 811 ret = ice_dcf_query_stats(hw, &pstats); 812 if (ret == 0) { 813 ice_dcf_update_stats(&hw->eth_stats_offset, &pstats); 814 stats->ipackets = pstats.rx_unicast + pstats.rx_multicast + 815 pstats.rx_broadcast - pstats.rx_discards; 816 stats->opackets = pstats.tx_broadcast + pstats.tx_multicast + 817 pstats.tx_unicast; 818 stats->imissed = pstats.rx_discards; 819 stats->oerrors = pstats.tx_errors + pstats.tx_discards; 820 stats->ibytes = pstats.rx_bytes; 821 stats->ibytes -= stats->ipackets * RTE_ETHER_CRC_LEN; 822 stats->obytes = pstats.tx_bytes; 823 } else { 824 PMD_DRV_LOG(ERR, "Get statistics failed"); 825 } 826 return ret; 827 } 828 829 static int 830 ice_dcf_stats_reset(struct rte_eth_dev *dev) 831 { 832 struct ice_dcf_adapter *ad = dev->data->dev_private; 833 struct ice_dcf_hw *hw = &ad->real_hw; 834 struct virtchnl_eth_stats pstats; 835 int ret; 836 837 /* read stat values to clear hardware registers */ 838 ret = ice_dcf_query_stats(hw, &pstats); 839 if (ret != 0) 840 return ret; 841 842 /* set stats offset base on current values */ 843 hw->eth_stats_offset = pstats; 844 845 return 0; 846 } 847 848 static void 849 ice_dcf_dev_close(struct rte_eth_dev *dev) 850 { 851 struct ice_dcf_adapter *adapter = dev->data->dev_private; 852 853 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 854 return; 855 856 dev->dev_ops = NULL; 857 dev->rx_pkt_burst = NULL; 858 dev->tx_pkt_burst = NULL; 859 860 ice_dcf_uninit_parent_adapter(dev); 861 ice_dcf_uninit_hw(dev, &adapter->real_hw); 862 } 863 864 static int 865 ice_dcf_link_update(__rte_unused struct rte_eth_dev *dev, 866 __rte_unused int wait_to_complete) 867 { 868 return 0; 869 } 870 871 static const struct eth_dev_ops ice_dcf_eth_dev_ops = { 872 .dev_start = ice_dcf_dev_start, 873 .dev_stop = ice_dcf_dev_stop, 874 .dev_close = ice_dcf_dev_close, 875 .dev_configure = ice_dcf_dev_configure, 876 .dev_infos_get = ice_dcf_dev_info_get, 877 .rx_queue_setup = ice_rx_queue_setup, 878 .tx_queue_setup = ice_tx_queue_setup, 879 .rx_queue_release = ice_rx_queue_release, 880 .tx_queue_release = ice_tx_queue_release, 881 .rx_queue_start = ice_dcf_rx_queue_start, 882 .tx_queue_start = ice_dcf_tx_queue_start, 883 .rx_queue_stop = ice_dcf_rx_queue_stop, 884 .tx_queue_stop = ice_dcf_tx_queue_stop, 885 .link_update = ice_dcf_link_update, 886 .stats_get = ice_dcf_stats_get, 887 .stats_reset = ice_dcf_stats_reset, 888 .promiscuous_enable = ice_dcf_dev_promiscuous_enable, 889 .promiscuous_disable = ice_dcf_dev_promiscuous_disable, 890 .allmulticast_enable = ice_dcf_dev_allmulticast_enable, 891 .allmulticast_disable = ice_dcf_dev_allmulticast_disable, 892 .filter_ctrl = ice_dcf_dev_filter_ctrl, 893 }; 894 895 static int 896 ice_dcf_dev_init(struct rte_eth_dev *eth_dev) 897 { 898 struct ice_dcf_adapter *adapter = eth_dev->data->dev_private; 899 900 eth_dev->dev_ops = &ice_dcf_eth_dev_ops; 901 eth_dev->rx_pkt_burst = ice_dcf_recv_pkts; 902 eth_dev->tx_pkt_burst = ice_dcf_xmit_pkts; 903 904 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 905 return 0; 906 907 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 908 909 adapter->real_hw.vc_event_msg_cb = ice_dcf_handle_pf_event_msg; 910 if (ice_dcf_init_hw(eth_dev, &adapter->real_hw) != 0) { 911 PMD_INIT_LOG(ERR, "Failed to init DCF hardware"); 912 return -1; 913 } 914 915 if (ice_dcf_init_parent_adapter(eth_dev) != 0) { 916 PMD_INIT_LOG(ERR, "Failed to init DCF parent adapter"); 917 ice_dcf_uninit_hw(eth_dev, &adapter->real_hw); 918 return -1; 919 } 920 921 return 0; 922 } 923 924 static int 925 ice_dcf_dev_uninit(struct rte_eth_dev *eth_dev) 926 { 927 ice_dcf_dev_close(eth_dev); 928 929 return 0; 930 } 931 932 static int 933 ice_dcf_cap_check_handler(__rte_unused const char *key, 934 const char *value, __rte_unused void *opaque) 935 { 936 if (strcmp(value, "dcf")) 937 return -1; 938 939 return 0; 940 } 941 942 static int 943 ice_dcf_cap_selected(struct rte_devargs *devargs) 944 { 945 struct rte_kvargs *kvlist; 946 const char *key = "cap"; 947 int ret = 0; 948 949 if (devargs == NULL) 950 return 0; 951 952 kvlist = rte_kvargs_parse(devargs->args, NULL); 953 if (kvlist == NULL) 954 return 0; 955 956 if (!rte_kvargs_count(kvlist, key)) 957 goto exit; 958 959 /* dcf capability selected when there's a key-value pair: cap=dcf */ 960 if (rte_kvargs_process(kvlist, key, 961 ice_dcf_cap_check_handler, NULL) < 0) 962 goto exit; 963 964 ret = 1; 965 966 exit: 967 rte_kvargs_free(kvlist); 968 return ret; 969 } 970 971 static int eth_ice_dcf_pci_probe(__rte_unused struct rte_pci_driver *pci_drv, 972 struct rte_pci_device *pci_dev) 973 { 974 if (!ice_dcf_cap_selected(pci_dev->device.devargs)) 975 return 1; 976 977 return rte_eth_dev_pci_generic_probe(pci_dev, 978 sizeof(struct ice_dcf_adapter), 979 ice_dcf_dev_init); 980 } 981 982 static int eth_ice_dcf_pci_remove(struct rte_pci_device *pci_dev) 983 { 984 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dcf_dev_uninit); 985 } 986 987 static const struct rte_pci_id pci_id_ice_dcf_map[] = { 988 { RTE_PCI_DEVICE(IAVF_INTEL_VENDOR_ID, IAVF_DEV_ID_ADAPTIVE_VF) }, 989 { .vendor_id = 0, /* sentinel */ }, 990 }; 991 992 static struct rte_pci_driver rte_ice_dcf_pmd = { 993 .id_table = pci_id_ice_dcf_map, 994 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 995 .probe = eth_ice_dcf_pci_probe, 996 .remove = eth_ice_dcf_pci_remove, 997 }; 998 999 RTE_PMD_REGISTER_PCI(net_ice_dcf, rte_ice_dcf_pmd); 1000 RTE_PMD_REGISTER_PCI_TABLE(net_ice_dcf, pci_id_ice_dcf_map); 1001 RTE_PMD_REGISTER_KMOD_DEP(net_ice_dcf, "* igb_uio | vfio-pci"); 1002 RTE_PMD_REGISTER_PARAM_STRING(net_ice_dcf, "cap=dcf"); 1003