1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2021 Intel Corporation 3 */ 4 5 #ifndef _ICE_COMMON_H_ 6 #define _ICE_COMMON_H_ 7 8 #include "ice_type.h" 9 #include "ice_nvm.h" 10 #include "ice_flex_pipe.h" 11 #include "ice_switch.h" 12 #include "ice_fdir.h" 13 14 #define ICE_SQ_SEND_DELAY_TIME_MS 10 15 #define ICE_SQ_SEND_MAX_EXECUTE 3 16 17 enum ice_fw_modes { 18 ICE_FW_MODE_NORMAL, 19 ICE_FW_MODE_DBG, 20 ICE_FW_MODE_REC, 21 ICE_FW_MODE_ROLLBACK 22 }; 23 24 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw); 25 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw); 26 enum ice_status ice_init_hw(struct ice_hw *hw); 27 void ice_deinit_hw(struct ice_hw *hw); 28 enum ice_status ice_check_reset(struct ice_hw *hw); 29 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req); 30 31 enum ice_status ice_create_all_ctrlq(struct ice_hw *hw); 32 enum ice_status ice_init_all_ctrlq(struct ice_hw *hw); 33 void ice_shutdown_all_ctrlq(struct ice_hw *hw); 34 void ice_destroy_all_ctrlq(struct ice_hw *hw); 35 enum ice_status 36 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq, 37 struct ice_rq_event_info *e, u16 *pending); 38 enum ice_status 39 ice_get_link_status(struct ice_port_info *pi, bool *link_up); 40 enum ice_status ice_update_link_info(struct ice_port_info *pi); 41 enum ice_status 42 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 43 enum ice_aq_res_access_type access, u32 timeout); 44 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res); 45 enum ice_status 46 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res); 47 enum ice_status 48 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res); 49 enum ice_status 50 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 51 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 52 enum ice_adminq_opc opc, struct ice_sq_cd *cd); 53 enum ice_status 54 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 55 struct ice_aq_desc *desc, void *buf, u16 buf_size, 56 struct ice_sq_cd *cd); 57 void ice_clear_pxe_mode(struct ice_hw *hw); 58 59 enum ice_status ice_get_caps(struct ice_hw *hw); 60 61 void ice_set_safe_mode_caps(struct ice_hw *hw); 62 63 /* Define a macro that will align a pointer to point to the next memory address 64 * that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For 65 * example, given the variable pointer = 0x1006, then after the following call: 66 * 67 * pointer = ICE_ALIGN(pointer, 4) 68 * 69 * ... the value of pointer would equal 0x1008, since 0x1008 is the next 70 * address after 0x1006 which is divisible by 4. 71 */ 72 #define ICE_ALIGN(ptr, align) (((ptr) + ((align) - 1)) & ~((align) - 1)) 73 74 enum ice_status 75 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 76 u32 rxq_index); 77 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index); 78 enum ice_status 79 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index); 80 enum ice_status 81 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw, 82 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx, 83 u32 tx_cmpltnq_index); 84 enum ice_status 85 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index); 86 enum ice_status 87 ice_write_tx_drbell_q_ctx(struct ice_hw *hw, 88 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx, 89 u32 tx_drbell_q_index); 90 91 enum ice_status 92 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params); 93 enum ice_status 94 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params); 95 enum ice_status 96 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 97 struct ice_aqc_get_set_rss_keys *keys); 98 enum ice_status 99 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 100 struct ice_aqc_get_set_rss_keys *keys); 101 enum ice_status 102 ice_aq_add_lan_txq(struct ice_hw *hw, u8 count, 103 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 104 struct ice_sq_cd *cd); 105 enum ice_status 106 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move, 107 bool is_tc_change, bool subseq_call, bool flush_pipe, 108 u8 timeout, u32 *blocked_cgds, 109 struct ice_aqc_move_txqs_data *buf, u16 buf_size, 110 u8 *txqs_moved, struct ice_sq_cd *cd); 111 112 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq); 113 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading); 114 void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode); 115 extern const struct ice_ctx_ele ice_tlan_ctx_info[]; 116 enum ice_status 117 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 118 const struct ice_ctx_ele *ce_info); 119 120 enum ice_status 121 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, 122 void *buf, u16 buf_size, struct ice_sq_cd *cd); 123 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd); 124 125 enum ice_status 126 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 127 struct ice_sq_cd *cd); 128 enum ice_status 129 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi, 130 bool save_bad_pac, bool pad_short_pac, bool double_vlan, 131 struct ice_sq_cd *cd); 132 enum ice_status 133 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 134 struct ice_aqc_get_phy_caps_data *caps, 135 struct ice_sq_cd *cd); 136 void 137 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 138 u16 link_speeds_bitmap); 139 enum ice_status 140 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 141 struct ice_sq_cd *cd); 142 143 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw); 144 enum ice_status 145 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 146 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd); 147 bool ice_fw_supports_link_override(struct ice_hw *hw); 148 enum ice_status 149 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 150 struct ice_port_info *pi); 151 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps); 152 153 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps); 154 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options); 155 enum ice_status 156 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, 157 bool ena_auto_link_update); 158 bool 159 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps, 160 struct ice_aqc_set_phy_cfg_data *cfg); 161 void 162 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 163 struct ice_aqc_get_phy_caps_data *caps, 164 struct ice_aqc_set_phy_cfg_data *cfg); 165 enum ice_status 166 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 167 enum ice_fec_mode fec); 168 enum ice_status 169 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 170 struct ice_sq_cd *cd); 171 enum ice_status 172 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd); 173 enum ice_status 174 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 175 struct ice_link_status *link, struct ice_sq_cd *cd); 176 enum ice_status 177 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 178 struct ice_sq_cd *cd); 179 enum ice_status 180 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd); 181 182 enum ice_status 183 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 184 struct ice_sq_cd *cd); 185 enum ice_status 186 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 187 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 188 bool write, struct ice_sq_cd *cd); 189 190 enum ice_status 191 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info); 192 enum ice_status 193 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 194 u16 *q_handle, u16 *q_ids, u32 *q_teids, 195 enum ice_disq_rst_src rst_src, u16 vmvf_num, 196 struct ice_sq_cd *cd); 197 enum ice_status 198 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 199 u16 *max_lanqs); 200 enum ice_status 201 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 202 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 203 struct ice_sq_cd *cd); 204 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle); 205 void ice_replay_post(struct ice_hw *hw); 206 struct ice_q_ctx * 207 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle); 208 void 209 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 210 u64 *prev_stat, u64 *cur_stat); 211 void 212 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 213 u64 *prev_stat, u64 *cur_stat); 214 void 215 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded, 216 struct ice_eth_stats *cur_stats); 217 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw); 218 void ice_print_rollback_msg(struct ice_hw *hw); 219 enum ice_status 220 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 221 struct ice_aqc_txsched_elem_data *buf); 222 enum ice_status 223 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 224 struct ice_sq_cd *cd); 225 enum ice_status 226 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 227 bool *value, struct ice_sq_cd *cd); 228 enum ice_status 229 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 230 struct ice_sq_cd *cd); 231 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw); 232 enum ice_status 233 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add); 234 enum ice_status 235 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 236 u16 bus_addr, __le16 addr, u8 params, u8 *data, 237 struct ice_sq_cd *cd); 238 enum ice_status 239 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 240 u16 bus_addr, __le16 addr, u8 params, u8 *data, 241 struct ice_sq_cd *cd); 242 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw); 243 #endif /* _ICE_COMMON_H_ */ 244