1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2021 Intel Corporation 3 */ 4 5 #include "ice_common.h" 6 #include "ice_sched.h" 7 #include "ice_adminq_cmd.h" 8 9 #include "ice_flow.h" 10 #include "ice_switch.h" 11 12 #define ICE_PF_RESET_WAIT_COUNT 300 13 14 /** 15 * ice_set_mac_type - Sets MAC type 16 * @hw: pointer to the HW structure 17 * 18 * This function sets the MAC type of the adapter based on the 19 * vendor ID and device ID stored in the HW structure. 20 */ 21 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 22 { 23 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 24 25 if (hw->vendor_id != ICE_INTEL_VENDOR_ID) 26 return ICE_ERR_DEVICE_NOT_SUPPORTED; 27 28 switch (hw->device_id) { 29 case ICE_DEV_ID_E810C_BACKPLANE: 30 case ICE_DEV_ID_E810C_QSFP: 31 case ICE_DEV_ID_E810C_SFP: 32 case ICE_DEV_ID_E810_XXV_BACKPLANE: 33 case ICE_DEV_ID_E810_XXV_QSFP: 34 case ICE_DEV_ID_E810_XXV_SFP: 35 hw->mac_type = ICE_MAC_E810; 36 break; 37 case ICE_DEV_ID_E822C_10G_BASE_T: 38 case ICE_DEV_ID_E822C_BACKPLANE: 39 case ICE_DEV_ID_E822C_QSFP: 40 case ICE_DEV_ID_E822C_SFP: 41 case ICE_DEV_ID_E822C_SGMII: 42 case ICE_DEV_ID_E822L_10G_BASE_T: 43 case ICE_DEV_ID_E822L_BACKPLANE: 44 case ICE_DEV_ID_E822L_SFP: 45 case ICE_DEV_ID_E822L_SGMII: 46 case ICE_DEV_ID_E823L_10G_BASE_T: 47 case ICE_DEV_ID_E823L_1GBE: 48 case ICE_DEV_ID_E823L_BACKPLANE: 49 case ICE_DEV_ID_E823L_QSFP: 50 case ICE_DEV_ID_E823L_SFP: 51 case ICE_DEV_ID_E823C_10G_BASE_T: 52 case ICE_DEV_ID_E823C_BACKPLANE: 53 case ICE_DEV_ID_E823C_QSFP: 54 case ICE_DEV_ID_E823C_SFP: 55 case ICE_DEV_ID_E823C_SGMII: 56 hw->mac_type = ICE_MAC_GENERIC; 57 break; 58 default: 59 hw->mac_type = ICE_MAC_UNKNOWN; 60 break; 61 } 62 63 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 64 return ICE_SUCCESS; 65 } 66 67 /** 68 * ice_clear_pf_cfg - Clear PF configuration 69 * @hw: pointer to the hardware structure 70 * 71 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 72 * configuration, flow director filters, etc.). 73 */ 74 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 75 { 76 struct ice_aq_desc desc; 77 78 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 79 80 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 81 } 82 83 /** 84 * ice_aq_manage_mac_read - manage MAC address read command 85 * @hw: pointer to the HW struct 86 * @buf: a virtual buffer to hold the manage MAC read response 87 * @buf_size: Size of the virtual buffer 88 * @cd: pointer to command details structure or NULL 89 * 90 * This function is used to return per PF station MAC address (0x0107). 91 * NOTE: Upon successful completion of this command, MAC address information 92 * is returned in user specified buffer. Please interpret user specified 93 * buffer as "manage_mac_read" response. 94 * Response such as various MAC addresses are stored in HW struct (port.mac) 95 * ice_discover_dev_caps is expected to be called before this function is 96 * called. 97 */ 98 static enum ice_status 99 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 100 struct ice_sq_cd *cd) 101 { 102 struct ice_aqc_manage_mac_read_resp *resp; 103 struct ice_aqc_manage_mac_read *cmd; 104 struct ice_aq_desc desc; 105 enum ice_status status; 106 u16 flags; 107 u8 i; 108 109 cmd = &desc.params.mac_read; 110 111 if (buf_size < sizeof(*resp)) 112 return ICE_ERR_BUF_TOO_SHORT; 113 114 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 115 116 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 117 if (status) 118 return status; 119 120 resp = (struct ice_aqc_manage_mac_read_resp *)buf; 121 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 122 123 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 124 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 125 return ICE_ERR_CFG; 126 } 127 128 /* A single port can report up to two (LAN and WoL) addresses */ 129 for (i = 0; i < cmd->num_addr; i++) 130 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 131 ice_memcpy(hw->port_info->mac.lan_addr, 132 resp[i].mac_addr, ETH_ALEN, 133 ICE_DMA_TO_NONDMA); 134 ice_memcpy(hw->port_info->mac.perm_addr, 135 resp[i].mac_addr, 136 ETH_ALEN, ICE_DMA_TO_NONDMA); 137 break; 138 } 139 return ICE_SUCCESS; 140 } 141 142 /** 143 * ice_aq_get_phy_caps - returns PHY capabilities 144 * @pi: port information structure 145 * @qual_mods: report qualified modules 146 * @report_mode: report mode capabilities 147 * @pcaps: structure for PHY capabilities to be filled 148 * @cd: pointer to command details structure or NULL 149 * 150 * Returns the various PHY capabilities supported on the Port (0x0600) 151 */ 152 enum ice_status 153 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 154 struct ice_aqc_get_phy_caps_data *pcaps, 155 struct ice_sq_cd *cd) 156 { 157 struct ice_aqc_get_phy_caps *cmd; 158 u16 pcaps_size = sizeof(*pcaps); 159 struct ice_aq_desc desc; 160 enum ice_status status; 161 struct ice_hw *hw; 162 163 cmd = &desc.params.get_phy; 164 165 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 166 return ICE_ERR_PARAM; 167 hw = pi->hw; 168 169 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 170 !ice_fw_supports_report_dflt_cfg(hw)) 171 return ICE_ERR_PARAM; 172 173 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 174 175 if (qual_mods) 176 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM); 177 178 cmd->param0 |= CPU_TO_LE16(report_mode); 179 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 180 181 ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n", 182 report_mode); 183 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 184 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_low)); 185 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 186 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_high)); 187 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps); 188 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 189 pcaps->low_power_ctrl_an); 190 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap); 191 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", 192 pcaps->eeer_value); 193 ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n", 194 pcaps->link_fec_options); 195 ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n", 196 pcaps->module_compliance_enforcement); 197 ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n", 198 pcaps->extended_compliance_code); 199 ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n", 200 pcaps->module_type[0]); 201 ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n", 202 pcaps->module_type[1]); 203 ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n", 204 pcaps->module_type[2]); 205 206 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 207 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low); 208 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high); 209 ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 210 sizeof(pi->phy.link_info.module_type), 211 ICE_NONDMA_TO_NONDMA); 212 } 213 214 return status; 215 } 216 217 /** 218 * ice_aq_get_link_topo_handle - get link topology node return status 219 * @pi: port information structure 220 * @node_type: requested node type 221 * @cd: pointer to command details structure or NULL 222 * 223 * Get link topology node return status for specified node type (0x06E0) 224 * 225 * Node type cage can be used to determine if cage is present. If AQC 226 * returns error (ENOENT), then no cage present. If no cage present, then 227 * connection type is backplane or BASE-T. 228 */ 229 static enum ice_status 230 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 231 struct ice_sq_cd *cd) 232 { 233 struct ice_aqc_get_link_topo *cmd; 234 struct ice_aq_desc desc; 235 236 cmd = &desc.params.get_link_topo; 237 238 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 239 240 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 241 ICE_AQC_LINK_TOPO_NODE_CTX_S); 242 243 /* set node type */ 244 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 245 246 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 247 } 248 249 /** 250 * ice_is_media_cage_present 251 * @pi: port information structure 252 * 253 * Returns true if media cage is present, else false. If no cage, then 254 * media type is backplane or BASE-T. 255 */ 256 static bool ice_is_media_cage_present(struct ice_port_info *pi) 257 { 258 /* Node type cage can be used to determine if cage is present. If AQC 259 * returns error (ENOENT), then no cage present. If no cage present then 260 * connection type is backplane or BASE-T. 261 */ 262 return !ice_aq_get_link_topo_handle(pi, 263 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 264 NULL); 265 } 266 267 /** 268 * ice_get_media_type - Gets media type 269 * @pi: port information structure 270 */ 271 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 272 { 273 struct ice_link_status *hw_link_info; 274 275 if (!pi) 276 return ICE_MEDIA_UNKNOWN; 277 278 hw_link_info = &pi->phy.link_info; 279 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 280 /* If more than one media type is selected, report unknown */ 281 return ICE_MEDIA_UNKNOWN; 282 283 if (hw_link_info->phy_type_low) { 284 /* 1G SGMII is a special case where some DA cable PHYs 285 * may show this as an option when it really shouldn't 286 * be since SGMII is meant to be between a MAC and a PHY 287 * in a backplane. Try to detect this case and handle it 288 */ 289 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 290 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 291 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 292 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 293 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 294 return ICE_MEDIA_DA; 295 296 switch (hw_link_info->phy_type_low) { 297 case ICE_PHY_TYPE_LOW_1000BASE_SX: 298 case ICE_PHY_TYPE_LOW_1000BASE_LX: 299 case ICE_PHY_TYPE_LOW_10GBASE_SR: 300 case ICE_PHY_TYPE_LOW_10GBASE_LR: 301 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 302 case ICE_PHY_TYPE_LOW_25GBASE_SR: 303 case ICE_PHY_TYPE_LOW_25GBASE_LR: 304 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 305 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 306 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 307 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 308 case ICE_PHY_TYPE_LOW_50GBASE_SR: 309 case ICE_PHY_TYPE_LOW_50GBASE_FR: 310 case ICE_PHY_TYPE_LOW_50GBASE_LR: 311 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 312 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 313 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 314 case ICE_PHY_TYPE_LOW_100GBASE_DR: 315 return ICE_MEDIA_FIBER; 316 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 317 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 318 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 319 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 320 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 321 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 322 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 323 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 324 return ICE_MEDIA_FIBER; 325 case ICE_PHY_TYPE_LOW_100BASE_TX: 326 case ICE_PHY_TYPE_LOW_1000BASE_T: 327 case ICE_PHY_TYPE_LOW_2500BASE_T: 328 case ICE_PHY_TYPE_LOW_5GBASE_T: 329 case ICE_PHY_TYPE_LOW_10GBASE_T: 330 case ICE_PHY_TYPE_LOW_25GBASE_T: 331 return ICE_MEDIA_BASET; 332 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 333 case ICE_PHY_TYPE_LOW_25GBASE_CR: 334 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 335 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 336 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 337 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 338 case ICE_PHY_TYPE_LOW_50GBASE_CP: 339 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 340 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 341 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 342 return ICE_MEDIA_DA; 343 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 344 case ICE_PHY_TYPE_LOW_40G_XLAUI: 345 case ICE_PHY_TYPE_LOW_50G_LAUI2: 346 case ICE_PHY_TYPE_LOW_50G_AUI2: 347 case ICE_PHY_TYPE_LOW_50G_AUI1: 348 case ICE_PHY_TYPE_LOW_100G_AUI4: 349 case ICE_PHY_TYPE_LOW_100G_CAUI4: 350 if (ice_is_media_cage_present(pi)) 351 return ICE_MEDIA_AUI; 352 /* fall-through */ 353 case ICE_PHY_TYPE_LOW_1000BASE_KX: 354 case ICE_PHY_TYPE_LOW_2500BASE_KX: 355 case ICE_PHY_TYPE_LOW_2500BASE_X: 356 case ICE_PHY_TYPE_LOW_5GBASE_KR: 357 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 358 case ICE_PHY_TYPE_LOW_25GBASE_KR: 359 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 360 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 361 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 362 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 363 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 364 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 365 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 366 return ICE_MEDIA_BACKPLANE; 367 } 368 } else { 369 switch (hw_link_info->phy_type_high) { 370 case ICE_PHY_TYPE_HIGH_100G_AUI2: 371 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 372 if (ice_is_media_cage_present(pi)) 373 return ICE_MEDIA_AUI; 374 /* fall-through */ 375 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 376 return ICE_MEDIA_BACKPLANE; 377 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 378 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 379 return ICE_MEDIA_FIBER; 380 } 381 } 382 return ICE_MEDIA_UNKNOWN; 383 } 384 385 /** 386 * ice_aq_get_link_info 387 * @pi: port information structure 388 * @ena_lse: enable/disable LinkStatusEvent reporting 389 * @link: pointer to link status structure - optional 390 * @cd: pointer to command details structure or NULL 391 * 392 * Get Link Status (0x607). Returns the link status of the adapter. 393 */ 394 enum ice_status 395 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 396 struct ice_link_status *link, struct ice_sq_cd *cd) 397 { 398 struct ice_aqc_get_link_status_data link_data = { 0 }; 399 struct ice_aqc_get_link_status *resp; 400 struct ice_link_status *li_old, *li; 401 enum ice_media_type *hw_media_type; 402 struct ice_fc_info *hw_fc_info; 403 bool tx_pause, rx_pause; 404 struct ice_aq_desc desc; 405 enum ice_status status; 406 struct ice_hw *hw; 407 u16 cmd_flags; 408 409 if (!pi) 410 return ICE_ERR_PARAM; 411 hw = pi->hw; 412 li_old = &pi->phy.link_info_old; 413 hw_media_type = &pi->phy.media_type; 414 li = &pi->phy.link_info; 415 hw_fc_info = &pi->fc; 416 417 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 418 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 419 resp = &desc.params.get_link_status; 420 resp->cmd_flags = CPU_TO_LE16(cmd_flags); 421 resp->lport_num = pi->lport; 422 423 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 424 425 if (status != ICE_SUCCESS) 426 return status; 427 428 /* save off old link status information */ 429 *li_old = *li; 430 431 /* update current link status information */ 432 li->link_speed = LE16_TO_CPU(link_data.link_speed); 433 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low); 434 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high); 435 *hw_media_type = ice_get_media_type(pi); 436 li->link_info = link_data.link_info; 437 li->link_cfg_err = link_data.link_cfg_err; 438 li->an_info = link_data.an_info; 439 li->ext_info = link_data.ext_info; 440 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size); 441 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 442 li->topo_media_conflict = link_data.topo_media_conflict; 443 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 444 ICE_AQ_CFG_PACING_TYPE_M); 445 446 /* update fc info */ 447 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 448 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 449 if (tx_pause && rx_pause) 450 hw_fc_info->current_mode = ICE_FC_FULL; 451 else if (tx_pause) 452 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 453 else if (rx_pause) 454 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 455 else 456 hw_fc_info->current_mode = ICE_FC_NONE; 457 458 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED)); 459 460 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 461 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 462 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 463 (unsigned long long)li->phy_type_low); 464 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 465 (unsigned long long)li->phy_type_high); 466 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 467 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 468 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 469 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 470 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 471 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 472 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 473 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 474 li->max_frame_size); 475 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 476 477 /* save link status information */ 478 if (link) 479 *link = *li; 480 481 /* flag cleared so calling functions don't call AQ again */ 482 pi->phy.get_link_info = false; 483 484 return ICE_SUCCESS; 485 } 486 487 /** 488 * ice_fill_tx_timer_and_fc_thresh 489 * @hw: pointer to the HW struct 490 * @cmd: pointer to MAC cfg structure 491 * 492 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 493 * descriptor 494 */ 495 static void 496 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 497 struct ice_aqc_set_mac_cfg *cmd) 498 { 499 u16 fc_thres_val, tx_timer_val; 500 u32 val; 501 502 /* We read back the transmit timer and fc threshold value of 503 * LFC. Thus, we will use index = 504 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 505 * 506 * Also, because we are opearating on transmit timer and fc 507 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 508 */ 509 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 510 511 /* Retrieve the transmit timer */ 512 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 513 tx_timer_val = val & 514 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 515 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val); 516 517 /* Retrieve the fc threshold */ 518 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 519 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 520 521 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val); 522 } 523 524 /** 525 * ice_aq_set_mac_cfg 526 * @hw: pointer to the HW struct 527 * @max_frame_size: Maximum Frame Size to be supported 528 * @cd: pointer to command details structure or NULL 529 * 530 * Set MAC configuration (0x0603) 531 */ 532 enum ice_status 533 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 534 { 535 struct ice_aqc_set_mac_cfg *cmd; 536 struct ice_aq_desc desc; 537 538 cmd = &desc.params.set_mac_cfg; 539 540 if (max_frame_size == 0) 541 return ICE_ERR_PARAM; 542 543 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 544 545 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 546 547 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 548 549 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 550 } 551 552 /** 553 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 554 * @hw: pointer to the HW struct 555 */ 556 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 557 { 558 struct ice_switch_info *sw; 559 enum ice_status status; 560 561 hw->switch_info = (struct ice_switch_info *) 562 ice_malloc(hw, sizeof(*hw->switch_info)); 563 564 sw = hw->switch_info; 565 566 if (!sw) 567 return ICE_ERR_NO_MEMORY; 568 569 INIT_LIST_HEAD(&sw->vsi_list_map_head); 570 sw->prof_res_bm_init = 0; 571 572 status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list); 573 if (status) { 574 ice_free(hw, hw->switch_info); 575 return status; 576 } 577 return ICE_SUCCESS; 578 } 579 580 /** 581 * ice_cleanup_fltr_mgmt_single - clears single filter mngt struct 582 * @hw: pointer to the HW struct 583 * @sw: pointer to switch info struct for which function clears filters 584 */ 585 static void 586 ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw) 587 { 588 struct ice_vsi_list_map_info *v_pos_map; 589 struct ice_vsi_list_map_info *v_tmp_map; 590 struct ice_sw_recipe *recps; 591 u8 i; 592 593 if (!sw) 594 return; 595 596 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 597 ice_vsi_list_map_info, list_entry) { 598 LIST_DEL(&v_pos_map->list_entry); 599 ice_free(hw, v_pos_map); 600 } 601 recps = sw->recp_list; 602 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 603 struct ice_recp_grp_entry *rg_entry, *tmprg_entry; 604 605 recps[i].root_rid = i; 606 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry, 607 &recps[i].rg_list, ice_recp_grp_entry, 608 l_entry) { 609 LIST_DEL(&rg_entry->l_entry); 610 ice_free(hw, rg_entry); 611 } 612 613 if (recps[i].adv_rule) { 614 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 615 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 616 617 ice_destroy_lock(&recps[i].filt_rule_lock); 618 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 619 &recps[i].filt_rules, 620 ice_adv_fltr_mgmt_list_entry, 621 list_entry) { 622 LIST_DEL(&lst_itr->list_entry); 623 ice_free(hw, lst_itr->lkups); 624 ice_free(hw, lst_itr); 625 } 626 } else { 627 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 628 629 ice_destroy_lock(&recps[i].filt_rule_lock); 630 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 631 &recps[i].filt_rules, 632 ice_fltr_mgmt_list_entry, 633 list_entry) { 634 LIST_DEL(&lst_itr->list_entry); 635 ice_free(hw, lst_itr); 636 } 637 } 638 if (recps[i].root_buf) 639 ice_free(hw, recps[i].root_buf); 640 } 641 ice_rm_sw_replay_rule_info(hw, sw); 642 ice_free(hw, sw->recp_list); 643 ice_free(hw, sw); 644 } 645 646 /** 647 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 648 * @hw: pointer to the HW struct 649 */ 650 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 651 { 652 ice_cleanup_fltr_mgmt_single(hw, hw->switch_info); 653 } 654 655 /** 656 * ice_get_itr_intrl_gran 657 * @hw: pointer to the HW struct 658 * 659 * Determines the ITR/INTRL granularities based on the maximum aggregate 660 * bandwidth according to the device's configuration during power-on. 661 */ 662 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 663 { 664 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 665 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 666 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 667 668 switch (max_agg_bw) { 669 case ICE_MAX_AGG_BW_200G: 670 case ICE_MAX_AGG_BW_100G: 671 case ICE_MAX_AGG_BW_50G: 672 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 673 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 674 break; 675 case ICE_MAX_AGG_BW_25G: 676 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 677 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 678 break; 679 } 680 } 681 682 /** 683 * ice_print_rollback_msg - print FW rollback message 684 * @hw: pointer to the hardware structure 685 */ 686 void ice_print_rollback_msg(struct ice_hw *hw) 687 { 688 char nvm_str[ICE_NVM_VER_LEN] = { 0 }; 689 struct ice_orom_info *orom; 690 struct ice_nvm_info *nvm; 691 692 orom = &hw->flash.orom; 693 nvm = &hw->flash.nvm; 694 695 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", 696 nvm->major, nvm->minor, nvm->eetrack, orom->major, 697 orom->build, orom->patch); 698 ice_warn(hw, 699 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n", 700 nvm_str, hw->fw_maj_ver, hw->fw_min_ver); 701 } 702 703 /** 704 * ice_init_hw - main hardware initialization routine 705 * @hw: pointer to the hardware structure 706 */ 707 enum ice_status ice_init_hw(struct ice_hw *hw) 708 { 709 struct ice_aqc_get_phy_caps_data *pcaps; 710 enum ice_status status; 711 u16 mac_buf_len; 712 void *mac_buf; 713 714 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 715 716 /* Set MAC type based on DeviceID */ 717 status = ice_set_mac_type(hw); 718 if (status) 719 return status; 720 721 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 722 PF_FUNC_RID_FUNCTION_NUMBER_M) >> 723 PF_FUNC_RID_FUNCTION_NUMBER_S; 724 725 status = ice_reset(hw, ICE_RESET_PFR); 726 if (status) 727 return status; 728 729 ice_get_itr_intrl_gran(hw); 730 731 status = ice_create_all_ctrlq(hw); 732 if (status) 733 goto err_unroll_cqinit; 734 735 status = ice_init_nvm(hw); 736 if (status) 737 goto err_unroll_cqinit; 738 739 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK) 740 ice_print_rollback_msg(hw); 741 742 status = ice_clear_pf_cfg(hw); 743 if (status) 744 goto err_unroll_cqinit; 745 746 /* Set bit to enable Flow Director filters */ 747 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 748 INIT_LIST_HEAD(&hw->fdir_list_head); 749 750 ice_clear_pxe_mode(hw); 751 752 status = ice_get_caps(hw); 753 if (status) 754 goto err_unroll_cqinit; 755 756 hw->port_info = (struct ice_port_info *) 757 ice_malloc(hw, sizeof(*hw->port_info)); 758 if (!hw->port_info) { 759 status = ICE_ERR_NO_MEMORY; 760 goto err_unroll_cqinit; 761 } 762 763 /* set the back pointer to HW */ 764 hw->port_info->hw = hw; 765 766 /* Initialize port_info struct with switch configuration data */ 767 status = ice_get_initial_sw_cfg(hw); 768 if (status) 769 goto err_unroll_alloc; 770 771 hw->evb_veb = true; 772 /* Query the allocated resources for Tx scheduler */ 773 status = ice_sched_query_res_alloc(hw); 774 if (status) { 775 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 776 goto err_unroll_alloc; 777 } 778 ice_sched_get_psm_clk_freq(hw); 779 780 /* Initialize port_info struct with scheduler data */ 781 status = ice_sched_init_port(hw->port_info); 782 if (status) 783 goto err_unroll_sched; 784 pcaps = (struct ice_aqc_get_phy_caps_data *) 785 ice_malloc(hw, sizeof(*pcaps)); 786 if (!pcaps) { 787 status = ICE_ERR_NO_MEMORY; 788 goto err_unroll_sched; 789 } 790 791 /* Initialize port_info struct with PHY capabilities */ 792 status = ice_aq_get_phy_caps(hw->port_info, false, 793 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, NULL); 794 ice_free(hw, pcaps); 795 if (status) 796 ice_warn(hw, "Get PHY capabilities failed status = %d, continuing anyway\n", 797 status); 798 799 /* Initialize port_info struct with link information */ 800 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 801 if (status) 802 goto err_unroll_sched; 803 /* need a valid SW entry point to build a Tx tree */ 804 if (!hw->sw_entry_point_layer) { 805 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 806 status = ICE_ERR_CFG; 807 goto err_unroll_sched; 808 } 809 INIT_LIST_HEAD(&hw->agg_list); 810 /* Initialize max burst size */ 811 if (!hw->max_burst_size) 812 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 813 status = ice_init_fltr_mgmt_struct(hw); 814 if (status) 815 goto err_unroll_sched; 816 817 /* Get MAC information */ 818 /* A single port can report up to two (LAN and WoL) addresses */ 819 mac_buf = ice_calloc(hw, 2, 820 sizeof(struct ice_aqc_manage_mac_read_resp)); 821 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 822 823 if (!mac_buf) { 824 status = ICE_ERR_NO_MEMORY; 825 goto err_unroll_fltr_mgmt_struct; 826 } 827 828 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 829 ice_free(hw, mac_buf); 830 831 if (status) 832 goto err_unroll_fltr_mgmt_struct; 833 /* enable jumbo frame support at MAC level */ 834 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 835 if (status) 836 goto err_unroll_fltr_mgmt_struct; 837 /* Obtain counter base index which would be used by flow director */ 838 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 839 if (status) 840 goto err_unroll_fltr_mgmt_struct; 841 status = ice_init_hw_tbls(hw); 842 if (status) 843 goto err_unroll_fltr_mgmt_struct; 844 ice_init_lock(&hw->tnl_lock); 845 846 return ICE_SUCCESS; 847 848 err_unroll_fltr_mgmt_struct: 849 ice_cleanup_fltr_mgmt_struct(hw); 850 err_unroll_sched: 851 ice_sched_cleanup_all(hw); 852 err_unroll_alloc: 853 ice_free(hw, hw->port_info); 854 hw->port_info = NULL; 855 err_unroll_cqinit: 856 ice_destroy_all_ctrlq(hw); 857 return status; 858 } 859 860 /** 861 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 862 * @hw: pointer to the hardware structure 863 * 864 * This should be called only during nominal operation, not as a result of 865 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 866 * applicable initializations if it fails for any reason. 867 */ 868 void ice_deinit_hw(struct ice_hw *hw) 869 { 870 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 871 ice_cleanup_fltr_mgmt_struct(hw); 872 873 ice_sched_cleanup_all(hw); 874 ice_sched_clear_agg(hw); 875 ice_free_seg(hw); 876 ice_free_hw_tbls(hw); 877 ice_destroy_lock(&hw->tnl_lock); 878 879 if (hw->port_info) { 880 ice_free(hw, hw->port_info); 881 hw->port_info = NULL; 882 } 883 884 ice_destroy_all_ctrlq(hw); 885 886 /* Clear VSI contexts if not already cleared */ 887 ice_clear_all_vsi_ctx(hw); 888 } 889 890 /** 891 * ice_check_reset - Check to see if a global reset is complete 892 * @hw: pointer to the hardware structure 893 */ 894 enum ice_status ice_check_reset(struct ice_hw *hw) 895 { 896 u32 cnt, reg = 0, grst_timeout, uld_mask; 897 898 /* Poll for Device Active state in case a recent CORER, GLOBR, 899 * or EMPR has occurred. The grst delay value is in 100ms units. 900 * Add 1sec for outstanding AQ commands that can take a long time. 901 */ 902 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 903 GLGEN_RSTCTL_GRSTDEL_S) + 10; 904 905 for (cnt = 0; cnt < grst_timeout; cnt++) { 906 ice_msec_delay(100, true); 907 reg = rd32(hw, GLGEN_RSTAT); 908 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 909 break; 910 } 911 912 if (cnt == grst_timeout) { 913 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 914 return ICE_ERR_RESET_FAILED; 915 } 916 917 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 918 GLNVM_ULD_PCIER_DONE_1_M |\ 919 GLNVM_ULD_CORER_DONE_M |\ 920 GLNVM_ULD_GLOBR_DONE_M |\ 921 GLNVM_ULD_POR_DONE_M |\ 922 GLNVM_ULD_POR_DONE_1_M |\ 923 GLNVM_ULD_PCIER_DONE_2_M) 924 925 uld_mask = ICE_RESET_DONE_MASK; 926 927 /* Device is Active; check Global Reset processes are done */ 928 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 929 reg = rd32(hw, GLNVM_ULD) & uld_mask; 930 if (reg == uld_mask) { 931 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 932 break; 933 } 934 ice_msec_delay(10, true); 935 } 936 937 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 938 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 939 reg); 940 return ICE_ERR_RESET_FAILED; 941 } 942 943 return ICE_SUCCESS; 944 } 945 946 /** 947 * ice_pf_reset - Reset the PF 948 * @hw: pointer to the hardware structure 949 * 950 * If a global reset has been triggered, this function checks 951 * for its completion and then issues the PF reset 952 */ 953 static enum ice_status ice_pf_reset(struct ice_hw *hw) 954 { 955 u32 cnt, reg; 956 957 /* If at function entry a global reset was already in progress, i.e. 958 * state is not 'device active' or any of the reset done bits are not 959 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 960 * global reset is done. 961 */ 962 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 963 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 964 /* poll on global reset currently in progress until done */ 965 if (ice_check_reset(hw)) 966 return ICE_ERR_RESET_FAILED; 967 968 return ICE_SUCCESS; 969 } 970 971 /* Reset the PF */ 972 reg = rd32(hw, PFGEN_CTRL); 973 974 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 975 976 /* Wait for the PFR to complete. The wait time is the global config lock 977 * timeout plus the PFR timeout which will account for a possible reset 978 * that is occurring during a download package operation. 979 */ 980 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 981 ICE_PF_RESET_WAIT_COUNT; cnt++) { 982 reg = rd32(hw, PFGEN_CTRL); 983 if (!(reg & PFGEN_CTRL_PFSWR_M)) 984 break; 985 986 ice_msec_delay(1, true); 987 } 988 989 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 990 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 991 return ICE_ERR_RESET_FAILED; 992 } 993 994 return ICE_SUCCESS; 995 } 996 997 /** 998 * ice_reset - Perform different types of reset 999 * @hw: pointer to the hardware structure 1000 * @req: reset request 1001 * 1002 * This function triggers a reset as specified by the req parameter. 1003 * 1004 * Note: 1005 * If anything other than a PF reset is triggered, PXE mode is restored. 1006 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1007 * interface has been restored in the rebuild flow. 1008 */ 1009 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1010 { 1011 u32 val = 0; 1012 1013 switch (req) { 1014 case ICE_RESET_PFR: 1015 return ice_pf_reset(hw); 1016 case ICE_RESET_CORER: 1017 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1018 val = GLGEN_RTRIG_CORER_M; 1019 break; 1020 case ICE_RESET_GLOBR: 1021 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1022 val = GLGEN_RTRIG_GLOBR_M; 1023 break; 1024 default: 1025 return ICE_ERR_PARAM; 1026 } 1027 1028 val |= rd32(hw, GLGEN_RTRIG); 1029 wr32(hw, GLGEN_RTRIG, val); 1030 ice_flush(hw); 1031 1032 /* wait for the FW to be ready */ 1033 return ice_check_reset(hw); 1034 } 1035 1036 /** 1037 * ice_copy_rxq_ctx_to_hw 1038 * @hw: pointer to the hardware structure 1039 * @ice_rxq_ctx: pointer to the rxq context 1040 * @rxq_index: the index of the Rx queue 1041 * 1042 * Copies rxq context from dense structure to HW register space 1043 */ 1044 static enum ice_status 1045 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1046 { 1047 u8 i; 1048 1049 if (!ice_rxq_ctx) 1050 return ICE_ERR_BAD_PTR; 1051 1052 if (rxq_index > QRX_CTRL_MAX_INDEX) 1053 return ICE_ERR_PARAM; 1054 1055 /* Copy each dword separately to HW */ 1056 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1057 wr32(hw, QRX_CONTEXT(i, rxq_index), 1058 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1059 1060 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1061 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1062 } 1063 1064 return ICE_SUCCESS; 1065 } 1066 1067 /* LAN Rx Queue Context */ 1068 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1069 /* Field Width LSB */ 1070 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1071 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1072 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1073 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1074 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1075 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1076 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1077 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1078 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1079 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1080 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1081 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1082 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1083 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1084 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1085 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1086 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1087 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1088 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1089 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1090 { 0 } 1091 }; 1092 1093 /** 1094 * ice_write_rxq_ctx 1095 * @hw: pointer to the hardware structure 1096 * @rlan_ctx: pointer to the rxq context 1097 * @rxq_index: the index of the Rx queue 1098 * 1099 * Converts rxq context from sparse to dense structure and then writes 1100 * it to HW register space and enables the hardware to prefetch descriptors 1101 * instead of only fetching them on demand 1102 */ 1103 enum ice_status 1104 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1105 u32 rxq_index) 1106 { 1107 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1108 1109 if (!rlan_ctx) 1110 return ICE_ERR_BAD_PTR; 1111 1112 rlan_ctx->prefena = 1; 1113 1114 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1115 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1116 } 1117 1118 /** 1119 * ice_clear_rxq_ctx 1120 * @hw: pointer to the hardware structure 1121 * @rxq_index: the index of the Rx queue to clear 1122 * 1123 * Clears rxq context in HW register space 1124 */ 1125 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index) 1126 { 1127 u8 i; 1128 1129 if (rxq_index > QRX_CTRL_MAX_INDEX) 1130 return ICE_ERR_PARAM; 1131 1132 /* Clear each dword register separately */ 1133 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) 1134 wr32(hw, QRX_CONTEXT(i, rxq_index), 0); 1135 1136 return ICE_SUCCESS; 1137 } 1138 1139 /* LAN Tx Queue Context */ 1140 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1141 /* Field Width LSB */ 1142 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1143 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1144 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1145 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1146 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1147 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1148 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1149 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1150 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1151 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1152 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1153 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1154 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1155 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1156 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1157 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1158 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1159 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1160 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1161 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1162 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1163 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1164 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1165 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1166 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1167 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1168 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1169 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1170 { 0 } 1171 }; 1172 1173 /** 1174 * ice_copy_tx_cmpltnq_ctx_to_hw 1175 * @hw: pointer to the hardware structure 1176 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context 1177 * @tx_cmpltnq_index: the index of the completion queue 1178 * 1179 * Copies Tx completion queue context from dense structure to HW register space 1180 */ 1181 static enum ice_status 1182 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx, 1183 u32 tx_cmpltnq_index) 1184 { 1185 u8 i; 1186 1187 if (!ice_tx_cmpltnq_ctx) 1188 return ICE_ERR_BAD_PTR; 1189 1190 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 1191 return ICE_ERR_PARAM; 1192 1193 /* Copy each dword separately to HW */ 1194 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) { 1195 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 1196 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 1197 1198 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i, 1199 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 1200 } 1201 1202 return ICE_SUCCESS; 1203 } 1204 1205 /* LAN Tx Completion Queue Context */ 1206 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = { 1207 /* Field Width LSB */ 1208 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0), 1209 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64), 1210 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96), 1211 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97), 1212 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128), 1213 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131), 1214 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141), 1215 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160), 1216 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161), 1217 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192), 1218 { 0 } 1219 }; 1220 1221 /** 1222 * ice_write_tx_cmpltnq_ctx 1223 * @hw: pointer to the hardware structure 1224 * @tx_cmpltnq_ctx: pointer to the completion queue context 1225 * @tx_cmpltnq_index: the index of the completion queue 1226 * 1227 * Converts completion queue context from sparse to dense structure and then 1228 * writes it to HW register space 1229 */ 1230 enum ice_status 1231 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw, 1232 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx, 1233 u32 tx_cmpltnq_index) 1234 { 1235 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 1236 1237 ice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info); 1238 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index); 1239 } 1240 1241 /** 1242 * ice_clear_tx_cmpltnq_ctx 1243 * @hw: pointer to the hardware structure 1244 * @tx_cmpltnq_index: the index of the completion queue to clear 1245 * 1246 * Clears Tx completion queue context in HW register space 1247 */ 1248 enum ice_status 1249 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index) 1250 { 1251 u8 i; 1252 1253 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 1254 return ICE_ERR_PARAM; 1255 1256 /* Clear each dword register separately */ 1257 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) 1258 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0); 1259 1260 return ICE_SUCCESS; 1261 } 1262 1263 /** 1264 * ice_copy_tx_drbell_q_ctx_to_hw 1265 * @hw: pointer to the hardware structure 1266 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context 1267 * @tx_drbell_q_index: the index of the doorbell queue 1268 * 1269 * Copies doorbell queue context from dense structure to HW register space 1270 */ 1271 static enum ice_status 1272 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx, 1273 u32 tx_drbell_q_index) 1274 { 1275 u8 i; 1276 1277 if (!ice_tx_drbell_q_ctx) 1278 return ICE_ERR_BAD_PTR; 1279 1280 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 1281 return ICE_ERR_PARAM; 1282 1283 /* Copy each dword separately to HW */ 1284 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) { 1285 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 1286 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 1287 1288 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i, 1289 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 1290 } 1291 1292 return ICE_SUCCESS; 1293 } 1294 1295 /* LAN Tx Doorbell Queue Context info */ 1296 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = { 1297 /* Field Width LSB */ 1298 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0), 1299 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64), 1300 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80), 1301 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84), 1302 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94), 1303 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96), 1304 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104), 1305 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108), 1306 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112), 1307 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128), 1308 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144), 1309 { 0 } 1310 }; 1311 1312 /** 1313 * ice_write_tx_drbell_q_ctx 1314 * @hw: pointer to the hardware structure 1315 * @tx_drbell_q_ctx: pointer to the doorbell queue context 1316 * @tx_drbell_q_index: the index of the doorbell queue 1317 * 1318 * Converts doorbell queue context from sparse to dense structure and then 1319 * writes it to HW register space 1320 */ 1321 enum ice_status 1322 ice_write_tx_drbell_q_ctx(struct ice_hw *hw, 1323 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx, 1324 u32 tx_drbell_q_index) 1325 { 1326 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 1327 1328 ice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf, 1329 ice_tx_drbell_q_ctx_info); 1330 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index); 1331 } 1332 1333 /** 1334 * ice_clear_tx_drbell_q_ctx 1335 * @hw: pointer to the hardware structure 1336 * @tx_drbell_q_index: the index of the doorbell queue to clear 1337 * 1338 * Clears doorbell queue context in HW register space 1339 */ 1340 enum ice_status 1341 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index) 1342 { 1343 u8 i; 1344 1345 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 1346 return ICE_ERR_PARAM; 1347 1348 /* Clear each dword register separately */ 1349 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) 1350 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0); 1351 1352 return ICE_SUCCESS; 1353 } 1354 1355 /* FW Admin Queue command wrappers */ 1356 1357 /** 1358 * ice_should_retry_sq_send_cmd 1359 * @opcode: AQ opcode 1360 * 1361 * Decide if we should retry the send command routine for the ATQ, depending 1362 * on the opcode. 1363 */ 1364 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1365 { 1366 switch (opcode) { 1367 case ice_aqc_opc_get_link_topo: 1368 case ice_aqc_opc_lldp_stop: 1369 case ice_aqc_opc_lldp_start: 1370 case ice_aqc_opc_lldp_filter_ctrl: 1371 return true; 1372 } 1373 1374 return false; 1375 } 1376 1377 /** 1378 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1379 * @hw: pointer to the HW struct 1380 * @cq: pointer to the specific Control queue 1381 * @desc: prefilled descriptor describing the command 1382 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1383 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1384 * @cd: pointer to command details structure 1385 * 1386 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1387 * Queue if the EBUSY AQ error is returned. 1388 */ 1389 static enum ice_status 1390 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1391 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1392 struct ice_sq_cd *cd) 1393 { 1394 struct ice_aq_desc desc_cpy; 1395 enum ice_status status; 1396 bool is_cmd_for_retry; 1397 u8 *buf_cpy = NULL; 1398 u8 idx = 0; 1399 u16 opcode; 1400 1401 opcode = LE16_TO_CPU(desc->opcode); 1402 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1403 ice_memset(&desc_cpy, 0, sizeof(desc_cpy), ICE_NONDMA_MEM); 1404 1405 if (is_cmd_for_retry) { 1406 if (buf) { 1407 buf_cpy = (u8 *)ice_malloc(hw, buf_size); 1408 if (!buf_cpy) 1409 return ICE_ERR_NO_MEMORY; 1410 } 1411 1412 ice_memcpy(&desc_cpy, desc, sizeof(desc_cpy), 1413 ICE_NONDMA_TO_NONDMA); 1414 } 1415 1416 do { 1417 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1418 1419 if (!is_cmd_for_retry || status == ICE_SUCCESS || 1420 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1421 break; 1422 1423 if (buf_cpy) 1424 ice_memcpy(buf, buf_cpy, buf_size, 1425 ICE_NONDMA_TO_NONDMA); 1426 1427 ice_memcpy(desc, &desc_cpy, sizeof(desc_cpy), 1428 ICE_NONDMA_TO_NONDMA); 1429 1430 ice_msec_delay(ICE_SQ_SEND_DELAY_TIME_MS, false); 1431 1432 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1433 1434 if (buf_cpy) 1435 ice_free(hw, buf_cpy); 1436 1437 return status; 1438 } 1439 1440 /** 1441 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1442 * @hw: pointer to the HW struct 1443 * @desc: descriptor describing the command 1444 * @buf: buffer to use for indirect commands (NULL for direct commands) 1445 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1446 * @cd: pointer to command details structure 1447 * 1448 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1449 */ 1450 enum ice_status 1451 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1452 u16 buf_size, struct ice_sq_cd *cd) 1453 { 1454 if (hw->aq_send_cmd_fn) { 1455 enum ice_status status = ICE_ERR_NOT_READY; 1456 u16 retval = ICE_AQ_RC_OK; 1457 1458 ice_acquire_lock(&hw->adminq.sq_lock); 1459 if (!hw->aq_send_cmd_fn(hw->aq_send_cmd_param, desc, 1460 buf, buf_size)) { 1461 retval = LE16_TO_CPU(desc->retval); 1462 /* strip off FW internal code */ 1463 if (retval) 1464 retval &= 0xff; 1465 if (retval == ICE_AQ_RC_OK) 1466 status = ICE_SUCCESS; 1467 else 1468 status = ICE_ERR_AQ_ERROR; 1469 } 1470 1471 hw->adminq.sq_last_status = (enum ice_aq_err)retval; 1472 ice_release_lock(&hw->adminq.sq_lock); 1473 1474 return status; 1475 } 1476 return ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1477 } 1478 1479 /** 1480 * ice_aq_get_fw_ver 1481 * @hw: pointer to the HW struct 1482 * @cd: pointer to command details structure or NULL 1483 * 1484 * Get the firmware version (0x0001) from the admin queue commands 1485 */ 1486 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1487 { 1488 struct ice_aqc_get_ver *resp; 1489 struct ice_aq_desc desc; 1490 enum ice_status status; 1491 1492 resp = &desc.params.get_ver; 1493 1494 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1495 1496 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1497 1498 if (!status) { 1499 hw->fw_branch = resp->fw_branch; 1500 hw->fw_maj_ver = resp->fw_major; 1501 hw->fw_min_ver = resp->fw_minor; 1502 hw->fw_patch = resp->fw_patch; 1503 hw->fw_build = LE32_TO_CPU(resp->fw_build); 1504 hw->api_branch = resp->api_branch; 1505 hw->api_maj_ver = resp->api_major; 1506 hw->api_min_ver = resp->api_minor; 1507 hw->api_patch = resp->api_patch; 1508 } 1509 1510 return status; 1511 } 1512 1513 /** 1514 * ice_aq_send_driver_ver 1515 * @hw: pointer to the HW struct 1516 * @dv: driver's major, minor version 1517 * @cd: pointer to command details structure or NULL 1518 * 1519 * Send the driver version (0x0002) to the firmware 1520 */ 1521 enum ice_status 1522 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1523 struct ice_sq_cd *cd) 1524 { 1525 struct ice_aqc_driver_ver *cmd; 1526 struct ice_aq_desc desc; 1527 u16 len; 1528 1529 cmd = &desc.params.driver_ver; 1530 1531 if (!dv) 1532 return ICE_ERR_PARAM; 1533 1534 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1535 1536 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 1537 cmd->major_ver = dv->major_ver; 1538 cmd->minor_ver = dv->minor_ver; 1539 cmd->build_ver = dv->build_ver; 1540 cmd->subbuild_ver = dv->subbuild_ver; 1541 1542 len = 0; 1543 while (len < sizeof(dv->driver_string) && 1544 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len]) 1545 len++; 1546 1547 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1548 } 1549 1550 /** 1551 * ice_aq_q_shutdown 1552 * @hw: pointer to the HW struct 1553 * @unloading: is the driver unloading itself 1554 * 1555 * Tell the Firmware that we're shutting down the AdminQ and whether 1556 * or not the driver is unloading as well (0x0003). 1557 */ 1558 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1559 { 1560 struct ice_aqc_q_shutdown *cmd; 1561 struct ice_aq_desc desc; 1562 1563 cmd = &desc.params.q_shutdown; 1564 1565 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1566 1567 if (unloading) 1568 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1569 1570 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1571 } 1572 1573 /** 1574 * ice_aq_req_res 1575 * @hw: pointer to the HW struct 1576 * @res: resource ID 1577 * @access: access type 1578 * @sdp_number: resource number 1579 * @timeout: the maximum time in ms that the driver may hold the resource 1580 * @cd: pointer to command details structure or NULL 1581 * 1582 * Requests common resource using the admin queue commands (0x0008). 1583 * When attempting to acquire the Global Config Lock, the driver can 1584 * learn of three states: 1585 * 1) ICE_SUCCESS - acquired lock, and can perform download package 1586 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1587 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1588 * successfully downloaded the package; the driver does 1589 * not have to download the package and can continue 1590 * loading 1591 * 1592 * Note that if the caller is in an acquire lock, perform action, release lock 1593 * phase of operation, it is possible that the FW may detect a timeout and issue 1594 * a CORER. In this case, the driver will receive a CORER interrupt and will 1595 * have to determine its cause. The calling thread that is handling this flow 1596 * will likely get an error propagated back to it indicating the Download 1597 * Package, Update Package or the Release Resource AQ commands timed out. 1598 */ 1599 static enum ice_status 1600 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1601 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1602 struct ice_sq_cd *cd) 1603 { 1604 struct ice_aqc_req_res *cmd_resp; 1605 struct ice_aq_desc desc; 1606 enum ice_status status; 1607 1608 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1609 1610 cmd_resp = &desc.params.res_owner; 1611 1612 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1613 1614 cmd_resp->res_id = CPU_TO_LE16(res); 1615 cmd_resp->access_type = CPU_TO_LE16(access); 1616 cmd_resp->res_number = CPU_TO_LE32(sdp_number); 1617 cmd_resp->timeout = CPU_TO_LE32(*timeout); 1618 *timeout = 0; 1619 1620 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1621 1622 /* The completion specifies the maximum time in ms that the driver 1623 * may hold the resource in the Timeout field. 1624 */ 1625 1626 /* Global config lock response utilizes an additional status field. 1627 * 1628 * If the Global config lock resource is held by some other driver, the 1629 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1630 * and the timeout field indicates the maximum time the current owner 1631 * of the resource has to free it. 1632 */ 1633 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1634 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1635 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1636 return ICE_SUCCESS; 1637 } else if (LE16_TO_CPU(cmd_resp->status) == 1638 ICE_AQ_RES_GLBL_IN_PROG) { 1639 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1640 return ICE_ERR_AQ_ERROR; 1641 } else if (LE16_TO_CPU(cmd_resp->status) == 1642 ICE_AQ_RES_GLBL_DONE) { 1643 return ICE_ERR_AQ_NO_WORK; 1644 } 1645 1646 /* invalid FW response, force a timeout immediately */ 1647 *timeout = 0; 1648 return ICE_ERR_AQ_ERROR; 1649 } 1650 1651 /* If the resource is held by some other driver, the command completes 1652 * with a busy return value and the timeout field indicates the maximum 1653 * time the current owner of the resource has to free it. 1654 */ 1655 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1656 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1657 1658 return status; 1659 } 1660 1661 /** 1662 * ice_aq_release_res 1663 * @hw: pointer to the HW struct 1664 * @res: resource ID 1665 * @sdp_number: resource number 1666 * @cd: pointer to command details structure or NULL 1667 * 1668 * release common resource using the admin queue commands (0x0009) 1669 */ 1670 static enum ice_status 1671 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1672 struct ice_sq_cd *cd) 1673 { 1674 struct ice_aqc_req_res *cmd; 1675 struct ice_aq_desc desc; 1676 1677 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1678 1679 cmd = &desc.params.res_owner; 1680 1681 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1682 1683 cmd->res_id = CPU_TO_LE16(res); 1684 cmd->res_number = CPU_TO_LE32(sdp_number); 1685 1686 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1687 } 1688 1689 /** 1690 * ice_acquire_res 1691 * @hw: pointer to the HW structure 1692 * @res: resource ID 1693 * @access: access type (read or write) 1694 * @timeout: timeout in milliseconds 1695 * 1696 * This function will attempt to acquire the ownership of a resource. 1697 */ 1698 enum ice_status 1699 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1700 enum ice_aq_res_access_type access, u32 timeout) 1701 { 1702 #define ICE_RES_POLLING_DELAY_MS 10 1703 u32 delay = ICE_RES_POLLING_DELAY_MS; 1704 u32 time_left = timeout; 1705 enum ice_status status; 1706 1707 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1708 1709 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1710 1711 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 1712 * previously acquired the resource and performed any necessary updates; 1713 * in this case the caller does not obtain the resource and has no 1714 * further work to do. 1715 */ 1716 if (status == ICE_ERR_AQ_NO_WORK) 1717 goto ice_acquire_res_exit; 1718 1719 if (status) 1720 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 1721 1722 /* If necessary, poll until the current lock owner timeouts */ 1723 timeout = time_left; 1724 while (status && timeout && time_left) { 1725 ice_msec_delay(delay, true); 1726 timeout = (timeout > delay) ? timeout - delay : 0; 1727 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1728 1729 if (status == ICE_ERR_AQ_NO_WORK) 1730 /* lock free, but no work to do */ 1731 break; 1732 1733 if (!status) 1734 /* lock acquired */ 1735 break; 1736 } 1737 if (status && status != ICE_ERR_AQ_NO_WORK) 1738 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1739 1740 ice_acquire_res_exit: 1741 if (status == ICE_ERR_AQ_NO_WORK) { 1742 if (access == ICE_RES_WRITE) 1743 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 1744 else 1745 ice_debug(hw, ICE_DBG_RES, "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1746 } 1747 return status; 1748 } 1749 1750 /** 1751 * ice_release_res 1752 * @hw: pointer to the HW structure 1753 * @res: resource ID 1754 * 1755 * This function will release a resource using the proper Admin Command. 1756 */ 1757 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1758 { 1759 enum ice_status status; 1760 u32 total_delay = 0; 1761 1762 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1763 1764 status = ice_aq_release_res(hw, res, 0, NULL); 1765 1766 /* there are some rare cases when trying to release the resource 1767 * results in an admin queue timeout, so handle them correctly 1768 */ 1769 while ((status == ICE_ERR_AQ_TIMEOUT) && 1770 (total_delay < hw->adminq.sq_cmd_timeout)) { 1771 ice_msec_delay(1, true); 1772 status = ice_aq_release_res(hw, res, 0, NULL); 1773 total_delay++; 1774 } 1775 } 1776 1777 /** 1778 * ice_aq_alloc_free_res - command to allocate/free resources 1779 * @hw: pointer to the HW struct 1780 * @num_entries: number of resource entries in buffer 1781 * @buf: Indirect buffer to hold data parameters and response 1782 * @buf_size: size of buffer for indirect commands 1783 * @opc: pass in the command opcode 1784 * @cd: pointer to command details structure or NULL 1785 * 1786 * Helper function to allocate/free resources using the admin queue commands 1787 */ 1788 enum ice_status 1789 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 1790 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1791 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1792 { 1793 struct ice_aqc_alloc_free_res_cmd *cmd; 1794 struct ice_aq_desc desc; 1795 1796 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1797 1798 cmd = &desc.params.sw_res_ctrl; 1799 1800 if (!buf) 1801 return ICE_ERR_PARAM; 1802 1803 if (buf_size < FLEX_ARRAY_SIZE(buf, elem, num_entries)) 1804 return ICE_ERR_PARAM; 1805 1806 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1807 1808 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 1809 1810 cmd->num_entries = CPU_TO_LE16(num_entries); 1811 1812 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1813 } 1814 1815 /** 1816 * ice_alloc_hw_res - allocate resource 1817 * @hw: pointer to the HW struct 1818 * @type: type of resource 1819 * @num: number of resources to allocate 1820 * @btm: allocate from bottom 1821 * @res: pointer to array that will receive the resources 1822 */ 1823 enum ice_status 1824 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 1825 { 1826 struct ice_aqc_alloc_free_res_elem *buf; 1827 enum ice_status status; 1828 u16 buf_len; 1829 1830 buf_len = ice_struct_size(buf, elem, num); 1831 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); 1832 if (!buf) 1833 return ICE_ERR_NO_MEMORY; 1834 1835 /* Prepare buffer to allocate resource. */ 1836 buf->num_elems = CPU_TO_LE16(num); 1837 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 1838 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 1839 if (btm) 1840 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 1841 1842 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 1843 ice_aqc_opc_alloc_res, NULL); 1844 if (status) 1845 goto ice_alloc_res_exit; 1846 1847 ice_memcpy(res, buf->elem, sizeof(*buf->elem) * num, 1848 ICE_NONDMA_TO_NONDMA); 1849 1850 ice_alloc_res_exit: 1851 ice_free(hw, buf); 1852 return status; 1853 } 1854 1855 /** 1856 * ice_free_hw_res - free allocated HW resource 1857 * @hw: pointer to the HW struct 1858 * @type: type of resource to free 1859 * @num: number of resources 1860 * @res: pointer to array that contains the resources to free 1861 */ 1862 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 1863 { 1864 struct ice_aqc_alloc_free_res_elem *buf; 1865 enum ice_status status; 1866 u16 buf_len; 1867 1868 buf_len = ice_struct_size(buf, elem, num); 1869 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); 1870 if (!buf) 1871 return ICE_ERR_NO_MEMORY; 1872 1873 /* Prepare buffer to free resource. */ 1874 buf->num_elems = CPU_TO_LE16(num); 1875 buf->res_type = CPU_TO_LE16(type); 1876 ice_memcpy(buf->elem, res, sizeof(*buf->elem) * num, 1877 ICE_NONDMA_TO_NONDMA); 1878 1879 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 1880 ice_aqc_opc_free_res, NULL); 1881 if (status) 1882 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 1883 1884 ice_free(hw, buf); 1885 return status; 1886 } 1887 1888 /** 1889 * ice_get_num_per_func - determine number of resources per PF 1890 * @hw: pointer to the HW structure 1891 * @max: value to be evenly split between each PF 1892 * 1893 * Determine the number of valid functions by going through the bitmap returned 1894 * from parsing capabilities and use this to calculate the number of resources 1895 * per PF based on the max value passed in. 1896 */ 1897 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 1898 { 1899 u8 funcs; 1900 1901 #define ICE_CAPS_VALID_FUNCS_M 0xFF 1902 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions & 1903 ICE_CAPS_VALID_FUNCS_M); 1904 1905 if (!funcs) 1906 return 0; 1907 1908 return max / funcs; 1909 } 1910 1911 /** 1912 * ice_parse_common_caps - parse common device/function capabilities 1913 * @hw: pointer to the HW struct 1914 * @caps: pointer to common capabilities structure 1915 * @elem: the capability element to parse 1916 * @prefix: message prefix for tracing capabilities 1917 * 1918 * Given a capability element, extract relevant details into the common 1919 * capability structure. 1920 * 1921 * Returns: true if the capability matches one of the common capability ids, 1922 * false otherwise. 1923 */ 1924 static bool 1925 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 1926 struct ice_aqc_list_caps_elem *elem, const char *prefix) 1927 { 1928 u32 logical_id = LE32_TO_CPU(elem->logical_id); 1929 u32 phys_id = LE32_TO_CPU(elem->phys_id); 1930 u32 number = LE32_TO_CPU(elem->number); 1931 u16 cap = LE16_TO_CPU(elem->cap); 1932 bool found = true; 1933 1934 switch (cap) { 1935 case ICE_AQC_CAPS_VALID_FUNCTIONS: 1936 caps->valid_functions = number; 1937 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 1938 caps->valid_functions); 1939 break; 1940 case ICE_AQC_CAPS_DCB: 1941 caps->dcb = (number == 1); 1942 caps->active_tc_bitmap = logical_id; 1943 caps->maxtc = phys_id; 1944 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 1945 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 1946 caps->active_tc_bitmap); 1947 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 1948 break; 1949 case ICE_AQC_CAPS_RSS: 1950 caps->rss_table_size = number; 1951 caps->rss_table_entry_width = logical_id; 1952 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 1953 caps->rss_table_size); 1954 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 1955 caps->rss_table_entry_width); 1956 break; 1957 case ICE_AQC_CAPS_RXQS: 1958 caps->num_rxq = number; 1959 caps->rxq_first_id = phys_id; 1960 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 1961 caps->num_rxq); 1962 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 1963 caps->rxq_first_id); 1964 break; 1965 case ICE_AQC_CAPS_TXQS: 1966 caps->num_txq = number; 1967 caps->txq_first_id = phys_id; 1968 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 1969 caps->num_txq); 1970 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 1971 caps->txq_first_id); 1972 break; 1973 case ICE_AQC_CAPS_MSIX: 1974 caps->num_msix_vectors = number; 1975 caps->msix_vector_first_id = phys_id; 1976 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 1977 caps->num_msix_vectors); 1978 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 1979 caps->msix_vector_first_id); 1980 break; 1981 case ICE_AQC_CAPS_NVM_MGMT: 1982 caps->sec_rev_disabled = 1983 (number & ICE_NVM_MGMT_SEC_REV_DISABLED) ? 1984 true : false; 1985 ice_debug(hw, ICE_DBG_INIT, "%s: sec_rev_disabled = %d\n", prefix, 1986 caps->sec_rev_disabled); 1987 caps->update_disabled = 1988 (number & ICE_NVM_MGMT_UPDATE_DISABLED) ? 1989 true : false; 1990 ice_debug(hw, ICE_DBG_INIT, "%s: update_disabled = %d\n", prefix, 1991 caps->update_disabled); 1992 caps->nvm_unified_update = 1993 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 1994 true : false; 1995 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 1996 caps->nvm_unified_update); 1997 break; 1998 case ICE_AQC_CAPS_MAX_MTU: 1999 caps->max_mtu = number; 2000 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2001 prefix, caps->max_mtu); 2002 break; 2003 default: 2004 /* Not one of the recognized common capabilities */ 2005 found = false; 2006 } 2007 2008 return found; 2009 } 2010 2011 /** 2012 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2013 * @hw: pointer to the HW structure 2014 * @caps: pointer to capabilities structure to fix 2015 * 2016 * Re-calculate the capabilities that are dependent on the number of physical 2017 * ports; i.e. some features are not supported or function differently on 2018 * devices with more than 4 ports. 2019 */ 2020 static void 2021 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2022 { 2023 /* This assumes device capabilities are always scanned before function 2024 * capabilities during the initialization flow. 2025 */ 2026 if (hw->dev_caps.num_funcs > 4) { 2027 /* Max 4 TCs per port */ 2028 caps->maxtc = 4; 2029 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2030 caps->maxtc); 2031 } 2032 } 2033 2034 /** 2035 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2036 * @hw: pointer to the HW struct 2037 * @func_p: pointer to function capabilities structure 2038 * @cap: pointer to the capability element to parse 2039 * 2040 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2041 */ 2042 static void 2043 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2044 struct ice_aqc_list_caps_elem *cap) 2045 { 2046 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2047 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2048 LE32_TO_CPU(cap->number)); 2049 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2050 func_p->guar_num_vsi); 2051 } 2052 2053 /** 2054 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2055 * @hw: pointer to the HW struct 2056 * @func_p: pointer to function capabilities structure 2057 * 2058 * Extract function capabilities for ICE_AQC_CAPS_FD. 2059 */ 2060 static void 2061 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2062 { 2063 u32 reg_val, val; 2064 2065 if (hw->dcf_enabled) 2066 return; 2067 reg_val = rd32(hw, GLQF_FD_SIZE); 2068 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 2069 GLQF_FD_SIZE_FD_GSIZE_S; 2070 func_p->fd_fltr_guar = 2071 ice_get_num_per_func(hw, val); 2072 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 2073 GLQF_FD_SIZE_FD_BSIZE_S; 2074 func_p->fd_fltr_best_effort = val; 2075 2076 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2077 func_p->fd_fltr_guar); 2078 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2079 func_p->fd_fltr_best_effort); 2080 } 2081 2082 /** 2083 * ice_parse_func_caps - Parse function capabilities 2084 * @hw: pointer to the HW struct 2085 * @func_p: pointer to function capabilities structure 2086 * @buf: buffer containing the function capability records 2087 * @cap_count: the number of capabilities 2088 * 2089 * Helper function to parse function (0x000A) capabilities list. For 2090 * capabilities shared between device and function, this relies on 2091 * ice_parse_common_caps. 2092 * 2093 * Loop through the list of provided capabilities and extract the relevant 2094 * data into the function capabilities structured. 2095 */ 2096 static void 2097 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2098 void *buf, u32 cap_count) 2099 { 2100 struct ice_aqc_list_caps_elem *cap_resp; 2101 u32 i; 2102 2103 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 2104 2105 ice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM); 2106 2107 for (i = 0; i < cap_count; i++) { 2108 u16 cap = LE16_TO_CPU(cap_resp[i].cap); 2109 bool found; 2110 2111 found = ice_parse_common_caps(hw, &func_p->common_cap, 2112 &cap_resp[i], "func caps"); 2113 2114 switch (cap) { 2115 case ICE_AQC_CAPS_VSI: 2116 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2117 break; 2118 case ICE_AQC_CAPS_FD: 2119 ice_parse_fdir_func_caps(hw, func_p); 2120 break; 2121 default: 2122 /* Don't list common capabilities as unknown */ 2123 if (!found) 2124 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2125 i, cap); 2126 break; 2127 } 2128 } 2129 2130 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2131 } 2132 2133 /** 2134 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2135 * @hw: pointer to the HW struct 2136 * @dev_p: pointer to device capabilities structure 2137 * @cap: capability element to parse 2138 * 2139 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2140 */ 2141 static void 2142 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2143 struct ice_aqc_list_caps_elem *cap) 2144 { 2145 u32 number = LE32_TO_CPU(cap->number); 2146 2147 dev_p->num_funcs = ice_hweight32(number); 2148 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2149 dev_p->num_funcs); 2150 } 2151 2152 /** 2153 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2154 * @hw: pointer to the HW struct 2155 * @dev_p: pointer to device capabilities structure 2156 * @cap: capability element to parse 2157 * 2158 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2159 */ 2160 static void 2161 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2162 struct ice_aqc_list_caps_elem *cap) 2163 { 2164 u32 number = LE32_TO_CPU(cap->number); 2165 2166 dev_p->num_vsi_allocd_to_host = number; 2167 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2168 dev_p->num_vsi_allocd_to_host); 2169 } 2170 2171 /** 2172 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2173 * @hw: pointer to the HW struct 2174 * @dev_p: pointer to device capabilities structure 2175 * @cap: capability element to parse 2176 * 2177 * Parse ICE_AQC_CAPS_FD for device capabilities. 2178 */ 2179 static void 2180 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2181 struct ice_aqc_list_caps_elem *cap) 2182 { 2183 u32 number = LE32_TO_CPU(cap->number); 2184 2185 dev_p->num_flow_director_fltr = number; 2186 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2187 dev_p->num_flow_director_fltr); 2188 } 2189 2190 /** 2191 * ice_parse_dev_caps - Parse device capabilities 2192 * @hw: pointer to the HW struct 2193 * @dev_p: pointer to device capabilities structure 2194 * @buf: buffer containing the device capability records 2195 * @cap_count: the number of capabilities 2196 * 2197 * Helper device to parse device (0x000B) capabilities list. For 2198 * capabilities shared between device and function, this relies on 2199 * ice_parse_common_caps. 2200 * 2201 * Loop through the list of provided capabilities and extract the relevant 2202 * data into the device capabilities structured. 2203 */ 2204 static void 2205 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2206 void *buf, u32 cap_count) 2207 { 2208 struct ice_aqc_list_caps_elem *cap_resp; 2209 u32 i; 2210 2211 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 2212 2213 ice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM); 2214 2215 for (i = 0; i < cap_count; i++) { 2216 u16 cap = LE16_TO_CPU(cap_resp[i].cap); 2217 bool found; 2218 2219 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2220 &cap_resp[i], "dev caps"); 2221 2222 switch (cap) { 2223 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2224 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2225 break; 2226 case ICE_AQC_CAPS_VSI: 2227 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2228 break; 2229 case ICE_AQC_CAPS_FD: 2230 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2231 break; 2232 default: 2233 /* Don't list common capabilities as unknown */ 2234 if (!found) 2235 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2236 i, cap); 2237 break; 2238 } 2239 } 2240 2241 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2242 } 2243 2244 /** 2245 * ice_aq_list_caps - query function/device capabilities 2246 * @hw: pointer to the HW struct 2247 * @buf: a buffer to hold the capabilities 2248 * @buf_size: size of the buffer 2249 * @cap_count: if not NULL, set to the number of capabilities reported 2250 * @opc: capabilities type to discover, device or function 2251 * @cd: pointer to command details structure or NULL 2252 * 2253 * Get the function (0x000A) or device (0x000B) capabilities description from 2254 * firmware and store it in the buffer. 2255 * 2256 * If the cap_count pointer is not NULL, then it is set to the number of 2257 * capabilities firmware will report. Note that if the buffer size is too 2258 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2259 * cap_count will still be updated in this case. It is recommended that the 2260 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2261 * firmware could return) to avoid this. 2262 */ 2263 static enum ice_status 2264 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2265 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2266 { 2267 struct ice_aqc_list_caps *cmd; 2268 struct ice_aq_desc desc; 2269 enum ice_status status; 2270 2271 cmd = &desc.params.get_cap; 2272 2273 if (opc != ice_aqc_opc_list_func_caps && 2274 opc != ice_aqc_opc_list_dev_caps) 2275 return ICE_ERR_PARAM; 2276 2277 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2278 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2279 2280 if (cap_count) 2281 *cap_count = LE32_TO_CPU(cmd->count); 2282 2283 return status; 2284 } 2285 2286 /** 2287 * ice_discover_dev_caps - Read and extract device capabilities 2288 * @hw: pointer to the hardware structure 2289 * @dev_caps: pointer to device capabilities structure 2290 * 2291 * Read the device capabilities and extract them into the dev_caps structure 2292 * for later use. 2293 */ 2294 static enum ice_status 2295 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2296 { 2297 enum ice_status status; 2298 u32 cap_count = 0; 2299 void *cbuf; 2300 2301 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN); 2302 if (!cbuf) 2303 return ICE_ERR_NO_MEMORY; 2304 2305 /* Although the driver doesn't know the number of capabilities the 2306 * device will return, we can simply send a 4KB buffer, the maximum 2307 * possible size that firmware can return. 2308 */ 2309 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2310 2311 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2312 ice_aqc_opc_list_dev_caps, NULL); 2313 if (!status) 2314 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2315 ice_free(hw, cbuf); 2316 2317 return status; 2318 } 2319 2320 /** 2321 * ice_discover_func_caps - Read and extract function capabilities 2322 * @hw: pointer to the hardware structure 2323 * @func_caps: pointer to function capabilities structure 2324 * 2325 * Read the function capabilities and extract them into the func_caps structure 2326 * for later use. 2327 */ 2328 static enum ice_status 2329 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2330 { 2331 enum ice_status status; 2332 u32 cap_count = 0; 2333 void *cbuf; 2334 2335 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN); 2336 if (!cbuf) 2337 return ICE_ERR_NO_MEMORY; 2338 2339 /* Although the driver doesn't know the number of capabilities the 2340 * device will return, we can simply send a 4KB buffer, the maximum 2341 * possible size that firmware can return. 2342 */ 2343 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2344 2345 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2346 ice_aqc_opc_list_func_caps, NULL); 2347 if (!status) 2348 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2349 ice_free(hw, cbuf); 2350 2351 return status; 2352 } 2353 2354 /** 2355 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2356 * @hw: pointer to the hardware structure 2357 */ 2358 void ice_set_safe_mode_caps(struct ice_hw *hw) 2359 { 2360 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2361 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2362 struct ice_hw_common_caps cached_caps; 2363 u32 num_funcs; 2364 2365 /* cache some func_caps values that should be restored after memset */ 2366 cached_caps = func_caps->common_cap; 2367 2368 /* unset func capabilities */ 2369 memset(func_caps, 0, sizeof(*func_caps)); 2370 2371 #define ICE_RESTORE_FUNC_CAP(name) \ 2372 func_caps->common_cap.name = cached_caps.name 2373 2374 /* restore cached values */ 2375 ICE_RESTORE_FUNC_CAP(valid_functions); 2376 ICE_RESTORE_FUNC_CAP(txq_first_id); 2377 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2378 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2379 ICE_RESTORE_FUNC_CAP(max_mtu); 2380 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2381 2382 /* one Tx and one Rx queue in safe mode */ 2383 func_caps->common_cap.num_rxq = 1; 2384 func_caps->common_cap.num_txq = 1; 2385 2386 /* two MSIX vectors, one for traffic and one for misc causes */ 2387 func_caps->common_cap.num_msix_vectors = 2; 2388 func_caps->guar_num_vsi = 1; 2389 2390 /* cache some dev_caps values that should be restored after memset */ 2391 cached_caps = dev_caps->common_cap; 2392 num_funcs = dev_caps->num_funcs; 2393 2394 /* unset dev capabilities */ 2395 memset(dev_caps, 0, sizeof(*dev_caps)); 2396 2397 #define ICE_RESTORE_DEV_CAP(name) \ 2398 dev_caps->common_cap.name = cached_caps.name 2399 2400 /* restore cached values */ 2401 ICE_RESTORE_DEV_CAP(valid_functions); 2402 ICE_RESTORE_DEV_CAP(txq_first_id); 2403 ICE_RESTORE_DEV_CAP(rxq_first_id); 2404 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2405 ICE_RESTORE_DEV_CAP(max_mtu); 2406 ICE_RESTORE_DEV_CAP(nvm_unified_update); 2407 dev_caps->num_funcs = num_funcs; 2408 2409 /* one Tx and one Rx queue per function in safe mode */ 2410 dev_caps->common_cap.num_rxq = num_funcs; 2411 dev_caps->common_cap.num_txq = num_funcs; 2412 2413 /* two MSIX vectors per function */ 2414 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2415 } 2416 2417 /** 2418 * ice_get_caps - get info about the HW 2419 * @hw: pointer to the hardware structure 2420 */ 2421 enum ice_status ice_get_caps(struct ice_hw *hw) 2422 { 2423 enum ice_status status; 2424 2425 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2426 if (status) 2427 return status; 2428 2429 return ice_discover_func_caps(hw, &hw->func_caps); 2430 } 2431 2432 /** 2433 * ice_aq_manage_mac_write - manage MAC address write command 2434 * @hw: pointer to the HW struct 2435 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2436 * @flags: flags to control write behavior 2437 * @cd: pointer to command details structure or NULL 2438 * 2439 * This function is used to write MAC address to the NVM (0x0108). 2440 */ 2441 enum ice_status 2442 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2443 struct ice_sq_cd *cd) 2444 { 2445 struct ice_aqc_manage_mac_write *cmd; 2446 struct ice_aq_desc desc; 2447 2448 cmd = &desc.params.mac_write; 2449 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2450 2451 cmd->flags = flags; 2452 ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 2453 2454 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2455 } 2456 2457 /** 2458 * ice_aq_clear_pxe_mode 2459 * @hw: pointer to the HW struct 2460 * 2461 * Tell the firmware that the driver is taking over from PXE (0x0110). 2462 */ 2463 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 2464 { 2465 struct ice_aq_desc desc; 2466 2467 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2468 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2469 2470 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2471 } 2472 2473 /** 2474 * ice_clear_pxe_mode - clear pxe operations mode 2475 * @hw: pointer to the HW struct 2476 * 2477 * Make sure all PXE mode settings are cleared, including things 2478 * like descriptor fetch/write-back mode. 2479 */ 2480 void ice_clear_pxe_mode(struct ice_hw *hw) 2481 { 2482 if (ice_check_sq_alive(hw, &hw->adminq)) 2483 ice_aq_clear_pxe_mode(hw); 2484 } 2485 2486 /** 2487 * ice_aq_set_port_params - set physical port parameters. 2488 * @pi: pointer to the port info struct 2489 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 2490 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 2491 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 2492 * @double_vlan: if set double VLAN is enabled 2493 * @cd: pointer to command details structure or NULL 2494 * 2495 * Set Physical port parameters (0x0203) 2496 */ 2497 enum ice_status 2498 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi, 2499 bool save_bad_pac, bool pad_short_pac, bool double_vlan, 2500 struct ice_sq_cd *cd) 2501 2502 { 2503 struct ice_aqc_set_port_params *cmd; 2504 struct ice_hw *hw = pi->hw; 2505 struct ice_aq_desc desc; 2506 u16 cmd_flags = 0; 2507 2508 cmd = &desc.params.set_port_params; 2509 2510 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 2511 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 2512 if (save_bad_pac) 2513 cmd_flags |= ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS; 2514 if (pad_short_pac) 2515 cmd_flags |= ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS; 2516 if (double_vlan) 2517 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 2518 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 2519 2520 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2521 } 2522 2523 /** 2524 * ice_get_link_speed_based_on_phy_type - returns link speed 2525 * @phy_type_low: lower part of phy_type 2526 * @phy_type_high: higher part of phy_type 2527 * 2528 * This helper function will convert an entry in PHY type structure 2529 * [phy_type_low, phy_type_high] to its corresponding link speed. 2530 * Note: In the structure of [phy_type_low, phy_type_high], there should 2531 * be one bit set, as this function will convert one PHY type to its 2532 * speed. 2533 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2534 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2535 */ 2536 static u16 2537 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 2538 { 2539 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2540 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2541 2542 switch (phy_type_low) { 2543 case ICE_PHY_TYPE_LOW_100BASE_TX: 2544 case ICE_PHY_TYPE_LOW_100M_SGMII: 2545 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 2546 break; 2547 case ICE_PHY_TYPE_LOW_1000BASE_T: 2548 case ICE_PHY_TYPE_LOW_1000BASE_SX: 2549 case ICE_PHY_TYPE_LOW_1000BASE_LX: 2550 case ICE_PHY_TYPE_LOW_1000BASE_KX: 2551 case ICE_PHY_TYPE_LOW_1G_SGMII: 2552 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 2553 break; 2554 case ICE_PHY_TYPE_LOW_2500BASE_T: 2555 case ICE_PHY_TYPE_LOW_2500BASE_X: 2556 case ICE_PHY_TYPE_LOW_2500BASE_KX: 2557 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 2558 break; 2559 case ICE_PHY_TYPE_LOW_5GBASE_T: 2560 case ICE_PHY_TYPE_LOW_5GBASE_KR: 2561 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 2562 break; 2563 case ICE_PHY_TYPE_LOW_10GBASE_T: 2564 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 2565 case ICE_PHY_TYPE_LOW_10GBASE_SR: 2566 case ICE_PHY_TYPE_LOW_10GBASE_LR: 2567 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 2568 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 2569 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 2570 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 2571 break; 2572 case ICE_PHY_TYPE_LOW_25GBASE_T: 2573 case ICE_PHY_TYPE_LOW_25GBASE_CR: 2574 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 2575 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 2576 case ICE_PHY_TYPE_LOW_25GBASE_SR: 2577 case ICE_PHY_TYPE_LOW_25GBASE_LR: 2578 case ICE_PHY_TYPE_LOW_25GBASE_KR: 2579 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 2580 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 2581 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 2582 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 2583 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 2584 break; 2585 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 2586 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 2587 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 2588 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 2589 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 2590 case ICE_PHY_TYPE_LOW_40G_XLAUI: 2591 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 2592 break; 2593 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 2594 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 2595 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 2596 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 2597 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 2598 case ICE_PHY_TYPE_LOW_50G_LAUI2: 2599 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 2600 case ICE_PHY_TYPE_LOW_50G_AUI2: 2601 case ICE_PHY_TYPE_LOW_50GBASE_CP: 2602 case ICE_PHY_TYPE_LOW_50GBASE_SR: 2603 case ICE_PHY_TYPE_LOW_50GBASE_FR: 2604 case ICE_PHY_TYPE_LOW_50GBASE_LR: 2605 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 2606 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 2607 case ICE_PHY_TYPE_LOW_50G_AUI1: 2608 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 2609 break; 2610 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 2611 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 2612 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 2613 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 2614 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 2615 case ICE_PHY_TYPE_LOW_100G_CAUI4: 2616 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 2617 case ICE_PHY_TYPE_LOW_100G_AUI4: 2618 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 2619 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 2620 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 2621 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 2622 case ICE_PHY_TYPE_LOW_100GBASE_DR: 2623 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 2624 break; 2625 default: 2626 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2627 break; 2628 } 2629 2630 switch (phy_type_high) { 2631 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 2632 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 2633 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 2634 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 2635 case ICE_PHY_TYPE_HIGH_100G_AUI2: 2636 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 2637 break; 2638 default: 2639 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2640 break; 2641 } 2642 2643 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 2644 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2645 return ICE_AQ_LINK_SPEED_UNKNOWN; 2646 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2647 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 2648 return ICE_AQ_LINK_SPEED_UNKNOWN; 2649 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2650 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2651 return speed_phy_type_low; 2652 else 2653 return speed_phy_type_high; 2654 } 2655 2656 /** 2657 * ice_update_phy_type 2658 * @phy_type_low: pointer to the lower part of phy_type 2659 * @phy_type_high: pointer to the higher part of phy_type 2660 * @link_speeds_bitmap: targeted link speeds bitmap 2661 * 2662 * Note: For the link_speeds_bitmap structure, you can check it at 2663 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 2664 * link_speeds_bitmap include multiple speeds. 2665 * 2666 * Each entry in this [phy_type_low, phy_type_high] structure will 2667 * present a certain link speed. This helper function will turn on bits 2668 * in [phy_type_low, phy_type_high] structure based on the value of 2669 * link_speeds_bitmap input parameter. 2670 */ 2671 void 2672 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 2673 u16 link_speeds_bitmap) 2674 { 2675 u64 pt_high; 2676 u64 pt_low; 2677 int index; 2678 u16 speed; 2679 2680 /* We first check with low part of phy_type */ 2681 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 2682 pt_low = BIT_ULL(index); 2683 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 2684 2685 if (link_speeds_bitmap & speed) 2686 *phy_type_low |= BIT_ULL(index); 2687 } 2688 2689 /* We then check with high part of phy_type */ 2690 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 2691 pt_high = BIT_ULL(index); 2692 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 2693 2694 if (link_speeds_bitmap & speed) 2695 *phy_type_high |= BIT_ULL(index); 2696 } 2697 } 2698 2699 /** 2700 * ice_aq_set_phy_cfg 2701 * @hw: pointer to the HW struct 2702 * @pi: port info structure of the interested logical port 2703 * @cfg: structure with PHY configuration data to be set 2704 * @cd: pointer to command details structure or NULL 2705 * 2706 * Set the various PHY configuration parameters supported on the Port. 2707 * One or more of the Set PHY config parameters may be ignored in an MFP 2708 * mode as the PF may not have the privilege to set some of the PHY Config 2709 * parameters. This status will be indicated by the command response (0x0601). 2710 */ 2711 enum ice_status 2712 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 2713 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 2714 { 2715 struct ice_aq_desc desc; 2716 enum ice_status status; 2717 2718 if (!cfg) 2719 return ICE_ERR_PARAM; 2720 2721 /* Ensure that only valid bits of cfg->caps can be turned on. */ 2722 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 2723 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 2724 cfg->caps); 2725 2726 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 2727 } 2728 2729 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 2730 desc.params.set_phy.lport_num = pi->lport; 2731 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 2732 2733 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 2734 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 2735 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low)); 2736 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 2737 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high)); 2738 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 2739 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 2740 cfg->low_power_ctrl_an); 2741 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 2742 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 2743 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 2744 cfg->link_fec_opt); 2745 2746 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 2747 2748 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 2749 status = ICE_SUCCESS; 2750 2751 if (!status) 2752 pi->phy.curr_user_phy_cfg = *cfg; 2753 2754 return status; 2755 } 2756 2757 /** 2758 * ice_update_link_info - update status of the HW network link 2759 * @pi: port info structure of the interested logical port 2760 */ 2761 enum ice_status ice_update_link_info(struct ice_port_info *pi) 2762 { 2763 struct ice_link_status *li; 2764 enum ice_status status; 2765 2766 if (!pi) 2767 return ICE_ERR_PARAM; 2768 2769 li = &pi->phy.link_info; 2770 2771 status = ice_aq_get_link_info(pi, true, NULL, NULL); 2772 if (status) 2773 return status; 2774 2775 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 2776 struct ice_aqc_get_phy_caps_data *pcaps; 2777 struct ice_hw *hw; 2778 2779 hw = pi->hw; 2780 pcaps = (struct ice_aqc_get_phy_caps_data *) 2781 ice_malloc(hw, sizeof(*pcaps)); 2782 if (!pcaps) 2783 return ICE_ERR_NO_MEMORY; 2784 2785 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 2786 pcaps, NULL); 2787 2788 if (status == ICE_SUCCESS) 2789 ice_memcpy(li->module_type, &pcaps->module_type, 2790 sizeof(li->module_type), 2791 ICE_NONDMA_TO_NONDMA); 2792 2793 ice_free(hw, pcaps); 2794 } 2795 2796 return status; 2797 } 2798 2799 /** 2800 * ice_cache_phy_user_req 2801 * @pi: port information structure 2802 * @cache_data: PHY logging data 2803 * @cache_mode: PHY logging mode 2804 * 2805 * Log the user request on (FC, FEC, SPEED) for later user. 2806 */ 2807 static void 2808 ice_cache_phy_user_req(struct ice_port_info *pi, 2809 struct ice_phy_cache_mode_data cache_data, 2810 enum ice_phy_cache_mode cache_mode) 2811 { 2812 if (!pi) 2813 return; 2814 2815 switch (cache_mode) { 2816 case ICE_FC_MODE: 2817 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 2818 break; 2819 case ICE_SPEED_MODE: 2820 pi->phy.curr_user_speed_req = 2821 cache_data.data.curr_user_speed_req; 2822 break; 2823 case ICE_FEC_MODE: 2824 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 2825 break; 2826 default: 2827 break; 2828 } 2829 } 2830 2831 /** 2832 * ice_caps_to_fc_mode 2833 * @caps: PHY capabilities 2834 * 2835 * Convert PHY FC capabilities to ice FC mode 2836 */ 2837 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 2838 { 2839 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 2840 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2841 return ICE_FC_FULL; 2842 2843 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 2844 return ICE_FC_TX_PAUSE; 2845 2846 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2847 return ICE_FC_RX_PAUSE; 2848 2849 return ICE_FC_NONE; 2850 } 2851 2852 /** 2853 * ice_caps_to_fec_mode 2854 * @caps: PHY capabilities 2855 * @fec_options: Link FEC options 2856 * 2857 * Convert PHY FEC capabilities to ice FEC mode 2858 */ 2859 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 2860 { 2861 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 2862 return ICE_FEC_AUTO; 2863 2864 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2865 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 2866 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 2867 ICE_AQC_PHY_FEC_25G_KR_REQ)) 2868 return ICE_FEC_BASER; 2869 2870 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 2871 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 2872 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 2873 return ICE_FEC_RS; 2874 2875 return ICE_FEC_NONE; 2876 } 2877 2878 /** 2879 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 2880 * @pi: port information structure 2881 * @cfg: PHY configuration data to set FC mode 2882 * @req_mode: FC mode to configure 2883 */ 2884 static enum ice_status 2885 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 2886 enum ice_fc_mode req_mode) 2887 { 2888 struct ice_phy_cache_mode_data cache_data; 2889 u8 pause_mask = 0x0; 2890 2891 if (!pi || !cfg) 2892 return ICE_ERR_BAD_PTR; 2893 2894 switch (req_mode) { 2895 case ICE_FC_AUTO: 2896 { 2897 struct ice_aqc_get_phy_caps_data *pcaps; 2898 enum ice_status status; 2899 2900 pcaps = (struct ice_aqc_get_phy_caps_data *) 2901 ice_malloc(pi->hw, sizeof(*pcaps)); 2902 if (!pcaps) 2903 return ICE_ERR_NO_MEMORY; 2904 2905 /* Query the value of FC that both the NIC and attached media 2906 * can do. 2907 */ 2908 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 2909 pcaps, NULL); 2910 if (status) { 2911 ice_free(pi->hw, pcaps); 2912 return status; 2913 } 2914 2915 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2916 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2917 2918 ice_free(pi->hw, pcaps); 2919 break; 2920 } 2921 case ICE_FC_FULL: 2922 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2923 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2924 break; 2925 case ICE_FC_RX_PAUSE: 2926 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2927 break; 2928 case ICE_FC_TX_PAUSE: 2929 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2930 break; 2931 default: 2932 break; 2933 } 2934 2935 /* clear the old pause settings */ 2936 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 2937 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 2938 2939 /* set the new capabilities */ 2940 cfg->caps |= pause_mask; 2941 2942 /* Cache user FC request */ 2943 cache_data.data.curr_user_fc_req = req_mode; 2944 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 2945 2946 return ICE_SUCCESS; 2947 } 2948 2949 /** 2950 * ice_set_fc 2951 * @pi: port information structure 2952 * @aq_failures: pointer to status code, specific to ice_set_fc routine 2953 * @ena_auto_link_update: enable automatic link update 2954 * 2955 * Set the requested flow control mode. 2956 */ 2957 enum ice_status 2958 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 2959 { 2960 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 2961 struct ice_aqc_get_phy_caps_data *pcaps; 2962 enum ice_status status; 2963 struct ice_hw *hw; 2964 2965 if (!pi || !aq_failures) 2966 return ICE_ERR_BAD_PTR; 2967 2968 *aq_failures = 0; 2969 hw = pi->hw; 2970 2971 pcaps = (struct ice_aqc_get_phy_caps_data *) 2972 ice_malloc(hw, sizeof(*pcaps)); 2973 if (!pcaps) 2974 return ICE_ERR_NO_MEMORY; 2975 2976 /* Get the current PHY config */ 2977 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 2978 pcaps, NULL); 2979 2980 if (status) { 2981 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2982 goto out; 2983 } 2984 2985 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 2986 2987 /* Configure the set PHY data */ 2988 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 2989 if (status) { 2990 if (status != ICE_ERR_BAD_PTR) 2991 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2992 2993 goto out; 2994 } 2995 2996 /* If the capabilities have changed, then set the new config */ 2997 if (cfg.caps != pcaps->caps) { 2998 int retry_count, retry_max = 10; 2999 3000 /* Auto restart link so settings take effect */ 3001 if (ena_auto_link_update) 3002 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3003 3004 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3005 if (status) { 3006 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3007 goto out; 3008 } 3009 3010 /* Update the link info 3011 * It sometimes takes a really long time for link to 3012 * come back from the atomic reset. Thus, we wait a 3013 * little bit. 3014 */ 3015 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3016 status = ice_update_link_info(pi); 3017 3018 if (status == ICE_SUCCESS) 3019 break; 3020 3021 ice_msec_delay(100, true); 3022 } 3023 3024 if (status) 3025 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3026 } 3027 3028 out: 3029 ice_free(hw, pcaps); 3030 return status; 3031 } 3032 3033 /** 3034 * ice_phy_caps_equals_cfg 3035 * @phy_caps: PHY capabilities 3036 * @phy_cfg: PHY configuration 3037 * 3038 * Helper function to determine if PHY capabilities matches PHY 3039 * configuration 3040 */ 3041 bool 3042 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3043 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3044 { 3045 u8 caps_mask, cfg_mask; 3046 3047 if (!phy_caps || !phy_cfg) 3048 return false; 3049 3050 /* These bits are not common between capabilities and configuration. 3051 * Do not use them to determine equality. 3052 */ 3053 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3054 ICE_AQC_PHY_EN_MOD_QUAL); 3055 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3056 3057 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3058 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3059 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3060 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3061 phy_caps->eee_cap != phy_cfg->eee_cap || 3062 phy_caps->eeer_value != phy_cfg->eeer_value || 3063 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3064 return false; 3065 3066 return true; 3067 } 3068 3069 /** 3070 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3071 * @pi: port information structure 3072 * @caps: PHY ability structure to copy date from 3073 * @cfg: PHY configuration structure to copy data to 3074 * 3075 * Helper function to copy AQC PHY get ability data to PHY set configuration 3076 * data structure 3077 */ 3078 void 3079 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3080 struct ice_aqc_get_phy_caps_data *caps, 3081 struct ice_aqc_set_phy_cfg_data *cfg) 3082 { 3083 if (!pi || !caps || !cfg) 3084 return; 3085 3086 ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM); 3087 cfg->phy_type_low = caps->phy_type_low; 3088 cfg->phy_type_high = caps->phy_type_high; 3089 cfg->caps = caps->caps; 3090 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3091 cfg->eee_cap = caps->eee_cap; 3092 cfg->eeer_value = caps->eeer_value; 3093 cfg->link_fec_opt = caps->link_fec_options; 3094 cfg->module_compliance_enforcement = 3095 caps->module_compliance_enforcement; 3096 } 3097 3098 /** 3099 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3100 * @pi: port information structure 3101 * @cfg: PHY configuration data to set FEC mode 3102 * @fec: FEC mode to configure 3103 */ 3104 enum ice_status 3105 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3106 enum ice_fec_mode fec) 3107 { 3108 struct ice_aqc_get_phy_caps_data *pcaps; 3109 enum ice_status status = ICE_SUCCESS; 3110 struct ice_hw *hw; 3111 3112 if (!pi || !cfg) 3113 return ICE_ERR_BAD_PTR; 3114 3115 hw = pi->hw; 3116 3117 pcaps = (struct ice_aqc_get_phy_caps_data *) 3118 ice_malloc(hw, sizeof(*pcaps)); 3119 if (!pcaps) 3120 return ICE_ERR_NO_MEMORY; 3121 3122 status = ice_aq_get_phy_caps(pi, false, 3123 (ice_fw_supports_report_dflt_cfg(hw) ? 3124 ICE_AQC_REPORT_DFLT_CFG : 3125 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3126 3127 if (status) 3128 goto out; 3129 3130 cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC); 3131 cfg->link_fec_opt = pcaps->link_fec_options; 3132 3133 switch (fec) { 3134 case ICE_FEC_BASER: 3135 /* Clear RS bits, and AND BASE-R ability 3136 * bits and OR request bits. 3137 */ 3138 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3139 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3140 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3141 ICE_AQC_PHY_FEC_25G_KR_REQ; 3142 break; 3143 case ICE_FEC_RS: 3144 /* Clear BASE-R bits, and AND RS ability 3145 * bits and OR request bits. 3146 */ 3147 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3148 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3149 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3150 break; 3151 case ICE_FEC_NONE: 3152 /* Clear all FEC option bits. */ 3153 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3154 break; 3155 case ICE_FEC_AUTO: 3156 /* AND auto FEC bit, and all caps bits. */ 3157 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 3158 cfg->link_fec_opt |= pcaps->link_fec_options; 3159 break; 3160 default: 3161 status = ICE_ERR_PARAM; 3162 break; 3163 } 3164 3165 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw) && 3166 !ice_fw_supports_report_dflt_cfg(pi->hw)) { 3167 struct ice_link_default_override_tlv tlv; 3168 3169 if (ice_get_link_default_override(&tlv, pi)) 3170 goto out; 3171 3172 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3173 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3174 cfg->link_fec_opt = tlv.fec_options; 3175 } 3176 3177 out: 3178 ice_free(hw, pcaps); 3179 3180 return status; 3181 } 3182 3183 /** 3184 * ice_get_link_status - get status of the HW network link 3185 * @pi: port information structure 3186 * @link_up: pointer to bool (true/false = linkup/linkdown) 3187 * 3188 * Variable link_up is true if link is up, false if link is down. 3189 * The variable link_up is invalid if status is non zero. As a 3190 * result of this call, link status reporting becomes enabled 3191 */ 3192 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3193 { 3194 struct ice_phy_info *phy_info; 3195 enum ice_status status = ICE_SUCCESS; 3196 3197 if (!pi || !link_up) 3198 return ICE_ERR_PARAM; 3199 3200 phy_info = &pi->phy; 3201 3202 if (phy_info->get_link_info) { 3203 status = ice_update_link_info(pi); 3204 3205 if (status) 3206 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3207 status); 3208 } 3209 3210 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3211 3212 return status; 3213 } 3214 3215 /** 3216 * ice_aq_set_link_restart_an 3217 * @pi: pointer to the port information structure 3218 * @ena_link: if true: enable link, if false: disable link 3219 * @cd: pointer to command details structure or NULL 3220 * 3221 * Sets up the link and restarts the Auto-Negotiation over the link. 3222 */ 3223 enum ice_status 3224 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3225 struct ice_sq_cd *cd) 3226 { 3227 struct ice_aqc_restart_an *cmd; 3228 struct ice_aq_desc desc; 3229 3230 cmd = &desc.params.restart_an; 3231 3232 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3233 3234 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3235 cmd->lport_num = pi->lport; 3236 if (ena_link) 3237 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3238 else 3239 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3240 3241 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3242 } 3243 3244 /** 3245 * ice_aq_set_event_mask 3246 * @hw: pointer to the HW struct 3247 * @port_num: port number of the physical function 3248 * @mask: event mask to be set 3249 * @cd: pointer to command details structure or NULL 3250 * 3251 * Set event mask (0x0613) 3252 */ 3253 enum ice_status 3254 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3255 struct ice_sq_cd *cd) 3256 { 3257 struct ice_aqc_set_event_mask *cmd; 3258 struct ice_aq_desc desc; 3259 3260 cmd = &desc.params.set_event_mask; 3261 3262 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3263 3264 cmd->lport_num = port_num; 3265 3266 cmd->event_mask = CPU_TO_LE16(mask); 3267 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3268 } 3269 3270 /** 3271 * ice_aq_set_mac_loopback 3272 * @hw: pointer to the HW struct 3273 * @ena_lpbk: Enable or Disable loopback 3274 * @cd: pointer to command details structure or NULL 3275 * 3276 * Enable/disable loopback on a given port 3277 */ 3278 enum ice_status 3279 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3280 { 3281 struct ice_aqc_set_mac_lb *cmd; 3282 struct ice_aq_desc desc; 3283 3284 cmd = &desc.params.set_mac_lb; 3285 3286 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3287 if (ena_lpbk) 3288 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3289 3290 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3291 } 3292 3293 /** 3294 * ice_aq_set_port_id_led 3295 * @pi: pointer to the port information 3296 * @is_orig_mode: is this LED set to original mode (by the net-list) 3297 * @cd: pointer to command details structure or NULL 3298 * 3299 * Set LED value for the given port (0x06e9) 3300 */ 3301 enum ice_status 3302 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3303 struct ice_sq_cd *cd) 3304 { 3305 struct ice_aqc_set_port_id_led *cmd; 3306 struct ice_hw *hw = pi->hw; 3307 struct ice_aq_desc desc; 3308 3309 cmd = &desc.params.set_port_id_led; 3310 3311 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3312 3313 if (is_orig_mode) 3314 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3315 else 3316 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3317 3318 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3319 } 3320 3321 /** 3322 * ice_aq_sff_eeprom 3323 * @hw: pointer to the HW struct 3324 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3325 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3326 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3327 * @page: QSFP page 3328 * @set_page: set or ignore the page 3329 * @data: pointer to data buffer to be read/written to the I2C device. 3330 * @length: 1-16 for read, 1 for write. 3331 * @write: 0 read, 1 for write. 3332 * @cd: pointer to command details structure or NULL 3333 * 3334 * Read/Write SFF EEPROM (0x06EE) 3335 */ 3336 enum ice_status 3337 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3338 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3339 bool write, struct ice_sq_cd *cd) 3340 { 3341 struct ice_aqc_sff_eeprom *cmd; 3342 struct ice_aq_desc desc; 3343 enum ice_status status; 3344 3345 if (!data || (mem_addr & 0xff00)) 3346 return ICE_ERR_PARAM; 3347 3348 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3349 cmd = &desc.params.read_write_sff_param; 3350 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD); 3351 cmd->lport_num = (u8)(lport & 0xff); 3352 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3353 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) & 3354 ICE_AQC_SFF_I2CBUS_7BIT_M) | 3355 ((set_page << 3356 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3357 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3358 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff); 3359 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3360 if (write) 3361 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE); 3362 3363 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3364 return status; 3365 } 3366 3367 /** 3368 * __ice_aq_get_set_rss_lut 3369 * @hw: pointer to the hardware structure 3370 * @params: RSS LUT parameters 3371 * @set: set true to set the table, false to get the table 3372 * 3373 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3374 */ 3375 static enum ice_status 3376 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set) 3377 { 3378 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle; 3379 struct ice_aqc_get_set_rss_lut *cmd_resp; 3380 struct ice_aq_desc desc; 3381 enum ice_status status; 3382 u8 *lut; 3383 3384 if (!params) 3385 return ICE_ERR_PARAM; 3386 3387 vsi_handle = params->vsi_handle; 3388 lut = params->lut; 3389 3390 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3391 return ICE_ERR_PARAM; 3392 3393 lut_size = params->lut_size; 3394 lut_type = params->lut_type; 3395 glob_lut_idx = params->global_lut_id; 3396 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 3397 3398 cmd_resp = &desc.params.get_set_rss_lut; 3399 3400 if (set) { 3401 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 3402 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3403 } else { 3404 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 3405 } 3406 3407 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 3408 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 3409 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 3410 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 3411 3412 switch (lut_type) { 3413 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 3414 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 3415 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 3416 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 3417 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 3418 break; 3419 default: 3420 status = ICE_ERR_PARAM; 3421 goto ice_aq_get_set_rss_lut_exit; 3422 } 3423 3424 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 3425 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 3426 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 3427 3428 if (!set) 3429 goto ice_aq_get_set_rss_lut_send; 3430 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3431 if (!set) 3432 goto ice_aq_get_set_rss_lut_send; 3433 } else { 3434 goto ice_aq_get_set_rss_lut_send; 3435 } 3436 3437 /* LUT size is only valid for Global and PF table types */ 3438 switch (lut_size) { 3439 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 3440 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG << 3441 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3442 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3443 break; 3444 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 3445 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 3446 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3447 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3448 break; 3449 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 3450 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3451 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 3452 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3453 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3454 break; 3455 } 3456 /* fall-through */ 3457 default: 3458 status = ICE_ERR_PARAM; 3459 goto ice_aq_get_set_rss_lut_exit; 3460 } 3461 3462 ice_aq_get_set_rss_lut_send: 3463 cmd_resp->flags = CPU_TO_LE16(flags); 3464 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 3465 3466 ice_aq_get_set_rss_lut_exit: 3467 return status; 3468 } 3469 3470 /** 3471 * ice_aq_get_rss_lut 3472 * @hw: pointer to the hardware structure 3473 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 3474 * 3475 * get the RSS lookup table, PF or VSI type 3476 */ 3477 enum ice_status 3478 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 3479 { 3480 return __ice_aq_get_set_rss_lut(hw, get_params, false); 3481 } 3482 3483 /** 3484 * ice_aq_set_rss_lut 3485 * @hw: pointer to the hardware structure 3486 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 3487 * 3488 * set the RSS lookup table, PF or VSI type 3489 */ 3490 enum ice_status 3491 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 3492 { 3493 return __ice_aq_get_set_rss_lut(hw, set_params, true); 3494 } 3495 3496 /** 3497 * __ice_aq_get_set_rss_key 3498 * @hw: pointer to the HW struct 3499 * @vsi_id: VSI FW index 3500 * @key: pointer to key info struct 3501 * @set: set true to set the key, false to get the key 3502 * 3503 * get (0x0B04) or set (0x0B02) the RSS key per VSI 3504 */ 3505 static enum 3506 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 3507 struct ice_aqc_get_set_rss_keys *key, 3508 bool set) 3509 { 3510 struct ice_aqc_get_set_rss_key *cmd_resp; 3511 u16 key_size = sizeof(*key); 3512 struct ice_aq_desc desc; 3513 3514 cmd_resp = &desc.params.get_set_rss_key; 3515 3516 if (set) { 3517 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 3518 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3519 } else { 3520 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 3521 } 3522 3523 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 3524 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 3525 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 3526 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 3527 3528 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 3529 } 3530 3531 /** 3532 * ice_aq_get_rss_key 3533 * @hw: pointer to the HW struct 3534 * @vsi_handle: software VSI handle 3535 * @key: pointer to key info struct 3536 * 3537 * get the RSS key per VSI 3538 */ 3539 enum ice_status 3540 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 3541 struct ice_aqc_get_set_rss_keys *key) 3542 { 3543 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 3544 return ICE_ERR_PARAM; 3545 3546 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3547 key, false); 3548 } 3549 3550 /** 3551 * ice_aq_set_rss_key 3552 * @hw: pointer to the HW struct 3553 * @vsi_handle: software VSI handle 3554 * @keys: pointer to key info struct 3555 * 3556 * set the RSS key per VSI 3557 */ 3558 enum ice_status 3559 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 3560 struct ice_aqc_get_set_rss_keys *keys) 3561 { 3562 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 3563 return ICE_ERR_PARAM; 3564 3565 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3566 keys, true); 3567 } 3568 3569 /** 3570 * ice_aq_add_lan_txq 3571 * @hw: pointer to the hardware structure 3572 * @num_qgrps: Number of added queue groups 3573 * @qg_list: list of queue groups to be added 3574 * @buf_size: size of buffer for indirect command 3575 * @cd: pointer to command details structure or NULL 3576 * 3577 * Add Tx LAN queue (0x0C30) 3578 * 3579 * NOTE: 3580 * Prior to calling add Tx LAN queue: 3581 * Initialize the following as part of the Tx queue context: 3582 * Completion queue ID if the queue uses Completion queue, Quanta profile, 3583 * Cache profile and Packet shaper profile. 3584 * 3585 * After add Tx LAN queue AQ command is completed: 3586 * Interrupts should be associated with specific queues, 3587 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 3588 * flow. 3589 */ 3590 enum ice_status 3591 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3592 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 3593 struct ice_sq_cd *cd) 3594 { 3595 struct ice_aqc_add_tx_qgrp *list; 3596 struct ice_aqc_add_txqs *cmd; 3597 struct ice_aq_desc desc; 3598 u16 i, sum_size = 0; 3599 3600 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 3601 3602 cmd = &desc.params.add_txqs; 3603 3604 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 3605 3606 if (!qg_list) 3607 return ICE_ERR_PARAM; 3608 3609 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3610 return ICE_ERR_PARAM; 3611 3612 for (i = 0, list = qg_list; i < num_qgrps; i++) { 3613 sum_size += ice_struct_size(list, txqs, list->num_txqs); 3614 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 3615 list->num_txqs); 3616 } 3617 3618 if (buf_size != sum_size) 3619 return ICE_ERR_PARAM; 3620 3621 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3622 3623 cmd->num_qgrps = num_qgrps; 3624 3625 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3626 } 3627 3628 /** 3629 * ice_aq_dis_lan_txq 3630 * @hw: pointer to the hardware structure 3631 * @num_qgrps: number of groups in the list 3632 * @qg_list: the list of groups to disable 3633 * @buf_size: the total size of the qg_list buffer in bytes 3634 * @rst_src: if called due to reset, specifies the reset source 3635 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3636 * @cd: pointer to command details structure or NULL 3637 * 3638 * Disable LAN Tx queue (0x0C31) 3639 */ 3640 static enum ice_status 3641 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3642 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 3643 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3644 struct ice_sq_cd *cd) 3645 { 3646 struct ice_aqc_dis_txq_item *item; 3647 struct ice_aqc_dis_txqs *cmd; 3648 struct ice_aq_desc desc; 3649 enum ice_status status; 3650 u16 i, sz = 0; 3651 3652 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 3653 cmd = &desc.params.dis_txqs; 3654 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 3655 3656 /* qg_list can be NULL only in VM/VF reset flow */ 3657 if (!qg_list && !rst_src) 3658 return ICE_ERR_PARAM; 3659 3660 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3661 return ICE_ERR_PARAM; 3662 3663 cmd->num_entries = num_qgrps; 3664 3665 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 3666 ICE_AQC_Q_DIS_TIMEOUT_M); 3667 3668 switch (rst_src) { 3669 case ICE_VM_RESET: 3670 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 3671 cmd->vmvf_and_timeout |= 3672 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 3673 break; 3674 case ICE_NO_RESET: 3675 default: 3676 break; 3677 } 3678 3679 /* flush pipe on time out */ 3680 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 3681 /* If no queue group info, we are in a reset flow. Issue the AQ */ 3682 if (!qg_list) 3683 goto do_aq; 3684 3685 /* set RD bit to indicate that command buffer is provided by the driver 3686 * and it needs to be read by the firmware 3687 */ 3688 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3689 3690 for (i = 0, item = qg_list; i < num_qgrps; i++) { 3691 u16 item_size = ice_struct_size(item, q_id, item->num_qs); 3692 3693 /* If the num of queues is even, add 2 bytes of padding */ 3694 if ((item->num_qs % 2) == 0) 3695 item_size += 2; 3696 3697 sz += item_size; 3698 3699 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 3700 } 3701 3702 if (buf_size != sz) 3703 return ICE_ERR_PARAM; 3704 3705 do_aq: 3706 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3707 if (status) { 3708 if (!qg_list) 3709 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 3710 vmvf_num, hw->adminq.sq_last_status); 3711 else 3712 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 3713 LE16_TO_CPU(qg_list[0].q_id[0]), 3714 hw->adminq.sq_last_status); 3715 } 3716 return status; 3717 } 3718 3719 /** 3720 * ice_aq_move_recfg_lan_txq 3721 * @hw: pointer to the hardware structure 3722 * @num_qs: number of queues to move/reconfigure 3723 * @is_move: true if this operation involves node movement 3724 * @is_tc_change: true if this operation involves a TC change 3725 * @subseq_call: true if this operation is a subsequent call 3726 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN 3727 * @timeout: timeout in units of 100 usec (valid values 0-50) 3728 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN 3729 * @buf: struct containing src/dest TEID and per-queue info 3730 * @buf_size: size of buffer for indirect command 3731 * @txqs_moved: out param, number of queues successfully moved 3732 * @cd: pointer to command details structure or NULL 3733 * 3734 * Move / Reconfigure Tx LAN queues (0x0C32) 3735 */ 3736 enum ice_status 3737 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move, 3738 bool is_tc_change, bool subseq_call, bool flush_pipe, 3739 u8 timeout, u32 *blocked_cgds, 3740 struct ice_aqc_move_txqs_data *buf, u16 buf_size, 3741 u8 *txqs_moved, struct ice_sq_cd *cd) 3742 { 3743 struct ice_aqc_move_txqs *cmd; 3744 struct ice_aq_desc desc; 3745 enum ice_status status; 3746 3747 cmd = &desc.params.move_txqs; 3748 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs); 3749 3750 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50 3751 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX) 3752 return ICE_ERR_PARAM; 3753 3754 if (is_tc_change && !flush_pipe && !blocked_cgds) 3755 return ICE_ERR_PARAM; 3756 3757 if (!is_move && !is_tc_change) 3758 return ICE_ERR_PARAM; 3759 3760 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3761 3762 if (is_move) 3763 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE; 3764 3765 if (is_tc_change) 3766 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE; 3767 3768 if (subseq_call) 3769 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL; 3770 3771 if (flush_pipe) 3772 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE; 3773 3774 cmd->num_qs = num_qs; 3775 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) & 3776 ICE_AQC_Q_CMD_TIMEOUT_M); 3777 3778 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 3779 3780 if (!status && txqs_moved) 3781 *txqs_moved = cmd->num_qs; 3782 3783 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN && 3784 is_tc_change && !flush_pipe) 3785 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds); 3786 3787 return status; 3788 } 3789 3790 /* End of FW Admin Queue command wrappers */ 3791 3792 /** 3793 * ice_write_byte - write a byte to a packed context structure 3794 * @src_ctx: the context structure to read from 3795 * @dest_ctx: the context to be written to 3796 * @ce_info: a description of the struct to be filled 3797 */ 3798 static void 3799 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3800 { 3801 u8 src_byte, dest_byte, mask; 3802 u8 *from, *dest; 3803 u16 shift_width; 3804 3805 /* copy from the next struct field */ 3806 from = src_ctx + ce_info->offset; 3807 3808 /* prepare the bits and mask */ 3809 shift_width = ce_info->lsb % 8; 3810 mask = (u8)(BIT(ce_info->width) - 1); 3811 3812 src_byte = *from; 3813 src_byte &= mask; 3814 3815 /* shift to correct alignment */ 3816 mask <<= shift_width; 3817 src_byte <<= shift_width; 3818 3819 /* get the current bits from the target bit string */ 3820 dest = dest_ctx + (ce_info->lsb / 8); 3821 3822 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 3823 3824 dest_byte &= ~mask; /* get the bits not changing */ 3825 dest_byte |= src_byte; /* add in the new bits */ 3826 3827 /* put it all back */ 3828 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 3829 } 3830 3831 /** 3832 * ice_write_word - write a word to a packed context structure 3833 * @src_ctx: the context structure to read from 3834 * @dest_ctx: the context to be written to 3835 * @ce_info: a description of the struct to be filled 3836 */ 3837 static void 3838 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3839 { 3840 u16 src_word, mask; 3841 __le16 dest_word; 3842 u8 *from, *dest; 3843 u16 shift_width; 3844 3845 /* copy from the next struct field */ 3846 from = src_ctx + ce_info->offset; 3847 3848 /* prepare the bits and mask */ 3849 shift_width = ce_info->lsb % 8; 3850 mask = BIT(ce_info->width) - 1; 3851 3852 /* don't swizzle the bits until after the mask because the mask bits 3853 * will be in a different bit position on big endian machines 3854 */ 3855 src_word = *(u16 *)from; 3856 src_word &= mask; 3857 3858 /* shift to correct alignment */ 3859 mask <<= shift_width; 3860 src_word <<= shift_width; 3861 3862 /* get the current bits from the target bit string */ 3863 dest = dest_ctx + (ce_info->lsb / 8); 3864 3865 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA); 3866 3867 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */ 3868 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */ 3869 3870 /* put it all back */ 3871 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 3872 } 3873 3874 /** 3875 * ice_write_dword - write a dword to a packed context structure 3876 * @src_ctx: the context structure to read from 3877 * @dest_ctx: the context to be written to 3878 * @ce_info: a description of the struct to be filled 3879 */ 3880 static void 3881 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3882 { 3883 u32 src_dword, mask; 3884 __le32 dest_dword; 3885 u8 *from, *dest; 3886 u16 shift_width; 3887 3888 /* copy from the next struct field */ 3889 from = src_ctx + ce_info->offset; 3890 3891 /* prepare the bits and mask */ 3892 shift_width = ce_info->lsb % 8; 3893 3894 /* if the field width is exactly 32 on an x86 machine, then the shift 3895 * operation will not work because the SHL instructions count is masked 3896 * to 5 bits so the shift will do nothing 3897 */ 3898 if (ce_info->width < 32) 3899 mask = BIT(ce_info->width) - 1; 3900 else 3901 mask = (u32)~0; 3902 3903 /* don't swizzle the bits until after the mask because the mask bits 3904 * will be in a different bit position on big endian machines 3905 */ 3906 src_dword = *(u32 *)from; 3907 src_dword &= mask; 3908 3909 /* shift to correct alignment */ 3910 mask <<= shift_width; 3911 src_dword <<= shift_width; 3912 3913 /* get the current bits from the target bit string */ 3914 dest = dest_ctx + (ce_info->lsb / 8); 3915 3916 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA); 3917 3918 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */ 3919 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */ 3920 3921 /* put it all back */ 3922 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 3923 } 3924 3925 /** 3926 * ice_write_qword - write a qword to a packed context structure 3927 * @src_ctx: the context structure to read from 3928 * @dest_ctx: the context to be written to 3929 * @ce_info: a description of the struct to be filled 3930 */ 3931 static void 3932 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3933 { 3934 u64 src_qword, mask; 3935 __le64 dest_qword; 3936 u8 *from, *dest; 3937 u16 shift_width; 3938 3939 /* copy from the next struct field */ 3940 from = src_ctx + ce_info->offset; 3941 3942 /* prepare the bits and mask */ 3943 shift_width = ce_info->lsb % 8; 3944 3945 /* if the field width is exactly 64 on an x86 machine, then the shift 3946 * operation will not work because the SHL instructions count is masked 3947 * to 6 bits so the shift will do nothing 3948 */ 3949 if (ce_info->width < 64) 3950 mask = BIT_ULL(ce_info->width) - 1; 3951 else 3952 mask = (u64)~0; 3953 3954 /* don't swizzle the bits until after the mask because the mask bits 3955 * will be in a different bit position on big endian machines 3956 */ 3957 src_qword = *(u64 *)from; 3958 src_qword &= mask; 3959 3960 /* shift to correct alignment */ 3961 mask <<= shift_width; 3962 src_qword <<= shift_width; 3963 3964 /* get the current bits from the target bit string */ 3965 dest = dest_ctx + (ce_info->lsb / 8); 3966 3967 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA); 3968 3969 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */ 3970 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */ 3971 3972 /* put it all back */ 3973 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 3974 } 3975 3976 /** 3977 * ice_set_ctx - set context bits in packed structure 3978 * @hw: pointer to the hardware structure 3979 * @src_ctx: pointer to a generic non-packed context structure 3980 * @dest_ctx: pointer to memory for the packed structure 3981 * @ce_info: a description of the structure to be transformed 3982 */ 3983 enum ice_status 3984 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 3985 const struct ice_ctx_ele *ce_info) 3986 { 3987 int f; 3988 3989 for (f = 0; ce_info[f].width; f++) { 3990 /* We have to deal with each element of the FW response 3991 * using the correct size so that we are correct regardless 3992 * of the endianness of the machine. 3993 */ 3994 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 3995 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 3996 f, ce_info[f].width, ce_info[f].size_of); 3997 continue; 3998 } 3999 switch (ce_info[f].size_of) { 4000 case sizeof(u8): 4001 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 4002 break; 4003 case sizeof(u16): 4004 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 4005 break; 4006 case sizeof(u32): 4007 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 4008 break; 4009 case sizeof(u64): 4010 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 4011 break; 4012 default: 4013 return ICE_ERR_INVAL_SIZE; 4014 } 4015 } 4016 4017 return ICE_SUCCESS; 4018 } 4019 4020 /** 4021 * ice_read_byte - read context byte into struct 4022 * @src_ctx: the context structure to read from 4023 * @dest_ctx: the context to be written to 4024 * @ce_info: a description of the struct to be filled 4025 */ 4026 static void 4027 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4028 { 4029 u8 dest_byte, mask; 4030 u8 *src, *target; 4031 u16 shift_width; 4032 4033 /* prepare the bits and mask */ 4034 shift_width = ce_info->lsb % 8; 4035 mask = (u8)(BIT(ce_info->width) - 1); 4036 4037 /* shift to correct alignment */ 4038 mask <<= shift_width; 4039 4040 /* get the current bits from the src bit string */ 4041 src = src_ctx + (ce_info->lsb / 8); 4042 4043 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 4044 4045 dest_byte &= ~(mask); 4046 4047 dest_byte >>= shift_width; 4048 4049 /* get the address from the struct field */ 4050 target = dest_ctx + ce_info->offset; 4051 4052 /* put it back in the struct */ 4053 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 4054 } 4055 4056 /** 4057 * ice_read_word - read context word into struct 4058 * @src_ctx: the context structure to read from 4059 * @dest_ctx: the context to be written to 4060 * @ce_info: a description of the struct to be filled 4061 */ 4062 static void 4063 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4064 { 4065 u16 dest_word, mask; 4066 u8 *src, *target; 4067 __le16 src_word; 4068 u16 shift_width; 4069 4070 /* prepare the bits and mask */ 4071 shift_width = ce_info->lsb % 8; 4072 mask = BIT(ce_info->width) - 1; 4073 4074 /* shift to correct alignment */ 4075 mask <<= shift_width; 4076 4077 /* get the current bits from the src bit string */ 4078 src = src_ctx + (ce_info->lsb / 8); 4079 4080 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA); 4081 4082 /* the data in the memory is stored as little endian so mask it 4083 * correctly 4084 */ 4085 src_word &= ~(CPU_TO_LE16(mask)); 4086 4087 /* get the data back into host order before shifting */ 4088 dest_word = LE16_TO_CPU(src_word); 4089 4090 dest_word >>= shift_width; 4091 4092 /* get the address from the struct field */ 4093 target = dest_ctx + ce_info->offset; 4094 4095 /* put it back in the struct */ 4096 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 4097 } 4098 4099 /** 4100 * ice_read_dword - read context dword into struct 4101 * @src_ctx: the context structure to read from 4102 * @dest_ctx: the context to be written to 4103 * @ce_info: a description of the struct to be filled 4104 */ 4105 static void 4106 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4107 { 4108 u32 dest_dword, mask; 4109 __le32 src_dword; 4110 u8 *src, *target; 4111 u16 shift_width; 4112 4113 /* prepare the bits and mask */ 4114 shift_width = ce_info->lsb % 8; 4115 4116 /* if the field width is exactly 32 on an x86 machine, then the shift 4117 * operation will not work because the SHL instructions count is masked 4118 * to 5 bits so the shift will do nothing 4119 */ 4120 if (ce_info->width < 32) 4121 mask = BIT(ce_info->width) - 1; 4122 else 4123 mask = (u32)~0; 4124 4125 /* shift to correct alignment */ 4126 mask <<= shift_width; 4127 4128 /* get the current bits from the src bit string */ 4129 src = src_ctx + (ce_info->lsb / 8); 4130 4131 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA); 4132 4133 /* the data in the memory is stored as little endian so mask it 4134 * correctly 4135 */ 4136 src_dword &= ~(CPU_TO_LE32(mask)); 4137 4138 /* get the data back into host order before shifting */ 4139 dest_dword = LE32_TO_CPU(src_dword); 4140 4141 dest_dword >>= shift_width; 4142 4143 /* get the address from the struct field */ 4144 target = dest_ctx + ce_info->offset; 4145 4146 /* put it back in the struct */ 4147 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 4148 } 4149 4150 /** 4151 * ice_read_qword - read context qword into struct 4152 * @src_ctx: the context structure to read from 4153 * @dest_ctx: the context to be written to 4154 * @ce_info: a description of the struct to be filled 4155 */ 4156 static void 4157 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4158 { 4159 u64 dest_qword, mask; 4160 __le64 src_qword; 4161 u8 *src, *target; 4162 u16 shift_width; 4163 4164 /* prepare the bits and mask */ 4165 shift_width = ce_info->lsb % 8; 4166 4167 /* if the field width is exactly 64 on an x86 machine, then the shift 4168 * operation will not work because the SHL instructions count is masked 4169 * to 6 bits so the shift will do nothing 4170 */ 4171 if (ce_info->width < 64) 4172 mask = BIT_ULL(ce_info->width) - 1; 4173 else 4174 mask = (u64)~0; 4175 4176 /* shift to correct alignment */ 4177 mask <<= shift_width; 4178 4179 /* get the current bits from the src bit string */ 4180 src = src_ctx + (ce_info->lsb / 8); 4181 4182 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA); 4183 4184 /* the data in the memory is stored as little endian so mask it 4185 * correctly 4186 */ 4187 src_qword &= ~(CPU_TO_LE64(mask)); 4188 4189 /* get the data back into host order before shifting */ 4190 dest_qword = LE64_TO_CPU(src_qword); 4191 4192 dest_qword >>= shift_width; 4193 4194 /* get the address from the struct field */ 4195 target = dest_ctx + ce_info->offset; 4196 4197 /* put it back in the struct */ 4198 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 4199 } 4200 4201 /** 4202 * ice_get_ctx - extract context bits from a packed structure 4203 * @src_ctx: pointer to a generic packed context structure 4204 * @dest_ctx: pointer to a generic non-packed context structure 4205 * @ce_info: a description of the structure to be read from 4206 */ 4207 enum ice_status 4208 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4209 { 4210 int f; 4211 4212 for (f = 0; ce_info[f].width; f++) { 4213 switch (ce_info[f].size_of) { 4214 case 1: 4215 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]); 4216 break; 4217 case 2: 4218 ice_read_word(src_ctx, dest_ctx, &ce_info[f]); 4219 break; 4220 case 4: 4221 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]); 4222 break; 4223 case 8: 4224 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]); 4225 break; 4226 default: 4227 /* nothing to do, just keep going */ 4228 break; 4229 } 4230 } 4231 4232 return ICE_SUCCESS; 4233 } 4234 4235 /** 4236 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4237 * @hw: pointer to the HW struct 4238 * @vsi_handle: software VSI handle 4239 * @tc: TC number 4240 * @q_handle: software queue handle 4241 */ 4242 struct ice_q_ctx * 4243 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4244 { 4245 struct ice_vsi_ctx *vsi; 4246 struct ice_q_ctx *q_ctx; 4247 4248 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4249 if (!vsi) 4250 return NULL; 4251 if (q_handle >= vsi->num_lan_q_entries[tc]) 4252 return NULL; 4253 if (!vsi->lan_q_ctx[tc]) 4254 return NULL; 4255 q_ctx = vsi->lan_q_ctx[tc]; 4256 return &q_ctx[q_handle]; 4257 } 4258 4259 /** 4260 * ice_ena_vsi_txq 4261 * @pi: port information structure 4262 * @vsi_handle: software VSI handle 4263 * @tc: TC number 4264 * @q_handle: software queue handle 4265 * @num_qgrps: Number of added queue groups 4266 * @buf: list of queue groups to be added 4267 * @buf_size: size of buffer for indirect command 4268 * @cd: pointer to command details structure or NULL 4269 * 4270 * This function adds one LAN queue 4271 */ 4272 enum ice_status 4273 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4274 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4275 struct ice_sq_cd *cd) 4276 { 4277 struct ice_aqc_txsched_elem_data node = { 0 }; 4278 struct ice_sched_node *parent; 4279 struct ice_q_ctx *q_ctx; 4280 enum ice_status status; 4281 struct ice_hw *hw; 4282 4283 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4284 return ICE_ERR_CFG; 4285 4286 if (num_qgrps > 1 || buf->num_txqs > 1) 4287 return ICE_ERR_MAX_LIMIT; 4288 4289 hw = pi->hw; 4290 4291 if (!ice_is_vsi_valid(hw, vsi_handle)) 4292 return ICE_ERR_PARAM; 4293 4294 ice_acquire_lock(&pi->sched_lock); 4295 4296 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4297 if (!q_ctx) { 4298 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4299 q_handle); 4300 status = ICE_ERR_PARAM; 4301 goto ena_txq_exit; 4302 } 4303 4304 /* find a parent node */ 4305 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4306 ICE_SCHED_NODE_OWNER_LAN); 4307 if (!parent) { 4308 status = ICE_ERR_PARAM; 4309 goto ena_txq_exit; 4310 } 4311 4312 buf->parent_teid = parent->info.node_teid; 4313 node.parent_teid = parent->info.node_teid; 4314 /* Mark that the values in the "generic" section as valid. The default 4315 * value in the "generic" section is zero. This means that : 4316 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4317 * - 0 priority among siblings, indicated by Bit 1-3. 4318 * - WFQ, indicated by Bit 4. 4319 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4320 * Bit 5-6. 4321 * - Bit 7 is reserved. 4322 * Without setting the generic section as valid in valid_sections, the 4323 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4324 */ 4325 buf->txqs[0].info.valid_sections = 4326 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4327 ICE_AQC_ELEM_VALID_EIR; 4328 buf->txqs[0].info.generic = 0; 4329 buf->txqs[0].info.cir_bw.bw_profile_idx = 4330 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 4331 buf->txqs[0].info.cir_bw.bw_alloc = 4332 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 4333 buf->txqs[0].info.eir_bw.bw_profile_idx = 4334 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 4335 buf->txqs[0].info.eir_bw.bw_alloc = 4336 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 4337 4338 /* add the LAN queue */ 4339 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4340 if (status != ICE_SUCCESS) { 4341 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4342 LE16_TO_CPU(buf->txqs[0].txq_id), 4343 hw->adminq.sq_last_status); 4344 goto ena_txq_exit; 4345 } 4346 4347 node.node_teid = buf->txqs[0].q_teid; 4348 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4349 q_ctx->q_handle = q_handle; 4350 q_ctx->q_teid = LE32_TO_CPU(node.node_teid); 4351 4352 /* add a leaf node into scheduler tree queue layer */ 4353 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 4354 if (!status) 4355 status = ice_sched_replay_q_bw(pi, q_ctx); 4356 4357 ena_txq_exit: 4358 ice_release_lock(&pi->sched_lock); 4359 return status; 4360 } 4361 4362 /** 4363 * ice_dis_vsi_txq 4364 * @pi: port information structure 4365 * @vsi_handle: software VSI handle 4366 * @tc: TC number 4367 * @num_queues: number of queues 4368 * @q_handles: pointer to software queue handle array 4369 * @q_ids: pointer to the q_id array 4370 * @q_teids: pointer to queue node teids 4371 * @rst_src: if called due to reset, specifies the reset source 4372 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4373 * @cd: pointer to command details structure or NULL 4374 * 4375 * This function removes queues and their corresponding nodes in SW DB 4376 */ 4377 enum ice_status 4378 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4379 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4380 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4381 struct ice_sq_cd *cd) 4382 { 4383 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 4384 struct ice_aqc_dis_txq_item *qg_list; 4385 struct ice_q_ctx *q_ctx; 4386 struct ice_hw *hw; 4387 u16 i, buf_size; 4388 4389 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4390 return ICE_ERR_CFG; 4391 4392 hw = pi->hw; 4393 4394 if (!num_queues) { 4395 /* if queue is disabled already yet the disable queue command 4396 * has to be sent to complete the VF reset, then call 4397 * ice_aq_dis_lan_txq without any queue information 4398 */ 4399 if (rst_src) 4400 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4401 vmvf_num, NULL); 4402 return ICE_ERR_CFG; 4403 } 4404 4405 buf_size = ice_struct_size(qg_list, q_id, 1); 4406 qg_list = (struct ice_aqc_dis_txq_item *)ice_malloc(hw, buf_size); 4407 if (!qg_list) 4408 return ICE_ERR_NO_MEMORY; 4409 4410 ice_acquire_lock(&pi->sched_lock); 4411 4412 for (i = 0; i < num_queues; i++) { 4413 struct ice_sched_node *node; 4414 4415 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4416 if (!node) 4417 continue; 4418 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4419 if (!q_ctx) { 4420 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4421 q_handles[i]); 4422 continue; 4423 } 4424 if (q_ctx->q_handle != q_handles[i]) { 4425 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4426 q_ctx->q_handle, q_handles[i]); 4427 continue; 4428 } 4429 qg_list->parent_teid = node->info.parent_teid; 4430 qg_list->num_qs = 1; 4431 qg_list->q_id[0] = CPU_TO_LE16(q_ids[i]); 4432 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4433 vmvf_num, cd); 4434 4435 if (status != ICE_SUCCESS) 4436 break; 4437 ice_free_sched_node(pi, node); 4438 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 4439 } 4440 ice_release_lock(&pi->sched_lock); 4441 ice_free(hw, qg_list); 4442 return status; 4443 } 4444 4445 /** 4446 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4447 * @pi: port information structure 4448 * @vsi_handle: software VSI handle 4449 * @tc_bitmap: TC bitmap 4450 * @maxqs: max queues array per TC 4451 * @owner: LAN or RDMA 4452 * 4453 * This function adds/updates the VSI queues per TC. 4454 */ 4455 static enum ice_status 4456 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4457 u16 *maxqs, u8 owner) 4458 { 4459 enum ice_status status = ICE_SUCCESS; 4460 u8 i; 4461 4462 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4463 return ICE_ERR_CFG; 4464 4465 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4466 return ICE_ERR_PARAM; 4467 4468 ice_acquire_lock(&pi->sched_lock); 4469 4470 ice_for_each_traffic_class(i) { 4471 /* configuration is possible only if TC node is present */ 4472 if (!ice_sched_get_tc_node(pi, i)) 4473 continue; 4474 4475 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4476 ice_is_tc_ena(tc_bitmap, i)); 4477 if (status) 4478 break; 4479 } 4480 4481 ice_release_lock(&pi->sched_lock); 4482 return status; 4483 } 4484 4485 /** 4486 * ice_cfg_vsi_lan - configure VSI LAN queues 4487 * @pi: port information structure 4488 * @vsi_handle: software VSI handle 4489 * @tc_bitmap: TC bitmap 4490 * @max_lanqs: max LAN queues array per TC 4491 * 4492 * This function adds/updates the VSI LAN queues per TC. 4493 */ 4494 enum ice_status 4495 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4496 u16 *max_lanqs) 4497 { 4498 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4499 ICE_SCHED_NODE_OWNER_LAN); 4500 } 4501 4502 /** 4503 * ice_is_main_vsi - checks whether the VSI is main VSI 4504 * @hw: pointer to the HW struct 4505 * @vsi_handle: VSI handle 4506 * 4507 * Checks whether the VSI is the main VSI (the first PF VSI created on 4508 * given PF). 4509 */ 4510 static bool ice_is_main_vsi(struct ice_hw *hw, u16 vsi_handle) 4511 { 4512 return vsi_handle == ICE_MAIN_VSI_HANDLE && hw->vsi_ctx[vsi_handle]; 4513 } 4514 4515 /** 4516 * ice_replay_pre_init - replay pre initialization 4517 * @hw: pointer to the HW struct 4518 * @sw: pointer to switch info struct for which function initializes filters 4519 * 4520 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 4521 */ 4522 static enum ice_status 4523 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw) 4524 { 4525 enum ice_status status; 4526 u8 i; 4527 4528 /* Delete old entries from replay filter list head if there is any */ 4529 ice_rm_sw_replay_rule_info(hw, sw); 4530 /* In start of replay, move entries into replay_rules list, it 4531 * will allow adding rules entries back to filt_rules list, 4532 * which is operational list. 4533 */ 4534 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 4535 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules, 4536 &sw->recp_list[i].filt_replay_rules); 4537 ice_sched_replay_agg_vsi_preinit(hw); 4538 4539 status = ice_sched_replay_root_node_bw(hw->port_info); 4540 if (status) 4541 return status; 4542 4543 return ice_sched_replay_tc_node_bw(hw->port_info); 4544 } 4545 4546 /** 4547 * ice_replay_vsi - replay VSI configuration 4548 * @hw: pointer to the HW struct 4549 * @vsi_handle: driver VSI handle 4550 * 4551 * Restore all VSI configuration after reset. It is required to call this 4552 * function with main VSI first. 4553 */ 4554 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 4555 { 4556 struct ice_switch_info *sw = hw->switch_info; 4557 struct ice_port_info *pi = hw->port_info; 4558 enum ice_status status; 4559 4560 if (!ice_is_vsi_valid(hw, vsi_handle)) 4561 return ICE_ERR_PARAM; 4562 4563 /* Replay pre-initialization if there is any */ 4564 if (ice_is_main_vsi(hw, vsi_handle)) { 4565 status = ice_replay_pre_init(hw, sw); 4566 if (status) 4567 return status; 4568 } 4569 /* Replay per VSI all RSS configurations */ 4570 status = ice_replay_rss_cfg(hw, vsi_handle); 4571 if (status) 4572 return status; 4573 /* Replay per VSI all filters */ 4574 status = ice_replay_vsi_all_fltr(hw, pi, vsi_handle); 4575 if (!status) 4576 status = ice_replay_vsi_agg(hw, vsi_handle); 4577 return status; 4578 } 4579 4580 /** 4581 * ice_replay_post - post replay configuration cleanup 4582 * @hw: pointer to the HW struct 4583 * 4584 * Post replay cleanup. 4585 */ 4586 void ice_replay_post(struct ice_hw *hw) 4587 { 4588 /* Delete old entries from replay filter list head */ 4589 ice_rm_all_sw_replay_rule_info(hw); 4590 ice_sched_replay_agg(hw); 4591 } 4592 4593 /** 4594 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 4595 * @hw: ptr to the hardware info 4596 * @reg: offset of 64 bit HW register to read from 4597 * @prev_stat_loaded: bool to specify if previous stats are loaded 4598 * @prev_stat: ptr to previous loaded stat value 4599 * @cur_stat: ptr to current stat value 4600 */ 4601 void 4602 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4603 u64 *prev_stat, u64 *cur_stat) 4604 { 4605 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 4606 4607 /* device stats are not reset at PFR, they likely will not be zeroed 4608 * when the driver starts. Thus, save the value from the first read 4609 * without adding to the statistic value so that we report stats which 4610 * count up from zero. 4611 */ 4612 if (!prev_stat_loaded) { 4613 *prev_stat = new_data; 4614 return; 4615 } 4616 4617 /* Calculate the difference between the new and old values, and then 4618 * add it to the software stat value. 4619 */ 4620 if (new_data >= *prev_stat) 4621 *cur_stat += new_data - *prev_stat; 4622 else 4623 /* to manage the potential roll-over */ 4624 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 4625 4626 /* Update the previously stored value to prepare for next read */ 4627 *prev_stat = new_data; 4628 } 4629 4630 /** 4631 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 4632 * @hw: ptr to the hardware info 4633 * @reg: offset of HW register to read from 4634 * @prev_stat_loaded: bool to specify if previous stats are loaded 4635 * @prev_stat: ptr to previous loaded stat value 4636 * @cur_stat: ptr to current stat value 4637 */ 4638 void 4639 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4640 u64 *prev_stat, u64 *cur_stat) 4641 { 4642 u32 new_data; 4643 4644 new_data = rd32(hw, reg); 4645 4646 /* device stats are not reset at PFR, they likely will not be zeroed 4647 * when the driver starts. Thus, save the value from the first read 4648 * without adding to the statistic value so that we report stats which 4649 * count up from zero. 4650 */ 4651 if (!prev_stat_loaded) { 4652 *prev_stat = new_data; 4653 return; 4654 } 4655 4656 /* Calculate the difference between the new and old values, and then 4657 * add it to the software stat value. 4658 */ 4659 if (new_data >= *prev_stat) 4660 *cur_stat += new_data - *prev_stat; 4661 else 4662 /* to manage the potential roll-over */ 4663 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 4664 4665 /* Update the previously stored value to prepare for next read */ 4666 *prev_stat = new_data; 4667 } 4668 4669 /** 4670 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values 4671 * @hw: ptr to the hardware info 4672 * @vsi_handle: VSI handle 4673 * @prev_stat_loaded: bool to specify if the previous stat values are loaded 4674 * @cur_stats: ptr to current stats structure 4675 * 4676 * The GLV_REPC statistic register actually tracks two 16bit statistics, and 4677 * thus cannot be read using the normal ice_stat_update32 function. 4678 * 4679 * Read the GLV_REPC register associated with the given VSI, and update the 4680 * rx_no_desc and rx_error values in the ice_eth_stats structure. 4681 * 4682 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be 4683 * cleared each time it's read. 4684 * 4685 * Note that the GLV_RDPC register also counts the causes that would trigger 4686 * GLV_REPC. However, it does not give the finer grained detail about why the 4687 * packets are being dropped. The GLV_REPC values can be used to distinguish 4688 * whether Rx packets are dropped due to errors or due to no available 4689 * descriptors. 4690 */ 4691 void 4692 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded, 4693 struct ice_eth_stats *cur_stats) 4694 { 4695 u16 vsi_num, no_desc, error_cnt; 4696 u32 repc; 4697 4698 if (!ice_is_vsi_valid(hw, vsi_handle)) 4699 return; 4700 4701 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle); 4702 4703 /* If we haven't loaded stats yet, just clear the current value */ 4704 if (!prev_stat_loaded) { 4705 wr32(hw, GLV_REPC(vsi_num), 0); 4706 return; 4707 } 4708 4709 repc = rd32(hw, GLV_REPC(vsi_num)); 4710 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S; 4711 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S; 4712 4713 /* Clear the count by writing to the stats register */ 4714 wr32(hw, GLV_REPC(vsi_num), 0); 4715 4716 cur_stats->rx_no_desc += no_desc; 4717 cur_stats->rx_errors += error_cnt; 4718 } 4719 4720 /** 4721 * ice_sched_query_elem - query element information from HW 4722 * @hw: pointer to the HW struct 4723 * @node_teid: node TEID to be queried 4724 * @buf: buffer to element information 4725 * 4726 * This function queries HW element information 4727 */ 4728 enum ice_status 4729 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 4730 struct ice_aqc_txsched_elem_data *buf) 4731 { 4732 u16 buf_size, num_elem_ret = 0; 4733 enum ice_status status; 4734 4735 buf_size = sizeof(*buf); 4736 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM); 4737 buf->node_teid = CPU_TO_LE32(node_teid); 4738 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 4739 NULL); 4740 if (status != ICE_SUCCESS || num_elem_ret != 1) 4741 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 4742 return status; 4743 } 4744 4745 /** 4746 * ice_get_fw_mode - returns FW mode 4747 * @hw: pointer to the HW struct 4748 */ 4749 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw) 4750 { 4751 #define ICE_FW_MODE_DBG_M BIT(0) 4752 #define ICE_FW_MODE_REC_M BIT(1) 4753 #define ICE_FW_MODE_ROLLBACK_M BIT(2) 4754 u32 fw_mode; 4755 4756 /* check the current FW mode */ 4757 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M; 4758 4759 if (fw_mode & ICE_FW_MODE_DBG_M) 4760 return ICE_FW_MODE_DBG; 4761 else if (fw_mode & ICE_FW_MODE_REC_M) 4762 return ICE_FW_MODE_REC; 4763 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M) 4764 return ICE_FW_MODE_ROLLBACK; 4765 else 4766 return ICE_FW_MODE_NORMAL; 4767 } 4768 4769 /** 4770 * ice_aq_read_i2c 4771 * @hw: pointer to the hw struct 4772 * @topo_addr: topology address for a device to communicate with 4773 * @bus_addr: 7-bit I2C bus address 4774 * @addr: I2C memory address (I2C offset) with up to 16 bits 4775 * @params: I2C parameters: bit [7] - Repeated start, bits [6:5] data offset size, 4776 * bit [4] - I2C address type, bits [3:0] - data size to read (0-16 bytes) 4777 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 4778 * @cd: pointer to command details structure or NULL 4779 * 4780 * Read I2C (0x06E2) 4781 */ 4782 enum ice_status 4783 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 4784 u16 bus_addr, __le16 addr, u8 params, u8 *data, 4785 struct ice_sq_cd *cd) 4786 { 4787 struct ice_aq_desc desc = { 0 }; 4788 struct ice_aqc_i2c *cmd; 4789 enum ice_status status; 4790 u8 data_size; 4791 4792 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 4793 cmd = &desc.params.read_write_i2c; 4794 4795 if (!data) 4796 return ICE_ERR_PARAM; 4797 4798 data_size = (params & ICE_AQC_I2C_DATA_SIZE_M) >> ICE_AQC_I2C_DATA_SIZE_S; 4799 4800 cmd->i2c_bus_addr = CPU_TO_LE16(bus_addr); 4801 cmd->topo_addr = topo_addr; 4802 cmd->i2c_params = params; 4803 cmd->i2c_addr = addr; 4804 4805 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4806 if (!status) { 4807 struct ice_aqc_read_i2c_resp *resp; 4808 u8 i; 4809 4810 resp = &desc.params.read_i2c_resp; 4811 for (i = 0; i < data_size; i++) { 4812 *data = resp->i2c_data[i]; 4813 data++; 4814 } 4815 } 4816 4817 return status; 4818 } 4819 4820 /** 4821 * ice_aq_write_i2c 4822 * @hw: pointer to the hw struct 4823 * @topo_addr: topology address for a device to communicate with 4824 * @bus_addr: 7-bit I2C bus address 4825 * @addr: I2C memory address (I2C offset) with up to 16 bits 4826 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 4827 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 4828 * @cd: pointer to command details structure or NULL 4829 * 4830 * Write I2C (0x06E3) 4831 */ 4832 enum ice_status 4833 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 4834 u16 bus_addr, __le16 addr, u8 params, u8 *data, 4835 struct ice_sq_cd *cd) 4836 { 4837 struct ice_aq_desc desc = { 0 }; 4838 struct ice_aqc_i2c *cmd; 4839 u8 i, data_size; 4840 4841 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 4842 cmd = &desc.params.read_write_i2c; 4843 4844 data_size = (params & ICE_AQC_I2C_DATA_SIZE_M) >> ICE_AQC_I2C_DATA_SIZE_S; 4845 4846 /* data_size limited to 4 */ 4847 if (data_size > 4) 4848 return ICE_ERR_PARAM; 4849 4850 cmd->i2c_bus_addr = CPU_TO_LE16(bus_addr); 4851 cmd->topo_addr = topo_addr; 4852 cmd->i2c_params = params; 4853 cmd->i2c_addr = addr; 4854 4855 for (i = 0; i < data_size; i++) { 4856 cmd->i2c_data[i] = *data; 4857 data++; 4858 } 4859 4860 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4861 } 4862 4863 /** 4864 * ice_aq_set_gpio 4865 * @hw: pointer to the hw struct 4866 * @gpio_ctrl_handle: GPIO controller node handle 4867 * @pin_idx: IO Number of the GPIO that needs to be set 4868 * @value: SW provide IO value to set in the LSB 4869 * @cd: pointer to command details structure or NULL 4870 * 4871 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 4872 */ 4873 enum ice_status 4874 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 4875 struct ice_sq_cd *cd) 4876 { 4877 struct ice_aqc_gpio *cmd; 4878 struct ice_aq_desc desc; 4879 4880 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 4881 cmd = &desc.params.read_write_gpio; 4882 cmd->gpio_ctrl_handle = gpio_ctrl_handle; 4883 cmd->gpio_num = pin_idx; 4884 cmd->gpio_val = value ? 1 : 0; 4885 4886 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4887 } 4888 4889 /** 4890 * ice_aq_get_gpio 4891 * @hw: pointer to the hw struct 4892 * @gpio_ctrl_handle: GPIO controller node handle 4893 * @pin_idx: IO Number of the GPIO that needs to be set 4894 * @value: IO value read 4895 * @cd: pointer to command details structure or NULL 4896 * 4897 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 4898 * the topology 4899 */ 4900 enum ice_status 4901 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 4902 bool *value, struct ice_sq_cd *cd) 4903 { 4904 struct ice_aqc_gpio *cmd; 4905 struct ice_aq_desc desc; 4906 enum ice_status status; 4907 4908 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 4909 cmd = &desc.params.read_write_gpio; 4910 cmd->gpio_ctrl_handle = gpio_ctrl_handle; 4911 cmd->gpio_num = pin_idx; 4912 4913 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4914 if (status) 4915 return status; 4916 4917 *value = !!cmd->gpio_val; 4918 return ICE_SUCCESS; 4919 } 4920 4921 /** 4922 * ice_fw_supports_link_override 4923 * @hw: pointer to the hardware structure 4924 * 4925 * Checks if the firmware supports link override 4926 */ 4927 bool ice_fw_supports_link_override(struct ice_hw *hw) 4928 { 4929 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) { 4930 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN) 4931 return true; 4932 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN && 4933 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH) 4934 return true; 4935 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) { 4936 return true; 4937 } 4938 4939 return false; 4940 } 4941 4942 /** 4943 * ice_get_link_default_override 4944 * @ldo: pointer to the link default override struct 4945 * @pi: pointer to the port info struct 4946 * 4947 * Gets the link default override for a port 4948 */ 4949 enum ice_status 4950 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 4951 struct ice_port_info *pi) 4952 { 4953 u16 i, tlv, tlv_len, tlv_start, buf, offset; 4954 struct ice_hw *hw = pi->hw; 4955 enum ice_status status; 4956 4957 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 4958 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 4959 if (status) { 4960 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 4961 return status; 4962 } 4963 4964 /* Each port has its own config; calculate for our port */ 4965 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 4966 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 4967 4968 /* link options first */ 4969 status = ice_read_sr_word(hw, tlv_start, &buf); 4970 if (status) { 4971 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4972 return status; 4973 } 4974 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 4975 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 4976 ICE_LINK_OVERRIDE_PHY_CFG_S; 4977 4978 /* link PHY config */ 4979 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 4980 status = ice_read_sr_word(hw, offset, &buf); 4981 if (status) { 4982 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 4983 return status; 4984 } 4985 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 4986 4987 /* PHY types low */ 4988 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 4989 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4990 status = ice_read_sr_word(hw, (offset + i), &buf); 4991 if (status) { 4992 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4993 return status; 4994 } 4995 /* shift 16 bits at a time to fill 64 bits */ 4996 ldo->phy_type_low |= ((u64)buf << (i * 16)); 4997 } 4998 4999 /* PHY types high */ 5000 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 5001 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 5002 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5003 status = ice_read_sr_word(hw, (offset + i), &buf); 5004 if (status) { 5005 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5006 return status; 5007 } 5008 /* shift 16 bits at a time to fill 64 bits */ 5009 ldo->phy_type_high |= ((u64)buf << (i * 16)); 5010 } 5011 5012 return status; 5013 } 5014 5015 /** 5016 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 5017 * @caps: get PHY capability data 5018 */ 5019 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 5020 { 5021 if (caps->caps & ICE_AQC_PHY_AN_MODE || 5022 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 5023 ICE_AQC_PHY_AN_EN_CLAUSE73 | 5024 ICE_AQC_PHY_AN_EN_CLAUSE37)) 5025 return true; 5026 5027 return false; 5028 } 5029 5030 /** 5031 * ice_aq_set_lldp_mib - Set the LLDP MIB 5032 * @hw: pointer to the HW struct 5033 * @mib_type: Local, Remote or both Local and Remote MIBs 5034 * @buf: pointer to the caller-supplied buffer to store the MIB block 5035 * @buf_size: size of the buffer (in bytes) 5036 * @cd: pointer to command details structure or NULL 5037 * 5038 * Set the LLDP MIB. (0x0A08) 5039 */ 5040 enum ice_status 5041 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 5042 struct ice_sq_cd *cd) 5043 { 5044 struct ice_aqc_lldp_set_local_mib *cmd; 5045 struct ice_aq_desc desc; 5046 5047 cmd = &desc.params.lldp_set_mib; 5048 5049 if (buf_size == 0 || !buf) 5050 return ICE_ERR_PARAM; 5051 5052 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 5053 5054 desc.flags |= CPU_TO_LE16((u16)ICE_AQ_FLAG_RD); 5055 desc.datalen = CPU_TO_LE16(buf_size); 5056 5057 cmd->type = mib_type; 5058 cmd->length = CPU_TO_LE16(buf_size); 5059 5060 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 5061 } 5062 5063 /** 5064 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 5065 * @hw: pointer to HW struct 5066 */ 5067 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 5068 { 5069 if (hw->mac_type != ICE_MAC_E810) 5070 return false; 5071 5072 if (hw->api_maj_ver == ICE_FW_API_LLDP_FLTR_MAJ) { 5073 if (hw->api_min_ver > ICE_FW_API_LLDP_FLTR_MIN) 5074 return true; 5075 if (hw->api_min_ver == ICE_FW_API_LLDP_FLTR_MIN && 5076 hw->api_patch >= ICE_FW_API_LLDP_FLTR_PATCH) 5077 return true; 5078 } else if (hw->api_maj_ver > ICE_FW_API_LLDP_FLTR_MAJ) { 5079 return true; 5080 } 5081 return false; 5082 } 5083 5084 /** 5085 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 5086 * @hw: pointer to HW struct 5087 * @vsi_num: absolute HW index for VSI 5088 * @add: boolean for if adding or removing a filter 5089 */ 5090 enum ice_status 5091 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 5092 { 5093 struct ice_aqc_lldp_filter_ctrl *cmd; 5094 struct ice_aq_desc desc; 5095 5096 cmd = &desc.params.lldp_filter_ctrl; 5097 5098 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 5099 5100 if (add) 5101 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 5102 else 5103 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 5104 5105 cmd->vsi_num = CPU_TO_LE16(vsi_num); 5106 5107 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5108 } 5109 5110 /** 5111 * ice_fw_supports_report_dflt_cfg 5112 * @hw: pointer to the hardware structure 5113 * 5114 * Checks if the firmware supports report default configuration 5115 */ 5116 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 5117 { 5118 if (hw->api_maj_ver == ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 5119 if (hw->api_min_ver > ICE_FW_API_REPORT_DFLT_CFG_MIN) 5120 return true; 5121 if (hw->api_min_ver == ICE_FW_API_REPORT_DFLT_CFG_MIN && 5122 hw->api_patch >= ICE_FW_API_REPORT_DFLT_CFG_PATCH) 5123 return true; 5124 } else if (hw->api_maj_ver > ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 5125 return true; 5126 } 5127 return false; 5128 } 5129