1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2021 Intel Corporation 3 */ 4 5 #include "ice_common.h" 6 #include "ice_sched.h" 7 #include "ice_adminq_cmd.h" 8 9 #include "ice_flow.h" 10 #include "ice_switch.h" 11 12 #define ICE_PF_RESET_WAIT_COUNT 300 13 14 /** 15 * dump_phy_type - helper function that prints PHY type strings 16 * @hw: pointer to the HW structure 17 * @phy: 64 bit PHY type to decipher 18 * @i: bit index within phy 19 * @phy_string: string corresponding to bit i in phy 20 * @prefix: prefix string to differentiate multiple dumps 21 */ 22 static void 23 dump_phy_type(struct ice_hw *hw, u64 phy, u8 i, const char *phy_string, 24 const char *prefix) 25 { 26 if (phy & BIT_ULL(i)) 27 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", prefix, i, 28 phy_string); 29 } 30 31 /** 32 * ice_dump_phy_type_low - helper function to dump phy_type_low 33 * @hw: pointer to the HW structure 34 * @low: 64 bit value for phy_type_low 35 * @prefix: prefix string to differentiate multiple dumps 36 */ 37 static void 38 ice_dump_phy_type_low(struct ice_hw *hw, u64 low, const char *prefix) 39 { 40 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, 41 (unsigned long long)low); 42 43 dump_phy_type(hw, low, 0, "100BASE_TX", prefix); 44 dump_phy_type(hw, low, 1, "100M_SGMII", prefix); 45 dump_phy_type(hw, low, 2, "1000BASE_T", prefix); 46 dump_phy_type(hw, low, 3, "1000BASE_SX", prefix); 47 dump_phy_type(hw, low, 4, "1000BASE_LX", prefix); 48 dump_phy_type(hw, low, 5, "1000BASE_KX", prefix); 49 dump_phy_type(hw, low, 6, "1G_SGMII", prefix); 50 dump_phy_type(hw, low, 7, "2500BASE_T", prefix); 51 dump_phy_type(hw, low, 8, "2500BASE_X", prefix); 52 dump_phy_type(hw, low, 9, "2500BASE_KX", prefix); 53 dump_phy_type(hw, low, 10, "5GBASE_T", prefix); 54 dump_phy_type(hw, low, 11, "5GBASE_KR", prefix); 55 dump_phy_type(hw, low, 12, "10GBASE_T", prefix); 56 dump_phy_type(hw, low, 13, "10G_SFI_DA", prefix); 57 dump_phy_type(hw, low, 14, "10GBASE_SR", prefix); 58 dump_phy_type(hw, low, 15, "10GBASE_LR", prefix); 59 dump_phy_type(hw, low, 16, "10GBASE_KR_CR1", prefix); 60 dump_phy_type(hw, low, 17, "10G_SFI_AOC_ACC", prefix); 61 dump_phy_type(hw, low, 18, "10G_SFI_C2C", prefix); 62 dump_phy_type(hw, low, 19, "25GBASE_T", prefix); 63 dump_phy_type(hw, low, 20, "25GBASE_CR", prefix); 64 dump_phy_type(hw, low, 21, "25GBASE_CR_S", prefix); 65 dump_phy_type(hw, low, 22, "25GBASE_CR1", prefix); 66 dump_phy_type(hw, low, 23, "25GBASE_SR", prefix); 67 dump_phy_type(hw, low, 24, "25GBASE_LR", prefix); 68 dump_phy_type(hw, low, 25, "25GBASE_KR", prefix); 69 dump_phy_type(hw, low, 26, "25GBASE_KR_S", prefix); 70 dump_phy_type(hw, low, 27, "25GBASE_KR1", prefix); 71 dump_phy_type(hw, low, 28, "25G_AUI_AOC_ACC", prefix); 72 dump_phy_type(hw, low, 29, "25G_AUI_C2C", prefix); 73 dump_phy_type(hw, low, 30, "40GBASE_CR4", prefix); 74 dump_phy_type(hw, low, 31, "40GBASE_SR4", prefix); 75 dump_phy_type(hw, low, 32, "40GBASE_LR4", prefix); 76 dump_phy_type(hw, low, 33, "40GBASE_KR4", prefix); 77 dump_phy_type(hw, low, 34, "40G_XLAUI_AOC_ACC", prefix); 78 dump_phy_type(hw, low, 35, "40G_XLAUI", prefix); 79 dump_phy_type(hw, low, 36, "50GBASE_CR2", prefix); 80 dump_phy_type(hw, low, 37, "50GBASE_SR2", prefix); 81 dump_phy_type(hw, low, 38, "50GBASE_LR2", prefix); 82 dump_phy_type(hw, low, 39, "50GBASE_KR2", prefix); 83 dump_phy_type(hw, low, 40, "50G_LAUI2_AOC_ACC", prefix); 84 dump_phy_type(hw, low, 41, "50G_LAUI2", prefix); 85 dump_phy_type(hw, low, 42, "50G_AUI2_AOC_ACC", prefix); 86 dump_phy_type(hw, low, 43, "50G_AUI2", prefix); 87 dump_phy_type(hw, low, 44, "50GBASE_CP", prefix); 88 dump_phy_type(hw, low, 45, "50GBASE_SR", prefix); 89 dump_phy_type(hw, low, 46, "50GBASE_FR", prefix); 90 dump_phy_type(hw, low, 47, "50GBASE_LR", prefix); 91 dump_phy_type(hw, low, 48, "50GBASE_KR_PAM4", prefix); 92 dump_phy_type(hw, low, 49, "50G_AUI1_AOC_ACC", prefix); 93 dump_phy_type(hw, low, 50, "50G_AUI1", prefix); 94 dump_phy_type(hw, low, 51, "100GBASE_CR4", prefix); 95 dump_phy_type(hw, low, 52, "100GBASE_SR4", prefix); 96 dump_phy_type(hw, low, 53, "100GBASE_LR4", prefix); 97 dump_phy_type(hw, low, 54, "100GBASE_KR4", prefix); 98 dump_phy_type(hw, low, 55, "100G_CAUI4_AOC_ACC", prefix); 99 dump_phy_type(hw, low, 56, "100G_CAUI4", prefix); 100 dump_phy_type(hw, low, 57, "100G_AUI4_AOC_ACC", prefix); 101 dump_phy_type(hw, low, 58, "100G_AUI4", prefix); 102 dump_phy_type(hw, low, 59, "100GBASE_CR_PAM4", prefix); 103 dump_phy_type(hw, low, 60, "100GBASE_KR_PAM4", prefix); 104 dump_phy_type(hw, low, 61, "100GBASE_CP2", prefix); 105 dump_phy_type(hw, low, 62, "100GBASE_SR2", prefix); 106 dump_phy_type(hw, low, 63, "100GBASE_DR", prefix); 107 } 108 109 /** 110 * ice_dump_phy_type_high - helper function to dump phy_type_high 111 * @hw: pointer to the HW structure 112 * @high: 64 bit value for phy_type_high 113 * @prefix: prefix string to differentiate multiple dumps 114 */ 115 static void 116 ice_dump_phy_type_high(struct ice_hw *hw, u64 high, const char *prefix) 117 { 118 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, 119 (unsigned long long)high); 120 121 dump_phy_type(hw, high, 0, "100GBASE_KR2_PAM4", prefix); 122 dump_phy_type(hw, high, 1, "100G_CAUI2_AOC_ACC", prefix); 123 dump_phy_type(hw, high, 2, "100G_CAUI2", prefix); 124 dump_phy_type(hw, high, 3, "100G_AUI2_AOC_ACC", prefix); 125 dump_phy_type(hw, high, 4, "100G_AUI2", prefix); 126 } 127 128 /** 129 * ice_set_mac_type - Sets MAC type 130 * @hw: pointer to the HW structure 131 * 132 * This function sets the MAC type of the adapter based on the 133 * vendor ID and device ID stored in the HW structure. 134 */ 135 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 136 { 137 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 138 139 if (hw->vendor_id != ICE_INTEL_VENDOR_ID) 140 return ICE_ERR_DEVICE_NOT_SUPPORTED; 141 142 switch (hw->device_id) { 143 case ICE_DEV_ID_E810C_BACKPLANE: 144 case ICE_DEV_ID_E810C_QSFP: 145 case ICE_DEV_ID_E810C_SFP: 146 case ICE_DEV_ID_E810_XXV_BACKPLANE: 147 case ICE_DEV_ID_E810_XXV_QSFP: 148 case ICE_DEV_ID_E810_XXV_SFP: 149 hw->mac_type = ICE_MAC_E810; 150 break; 151 case ICE_DEV_ID_E822C_10G_BASE_T: 152 case ICE_DEV_ID_E822C_BACKPLANE: 153 case ICE_DEV_ID_E822C_QSFP: 154 case ICE_DEV_ID_E822C_SFP: 155 case ICE_DEV_ID_E822C_SGMII: 156 case ICE_DEV_ID_E822L_10G_BASE_T: 157 case ICE_DEV_ID_E822L_BACKPLANE: 158 case ICE_DEV_ID_E822L_SFP: 159 case ICE_DEV_ID_E822L_SGMII: 160 case ICE_DEV_ID_E823L_10G_BASE_T: 161 case ICE_DEV_ID_E823L_1GBE: 162 case ICE_DEV_ID_E823L_BACKPLANE: 163 case ICE_DEV_ID_E823L_QSFP: 164 case ICE_DEV_ID_E823L_SFP: 165 case ICE_DEV_ID_E823C_10G_BASE_T: 166 case ICE_DEV_ID_E823C_BACKPLANE: 167 case ICE_DEV_ID_E823C_QSFP: 168 case ICE_DEV_ID_E823C_SFP: 169 case ICE_DEV_ID_E823C_SGMII: 170 hw->mac_type = ICE_MAC_GENERIC; 171 break; 172 default: 173 hw->mac_type = ICE_MAC_UNKNOWN; 174 break; 175 } 176 177 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 178 return ICE_SUCCESS; 179 } 180 181 /** 182 * ice_is_generic_mac 183 * @hw: pointer to the hardware structure 184 * 185 * returns true if mac_type is ICE_MAC_GENERIC, false if not 186 */ 187 bool ice_is_generic_mac(struct ice_hw *hw) 188 { 189 return hw->mac_type == ICE_MAC_GENERIC; 190 } 191 192 /** 193 * ice_is_e810 194 * @hw: pointer to the hardware structure 195 * 196 * returns true if the device is E810 based, false if not. 197 */ 198 bool ice_is_e810(struct ice_hw *hw) 199 { 200 return hw->mac_type == ICE_MAC_E810; 201 } 202 203 /** 204 * ice_is_e810t 205 * @hw: pointer to the hardware structure 206 * 207 * returns true if the device is E810T based, false if not. 208 */ 209 bool ice_is_e810t(struct ice_hw *hw) 210 { 211 switch (hw->device_id) { 212 case ICE_DEV_ID_E810C_SFP: 213 if (hw->subsystem_device_id == ICE_SUBDEV_ID_E810T || 214 hw->subsystem_device_id == ICE_SUBDEV_ID_E810T2) 215 return true; 216 break; 217 case ICE_DEV_ID_E810C_QSFP: 218 if (hw->subsystem_device_id == ICE_SUBDEV_ID_E810T2) 219 return true; 220 break; 221 default: 222 break; 223 } 224 225 return false; 226 } 227 228 /** 229 * ice_clear_pf_cfg - Clear PF configuration 230 * @hw: pointer to the hardware structure 231 * 232 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 233 * configuration, flow director filters, etc.). 234 */ 235 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 236 { 237 struct ice_aq_desc desc; 238 239 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 240 241 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 242 } 243 244 /** 245 * ice_aq_manage_mac_read - manage MAC address read command 246 * @hw: pointer to the HW struct 247 * @buf: a virtual buffer to hold the manage MAC read response 248 * @buf_size: Size of the virtual buffer 249 * @cd: pointer to command details structure or NULL 250 * 251 * This function is used to return per PF station MAC address (0x0107). 252 * NOTE: Upon successful completion of this command, MAC address information 253 * is returned in user specified buffer. Please interpret user specified 254 * buffer as "manage_mac_read" response. 255 * Response such as various MAC addresses are stored in HW struct (port.mac) 256 * ice_discover_dev_caps is expected to be called before this function is 257 * called. 258 */ 259 static enum ice_status 260 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 261 struct ice_sq_cd *cd) 262 { 263 struct ice_aqc_manage_mac_read_resp *resp; 264 struct ice_aqc_manage_mac_read *cmd; 265 struct ice_aq_desc desc; 266 enum ice_status status; 267 u16 flags; 268 u8 i; 269 270 cmd = &desc.params.mac_read; 271 272 if (buf_size < sizeof(*resp)) 273 return ICE_ERR_BUF_TOO_SHORT; 274 275 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 276 277 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 278 if (status) 279 return status; 280 281 resp = (struct ice_aqc_manage_mac_read_resp *)buf; 282 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 283 284 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 285 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 286 return ICE_ERR_CFG; 287 } 288 289 /* A single port can report up to two (LAN and WoL) addresses */ 290 for (i = 0; i < cmd->num_addr; i++) 291 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 292 ice_memcpy(hw->port_info->mac.lan_addr, 293 resp[i].mac_addr, ETH_ALEN, 294 ICE_DMA_TO_NONDMA); 295 ice_memcpy(hw->port_info->mac.perm_addr, 296 resp[i].mac_addr, 297 ETH_ALEN, ICE_DMA_TO_NONDMA); 298 break; 299 } 300 return ICE_SUCCESS; 301 } 302 303 /** 304 * ice_aq_get_phy_caps - returns PHY capabilities 305 * @pi: port information structure 306 * @qual_mods: report qualified modules 307 * @report_mode: report mode capabilities 308 * @pcaps: structure for PHY capabilities to be filled 309 * @cd: pointer to command details structure or NULL 310 * 311 * Returns the various PHY capabilities supported on the Port (0x0600) 312 */ 313 enum ice_status 314 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 315 struct ice_aqc_get_phy_caps_data *pcaps, 316 struct ice_sq_cd *cd) 317 { 318 struct ice_aqc_get_phy_caps *cmd; 319 u16 pcaps_size = sizeof(*pcaps); 320 struct ice_aq_desc desc; 321 enum ice_status status; 322 const char *prefix; 323 struct ice_hw *hw; 324 325 cmd = &desc.params.get_phy; 326 327 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 328 return ICE_ERR_PARAM; 329 hw = pi->hw; 330 331 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 332 !ice_fw_supports_report_dflt_cfg(hw)) 333 return ICE_ERR_PARAM; 334 335 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 336 337 if (qual_mods) 338 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM); 339 340 cmd->param0 |= CPU_TO_LE16(report_mode); 341 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 342 343 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 344 345 if (report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) 346 prefix = "phy_caps_media"; 347 else if (report_mode == ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA) 348 prefix = "phy_caps_no_media"; 349 else if (report_mode == ICE_AQC_REPORT_ACTIVE_CFG) 350 prefix = "phy_caps_active"; 351 else if (report_mode == ICE_AQC_REPORT_DFLT_CFG) 352 prefix = "phy_caps_default"; 353 else 354 prefix = "phy_caps_invalid"; 355 356 ice_dump_phy_type_low(hw, LE64_TO_CPU(pcaps->phy_type_low), prefix); 357 ice_dump_phy_type_high(hw, LE64_TO_CPU(pcaps->phy_type_high), prefix); 358 359 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 360 prefix, report_mode); 361 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 362 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 363 pcaps->low_power_ctrl_an); 364 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 365 pcaps->eee_cap); 366 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 367 pcaps->eeer_value); 368 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 369 pcaps->link_fec_options); 370 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 371 prefix, pcaps->module_compliance_enforcement); 372 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 373 prefix, pcaps->extended_compliance_code); 374 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 375 pcaps->module_type[0]); 376 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 377 pcaps->module_type[1]); 378 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 379 pcaps->module_type[2]); 380 381 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 382 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low); 383 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high); 384 ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 385 sizeof(pi->phy.link_info.module_type), 386 ICE_NONDMA_TO_NONDMA); 387 } 388 389 return status; 390 } 391 392 /** 393 * ice_aq_get_link_topo_handle - get link topology node return status 394 * @pi: port information structure 395 * @node_type: requested node type 396 * @cd: pointer to command details structure or NULL 397 * 398 * Get link topology node return status for specified node type (0x06E0) 399 * 400 * Node type cage can be used to determine if cage is present. If AQC 401 * returns error (ENOENT), then no cage present. If no cage present, then 402 * connection type is backplane or BASE-T. 403 */ 404 static enum ice_status 405 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 406 struct ice_sq_cd *cd) 407 { 408 struct ice_aqc_get_link_topo *cmd; 409 struct ice_aq_desc desc; 410 411 cmd = &desc.params.get_link_topo; 412 413 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 414 415 cmd->addr.topo_params.node_type_ctx = 416 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 417 ICE_AQC_LINK_TOPO_NODE_CTX_S); 418 419 /* set node type */ 420 cmd->addr.topo_params.node_type_ctx |= 421 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 422 423 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 424 } 425 426 /** 427 * ice_is_media_cage_present 428 * @pi: port information structure 429 * 430 * Returns true if media cage is present, else false. If no cage, then 431 * media type is backplane or BASE-T. 432 */ 433 static bool ice_is_media_cage_present(struct ice_port_info *pi) 434 { 435 /* Node type cage can be used to determine if cage is present. If AQC 436 * returns error (ENOENT), then no cage present. If no cage present then 437 * connection type is backplane or BASE-T. 438 */ 439 return !ice_aq_get_link_topo_handle(pi, 440 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 441 NULL); 442 } 443 444 /** 445 * ice_get_media_type - Gets media type 446 * @pi: port information structure 447 */ 448 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 449 { 450 struct ice_link_status *hw_link_info; 451 452 if (!pi) 453 return ICE_MEDIA_UNKNOWN; 454 455 hw_link_info = &pi->phy.link_info; 456 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 457 /* If more than one media type is selected, report unknown */ 458 return ICE_MEDIA_UNKNOWN; 459 460 if (hw_link_info->phy_type_low) { 461 /* 1G SGMII is a special case where some DA cable PHYs 462 * may show this as an option when it really shouldn't 463 * be since SGMII is meant to be between a MAC and a PHY 464 * in a backplane. Try to detect this case and handle it 465 */ 466 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 467 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 468 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 469 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 470 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 471 return ICE_MEDIA_DA; 472 473 switch (hw_link_info->phy_type_low) { 474 case ICE_PHY_TYPE_LOW_1000BASE_SX: 475 case ICE_PHY_TYPE_LOW_1000BASE_LX: 476 case ICE_PHY_TYPE_LOW_10GBASE_SR: 477 case ICE_PHY_TYPE_LOW_10GBASE_LR: 478 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 479 case ICE_PHY_TYPE_LOW_25GBASE_SR: 480 case ICE_PHY_TYPE_LOW_25GBASE_LR: 481 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 482 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 483 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 484 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 485 case ICE_PHY_TYPE_LOW_50GBASE_SR: 486 case ICE_PHY_TYPE_LOW_50GBASE_FR: 487 case ICE_PHY_TYPE_LOW_50GBASE_LR: 488 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 489 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 490 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 491 case ICE_PHY_TYPE_LOW_100GBASE_DR: 492 return ICE_MEDIA_FIBER; 493 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 494 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 495 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 496 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 497 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 498 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 499 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 500 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 501 return ICE_MEDIA_FIBER; 502 case ICE_PHY_TYPE_LOW_100BASE_TX: 503 case ICE_PHY_TYPE_LOW_1000BASE_T: 504 case ICE_PHY_TYPE_LOW_2500BASE_T: 505 case ICE_PHY_TYPE_LOW_5GBASE_T: 506 case ICE_PHY_TYPE_LOW_10GBASE_T: 507 case ICE_PHY_TYPE_LOW_25GBASE_T: 508 return ICE_MEDIA_BASET; 509 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 510 case ICE_PHY_TYPE_LOW_25GBASE_CR: 511 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 512 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 513 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 514 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 515 case ICE_PHY_TYPE_LOW_50GBASE_CP: 516 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 517 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 518 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 519 return ICE_MEDIA_DA; 520 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 521 case ICE_PHY_TYPE_LOW_40G_XLAUI: 522 case ICE_PHY_TYPE_LOW_50G_LAUI2: 523 case ICE_PHY_TYPE_LOW_50G_AUI2: 524 case ICE_PHY_TYPE_LOW_50G_AUI1: 525 case ICE_PHY_TYPE_LOW_100G_AUI4: 526 case ICE_PHY_TYPE_LOW_100G_CAUI4: 527 if (ice_is_media_cage_present(pi)) 528 return ICE_MEDIA_AUI; 529 /* fall-through */ 530 case ICE_PHY_TYPE_LOW_1000BASE_KX: 531 case ICE_PHY_TYPE_LOW_2500BASE_KX: 532 case ICE_PHY_TYPE_LOW_2500BASE_X: 533 case ICE_PHY_TYPE_LOW_5GBASE_KR: 534 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 535 case ICE_PHY_TYPE_LOW_25GBASE_KR: 536 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 537 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 538 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 539 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 540 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 541 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 542 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 543 return ICE_MEDIA_BACKPLANE; 544 } 545 } else { 546 switch (hw_link_info->phy_type_high) { 547 case ICE_PHY_TYPE_HIGH_100G_AUI2: 548 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 549 if (ice_is_media_cage_present(pi)) 550 return ICE_MEDIA_AUI; 551 /* fall-through */ 552 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 553 return ICE_MEDIA_BACKPLANE; 554 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 555 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 556 return ICE_MEDIA_FIBER; 557 } 558 } 559 return ICE_MEDIA_UNKNOWN; 560 } 561 562 /** 563 * ice_aq_get_link_info 564 * @pi: port information structure 565 * @ena_lse: enable/disable LinkStatusEvent reporting 566 * @link: pointer to link status structure - optional 567 * @cd: pointer to command details structure or NULL 568 * 569 * Get Link Status (0x607). Returns the link status of the adapter. 570 */ 571 enum ice_status 572 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 573 struct ice_link_status *link, struct ice_sq_cd *cd) 574 { 575 struct ice_aqc_get_link_status_data link_data = { 0 }; 576 struct ice_aqc_get_link_status *resp; 577 struct ice_link_status *li_old, *li; 578 enum ice_media_type *hw_media_type; 579 struct ice_fc_info *hw_fc_info; 580 bool tx_pause, rx_pause; 581 struct ice_aq_desc desc; 582 enum ice_status status; 583 struct ice_hw *hw; 584 u16 cmd_flags; 585 586 if (!pi) 587 return ICE_ERR_PARAM; 588 hw = pi->hw; 589 li_old = &pi->phy.link_info_old; 590 hw_media_type = &pi->phy.media_type; 591 li = &pi->phy.link_info; 592 hw_fc_info = &pi->fc; 593 594 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 595 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 596 resp = &desc.params.get_link_status; 597 resp->cmd_flags = CPU_TO_LE16(cmd_flags); 598 resp->lport_num = pi->lport; 599 600 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 601 602 if (status != ICE_SUCCESS) 603 return status; 604 605 /* save off old link status information */ 606 *li_old = *li; 607 608 /* update current link status information */ 609 li->link_speed = LE16_TO_CPU(link_data.link_speed); 610 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low); 611 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high); 612 *hw_media_type = ice_get_media_type(pi); 613 li->link_info = link_data.link_info; 614 li->link_cfg_err = link_data.link_cfg_err; 615 li->an_info = link_data.an_info; 616 li->ext_info = link_data.ext_info; 617 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size); 618 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 619 li->topo_media_conflict = link_data.topo_media_conflict; 620 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 621 ICE_AQ_CFG_PACING_TYPE_M); 622 623 /* update fc info */ 624 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 625 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 626 if (tx_pause && rx_pause) 627 hw_fc_info->current_mode = ICE_FC_FULL; 628 else if (tx_pause) 629 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 630 else if (rx_pause) 631 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 632 else 633 hw_fc_info->current_mode = ICE_FC_NONE; 634 635 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED)); 636 637 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 638 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 639 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 640 (unsigned long long)li->phy_type_low); 641 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 642 (unsigned long long)li->phy_type_high); 643 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 644 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 645 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 646 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 647 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 648 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 649 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 650 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 651 li->max_frame_size); 652 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 653 654 /* save link status information */ 655 if (link) 656 *link = *li; 657 658 /* flag cleared so calling functions don't call AQ again */ 659 pi->phy.get_link_info = false; 660 661 return ICE_SUCCESS; 662 } 663 664 /** 665 * ice_fill_tx_timer_and_fc_thresh 666 * @hw: pointer to the HW struct 667 * @cmd: pointer to MAC cfg structure 668 * 669 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 670 * descriptor 671 */ 672 static void 673 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 674 struct ice_aqc_set_mac_cfg *cmd) 675 { 676 u16 fc_thres_val, tx_timer_val; 677 u32 val; 678 679 /* We read back the transmit timer and fc threshold value of 680 * LFC. Thus, we will use index = 681 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 682 * 683 * Also, because we are opearating on transmit timer and fc 684 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 685 */ 686 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 687 688 /* Retrieve the transmit timer */ 689 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 690 tx_timer_val = val & 691 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 692 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val); 693 694 /* Retrieve the fc threshold */ 695 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 696 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 697 698 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val); 699 } 700 701 /** 702 * ice_aq_set_mac_cfg 703 * @hw: pointer to the HW struct 704 * @max_frame_size: Maximum Frame Size to be supported 705 * @cd: pointer to command details structure or NULL 706 * 707 * Set MAC configuration (0x0603) 708 */ 709 enum ice_status 710 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 711 { 712 struct ice_aqc_set_mac_cfg *cmd; 713 struct ice_aq_desc desc; 714 715 cmd = &desc.params.set_mac_cfg; 716 717 if (max_frame_size == 0) 718 return ICE_ERR_PARAM; 719 720 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 721 722 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 723 724 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 725 726 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 727 } 728 729 /** 730 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 731 * @hw: pointer to the HW struct 732 */ 733 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 734 { 735 struct ice_switch_info *sw; 736 enum ice_status status; 737 738 hw->switch_info = (struct ice_switch_info *) 739 ice_malloc(hw, sizeof(*hw->switch_info)); 740 741 sw = hw->switch_info; 742 743 if (!sw) 744 return ICE_ERR_NO_MEMORY; 745 746 INIT_LIST_HEAD(&sw->vsi_list_map_head); 747 sw->prof_res_bm_init = 0; 748 749 status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list); 750 if (status) { 751 ice_free(hw, hw->switch_info); 752 return status; 753 } 754 return ICE_SUCCESS; 755 } 756 757 /** 758 * ice_cleanup_fltr_mgmt_single - clears single filter mngt struct 759 * @hw: pointer to the HW struct 760 * @sw: pointer to switch info struct for which function clears filters 761 */ 762 static void 763 ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw) 764 { 765 struct ice_vsi_list_map_info *v_pos_map; 766 struct ice_vsi_list_map_info *v_tmp_map; 767 struct ice_sw_recipe *recps; 768 u8 i; 769 770 if (!sw) 771 return; 772 773 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 774 ice_vsi_list_map_info, list_entry) { 775 LIST_DEL(&v_pos_map->list_entry); 776 ice_free(hw, v_pos_map); 777 } 778 recps = sw->recp_list; 779 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 780 struct ice_recp_grp_entry *rg_entry, *tmprg_entry; 781 782 recps[i].root_rid = i; 783 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry, 784 &recps[i].rg_list, ice_recp_grp_entry, 785 l_entry) { 786 LIST_DEL(&rg_entry->l_entry); 787 ice_free(hw, rg_entry); 788 } 789 790 if (recps[i].adv_rule) { 791 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 792 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 793 794 ice_destroy_lock(&recps[i].filt_rule_lock); 795 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 796 &recps[i].filt_rules, 797 ice_adv_fltr_mgmt_list_entry, 798 list_entry) { 799 LIST_DEL(&lst_itr->list_entry); 800 ice_free(hw, lst_itr->lkups); 801 ice_free(hw, lst_itr); 802 } 803 } else { 804 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 805 806 ice_destroy_lock(&recps[i].filt_rule_lock); 807 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 808 &recps[i].filt_rules, 809 ice_fltr_mgmt_list_entry, 810 list_entry) { 811 LIST_DEL(&lst_itr->list_entry); 812 ice_free(hw, lst_itr); 813 } 814 } 815 if (recps[i].root_buf) 816 ice_free(hw, recps[i].root_buf); 817 } 818 ice_rm_sw_replay_rule_info(hw, sw); 819 ice_free(hw, sw->recp_list); 820 ice_free(hw, sw); 821 } 822 823 /** 824 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 825 * @hw: pointer to the HW struct 826 */ 827 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 828 { 829 ice_cleanup_fltr_mgmt_single(hw, hw->switch_info); 830 } 831 832 /** 833 * ice_get_itr_intrl_gran 834 * @hw: pointer to the HW struct 835 * 836 * Determines the ITR/INTRL granularities based on the maximum aggregate 837 * bandwidth according to the device's configuration during power-on. 838 */ 839 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 840 { 841 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 842 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 843 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 844 845 switch (max_agg_bw) { 846 case ICE_MAX_AGG_BW_200G: 847 case ICE_MAX_AGG_BW_100G: 848 case ICE_MAX_AGG_BW_50G: 849 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 850 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 851 break; 852 case ICE_MAX_AGG_BW_25G: 853 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 854 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 855 break; 856 } 857 } 858 859 /** 860 * ice_print_rollback_msg - print FW rollback message 861 * @hw: pointer to the hardware structure 862 */ 863 void ice_print_rollback_msg(struct ice_hw *hw) 864 { 865 char nvm_str[ICE_NVM_VER_LEN] = { 0 }; 866 struct ice_orom_info *orom; 867 struct ice_nvm_info *nvm; 868 869 orom = &hw->flash.orom; 870 nvm = &hw->flash.nvm; 871 872 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", 873 nvm->major, nvm->minor, nvm->eetrack, orom->major, 874 orom->build, orom->patch); 875 ice_warn(hw, 876 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n", 877 nvm_str, hw->fw_maj_ver, hw->fw_min_ver); 878 } 879 880 /** 881 * ice_set_umac_shared 882 * @hw: pointer to the hw struct 883 * 884 * Set boolean flag to allow unicast MAC sharing 885 */ 886 void ice_set_umac_shared(struct ice_hw *hw) 887 { 888 hw->umac_shared = true; 889 } 890 891 /** 892 * ice_init_hw - main hardware initialization routine 893 * @hw: pointer to the hardware structure 894 */ 895 enum ice_status ice_init_hw(struct ice_hw *hw) 896 { 897 struct ice_aqc_get_phy_caps_data *pcaps; 898 enum ice_status status; 899 u16 mac_buf_len; 900 void *mac_buf; 901 902 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 903 904 /* Set MAC type based on DeviceID */ 905 status = ice_set_mac_type(hw); 906 if (status) 907 return status; 908 909 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 910 PF_FUNC_RID_FUNCTION_NUMBER_M) >> 911 PF_FUNC_RID_FUNCTION_NUMBER_S; 912 913 status = ice_reset(hw, ICE_RESET_PFR); 914 if (status) 915 return status; 916 917 ice_get_itr_intrl_gran(hw); 918 919 status = ice_create_all_ctrlq(hw); 920 if (status) 921 goto err_unroll_cqinit; 922 923 status = ice_init_nvm(hw); 924 if (status) 925 goto err_unroll_cqinit; 926 927 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK) 928 ice_print_rollback_msg(hw); 929 930 status = ice_clear_pf_cfg(hw); 931 if (status) 932 goto err_unroll_cqinit; 933 934 /* Set bit to enable Flow Director filters */ 935 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 936 INIT_LIST_HEAD(&hw->fdir_list_head); 937 938 ice_clear_pxe_mode(hw); 939 940 status = ice_get_caps(hw); 941 if (status) 942 goto err_unroll_cqinit; 943 944 hw->port_info = (struct ice_port_info *) 945 ice_malloc(hw, sizeof(*hw->port_info)); 946 if (!hw->port_info) { 947 status = ICE_ERR_NO_MEMORY; 948 goto err_unroll_cqinit; 949 } 950 951 /* set the back pointer to HW */ 952 hw->port_info->hw = hw; 953 954 /* Initialize port_info struct with switch configuration data */ 955 status = ice_get_initial_sw_cfg(hw); 956 if (status) 957 goto err_unroll_alloc; 958 959 hw->evb_veb = true; 960 /* Query the allocated resources for Tx scheduler */ 961 status = ice_sched_query_res_alloc(hw); 962 if (status) { 963 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 964 goto err_unroll_alloc; 965 } 966 ice_sched_get_psm_clk_freq(hw); 967 968 /* Initialize port_info struct with scheduler data */ 969 status = ice_sched_init_port(hw->port_info); 970 if (status) 971 goto err_unroll_sched; 972 pcaps = (struct ice_aqc_get_phy_caps_data *) 973 ice_malloc(hw, sizeof(*pcaps)); 974 if (!pcaps) { 975 status = ICE_ERR_NO_MEMORY; 976 goto err_unroll_sched; 977 } 978 979 /* Initialize port_info struct with PHY capabilities */ 980 status = ice_aq_get_phy_caps(hw->port_info, false, 981 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, NULL); 982 ice_free(hw, pcaps); 983 if (status) 984 ice_warn(hw, "Get PHY capabilities failed status = %d, continuing anyway\n", 985 status); 986 987 /* Initialize port_info struct with link information */ 988 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 989 if (status) 990 goto err_unroll_sched; 991 /* need a valid SW entry point to build a Tx tree */ 992 if (!hw->sw_entry_point_layer) { 993 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 994 status = ICE_ERR_CFG; 995 goto err_unroll_sched; 996 } 997 INIT_LIST_HEAD(&hw->agg_list); 998 /* Initialize max burst size */ 999 if (!hw->max_burst_size) 1000 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1001 status = ice_init_fltr_mgmt_struct(hw); 1002 if (status) 1003 goto err_unroll_sched; 1004 1005 /* Get MAC information */ 1006 /* A single port can report up to two (LAN and WoL) addresses */ 1007 mac_buf = ice_calloc(hw, 2, 1008 sizeof(struct ice_aqc_manage_mac_read_resp)); 1009 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1010 1011 if (!mac_buf) { 1012 status = ICE_ERR_NO_MEMORY; 1013 goto err_unroll_fltr_mgmt_struct; 1014 } 1015 1016 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1017 ice_free(hw, mac_buf); 1018 1019 if (status) 1020 goto err_unroll_fltr_mgmt_struct; 1021 1022 /* enable jumbo frame support at MAC level */ 1023 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1024 if (status) 1025 goto err_unroll_fltr_mgmt_struct; 1026 1027 /* Obtain counter base index which would be used by flow director */ 1028 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1029 if (status) 1030 goto err_unroll_fltr_mgmt_struct; 1031 status = ice_init_hw_tbls(hw); 1032 if (status) 1033 goto err_unroll_fltr_mgmt_struct; 1034 ice_init_lock(&hw->tnl_lock); 1035 1036 return ICE_SUCCESS; 1037 1038 err_unroll_fltr_mgmt_struct: 1039 ice_cleanup_fltr_mgmt_struct(hw); 1040 err_unroll_sched: 1041 ice_sched_cleanup_all(hw); 1042 err_unroll_alloc: 1043 ice_free(hw, hw->port_info); 1044 hw->port_info = NULL; 1045 err_unroll_cqinit: 1046 ice_destroy_all_ctrlq(hw); 1047 return status; 1048 } 1049 1050 /** 1051 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1052 * @hw: pointer to the hardware structure 1053 * 1054 * This should be called only during nominal operation, not as a result of 1055 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1056 * applicable initializations if it fails for any reason. 1057 */ 1058 void ice_deinit_hw(struct ice_hw *hw) 1059 { 1060 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1061 ice_cleanup_fltr_mgmt_struct(hw); 1062 1063 ice_sched_cleanup_all(hw); 1064 ice_sched_clear_agg(hw); 1065 ice_free_seg(hw); 1066 ice_free_hw_tbls(hw); 1067 ice_destroy_lock(&hw->tnl_lock); 1068 1069 if (hw->port_info) { 1070 ice_free(hw, hw->port_info); 1071 hw->port_info = NULL; 1072 } 1073 1074 ice_destroy_all_ctrlq(hw); 1075 1076 /* Clear VSI contexts if not already cleared */ 1077 ice_clear_all_vsi_ctx(hw); 1078 } 1079 1080 /** 1081 * ice_check_reset - Check to see if a global reset is complete 1082 * @hw: pointer to the hardware structure 1083 */ 1084 enum ice_status ice_check_reset(struct ice_hw *hw) 1085 { 1086 u32 cnt, reg = 0, grst_timeout, uld_mask; 1087 1088 /* Poll for Device Active state in case a recent CORER, GLOBR, 1089 * or EMPR has occurred. The grst delay value is in 100ms units. 1090 * Add 1sec for outstanding AQ commands that can take a long time. 1091 */ 1092 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 1093 GLGEN_RSTCTL_GRSTDEL_S) + 10; 1094 1095 for (cnt = 0; cnt < grst_timeout; cnt++) { 1096 ice_msec_delay(100, true); 1097 reg = rd32(hw, GLGEN_RSTAT); 1098 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1099 break; 1100 } 1101 1102 if (cnt == grst_timeout) { 1103 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1104 return ICE_ERR_RESET_FAILED; 1105 } 1106 1107 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1108 GLNVM_ULD_PCIER_DONE_1_M |\ 1109 GLNVM_ULD_CORER_DONE_M |\ 1110 GLNVM_ULD_GLOBR_DONE_M |\ 1111 GLNVM_ULD_POR_DONE_M |\ 1112 GLNVM_ULD_POR_DONE_1_M |\ 1113 GLNVM_ULD_PCIER_DONE_2_M) 1114 1115 uld_mask = ICE_RESET_DONE_MASK; 1116 1117 /* Device is Active; check Global Reset processes are done */ 1118 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1119 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1120 if (reg == uld_mask) { 1121 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1122 break; 1123 } 1124 ice_msec_delay(10, true); 1125 } 1126 1127 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1128 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1129 reg); 1130 return ICE_ERR_RESET_FAILED; 1131 } 1132 1133 return ICE_SUCCESS; 1134 } 1135 1136 /** 1137 * ice_pf_reset - Reset the PF 1138 * @hw: pointer to the hardware structure 1139 * 1140 * If a global reset has been triggered, this function checks 1141 * for its completion and then issues the PF reset 1142 */ 1143 static enum ice_status ice_pf_reset(struct ice_hw *hw) 1144 { 1145 u32 cnt, reg; 1146 1147 /* If at function entry a global reset was already in progress, i.e. 1148 * state is not 'device active' or any of the reset done bits are not 1149 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1150 * global reset is done. 1151 */ 1152 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1153 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1154 /* poll on global reset currently in progress until done */ 1155 if (ice_check_reset(hw)) 1156 return ICE_ERR_RESET_FAILED; 1157 1158 return ICE_SUCCESS; 1159 } 1160 1161 /* Reset the PF */ 1162 reg = rd32(hw, PFGEN_CTRL); 1163 1164 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1165 1166 /* Wait for the PFR to complete. The wait time is the global config lock 1167 * timeout plus the PFR timeout which will account for a possible reset 1168 * that is occurring during a download package operation. 1169 */ 1170 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1171 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1172 reg = rd32(hw, PFGEN_CTRL); 1173 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1174 break; 1175 1176 ice_msec_delay(1, true); 1177 } 1178 1179 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1180 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1181 return ICE_ERR_RESET_FAILED; 1182 } 1183 1184 return ICE_SUCCESS; 1185 } 1186 1187 /** 1188 * ice_reset - Perform different types of reset 1189 * @hw: pointer to the hardware structure 1190 * @req: reset request 1191 * 1192 * This function triggers a reset as specified by the req parameter. 1193 * 1194 * Note: 1195 * If anything other than a PF reset is triggered, PXE mode is restored. 1196 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1197 * interface has been restored in the rebuild flow. 1198 */ 1199 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1200 { 1201 u32 val = 0; 1202 1203 switch (req) { 1204 case ICE_RESET_PFR: 1205 return ice_pf_reset(hw); 1206 case ICE_RESET_CORER: 1207 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1208 val = GLGEN_RTRIG_CORER_M; 1209 break; 1210 case ICE_RESET_GLOBR: 1211 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1212 val = GLGEN_RTRIG_GLOBR_M; 1213 break; 1214 default: 1215 return ICE_ERR_PARAM; 1216 } 1217 1218 val |= rd32(hw, GLGEN_RTRIG); 1219 wr32(hw, GLGEN_RTRIG, val); 1220 ice_flush(hw); 1221 1222 /* wait for the FW to be ready */ 1223 return ice_check_reset(hw); 1224 } 1225 1226 /** 1227 * ice_copy_rxq_ctx_to_hw 1228 * @hw: pointer to the hardware structure 1229 * @ice_rxq_ctx: pointer to the rxq context 1230 * @rxq_index: the index of the Rx queue 1231 * 1232 * Copies rxq context from dense structure to HW register space 1233 */ 1234 static enum ice_status 1235 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1236 { 1237 u8 i; 1238 1239 if (!ice_rxq_ctx) 1240 return ICE_ERR_BAD_PTR; 1241 1242 if (rxq_index > QRX_CTRL_MAX_INDEX) 1243 return ICE_ERR_PARAM; 1244 1245 /* Copy each dword separately to HW */ 1246 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1247 wr32(hw, QRX_CONTEXT(i, rxq_index), 1248 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1249 1250 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1251 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1252 } 1253 1254 return ICE_SUCCESS; 1255 } 1256 1257 /* LAN Rx Queue Context */ 1258 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1259 /* Field Width LSB */ 1260 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1261 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1262 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1263 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1264 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1265 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1266 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1267 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1268 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1269 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1270 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1271 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1272 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1273 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1274 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1275 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1276 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1277 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1278 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1279 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1280 { 0 } 1281 }; 1282 1283 /** 1284 * ice_write_rxq_ctx 1285 * @hw: pointer to the hardware structure 1286 * @rlan_ctx: pointer to the rxq context 1287 * @rxq_index: the index of the Rx queue 1288 * 1289 * Converts rxq context from sparse to dense structure and then writes 1290 * it to HW register space and enables the hardware to prefetch descriptors 1291 * instead of only fetching them on demand 1292 */ 1293 enum ice_status 1294 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1295 u32 rxq_index) 1296 { 1297 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1298 1299 if (!rlan_ctx) 1300 return ICE_ERR_BAD_PTR; 1301 1302 rlan_ctx->prefena = 1; 1303 1304 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1305 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1306 } 1307 1308 /** 1309 * ice_clear_rxq_ctx 1310 * @hw: pointer to the hardware structure 1311 * @rxq_index: the index of the Rx queue to clear 1312 * 1313 * Clears rxq context in HW register space 1314 */ 1315 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index) 1316 { 1317 u8 i; 1318 1319 if (rxq_index > QRX_CTRL_MAX_INDEX) 1320 return ICE_ERR_PARAM; 1321 1322 /* Clear each dword register separately */ 1323 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) 1324 wr32(hw, QRX_CONTEXT(i, rxq_index), 0); 1325 1326 return ICE_SUCCESS; 1327 } 1328 1329 /* LAN Tx Queue Context */ 1330 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1331 /* Field Width LSB */ 1332 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1333 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1334 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1335 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1336 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1337 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1338 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1339 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1340 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1341 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1342 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1343 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1344 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1345 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1346 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1347 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1348 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1349 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1350 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1351 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1352 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1353 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1354 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1355 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1356 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1357 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1358 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1359 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1360 ICE_CTX_STORE(ice_tlan_ctx, gsc_ena, 1, 172), 1361 { 0 } 1362 }; 1363 1364 /** 1365 * ice_copy_tx_cmpltnq_ctx_to_hw 1366 * @hw: pointer to the hardware structure 1367 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context 1368 * @tx_cmpltnq_index: the index of the completion queue 1369 * 1370 * Copies Tx completion queue context from dense structure to HW register space 1371 */ 1372 static enum ice_status 1373 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx, 1374 u32 tx_cmpltnq_index) 1375 { 1376 u8 i; 1377 1378 if (!ice_tx_cmpltnq_ctx) 1379 return ICE_ERR_BAD_PTR; 1380 1381 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 1382 return ICE_ERR_PARAM; 1383 1384 /* Copy each dword separately to HW */ 1385 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) { 1386 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 1387 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 1388 1389 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i, 1390 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 1391 } 1392 1393 return ICE_SUCCESS; 1394 } 1395 1396 /* LAN Tx Completion Queue Context */ 1397 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = { 1398 /* Field Width LSB */ 1399 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0), 1400 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64), 1401 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96), 1402 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97), 1403 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128), 1404 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131), 1405 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141), 1406 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160), 1407 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161), 1408 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192), 1409 { 0 } 1410 }; 1411 1412 /** 1413 * ice_write_tx_cmpltnq_ctx 1414 * @hw: pointer to the hardware structure 1415 * @tx_cmpltnq_ctx: pointer to the completion queue context 1416 * @tx_cmpltnq_index: the index of the completion queue 1417 * 1418 * Converts completion queue context from sparse to dense structure and then 1419 * writes it to HW register space 1420 */ 1421 enum ice_status 1422 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw, 1423 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx, 1424 u32 tx_cmpltnq_index) 1425 { 1426 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 1427 1428 ice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info); 1429 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index); 1430 } 1431 1432 /** 1433 * ice_clear_tx_cmpltnq_ctx 1434 * @hw: pointer to the hardware structure 1435 * @tx_cmpltnq_index: the index of the completion queue to clear 1436 * 1437 * Clears Tx completion queue context in HW register space 1438 */ 1439 enum ice_status 1440 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index) 1441 { 1442 u8 i; 1443 1444 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 1445 return ICE_ERR_PARAM; 1446 1447 /* Clear each dword register separately */ 1448 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) 1449 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0); 1450 1451 return ICE_SUCCESS; 1452 } 1453 1454 /** 1455 * ice_copy_tx_drbell_q_ctx_to_hw 1456 * @hw: pointer to the hardware structure 1457 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context 1458 * @tx_drbell_q_index: the index of the doorbell queue 1459 * 1460 * Copies doorbell queue context from dense structure to HW register space 1461 */ 1462 static enum ice_status 1463 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx, 1464 u32 tx_drbell_q_index) 1465 { 1466 u8 i; 1467 1468 if (!ice_tx_drbell_q_ctx) 1469 return ICE_ERR_BAD_PTR; 1470 1471 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 1472 return ICE_ERR_PARAM; 1473 1474 /* Copy each dword separately to HW */ 1475 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) { 1476 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 1477 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 1478 1479 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i, 1480 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 1481 } 1482 1483 return ICE_SUCCESS; 1484 } 1485 1486 /* LAN Tx Doorbell Queue Context info */ 1487 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = { 1488 /* Field Width LSB */ 1489 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0), 1490 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64), 1491 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80), 1492 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84), 1493 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94), 1494 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96), 1495 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104), 1496 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108), 1497 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112), 1498 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128), 1499 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144), 1500 { 0 } 1501 }; 1502 1503 /** 1504 * ice_write_tx_drbell_q_ctx 1505 * @hw: pointer to the hardware structure 1506 * @tx_drbell_q_ctx: pointer to the doorbell queue context 1507 * @tx_drbell_q_index: the index of the doorbell queue 1508 * 1509 * Converts doorbell queue context from sparse to dense structure and then 1510 * writes it to HW register space 1511 */ 1512 enum ice_status 1513 ice_write_tx_drbell_q_ctx(struct ice_hw *hw, 1514 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx, 1515 u32 tx_drbell_q_index) 1516 { 1517 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 1518 1519 ice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf, 1520 ice_tx_drbell_q_ctx_info); 1521 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index); 1522 } 1523 1524 /** 1525 * ice_clear_tx_drbell_q_ctx 1526 * @hw: pointer to the hardware structure 1527 * @tx_drbell_q_index: the index of the doorbell queue to clear 1528 * 1529 * Clears doorbell queue context in HW register space 1530 */ 1531 enum ice_status 1532 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index) 1533 { 1534 u8 i; 1535 1536 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 1537 return ICE_ERR_PARAM; 1538 1539 /* Clear each dword register separately */ 1540 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) 1541 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0); 1542 1543 return ICE_SUCCESS; 1544 } 1545 1546 /* Sideband Queue command wrappers */ 1547 1548 /** 1549 * ice_get_sbq - returns the right control queue to use for sideband 1550 * @hw: pointer to the hardware structure 1551 */ 1552 static struct ice_ctl_q_info *ice_get_sbq(struct ice_hw *hw) 1553 { 1554 if (!ice_is_generic_mac(hw)) 1555 return &hw->adminq; 1556 return &hw->sbq; 1557 } 1558 1559 /** 1560 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1561 * @hw: pointer to the HW struct 1562 * @desc: descriptor describing the command 1563 * @buf: buffer to use for indirect commands (NULL for direct commands) 1564 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1565 * @cd: pointer to command details structure 1566 */ 1567 static enum ice_status 1568 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1569 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1570 { 1571 return ice_sq_send_cmd(hw, ice_get_sbq(hw), (struct ice_aq_desc *)desc, 1572 buf, buf_size, cd); 1573 } 1574 1575 /** 1576 * ice_sbq_send_cmd_nolock - send Sideband Queue command to Sideband Queue 1577 * but do not lock sq_lock 1578 * @hw: pointer to the HW struct 1579 * @desc: descriptor describing the command 1580 * @buf: buffer to use for indirect commands (NULL for direct commands) 1581 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1582 * @cd: pointer to command details structure 1583 */ 1584 static enum ice_status 1585 ice_sbq_send_cmd_nolock(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1586 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1587 { 1588 return ice_sq_send_cmd_nolock(hw, ice_get_sbq(hw), 1589 (struct ice_aq_desc *)desc, buf, 1590 buf_size, cd); 1591 } 1592 1593 /** 1594 * ice_sbq_rw_reg_lp - Fill Sideband Queue command, with lock parameter 1595 * @hw: pointer to the HW struct 1596 * @in: message info to be filled in descriptor 1597 * @lock: true to lock the sq_lock (the usual case); false if the sq_lock has 1598 * already been locked at a higher level 1599 */ 1600 enum ice_status ice_sbq_rw_reg_lp(struct ice_hw *hw, 1601 struct ice_sbq_msg_input *in, bool lock) 1602 { 1603 struct ice_sbq_cmd_desc desc = {0}; 1604 struct ice_sbq_msg_req msg = {0}; 1605 enum ice_status status; 1606 u16 msg_len; 1607 1608 msg_len = sizeof(msg); 1609 1610 msg.dest_dev = in->dest_dev; 1611 msg.opcode = in->opcode; 1612 msg.flags = ICE_SBQ_MSG_FLAGS; 1613 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1614 msg.msg_addr_low = CPU_TO_LE16(in->msg_addr_low); 1615 msg.msg_addr_high = CPU_TO_LE32(in->msg_addr_high); 1616 1617 if (in->opcode) 1618 msg.data = CPU_TO_LE32(in->data); 1619 else 1620 /* data read comes back in completion, so shorten the struct by 1621 * sizeof(msg.data) 1622 */ 1623 msg_len -= sizeof(msg.data); 1624 1625 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD); 1626 desc.opcode = CPU_TO_LE16(ice_sbq_opc_neigh_dev_req); 1627 desc.param0.cmd_len = CPU_TO_LE16(msg_len); 1628 if (lock) 1629 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1630 else 1631 status = ice_sbq_send_cmd_nolock(hw, &desc, &msg, msg_len, 1632 NULL); 1633 if (!status && !in->opcode) 1634 in->data = LE32_TO_CPU 1635 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1636 return status; 1637 } 1638 1639 /** 1640 * ice_sbq_rw_reg - Fill Sideband Queue command 1641 * @hw: pointer to the HW struct 1642 * @in: message info to be filled in descriptor 1643 */ 1644 enum ice_status ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in) 1645 { 1646 return ice_sbq_rw_reg_lp(hw, in, true); 1647 } 1648 1649 /** 1650 * ice_sbq_lock - Lock the sideband queue's sq_lock 1651 * @hw: pointer to the HW struct 1652 */ 1653 void ice_sbq_lock(struct ice_hw *hw) 1654 { 1655 ice_acquire_lock(&ice_get_sbq(hw)->sq_lock); 1656 } 1657 1658 /** 1659 * ice_sbq_unlock - Unlock the sideband queue's sq_lock 1660 * @hw: pointer to the HW struct 1661 */ 1662 void ice_sbq_unlock(struct ice_hw *hw) 1663 { 1664 ice_release_lock(&ice_get_sbq(hw)->sq_lock); 1665 } 1666 1667 /* FW Admin Queue command wrappers */ 1668 1669 /** 1670 * ice_should_retry_sq_send_cmd 1671 * @opcode: AQ opcode 1672 * 1673 * Decide if we should retry the send command routine for the ATQ, depending 1674 * on the opcode. 1675 */ 1676 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1677 { 1678 switch (opcode) { 1679 case ice_aqc_opc_get_link_topo: 1680 case ice_aqc_opc_lldp_stop: 1681 case ice_aqc_opc_lldp_start: 1682 case ice_aqc_opc_lldp_filter_ctrl: 1683 return true; 1684 } 1685 1686 return false; 1687 } 1688 1689 /** 1690 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1691 * @hw: pointer to the HW struct 1692 * @cq: pointer to the specific Control queue 1693 * @desc: prefilled descriptor describing the command 1694 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1695 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1696 * @cd: pointer to command details structure 1697 * 1698 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1699 * Queue if the EBUSY AQ error is returned. 1700 */ 1701 static enum ice_status 1702 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1703 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1704 struct ice_sq_cd *cd) 1705 { 1706 struct ice_aq_desc desc_cpy; 1707 enum ice_status status; 1708 bool is_cmd_for_retry; 1709 u8 *buf_cpy = NULL; 1710 u8 idx = 0; 1711 u16 opcode; 1712 1713 opcode = LE16_TO_CPU(desc->opcode); 1714 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1715 ice_memset(&desc_cpy, 0, sizeof(desc_cpy), ICE_NONDMA_MEM); 1716 1717 if (is_cmd_for_retry) { 1718 if (buf) { 1719 buf_cpy = (u8 *)ice_malloc(hw, buf_size); 1720 if (!buf_cpy) 1721 return ICE_ERR_NO_MEMORY; 1722 } 1723 1724 ice_memcpy(&desc_cpy, desc, sizeof(desc_cpy), 1725 ICE_NONDMA_TO_NONDMA); 1726 } 1727 1728 do { 1729 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1730 1731 if (!is_cmd_for_retry || status == ICE_SUCCESS || 1732 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1733 break; 1734 1735 if (buf_cpy) 1736 ice_memcpy(buf, buf_cpy, buf_size, 1737 ICE_NONDMA_TO_NONDMA); 1738 1739 ice_memcpy(desc, &desc_cpy, sizeof(desc_cpy), 1740 ICE_NONDMA_TO_NONDMA); 1741 1742 ice_msec_delay(ICE_SQ_SEND_DELAY_TIME_MS, false); 1743 1744 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1745 1746 if (buf_cpy) 1747 ice_free(hw, buf_cpy); 1748 1749 return status; 1750 } 1751 1752 /** 1753 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1754 * @hw: pointer to the HW struct 1755 * @desc: descriptor describing the command 1756 * @buf: buffer to use for indirect commands (NULL for direct commands) 1757 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1758 * @cd: pointer to command details structure 1759 * 1760 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1761 */ 1762 enum ice_status 1763 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1764 u16 buf_size, struct ice_sq_cd *cd) 1765 { 1766 if (hw->aq_send_cmd_fn) { 1767 enum ice_status status = ICE_ERR_NOT_READY; 1768 u16 retval = ICE_AQ_RC_OK; 1769 1770 ice_acquire_lock(&hw->adminq.sq_lock); 1771 if (!hw->aq_send_cmd_fn(hw->aq_send_cmd_param, desc, 1772 buf, buf_size)) { 1773 retval = LE16_TO_CPU(desc->retval); 1774 /* strip off FW internal code */ 1775 if (retval) 1776 retval &= 0xff; 1777 if (retval == ICE_AQ_RC_OK) 1778 status = ICE_SUCCESS; 1779 else 1780 status = ICE_ERR_AQ_ERROR; 1781 } 1782 1783 hw->adminq.sq_last_status = (enum ice_aq_err)retval; 1784 ice_release_lock(&hw->adminq.sq_lock); 1785 1786 return status; 1787 } 1788 return ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1789 } 1790 1791 /** 1792 * ice_aq_get_fw_ver 1793 * @hw: pointer to the HW struct 1794 * @cd: pointer to command details structure or NULL 1795 * 1796 * Get the firmware version (0x0001) from the admin queue commands 1797 */ 1798 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1799 { 1800 struct ice_aqc_get_ver *resp; 1801 struct ice_aq_desc desc; 1802 enum ice_status status; 1803 1804 resp = &desc.params.get_ver; 1805 1806 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1807 1808 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1809 1810 if (!status) { 1811 hw->fw_branch = resp->fw_branch; 1812 hw->fw_maj_ver = resp->fw_major; 1813 hw->fw_min_ver = resp->fw_minor; 1814 hw->fw_patch = resp->fw_patch; 1815 hw->fw_build = LE32_TO_CPU(resp->fw_build); 1816 hw->api_branch = resp->api_branch; 1817 hw->api_maj_ver = resp->api_major; 1818 hw->api_min_ver = resp->api_minor; 1819 hw->api_patch = resp->api_patch; 1820 } 1821 1822 return status; 1823 } 1824 1825 /** 1826 * ice_aq_send_driver_ver 1827 * @hw: pointer to the HW struct 1828 * @dv: driver's major, minor version 1829 * @cd: pointer to command details structure or NULL 1830 * 1831 * Send the driver version (0x0002) to the firmware 1832 */ 1833 enum ice_status 1834 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1835 struct ice_sq_cd *cd) 1836 { 1837 struct ice_aqc_driver_ver *cmd; 1838 struct ice_aq_desc desc; 1839 u16 len; 1840 1841 cmd = &desc.params.driver_ver; 1842 1843 if (!dv) 1844 return ICE_ERR_PARAM; 1845 1846 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1847 1848 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 1849 cmd->major_ver = dv->major_ver; 1850 cmd->minor_ver = dv->minor_ver; 1851 cmd->build_ver = dv->build_ver; 1852 cmd->subbuild_ver = dv->subbuild_ver; 1853 1854 len = 0; 1855 while (len < sizeof(dv->driver_string) && 1856 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len]) 1857 len++; 1858 1859 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1860 } 1861 1862 /** 1863 * ice_aq_q_shutdown 1864 * @hw: pointer to the HW struct 1865 * @unloading: is the driver unloading itself 1866 * 1867 * Tell the Firmware that we're shutting down the AdminQ and whether 1868 * or not the driver is unloading as well (0x0003). 1869 */ 1870 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1871 { 1872 struct ice_aqc_q_shutdown *cmd; 1873 struct ice_aq_desc desc; 1874 1875 cmd = &desc.params.q_shutdown; 1876 1877 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1878 1879 if (unloading) 1880 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1881 1882 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1883 } 1884 1885 /** 1886 * ice_aq_req_res 1887 * @hw: pointer to the HW struct 1888 * @res: resource ID 1889 * @access: access type 1890 * @sdp_number: resource number 1891 * @timeout: the maximum time in ms that the driver may hold the resource 1892 * @cd: pointer to command details structure or NULL 1893 * 1894 * Requests common resource using the admin queue commands (0x0008). 1895 * When attempting to acquire the Global Config Lock, the driver can 1896 * learn of three states: 1897 * 1) ICE_SUCCESS - acquired lock, and can perform download package 1898 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1899 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1900 * successfully downloaded the package; the driver does 1901 * not have to download the package and can continue 1902 * loading 1903 * 1904 * Note that if the caller is in an acquire lock, perform action, release lock 1905 * phase of operation, it is possible that the FW may detect a timeout and issue 1906 * a CORER. In this case, the driver will receive a CORER interrupt and will 1907 * have to determine its cause. The calling thread that is handling this flow 1908 * will likely get an error propagated back to it indicating the Download 1909 * Package, Update Package or the Release Resource AQ commands timed out. 1910 */ 1911 static enum ice_status 1912 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1913 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1914 struct ice_sq_cd *cd) 1915 { 1916 struct ice_aqc_req_res *cmd_resp; 1917 struct ice_aq_desc desc; 1918 enum ice_status status; 1919 1920 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1921 1922 cmd_resp = &desc.params.res_owner; 1923 1924 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1925 1926 cmd_resp->res_id = CPU_TO_LE16(res); 1927 cmd_resp->access_type = CPU_TO_LE16(access); 1928 cmd_resp->res_number = CPU_TO_LE32(sdp_number); 1929 cmd_resp->timeout = CPU_TO_LE32(*timeout); 1930 *timeout = 0; 1931 1932 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1933 1934 /* The completion specifies the maximum time in ms that the driver 1935 * may hold the resource in the Timeout field. 1936 */ 1937 1938 /* Global config lock response utilizes an additional status field. 1939 * 1940 * If the Global config lock resource is held by some other driver, the 1941 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1942 * and the timeout field indicates the maximum time the current owner 1943 * of the resource has to free it. 1944 */ 1945 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1946 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1947 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1948 return ICE_SUCCESS; 1949 } else if (LE16_TO_CPU(cmd_resp->status) == 1950 ICE_AQ_RES_GLBL_IN_PROG) { 1951 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1952 return ICE_ERR_AQ_ERROR; 1953 } else if (LE16_TO_CPU(cmd_resp->status) == 1954 ICE_AQ_RES_GLBL_DONE) { 1955 return ICE_ERR_AQ_NO_WORK; 1956 } 1957 1958 /* invalid FW response, force a timeout immediately */ 1959 *timeout = 0; 1960 return ICE_ERR_AQ_ERROR; 1961 } 1962 1963 /* If the resource is held by some other driver, the command completes 1964 * with a busy return value and the timeout field indicates the maximum 1965 * time the current owner of the resource has to free it. 1966 */ 1967 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1968 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1969 1970 return status; 1971 } 1972 1973 /** 1974 * ice_aq_release_res 1975 * @hw: pointer to the HW struct 1976 * @res: resource ID 1977 * @sdp_number: resource number 1978 * @cd: pointer to command details structure or NULL 1979 * 1980 * release common resource using the admin queue commands (0x0009) 1981 */ 1982 static enum ice_status 1983 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1984 struct ice_sq_cd *cd) 1985 { 1986 struct ice_aqc_req_res *cmd; 1987 struct ice_aq_desc desc; 1988 1989 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1990 1991 cmd = &desc.params.res_owner; 1992 1993 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1994 1995 cmd->res_id = CPU_TO_LE16(res); 1996 cmd->res_number = CPU_TO_LE32(sdp_number); 1997 1998 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1999 } 2000 2001 /** 2002 * ice_acquire_res 2003 * @hw: pointer to the HW structure 2004 * @res: resource ID 2005 * @access: access type (read or write) 2006 * @timeout: timeout in milliseconds 2007 * 2008 * This function will attempt to acquire the ownership of a resource. 2009 */ 2010 enum ice_status 2011 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2012 enum ice_aq_res_access_type access, u32 timeout) 2013 { 2014 #define ICE_RES_POLLING_DELAY_MS 10 2015 u32 delay = ICE_RES_POLLING_DELAY_MS; 2016 u32 time_left = timeout; 2017 enum ice_status status; 2018 2019 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 2020 2021 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2022 2023 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 2024 * previously acquired the resource and performed any necessary updates; 2025 * in this case the caller does not obtain the resource and has no 2026 * further work to do. 2027 */ 2028 if (status == ICE_ERR_AQ_NO_WORK) 2029 goto ice_acquire_res_exit; 2030 2031 if (status) 2032 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 2033 2034 /* If necessary, poll until the current lock owner timeouts */ 2035 timeout = time_left; 2036 while (status && timeout && time_left) { 2037 ice_msec_delay(delay, true); 2038 timeout = (timeout > delay) ? timeout - delay : 0; 2039 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2040 2041 if (status == ICE_ERR_AQ_NO_WORK) 2042 /* lock free, but no work to do */ 2043 break; 2044 2045 if (!status) 2046 /* lock acquired */ 2047 break; 2048 } 2049 if (status && status != ICE_ERR_AQ_NO_WORK) 2050 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 2051 2052 ice_acquire_res_exit: 2053 if (status == ICE_ERR_AQ_NO_WORK) { 2054 if (access == ICE_RES_WRITE) 2055 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 2056 else 2057 ice_debug(hw, ICE_DBG_RES, "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 2058 } 2059 return status; 2060 } 2061 2062 /** 2063 * ice_release_res 2064 * @hw: pointer to the HW structure 2065 * @res: resource ID 2066 * 2067 * This function will release a resource using the proper Admin Command. 2068 */ 2069 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 2070 { 2071 enum ice_status status; 2072 u32 total_delay = 0; 2073 2074 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 2075 2076 status = ice_aq_release_res(hw, res, 0, NULL); 2077 2078 /* there are some rare cases when trying to release the resource 2079 * results in an admin queue timeout, so handle them correctly 2080 */ 2081 while ((status == ICE_ERR_AQ_TIMEOUT) && 2082 (total_delay < hw->adminq.sq_cmd_timeout)) { 2083 ice_msec_delay(1, true); 2084 status = ice_aq_release_res(hw, res, 0, NULL); 2085 total_delay++; 2086 } 2087 } 2088 2089 /** 2090 * ice_aq_alloc_free_res - command to allocate/free resources 2091 * @hw: pointer to the HW struct 2092 * @num_entries: number of resource entries in buffer 2093 * @buf: Indirect buffer to hold data parameters and response 2094 * @buf_size: size of buffer for indirect commands 2095 * @opc: pass in the command opcode 2096 * @cd: pointer to command details structure or NULL 2097 * 2098 * Helper function to allocate/free resources using the admin queue commands 2099 */ 2100 enum ice_status 2101 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 2102 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 2103 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2104 { 2105 struct ice_aqc_alloc_free_res_cmd *cmd; 2106 struct ice_aq_desc desc; 2107 2108 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 2109 2110 cmd = &desc.params.sw_res_ctrl; 2111 2112 if (!buf) 2113 return ICE_ERR_PARAM; 2114 2115 if (buf_size < FLEX_ARRAY_SIZE(buf, elem, num_entries)) 2116 return ICE_ERR_PARAM; 2117 2118 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2119 2120 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 2121 2122 cmd->num_entries = CPU_TO_LE16(num_entries); 2123 2124 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2125 } 2126 2127 /** 2128 * ice_alloc_hw_res - allocate resource 2129 * @hw: pointer to the HW struct 2130 * @type: type of resource 2131 * @num: number of resources to allocate 2132 * @btm: allocate from bottom 2133 * @res: pointer to array that will receive the resources 2134 */ 2135 enum ice_status 2136 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2137 { 2138 struct ice_aqc_alloc_free_res_elem *buf; 2139 enum ice_status status; 2140 u16 buf_len; 2141 2142 buf_len = ice_struct_size(buf, elem, num); 2143 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); 2144 if (!buf) 2145 return ICE_ERR_NO_MEMORY; 2146 2147 /* Prepare buffer to allocate resource. */ 2148 buf->num_elems = CPU_TO_LE16(num); 2149 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2150 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2151 if (btm) 2152 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2153 2154 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 2155 ice_aqc_opc_alloc_res, NULL); 2156 if (status) 2157 goto ice_alloc_res_exit; 2158 2159 ice_memcpy(res, buf->elem, sizeof(*buf->elem) * num, 2160 ICE_NONDMA_TO_NONDMA); 2161 2162 ice_alloc_res_exit: 2163 ice_free(hw, buf); 2164 return status; 2165 } 2166 2167 /** 2168 * ice_free_hw_res - free allocated HW resource 2169 * @hw: pointer to the HW struct 2170 * @type: type of resource to free 2171 * @num: number of resources 2172 * @res: pointer to array that contains the resources to free 2173 */ 2174 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2175 { 2176 struct ice_aqc_alloc_free_res_elem *buf; 2177 enum ice_status status; 2178 u16 buf_len; 2179 2180 buf_len = ice_struct_size(buf, elem, num); 2181 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); 2182 if (!buf) 2183 return ICE_ERR_NO_MEMORY; 2184 2185 /* Prepare buffer to free resource. */ 2186 buf->num_elems = CPU_TO_LE16(num); 2187 buf->res_type = CPU_TO_LE16(type); 2188 ice_memcpy(buf->elem, res, sizeof(*buf->elem) * num, 2189 ICE_NONDMA_TO_NONDMA); 2190 2191 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 2192 ice_aqc_opc_free_res, NULL); 2193 if (status) 2194 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2195 2196 ice_free(hw, buf); 2197 return status; 2198 } 2199 2200 /** 2201 * ice_get_num_per_func - determine number of resources per PF 2202 * @hw: pointer to the HW structure 2203 * @max: value to be evenly split between each PF 2204 * 2205 * Determine the number of valid functions by going through the bitmap returned 2206 * from parsing capabilities and use this to calculate the number of resources 2207 * per PF based on the max value passed in. 2208 */ 2209 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2210 { 2211 u8 funcs; 2212 2213 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2214 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions & 2215 ICE_CAPS_VALID_FUNCS_M); 2216 2217 if (!funcs) 2218 return 0; 2219 2220 return max / funcs; 2221 } 2222 2223 /** 2224 * ice_parse_common_caps - parse common device/function capabilities 2225 * @hw: pointer to the HW struct 2226 * @caps: pointer to common capabilities structure 2227 * @elem: the capability element to parse 2228 * @prefix: message prefix for tracing capabilities 2229 * 2230 * Given a capability element, extract relevant details into the common 2231 * capability structure. 2232 * 2233 * Returns: true if the capability matches one of the common capability ids, 2234 * false otherwise. 2235 */ 2236 static bool 2237 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2238 struct ice_aqc_list_caps_elem *elem, const char *prefix) 2239 { 2240 u32 logical_id = LE32_TO_CPU(elem->logical_id); 2241 u32 phys_id = LE32_TO_CPU(elem->phys_id); 2242 u32 number = LE32_TO_CPU(elem->number); 2243 u16 cap = LE16_TO_CPU(elem->cap); 2244 bool found = true; 2245 2246 switch (cap) { 2247 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2248 caps->valid_functions = number; 2249 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2250 caps->valid_functions); 2251 break; 2252 case ICE_AQC_CAPS_DCB: 2253 caps->dcb = (number == 1); 2254 caps->active_tc_bitmap = logical_id; 2255 caps->maxtc = phys_id; 2256 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2257 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2258 caps->active_tc_bitmap); 2259 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2260 break; 2261 case ICE_AQC_CAPS_RSS: 2262 caps->rss_table_size = number; 2263 caps->rss_table_entry_width = logical_id; 2264 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2265 caps->rss_table_size); 2266 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2267 caps->rss_table_entry_width); 2268 break; 2269 case ICE_AQC_CAPS_RXQS: 2270 caps->num_rxq = number; 2271 caps->rxq_first_id = phys_id; 2272 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2273 caps->num_rxq); 2274 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2275 caps->rxq_first_id); 2276 break; 2277 case ICE_AQC_CAPS_TXQS: 2278 caps->num_txq = number; 2279 caps->txq_first_id = phys_id; 2280 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2281 caps->num_txq); 2282 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2283 caps->txq_first_id); 2284 break; 2285 case ICE_AQC_CAPS_MSIX: 2286 caps->num_msix_vectors = number; 2287 caps->msix_vector_first_id = phys_id; 2288 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2289 caps->num_msix_vectors); 2290 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2291 caps->msix_vector_first_id); 2292 break; 2293 case ICE_AQC_CAPS_NVM_MGMT: 2294 caps->sec_rev_disabled = 2295 (number & ICE_NVM_MGMT_SEC_REV_DISABLED) ? 2296 true : false; 2297 ice_debug(hw, ICE_DBG_INIT, "%s: sec_rev_disabled = %d\n", prefix, 2298 caps->sec_rev_disabled); 2299 caps->update_disabled = 2300 (number & ICE_NVM_MGMT_UPDATE_DISABLED) ? 2301 true : false; 2302 ice_debug(hw, ICE_DBG_INIT, "%s: update_disabled = %d\n", prefix, 2303 caps->update_disabled); 2304 caps->nvm_unified_update = 2305 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2306 true : false; 2307 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2308 caps->nvm_unified_update); 2309 break; 2310 case ICE_AQC_CAPS_MAX_MTU: 2311 caps->max_mtu = number; 2312 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2313 prefix, caps->max_mtu); 2314 break; 2315 case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2316 caps->pcie_reset_avoidance = (number > 0); 2317 ice_debug(hw, ICE_DBG_INIT, 2318 "%s: pcie_reset_avoidance = %d\n", prefix, 2319 caps->pcie_reset_avoidance); 2320 break; 2321 case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2322 caps->reset_restrict_support = (number == 1); 2323 ice_debug(hw, ICE_DBG_INIT, 2324 "%s: reset_restrict_support = %d\n", prefix, 2325 caps->reset_restrict_support); 2326 break; 2327 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0: 2328 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1: 2329 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2: 2330 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3: 2331 { 2332 u8 index = cap - ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0; 2333 2334 caps->ext_topo_dev_img_ver_high[index] = number; 2335 caps->ext_topo_dev_img_ver_low[index] = logical_id; 2336 caps->ext_topo_dev_img_part_num[index] = 2337 (phys_id & ICE_EXT_TOPO_DEV_IMG_PART_NUM_M) >> 2338 ICE_EXT_TOPO_DEV_IMG_PART_NUM_S; 2339 caps->ext_topo_dev_img_load_en[index] = 2340 (phys_id & ICE_EXT_TOPO_DEV_IMG_LOAD_EN) != 0; 2341 caps->ext_topo_dev_img_prog_en[index] = 2342 (phys_id & ICE_EXT_TOPO_DEV_IMG_PROG_EN) != 0; 2343 ice_debug(hw, ICE_DBG_INIT, 2344 "%s: ext_topo_dev_img_ver_high[%d] = %d\n", 2345 prefix, index, 2346 caps->ext_topo_dev_img_ver_high[index]); 2347 ice_debug(hw, ICE_DBG_INIT, 2348 "%s: ext_topo_dev_img_ver_low[%d] = %d\n", 2349 prefix, index, 2350 caps->ext_topo_dev_img_ver_low[index]); 2351 ice_debug(hw, ICE_DBG_INIT, 2352 "%s: ext_topo_dev_img_part_num[%d] = %d\n", 2353 prefix, index, 2354 caps->ext_topo_dev_img_part_num[index]); 2355 ice_debug(hw, ICE_DBG_INIT, 2356 "%s: ext_topo_dev_img_load_en[%d] = %d\n", 2357 prefix, index, 2358 caps->ext_topo_dev_img_load_en[index]); 2359 ice_debug(hw, ICE_DBG_INIT, 2360 "%s: ext_topo_dev_img_prog_en[%d] = %d\n", 2361 prefix, index, 2362 caps->ext_topo_dev_img_prog_en[index]); 2363 break; 2364 } 2365 default: 2366 /* Not one of the recognized common capabilities */ 2367 found = false; 2368 } 2369 2370 return found; 2371 } 2372 2373 /** 2374 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2375 * @hw: pointer to the HW structure 2376 * @caps: pointer to capabilities structure to fix 2377 * 2378 * Re-calculate the capabilities that are dependent on the number of physical 2379 * ports; i.e. some features are not supported or function differently on 2380 * devices with more than 4 ports. 2381 */ 2382 static void 2383 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2384 { 2385 /* This assumes device capabilities are always scanned before function 2386 * capabilities during the initialization flow. 2387 */ 2388 if (hw->dev_caps.num_funcs > 4) { 2389 /* Max 4 TCs per port */ 2390 caps->maxtc = 4; 2391 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2392 caps->maxtc); 2393 } 2394 } 2395 2396 /** 2397 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2398 * @hw: pointer to the HW struct 2399 * @func_p: pointer to function capabilities structure 2400 * @cap: pointer to the capability element to parse 2401 * 2402 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2403 */ 2404 static void 2405 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2406 struct ice_aqc_list_caps_elem *cap) 2407 { 2408 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2409 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2410 LE32_TO_CPU(cap->number)); 2411 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2412 func_p->guar_num_vsi); 2413 } 2414 2415 /** 2416 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2417 * @hw: pointer to the HW struct 2418 * @func_p: pointer to function capabilities structure 2419 * @cap: pointer to the capability element to parse 2420 * 2421 * Extract function capabilities for ICE_AQC_CAPS_1588. 2422 */ 2423 static void 2424 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2425 struct ice_aqc_list_caps_elem *cap) 2426 { 2427 struct ice_ts_func_info *info = &func_p->ts_func_info; 2428 u32 number = LE32_TO_CPU(cap->number); 2429 2430 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2431 func_p->common_cap.ieee_1588 = info->ena; 2432 2433 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2434 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2435 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2436 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2437 2438 info->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S; 2439 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2440 2441 if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) { 2442 info->time_ref = (enum ice_time_ref_freq)info->clk_freq; 2443 } else { 2444 /* Unknown clock frequency, so assume a (probably incorrect) 2445 * default to avoid out-of-bounds look ups of frequency 2446 * related information. 2447 */ 2448 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2449 info->clk_freq); 2450 info->time_ref = ICE_TIME_REF_FREQ_25_000; 2451 } 2452 2453 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2454 func_p->common_cap.ieee_1588); 2455 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2456 info->src_tmr_owned); 2457 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2458 info->tmr_ena); 2459 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2460 info->tmr_index_owned); 2461 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2462 info->tmr_index_assoc); 2463 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2464 info->clk_freq); 2465 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2466 info->clk_src); 2467 } 2468 2469 /** 2470 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2471 * @hw: pointer to the HW struct 2472 * @func_p: pointer to function capabilities structure 2473 * 2474 * Extract function capabilities for ICE_AQC_CAPS_FD. 2475 */ 2476 static void 2477 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2478 { 2479 u32 reg_val, val; 2480 2481 if (hw->dcf_enabled) 2482 return; 2483 reg_val = rd32(hw, GLQF_FD_SIZE); 2484 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 2485 GLQF_FD_SIZE_FD_GSIZE_S; 2486 func_p->fd_fltr_guar = 2487 ice_get_num_per_func(hw, val); 2488 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 2489 GLQF_FD_SIZE_FD_BSIZE_S; 2490 func_p->fd_fltr_best_effort = val; 2491 2492 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2493 func_p->fd_fltr_guar); 2494 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2495 func_p->fd_fltr_best_effort); 2496 } 2497 2498 /** 2499 * ice_parse_func_caps - Parse function capabilities 2500 * @hw: pointer to the HW struct 2501 * @func_p: pointer to function capabilities structure 2502 * @buf: buffer containing the function capability records 2503 * @cap_count: the number of capabilities 2504 * 2505 * Helper function to parse function (0x000A) capabilities list. For 2506 * capabilities shared between device and function, this relies on 2507 * ice_parse_common_caps. 2508 * 2509 * Loop through the list of provided capabilities and extract the relevant 2510 * data into the function capabilities structured. 2511 */ 2512 static void 2513 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2514 void *buf, u32 cap_count) 2515 { 2516 struct ice_aqc_list_caps_elem *cap_resp; 2517 u32 i; 2518 2519 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 2520 2521 ice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM); 2522 2523 for (i = 0; i < cap_count; i++) { 2524 u16 cap = LE16_TO_CPU(cap_resp[i].cap); 2525 bool found; 2526 2527 found = ice_parse_common_caps(hw, &func_p->common_cap, 2528 &cap_resp[i], "func caps"); 2529 2530 switch (cap) { 2531 case ICE_AQC_CAPS_VSI: 2532 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2533 break; 2534 case ICE_AQC_CAPS_1588: 2535 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2536 break; 2537 case ICE_AQC_CAPS_FD: 2538 ice_parse_fdir_func_caps(hw, func_p); 2539 break; 2540 default: 2541 /* Don't list common capabilities as unknown */ 2542 if (!found) 2543 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2544 i, cap); 2545 break; 2546 } 2547 } 2548 2549 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2550 } 2551 2552 /** 2553 * ice_func_id_to_logical_id - map from function id to logical pf id 2554 * @active_function_bitmap: active function bitmap 2555 * @pf_id: function number of device 2556 */ 2557 static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id) 2558 { 2559 u8 logical_id = 0; 2560 u8 i; 2561 2562 for (i = 0; i < pf_id; i++) 2563 if (active_function_bitmap & BIT(i)) 2564 logical_id++; 2565 2566 return logical_id; 2567 } 2568 2569 /** 2570 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2571 * @hw: pointer to the HW struct 2572 * @dev_p: pointer to device capabilities structure 2573 * @cap: capability element to parse 2574 * 2575 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2576 */ 2577 static void 2578 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2579 struct ice_aqc_list_caps_elem *cap) 2580 { 2581 u32 number = LE32_TO_CPU(cap->number); 2582 2583 dev_p->num_funcs = ice_hweight32(number); 2584 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2585 dev_p->num_funcs); 2586 2587 hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id); 2588 } 2589 2590 /** 2591 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2592 * @hw: pointer to the HW struct 2593 * @dev_p: pointer to device capabilities structure 2594 * @cap: capability element to parse 2595 * 2596 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2597 */ 2598 static void 2599 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2600 struct ice_aqc_list_caps_elem *cap) 2601 { 2602 u32 number = LE32_TO_CPU(cap->number); 2603 2604 dev_p->num_vsi_allocd_to_host = number; 2605 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2606 dev_p->num_vsi_allocd_to_host); 2607 } 2608 2609 /** 2610 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2611 * @hw: pointer to the HW struct 2612 * @dev_p: pointer to device capabilities structure 2613 * @cap: capability element to parse 2614 * 2615 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2616 */ 2617 static void 2618 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2619 struct ice_aqc_list_caps_elem *cap) 2620 { 2621 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2622 u32 logical_id = LE32_TO_CPU(cap->logical_id); 2623 u32 phys_id = LE32_TO_CPU(cap->phys_id); 2624 u32 number = LE32_TO_CPU(cap->number); 2625 2626 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2627 dev_p->common_cap.ieee_1588 = info->ena; 2628 2629 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2630 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2631 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2632 2633 info->tmr1_owner = (number & ICE_TS_TMR1_OWNR_M) >> ICE_TS_TMR1_OWNR_S; 2634 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2635 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2636 2637 info->ena_ports = logical_id; 2638 info->tmr_own_map = phys_id; 2639 2640 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2641 dev_p->common_cap.ieee_1588); 2642 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2643 info->tmr0_owner); 2644 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2645 info->tmr0_owned); 2646 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2647 info->tmr0_ena); 2648 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2649 info->tmr1_owner); 2650 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2651 info->tmr1_owned); 2652 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2653 info->tmr1_ena); 2654 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2655 info->ena_ports); 2656 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2657 info->tmr_own_map); 2658 } 2659 2660 /** 2661 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2662 * @hw: pointer to the HW struct 2663 * @dev_p: pointer to device capabilities structure 2664 * @cap: capability element to parse 2665 * 2666 * Parse ICE_AQC_CAPS_FD for device capabilities. 2667 */ 2668 static void 2669 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2670 struct ice_aqc_list_caps_elem *cap) 2671 { 2672 u32 number = LE32_TO_CPU(cap->number); 2673 2674 dev_p->num_flow_director_fltr = number; 2675 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2676 dev_p->num_flow_director_fltr); 2677 } 2678 2679 /** 2680 * ice_parse_dev_caps - Parse device capabilities 2681 * @hw: pointer to the HW struct 2682 * @dev_p: pointer to device capabilities structure 2683 * @buf: buffer containing the device capability records 2684 * @cap_count: the number of capabilities 2685 * 2686 * Helper device to parse device (0x000B) capabilities list. For 2687 * capabilities shared between device and function, this relies on 2688 * ice_parse_common_caps. 2689 * 2690 * Loop through the list of provided capabilities and extract the relevant 2691 * data into the device capabilities structured. 2692 */ 2693 static void 2694 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2695 void *buf, u32 cap_count) 2696 { 2697 struct ice_aqc_list_caps_elem *cap_resp; 2698 u32 i; 2699 2700 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 2701 2702 ice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM); 2703 2704 for (i = 0; i < cap_count; i++) { 2705 u16 cap = LE16_TO_CPU(cap_resp[i].cap); 2706 bool found; 2707 2708 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2709 &cap_resp[i], "dev caps"); 2710 2711 switch (cap) { 2712 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2713 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2714 break; 2715 case ICE_AQC_CAPS_VSI: 2716 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2717 break; 2718 case ICE_AQC_CAPS_1588: 2719 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2720 break; 2721 case ICE_AQC_CAPS_FD: 2722 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2723 break; 2724 default: 2725 /* Don't list common capabilities as unknown */ 2726 if (!found) 2727 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2728 i, cap); 2729 break; 2730 } 2731 } 2732 2733 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2734 } 2735 2736 /** 2737 * ice_aq_list_caps - query function/device capabilities 2738 * @hw: pointer to the HW struct 2739 * @buf: a buffer to hold the capabilities 2740 * @buf_size: size of the buffer 2741 * @cap_count: if not NULL, set to the number of capabilities reported 2742 * @opc: capabilities type to discover, device or function 2743 * @cd: pointer to command details structure or NULL 2744 * 2745 * Get the function (0x000A) or device (0x000B) capabilities description from 2746 * firmware and store it in the buffer. 2747 * 2748 * If the cap_count pointer is not NULL, then it is set to the number of 2749 * capabilities firmware will report. Note that if the buffer size is too 2750 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2751 * cap_count will still be updated in this case. It is recommended that the 2752 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2753 * firmware could return) to avoid this. 2754 */ 2755 static enum ice_status 2756 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2757 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2758 { 2759 struct ice_aqc_list_caps *cmd; 2760 struct ice_aq_desc desc; 2761 enum ice_status status; 2762 2763 cmd = &desc.params.get_cap; 2764 2765 if (opc != ice_aqc_opc_list_func_caps && 2766 opc != ice_aqc_opc_list_dev_caps) 2767 return ICE_ERR_PARAM; 2768 2769 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2770 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2771 2772 if (cap_count) 2773 *cap_count = LE32_TO_CPU(cmd->count); 2774 2775 return status; 2776 } 2777 2778 /** 2779 * ice_discover_dev_caps - Read and extract device capabilities 2780 * @hw: pointer to the hardware structure 2781 * @dev_caps: pointer to device capabilities structure 2782 * 2783 * Read the device capabilities and extract them into the dev_caps structure 2784 * for later use. 2785 */ 2786 static enum ice_status 2787 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2788 { 2789 enum ice_status status; 2790 u32 cap_count = 0; 2791 void *cbuf; 2792 2793 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN); 2794 if (!cbuf) 2795 return ICE_ERR_NO_MEMORY; 2796 2797 /* Although the driver doesn't know the number of capabilities the 2798 * device will return, we can simply send a 4KB buffer, the maximum 2799 * possible size that firmware can return. 2800 */ 2801 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2802 2803 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2804 ice_aqc_opc_list_dev_caps, NULL); 2805 if (!status) 2806 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2807 ice_free(hw, cbuf); 2808 2809 return status; 2810 } 2811 2812 /** 2813 * ice_discover_func_caps - Read and extract function capabilities 2814 * @hw: pointer to the hardware structure 2815 * @func_caps: pointer to function capabilities structure 2816 * 2817 * Read the function capabilities and extract them into the func_caps structure 2818 * for later use. 2819 */ 2820 static enum ice_status 2821 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2822 { 2823 enum ice_status status; 2824 u32 cap_count = 0; 2825 void *cbuf; 2826 2827 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN); 2828 if (!cbuf) 2829 return ICE_ERR_NO_MEMORY; 2830 2831 /* Although the driver doesn't know the number of capabilities the 2832 * device will return, we can simply send a 4KB buffer, the maximum 2833 * possible size that firmware can return. 2834 */ 2835 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2836 2837 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2838 ice_aqc_opc_list_func_caps, NULL); 2839 if (!status) 2840 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2841 ice_free(hw, cbuf); 2842 2843 return status; 2844 } 2845 2846 /** 2847 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2848 * @hw: pointer to the hardware structure 2849 */ 2850 void ice_set_safe_mode_caps(struct ice_hw *hw) 2851 { 2852 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2853 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2854 struct ice_hw_common_caps cached_caps; 2855 u32 num_funcs; 2856 2857 /* cache some func_caps values that should be restored after memset */ 2858 cached_caps = func_caps->common_cap; 2859 2860 /* unset func capabilities */ 2861 memset(func_caps, 0, sizeof(*func_caps)); 2862 2863 #define ICE_RESTORE_FUNC_CAP(name) \ 2864 func_caps->common_cap.name = cached_caps.name 2865 2866 /* restore cached values */ 2867 ICE_RESTORE_FUNC_CAP(valid_functions); 2868 ICE_RESTORE_FUNC_CAP(txq_first_id); 2869 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2870 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2871 ICE_RESTORE_FUNC_CAP(max_mtu); 2872 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2873 2874 /* one Tx and one Rx queue in safe mode */ 2875 func_caps->common_cap.num_rxq = 1; 2876 func_caps->common_cap.num_txq = 1; 2877 2878 /* two MSIX vectors, one for traffic and one for misc causes */ 2879 func_caps->common_cap.num_msix_vectors = 2; 2880 func_caps->guar_num_vsi = 1; 2881 2882 /* cache some dev_caps values that should be restored after memset */ 2883 cached_caps = dev_caps->common_cap; 2884 num_funcs = dev_caps->num_funcs; 2885 2886 /* unset dev capabilities */ 2887 memset(dev_caps, 0, sizeof(*dev_caps)); 2888 2889 #define ICE_RESTORE_DEV_CAP(name) \ 2890 dev_caps->common_cap.name = cached_caps.name 2891 2892 /* restore cached values */ 2893 ICE_RESTORE_DEV_CAP(valid_functions); 2894 ICE_RESTORE_DEV_CAP(txq_first_id); 2895 ICE_RESTORE_DEV_CAP(rxq_first_id); 2896 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2897 ICE_RESTORE_DEV_CAP(max_mtu); 2898 ICE_RESTORE_DEV_CAP(nvm_unified_update); 2899 dev_caps->num_funcs = num_funcs; 2900 2901 /* one Tx and one Rx queue per function in safe mode */ 2902 dev_caps->common_cap.num_rxq = num_funcs; 2903 dev_caps->common_cap.num_txq = num_funcs; 2904 2905 /* two MSIX vectors per function */ 2906 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2907 } 2908 2909 /** 2910 * ice_get_caps - get info about the HW 2911 * @hw: pointer to the hardware structure 2912 */ 2913 enum ice_status ice_get_caps(struct ice_hw *hw) 2914 { 2915 enum ice_status status; 2916 2917 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2918 if (status) 2919 return status; 2920 2921 return ice_discover_func_caps(hw, &hw->func_caps); 2922 } 2923 2924 /** 2925 * ice_aq_manage_mac_write - manage MAC address write command 2926 * @hw: pointer to the HW struct 2927 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2928 * @flags: flags to control write behavior 2929 * @cd: pointer to command details structure or NULL 2930 * 2931 * This function is used to write MAC address to the NVM (0x0108). 2932 */ 2933 enum ice_status 2934 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2935 struct ice_sq_cd *cd) 2936 { 2937 struct ice_aqc_manage_mac_write *cmd; 2938 struct ice_aq_desc desc; 2939 2940 cmd = &desc.params.mac_write; 2941 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2942 2943 cmd->flags = flags; 2944 ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 2945 2946 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2947 } 2948 2949 /** 2950 * ice_aq_clear_pxe_mode 2951 * @hw: pointer to the HW struct 2952 * 2953 * Tell the firmware that the driver is taking over from PXE (0x0110). 2954 */ 2955 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 2956 { 2957 struct ice_aq_desc desc; 2958 2959 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2960 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2961 2962 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2963 } 2964 2965 /** 2966 * ice_clear_pxe_mode - clear pxe operations mode 2967 * @hw: pointer to the HW struct 2968 * 2969 * Make sure all PXE mode settings are cleared, including things 2970 * like descriptor fetch/write-back mode. 2971 */ 2972 void ice_clear_pxe_mode(struct ice_hw *hw) 2973 { 2974 if (ice_check_sq_alive(hw, &hw->adminq)) 2975 ice_aq_clear_pxe_mode(hw); 2976 } 2977 2978 /** 2979 * ice_aq_set_port_params - set physical port parameters. 2980 * @pi: pointer to the port info struct 2981 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 2982 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 2983 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 2984 * @double_vlan: if set double VLAN is enabled 2985 * @cd: pointer to command details structure or NULL 2986 * 2987 * Set Physical port parameters (0x0203) 2988 */ 2989 enum ice_status 2990 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi, 2991 bool save_bad_pac, bool pad_short_pac, bool double_vlan, 2992 struct ice_sq_cd *cd) 2993 2994 { 2995 struct ice_aqc_set_port_params *cmd; 2996 struct ice_hw *hw = pi->hw; 2997 struct ice_aq_desc desc; 2998 u16 cmd_flags = 0; 2999 3000 cmd = &desc.params.set_port_params; 3001 3002 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 3003 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 3004 if (save_bad_pac) 3005 cmd_flags |= ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS; 3006 if (pad_short_pac) 3007 cmd_flags |= ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS; 3008 if (double_vlan) 3009 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3010 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3011 3012 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3013 } 3014 3015 /** 3016 * ice_is_100m_speed_supported 3017 * @hw: pointer to the HW struct 3018 * 3019 * returns true if 100M speeds are supported by the device, 3020 * false otherwise. 3021 */ 3022 bool ice_is_100m_speed_supported(struct ice_hw *hw) 3023 { 3024 switch (hw->device_id) { 3025 case ICE_DEV_ID_E822C_10G_BASE_T: 3026 case ICE_DEV_ID_E822C_SGMII: 3027 case ICE_DEV_ID_E822L_10G_BASE_T: 3028 case ICE_DEV_ID_E822L_SGMII: 3029 case ICE_DEV_ID_E823L_10G_BASE_T: 3030 case ICE_DEV_ID_E823L_1GBE: 3031 return true; 3032 default: 3033 return false; 3034 } 3035 } 3036 3037 /** 3038 * ice_get_link_speed_based_on_phy_type - returns link speed 3039 * @phy_type_low: lower part of phy_type 3040 * @phy_type_high: higher part of phy_type 3041 * 3042 * This helper function will convert an entry in PHY type structure 3043 * [phy_type_low, phy_type_high] to its corresponding link speed. 3044 * Note: In the structure of [phy_type_low, phy_type_high], there should 3045 * be one bit set, as this function will convert one PHY type to its 3046 * speed. 3047 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 3048 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 3049 */ 3050 static u16 3051 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 3052 { 3053 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3054 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3055 3056 switch (phy_type_low) { 3057 case ICE_PHY_TYPE_LOW_100BASE_TX: 3058 case ICE_PHY_TYPE_LOW_100M_SGMII: 3059 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 3060 break; 3061 case ICE_PHY_TYPE_LOW_1000BASE_T: 3062 case ICE_PHY_TYPE_LOW_1000BASE_SX: 3063 case ICE_PHY_TYPE_LOW_1000BASE_LX: 3064 case ICE_PHY_TYPE_LOW_1000BASE_KX: 3065 case ICE_PHY_TYPE_LOW_1G_SGMII: 3066 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 3067 break; 3068 case ICE_PHY_TYPE_LOW_2500BASE_T: 3069 case ICE_PHY_TYPE_LOW_2500BASE_X: 3070 case ICE_PHY_TYPE_LOW_2500BASE_KX: 3071 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 3072 break; 3073 case ICE_PHY_TYPE_LOW_5GBASE_T: 3074 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3075 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3076 break; 3077 case ICE_PHY_TYPE_LOW_10GBASE_T: 3078 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3079 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3080 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3081 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3082 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3083 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3084 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3085 break; 3086 case ICE_PHY_TYPE_LOW_25GBASE_T: 3087 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3088 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3089 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3090 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3091 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3092 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3093 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3094 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3095 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3096 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3097 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3098 break; 3099 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3100 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3101 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3102 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3103 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3104 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3105 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3106 break; 3107 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3108 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3109 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3110 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3111 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3112 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3113 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3114 case ICE_PHY_TYPE_LOW_50G_AUI2: 3115 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3116 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3117 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3118 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3119 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3120 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3121 case ICE_PHY_TYPE_LOW_50G_AUI1: 3122 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3123 break; 3124 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3125 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3126 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3127 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3128 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3129 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3130 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3131 case ICE_PHY_TYPE_LOW_100G_AUI4: 3132 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3133 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3134 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3135 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3136 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3137 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3138 break; 3139 default: 3140 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3141 break; 3142 } 3143 3144 switch (phy_type_high) { 3145 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3146 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3147 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3148 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3149 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3150 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3151 break; 3152 default: 3153 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3154 break; 3155 } 3156 3157 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3158 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3159 return ICE_AQ_LINK_SPEED_UNKNOWN; 3160 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3161 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3162 return ICE_AQ_LINK_SPEED_UNKNOWN; 3163 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3164 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3165 return speed_phy_type_low; 3166 else 3167 return speed_phy_type_high; 3168 } 3169 3170 /** 3171 * ice_update_phy_type 3172 * @phy_type_low: pointer to the lower part of phy_type 3173 * @phy_type_high: pointer to the higher part of phy_type 3174 * @link_speeds_bitmap: targeted link speeds bitmap 3175 * 3176 * Note: For the link_speeds_bitmap structure, you can check it at 3177 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3178 * link_speeds_bitmap include multiple speeds. 3179 * 3180 * Each entry in this [phy_type_low, phy_type_high] structure will 3181 * present a certain link speed. This helper function will turn on bits 3182 * in [phy_type_low, phy_type_high] structure based on the value of 3183 * link_speeds_bitmap input parameter. 3184 */ 3185 void 3186 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3187 u16 link_speeds_bitmap) 3188 { 3189 u64 pt_high; 3190 u64 pt_low; 3191 int index; 3192 u16 speed; 3193 3194 /* We first check with low part of phy_type */ 3195 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3196 pt_low = BIT_ULL(index); 3197 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3198 3199 if (link_speeds_bitmap & speed) 3200 *phy_type_low |= BIT_ULL(index); 3201 } 3202 3203 /* We then check with high part of phy_type */ 3204 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3205 pt_high = BIT_ULL(index); 3206 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3207 3208 if (link_speeds_bitmap & speed) 3209 *phy_type_high |= BIT_ULL(index); 3210 } 3211 } 3212 3213 /** 3214 * ice_aq_set_phy_cfg 3215 * @hw: pointer to the HW struct 3216 * @pi: port info structure of the interested logical port 3217 * @cfg: structure with PHY configuration data to be set 3218 * @cd: pointer to command details structure or NULL 3219 * 3220 * Set the various PHY configuration parameters supported on the Port. 3221 * One or more of the Set PHY config parameters may be ignored in an MFP 3222 * mode as the PF may not have the privilege to set some of the PHY Config 3223 * parameters. This status will be indicated by the command response (0x0601). 3224 */ 3225 enum ice_status 3226 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3227 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3228 { 3229 struct ice_aq_desc desc; 3230 enum ice_status status; 3231 3232 if (!cfg) 3233 return ICE_ERR_PARAM; 3234 3235 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3236 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3237 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3238 cfg->caps); 3239 3240 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3241 } 3242 3243 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3244 desc.params.set_phy.lport_num = pi->lport; 3245 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3246 3247 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3248 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3249 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low)); 3250 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3251 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high)); 3252 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3253 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3254 cfg->low_power_ctrl_an); 3255 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3256 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3257 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3258 cfg->link_fec_opt); 3259 3260 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3261 3262 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 3263 status = ICE_SUCCESS; 3264 3265 if (!status) 3266 pi->phy.curr_user_phy_cfg = *cfg; 3267 3268 return status; 3269 } 3270 3271 /** 3272 * ice_update_link_info - update status of the HW network link 3273 * @pi: port info structure of the interested logical port 3274 */ 3275 enum ice_status ice_update_link_info(struct ice_port_info *pi) 3276 { 3277 struct ice_link_status *li; 3278 enum ice_status status; 3279 3280 if (!pi) 3281 return ICE_ERR_PARAM; 3282 3283 li = &pi->phy.link_info; 3284 3285 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3286 if (status) 3287 return status; 3288 3289 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3290 struct ice_aqc_get_phy_caps_data *pcaps; 3291 struct ice_hw *hw; 3292 3293 hw = pi->hw; 3294 pcaps = (struct ice_aqc_get_phy_caps_data *) 3295 ice_malloc(hw, sizeof(*pcaps)); 3296 if (!pcaps) 3297 return ICE_ERR_NO_MEMORY; 3298 3299 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3300 pcaps, NULL); 3301 3302 if (status == ICE_SUCCESS) 3303 ice_memcpy(li->module_type, &pcaps->module_type, 3304 sizeof(li->module_type), 3305 ICE_NONDMA_TO_NONDMA); 3306 3307 ice_free(hw, pcaps); 3308 } 3309 3310 return status; 3311 } 3312 3313 /** 3314 * ice_cache_phy_user_req 3315 * @pi: port information structure 3316 * @cache_data: PHY logging data 3317 * @cache_mode: PHY logging mode 3318 * 3319 * Log the user request on (FC, FEC, SPEED) for later user. 3320 */ 3321 static void 3322 ice_cache_phy_user_req(struct ice_port_info *pi, 3323 struct ice_phy_cache_mode_data cache_data, 3324 enum ice_phy_cache_mode cache_mode) 3325 { 3326 if (!pi) 3327 return; 3328 3329 switch (cache_mode) { 3330 case ICE_FC_MODE: 3331 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3332 break; 3333 case ICE_SPEED_MODE: 3334 pi->phy.curr_user_speed_req = 3335 cache_data.data.curr_user_speed_req; 3336 break; 3337 case ICE_FEC_MODE: 3338 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3339 break; 3340 default: 3341 break; 3342 } 3343 } 3344 3345 /** 3346 * ice_caps_to_fc_mode 3347 * @caps: PHY capabilities 3348 * 3349 * Convert PHY FC capabilities to ice FC mode 3350 */ 3351 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3352 { 3353 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3354 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3355 return ICE_FC_FULL; 3356 3357 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3358 return ICE_FC_TX_PAUSE; 3359 3360 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3361 return ICE_FC_RX_PAUSE; 3362 3363 return ICE_FC_NONE; 3364 } 3365 3366 /** 3367 * ice_caps_to_fec_mode 3368 * @caps: PHY capabilities 3369 * @fec_options: Link FEC options 3370 * 3371 * Convert PHY FEC capabilities to ice FEC mode 3372 */ 3373 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3374 { 3375 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3376 return ICE_FEC_AUTO; 3377 3378 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3379 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3380 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3381 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3382 return ICE_FEC_BASER; 3383 3384 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3385 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3386 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3387 return ICE_FEC_RS; 3388 3389 return ICE_FEC_NONE; 3390 } 3391 3392 /** 3393 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3394 * @pi: port information structure 3395 * @cfg: PHY configuration data to set FC mode 3396 * @req_mode: FC mode to configure 3397 */ 3398 static enum ice_status 3399 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3400 enum ice_fc_mode req_mode) 3401 { 3402 struct ice_phy_cache_mode_data cache_data; 3403 u8 pause_mask = 0x0; 3404 3405 if (!pi || !cfg) 3406 return ICE_ERR_BAD_PTR; 3407 3408 switch (req_mode) { 3409 case ICE_FC_AUTO: 3410 { 3411 struct ice_aqc_get_phy_caps_data *pcaps; 3412 enum ice_status status; 3413 3414 pcaps = (struct ice_aqc_get_phy_caps_data *) 3415 ice_malloc(pi->hw, sizeof(*pcaps)); 3416 if (!pcaps) 3417 return ICE_ERR_NO_MEMORY; 3418 3419 /* Query the value of FC that both the NIC and attached media 3420 * can do. 3421 */ 3422 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3423 pcaps, NULL); 3424 if (status) { 3425 ice_free(pi->hw, pcaps); 3426 return status; 3427 } 3428 3429 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3430 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3431 3432 ice_free(pi->hw, pcaps); 3433 break; 3434 } 3435 case ICE_FC_FULL: 3436 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3437 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3438 break; 3439 case ICE_FC_RX_PAUSE: 3440 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3441 break; 3442 case ICE_FC_TX_PAUSE: 3443 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3444 break; 3445 default: 3446 break; 3447 } 3448 3449 /* clear the old pause settings */ 3450 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3451 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3452 3453 /* set the new capabilities */ 3454 cfg->caps |= pause_mask; 3455 3456 /* Cache user FC request */ 3457 cache_data.data.curr_user_fc_req = req_mode; 3458 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3459 3460 return ICE_SUCCESS; 3461 } 3462 3463 /** 3464 * ice_set_fc 3465 * @pi: port information structure 3466 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3467 * @ena_auto_link_update: enable automatic link update 3468 * 3469 * Set the requested flow control mode. 3470 */ 3471 enum ice_status 3472 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3473 { 3474 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3475 struct ice_aqc_get_phy_caps_data *pcaps; 3476 enum ice_status status; 3477 struct ice_hw *hw; 3478 3479 if (!pi || !aq_failures) 3480 return ICE_ERR_BAD_PTR; 3481 3482 *aq_failures = 0; 3483 hw = pi->hw; 3484 3485 pcaps = (struct ice_aqc_get_phy_caps_data *) 3486 ice_malloc(hw, sizeof(*pcaps)); 3487 if (!pcaps) 3488 return ICE_ERR_NO_MEMORY; 3489 3490 /* Get the current PHY config */ 3491 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3492 pcaps, NULL); 3493 3494 if (status) { 3495 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3496 goto out; 3497 } 3498 3499 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3500 3501 /* Configure the set PHY data */ 3502 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3503 if (status) { 3504 if (status != ICE_ERR_BAD_PTR) 3505 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3506 3507 goto out; 3508 } 3509 3510 /* If the capabilities have changed, then set the new config */ 3511 if (cfg.caps != pcaps->caps) { 3512 int retry_count, retry_max = 10; 3513 3514 /* Auto restart link so settings take effect */ 3515 if (ena_auto_link_update) 3516 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3517 3518 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3519 if (status) { 3520 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3521 goto out; 3522 } 3523 3524 /* Update the link info 3525 * It sometimes takes a really long time for link to 3526 * come back from the atomic reset. Thus, we wait a 3527 * little bit. 3528 */ 3529 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3530 status = ice_update_link_info(pi); 3531 3532 if (status == ICE_SUCCESS) 3533 break; 3534 3535 ice_msec_delay(100, true); 3536 } 3537 3538 if (status) 3539 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3540 } 3541 3542 out: 3543 ice_free(hw, pcaps); 3544 return status; 3545 } 3546 3547 /** 3548 * ice_phy_caps_equals_cfg 3549 * @phy_caps: PHY capabilities 3550 * @phy_cfg: PHY configuration 3551 * 3552 * Helper function to determine if PHY capabilities matches PHY 3553 * configuration 3554 */ 3555 bool 3556 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3557 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3558 { 3559 u8 caps_mask, cfg_mask; 3560 3561 if (!phy_caps || !phy_cfg) 3562 return false; 3563 3564 /* These bits are not common between capabilities and configuration. 3565 * Do not use them to determine equality. 3566 */ 3567 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3568 ICE_AQC_PHY_EN_MOD_QUAL); 3569 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3570 3571 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3572 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3573 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3574 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3575 phy_caps->eee_cap != phy_cfg->eee_cap || 3576 phy_caps->eeer_value != phy_cfg->eeer_value || 3577 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3578 return false; 3579 3580 return true; 3581 } 3582 3583 /** 3584 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3585 * @pi: port information structure 3586 * @caps: PHY ability structure to copy data from 3587 * @cfg: PHY configuration structure to copy data to 3588 * 3589 * Helper function to copy AQC PHY get ability data to PHY set configuration 3590 * data structure 3591 */ 3592 void 3593 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3594 struct ice_aqc_get_phy_caps_data *caps, 3595 struct ice_aqc_set_phy_cfg_data *cfg) 3596 { 3597 if (!pi || !caps || !cfg) 3598 return; 3599 3600 ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM); 3601 cfg->phy_type_low = caps->phy_type_low; 3602 cfg->phy_type_high = caps->phy_type_high; 3603 cfg->caps = caps->caps; 3604 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3605 cfg->eee_cap = caps->eee_cap; 3606 cfg->eeer_value = caps->eeer_value; 3607 cfg->link_fec_opt = caps->link_fec_options; 3608 cfg->module_compliance_enforcement = 3609 caps->module_compliance_enforcement; 3610 } 3611 3612 /** 3613 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3614 * @pi: port information structure 3615 * @cfg: PHY configuration data to set FEC mode 3616 * @fec: FEC mode to configure 3617 */ 3618 enum ice_status 3619 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3620 enum ice_fec_mode fec) 3621 { 3622 struct ice_aqc_get_phy_caps_data *pcaps; 3623 enum ice_status status = ICE_SUCCESS; 3624 struct ice_hw *hw; 3625 3626 if (!pi || !cfg) 3627 return ICE_ERR_BAD_PTR; 3628 3629 hw = pi->hw; 3630 3631 pcaps = (struct ice_aqc_get_phy_caps_data *) 3632 ice_malloc(hw, sizeof(*pcaps)); 3633 if (!pcaps) 3634 return ICE_ERR_NO_MEMORY; 3635 3636 status = ice_aq_get_phy_caps(pi, false, 3637 (ice_fw_supports_report_dflt_cfg(hw) ? 3638 ICE_AQC_REPORT_DFLT_CFG : 3639 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3640 3641 if (status) 3642 goto out; 3643 3644 cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC); 3645 cfg->link_fec_opt = pcaps->link_fec_options; 3646 3647 switch (fec) { 3648 case ICE_FEC_BASER: 3649 /* Clear RS bits, and AND BASE-R ability 3650 * bits and OR request bits. 3651 */ 3652 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3653 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3654 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3655 ICE_AQC_PHY_FEC_25G_KR_REQ; 3656 break; 3657 case ICE_FEC_RS: 3658 /* Clear BASE-R bits, and AND RS ability 3659 * bits and OR request bits. 3660 */ 3661 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3662 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3663 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3664 break; 3665 case ICE_FEC_NONE: 3666 /* Clear all FEC option bits. */ 3667 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3668 break; 3669 case ICE_FEC_AUTO: 3670 /* AND auto FEC bit, and all caps bits. */ 3671 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 3672 cfg->link_fec_opt |= pcaps->link_fec_options; 3673 break; 3674 default: 3675 status = ICE_ERR_PARAM; 3676 break; 3677 } 3678 3679 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw) && 3680 !ice_fw_supports_report_dflt_cfg(pi->hw)) { 3681 struct ice_link_default_override_tlv tlv; 3682 3683 if (ice_get_link_default_override(&tlv, pi)) 3684 goto out; 3685 3686 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3687 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3688 cfg->link_fec_opt = tlv.fec_options; 3689 } 3690 3691 out: 3692 ice_free(hw, pcaps); 3693 3694 return status; 3695 } 3696 3697 /** 3698 * ice_get_link_status - get status of the HW network link 3699 * @pi: port information structure 3700 * @link_up: pointer to bool (true/false = linkup/linkdown) 3701 * 3702 * Variable link_up is true if link is up, false if link is down. 3703 * The variable link_up is invalid if status is non zero. As a 3704 * result of this call, link status reporting becomes enabled 3705 */ 3706 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3707 { 3708 struct ice_phy_info *phy_info; 3709 enum ice_status status = ICE_SUCCESS; 3710 3711 if (!pi || !link_up) 3712 return ICE_ERR_PARAM; 3713 3714 phy_info = &pi->phy; 3715 3716 if (phy_info->get_link_info) { 3717 status = ice_update_link_info(pi); 3718 3719 if (status) 3720 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3721 status); 3722 } 3723 3724 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3725 3726 return status; 3727 } 3728 3729 /** 3730 * ice_aq_set_link_restart_an 3731 * @pi: pointer to the port information structure 3732 * @ena_link: if true: enable link, if false: disable link 3733 * @cd: pointer to command details structure or NULL 3734 * 3735 * Sets up the link and restarts the Auto-Negotiation over the link. 3736 */ 3737 enum ice_status 3738 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3739 struct ice_sq_cd *cd) 3740 { 3741 struct ice_aqc_restart_an *cmd; 3742 struct ice_aq_desc desc; 3743 3744 cmd = &desc.params.restart_an; 3745 3746 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3747 3748 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3749 cmd->lport_num = pi->lport; 3750 if (ena_link) 3751 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3752 else 3753 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3754 3755 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3756 } 3757 3758 /** 3759 * ice_aq_set_event_mask 3760 * @hw: pointer to the HW struct 3761 * @port_num: port number of the physical function 3762 * @mask: event mask to be set 3763 * @cd: pointer to command details structure or NULL 3764 * 3765 * Set event mask (0x0613) 3766 */ 3767 enum ice_status 3768 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3769 struct ice_sq_cd *cd) 3770 { 3771 struct ice_aqc_set_event_mask *cmd; 3772 struct ice_aq_desc desc; 3773 3774 cmd = &desc.params.set_event_mask; 3775 3776 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3777 3778 cmd->lport_num = port_num; 3779 3780 cmd->event_mask = CPU_TO_LE16(mask); 3781 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3782 } 3783 3784 /** 3785 * ice_aq_set_mac_loopback 3786 * @hw: pointer to the HW struct 3787 * @ena_lpbk: Enable or Disable loopback 3788 * @cd: pointer to command details structure or NULL 3789 * 3790 * Enable/disable loopback on a given port 3791 */ 3792 enum ice_status 3793 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3794 { 3795 struct ice_aqc_set_mac_lb *cmd; 3796 struct ice_aq_desc desc; 3797 3798 cmd = &desc.params.set_mac_lb; 3799 3800 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3801 if (ena_lpbk) 3802 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3803 3804 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3805 } 3806 3807 /** 3808 * ice_aq_set_port_id_led 3809 * @pi: pointer to the port information 3810 * @is_orig_mode: is this LED set to original mode (by the net-list) 3811 * @cd: pointer to command details structure or NULL 3812 * 3813 * Set LED value for the given port (0x06e9) 3814 */ 3815 enum ice_status 3816 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3817 struct ice_sq_cd *cd) 3818 { 3819 struct ice_aqc_set_port_id_led *cmd; 3820 struct ice_hw *hw = pi->hw; 3821 struct ice_aq_desc desc; 3822 3823 cmd = &desc.params.set_port_id_led; 3824 3825 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3826 3827 if (is_orig_mode) 3828 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3829 else 3830 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3831 3832 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3833 } 3834 3835 /** 3836 * ice_aq_sff_eeprom 3837 * @hw: pointer to the HW struct 3838 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3839 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3840 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3841 * @page: QSFP page 3842 * @set_page: set or ignore the page 3843 * @data: pointer to data buffer to be read/written to the I2C device. 3844 * @length: 1-16 for read, 1 for write. 3845 * @write: 0 read, 1 for write. 3846 * @cd: pointer to command details structure or NULL 3847 * 3848 * Read/Write SFF EEPROM (0x06EE) 3849 */ 3850 enum ice_status 3851 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3852 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3853 bool write, struct ice_sq_cd *cd) 3854 { 3855 struct ice_aqc_sff_eeprom *cmd; 3856 struct ice_aq_desc desc; 3857 enum ice_status status; 3858 3859 if (!data || (mem_addr & 0xff00)) 3860 return ICE_ERR_PARAM; 3861 3862 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3863 cmd = &desc.params.read_write_sff_param; 3864 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD); 3865 cmd->lport_num = (u8)(lport & 0xff); 3866 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3867 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) & 3868 ICE_AQC_SFF_I2CBUS_7BIT_M) | 3869 ((set_page << 3870 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3871 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3872 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff); 3873 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3874 if (write) 3875 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE); 3876 3877 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3878 return status; 3879 } 3880 3881 /** 3882 * ice_aq_prog_topo_dev_nvm 3883 * @hw: pointer to the hardware structure 3884 * @topo_params: pointer to structure storing topology parameters for a device 3885 * @cd: pointer to command details structure or NULL 3886 * 3887 * Program Topology Device NVM (0x06F2) 3888 * 3889 */ 3890 enum ice_status 3891 ice_aq_prog_topo_dev_nvm(struct ice_hw *hw, 3892 struct ice_aqc_link_topo_params *topo_params, 3893 struct ice_sq_cd *cd) 3894 { 3895 struct ice_aqc_prog_topo_dev_nvm *cmd; 3896 struct ice_aq_desc desc; 3897 3898 cmd = &desc.params.prog_topo_dev_nvm; 3899 3900 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_prog_topo_dev_nvm); 3901 3902 ice_memcpy(&cmd->topo_params, topo_params, sizeof(*topo_params), 3903 ICE_NONDMA_TO_NONDMA); 3904 3905 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3906 } 3907 3908 /** 3909 * ice_aq_read_topo_dev_nvm 3910 * @hw: pointer to the hardware structure 3911 * @topo_params: pointer to structure storing topology parameters for a device 3912 * @start_address: byte offset in the topology device NVM 3913 * @data: pointer to data buffer 3914 * @data_size: number of bytes to be read from the topology device NVM 3915 * @cd: pointer to command details structure or NULL 3916 * Read Topology Device NVM (0x06F3) 3917 * 3918 */ 3919 enum ice_status 3920 ice_aq_read_topo_dev_nvm(struct ice_hw *hw, 3921 struct ice_aqc_link_topo_params *topo_params, 3922 u32 start_address, u8 *data, u8 data_size, 3923 struct ice_sq_cd *cd) 3924 { 3925 struct ice_aqc_read_topo_dev_nvm *cmd; 3926 struct ice_aq_desc desc; 3927 enum ice_status status; 3928 3929 if (!data || data_size == 0 || 3930 data_size > ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE) 3931 return ICE_ERR_PARAM; 3932 3933 cmd = &desc.params.read_topo_dev_nvm; 3934 3935 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_topo_dev_nvm); 3936 3937 desc.datalen = data_size; 3938 ice_memcpy(&cmd->topo_params, topo_params, sizeof(*topo_params), 3939 ICE_NONDMA_TO_NONDMA); 3940 cmd->start_address = CPU_TO_LE32(start_address); 3941 3942 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3943 if (status) 3944 return status; 3945 3946 ice_memcpy(data, cmd->data_read, data_size, ICE_NONDMA_TO_NONDMA); 3947 3948 return ICE_SUCCESS; 3949 } 3950 3951 /** 3952 * __ice_aq_get_set_rss_lut 3953 * @hw: pointer to the hardware structure 3954 * @params: RSS LUT parameters 3955 * @set: set true to set the table, false to get the table 3956 * 3957 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3958 */ 3959 static enum ice_status 3960 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set) 3961 { 3962 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle; 3963 struct ice_aqc_get_set_rss_lut *cmd_resp; 3964 struct ice_aq_desc desc; 3965 enum ice_status status; 3966 u8 *lut; 3967 3968 if (!params) 3969 return ICE_ERR_PARAM; 3970 3971 vsi_handle = params->vsi_handle; 3972 lut = params->lut; 3973 3974 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3975 return ICE_ERR_PARAM; 3976 3977 lut_size = params->lut_size; 3978 lut_type = params->lut_type; 3979 glob_lut_idx = params->global_lut_id; 3980 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 3981 3982 cmd_resp = &desc.params.get_set_rss_lut; 3983 3984 if (set) { 3985 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 3986 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3987 } else { 3988 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 3989 } 3990 3991 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 3992 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 3993 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 3994 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 3995 3996 switch (lut_type) { 3997 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 3998 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 3999 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 4000 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 4001 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 4002 break; 4003 default: 4004 status = ICE_ERR_PARAM; 4005 goto ice_aq_get_set_rss_lut_exit; 4006 } 4007 4008 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 4009 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 4010 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 4011 4012 if (!set) 4013 goto ice_aq_get_set_rss_lut_send; 4014 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 4015 if (!set) 4016 goto ice_aq_get_set_rss_lut_send; 4017 } else { 4018 goto ice_aq_get_set_rss_lut_send; 4019 } 4020 4021 /* LUT size is only valid for Global and PF table types */ 4022 switch (lut_size) { 4023 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 4024 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG << 4025 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 4026 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 4027 break; 4028 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 4029 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 4030 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 4031 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 4032 break; 4033 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 4034 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 4035 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 4036 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 4037 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 4038 break; 4039 } 4040 /* fall-through */ 4041 default: 4042 status = ICE_ERR_PARAM; 4043 goto ice_aq_get_set_rss_lut_exit; 4044 } 4045 4046 ice_aq_get_set_rss_lut_send: 4047 cmd_resp->flags = CPU_TO_LE16(flags); 4048 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 4049 4050 ice_aq_get_set_rss_lut_exit: 4051 return status; 4052 } 4053 4054 /** 4055 * ice_aq_get_rss_lut 4056 * @hw: pointer to the hardware structure 4057 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 4058 * 4059 * get the RSS lookup table, PF or VSI type 4060 */ 4061 enum ice_status 4062 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 4063 { 4064 return __ice_aq_get_set_rss_lut(hw, get_params, false); 4065 } 4066 4067 /** 4068 * ice_aq_set_rss_lut 4069 * @hw: pointer to the hardware structure 4070 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4071 * 4072 * set the RSS lookup table, PF or VSI type 4073 */ 4074 enum ice_status 4075 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4076 { 4077 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4078 } 4079 4080 /** 4081 * __ice_aq_get_set_rss_key 4082 * @hw: pointer to the HW struct 4083 * @vsi_id: VSI FW index 4084 * @key: pointer to key info struct 4085 * @set: set true to set the key, false to get the key 4086 * 4087 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4088 */ 4089 static enum 4090 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4091 struct ice_aqc_get_set_rss_keys *key, 4092 bool set) 4093 { 4094 struct ice_aqc_get_set_rss_key *cmd_resp; 4095 u16 key_size = sizeof(*key); 4096 struct ice_aq_desc desc; 4097 4098 cmd_resp = &desc.params.get_set_rss_key; 4099 4100 if (set) { 4101 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4102 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 4103 } else { 4104 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4105 } 4106 4107 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 4108 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 4109 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 4110 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 4111 4112 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4113 } 4114 4115 /** 4116 * ice_aq_get_rss_key 4117 * @hw: pointer to the HW struct 4118 * @vsi_handle: software VSI handle 4119 * @key: pointer to key info struct 4120 * 4121 * get the RSS key per VSI 4122 */ 4123 enum ice_status 4124 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4125 struct ice_aqc_get_set_rss_keys *key) 4126 { 4127 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4128 return ICE_ERR_PARAM; 4129 4130 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4131 key, false); 4132 } 4133 4134 /** 4135 * ice_aq_set_rss_key 4136 * @hw: pointer to the HW struct 4137 * @vsi_handle: software VSI handle 4138 * @keys: pointer to key info struct 4139 * 4140 * set the RSS key per VSI 4141 */ 4142 enum ice_status 4143 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4144 struct ice_aqc_get_set_rss_keys *keys) 4145 { 4146 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4147 return ICE_ERR_PARAM; 4148 4149 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4150 keys, true); 4151 } 4152 4153 /** 4154 * ice_aq_add_lan_txq 4155 * @hw: pointer to the hardware structure 4156 * @num_qgrps: Number of added queue groups 4157 * @qg_list: list of queue groups to be added 4158 * @buf_size: size of buffer for indirect command 4159 * @cd: pointer to command details structure or NULL 4160 * 4161 * Add Tx LAN queue (0x0C30) 4162 * 4163 * NOTE: 4164 * Prior to calling add Tx LAN queue: 4165 * Initialize the following as part of the Tx queue context: 4166 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4167 * Cache profile and Packet shaper profile. 4168 * 4169 * After add Tx LAN queue AQ command is completed: 4170 * Interrupts should be associated with specific queues, 4171 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4172 * flow. 4173 */ 4174 enum ice_status 4175 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4176 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4177 struct ice_sq_cd *cd) 4178 { 4179 struct ice_aqc_add_tx_qgrp *list; 4180 struct ice_aqc_add_txqs *cmd; 4181 struct ice_aq_desc desc; 4182 u16 i, sum_size = 0; 4183 4184 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 4185 4186 cmd = &desc.params.add_txqs; 4187 4188 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4189 4190 if (!qg_list) 4191 return ICE_ERR_PARAM; 4192 4193 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4194 return ICE_ERR_PARAM; 4195 4196 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4197 sum_size += ice_struct_size(list, txqs, list->num_txqs); 4198 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4199 list->num_txqs); 4200 } 4201 4202 if (buf_size != sum_size) 4203 return ICE_ERR_PARAM; 4204 4205 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 4206 4207 cmd->num_qgrps = num_qgrps; 4208 4209 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4210 } 4211 4212 /** 4213 * ice_aq_dis_lan_txq 4214 * @hw: pointer to the hardware structure 4215 * @num_qgrps: number of groups in the list 4216 * @qg_list: the list of groups to disable 4217 * @buf_size: the total size of the qg_list buffer in bytes 4218 * @rst_src: if called due to reset, specifies the reset source 4219 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4220 * @cd: pointer to command details structure or NULL 4221 * 4222 * Disable LAN Tx queue (0x0C31) 4223 */ 4224 static enum ice_status 4225 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4226 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4227 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4228 struct ice_sq_cd *cd) 4229 { 4230 struct ice_aqc_dis_txq_item *item; 4231 struct ice_aqc_dis_txqs *cmd; 4232 struct ice_aq_desc desc; 4233 enum ice_status status; 4234 u16 i, sz = 0; 4235 4236 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 4237 cmd = &desc.params.dis_txqs; 4238 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4239 4240 /* qg_list can be NULL only in VM/VF reset flow */ 4241 if (!qg_list && !rst_src) 4242 return ICE_ERR_PARAM; 4243 4244 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4245 return ICE_ERR_PARAM; 4246 4247 cmd->num_entries = num_qgrps; 4248 4249 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 4250 ICE_AQC_Q_DIS_TIMEOUT_M); 4251 4252 switch (rst_src) { 4253 case ICE_VM_RESET: 4254 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4255 cmd->vmvf_and_timeout |= 4256 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 4257 break; 4258 case ICE_NO_RESET: 4259 default: 4260 break; 4261 } 4262 4263 /* flush pipe on time out */ 4264 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4265 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4266 if (!qg_list) 4267 goto do_aq; 4268 4269 /* set RD bit to indicate that command buffer is provided by the driver 4270 * and it needs to be read by the firmware 4271 */ 4272 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 4273 4274 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4275 u16 item_size = ice_struct_size(item, q_id, item->num_qs); 4276 4277 /* If the num of queues is even, add 2 bytes of padding */ 4278 if ((item->num_qs % 2) == 0) 4279 item_size += 2; 4280 4281 sz += item_size; 4282 4283 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4284 } 4285 4286 if (buf_size != sz) 4287 return ICE_ERR_PARAM; 4288 4289 do_aq: 4290 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4291 if (status) { 4292 if (!qg_list) 4293 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4294 vmvf_num, hw->adminq.sq_last_status); 4295 else 4296 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4297 LE16_TO_CPU(qg_list[0].q_id[0]), 4298 hw->adminq.sq_last_status); 4299 } 4300 return status; 4301 } 4302 4303 /** 4304 * ice_aq_move_recfg_lan_txq 4305 * @hw: pointer to the hardware structure 4306 * @num_qs: number of queues to move/reconfigure 4307 * @is_move: true if this operation involves node movement 4308 * @is_tc_change: true if this operation involves a TC change 4309 * @subseq_call: true if this operation is a subsequent call 4310 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN 4311 * @timeout: timeout in units of 100 usec (valid values 0-50) 4312 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN 4313 * @buf: struct containing src/dest TEID and per-queue info 4314 * @buf_size: size of buffer for indirect command 4315 * @txqs_moved: out param, number of queues successfully moved 4316 * @cd: pointer to command details structure or NULL 4317 * 4318 * Move / Reconfigure Tx LAN queues (0x0C32) 4319 */ 4320 enum ice_status 4321 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move, 4322 bool is_tc_change, bool subseq_call, bool flush_pipe, 4323 u8 timeout, u32 *blocked_cgds, 4324 struct ice_aqc_move_txqs_data *buf, u16 buf_size, 4325 u8 *txqs_moved, struct ice_sq_cd *cd) 4326 { 4327 struct ice_aqc_move_txqs *cmd; 4328 struct ice_aq_desc desc; 4329 enum ice_status status; 4330 4331 cmd = &desc.params.move_txqs; 4332 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs); 4333 4334 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50 4335 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX) 4336 return ICE_ERR_PARAM; 4337 4338 if (is_tc_change && !flush_pipe && !blocked_cgds) 4339 return ICE_ERR_PARAM; 4340 4341 if (!is_move && !is_tc_change) 4342 return ICE_ERR_PARAM; 4343 4344 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 4345 4346 if (is_move) 4347 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE; 4348 4349 if (is_tc_change) 4350 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE; 4351 4352 if (subseq_call) 4353 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL; 4354 4355 if (flush_pipe) 4356 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE; 4357 4358 cmd->num_qs = num_qs; 4359 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) & 4360 ICE_AQC_Q_CMD_TIMEOUT_M); 4361 4362 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4363 4364 if (!status && txqs_moved) 4365 *txqs_moved = cmd->num_qs; 4366 4367 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN && 4368 is_tc_change && !flush_pipe) 4369 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds); 4370 4371 return status; 4372 } 4373 4374 /* End of FW Admin Queue command wrappers */ 4375 4376 /** 4377 * ice_write_byte - write a byte to a packed context structure 4378 * @src_ctx: the context structure to read from 4379 * @dest_ctx: the context to be written to 4380 * @ce_info: a description of the struct to be filled 4381 */ 4382 static void 4383 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4384 { 4385 u8 src_byte, dest_byte, mask; 4386 u8 *from, *dest; 4387 u16 shift_width; 4388 4389 /* copy from the next struct field */ 4390 from = src_ctx + ce_info->offset; 4391 4392 /* prepare the bits and mask */ 4393 shift_width = ce_info->lsb % 8; 4394 mask = (u8)(BIT(ce_info->width) - 1); 4395 4396 src_byte = *from; 4397 src_byte &= mask; 4398 4399 /* shift to correct alignment */ 4400 mask <<= shift_width; 4401 src_byte <<= shift_width; 4402 4403 /* get the current bits from the target bit string */ 4404 dest = dest_ctx + (ce_info->lsb / 8); 4405 4406 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 4407 4408 dest_byte &= ~mask; /* get the bits not changing */ 4409 dest_byte |= src_byte; /* add in the new bits */ 4410 4411 /* put it all back */ 4412 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 4413 } 4414 4415 /** 4416 * ice_write_word - write a word to a packed context structure 4417 * @src_ctx: the context structure to read from 4418 * @dest_ctx: the context to be written to 4419 * @ce_info: a description of the struct to be filled 4420 */ 4421 static void 4422 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4423 { 4424 u16 src_word, mask; 4425 __le16 dest_word; 4426 u8 *from, *dest; 4427 u16 shift_width; 4428 4429 /* copy from the next struct field */ 4430 from = src_ctx + ce_info->offset; 4431 4432 /* prepare the bits and mask */ 4433 shift_width = ce_info->lsb % 8; 4434 mask = BIT(ce_info->width) - 1; 4435 4436 /* don't swizzle the bits until after the mask because the mask bits 4437 * will be in a different bit position on big endian machines 4438 */ 4439 src_word = *(u16 *)from; 4440 src_word &= mask; 4441 4442 /* shift to correct alignment */ 4443 mask <<= shift_width; 4444 src_word <<= shift_width; 4445 4446 /* get the current bits from the target bit string */ 4447 dest = dest_ctx + (ce_info->lsb / 8); 4448 4449 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA); 4450 4451 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */ 4452 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */ 4453 4454 /* put it all back */ 4455 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 4456 } 4457 4458 /** 4459 * ice_write_dword - write a dword to a packed context structure 4460 * @src_ctx: the context structure to read from 4461 * @dest_ctx: the context to be written to 4462 * @ce_info: a description of the struct to be filled 4463 */ 4464 static void 4465 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4466 { 4467 u32 src_dword, mask; 4468 __le32 dest_dword; 4469 u8 *from, *dest; 4470 u16 shift_width; 4471 4472 /* copy from the next struct field */ 4473 from = src_ctx + ce_info->offset; 4474 4475 /* prepare the bits and mask */ 4476 shift_width = ce_info->lsb % 8; 4477 4478 /* if the field width is exactly 32 on an x86 machine, then the shift 4479 * operation will not work because the SHL instructions count is masked 4480 * to 5 bits so the shift will do nothing 4481 */ 4482 if (ce_info->width < 32) 4483 mask = BIT(ce_info->width) - 1; 4484 else 4485 mask = (u32)~0; 4486 4487 /* don't swizzle the bits until after the mask because the mask bits 4488 * will be in a different bit position on big endian machines 4489 */ 4490 src_dword = *(u32 *)from; 4491 src_dword &= mask; 4492 4493 /* shift to correct alignment */ 4494 mask <<= shift_width; 4495 src_dword <<= shift_width; 4496 4497 /* get the current bits from the target bit string */ 4498 dest = dest_ctx + (ce_info->lsb / 8); 4499 4500 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA); 4501 4502 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */ 4503 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */ 4504 4505 /* put it all back */ 4506 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 4507 } 4508 4509 /** 4510 * ice_write_qword - write a qword to a packed context structure 4511 * @src_ctx: the context structure to read from 4512 * @dest_ctx: the context to be written to 4513 * @ce_info: a description of the struct to be filled 4514 */ 4515 static void 4516 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4517 { 4518 u64 src_qword, mask; 4519 __le64 dest_qword; 4520 u8 *from, *dest; 4521 u16 shift_width; 4522 4523 /* copy from the next struct field */ 4524 from = src_ctx + ce_info->offset; 4525 4526 /* prepare the bits and mask */ 4527 shift_width = ce_info->lsb % 8; 4528 4529 /* if the field width is exactly 64 on an x86 machine, then the shift 4530 * operation will not work because the SHL instructions count is masked 4531 * to 6 bits so the shift will do nothing 4532 */ 4533 if (ce_info->width < 64) 4534 mask = BIT_ULL(ce_info->width) - 1; 4535 else 4536 mask = (u64)~0; 4537 4538 /* don't swizzle the bits until after the mask because the mask bits 4539 * will be in a different bit position on big endian machines 4540 */ 4541 src_qword = *(u64 *)from; 4542 src_qword &= mask; 4543 4544 /* shift to correct alignment */ 4545 mask <<= shift_width; 4546 src_qword <<= shift_width; 4547 4548 /* get the current bits from the target bit string */ 4549 dest = dest_ctx + (ce_info->lsb / 8); 4550 4551 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA); 4552 4553 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */ 4554 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */ 4555 4556 /* put it all back */ 4557 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 4558 } 4559 4560 /** 4561 * ice_set_ctx - set context bits in packed structure 4562 * @hw: pointer to the hardware structure 4563 * @src_ctx: pointer to a generic non-packed context structure 4564 * @dest_ctx: pointer to memory for the packed structure 4565 * @ce_info: a description of the structure to be transformed 4566 */ 4567 enum ice_status 4568 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 4569 const struct ice_ctx_ele *ce_info) 4570 { 4571 int f; 4572 4573 for (f = 0; ce_info[f].width; f++) { 4574 /* We have to deal with each element of the FW response 4575 * using the correct size so that we are correct regardless 4576 * of the endianness of the machine. 4577 */ 4578 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 4579 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 4580 f, ce_info[f].width, ce_info[f].size_of); 4581 continue; 4582 } 4583 switch (ce_info[f].size_of) { 4584 case sizeof(u8): 4585 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 4586 break; 4587 case sizeof(u16): 4588 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 4589 break; 4590 case sizeof(u32): 4591 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 4592 break; 4593 case sizeof(u64): 4594 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 4595 break; 4596 default: 4597 return ICE_ERR_INVAL_SIZE; 4598 } 4599 } 4600 4601 return ICE_SUCCESS; 4602 } 4603 4604 /** 4605 * ice_aq_get_internal_data 4606 * @hw: pointer to the hardware structure 4607 * @cluster_id: specific cluster to dump 4608 * @table_id: table ID within cluster 4609 * @start: index of line in the block to read 4610 * @buf: dump buffer 4611 * @buf_size: dump buffer size 4612 * @ret_buf_size: return buffer size (returned by FW) 4613 * @ret_next_table: next block to read (returned by FW) 4614 * @ret_next_index: next index to read (returned by FW) 4615 * @cd: pointer to command details structure 4616 * 4617 * Get internal FW/HW data (0xFF08) for debug purposes. 4618 */ 4619 enum ice_status 4620 ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id, 4621 u32 start, void *buf, u16 buf_size, u16 *ret_buf_size, 4622 u16 *ret_next_table, u32 *ret_next_index, 4623 struct ice_sq_cd *cd) 4624 { 4625 struct ice_aqc_debug_dump_internals *cmd; 4626 struct ice_aq_desc desc; 4627 enum ice_status status; 4628 4629 cmd = &desc.params.debug_dump; 4630 4631 if (buf_size == 0 || !buf) 4632 return ICE_ERR_PARAM; 4633 4634 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_debug_dump_internals); 4635 4636 cmd->cluster_id = cluster_id; 4637 cmd->table_id = CPU_TO_LE16(table_id); 4638 cmd->idx = CPU_TO_LE32(start); 4639 4640 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4641 4642 if (!status) { 4643 if (ret_buf_size) 4644 *ret_buf_size = LE16_TO_CPU(desc.datalen); 4645 if (ret_next_table) 4646 *ret_next_table = LE16_TO_CPU(cmd->table_id); 4647 if (ret_next_index) 4648 *ret_next_index = LE32_TO_CPU(cmd->idx); 4649 } 4650 4651 return status; 4652 } 4653 4654 /** 4655 * ice_read_byte - read context byte into struct 4656 * @src_ctx: the context structure to read from 4657 * @dest_ctx: the context to be written to 4658 * @ce_info: a description of the struct to be filled 4659 */ 4660 static void 4661 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4662 { 4663 u8 dest_byte, mask; 4664 u8 *src, *target; 4665 u16 shift_width; 4666 4667 /* prepare the bits and mask */ 4668 shift_width = ce_info->lsb % 8; 4669 mask = (u8)(BIT(ce_info->width) - 1); 4670 4671 /* shift to correct alignment */ 4672 mask <<= shift_width; 4673 4674 /* get the current bits from the src bit string */ 4675 src = src_ctx + (ce_info->lsb / 8); 4676 4677 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 4678 4679 dest_byte &= ~(mask); 4680 4681 dest_byte >>= shift_width; 4682 4683 /* get the address from the struct field */ 4684 target = dest_ctx + ce_info->offset; 4685 4686 /* put it back in the struct */ 4687 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 4688 } 4689 4690 /** 4691 * ice_read_word - read context word into struct 4692 * @src_ctx: the context structure to read from 4693 * @dest_ctx: the context to be written to 4694 * @ce_info: a description of the struct to be filled 4695 */ 4696 static void 4697 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4698 { 4699 u16 dest_word, mask; 4700 u8 *src, *target; 4701 __le16 src_word; 4702 u16 shift_width; 4703 4704 /* prepare the bits and mask */ 4705 shift_width = ce_info->lsb % 8; 4706 mask = BIT(ce_info->width) - 1; 4707 4708 /* shift to correct alignment */ 4709 mask <<= shift_width; 4710 4711 /* get the current bits from the src bit string */ 4712 src = src_ctx + (ce_info->lsb / 8); 4713 4714 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA); 4715 4716 /* the data in the memory is stored as little endian so mask it 4717 * correctly 4718 */ 4719 src_word &= ~(CPU_TO_LE16(mask)); 4720 4721 /* get the data back into host order before shifting */ 4722 dest_word = LE16_TO_CPU(src_word); 4723 4724 dest_word >>= shift_width; 4725 4726 /* get the address from the struct field */ 4727 target = dest_ctx + ce_info->offset; 4728 4729 /* put it back in the struct */ 4730 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 4731 } 4732 4733 /** 4734 * ice_read_dword - read context dword into struct 4735 * @src_ctx: the context structure to read from 4736 * @dest_ctx: the context to be written to 4737 * @ce_info: a description of the struct to be filled 4738 */ 4739 static void 4740 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4741 { 4742 u32 dest_dword, mask; 4743 __le32 src_dword; 4744 u8 *src, *target; 4745 u16 shift_width; 4746 4747 /* prepare the bits and mask */ 4748 shift_width = ce_info->lsb % 8; 4749 4750 /* if the field width is exactly 32 on an x86 machine, then the shift 4751 * operation will not work because the SHL instructions count is masked 4752 * to 5 bits so the shift will do nothing 4753 */ 4754 if (ce_info->width < 32) 4755 mask = BIT(ce_info->width) - 1; 4756 else 4757 mask = (u32)~0; 4758 4759 /* shift to correct alignment */ 4760 mask <<= shift_width; 4761 4762 /* get the current bits from the src bit string */ 4763 src = src_ctx + (ce_info->lsb / 8); 4764 4765 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA); 4766 4767 /* the data in the memory is stored as little endian so mask it 4768 * correctly 4769 */ 4770 src_dword &= ~(CPU_TO_LE32(mask)); 4771 4772 /* get the data back into host order before shifting */ 4773 dest_dword = LE32_TO_CPU(src_dword); 4774 4775 dest_dword >>= shift_width; 4776 4777 /* get the address from the struct field */ 4778 target = dest_ctx + ce_info->offset; 4779 4780 /* put it back in the struct */ 4781 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 4782 } 4783 4784 /** 4785 * ice_read_qword - read context qword into struct 4786 * @src_ctx: the context structure to read from 4787 * @dest_ctx: the context to be written to 4788 * @ce_info: a description of the struct to be filled 4789 */ 4790 static void 4791 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4792 { 4793 u64 dest_qword, mask; 4794 __le64 src_qword; 4795 u8 *src, *target; 4796 u16 shift_width; 4797 4798 /* prepare the bits and mask */ 4799 shift_width = ce_info->lsb % 8; 4800 4801 /* if the field width is exactly 64 on an x86 machine, then the shift 4802 * operation will not work because the SHL instructions count is masked 4803 * to 6 bits so the shift will do nothing 4804 */ 4805 if (ce_info->width < 64) 4806 mask = BIT_ULL(ce_info->width) - 1; 4807 else 4808 mask = (u64)~0; 4809 4810 /* shift to correct alignment */ 4811 mask <<= shift_width; 4812 4813 /* get the current bits from the src bit string */ 4814 src = src_ctx + (ce_info->lsb / 8); 4815 4816 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA); 4817 4818 /* the data in the memory is stored as little endian so mask it 4819 * correctly 4820 */ 4821 src_qword &= ~(CPU_TO_LE64(mask)); 4822 4823 /* get the data back into host order before shifting */ 4824 dest_qword = LE64_TO_CPU(src_qword); 4825 4826 dest_qword >>= shift_width; 4827 4828 /* get the address from the struct field */ 4829 target = dest_ctx + ce_info->offset; 4830 4831 /* put it back in the struct */ 4832 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 4833 } 4834 4835 /** 4836 * ice_get_ctx - extract context bits from a packed structure 4837 * @src_ctx: pointer to a generic packed context structure 4838 * @dest_ctx: pointer to a generic non-packed context structure 4839 * @ce_info: a description of the structure to be read from 4840 */ 4841 enum ice_status 4842 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4843 { 4844 int f; 4845 4846 for (f = 0; ce_info[f].width; f++) { 4847 switch (ce_info[f].size_of) { 4848 case 1: 4849 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]); 4850 break; 4851 case 2: 4852 ice_read_word(src_ctx, dest_ctx, &ce_info[f]); 4853 break; 4854 case 4: 4855 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]); 4856 break; 4857 case 8: 4858 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]); 4859 break; 4860 default: 4861 /* nothing to do, just keep going */ 4862 break; 4863 } 4864 } 4865 4866 return ICE_SUCCESS; 4867 } 4868 4869 /** 4870 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4871 * @hw: pointer to the HW struct 4872 * @vsi_handle: software VSI handle 4873 * @tc: TC number 4874 * @q_handle: software queue handle 4875 */ 4876 struct ice_q_ctx * 4877 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4878 { 4879 struct ice_vsi_ctx *vsi; 4880 struct ice_q_ctx *q_ctx; 4881 4882 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4883 if (!vsi) 4884 return NULL; 4885 if (q_handle >= vsi->num_lan_q_entries[tc]) 4886 return NULL; 4887 if (!vsi->lan_q_ctx[tc]) 4888 return NULL; 4889 q_ctx = vsi->lan_q_ctx[tc]; 4890 return &q_ctx[q_handle]; 4891 } 4892 4893 /** 4894 * ice_ena_vsi_txq 4895 * @pi: port information structure 4896 * @vsi_handle: software VSI handle 4897 * @tc: TC number 4898 * @q_handle: software queue handle 4899 * @num_qgrps: Number of added queue groups 4900 * @buf: list of queue groups to be added 4901 * @buf_size: size of buffer for indirect command 4902 * @cd: pointer to command details structure or NULL 4903 * 4904 * This function adds one LAN queue 4905 */ 4906 enum ice_status 4907 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4908 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4909 struct ice_sq_cd *cd) 4910 { 4911 struct ice_aqc_txsched_elem_data node = { 0 }; 4912 struct ice_sched_node *parent; 4913 struct ice_q_ctx *q_ctx; 4914 enum ice_status status; 4915 struct ice_hw *hw; 4916 4917 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4918 return ICE_ERR_CFG; 4919 4920 if (num_qgrps > 1 || buf->num_txqs > 1) 4921 return ICE_ERR_MAX_LIMIT; 4922 4923 hw = pi->hw; 4924 4925 if (!ice_is_vsi_valid(hw, vsi_handle)) 4926 return ICE_ERR_PARAM; 4927 4928 ice_acquire_lock(&pi->sched_lock); 4929 4930 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4931 if (!q_ctx) { 4932 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4933 q_handle); 4934 status = ICE_ERR_PARAM; 4935 goto ena_txq_exit; 4936 } 4937 4938 /* find a parent node */ 4939 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4940 ICE_SCHED_NODE_OWNER_LAN); 4941 if (!parent) { 4942 status = ICE_ERR_PARAM; 4943 goto ena_txq_exit; 4944 } 4945 4946 buf->parent_teid = parent->info.node_teid; 4947 node.parent_teid = parent->info.node_teid; 4948 /* Mark that the values in the "generic" section as valid. The default 4949 * value in the "generic" section is zero. This means that : 4950 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4951 * - 0 priority among siblings, indicated by Bit 1-3. 4952 * - WFQ, indicated by Bit 4. 4953 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4954 * Bit 5-6. 4955 * - Bit 7 is reserved. 4956 * Without setting the generic section as valid in valid_sections, the 4957 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4958 */ 4959 buf->txqs[0].info.valid_sections = 4960 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4961 ICE_AQC_ELEM_VALID_EIR; 4962 buf->txqs[0].info.generic = 0; 4963 buf->txqs[0].info.cir_bw.bw_profile_idx = 4964 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 4965 buf->txqs[0].info.cir_bw.bw_alloc = 4966 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 4967 buf->txqs[0].info.eir_bw.bw_profile_idx = 4968 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 4969 buf->txqs[0].info.eir_bw.bw_alloc = 4970 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 4971 4972 /* add the LAN queue */ 4973 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4974 if (status != ICE_SUCCESS) { 4975 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4976 LE16_TO_CPU(buf->txqs[0].txq_id), 4977 hw->adminq.sq_last_status); 4978 goto ena_txq_exit; 4979 } 4980 4981 node.node_teid = buf->txqs[0].q_teid; 4982 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4983 q_ctx->q_handle = q_handle; 4984 q_ctx->q_teid = LE32_TO_CPU(node.node_teid); 4985 4986 /* add a leaf node into scheduler tree queue layer */ 4987 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 4988 if (!status) 4989 status = ice_sched_replay_q_bw(pi, q_ctx); 4990 4991 ena_txq_exit: 4992 ice_release_lock(&pi->sched_lock); 4993 return status; 4994 } 4995 4996 /** 4997 * ice_dis_vsi_txq 4998 * @pi: port information structure 4999 * @vsi_handle: software VSI handle 5000 * @tc: TC number 5001 * @num_queues: number of queues 5002 * @q_handles: pointer to software queue handle array 5003 * @q_ids: pointer to the q_id array 5004 * @q_teids: pointer to queue node teids 5005 * @rst_src: if called due to reset, specifies the reset source 5006 * @vmvf_num: the relative VM or VF number that is undergoing the reset 5007 * @cd: pointer to command details structure or NULL 5008 * 5009 * This function removes queues and their corresponding nodes in SW DB 5010 */ 5011 enum ice_status 5012 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 5013 u16 *q_handles, u16 *q_ids, u32 *q_teids, 5014 enum ice_disq_rst_src rst_src, u16 vmvf_num, 5015 struct ice_sq_cd *cd) 5016 { 5017 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 5018 struct ice_aqc_dis_txq_item *qg_list; 5019 struct ice_q_ctx *q_ctx; 5020 struct ice_hw *hw; 5021 u16 i, buf_size; 5022 5023 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5024 return ICE_ERR_CFG; 5025 5026 hw = pi->hw; 5027 5028 if (!num_queues) { 5029 /* if queue is disabled already yet the disable queue command 5030 * has to be sent to complete the VF reset, then call 5031 * ice_aq_dis_lan_txq without any queue information 5032 */ 5033 if (rst_src) 5034 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 5035 vmvf_num, NULL); 5036 return ICE_ERR_CFG; 5037 } 5038 5039 buf_size = ice_struct_size(qg_list, q_id, 1); 5040 qg_list = (struct ice_aqc_dis_txq_item *)ice_malloc(hw, buf_size); 5041 if (!qg_list) 5042 return ICE_ERR_NO_MEMORY; 5043 5044 ice_acquire_lock(&pi->sched_lock); 5045 5046 for (i = 0; i < num_queues; i++) { 5047 struct ice_sched_node *node; 5048 5049 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 5050 if (!node) 5051 continue; 5052 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 5053 if (!q_ctx) { 5054 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 5055 q_handles[i]); 5056 continue; 5057 } 5058 if (q_ctx->q_handle != q_handles[i]) { 5059 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 5060 q_ctx->q_handle, q_handles[i]); 5061 continue; 5062 } 5063 qg_list->parent_teid = node->info.parent_teid; 5064 qg_list->num_qs = 1; 5065 qg_list->q_id[0] = CPU_TO_LE16(q_ids[i]); 5066 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 5067 vmvf_num, cd); 5068 5069 if (status != ICE_SUCCESS) 5070 break; 5071 ice_free_sched_node(pi, node); 5072 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 5073 } 5074 ice_release_lock(&pi->sched_lock); 5075 ice_free(hw, qg_list); 5076 return status; 5077 } 5078 5079 /** 5080 * ice_cfg_vsi_qs - configure the new/existing VSI queues 5081 * @pi: port information structure 5082 * @vsi_handle: software VSI handle 5083 * @tc_bitmap: TC bitmap 5084 * @maxqs: max queues array per TC 5085 * @owner: LAN or RDMA 5086 * 5087 * This function adds/updates the VSI queues per TC. 5088 */ 5089 static enum ice_status 5090 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 5091 u16 *maxqs, u8 owner) 5092 { 5093 enum ice_status status = ICE_SUCCESS; 5094 u8 i; 5095 5096 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5097 return ICE_ERR_CFG; 5098 5099 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 5100 return ICE_ERR_PARAM; 5101 5102 ice_acquire_lock(&pi->sched_lock); 5103 5104 ice_for_each_traffic_class(i) { 5105 /* configuration is possible only if TC node is present */ 5106 if (!ice_sched_get_tc_node(pi, i)) 5107 continue; 5108 5109 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 5110 ice_is_tc_ena(tc_bitmap, i)); 5111 if (status) 5112 break; 5113 } 5114 5115 ice_release_lock(&pi->sched_lock); 5116 return status; 5117 } 5118 5119 /** 5120 * ice_cfg_vsi_lan - configure VSI LAN queues 5121 * @pi: port information structure 5122 * @vsi_handle: software VSI handle 5123 * @tc_bitmap: TC bitmap 5124 * @max_lanqs: max LAN queues array per TC 5125 * 5126 * This function adds/updates the VSI LAN queues per TC. 5127 */ 5128 enum ice_status 5129 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 5130 u16 *max_lanqs) 5131 { 5132 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 5133 ICE_SCHED_NODE_OWNER_LAN); 5134 } 5135 5136 /** 5137 * ice_is_main_vsi - checks whether the VSI is main VSI 5138 * @hw: pointer to the HW struct 5139 * @vsi_handle: VSI handle 5140 * 5141 * Checks whether the VSI is the main VSI (the first PF VSI created on 5142 * given PF). 5143 */ 5144 static bool ice_is_main_vsi(struct ice_hw *hw, u16 vsi_handle) 5145 { 5146 return vsi_handle == ICE_MAIN_VSI_HANDLE && hw->vsi_ctx[vsi_handle]; 5147 } 5148 5149 /** 5150 * ice_replay_pre_init - replay pre initialization 5151 * @hw: pointer to the HW struct 5152 * @sw: pointer to switch info struct for which function initializes filters 5153 * 5154 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 5155 */ 5156 enum ice_status 5157 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw) 5158 { 5159 enum ice_status status; 5160 u8 i; 5161 5162 /* Delete old entries from replay filter list head if there is any */ 5163 ice_rm_sw_replay_rule_info(hw, sw); 5164 /* In start of replay, move entries into replay_rules list, it 5165 * will allow adding rules entries back to filt_rules list, 5166 * which is operational list. 5167 */ 5168 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 5169 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules, 5170 &sw->recp_list[i].filt_replay_rules); 5171 ice_sched_replay_agg_vsi_preinit(hw); 5172 5173 status = ice_sched_replay_root_node_bw(hw->port_info); 5174 if (status) 5175 return status; 5176 5177 return ice_sched_replay_tc_node_bw(hw->port_info); 5178 } 5179 5180 /** 5181 * ice_replay_vsi - replay VSI configuration 5182 * @hw: pointer to the HW struct 5183 * @vsi_handle: driver VSI handle 5184 * 5185 * Restore all VSI configuration after reset. It is required to call this 5186 * function with main VSI first. 5187 */ 5188 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 5189 { 5190 struct ice_switch_info *sw = hw->switch_info; 5191 struct ice_port_info *pi = hw->port_info; 5192 enum ice_status status; 5193 5194 if (!ice_is_vsi_valid(hw, vsi_handle)) 5195 return ICE_ERR_PARAM; 5196 5197 /* Replay pre-initialization if there is any */ 5198 if (ice_is_main_vsi(hw, vsi_handle)) { 5199 status = ice_replay_pre_init(hw, sw); 5200 if (status) 5201 return status; 5202 } 5203 /* Replay per VSI all RSS configurations */ 5204 status = ice_replay_rss_cfg(hw, vsi_handle); 5205 if (status) 5206 return status; 5207 /* Replay per VSI all filters */ 5208 status = ice_replay_vsi_all_fltr(hw, pi, vsi_handle); 5209 if (!status) 5210 status = ice_replay_vsi_agg(hw, vsi_handle); 5211 return status; 5212 } 5213 5214 /** 5215 * ice_replay_post - post replay configuration cleanup 5216 * @hw: pointer to the HW struct 5217 * 5218 * Post replay cleanup. 5219 */ 5220 void ice_replay_post(struct ice_hw *hw) 5221 { 5222 /* Delete old entries from replay filter list head */ 5223 ice_rm_all_sw_replay_rule_info(hw); 5224 ice_sched_replay_agg(hw); 5225 } 5226 5227 /** 5228 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5229 * @hw: ptr to the hardware info 5230 * @reg: offset of 64 bit HW register to read from 5231 * @prev_stat_loaded: bool to specify if previous stats are loaded 5232 * @prev_stat: ptr to previous loaded stat value 5233 * @cur_stat: ptr to current stat value 5234 */ 5235 void 5236 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5237 u64 *prev_stat, u64 *cur_stat) 5238 { 5239 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5240 5241 /* device stats are not reset at PFR, they likely will not be zeroed 5242 * when the driver starts. Thus, save the value from the first read 5243 * without adding to the statistic value so that we report stats which 5244 * count up from zero. 5245 */ 5246 if (!prev_stat_loaded) { 5247 *prev_stat = new_data; 5248 return; 5249 } 5250 5251 /* Calculate the difference between the new and old values, and then 5252 * add it to the software stat value. 5253 */ 5254 if (new_data >= *prev_stat) 5255 *cur_stat += new_data - *prev_stat; 5256 else 5257 /* to manage the potential roll-over */ 5258 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5259 5260 /* Update the previously stored value to prepare for next read */ 5261 *prev_stat = new_data; 5262 } 5263 5264 /** 5265 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5266 * @hw: ptr to the hardware info 5267 * @reg: offset of HW register to read from 5268 * @prev_stat_loaded: bool to specify if previous stats are loaded 5269 * @prev_stat: ptr to previous loaded stat value 5270 * @cur_stat: ptr to current stat value 5271 */ 5272 void 5273 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5274 u64 *prev_stat, u64 *cur_stat) 5275 { 5276 u32 new_data; 5277 5278 new_data = rd32(hw, reg); 5279 5280 /* device stats are not reset at PFR, they likely will not be zeroed 5281 * when the driver starts. Thus, save the value from the first read 5282 * without adding to the statistic value so that we report stats which 5283 * count up from zero. 5284 */ 5285 if (!prev_stat_loaded) { 5286 *prev_stat = new_data; 5287 return; 5288 } 5289 5290 /* Calculate the difference between the new and old values, and then 5291 * add it to the software stat value. 5292 */ 5293 if (new_data >= *prev_stat) 5294 *cur_stat += new_data - *prev_stat; 5295 else 5296 /* to manage the potential roll-over */ 5297 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5298 5299 /* Update the previously stored value to prepare for next read */ 5300 *prev_stat = new_data; 5301 } 5302 5303 /** 5304 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values 5305 * @hw: ptr to the hardware info 5306 * @vsi_handle: VSI handle 5307 * @prev_stat_loaded: bool to specify if the previous stat values are loaded 5308 * @cur_stats: ptr to current stats structure 5309 * 5310 * The GLV_REPC statistic register actually tracks two 16bit statistics, and 5311 * thus cannot be read using the normal ice_stat_update32 function. 5312 * 5313 * Read the GLV_REPC register associated with the given VSI, and update the 5314 * rx_no_desc and rx_error values in the ice_eth_stats structure. 5315 * 5316 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be 5317 * cleared each time it's read. 5318 * 5319 * Note that the GLV_RDPC register also counts the causes that would trigger 5320 * GLV_REPC. However, it does not give the finer grained detail about why the 5321 * packets are being dropped. The GLV_REPC values can be used to distinguish 5322 * whether Rx packets are dropped due to errors or due to no available 5323 * descriptors. 5324 */ 5325 void 5326 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded, 5327 struct ice_eth_stats *cur_stats) 5328 { 5329 u16 vsi_num, no_desc, error_cnt; 5330 u32 repc; 5331 5332 if (!ice_is_vsi_valid(hw, vsi_handle)) 5333 return; 5334 5335 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle); 5336 5337 /* If we haven't loaded stats yet, just clear the current value */ 5338 if (!prev_stat_loaded) { 5339 wr32(hw, GLV_REPC(vsi_num), 0); 5340 return; 5341 } 5342 5343 repc = rd32(hw, GLV_REPC(vsi_num)); 5344 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S; 5345 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S; 5346 5347 /* Clear the count by writing to the stats register */ 5348 wr32(hw, GLV_REPC(vsi_num), 0); 5349 5350 cur_stats->rx_no_desc += no_desc; 5351 cur_stats->rx_errors += error_cnt; 5352 } 5353 5354 /** 5355 * ice_sched_query_elem - query element information from HW 5356 * @hw: pointer to the HW struct 5357 * @node_teid: node TEID to be queried 5358 * @buf: buffer to element information 5359 * 5360 * This function queries HW element information 5361 */ 5362 enum ice_status 5363 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5364 struct ice_aqc_txsched_elem_data *buf) 5365 { 5366 u16 buf_size, num_elem_ret = 0; 5367 enum ice_status status; 5368 5369 buf_size = sizeof(*buf); 5370 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM); 5371 buf->node_teid = CPU_TO_LE32(node_teid); 5372 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5373 NULL); 5374 if (status != ICE_SUCCESS || num_elem_ret != 1) 5375 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5376 return status; 5377 } 5378 5379 /** 5380 * ice_get_fw_mode - returns FW mode 5381 * @hw: pointer to the HW struct 5382 */ 5383 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw) 5384 { 5385 #define ICE_FW_MODE_DBG_M BIT(0) 5386 #define ICE_FW_MODE_REC_M BIT(1) 5387 #define ICE_FW_MODE_ROLLBACK_M BIT(2) 5388 u32 fw_mode; 5389 5390 /* check the current FW mode */ 5391 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M; 5392 5393 if (fw_mode & ICE_FW_MODE_DBG_M) 5394 return ICE_FW_MODE_DBG; 5395 else if (fw_mode & ICE_FW_MODE_REC_M) 5396 return ICE_FW_MODE_REC; 5397 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M) 5398 return ICE_FW_MODE_ROLLBACK; 5399 else 5400 return ICE_FW_MODE_NORMAL; 5401 } 5402 5403 /** 5404 * ice_aq_read_i2c 5405 * @hw: pointer to the hw struct 5406 * @topo_addr: topology address for a device to communicate with 5407 * @bus_addr: 7-bit I2C bus address 5408 * @addr: I2C memory address (I2C offset) with up to 16 bits 5409 * @params: I2C parameters: bit [7] - Repeated start, bits [6:5] data offset size, 5410 * bit [4] - I2C address type, bits [3:0] - data size to read (0-16 bytes) 5411 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5412 * @cd: pointer to command details structure or NULL 5413 * 5414 * Read I2C (0x06E2) 5415 */ 5416 enum ice_status 5417 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5418 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5419 struct ice_sq_cd *cd) 5420 { 5421 struct ice_aq_desc desc = { 0 }; 5422 struct ice_aqc_i2c *cmd; 5423 enum ice_status status; 5424 u8 data_size; 5425 5426 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5427 cmd = &desc.params.read_write_i2c; 5428 5429 if (!data) 5430 return ICE_ERR_PARAM; 5431 5432 data_size = (params & ICE_AQC_I2C_DATA_SIZE_M) >> ICE_AQC_I2C_DATA_SIZE_S; 5433 5434 cmd->i2c_bus_addr = CPU_TO_LE16(bus_addr); 5435 cmd->topo_addr = topo_addr; 5436 cmd->i2c_params = params; 5437 cmd->i2c_addr = addr; 5438 5439 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5440 if (!status) { 5441 struct ice_aqc_read_i2c_resp *resp; 5442 u8 i; 5443 5444 resp = &desc.params.read_i2c_resp; 5445 for (i = 0; i < data_size; i++) { 5446 *data = resp->i2c_data[i]; 5447 data++; 5448 } 5449 } 5450 5451 return status; 5452 } 5453 5454 /** 5455 * ice_aq_write_i2c 5456 * @hw: pointer to the hw struct 5457 * @topo_addr: topology address for a device to communicate with 5458 * @bus_addr: 7-bit I2C bus address 5459 * @addr: I2C memory address (I2C offset) with up to 16 bits 5460 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5461 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5462 * @cd: pointer to command details structure or NULL 5463 * 5464 * Write I2C (0x06E3) 5465 */ 5466 enum ice_status 5467 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5468 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5469 struct ice_sq_cd *cd) 5470 { 5471 struct ice_aq_desc desc = { 0 }; 5472 struct ice_aqc_i2c *cmd; 5473 u8 i, data_size; 5474 5475 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 5476 cmd = &desc.params.read_write_i2c; 5477 5478 data_size = (params & ICE_AQC_I2C_DATA_SIZE_M) >> ICE_AQC_I2C_DATA_SIZE_S; 5479 5480 /* data_size limited to 4 */ 5481 if (data_size > 4) 5482 return ICE_ERR_PARAM; 5483 5484 cmd->i2c_bus_addr = CPU_TO_LE16(bus_addr); 5485 cmd->topo_addr = topo_addr; 5486 cmd->i2c_params = params; 5487 cmd->i2c_addr = addr; 5488 5489 for (i = 0; i < data_size; i++) { 5490 cmd->i2c_data[i] = *data; 5491 data++; 5492 } 5493 5494 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5495 } 5496 5497 /** 5498 * ice_aq_set_driver_param - Set driver parameter to share via firmware 5499 * @hw: pointer to the HW struct 5500 * @idx: parameter index to set 5501 * @value: the value to set the parameter to 5502 * @cd: pointer to command details structure or NULL 5503 * 5504 * Set the value of one of the software defined parameters. All PFs connected 5505 * to this device can read the value using ice_aq_get_driver_param. 5506 * 5507 * Note that firmware provides no synchronization or locking, and will not 5508 * save the parameter value during a device reset. It is expected that 5509 * a single PF will write the parameter value, while all other PFs will only 5510 * read it. 5511 */ 5512 enum ice_status 5513 ice_aq_set_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx, 5514 u32 value, struct ice_sq_cd *cd) 5515 { 5516 struct ice_aqc_driver_shared_params *cmd; 5517 struct ice_aq_desc desc; 5518 5519 if (idx >= ICE_AQC_DRIVER_PARAM_MAX) 5520 return ICE_ERR_OUT_OF_RANGE; 5521 5522 cmd = &desc.params.drv_shared_params; 5523 5524 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params); 5525 5526 cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_SET; 5527 cmd->param_indx = idx; 5528 cmd->param_val = CPU_TO_LE32(value); 5529 5530 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5531 } 5532 5533 /** 5534 * ice_aq_get_driver_param - Get driver parameter shared via firmware 5535 * @hw: pointer to the HW struct 5536 * @idx: parameter index to set 5537 * @value: storage to return the shared parameter 5538 * @cd: pointer to command details structure or NULL 5539 * 5540 * Get the value of one of the software defined parameters. 5541 * 5542 * Note that firmware provides no synchronization or locking. It is expected 5543 * that only a single PF will write a given parameter. 5544 */ 5545 enum ice_status 5546 ice_aq_get_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx, 5547 u32 *value, struct ice_sq_cd *cd) 5548 { 5549 struct ice_aqc_driver_shared_params *cmd; 5550 struct ice_aq_desc desc; 5551 enum ice_status status; 5552 5553 if (idx >= ICE_AQC_DRIVER_PARAM_MAX) 5554 return ICE_ERR_OUT_OF_RANGE; 5555 5556 cmd = &desc.params.drv_shared_params; 5557 5558 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params); 5559 5560 cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_GET; 5561 cmd->param_indx = idx; 5562 5563 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5564 if (status) 5565 return status; 5566 5567 *value = LE32_TO_CPU(cmd->param_val); 5568 5569 return ICE_SUCCESS; 5570 } 5571 5572 /** 5573 * ice_aq_set_gpio 5574 * @hw: pointer to the hw struct 5575 * @gpio_ctrl_handle: GPIO controller node handle 5576 * @pin_idx: IO Number of the GPIO that needs to be set 5577 * @value: SW provide IO value to set in the LSB 5578 * @cd: pointer to command details structure or NULL 5579 * 5580 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 5581 */ 5582 enum ice_status 5583 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 5584 struct ice_sq_cd *cd) 5585 { 5586 struct ice_aqc_gpio *cmd; 5587 struct ice_aq_desc desc; 5588 5589 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 5590 cmd = &desc.params.read_write_gpio; 5591 cmd->gpio_ctrl_handle = gpio_ctrl_handle; 5592 cmd->gpio_num = pin_idx; 5593 cmd->gpio_val = value ? 1 : 0; 5594 5595 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5596 } 5597 5598 /** 5599 * ice_aq_get_gpio 5600 * @hw: pointer to the hw struct 5601 * @gpio_ctrl_handle: GPIO controller node handle 5602 * @pin_idx: IO Number of the GPIO that needs to be set 5603 * @value: IO value read 5604 * @cd: pointer to command details structure or NULL 5605 * 5606 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 5607 * the topology 5608 */ 5609 enum ice_status 5610 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 5611 bool *value, struct ice_sq_cd *cd) 5612 { 5613 struct ice_aqc_gpio *cmd; 5614 struct ice_aq_desc desc; 5615 enum ice_status status; 5616 5617 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 5618 cmd = &desc.params.read_write_gpio; 5619 cmd->gpio_ctrl_handle = gpio_ctrl_handle; 5620 cmd->gpio_num = pin_idx; 5621 5622 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5623 if (status) 5624 return status; 5625 5626 *value = !!cmd->gpio_val; 5627 return ICE_SUCCESS; 5628 } 5629 5630 /** 5631 * ice_fw_supports_link_override 5632 * @hw: pointer to the hardware structure 5633 * 5634 * Checks if the firmware supports link override 5635 */ 5636 bool ice_fw_supports_link_override(struct ice_hw *hw) 5637 { 5638 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) { 5639 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN) 5640 return true; 5641 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN && 5642 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH) 5643 return true; 5644 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) { 5645 return true; 5646 } 5647 5648 return false; 5649 } 5650 5651 /** 5652 * ice_get_link_default_override 5653 * @ldo: pointer to the link default override struct 5654 * @pi: pointer to the port info struct 5655 * 5656 * Gets the link default override for a port 5657 */ 5658 enum ice_status 5659 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 5660 struct ice_port_info *pi) 5661 { 5662 u16 i, tlv, tlv_len, tlv_start, buf, offset; 5663 struct ice_hw *hw = pi->hw; 5664 enum ice_status status; 5665 5666 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 5667 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 5668 if (status) { 5669 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 5670 return status; 5671 } 5672 5673 /* Each port has its own config; calculate for our port */ 5674 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 5675 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 5676 5677 /* link options first */ 5678 status = ice_read_sr_word(hw, tlv_start, &buf); 5679 if (status) { 5680 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5681 return status; 5682 } 5683 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 5684 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 5685 ICE_LINK_OVERRIDE_PHY_CFG_S; 5686 5687 /* link PHY config */ 5688 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 5689 status = ice_read_sr_word(hw, offset, &buf); 5690 if (status) { 5691 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 5692 return status; 5693 } 5694 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 5695 5696 /* PHY types low */ 5697 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 5698 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5699 status = ice_read_sr_word(hw, (offset + i), &buf); 5700 if (status) { 5701 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5702 return status; 5703 } 5704 /* shift 16 bits at a time to fill 64 bits */ 5705 ldo->phy_type_low |= ((u64)buf << (i * 16)); 5706 } 5707 5708 /* PHY types high */ 5709 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 5710 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 5711 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5712 status = ice_read_sr_word(hw, (offset + i), &buf); 5713 if (status) { 5714 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5715 return status; 5716 } 5717 /* shift 16 bits at a time to fill 64 bits */ 5718 ldo->phy_type_high |= ((u64)buf << (i * 16)); 5719 } 5720 5721 return status; 5722 } 5723 5724 /** 5725 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 5726 * @caps: get PHY capability data 5727 */ 5728 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 5729 { 5730 if (caps->caps & ICE_AQC_PHY_AN_MODE || 5731 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 5732 ICE_AQC_PHY_AN_EN_CLAUSE73 | 5733 ICE_AQC_PHY_AN_EN_CLAUSE37)) 5734 return true; 5735 5736 return false; 5737 } 5738 5739 /** 5740 * ice_aq_set_lldp_mib - Set the LLDP MIB 5741 * @hw: pointer to the HW struct 5742 * @mib_type: Local, Remote or both Local and Remote MIBs 5743 * @buf: pointer to the caller-supplied buffer to store the MIB block 5744 * @buf_size: size of the buffer (in bytes) 5745 * @cd: pointer to command details structure or NULL 5746 * 5747 * Set the LLDP MIB. (0x0A08) 5748 */ 5749 enum ice_status 5750 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 5751 struct ice_sq_cd *cd) 5752 { 5753 struct ice_aqc_lldp_set_local_mib *cmd; 5754 struct ice_aq_desc desc; 5755 5756 cmd = &desc.params.lldp_set_mib; 5757 5758 if (buf_size == 0 || !buf) 5759 return ICE_ERR_PARAM; 5760 5761 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 5762 5763 desc.flags |= CPU_TO_LE16((u16)ICE_AQ_FLAG_RD); 5764 desc.datalen = CPU_TO_LE16(buf_size); 5765 5766 cmd->type = mib_type; 5767 cmd->length = CPU_TO_LE16(buf_size); 5768 5769 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 5770 } 5771 5772 /** 5773 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 5774 * @hw: pointer to HW struct 5775 */ 5776 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 5777 { 5778 if (hw->mac_type != ICE_MAC_E810) 5779 return false; 5780 5781 if (hw->api_maj_ver == ICE_FW_API_LLDP_FLTR_MAJ) { 5782 if (hw->api_min_ver > ICE_FW_API_LLDP_FLTR_MIN) 5783 return true; 5784 if (hw->api_min_ver == ICE_FW_API_LLDP_FLTR_MIN && 5785 hw->api_patch >= ICE_FW_API_LLDP_FLTR_PATCH) 5786 return true; 5787 } else if (hw->api_maj_ver > ICE_FW_API_LLDP_FLTR_MAJ) { 5788 return true; 5789 } 5790 return false; 5791 } 5792 5793 /** 5794 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 5795 * @hw: pointer to HW struct 5796 * @vsi_num: absolute HW index for VSI 5797 * @add: boolean for if adding or removing a filter 5798 */ 5799 enum ice_status 5800 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 5801 { 5802 struct ice_aqc_lldp_filter_ctrl *cmd; 5803 struct ice_aq_desc desc; 5804 5805 cmd = &desc.params.lldp_filter_ctrl; 5806 5807 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 5808 5809 if (add) 5810 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 5811 else 5812 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 5813 5814 cmd->vsi_num = CPU_TO_LE16(vsi_num); 5815 5816 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5817 } 5818 5819 /** 5820 * ice_fw_supports_report_dflt_cfg 5821 * @hw: pointer to the hardware structure 5822 * 5823 * Checks if the firmware supports report default configuration 5824 */ 5825 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 5826 { 5827 if (hw->api_maj_ver == ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 5828 if (hw->api_min_ver > ICE_FW_API_REPORT_DFLT_CFG_MIN) 5829 return true; 5830 if (hw->api_min_ver == ICE_FW_API_REPORT_DFLT_CFG_MIN && 5831 hw->api_patch >= ICE_FW_API_REPORT_DFLT_CFG_PATCH) 5832 return true; 5833 } else if (hw->api_maj_ver > ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 5834 return true; 5835 } 5836 return false; 5837 } 5838