1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #include "ice_common.h" 6 #include "ice_sched.h" 7 #include "ice_adminq_cmd.h" 8 9 #include "ice_flow.h" 10 #include "ice_switch.h" 11 12 #define ICE_PF_RESET_WAIT_COUNT 300 13 14 /** 15 * ice_set_mac_type - Sets MAC type 16 * @hw: pointer to the HW structure 17 * 18 * This function sets the MAC type of the adapter based on the 19 * vendor ID and device ID stored in the HW structure. 20 */ 21 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 22 { 23 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 24 25 if (hw->vendor_id != ICE_INTEL_VENDOR_ID) 26 return ICE_ERR_DEVICE_NOT_SUPPORTED; 27 28 switch (hw->device_id) { 29 case ICE_DEV_ID_E810C_BACKPLANE: 30 case ICE_DEV_ID_E810C_QSFP: 31 case ICE_DEV_ID_E810C_SFP: 32 case ICE_DEV_ID_E810_XXV_BACKPLANE: 33 case ICE_DEV_ID_E810_XXV_QSFP: 34 case ICE_DEV_ID_E810_XXV_SFP: 35 hw->mac_type = ICE_MAC_E810; 36 break; 37 case ICE_DEV_ID_E822C_10G_BASE_T: 38 case ICE_DEV_ID_E822C_BACKPLANE: 39 case ICE_DEV_ID_E822C_QSFP: 40 case ICE_DEV_ID_E822C_SFP: 41 case ICE_DEV_ID_E822C_SGMII: 42 case ICE_DEV_ID_E822L_10G_BASE_T: 43 case ICE_DEV_ID_E822L_BACKPLANE: 44 case ICE_DEV_ID_E822L_SFP: 45 case ICE_DEV_ID_E822L_SGMII: 46 case ICE_DEV_ID_E823L_10G_BASE_T: 47 case ICE_DEV_ID_E823L_1GBE: 48 case ICE_DEV_ID_E823L_BACKPLANE: 49 case ICE_DEV_ID_E823L_QSFP: 50 case ICE_DEV_ID_E823L_SFP: 51 hw->mac_type = ICE_MAC_GENERIC; 52 break; 53 default: 54 hw->mac_type = ICE_MAC_UNKNOWN; 55 break; 56 } 57 58 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 59 return ICE_SUCCESS; 60 } 61 62 /** 63 * ice_clear_pf_cfg - Clear PF configuration 64 * @hw: pointer to the hardware structure 65 * 66 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 67 * configuration, flow director filters, etc.). 68 */ 69 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 70 { 71 struct ice_aq_desc desc; 72 73 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 74 75 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 76 } 77 78 /** 79 * ice_aq_manage_mac_read - manage MAC address read command 80 * @hw: pointer to the HW struct 81 * @buf: a virtual buffer to hold the manage MAC read response 82 * @buf_size: Size of the virtual buffer 83 * @cd: pointer to command details structure or NULL 84 * 85 * This function is used to return per PF station MAC address (0x0107). 86 * NOTE: Upon successful completion of this command, MAC address information 87 * is returned in user specified buffer. Please interpret user specified 88 * buffer as "manage_mac_read" response. 89 * Response such as various MAC addresses are stored in HW struct (port.mac) 90 * ice_aq_discover_caps is expected to be called before this function is called. 91 */ 92 static enum ice_status 93 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 94 struct ice_sq_cd *cd) 95 { 96 struct ice_aqc_manage_mac_read_resp *resp; 97 struct ice_aqc_manage_mac_read *cmd; 98 struct ice_aq_desc desc; 99 enum ice_status status; 100 u16 flags; 101 u8 i; 102 103 cmd = &desc.params.mac_read; 104 105 if (buf_size < sizeof(*resp)) 106 return ICE_ERR_BUF_TOO_SHORT; 107 108 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 109 110 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 111 if (status) 112 return status; 113 114 resp = (struct ice_aqc_manage_mac_read_resp *)buf; 115 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 116 117 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 118 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 119 return ICE_ERR_CFG; 120 } 121 122 /* A single port can report up to two (LAN and WoL) addresses */ 123 for (i = 0; i < cmd->num_addr; i++) 124 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 125 ice_memcpy(hw->port_info->mac.lan_addr, 126 resp[i].mac_addr, ETH_ALEN, 127 ICE_DMA_TO_NONDMA); 128 ice_memcpy(hw->port_info->mac.perm_addr, 129 resp[i].mac_addr, 130 ETH_ALEN, ICE_DMA_TO_NONDMA); 131 break; 132 } 133 return ICE_SUCCESS; 134 } 135 136 /** 137 * ice_aq_get_phy_caps - returns PHY capabilities 138 * @pi: port information structure 139 * @qual_mods: report qualified modules 140 * @report_mode: report mode capabilities 141 * @pcaps: structure for PHY capabilities to be filled 142 * @cd: pointer to command details structure or NULL 143 * 144 * Returns the various PHY capabilities supported on the Port (0x0600) 145 */ 146 enum ice_status 147 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 148 struct ice_aqc_get_phy_caps_data *pcaps, 149 struct ice_sq_cd *cd) 150 { 151 struct ice_aqc_get_phy_caps *cmd; 152 u16 pcaps_size = sizeof(*pcaps); 153 struct ice_aq_desc desc; 154 enum ice_status status; 155 struct ice_hw *hw; 156 157 cmd = &desc.params.get_phy; 158 159 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 160 return ICE_ERR_PARAM; 161 hw = pi->hw; 162 163 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 164 165 if (qual_mods) 166 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM); 167 168 cmd->param0 |= CPU_TO_LE16(report_mode); 169 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 170 171 ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n", 172 report_mode); 173 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 174 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_low)); 175 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 176 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_high)); 177 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps); 178 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 179 pcaps->low_power_ctrl_an); 180 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap); 181 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", 182 pcaps->eeer_value); 183 ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n", 184 pcaps->link_fec_options); 185 ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n", 186 pcaps->module_compliance_enforcement); 187 ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n", 188 pcaps->extended_compliance_code); 189 ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n", 190 pcaps->module_type[0]); 191 ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n", 192 pcaps->module_type[1]); 193 ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n", 194 pcaps->module_type[2]); 195 196 197 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) { 198 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low); 199 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high); 200 ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 201 sizeof(pi->phy.link_info.module_type), 202 ICE_NONDMA_TO_NONDMA); 203 204 } 205 206 return status; 207 } 208 209 /** 210 * ice_aq_get_link_topo_handle - get link topology node return status 211 * @pi: port information structure 212 * @node_type: requested node type 213 * @cd: pointer to command details structure or NULL 214 * 215 * Get link topology node return status for specified node type (0x06E0) 216 * 217 * Node type cage can be used to determine if cage is present. If AQC 218 * returns error (ENOENT), then no cage present. If no cage present, then 219 * connection type is backplane or BASE-T. 220 */ 221 static enum ice_status 222 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 223 struct ice_sq_cd *cd) 224 { 225 struct ice_aqc_get_link_topo *cmd; 226 struct ice_aq_desc desc; 227 228 cmd = &desc.params.get_link_topo; 229 230 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 231 232 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 233 ICE_AQC_LINK_TOPO_NODE_CTX_S); 234 235 /* set node type */ 236 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 237 238 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 239 } 240 241 /** 242 * ice_is_media_cage_present 243 * @pi: port information structure 244 * 245 * Returns true if media cage is present, else false. If no cage, then 246 * media type is backplane or BASE-T. 247 */ 248 static bool ice_is_media_cage_present(struct ice_port_info *pi) 249 { 250 /* Node type cage can be used to determine if cage is present. If AQC 251 * returns error (ENOENT), then no cage present. If no cage present then 252 * connection type is backplane or BASE-T. 253 */ 254 return !ice_aq_get_link_topo_handle(pi, 255 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 256 NULL); 257 } 258 259 /** 260 * ice_get_media_type - Gets media type 261 * @pi: port information structure 262 */ 263 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 264 { 265 struct ice_link_status *hw_link_info; 266 267 if (!pi) 268 return ICE_MEDIA_UNKNOWN; 269 270 hw_link_info = &pi->phy.link_info; 271 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 272 /* If more than one media type is selected, report unknown */ 273 return ICE_MEDIA_UNKNOWN; 274 275 if (hw_link_info->phy_type_low) { 276 /* 1G SGMII is a special case where some DA cable PHYs 277 * may show this as an option when it really shouldn't 278 * be since SGMII is meant to be between a MAC and a PHY 279 * in a backplane. Try to detect this case and handle it 280 */ 281 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 282 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 283 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 284 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 285 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 286 return ICE_MEDIA_DA; 287 288 switch (hw_link_info->phy_type_low) { 289 case ICE_PHY_TYPE_LOW_1000BASE_SX: 290 case ICE_PHY_TYPE_LOW_1000BASE_LX: 291 case ICE_PHY_TYPE_LOW_10GBASE_SR: 292 case ICE_PHY_TYPE_LOW_10GBASE_LR: 293 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 294 case ICE_PHY_TYPE_LOW_25GBASE_SR: 295 case ICE_PHY_TYPE_LOW_25GBASE_LR: 296 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 297 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 298 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 299 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 300 case ICE_PHY_TYPE_LOW_50GBASE_SR: 301 case ICE_PHY_TYPE_LOW_50GBASE_FR: 302 case ICE_PHY_TYPE_LOW_50GBASE_LR: 303 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 304 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 305 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 306 case ICE_PHY_TYPE_LOW_100GBASE_DR: 307 return ICE_MEDIA_FIBER; 308 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 309 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 310 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 311 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 312 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 313 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 314 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 315 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 316 return ICE_MEDIA_FIBER; 317 case ICE_PHY_TYPE_LOW_100BASE_TX: 318 case ICE_PHY_TYPE_LOW_1000BASE_T: 319 case ICE_PHY_TYPE_LOW_2500BASE_T: 320 case ICE_PHY_TYPE_LOW_5GBASE_T: 321 case ICE_PHY_TYPE_LOW_10GBASE_T: 322 case ICE_PHY_TYPE_LOW_25GBASE_T: 323 return ICE_MEDIA_BASET; 324 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 325 case ICE_PHY_TYPE_LOW_25GBASE_CR: 326 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 327 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 328 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 329 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 330 case ICE_PHY_TYPE_LOW_50GBASE_CP: 331 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 332 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 333 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 334 return ICE_MEDIA_DA; 335 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 336 case ICE_PHY_TYPE_LOW_40G_XLAUI: 337 case ICE_PHY_TYPE_LOW_50G_LAUI2: 338 case ICE_PHY_TYPE_LOW_50G_AUI2: 339 case ICE_PHY_TYPE_LOW_50G_AUI1: 340 case ICE_PHY_TYPE_LOW_100G_AUI4: 341 case ICE_PHY_TYPE_LOW_100G_CAUI4: 342 if (ice_is_media_cage_present(pi)) 343 return ICE_MEDIA_AUI; 344 /* fall-through */ 345 case ICE_PHY_TYPE_LOW_1000BASE_KX: 346 case ICE_PHY_TYPE_LOW_2500BASE_KX: 347 case ICE_PHY_TYPE_LOW_2500BASE_X: 348 case ICE_PHY_TYPE_LOW_5GBASE_KR: 349 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 350 case ICE_PHY_TYPE_LOW_25GBASE_KR: 351 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 352 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 353 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 354 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 355 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 356 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 357 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 358 return ICE_MEDIA_BACKPLANE; 359 } 360 } else { 361 switch (hw_link_info->phy_type_high) { 362 case ICE_PHY_TYPE_HIGH_100G_AUI2: 363 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 364 if (ice_is_media_cage_present(pi)) 365 return ICE_MEDIA_AUI; 366 /* fall-through */ 367 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 368 return ICE_MEDIA_BACKPLANE; 369 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 370 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 371 return ICE_MEDIA_FIBER; 372 } 373 } 374 return ICE_MEDIA_UNKNOWN; 375 } 376 377 /** 378 * ice_aq_get_link_info 379 * @pi: port information structure 380 * @ena_lse: enable/disable LinkStatusEvent reporting 381 * @link: pointer to link status structure - optional 382 * @cd: pointer to command details structure or NULL 383 * 384 * Get Link Status (0x607). Returns the link status of the adapter. 385 */ 386 enum ice_status 387 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 388 struct ice_link_status *link, struct ice_sq_cd *cd) 389 { 390 struct ice_aqc_get_link_status_data link_data = { 0 }; 391 struct ice_aqc_get_link_status *resp; 392 struct ice_link_status *li_old, *li; 393 enum ice_media_type *hw_media_type; 394 struct ice_fc_info *hw_fc_info; 395 bool tx_pause, rx_pause; 396 struct ice_aq_desc desc; 397 enum ice_status status; 398 struct ice_hw *hw; 399 u16 cmd_flags; 400 401 if (!pi) 402 return ICE_ERR_PARAM; 403 hw = pi->hw; 404 li_old = &pi->phy.link_info_old; 405 hw_media_type = &pi->phy.media_type; 406 li = &pi->phy.link_info; 407 hw_fc_info = &pi->fc; 408 409 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 410 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 411 resp = &desc.params.get_link_status; 412 resp->cmd_flags = CPU_TO_LE16(cmd_flags); 413 resp->lport_num = pi->lport; 414 415 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 416 417 if (status != ICE_SUCCESS) 418 return status; 419 420 /* save off old link status information */ 421 *li_old = *li; 422 423 /* update current link status information */ 424 li->link_speed = LE16_TO_CPU(link_data.link_speed); 425 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low); 426 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high); 427 *hw_media_type = ice_get_media_type(pi); 428 li->link_info = link_data.link_info; 429 li->an_info = link_data.an_info; 430 li->ext_info = link_data.ext_info; 431 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size); 432 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 433 li->topo_media_conflict = link_data.topo_media_conflict; 434 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 435 ICE_AQ_CFG_PACING_TYPE_M); 436 437 /* update fc info */ 438 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 439 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 440 if (tx_pause && rx_pause) 441 hw_fc_info->current_mode = ICE_FC_FULL; 442 else if (tx_pause) 443 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 444 else if (rx_pause) 445 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 446 else 447 hw_fc_info->current_mode = ICE_FC_NONE; 448 449 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED)); 450 451 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 452 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 453 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 454 (unsigned long long)li->phy_type_low); 455 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 456 (unsigned long long)li->phy_type_high); 457 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 458 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 459 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 460 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 461 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 462 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 463 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 464 li->max_frame_size); 465 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 466 467 /* save link status information */ 468 if (link) 469 *link = *li; 470 471 /* flag cleared so calling functions don't call AQ again */ 472 pi->phy.get_link_info = false; 473 474 return ICE_SUCCESS; 475 } 476 477 /** 478 * ice_fill_tx_timer_and_fc_thresh 479 * @hw: pointer to the HW struct 480 * @cmd: pointer to MAC cfg structure 481 * 482 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 483 * descriptor 484 */ 485 static void 486 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 487 struct ice_aqc_set_mac_cfg *cmd) 488 { 489 u16 fc_thres_val, tx_timer_val; 490 u32 val; 491 492 /* We read back the transmit timer and fc threshold value of 493 * LFC. Thus, we will use index = 494 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 495 * 496 * Also, because we are opearating on transmit timer and fc 497 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 498 */ 499 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 500 501 /* Retrieve the transmit timer */ 502 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 503 tx_timer_val = val & 504 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 505 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val); 506 507 /* Retrieve the fc threshold */ 508 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 509 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 510 511 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val); 512 } 513 514 /** 515 * ice_aq_set_mac_cfg 516 * @hw: pointer to the HW struct 517 * @max_frame_size: Maximum Frame Size to be supported 518 * @cd: pointer to command details structure or NULL 519 * 520 * Set MAC configuration (0x0603) 521 */ 522 enum ice_status 523 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 524 { 525 struct ice_aqc_set_mac_cfg *cmd; 526 struct ice_aq_desc desc; 527 528 cmd = &desc.params.set_mac_cfg; 529 530 if (max_frame_size == 0) 531 return ICE_ERR_PARAM; 532 533 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 534 535 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 536 537 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 538 539 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 540 } 541 542 /** 543 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 544 * @hw: pointer to the HW struct 545 */ 546 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 547 { 548 struct ice_switch_info *sw; 549 enum ice_status status; 550 551 hw->switch_info = (struct ice_switch_info *) 552 ice_malloc(hw, sizeof(*hw->switch_info)); 553 554 sw = hw->switch_info; 555 556 if (!sw) 557 return ICE_ERR_NO_MEMORY; 558 559 INIT_LIST_HEAD(&sw->vsi_list_map_head); 560 sw->prof_res_bm_init = 0; 561 562 status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list); 563 if (status) { 564 ice_free(hw, hw->switch_info); 565 return status; 566 } 567 return ICE_SUCCESS; 568 } 569 570 /** 571 * ice_cleanup_fltr_mgmt_single - clears single filter mngt struct 572 * @hw: pointer to the HW struct 573 * @sw: pointer to switch info struct for which function clears filters 574 */ 575 static void 576 ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw) 577 { 578 struct ice_vsi_list_map_info *v_pos_map; 579 struct ice_vsi_list_map_info *v_tmp_map; 580 struct ice_sw_recipe *recps; 581 u8 i; 582 583 if (!sw) 584 return; 585 586 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 587 ice_vsi_list_map_info, list_entry) { 588 LIST_DEL(&v_pos_map->list_entry); 589 ice_free(hw, v_pos_map); 590 } 591 recps = sw->recp_list; 592 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 593 struct ice_recp_grp_entry *rg_entry, *tmprg_entry; 594 595 recps[i].root_rid = i; 596 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry, 597 &recps[i].rg_list, ice_recp_grp_entry, 598 l_entry) { 599 LIST_DEL(&rg_entry->l_entry); 600 ice_free(hw, rg_entry); 601 } 602 603 if (recps[i].adv_rule) { 604 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 605 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 606 607 ice_destroy_lock(&recps[i].filt_rule_lock); 608 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 609 &recps[i].filt_rules, 610 ice_adv_fltr_mgmt_list_entry, 611 list_entry) { 612 LIST_DEL(&lst_itr->list_entry); 613 ice_free(hw, lst_itr->lkups); 614 ice_free(hw, lst_itr); 615 } 616 } else { 617 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 618 619 ice_destroy_lock(&recps[i].filt_rule_lock); 620 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 621 &recps[i].filt_rules, 622 ice_fltr_mgmt_list_entry, 623 list_entry) { 624 LIST_DEL(&lst_itr->list_entry); 625 ice_free(hw, lst_itr); 626 } 627 } 628 if (recps[i].root_buf) 629 ice_free(hw, recps[i].root_buf); 630 } 631 ice_rm_sw_replay_rule_info(hw, sw); 632 ice_free(hw, sw->recp_list); 633 ice_free(hw, sw); 634 } 635 636 /** 637 * ice_cleanup_all_fltr_mgmt - cleanup filter management list and locks 638 * @hw: pointer to the HW struct 639 */ 640 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 641 { 642 ice_cleanup_fltr_mgmt_single(hw, hw->switch_info); 643 } 644 645 /** 646 * ice_get_itr_intrl_gran 647 * @hw: pointer to the HW struct 648 * 649 * Determines the ITR/INTRL granularities based on the maximum aggregate 650 * bandwidth according to the device's configuration during power-on. 651 */ 652 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 653 { 654 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 655 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 656 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 657 658 switch (max_agg_bw) { 659 case ICE_MAX_AGG_BW_200G: 660 case ICE_MAX_AGG_BW_100G: 661 case ICE_MAX_AGG_BW_50G: 662 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 663 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 664 break; 665 case ICE_MAX_AGG_BW_25G: 666 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 667 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 668 break; 669 } 670 } 671 672 /** 673 * ice_print_rollback_msg - print FW rollback message 674 * @hw: pointer to the hardware structure 675 */ 676 void ice_print_rollback_msg(struct ice_hw *hw) 677 { 678 char nvm_str[ICE_NVM_VER_LEN] = { 0 }; 679 struct ice_nvm_info *nvm = &hw->nvm; 680 struct ice_orom_info *orom; 681 682 orom = &nvm->orom; 683 684 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", 685 nvm->major_ver, nvm->minor_ver, nvm->eetrack, orom->major, 686 orom->build, orom->patch); 687 ice_warn(hw, 688 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n", 689 nvm_str, hw->fw_maj_ver, hw->fw_min_ver); 690 } 691 692 /** 693 * ice_init_hw - main hardware initialization routine 694 * @hw: pointer to the hardware structure 695 */ 696 enum ice_status ice_init_hw(struct ice_hw *hw) 697 { 698 struct ice_aqc_get_phy_caps_data *pcaps; 699 enum ice_status status; 700 u16 mac_buf_len; 701 void *mac_buf; 702 703 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 704 705 /* Set MAC type based on DeviceID */ 706 status = ice_set_mac_type(hw); 707 if (status) 708 return status; 709 710 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 711 PF_FUNC_RID_FUNCTION_NUMBER_M) >> 712 PF_FUNC_RID_FUNCTION_NUMBER_S; 713 714 status = ice_reset(hw, ICE_RESET_PFR); 715 if (status) 716 return status; 717 718 ice_get_itr_intrl_gran(hw); 719 720 status = ice_create_all_ctrlq(hw); 721 if (status) 722 goto err_unroll_cqinit; 723 724 status = ice_init_nvm(hw); 725 if (status) 726 goto err_unroll_cqinit; 727 728 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK) 729 ice_print_rollback_msg(hw); 730 731 status = ice_clear_pf_cfg(hw); 732 if (status) 733 goto err_unroll_cqinit; 734 735 /* Set bit to enable Flow Director filters */ 736 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 737 INIT_LIST_HEAD(&hw->fdir_list_head); 738 739 ice_clear_pxe_mode(hw); 740 741 status = ice_get_caps(hw); 742 if (status) 743 goto err_unroll_cqinit; 744 745 hw->port_info = (struct ice_port_info *) 746 ice_malloc(hw, sizeof(*hw->port_info)); 747 if (!hw->port_info) { 748 status = ICE_ERR_NO_MEMORY; 749 goto err_unroll_cqinit; 750 } 751 752 /* set the back pointer to HW */ 753 hw->port_info->hw = hw; 754 755 /* Initialize port_info struct with switch configuration data */ 756 status = ice_get_initial_sw_cfg(hw); 757 if (status) 758 goto err_unroll_alloc; 759 760 hw->evb_veb = true; 761 /* Query the allocated resources for Tx scheduler */ 762 status = ice_sched_query_res_alloc(hw); 763 if (status) { 764 ice_debug(hw, ICE_DBG_SCHED, 765 "Failed to get scheduler allocated resources\n"); 766 goto err_unroll_alloc; 767 } 768 ice_sched_get_psm_clk_freq(hw); 769 770 /* Initialize port_info struct with scheduler data */ 771 status = ice_sched_init_port(hw->port_info); 772 if (status) 773 goto err_unroll_sched; 774 775 pcaps = (struct ice_aqc_get_phy_caps_data *) 776 ice_malloc(hw, sizeof(*pcaps)); 777 if (!pcaps) { 778 status = ICE_ERR_NO_MEMORY; 779 goto err_unroll_sched; 780 } 781 782 /* Initialize port_info struct with PHY capabilities */ 783 status = ice_aq_get_phy_caps(hw->port_info, false, 784 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); 785 ice_free(hw, pcaps); 786 if (status) 787 goto err_unroll_sched; 788 789 /* Initialize port_info struct with link information */ 790 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 791 if (status) 792 goto err_unroll_sched; 793 /* need a valid SW entry point to build a Tx tree */ 794 if (!hw->sw_entry_point_layer) { 795 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 796 status = ICE_ERR_CFG; 797 goto err_unroll_sched; 798 } 799 INIT_LIST_HEAD(&hw->agg_list); 800 /* Initialize max burst size */ 801 if (!hw->max_burst_size) 802 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 803 status = ice_init_fltr_mgmt_struct(hw); 804 if (status) 805 goto err_unroll_sched; 806 807 /* Get MAC information */ 808 /* A single port can report up to two (LAN and WoL) addresses */ 809 mac_buf = ice_calloc(hw, 2, 810 sizeof(struct ice_aqc_manage_mac_read_resp)); 811 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 812 813 if (!mac_buf) { 814 status = ICE_ERR_NO_MEMORY; 815 goto err_unroll_fltr_mgmt_struct; 816 } 817 818 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 819 ice_free(hw, mac_buf); 820 821 if (status) 822 goto err_unroll_fltr_mgmt_struct; 823 /* enable jumbo frame support at MAC level */ 824 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 825 if (status) 826 goto err_unroll_fltr_mgmt_struct; 827 /* Obtain counter base index which would be used by flow director */ 828 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 829 if (status) 830 goto err_unroll_fltr_mgmt_struct; 831 status = ice_init_hw_tbls(hw); 832 if (status) 833 goto err_unroll_fltr_mgmt_struct; 834 ice_init_lock(&hw->tnl_lock); 835 return ICE_SUCCESS; 836 837 err_unroll_fltr_mgmt_struct: 838 ice_cleanup_fltr_mgmt_struct(hw); 839 err_unroll_sched: 840 ice_sched_cleanup_all(hw); 841 err_unroll_alloc: 842 ice_free(hw, hw->port_info); 843 hw->port_info = NULL; 844 err_unroll_cqinit: 845 ice_destroy_all_ctrlq(hw); 846 return status; 847 } 848 849 /** 850 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 851 * @hw: pointer to the hardware structure 852 * 853 * This should be called only during nominal operation, not as a result of 854 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 855 * applicable initializations if it fails for any reason. 856 */ 857 void ice_deinit_hw(struct ice_hw *hw) 858 { 859 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 860 ice_cleanup_fltr_mgmt_struct(hw); 861 862 ice_sched_cleanup_all(hw); 863 ice_sched_clear_agg(hw); 864 ice_free_seg(hw); 865 ice_free_hw_tbls(hw); 866 ice_destroy_lock(&hw->tnl_lock); 867 868 if (hw->port_info) { 869 ice_free(hw, hw->port_info); 870 hw->port_info = NULL; 871 } 872 873 ice_destroy_all_ctrlq(hw); 874 875 /* Clear VSI contexts if not already cleared */ 876 ice_clear_all_vsi_ctx(hw); 877 } 878 879 /** 880 * ice_check_reset - Check to see if a global reset is complete 881 * @hw: pointer to the hardware structure 882 */ 883 enum ice_status ice_check_reset(struct ice_hw *hw) 884 { 885 u32 cnt, reg = 0, grst_timeout, uld_mask; 886 887 /* Poll for Device Active state in case a recent CORER, GLOBR, 888 * or EMPR has occurred. The grst delay value is in 100ms units. 889 * Add 1sec for outstanding AQ commands that can take a long time. 890 */ 891 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 892 GLGEN_RSTCTL_GRSTDEL_S) + 10; 893 894 for (cnt = 0; cnt < grst_timeout; cnt++) { 895 ice_msec_delay(100, true); 896 reg = rd32(hw, GLGEN_RSTAT); 897 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 898 break; 899 } 900 901 if (cnt == grst_timeout) { 902 ice_debug(hw, ICE_DBG_INIT, 903 "Global reset polling failed to complete.\n"); 904 return ICE_ERR_RESET_FAILED; 905 } 906 907 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 908 GLNVM_ULD_PCIER_DONE_1_M |\ 909 GLNVM_ULD_CORER_DONE_M |\ 910 GLNVM_ULD_GLOBR_DONE_M |\ 911 GLNVM_ULD_POR_DONE_M |\ 912 GLNVM_ULD_POR_DONE_1_M |\ 913 GLNVM_ULD_PCIER_DONE_2_M) 914 915 uld_mask = ICE_RESET_DONE_MASK; 916 917 /* Device is Active; check Global Reset processes are done */ 918 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 919 reg = rd32(hw, GLNVM_ULD) & uld_mask; 920 if (reg == uld_mask) { 921 ice_debug(hw, ICE_DBG_INIT, 922 "Global reset processes done. %d\n", cnt); 923 break; 924 } 925 ice_msec_delay(10, true); 926 } 927 928 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 929 ice_debug(hw, ICE_DBG_INIT, 930 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 931 reg); 932 return ICE_ERR_RESET_FAILED; 933 } 934 935 return ICE_SUCCESS; 936 } 937 938 /** 939 * ice_pf_reset - Reset the PF 940 * @hw: pointer to the hardware structure 941 * 942 * If a global reset has been triggered, this function checks 943 * for its completion and then issues the PF reset 944 */ 945 static enum ice_status ice_pf_reset(struct ice_hw *hw) 946 { 947 u32 cnt, reg; 948 949 /* If at function entry a global reset was already in progress, i.e. 950 * state is not 'device active' or any of the reset done bits are not 951 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 952 * global reset is done. 953 */ 954 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 955 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 956 /* poll on global reset currently in progress until done */ 957 if (ice_check_reset(hw)) 958 return ICE_ERR_RESET_FAILED; 959 960 return ICE_SUCCESS; 961 } 962 963 /* Reset the PF */ 964 reg = rd32(hw, PFGEN_CTRL); 965 966 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 967 968 /* Wait for the PFR to complete. The wait time is the global config lock 969 * timeout plus the PFR timeout which will account for a possible reset 970 * that is occurring during a download package operation. 971 */ 972 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 973 ICE_PF_RESET_WAIT_COUNT; cnt++) { 974 reg = rd32(hw, PFGEN_CTRL); 975 if (!(reg & PFGEN_CTRL_PFSWR_M)) 976 break; 977 978 ice_msec_delay(1, true); 979 } 980 981 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 982 ice_debug(hw, ICE_DBG_INIT, 983 "PF reset polling failed to complete.\n"); 984 return ICE_ERR_RESET_FAILED; 985 } 986 987 return ICE_SUCCESS; 988 } 989 990 /** 991 * ice_reset - Perform different types of reset 992 * @hw: pointer to the hardware structure 993 * @req: reset request 994 * 995 * This function triggers a reset as specified by the req parameter. 996 * 997 * Note: 998 * If anything other than a PF reset is triggered, PXE mode is restored. 999 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1000 * interface has been restored in the rebuild flow. 1001 */ 1002 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1003 { 1004 u32 val = 0; 1005 1006 switch (req) { 1007 case ICE_RESET_PFR: 1008 return ice_pf_reset(hw); 1009 case ICE_RESET_CORER: 1010 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1011 val = GLGEN_RTRIG_CORER_M; 1012 break; 1013 case ICE_RESET_GLOBR: 1014 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1015 val = GLGEN_RTRIG_GLOBR_M; 1016 break; 1017 default: 1018 return ICE_ERR_PARAM; 1019 } 1020 1021 val |= rd32(hw, GLGEN_RTRIG); 1022 wr32(hw, GLGEN_RTRIG, val); 1023 ice_flush(hw); 1024 1025 /* wait for the FW to be ready */ 1026 return ice_check_reset(hw); 1027 } 1028 1029 /** 1030 * ice_copy_rxq_ctx_to_hw 1031 * @hw: pointer to the hardware structure 1032 * @ice_rxq_ctx: pointer to the rxq context 1033 * @rxq_index: the index of the Rx queue 1034 * 1035 * Copies rxq context from dense structure to HW register space 1036 */ 1037 static enum ice_status 1038 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1039 { 1040 u8 i; 1041 1042 if (!ice_rxq_ctx) 1043 return ICE_ERR_BAD_PTR; 1044 1045 if (rxq_index > QRX_CTRL_MAX_INDEX) 1046 return ICE_ERR_PARAM; 1047 1048 /* Copy each dword separately to HW */ 1049 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1050 wr32(hw, QRX_CONTEXT(i, rxq_index), 1051 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1052 1053 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1054 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1055 } 1056 1057 return ICE_SUCCESS; 1058 } 1059 1060 /* LAN Rx Queue Context */ 1061 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1062 /* Field Width LSB */ 1063 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1064 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1065 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1066 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1067 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1068 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1069 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1070 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1071 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1072 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1073 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1074 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1075 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1076 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1077 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1078 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1079 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1080 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1081 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1082 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1083 { 0 } 1084 }; 1085 1086 /** 1087 * ice_write_rxq_ctx 1088 * @hw: pointer to the hardware structure 1089 * @rlan_ctx: pointer to the rxq context 1090 * @rxq_index: the index of the Rx queue 1091 * 1092 * Converts rxq context from sparse to dense structure and then writes 1093 * it to HW register space and enables the hardware to prefetch descriptors 1094 * instead of only fetching them on demand 1095 */ 1096 enum ice_status 1097 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1098 u32 rxq_index) 1099 { 1100 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1101 1102 if (!rlan_ctx) 1103 return ICE_ERR_BAD_PTR; 1104 1105 rlan_ctx->prefena = 1; 1106 1107 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1108 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1109 } 1110 1111 /** 1112 * ice_clear_rxq_ctx 1113 * @hw: pointer to the hardware structure 1114 * @rxq_index: the index of the Rx queue to clear 1115 * 1116 * Clears rxq context in HW register space 1117 */ 1118 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index) 1119 { 1120 u8 i; 1121 1122 if (rxq_index > QRX_CTRL_MAX_INDEX) 1123 return ICE_ERR_PARAM; 1124 1125 /* Clear each dword register separately */ 1126 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) 1127 wr32(hw, QRX_CONTEXT(i, rxq_index), 0); 1128 1129 return ICE_SUCCESS; 1130 } 1131 1132 /* LAN Tx Queue Context */ 1133 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1134 /* Field Width LSB */ 1135 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1136 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1137 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1138 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1139 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1140 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1141 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1142 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1143 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1144 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1145 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1146 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1147 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1148 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1149 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1150 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1151 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1152 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1153 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1154 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1155 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1156 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1157 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1158 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1159 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1160 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1161 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1162 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1163 { 0 } 1164 }; 1165 1166 /** 1167 * ice_copy_tx_cmpltnq_ctx_to_hw 1168 * @hw: pointer to the hardware structure 1169 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context 1170 * @tx_cmpltnq_index: the index of the completion queue 1171 * 1172 * Copies Tx completion queue context from dense structure to HW register space 1173 */ 1174 static enum ice_status 1175 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx, 1176 u32 tx_cmpltnq_index) 1177 { 1178 u8 i; 1179 1180 if (!ice_tx_cmpltnq_ctx) 1181 return ICE_ERR_BAD_PTR; 1182 1183 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 1184 return ICE_ERR_PARAM; 1185 1186 /* Copy each dword separately to HW */ 1187 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) { 1188 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 1189 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 1190 1191 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i, 1192 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 1193 } 1194 1195 return ICE_SUCCESS; 1196 } 1197 1198 /* LAN Tx Completion Queue Context */ 1199 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = { 1200 /* Field Width LSB */ 1201 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0), 1202 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64), 1203 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96), 1204 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97), 1205 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128), 1206 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131), 1207 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141), 1208 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160), 1209 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161), 1210 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192), 1211 { 0 } 1212 }; 1213 1214 /** 1215 * ice_write_tx_cmpltnq_ctx 1216 * @hw: pointer to the hardware structure 1217 * @tx_cmpltnq_ctx: pointer to the completion queue context 1218 * @tx_cmpltnq_index: the index of the completion queue 1219 * 1220 * Converts completion queue context from sparse to dense structure and then 1221 * writes it to HW register space 1222 */ 1223 enum ice_status 1224 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw, 1225 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx, 1226 u32 tx_cmpltnq_index) 1227 { 1228 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 1229 1230 ice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info); 1231 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index); 1232 } 1233 1234 /** 1235 * ice_clear_tx_cmpltnq_ctx 1236 * @hw: pointer to the hardware structure 1237 * @tx_cmpltnq_index: the index of the completion queue to clear 1238 * 1239 * Clears Tx completion queue context in HW register space 1240 */ 1241 enum ice_status 1242 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index) 1243 { 1244 u8 i; 1245 1246 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 1247 return ICE_ERR_PARAM; 1248 1249 /* Clear each dword register separately */ 1250 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) 1251 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0); 1252 1253 return ICE_SUCCESS; 1254 } 1255 1256 /** 1257 * ice_copy_tx_drbell_q_ctx_to_hw 1258 * @hw: pointer to the hardware structure 1259 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context 1260 * @tx_drbell_q_index: the index of the doorbell queue 1261 * 1262 * Copies doorbell queue context from dense structure to HW register space 1263 */ 1264 static enum ice_status 1265 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx, 1266 u32 tx_drbell_q_index) 1267 { 1268 u8 i; 1269 1270 if (!ice_tx_drbell_q_ctx) 1271 return ICE_ERR_BAD_PTR; 1272 1273 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 1274 return ICE_ERR_PARAM; 1275 1276 /* Copy each dword separately to HW */ 1277 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) { 1278 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 1279 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 1280 1281 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i, 1282 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 1283 } 1284 1285 return ICE_SUCCESS; 1286 } 1287 1288 /* LAN Tx Doorbell Queue Context info */ 1289 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = { 1290 /* Field Width LSB */ 1291 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0), 1292 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64), 1293 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80), 1294 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84), 1295 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94), 1296 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96), 1297 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104), 1298 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108), 1299 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112), 1300 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128), 1301 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144), 1302 { 0 } 1303 }; 1304 1305 /** 1306 * ice_write_tx_drbell_q_ctx 1307 * @hw: pointer to the hardware structure 1308 * @tx_drbell_q_ctx: pointer to the doorbell queue context 1309 * @tx_drbell_q_index: the index of the doorbell queue 1310 * 1311 * Converts doorbell queue context from sparse to dense structure and then 1312 * writes it to HW register space 1313 */ 1314 enum ice_status 1315 ice_write_tx_drbell_q_ctx(struct ice_hw *hw, 1316 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx, 1317 u32 tx_drbell_q_index) 1318 { 1319 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 1320 1321 ice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf, 1322 ice_tx_drbell_q_ctx_info); 1323 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index); 1324 } 1325 1326 /** 1327 * ice_clear_tx_drbell_q_ctx 1328 * @hw: pointer to the hardware structure 1329 * @tx_drbell_q_index: the index of the doorbell queue to clear 1330 * 1331 * Clears doorbell queue context in HW register space 1332 */ 1333 enum ice_status 1334 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index) 1335 { 1336 u8 i; 1337 1338 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 1339 return ICE_ERR_PARAM; 1340 1341 /* Clear each dword register separately */ 1342 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) 1343 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0); 1344 1345 return ICE_SUCCESS; 1346 } 1347 1348 /* FW Admin Queue command wrappers */ 1349 1350 /** 1351 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1352 * @hw: pointer to the HW struct 1353 * @desc: descriptor describing the command 1354 * @buf: buffer to use for indirect commands (NULL for direct commands) 1355 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1356 * @cd: pointer to command details structure 1357 * 1358 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1359 */ 1360 enum ice_status 1361 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1362 u16 buf_size, struct ice_sq_cd *cd) 1363 { 1364 if (hw->aq_send_cmd_fn) { 1365 enum ice_status status = ICE_ERR_NOT_READY; 1366 u16 retval = ICE_AQ_RC_OK; 1367 1368 ice_acquire_lock(&hw->adminq.sq_lock); 1369 if (!hw->aq_send_cmd_fn(hw->aq_send_cmd_param, desc, 1370 buf, buf_size)) { 1371 retval = LE16_TO_CPU(desc->retval); 1372 /* strip off FW internal code */ 1373 if (retval) 1374 retval &= 0xff; 1375 if (retval == ICE_AQ_RC_OK) 1376 status = ICE_SUCCESS; 1377 else 1378 status = ICE_ERR_AQ_ERROR; 1379 } 1380 1381 hw->adminq.sq_last_status = (enum ice_aq_err)retval; 1382 ice_release_lock(&hw->adminq.sq_lock); 1383 1384 return status; 1385 } 1386 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd); 1387 } 1388 1389 /** 1390 * ice_aq_get_fw_ver 1391 * @hw: pointer to the HW struct 1392 * @cd: pointer to command details structure or NULL 1393 * 1394 * Get the firmware version (0x0001) from the admin queue commands 1395 */ 1396 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1397 { 1398 struct ice_aqc_get_ver *resp; 1399 struct ice_aq_desc desc; 1400 enum ice_status status; 1401 1402 resp = &desc.params.get_ver; 1403 1404 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1405 1406 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1407 1408 if (!status) { 1409 hw->fw_branch = resp->fw_branch; 1410 hw->fw_maj_ver = resp->fw_major; 1411 hw->fw_min_ver = resp->fw_minor; 1412 hw->fw_patch = resp->fw_patch; 1413 hw->fw_build = LE32_TO_CPU(resp->fw_build); 1414 hw->api_branch = resp->api_branch; 1415 hw->api_maj_ver = resp->api_major; 1416 hw->api_min_ver = resp->api_minor; 1417 hw->api_patch = resp->api_patch; 1418 } 1419 1420 return status; 1421 } 1422 1423 /** 1424 * ice_aq_send_driver_ver 1425 * @hw: pointer to the HW struct 1426 * @dv: driver's major, minor version 1427 * @cd: pointer to command details structure or NULL 1428 * 1429 * Send the driver version (0x0002) to the firmware 1430 */ 1431 enum ice_status 1432 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1433 struct ice_sq_cd *cd) 1434 { 1435 struct ice_aqc_driver_ver *cmd; 1436 struct ice_aq_desc desc; 1437 u16 len; 1438 1439 cmd = &desc.params.driver_ver; 1440 1441 if (!dv) 1442 return ICE_ERR_PARAM; 1443 1444 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1445 1446 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 1447 cmd->major_ver = dv->major_ver; 1448 cmd->minor_ver = dv->minor_ver; 1449 cmd->build_ver = dv->build_ver; 1450 cmd->subbuild_ver = dv->subbuild_ver; 1451 1452 len = 0; 1453 while (len < sizeof(dv->driver_string) && 1454 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len]) 1455 len++; 1456 1457 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1458 } 1459 1460 /** 1461 * ice_aq_q_shutdown 1462 * @hw: pointer to the HW struct 1463 * @unloading: is the driver unloading itself 1464 * 1465 * Tell the Firmware that we're shutting down the AdminQ and whether 1466 * or not the driver is unloading as well (0x0003). 1467 */ 1468 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1469 { 1470 struct ice_aqc_q_shutdown *cmd; 1471 struct ice_aq_desc desc; 1472 1473 cmd = &desc.params.q_shutdown; 1474 1475 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1476 1477 if (unloading) 1478 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1479 1480 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1481 } 1482 1483 /** 1484 * ice_aq_req_res 1485 * @hw: pointer to the HW struct 1486 * @res: resource ID 1487 * @access: access type 1488 * @sdp_number: resource number 1489 * @timeout: the maximum time in ms that the driver may hold the resource 1490 * @cd: pointer to command details structure or NULL 1491 * 1492 * Requests common resource using the admin queue commands (0x0008). 1493 * When attempting to acquire the Global Config Lock, the driver can 1494 * learn of three states: 1495 * 1) ICE_SUCCESS - acquired lock, and can perform download package 1496 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1497 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1498 * successfully downloaded the package; the driver does 1499 * not have to download the package and can continue 1500 * loading 1501 * 1502 * Note that if the caller is in an acquire lock, perform action, release lock 1503 * phase of operation, it is possible that the FW may detect a timeout and issue 1504 * a CORER. In this case, the driver will receive a CORER interrupt and will 1505 * have to determine its cause. The calling thread that is handling this flow 1506 * will likely get an error propagated back to it indicating the Download 1507 * Package, Update Package or the Release Resource AQ commands timed out. 1508 */ 1509 static enum ice_status 1510 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1511 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1512 struct ice_sq_cd *cd) 1513 { 1514 struct ice_aqc_req_res *cmd_resp; 1515 struct ice_aq_desc desc; 1516 enum ice_status status; 1517 1518 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1519 1520 cmd_resp = &desc.params.res_owner; 1521 1522 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1523 1524 cmd_resp->res_id = CPU_TO_LE16(res); 1525 cmd_resp->access_type = CPU_TO_LE16(access); 1526 cmd_resp->res_number = CPU_TO_LE32(sdp_number); 1527 cmd_resp->timeout = CPU_TO_LE32(*timeout); 1528 *timeout = 0; 1529 1530 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1531 1532 /* The completion specifies the maximum time in ms that the driver 1533 * may hold the resource in the Timeout field. 1534 */ 1535 1536 /* Global config lock response utilizes an additional status field. 1537 * 1538 * If the Global config lock resource is held by some other driver, the 1539 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1540 * and the timeout field indicates the maximum time the current owner 1541 * of the resource has to free it. 1542 */ 1543 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1544 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1545 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1546 return ICE_SUCCESS; 1547 } else if (LE16_TO_CPU(cmd_resp->status) == 1548 ICE_AQ_RES_GLBL_IN_PROG) { 1549 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1550 return ICE_ERR_AQ_ERROR; 1551 } else if (LE16_TO_CPU(cmd_resp->status) == 1552 ICE_AQ_RES_GLBL_DONE) { 1553 return ICE_ERR_AQ_NO_WORK; 1554 } 1555 1556 /* invalid FW response, force a timeout immediately */ 1557 *timeout = 0; 1558 return ICE_ERR_AQ_ERROR; 1559 } 1560 1561 /* If the resource is held by some other driver, the command completes 1562 * with a busy return value and the timeout field indicates the maximum 1563 * time the current owner of the resource has to free it. 1564 */ 1565 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1566 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1567 1568 return status; 1569 } 1570 1571 /** 1572 * ice_aq_release_res 1573 * @hw: pointer to the HW struct 1574 * @res: resource ID 1575 * @sdp_number: resource number 1576 * @cd: pointer to command details structure or NULL 1577 * 1578 * release common resource using the admin queue commands (0x0009) 1579 */ 1580 static enum ice_status 1581 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1582 struct ice_sq_cd *cd) 1583 { 1584 struct ice_aqc_req_res *cmd; 1585 struct ice_aq_desc desc; 1586 1587 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1588 1589 cmd = &desc.params.res_owner; 1590 1591 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1592 1593 cmd->res_id = CPU_TO_LE16(res); 1594 cmd->res_number = CPU_TO_LE32(sdp_number); 1595 1596 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1597 } 1598 1599 /** 1600 * ice_acquire_res 1601 * @hw: pointer to the HW structure 1602 * @res: resource ID 1603 * @access: access type (read or write) 1604 * @timeout: timeout in milliseconds 1605 * 1606 * This function will attempt to acquire the ownership of a resource. 1607 */ 1608 enum ice_status 1609 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1610 enum ice_aq_res_access_type access, u32 timeout) 1611 { 1612 #define ICE_RES_POLLING_DELAY_MS 10 1613 u32 delay = ICE_RES_POLLING_DELAY_MS; 1614 u32 time_left = timeout; 1615 enum ice_status status; 1616 1617 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1618 1619 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1620 1621 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 1622 * previously acquired the resource and performed any necessary updates; 1623 * in this case the caller does not obtain the resource and has no 1624 * further work to do. 1625 */ 1626 if (status == ICE_ERR_AQ_NO_WORK) 1627 goto ice_acquire_res_exit; 1628 1629 if (status) 1630 ice_debug(hw, ICE_DBG_RES, 1631 "resource %d acquire type %d failed.\n", res, access); 1632 1633 /* If necessary, poll until the current lock owner timeouts */ 1634 timeout = time_left; 1635 while (status && timeout && time_left) { 1636 ice_msec_delay(delay, true); 1637 timeout = (timeout > delay) ? timeout - delay : 0; 1638 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1639 1640 if (status == ICE_ERR_AQ_NO_WORK) 1641 /* lock free, but no work to do */ 1642 break; 1643 1644 if (!status) 1645 /* lock acquired */ 1646 break; 1647 } 1648 if (status && status != ICE_ERR_AQ_NO_WORK) 1649 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1650 1651 ice_acquire_res_exit: 1652 if (status == ICE_ERR_AQ_NO_WORK) { 1653 if (access == ICE_RES_WRITE) 1654 ice_debug(hw, ICE_DBG_RES, 1655 "resource indicates no work to do.\n"); 1656 else 1657 ice_debug(hw, ICE_DBG_RES, 1658 "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1659 } 1660 return status; 1661 } 1662 1663 /** 1664 * ice_release_res 1665 * @hw: pointer to the HW structure 1666 * @res: resource ID 1667 * 1668 * This function will release a resource using the proper Admin Command. 1669 */ 1670 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1671 { 1672 enum ice_status status; 1673 u32 total_delay = 0; 1674 1675 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1676 1677 status = ice_aq_release_res(hw, res, 0, NULL); 1678 1679 /* there are some rare cases when trying to release the resource 1680 * results in an admin queue timeout, so handle them correctly 1681 */ 1682 while ((status == ICE_ERR_AQ_TIMEOUT) && 1683 (total_delay < hw->adminq.sq_cmd_timeout)) { 1684 ice_msec_delay(1, true); 1685 status = ice_aq_release_res(hw, res, 0, NULL); 1686 total_delay++; 1687 } 1688 } 1689 1690 /** 1691 * ice_aq_alloc_free_res - command to allocate/free resources 1692 * @hw: pointer to the HW struct 1693 * @num_entries: number of resource entries in buffer 1694 * @buf: Indirect buffer to hold data parameters and response 1695 * @buf_size: size of buffer for indirect commands 1696 * @opc: pass in the command opcode 1697 * @cd: pointer to command details structure or NULL 1698 * 1699 * Helper function to allocate/free resources using the admin queue commands 1700 */ 1701 enum ice_status 1702 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 1703 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1704 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1705 { 1706 struct ice_aqc_alloc_free_res_cmd *cmd; 1707 struct ice_aq_desc desc; 1708 1709 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1710 1711 cmd = &desc.params.sw_res_ctrl; 1712 1713 if (!buf) 1714 return ICE_ERR_PARAM; 1715 1716 if (buf_size < (num_entries * sizeof(buf->elem[0]))) 1717 return ICE_ERR_PARAM; 1718 1719 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1720 1721 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 1722 1723 cmd->num_entries = CPU_TO_LE16(num_entries); 1724 1725 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1726 } 1727 1728 /** 1729 * ice_alloc_hw_res - allocate resource 1730 * @hw: pointer to the HW struct 1731 * @type: type of resource 1732 * @num: number of resources to allocate 1733 * @btm: allocate from bottom 1734 * @res: pointer to array that will receive the resources 1735 */ 1736 enum ice_status 1737 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 1738 { 1739 struct ice_aqc_alloc_free_res_elem *buf; 1740 enum ice_status status; 1741 u16 buf_len; 1742 1743 buf_len = ice_struct_size(buf, elem, num - 1); 1744 buf = (struct ice_aqc_alloc_free_res_elem *) 1745 ice_malloc(hw, buf_len); 1746 if (!buf) 1747 return ICE_ERR_NO_MEMORY; 1748 1749 /* Prepare buffer to allocate resource. */ 1750 buf->num_elems = CPU_TO_LE16(num); 1751 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 1752 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 1753 if (btm) 1754 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 1755 1756 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 1757 ice_aqc_opc_alloc_res, NULL); 1758 if (status) 1759 goto ice_alloc_res_exit; 1760 1761 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num, 1762 ICE_NONDMA_TO_NONDMA); 1763 1764 ice_alloc_res_exit: 1765 ice_free(hw, buf); 1766 return status; 1767 } 1768 1769 /** 1770 * ice_free_hw_res - free allocated HW resource 1771 * @hw: pointer to the HW struct 1772 * @type: type of resource to free 1773 * @num: number of resources 1774 * @res: pointer to array that contains the resources to free 1775 */ 1776 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 1777 { 1778 struct ice_aqc_alloc_free_res_elem *buf; 1779 enum ice_status status; 1780 u16 buf_len; 1781 1782 buf_len = ice_struct_size(buf, elem, num - 1); 1783 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); 1784 if (!buf) 1785 return ICE_ERR_NO_MEMORY; 1786 1787 /* Prepare buffer to free resource. */ 1788 buf->num_elems = CPU_TO_LE16(num); 1789 buf->res_type = CPU_TO_LE16(type); 1790 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num, 1791 ICE_NONDMA_TO_NONDMA); 1792 1793 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 1794 ice_aqc_opc_free_res, NULL); 1795 if (status) 1796 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 1797 1798 ice_free(hw, buf); 1799 return status; 1800 } 1801 1802 /** 1803 * ice_get_num_per_func - determine number of resources per PF 1804 * @hw: pointer to the HW structure 1805 * @max: value to be evenly split between each PF 1806 * 1807 * Determine the number of valid functions by going through the bitmap returned 1808 * from parsing capabilities and use this to calculate the number of resources 1809 * per PF based on the max value passed in. 1810 */ 1811 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 1812 { 1813 u8 funcs; 1814 1815 #define ICE_CAPS_VALID_FUNCS_M 0xFF 1816 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions & 1817 ICE_CAPS_VALID_FUNCS_M); 1818 1819 if (!funcs) 1820 return 0; 1821 1822 return max / funcs; 1823 } 1824 1825 /** 1826 * ice_parse_caps - parse function/device capabilities 1827 * @hw: pointer to the HW struct 1828 * @buf: pointer to a buffer containing function/device capability records 1829 * @cap_count: number of capability records in the list 1830 * @opc: type of capabilities list to parse 1831 * 1832 * Helper function to parse function(0x000a)/device(0x000b) capabilities list. 1833 */ 1834 static void 1835 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count, 1836 enum ice_adminq_opc opc) 1837 { 1838 struct ice_aqc_list_caps_elem *cap_resp; 1839 struct ice_hw_func_caps *func_p = NULL; 1840 struct ice_hw_dev_caps *dev_p = NULL; 1841 struct ice_hw_common_caps *caps; 1842 char const *prefix; 1843 u32 i; 1844 1845 if (!buf) 1846 return; 1847 1848 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 1849 1850 if (opc == ice_aqc_opc_list_dev_caps) { 1851 dev_p = &hw->dev_caps; 1852 caps = &dev_p->common_cap; 1853 1854 ice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM); 1855 1856 prefix = "dev cap"; 1857 } else if (opc == ice_aqc_opc_list_func_caps) { 1858 func_p = &hw->func_caps; 1859 caps = &func_p->common_cap; 1860 1861 ice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM); 1862 1863 prefix = "func cap"; 1864 } else { 1865 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n"); 1866 return; 1867 } 1868 1869 for (i = 0; caps && i < cap_count; i++, cap_resp++) { 1870 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id); 1871 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id); 1872 u32 number = LE32_TO_CPU(cap_resp->number); 1873 u16 cap = LE16_TO_CPU(cap_resp->cap); 1874 1875 switch (cap) { 1876 case ICE_AQC_CAPS_VALID_FUNCTIONS: 1877 caps->valid_functions = number; 1878 ice_debug(hw, ICE_DBG_INIT, 1879 "%s: valid_functions (bitmap) = %d\n", prefix, 1880 caps->valid_functions); 1881 1882 /* store func count for resource management purposes */ 1883 if (dev_p) 1884 dev_p->num_funcs = ice_hweight32(number); 1885 break; 1886 case ICE_AQC_CAPS_VSI: 1887 if (dev_p) { 1888 dev_p->num_vsi_allocd_to_host = number; 1889 ice_debug(hw, ICE_DBG_INIT, 1890 "%s: num_vsi_allocd_to_host = %d\n", 1891 prefix, 1892 dev_p->num_vsi_allocd_to_host); 1893 } else if (func_p) { 1894 func_p->guar_num_vsi = 1895 ice_get_num_per_func(hw, ICE_MAX_VSI); 1896 ice_debug(hw, ICE_DBG_INIT, 1897 "%s: guar_num_vsi (fw) = %d\n", 1898 prefix, number); 1899 ice_debug(hw, ICE_DBG_INIT, 1900 "%s: guar_num_vsi = %d\n", 1901 prefix, func_p->guar_num_vsi); 1902 } 1903 break; 1904 case ICE_AQC_CAPS_DCB: 1905 caps->dcb = (number == 1); 1906 caps->active_tc_bitmap = logical_id; 1907 caps->maxtc = phys_id; 1908 ice_debug(hw, ICE_DBG_INIT, 1909 "%s: dcb = %d\n", prefix, caps->dcb); 1910 ice_debug(hw, ICE_DBG_INIT, 1911 "%s: active_tc_bitmap = %d\n", prefix, 1912 caps->active_tc_bitmap); 1913 ice_debug(hw, ICE_DBG_INIT, 1914 "%s: maxtc = %d\n", prefix, caps->maxtc); 1915 break; 1916 case ICE_AQC_CAPS_RSS: 1917 caps->rss_table_size = number; 1918 caps->rss_table_entry_width = logical_id; 1919 ice_debug(hw, ICE_DBG_INIT, 1920 "%s: rss_table_size = %d\n", prefix, 1921 caps->rss_table_size); 1922 ice_debug(hw, ICE_DBG_INIT, 1923 "%s: rss_table_entry_width = %d\n", prefix, 1924 caps->rss_table_entry_width); 1925 break; 1926 case ICE_AQC_CAPS_RXQS: 1927 caps->num_rxq = number; 1928 caps->rxq_first_id = phys_id; 1929 ice_debug(hw, ICE_DBG_INIT, 1930 "%s: num_rxq = %d\n", prefix, 1931 caps->num_rxq); 1932 ice_debug(hw, ICE_DBG_INIT, 1933 "%s: rxq_first_id = %d\n", prefix, 1934 caps->rxq_first_id); 1935 break; 1936 case ICE_AQC_CAPS_TXQS: 1937 caps->num_txq = number; 1938 caps->txq_first_id = phys_id; 1939 ice_debug(hw, ICE_DBG_INIT, 1940 "%s: num_txq = %d\n", prefix, 1941 caps->num_txq); 1942 ice_debug(hw, ICE_DBG_INIT, 1943 "%s: txq_first_id = %d\n", prefix, 1944 caps->txq_first_id); 1945 break; 1946 case ICE_AQC_CAPS_MSIX: 1947 caps->num_msix_vectors = number; 1948 caps->msix_vector_first_id = phys_id; 1949 ice_debug(hw, ICE_DBG_INIT, 1950 "%s: num_msix_vectors = %d\n", prefix, 1951 caps->num_msix_vectors); 1952 ice_debug(hw, ICE_DBG_INIT, 1953 "%s: msix_vector_first_id = %d\n", prefix, 1954 caps->msix_vector_first_id); 1955 break; 1956 case ICE_AQC_CAPS_FD: 1957 if (dev_p) { 1958 dev_p->num_flow_director_fltr = number; 1959 ice_debug(hw, ICE_DBG_INIT, 1960 "%s: num_flow_director_fltr = %d\n", 1961 prefix, 1962 dev_p->num_flow_director_fltr); 1963 } 1964 if (func_p) { 1965 u32 reg_val, val; 1966 1967 if (hw->dcf_enabled) 1968 break; 1969 reg_val = rd32(hw, GLQF_FD_SIZE); 1970 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 1971 GLQF_FD_SIZE_FD_GSIZE_S; 1972 func_p->fd_fltr_guar = 1973 ice_get_num_per_func(hw, val); 1974 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 1975 GLQF_FD_SIZE_FD_BSIZE_S; 1976 func_p->fd_fltr_best_effort = val; 1977 ice_debug(hw, ICE_DBG_INIT, 1978 "%s: fd_fltr_guar = %d\n", 1979 prefix, func_p->fd_fltr_guar); 1980 ice_debug(hw, ICE_DBG_INIT, 1981 "%s: fd_fltr_best_effort = %d\n", 1982 prefix, func_p->fd_fltr_best_effort); 1983 } 1984 break; 1985 case ICE_AQC_CAPS_MAX_MTU: 1986 caps->max_mtu = number; 1987 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 1988 prefix, caps->max_mtu); 1989 break; 1990 default: 1991 ice_debug(hw, ICE_DBG_INIT, 1992 "%s: unknown capability[%d]: 0x%x\n", prefix, 1993 i, cap); 1994 break; 1995 } 1996 } 1997 1998 /* Re-calculate capabilities that are dependent on the number of 1999 * physical ports; i.e. some features are not supported or function 2000 * differently on devices with more than 4 ports. 2001 */ 2002 if (hw->dev_caps.num_funcs > 4) { 2003 /* Max 4 TCs per port */ 2004 caps->maxtc = 4; 2005 ice_debug(hw, ICE_DBG_INIT, 2006 "%s: maxtc = %d (based on #ports)\n", prefix, 2007 caps->maxtc); 2008 } 2009 } 2010 2011 /** 2012 * ice_aq_discover_caps - query function/device capabilities 2013 * @hw: pointer to the HW struct 2014 * @buf: a virtual buffer to hold the capabilities 2015 * @buf_size: Size of the virtual buffer 2016 * @cap_count: cap count needed if AQ err==ENOMEM 2017 * @opc: capabilities type to discover - pass in the command opcode 2018 * @cd: pointer to command details structure or NULL 2019 * 2020 * Get the function(0x000a)/device(0x000b) capabilities description from 2021 * the firmware. 2022 */ 2023 static enum ice_status 2024 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2025 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2026 { 2027 struct ice_aqc_list_caps *cmd; 2028 struct ice_aq_desc desc; 2029 enum ice_status status; 2030 2031 cmd = &desc.params.get_cap; 2032 2033 if (opc != ice_aqc_opc_list_func_caps && 2034 opc != ice_aqc_opc_list_dev_caps) 2035 return ICE_ERR_PARAM; 2036 2037 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2038 2039 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2040 if (!status) 2041 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc); 2042 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM) 2043 *cap_count = LE32_TO_CPU(cmd->count); 2044 return status; 2045 } 2046 2047 /** 2048 * ice_discover_caps - get info about the HW 2049 * @hw: pointer to the hardware structure 2050 * @opc: capabilities type to discover - pass in the command opcode 2051 */ 2052 static enum ice_status 2053 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc) 2054 { 2055 enum ice_status status; 2056 u32 cap_count; 2057 void *cbuf; 2058 2059 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN); 2060 if (!cbuf) 2061 return ICE_ERR_NO_MEMORY; 2062 2063 /* Although the driver doesn't know the number of capabilities the 2064 * device will return, we can simply send a 4KB buffer, the maximum 2065 * possible size that firmware can return. 2066 */ 2067 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2068 2069 status = ice_aq_discover_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2070 opc, NULL); 2071 ice_free(hw, cbuf); 2072 2073 return status; 2074 } 2075 2076 /** 2077 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2078 * @hw: pointer to the hardware structure 2079 */ 2080 void ice_set_safe_mode_caps(struct ice_hw *hw) 2081 { 2082 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2083 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2084 u32 valid_func, rxq_first_id, txq_first_id; 2085 u32 msix_vector_first_id, max_mtu; 2086 u32 num_funcs; 2087 2088 /* cache some func_caps values that should be restored after memset */ 2089 valid_func = func_caps->common_cap.valid_functions; 2090 txq_first_id = func_caps->common_cap.txq_first_id; 2091 rxq_first_id = func_caps->common_cap.rxq_first_id; 2092 msix_vector_first_id = func_caps->common_cap.msix_vector_first_id; 2093 max_mtu = func_caps->common_cap.max_mtu; 2094 2095 /* unset func capabilities */ 2096 memset(func_caps, 0, sizeof(*func_caps)); 2097 2098 /* restore cached values */ 2099 func_caps->common_cap.valid_functions = valid_func; 2100 func_caps->common_cap.txq_first_id = txq_first_id; 2101 func_caps->common_cap.rxq_first_id = rxq_first_id; 2102 func_caps->common_cap.msix_vector_first_id = msix_vector_first_id; 2103 func_caps->common_cap.max_mtu = max_mtu; 2104 2105 /* one Tx and one Rx queue in safe mode */ 2106 func_caps->common_cap.num_rxq = 1; 2107 func_caps->common_cap.num_txq = 1; 2108 2109 /* two MSIX vectors, one for traffic and one for misc causes */ 2110 func_caps->common_cap.num_msix_vectors = 2; 2111 func_caps->guar_num_vsi = 1; 2112 2113 /* cache some dev_caps values that should be restored after memset */ 2114 valid_func = dev_caps->common_cap.valid_functions; 2115 txq_first_id = dev_caps->common_cap.txq_first_id; 2116 rxq_first_id = dev_caps->common_cap.rxq_first_id; 2117 msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id; 2118 max_mtu = dev_caps->common_cap.max_mtu; 2119 num_funcs = dev_caps->num_funcs; 2120 2121 /* unset dev capabilities */ 2122 memset(dev_caps, 0, sizeof(*dev_caps)); 2123 2124 /* restore cached values */ 2125 dev_caps->common_cap.valid_functions = valid_func; 2126 dev_caps->common_cap.txq_first_id = txq_first_id; 2127 dev_caps->common_cap.rxq_first_id = rxq_first_id; 2128 dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id; 2129 dev_caps->common_cap.max_mtu = max_mtu; 2130 dev_caps->num_funcs = num_funcs; 2131 2132 /* one Tx and one Rx queue per function in safe mode */ 2133 dev_caps->common_cap.num_rxq = num_funcs; 2134 dev_caps->common_cap.num_txq = num_funcs; 2135 2136 /* two MSIX vectors per function */ 2137 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2138 } 2139 2140 /** 2141 * ice_get_caps - get info about the HW 2142 * @hw: pointer to the hardware structure 2143 */ 2144 enum ice_status ice_get_caps(struct ice_hw *hw) 2145 { 2146 enum ice_status status; 2147 2148 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps); 2149 if (!status) 2150 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps); 2151 2152 return status; 2153 } 2154 2155 /** 2156 * ice_aq_manage_mac_write - manage MAC address write command 2157 * @hw: pointer to the HW struct 2158 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2159 * @flags: flags to control write behavior 2160 * @cd: pointer to command details structure or NULL 2161 * 2162 * This function is used to write MAC address to the NVM (0x0108). 2163 */ 2164 enum ice_status 2165 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2166 struct ice_sq_cd *cd) 2167 { 2168 struct ice_aqc_manage_mac_write *cmd; 2169 struct ice_aq_desc desc; 2170 2171 cmd = &desc.params.mac_write; 2172 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2173 2174 cmd->flags = flags; 2175 ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_DMA); 2176 2177 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2178 } 2179 2180 /** 2181 * ice_aq_clear_pxe_mode 2182 * @hw: pointer to the HW struct 2183 * 2184 * Tell the firmware that the driver is taking over from PXE (0x0110). 2185 */ 2186 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 2187 { 2188 struct ice_aq_desc desc; 2189 2190 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2191 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2192 2193 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2194 } 2195 2196 /** 2197 * ice_clear_pxe_mode - clear pxe operations mode 2198 * @hw: pointer to the HW struct 2199 * 2200 * Make sure all PXE mode settings are cleared, including things 2201 * like descriptor fetch/write-back mode. 2202 */ 2203 void ice_clear_pxe_mode(struct ice_hw *hw) 2204 { 2205 if (ice_check_sq_alive(hw, &hw->adminq)) 2206 ice_aq_clear_pxe_mode(hw); 2207 } 2208 2209 /** 2210 * ice_get_link_speed_based_on_phy_type - returns link speed 2211 * @phy_type_low: lower part of phy_type 2212 * @phy_type_high: higher part of phy_type 2213 * 2214 * This helper function will convert an entry in PHY type structure 2215 * [phy_type_low, phy_type_high] to its corresponding link speed. 2216 * Note: In the structure of [phy_type_low, phy_type_high], there should 2217 * be one bit set, as this function will convert one PHY type to its 2218 * speed. 2219 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2220 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2221 */ 2222 static u16 2223 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 2224 { 2225 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2226 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2227 2228 switch (phy_type_low) { 2229 case ICE_PHY_TYPE_LOW_100BASE_TX: 2230 case ICE_PHY_TYPE_LOW_100M_SGMII: 2231 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 2232 break; 2233 case ICE_PHY_TYPE_LOW_1000BASE_T: 2234 case ICE_PHY_TYPE_LOW_1000BASE_SX: 2235 case ICE_PHY_TYPE_LOW_1000BASE_LX: 2236 case ICE_PHY_TYPE_LOW_1000BASE_KX: 2237 case ICE_PHY_TYPE_LOW_1G_SGMII: 2238 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 2239 break; 2240 case ICE_PHY_TYPE_LOW_2500BASE_T: 2241 case ICE_PHY_TYPE_LOW_2500BASE_X: 2242 case ICE_PHY_TYPE_LOW_2500BASE_KX: 2243 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 2244 break; 2245 case ICE_PHY_TYPE_LOW_5GBASE_T: 2246 case ICE_PHY_TYPE_LOW_5GBASE_KR: 2247 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 2248 break; 2249 case ICE_PHY_TYPE_LOW_10GBASE_T: 2250 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 2251 case ICE_PHY_TYPE_LOW_10GBASE_SR: 2252 case ICE_PHY_TYPE_LOW_10GBASE_LR: 2253 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 2254 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 2255 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 2256 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 2257 break; 2258 case ICE_PHY_TYPE_LOW_25GBASE_T: 2259 case ICE_PHY_TYPE_LOW_25GBASE_CR: 2260 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 2261 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 2262 case ICE_PHY_TYPE_LOW_25GBASE_SR: 2263 case ICE_PHY_TYPE_LOW_25GBASE_LR: 2264 case ICE_PHY_TYPE_LOW_25GBASE_KR: 2265 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 2266 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 2267 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 2268 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 2269 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 2270 break; 2271 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 2272 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 2273 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 2274 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 2275 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 2276 case ICE_PHY_TYPE_LOW_40G_XLAUI: 2277 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 2278 break; 2279 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 2280 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 2281 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 2282 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 2283 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 2284 case ICE_PHY_TYPE_LOW_50G_LAUI2: 2285 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 2286 case ICE_PHY_TYPE_LOW_50G_AUI2: 2287 case ICE_PHY_TYPE_LOW_50GBASE_CP: 2288 case ICE_PHY_TYPE_LOW_50GBASE_SR: 2289 case ICE_PHY_TYPE_LOW_50GBASE_FR: 2290 case ICE_PHY_TYPE_LOW_50GBASE_LR: 2291 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 2292 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 2293 case ICE_PHY_TYPE_LOW_50G_AUI1: 2294 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 2295 break; 2296 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 2297 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 2298 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 2299 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 2300 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 2301 case ICE_PHY_TYPE_LOW_100G_CAUI4: 2302 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 2303 case ICE_PHY_TYPE_LOW_100G_AUI4: 2304 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 2305 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 2306 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 2307 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 2308 case ICE_PHY_TYPE_LOW_100GBASE_DR: 2309 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 2310 break; 2311 default: 2312 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2313 break; 2314 } 2315 2316 switch (phy_type_high) { 2317 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 2318 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 2319 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 2320 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 2321 case ICE_PHY_TYPE_HIGH_100G_AUI2: 2322 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 2323 break; 2324 default: 2325 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2326 break; 2327 } 2328 2329 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 2330 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2331 return ICE_AQ_LINK_SPEED_UNKNOWN; 2332 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2333 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 2334 return ICE_AQ_LINK_SPEED_UNKNOWN; 2335 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2336 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2337 return speed_phy_type_low; 2338 else 2339 return speed_phy_type_high; 2340 } 2341 2342 /** 2343 * ice_update_phy_type 2344 * @phy_type_low: pointer to the lower part of phy_type 2345 * @phy_type_high: pointer to the higher part of phy_type 2346 * @link_speeds_bitmap: targeted link speeds bitmap 2347 * 2348 * Note: For the link_speeds_bitmap structure, you can check it at 2349 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 2350 * link_speeds_bitmap include multiple speeds. 2351 * 2352 * Each entry in this [phy_type_low, phy_type_high] structure will 2353 * present a certain link speed. This helper function will turn on bits 2354 * in [phy_type_low, phy_type_high] structure based on the value of 2355 * link_speeds_bitmap input parameter. 2356 */ 2357 void 2358 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 2359 u16 link_speeds_bitmap) 2360 { 2361 u64 pt_high; 2362 u64 pt_low; 2363 int index; 2364 u16 speed; 2365 2366 /* We first check with low part of phy_type */ 2367 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 2368 pt_low = BIT_ULL(index); 2369 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 2370 2371 if (link_speeds_bitmap & speed) 2372 *phy_type_low |= BIT_ULL(index); 2373 } 2374 2375 /* We then check with high part of phy_type */ 2376 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 2377 pt_high = BIT_ULL(index); 2378 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 2379 2380 if (link_speeds_bitmap & speed) 2381 *phy_type_high |= BIT_ULL(index); 2382 } 2383 } 2384 2385 /** 2386 * ice_aq_set_phy_cfg 2387 * @hw: pointer to the HW struct 2388 * @pi: port info structure of the interested logical port 2389 * @cfg: structure with PHY configuration data to be set 2390 * @cd: pointer to command details structure or NULL 2391 * 2392 * Set the various PHY configuration parameters supported on the Port. 2393 * One or more of the Set PHY config parameters may be ignored in an MFP 2394 * mode as the PF may not have the privilege to set some of the PHY Config 2395 * parameters. This status will be indicated by the command response (0x0601). 2396 */ 2397 enum ice_status 2398 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 2399 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 2400 { 2401 struct ice_aq_desc desc; 2402 enum ice_status status; 2403 2404 if (!cfg) 2405 return ICE_ERR_PARAM; 2406 2407 /* Ensure that only valid bits of cfg->caps can be turned on. */ 2408 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 2409 ice_debug(hw, ICE_DBG_PHY, 2410 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 2411 cfg->caps); 2412 2413 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 2414 } 2415 2416 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 2417 desc.params.set_phy.lport_num = pi->lport; 2418 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 2419 2420 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 2421 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 2422 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low)); 2423 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 2424 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high)); 2425 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 2426 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 2427 cfg->low_power_ctrl_an); 2428 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 2429 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 2430 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 2431 cfg->link_fec_opt); 2432 2433 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 2434 2435 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 2436 status = ICE_SUCCESS; 2437 2438 if (!status) 2439 pi->phy.curr_user_phy_cfg = *cfg; 2440 2441 return status; 2442 } 2443 2444 /** 2445 * ice_update_link_info - update status of the HW network link 2446 * @pi: port info structure of the interested logical port 2447 */ 2448 enum ice_status ice_update_link_info(struct ice_port_info *pi) 2449 { 2450 struct ice_link_status *li; 2451 enum ice_status status; 2452 2453 if (!pi) 2454 return ICE_ERR_PARAM; 2455 2456 li = &pi->phy.link_info; 2457 2458 status = ice_aq_get_link_info(pi, true, NULL, NULL); 2459 if (status) 2460 return status; 2461 2462 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 2463 struct ice_aqc_get_phy_caps_data *pcaps; 2464 struct ice_hw *hw; 2465 2466 hw = pi->hw; 2467 pcaps = (struct ice_aqc_get_phy_caps_data *) 2468 ice_malloc(hw, sizeof(*pcaps)); 2469 if (!pcaps) 2470 return ICE_ERR_NO_MEMORY; 2471 2472 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, 2473 pcaps, NULL); 2474 2475 ice_free(hw, pcaps); 2476 } 2477 2478 return status; 2479 } 2480 2481 /** 2482 * ice_cache_phy_user_req 2483 * @pi: port information structure 2484 * @cache_data: PHY logging data 2485 * @cache_mode: PHY logging mode 2486 * 2487 * Log the user request on (FC, FEC, SPEED) for later user. 2488 */ 2489 static void 2490 ice_cache_phy_user_req(struct ice_port_info *pi, 2491 struct ice_phy_cache_mode_data cache_data, 2492 enum ice_phy_cache_mode cache_mode) 2493 { 2494 if (!pi) 2495 return; 2496 2497 switch (cache_mode) { 2498 case ICE_FC_MODE: 2499 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 2500 break; 2501 case ICE_SPEED_MODE: 2502 pi->phy.curr_user_speed_req = 2503 cache_data.data.curr_user_speed_req; 2504 break; 2505 case ICE_FEC_MODE: 2506 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 2507 break; 2508 default: 2509 break; 2510 } 2511 } 2512 2513 /** 2514 * ice_caps_to_fc_mode 2515 * @caps: PHY capabilities 2516 * 2517 * Convert PHY FC capabilities to ice FC mode 2518 */ 2519 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 2520 { 2521 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 2522 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2523 return ICE_FC_FULL; 2524 2525 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 2526 return ICE_FC_TX_PAUSE; 2527 2528 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2529 return ICE_FC_RX_PAUSE; 2530 2531 return ICE_FC_NONE; 2532 } 2533 2534 /** 2535 * ice_caps_to_fec_mode 2536 * @caps: PHY capabilities 2537 * @fec_options: Link FEC options 2538 * 2539 * Convert PHY FEC capabilities to ice FEC mode 2540 */ 2541 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 2542 { 2543 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 2544 return ICE_FEC_AUTO; 2545 2546 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2547 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 2548 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 2549 ICE_AQC_PHY_FEC_25G_KR_REQ)) 2550 return ICE_FEC_BASER; 2551 2552 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 2553 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 2554 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 2555 return ICE_FEC_RS; 2556 2557 return ICE_FEC_NONE; 2558 } 2559 2560 static enum ice_status 2561 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 2562 enum ice_fc_mode req_mode) 2563 { 2564 struct ice_aqc_get_phy_caps_data *pcaps = NULL; 2565 struct ice_phy_cache_mode_data cache_data; 2566 enum ice_status status = ICE_SUCCESS; 2567 u8 pause_mask = 0x0; 2568 2569 if (!pi || !cfg) 2570 return ICE_ERR_BAD_PTR; 2571 2572 pcaps = (struct ice_aqc_get_phy_caps_data *) 2573 ice_malloc(pi->hw, sizeof(*pcaps)); 2574 if (!pcaps) 2575 return ICE_ERR_NO_MEMORY; 2576 2577 /* Cache user FC request */ 2578 cache_data.data.curr_user_fc_req = req_mode; 2579 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 2580 2581 switch (req_mode) { 2582 case ICE_FC_AUTO: 2583 /* Query the value of FC that both the NIC and attached media 2584 * can do. 2585 */ 2586 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, 2587 pcaps, NULL); 2588 if (status) 2589 goto out; 2590 2591 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2592 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2593 break; 2594 case ICE_FC_FULL: 2595 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2596 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2597 break; 2598 case ICE_FC_RX_PAUSE: 2599 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2600 break; 2601 case ICE_FC_TX_PAUSE: 2602 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2603 break; 2604 default: 2605 break; 2606 } 2607 2608 /* clear the old pause settings */ 2609 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 2610 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 2611 2612 /* set the new capabilities */ 2613 cfg->caps |= pause_mask; 2614 2615 out: 2616 ice_free(pi->hw, pcaps); 2617 return status; 2618 } 2619 2620 /** 2621 * ice_set_fc 2622 * @pi: port information structure 2623 * @aq_failures: pointer to status code, specific to ice_set_fc routine 2624 * @ena_auto_link_update: enable automatic link update 2625 * 2626 * Set the requested flow control mode. 2627 */ 2628 enum ice_status 2629 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 2630 { 2631 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 2632 struct ice_aqc_get_phy_caps_data *pcaps; 2633 enum ice_status status; 2634 struct ice_hw *hw; 2635 2636 if (!pi || !aq_failures) 2637 return ICE_ERR_BAD_PTR; 2638 2639 *aq_failures = 0; 2640 hw = pi->hw; 2641 2642 pcaps = (struct ice_aqc_get_phy_caps_data *) 2643 ice_malloc(hw, sizeof(*pcaps)); 2644 if (!pcaps) 2645 return ICE_ERR_NO_MEMORY; 2646 2647 /* Get the current PHY config */ 2648 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, 2649 NULL); 2650 if (status) { 2651 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2652 goto out; 2653 } 2654 2655 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 2656 2657 /* Configure the set PHY data */ 2658 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 2659 if (status) { 2660 if (status != ICE_ERR_BAD_PTR) 2661 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2662 2663 goto out; 2664 } 2665 2666 /* If the capabilities have changed, then set the new config */ 2667 if (cfg.caps != pcaps->caps) { 2668 int retry_count, retry_max = 10; 2669 2670 /* Auto restart link so settings take effect */ 2671 if (ena_auto_link_update) 2672 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2673 2674 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 2675 if (status) { 2676 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 2677 goto out; 2678 } 2679 2680 /* Update the link info 2681 * It sometimes takes a really long time for link to 2682 * come back from the atomic reset. Thus, we wait a 2683 * little bit. 2684 */ 2685 for (retry_count = 0; retry_count < retry_max; retry_count++) { 2686 status = ice_update_link_info(pi); 2687 2688 if (status == ICE_SUCCESS) 2689 break; 2690 2691 ice_msec_delay(100, true); 2692 } 2693 2694 if (status) 2695 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 2696 } 2697 2698 out: 2699 ice_free(hw, pcaps); 2700 return status; 2701 } 2702 2703 /** 2704 * ice_phy_caps_equals_cfg 2705 * @phy_caps: PHY capabilities 2706 * @phy_cfg: PHY configuration 2707 * 2708 * Helper function to determine if PHY capabilities matches PHY 2709 * configuration 2710 */ 2711 bool 2712 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 2713 struct ice_aqc_set_phy_cfg_data *phy_cfg) 2714 { 2715 u8 caps_mask, cfg_mask; 2716 2717 if (!phy_caps || !phy_cfg) 2718 return false; 2719 2720 /* These bits are not common between capabilities and configuration. 2721 * Do not use them to determine equality. 2722 */ 2723 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 2724 ICE_AQC_PHY_EN_MOD_QUAL); 2725 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2726 2727 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 2728 phy_caps->phy_type_high != phy_cfg->phy_type_high || 2729 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 2730 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 2731 phy_caps->eee_cap != phy_cfg->eee_cap || 2732 phy_caps->eeer_value != phy_cfg->eeer_value || 2733 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 2734 return false; 2735 2736 return true; 2737 } 2738 2739 /** 2740 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 2741 * @pi: port information structure 2742 * @caps: PHY ability structure to copy date from 2743 * @cfg: PHY configuration structure to copy data to 2744 * 2745 * Helper function to copy AQC PHY get ability data to PHY set configuration 2746 * data structure 2747 */ 2748 void 2749 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 2750 struct ice_aqc_get_phy_caps_data *caps, 2751 struct ice_aqc_set_phy_cfg_data *cfg) 2752 { 2753 if (!pi || !caps || !cfg) 2754 return; 2755 2756 ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM); 2757 cfg->phy_type_low = caps->phy_type_low; 2758 cfg->phy_type_high = caps->phy_type_high; 2759 cfg->caps = caps->caps; 2760 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 2761 cfg->eee_cap = caps->eee_cap; 2762 cfg->eeer_value = caps->eeer_value; 2763 cfg->link_fec_opt = caps->link_fec_options; 2764 cfg->module_compliance_enforcement = 2765 caps->module_compliance_enforcement; 2766 2767 if (ice_fw_supports_link_override(pi->hw)) { 2768 struct ice_link_default_override_tlv tlv; 2769 2770 if (ice_get_link_default_override(&tlv, pi)) 2771 return; 2772 2773 if (tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) 2774 cfg->module_compliance_enforcement |= 2775 ICE_LINK_OVERRIDE_STRICT_MODE; 2776 } 2777 } 2778 2779 /** 2780 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 2781 * @pi: port information structure 2782 * @cfg: PHY configuration data to set FEC mode 2783 * @fec: FEC mode to configure 2784 */ 2785 enum ice_status 2786 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 2787 enum ice_fec_mode fec) 2788 { 2789 struct ice_aqc_get_phy_caps_data *pcaps; 2790 enum ice_status status = ICE_SUCCESS; 2791 struct ice_hw *hw; 2792 2793 if (!pi || !cfg) 2794 return ICE_ERR_BAD_PTR; 2795 2796 hw = pi->hw; 2797 2798 pcaps = (struct ice_aqc_get_phy_caps_data *) 2799 ice_malloc(hw, sizeof(*pcaps)); 2800 if (!pcaps) 2801 return ICE_ERR_NO_MEMORY; 2802 2803 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, pcaps, 2804 NULL); 2805 if (status) 2806 goto out; 2807 2808 cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC); 2809 cfg->link_fec_opt = pcaps->link_fec_options; 2810 2811 switch (fec) { 2812 case ICE_FEC_BASER: 2813 /* Clear RS bits, and AND BASE-R ability 2814 * bits and OR request bits. 2815 */ 2816 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2817 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 2818 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 2819 ICE_AQC_PHY_FEC_25G_KR_REQ; 2820 break; 2821 case ICE_FEC_RS: 2822 /* Clear BASE-R bits, and AND RS ability 2823 * bits and OR request bits. 2824 */ 2825 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 2826 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 2827 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 2828 break; 2829 case ICE_FEC_NONE: 2830 /* Clear all FEC option bits. */ 2831 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 2832 break; 2833 case ICE_FEC_AUTO: 2834 /* AND auto FEC bit, and all caps bits. */ 2835 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 2836 cfg->link_fec_opt |= pcaps->link_fec_options; 2837 break; 2838 default: 2839 status = ICE_ERR_PARAM; 2840 break; 2841 } 2842 2843 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw)) { 2844 struct ice_link_default_override_tlv tlv; 2845 2846 if (ice_get_link_default_override(&tlv, pi)) 2847 goto out; 2848 2849 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 2850 (tlv.options & ICE_LINK_OVERRIDE_EN)) 2851 cfg->link_fec_opt = tlv.fec_options; 2852 } 2853 2854 out: 2855 ice_free(hw, pcaps); 2856 2857 return status; 2858 } 2859 2860 /** 2861 * ice_get_link_status - get status of the HW network link 2862 * @pi: port information structure 2863 * @link_up: pointer to bool (true/false = linkup/linkdown) 2864 * 2865 * Variable link_up is true if link is up, false if link is down. 2866 * The variable link_up is invalid if status is non zero. As a 2867 * result of this call, link status reporting becomes enabled 2868 */ 2869 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 2870 { 2871 struct ice_phy_info *phy_info; 2872 enum ice_status status = ICE_SUCCESS; 2873 2874 if (!pi || !link_up) 2875 return ICE_ERR_PARAM; 2876 2877 phy_info = &pi->phy; 2878 2879 if (phy_info->get_link_info) { 2880 status = ice_update_link_info(pi); 2881 2882 if (status) 2883 ice_debug(pi->hw, ICE_DBG_LINK, 2884 "get link status error, status = %d\n", 2885 status); 2886 } 2887 2888 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 2889 2890 return status; 2891 } 2892 2893 /** 2894 * ice_aq_set_link_restart_an 2895 * @pi: pointer to the port information structure 2896 * @ena_link: if true: enable link, if false: disable link 2897 * @cd: pointer to command details structure or NULL 2898 * 2899 * Sets up the link and restarts the Auto-Negotiation over the link. 2900 */ 2901 enum ice_status 2902 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 2903 struct ice_sq_cd *cd) 2904 { 2905 struct ice_aqc_restart_an *cmd; 2906 struct ice_aq_desc desc; 2907 2908 cmd = &desc.params.restart_an; 2909 2910 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 2911 2912 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 2913 cmd->lport_num = pi->lport; 2914 if (ena_link) 2915 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 2916 else 2917 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 2918 2919 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 2920 } 2921 2922 /** 2923 * ice_aq_set_event_mask 2924 * @hw: pointer to the HW struct 2925 * @port_num: port number of the physical function 2926 * @mask: event mask to be set 2927 * @cd: pointer to command details structure or NULL 2928 * 2929 * Set event mask (0x0613) 2930 */ 2931 enum ice_status 2932 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 2933 struct ice_sq_cd *cd) 2934 { 2935 struct ice_aqc_set_event_mask *cmd; 2936 struct ice_aq_desc desc; 2937 2938 cmd = &desc.params.set_event_mask; 2939 2940 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 2941 2942 cmd->lport_num = port_num; 2943 2944 cmd->event_mask = CPU_TO_LE16(mask); 2945 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2946 } 2947 2948 /** 2949 * ice_aq_set_mac_loopback 2950 * @hw: pointer to the HW struct 2951 * @ena_lpbk: Enable or Disable loopback 2952 * @cd: pointer to command details structure or NULL 2953 * 2954 * Enable/disable loopback on a given port 2955 */ 2956 enum ice_status 2957 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 2958 { 2959 struct ice_aqc_set_mac_lb *cmd; 2960 struct ice_aq_desc desc; 2961 2962 cmd = &desc.params.set_mac_lb; 2963 2964 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 2965 if (ena_lpbk) 2966 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 2967 2968 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2969 } 2970 2971 /** 2972 * ice_aq_set_port_id_led 2973 * @pi: pointer to the port information 2974 * @is_orig_mode: is this LED set to original mode (by the net-list) 2975 * @cd: pointer to command details structure or NULL 2976 * 2977 * Set LED value for the given port (0x06e9) 2978 */ 2979 enum ice_status 2980 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 2981 struct ice_sq_cd *cd) 2982 { 2983 struct ice_aqc_set_port_id_led *cmd; 2984 struct ice_hw *hw = pi->hw; 2985 struct ice_aq_desc desc; 2986 2987 cmd = &desc.params.set_port_id_led; 2988 2989 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 2990 2991 if (is_orig_mode) 2992 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 2993 else 2994 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 2995 2996 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2997 } 2998 2999 /** 3000 * ice_aq_sff_eeprom 3001 * @hw: pointer to the HW struct 3002 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3003 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3004 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3005 * @page: QSFP page 3006 * @set_page: set or ignore the page 3007 * @data: pointer to data buffer to be read/written to the I2C device. 3008 * @length: 1-16 for read, 1 for write. 3009 * @write: 0 read, 1 for write. 3010 * @cd: pointer to command details structure or NULL 3011 * 3012 * Read/Write SFF EEPROM (0x06EE) 3013 */ 3014 enum ice_status 3015 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3016 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3017 bool write, struct ice_sq_cd *cd) 3018 { 3019 struct ice_aqc_sff_eeprom *cmd; 3020 struct ice_aq_desc desc; 3021 enum ice_status status; 3022 3023 if (!data || (mem_addr & 0xff00)) 3024 return ICE_ERR_PARAM; 3025 3026 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3027 cmd = &desc.params.read_write_sff_param; 3028 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF); 3029 cmd->lport_num = (u8)(lport & 0xff); 3030 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3031 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) & 3032 ICE_AQC_SFF_I2CBUS_7BIT_M) | 3033 ((set_page << 3034 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3035 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3036 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff); 3037 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3038 if (write) 3039 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE); 3040 3041 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3042 return status; 3043 } 3044 3045 /** 3046 * __ice_aq_get_set_rss_lut 3047 * @hw: pointer to the hardware structure 3048 * @vsi_id: VSI FW index 3049 * @lut_type: LUT table type 3050 * @lut: pointer to the LUT buffer provided by the caller 3051 * @lut_size: size of the LUT buffer 3052 * @glob_lut_idx: global LUT index 3053 * @set: set true to set the table, false to get the table 3054 * 3055 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3056 */ 3057 static enum ice_status 3058 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, 3059 u16 lut_size, u8 glob_lut_idx, bool set) 3060 { 3061 struct ice_aqc_get_set_rss_lut *cmd_resp; 3062 struct ice_aq_desc desc; 3063 enum ice_status status; 3064 u16 flags = 0; 3065 3066 cmd_resp = &desc.params.get_set_rss_lut; 3067 3068 if (set) { 3069 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 3070 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3071 } else { 3072 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 3073 } 3074 3075 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 3076 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 3077 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 3078 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 3079 3080 switch (lut_type) { 3081 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 3082 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 3083 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 3084 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 3085 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 3086 break; 3087 default: 3088 status = ICE_ERR_PARAM; 3089 goto ice_aq_get_set_rss_lut_exit; 3090 } 3091 3092 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 3093 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 3094 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 3095 3096 if (!set) 3097 goto ice_aq_get_set_rss_lut_send; 3098 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3099 if (!set) 3100 goto ice_aq_get_set_rss_lut_send; 3101 } else { 3102 goto ice_aq_get_set_rss_lut_send; 3103 } 3104 3105 /* LUT size is only valid for Global and PF table types */ 3106 switch (lut_size) { 3107 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 3108 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG << 3109 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3110 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3111 break; 3112 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 3113 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 3114 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3115 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3116 break; 3117 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 3118 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3119 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 3120 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3121 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3122 break; 3123 } 3124 /* fall-through */ 3125 default: 3126 status = ICE_ERR_PARAM; 3127 goto ice_aq_get_set_rss_lut_exit; 3128 } 3129 3130 ice_aq_get_set_rss_lut_send: 3131 cmd_resp->flags = CPU_TO_LE16(flags); 3132 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 3133 3134 ice_aq_get_set_rss_lut_exit: 3135 return status; 3136 } 3137 3138 /** 3139 * ice_aq_get_rss_lut 3140 * @hw: pointer to the hardware structure 3141 * @vsi_handle: software VSI handle 3142 * @lut_type: LUT table type 3143 * @lut: pointer to the LUT buffer provided by the caller 3144 * @lut_size: size of the LUT buffer 3145 * 3146 * get the RSS lookup table, PF or VSI type 3147 */ 3148 enum ice_status 3149 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 3150 u8 *lut, u16 lut_size) 3151 { 3152 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3153 return ICE_ERR_PARAM; 3154 3155 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3156 lut_type, lut, lut_size, 0, false); 3157 } 3158 3159 /** 3160 * ice_aq_set_rss_lut 3161 * @hw: pointer to the hardware structure 3162 * @vsi_handle: software VSI handle 3163 * @lut_type: LUT table type 3164 * @lut: pointer to the LUT buffer provided by the caller 3165 * @lut_size: size of the LUT buffer 3166 * 3167 * set the RSS lookup table, PF or VSI type 3168 */ 3169 enum ice_status 3170 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 3171 u8 *lut, u16 lut_size) 3172 { 3173 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3174 return ICE_ERR_PARAM; 3175 3176 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3177 lut_type, lut, lut_size, 0, true); 3178 } 3179 3180 /** 3181 * __ice_aq_get_set_rss_key 3182 * @hw: pointer to the HW struct 3183 * @vsi_id: VSI FW index 3184 * @key: pointer to key info struct 3185 * @set: set true to set the key, false to get the key 3186 * 3187 * get (0x0B04) or set (0x0B02) the RSS key per VSI 3188 */ 3189 static enum 3190 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 3191 struct ice_aqc_get_set_rss_keys *key, 3192 bool set) 3193 { 3194 struct ice_aqc_get_set_rss_key *cmd_resp; 3195 u16 key_size = sizeof(*key); 3196 struct ice_aq_desc desc; 3197 3198 cmd_resp = &desc.params.get_set_rss_key; 3199 3200 if (set) { 3201 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 3202 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3203 } else { 3204 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 3205 } 3206 3207 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 3208 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 3209 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 3210 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 3211 3212 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 3213 } 3214 3215 /** 3216 * ice_aq_get_rss_key 3217 * @hw: pointer to the HW struct 3218 * @vsi_handle: software VSI handle 3219 * @key: pointer to key info struct 3220 * 3221 * get the RSS key per VSI 3222 */ 3223 enum ice_status 3224 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 3225 struct ice_aqc_get_set_rss_keys *key) 3226 { 3227 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 3228 return ICE_ERR_PARAM; 3229 3230 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3231 key, false); 3232 } 3233 3234 /** 3235 * ice_aq_set_rss_key 3236 * @hw: pointer to the HW struct 3237 * @vsi_handle: software VSI handle 3238 * @keys: pointer to key info struct 3239 * 3240 * set the RSS key per VSI 3241 */ 3242 enum ice_status 3243 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 3244 struct ice_aqc_get_set_rss_keys *keys) 3245 { 3246 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 3247 return ICE_ERR_PARAM; 3248 3249 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3250 keys, true); 3251 } 3252 3253 /** 3254 * ice_aq_add_lan_txq 3255 * @hw: pointer to the hardware structure 3256 * @num_qgrps: Number of added queue groups 3257 * @qg_list: list of queue groups to be added 3258 * @buf_size: size of buffer for indirect command 3259 * @cd: pointer to command details structure or NULL 3260 * 3261 * Add Tx LAN queue (0x0C30) 3262 * 3263 * NOTE: 3264 * Prior to calling add Tx LAN queue: 3265 * Initialize the following as part of the Tx queue context: 3266 * Completion queue ID if the queue uses Completion queue, Quanta profile, 3267 * Cache profile and Packet shaper profile. 3268 * 3269 * After add Tx LAN queue AQ command is completed: 3270 * Interrupts should be associated with specific queues, 3271 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 3272 * flow. 3273 */ 3274 enum ice_status 3275 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3276 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 3277 struct ice_sq_cd *cd) 3278 { 3279 u16 i, sum_header_size, sum_q_size = 0; 3280 struct ice_aqc_add_tx_qgrp *list; 3281 struct ice_aqc_add_txqs *cmd; 3282 struct ice_aq_desc desc; 3283 3284 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 3285 3286 cmd = &desc.params.add_txqs; 3287 3288 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 3289 3290 if (!qg_list) 3291 return ICE_ERR_PARAM; 3292 3293 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3294 return ICE_ERR_PARAM; 3295 3296 sum_header_size = num_qgrps * 3297 (sizeof(*qg_list) - sizeof(*qg_list->txqs)); 3298 3299 list = qg_list; 3300 for (i = 0; i < num_qgrps; i++) { 3301 struct ice_aqc_add_txqs_perq *q = list->txqs; 3302 3303 sum_q_size += list->num_txqs * sizeof(*q); 3304 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs); 3305 } 3306 3307 if (buf_size != (sum_header_size + sum_q_size)) 3308 return ICE_ERR_PARAM; 3309 3310 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3311 3312 cmd->num_qgrps = num_qgrps; 3313 3314 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3315 } 3316 3317 /** 3318 * ice_aq_dis_lan_txq 3319 * @hw: pointer to the hardware structure 3320 * @num_qgrps: number of groups in the list 3321 * @qg_list: the list of groups to disable 3322 * @buf_size: the total size of the qg_list buffer in bytes 3323 * @rst_src: if called due to reset, specifies the reset source 3324 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3325 * @cd: pointer to command details structure or NULL 3326 * 3327 * Disable LAN Tx queue (0x0C31) 3328 */ 3329 static enum ice_status 3330 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3331 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 3332 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3333 struct ice_sq_cd *cd) 3334 { 3335 struct ice_aqc_dis_txqs *cmd; 3336 struct ice_aq_desc desc; 3337 enum ice_status status; 3338 u16 i, sz = 0; 3339 3340 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 3341 cmd = &desc.params.dis_txqs; 3342 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 3343 3344 /* qg_list can be NULL only in VM/VF reset flow */ 3345 if (!qg_list && !rst_src) 3346 return ICE_ERR_PARAM; 3347 3348 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3349 return ICE_ERR_PARAM; 3350 3351 cmd->num_entries = num_qgrps; 3352 3353 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 3354 ICE_AQC_Q_DIS_TIMEOUT_M); 3355 3356 switch (rst_src) { 3357 case ICE_VM_RESET: 3358 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 3359 cmd->vmvf_and_timeout |= 3360 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 3361 break; 3362 case ICE_NO_RESET: 3363 default: 3364 break; 3365 } 3366 3367 /* flush pipe on time out */ 3368 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 3369 /* If no queue group info, we are in a reset flow. Issue the AQ */ 3370 if (!qg_list) 3371 goto do_aq; 3372 3373 /* set RD bit to indicate that command buffer is provided by the driver 3374 * and it needs to be read by the firmware 3375 */ 3376 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3377 3378 for (i = 0; i < num_qgrps; ++i) { 3379 /* Calculate the size taken up by the queue IDs in this group */ 3380 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id); 3381 3382 /* Add the size of the group header */ 3383 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id); 3384 3385 /* If the num of queues is even, add 2 bytes of padding */ 3386 if ((qg_list[i].num_qs % 2) == 0) 3387 sz += 2; 3388 } 3389 3390 if (buf_size != sz) 3391 return ICE_ERR_PARAM; 3392 3393 do_aq: 3394 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3395 if (status) { 3396 if (!qg_list) 3397 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 3398 vmvf_num, hw->adminq.sq_last_status); 3399 else 3400 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 3401 LE16_TO_CPU(qg_list[0].q_id[0]), 3402 hw->adminq.sq_last_status); 3403 } 3404 return status; 3405 } 3406 3407 /** 3408 * ice_aq_move_recfg_lan_txq 3409 * @hw: pointer to the hardware structure 3410 * @num_qs: number of queues to move/reconfigure 3411 * @is_move: true if this operation involves node movement 3412 * @is_tc_change: true if this operation involves a TC change 3413 * @subseq_call: true if this operation is a subsequent call 3414 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN 3415 * @timeout: timeout in units of 100 usec (valid values 0-50) 3416 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN 3417 * @buf: struct containing src/dest TEID and per-queue info 3418 * @buf_size: size of buffer for indirect command 3419 * @txqs_moved: out param, number of queues successfully moved 3420 * @cd: pointer to command details structure or NULL 3421 * 3422 * Move / Reconfigure Tx LAN queues (0x0C32) 3423 */ 3424 enum ice_status 3425 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move, 3426 bool is_tc_change, bool subseq_call, bool flush_pipe, 3427 u8 timeout, u32 *blocked_cgds, 3428 struct ice_aqc_move_txqs_data *buf, u16 buf_size, 3429 u8 *txqs_moved, struct ice_sq_cd *cd) 3430 { 3431 struct ice_aqc_move_txqs *cmd; 3432 struct ice_aq_desc desc; 3433 enum ice_status status; 3434 3435 cmd = &desc.params.move_txqs; 3436 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs); 3437 3438 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50 3439 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX) 3440 return ICE_ERR_PARAM; 3441 3442 if (is_tc_change && !flush_pipe && !blocked_cgds) 3443 return ICE_ERR_PARAM; 3444 3445 if (!is_move && !is_tc_change) 3446 return ICE_ERR_PARAM; 3447 3448 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3449 3450 if (is_move) 3451 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE; 3452 3453 if (is_tc_change) 3454 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE; 3455 3456 if (subseq_call) 3457 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL; 3458 3459 if (flush_pipe) 3460 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE; 3461 3462 cmd->num_qs = num_qs; 3463 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) & 3464 ICE_AQC_Q_CMD_TIMEOUT_M); 3465 3466 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 3467 3468 if (!status && txqs_moved) 3469 *txqs_moved = cmd->num_qs; 3470 3471 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN && 3472 is_tc_change && !flush_pipe) 3473 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds); 3474 3475 return status; 3476 } 3477 3478 /* End of FW Admin Queue command wrappers */ 3479 3480 /** 3481 * ice_write_byte - write a byte to a packed context structure 3482 * @src_ctx: the context structure to read from 3483 * @dest_ctx: the context to be written to 3484 * @ce_info: a description of the struct to be filled 3485 */ 3486 static void 3487 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3488 { 3489 u8 src_byte, dest_byte, mask; 3490 u8 *from, *dest; 3491 u16 shift_width; 3492 3493 /* copy from the next struct field */ 3494 from = src_ctx + ce_info->offset; 3495 3496 /* prepare the bits and mask */ 3497 shift_width = ce_info->lsb % 8; 3498 mask = (u8)(BIT(ce_info->width) - 1); 3499 3500 src_byte = *from; 3501 src_byte &= mask; 3502 3503 /* shift to correct alignment */ 3504 mask <<= shift_width; 3505 src_byte <<= shift_width; 3506 3507 /* get the current bits from the target bit string */ 3508 dest = dest_ctx + (ce_info->lsb / 8); 3509 3510 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 3511 3512 dest_byte &= ~mask; /* get the bits not changing */ 3513 dest_byte |= src_byte; /* add in the new bits */ 3514 3515 /* put it all back */ 3516 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 3517 } 3518 3519 /** 3520 * ice_write_word - write a word to a packed context structure 3521 * @src_ctx: the context structure to read from 3522 * @dest_ctx: the context to be written to 3523 * @ce_info: a description of the struct to be filled 3524 */ 3525 static void 3526 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3527 { 3528 u16 src_word, mask; 3529 __le16 dest_word; 3530 u8 *from, *dest; 3531 u16 shift_width; 3532 3533 /* copy from the next struct field */ 3534 from = src_ctx + ce_info->offset; 3535 3536 /* prepare the bits and mask */ 3537 shift_width = ce_info->lsb % 8; 3538 mask = BIT(ce_info->width) - 1; 3539 3540 /* don't swizzle the bits until after the mask because the mask bits 3541 * will be in a different bit position on big endian machines 3542 */ 3543 src_word = *(u16 *)from; 3544 src_word &= mask; 3545 3546 /* shift to correct alignment */ 3547 mask <<= shift_width; 3548 src_word <<= shift_width; 3549 3550 /* get the current bits from the target bit string */ 3551 dest = dest_ctx + (ce_info->lsb / 8); 3552 3553 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA); 3554 3555 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */ 3556 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */ 3557 3558 /* put it all back */ 3559 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 3560 } 3561 3562 /** 3563 * ice_write_dword - write a dword to a packed context structure 3564 * @src_ctx: the context structure to read from 3565 * @dest_ctx: the context to be written to 3566 * @ce_info: a description of the struct to be filled 3567 */ 3568 static void 3569 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3570 { 3571 u32 src_dword, mask; 3572 __le32 dest_dword; 3573 u8 *from, *dest; 3574 u16 shift_width; 3575 3576 /* copy from the next struct field */ 3577 from = src_ctx + ce_info->offset; 3578 3579 /* prepare the bits and mask */ 3580 shift_width = ce_info->lsb % 8; 3581 3582 /* if the field width is exactly 32 on an x86 machine, then the shift 3583 * operation will not work because the SHL instructions count is masked 3584 * to 5 bits so the shift will do nothing 3585 */ 3586 if (ce_info->width < 32) 3587 mask = BIT(ce_info->width) - 1; 3588 else 3589 mask = (u32)~0; 3590 3591 /* don't swizzle the bits until after the mask because the mask bits 3592 * will be in a different bit position on big endian machines 3593 */ 3594 src_dword = *(u32 *)from; 3595 src_dword &= mask; 3596 3597 /* shift to correct alignment */ 3598 mask <<= shift_width; 3599 src_dword <<= shift_width; 3600 3601 /* get the current bits from the target bit string */ 3602 dest = dest_ctx + (ce_info->lsb / 8); 3603 3604 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA); 3605 3606 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */ 3607 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */ 3608 3609 /* put it all back */ 3610 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 3611 } 3612 3613 /** 3614 * ice_write_qword - write a qword to a packed context structure 3615 * @src_ctx: the context structure to read from 3616 * @dest_ctx: the context to be written to 3617 * @ce_info: a description of the struct to be filled 3618 */ 3619 static void 3620 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3621 { 3622 u64 src_qword, mask; 3623 __le64 dest_qword; 3624 u8 *from, *dest; 3625 u16 shift_width; 3626 3627 /* copy from the next struct field */ 3628 from = src_ctx + ce_info->offset; 3629 3630 /* prepare the bits and mask */ 3631 shift_width = ce_info->lsb % 8; 3632 3633 /* if the field width is exactly 64 on an x86 machine, then the shift 3634 * operation will not work because the SHL instructions count is masked 3635 * to 6 bits so the shift will do nothing 3636 */ 3637 if (ce_info->width < 64) 3638 mask = BIT_ULL(ce_info->width) - 1; 3639 else 3640 mask = (u64)~0; 3641 3642 /* don't swizzle the bits until after the mask because the mask bits 3643 * will be in a different bit position on big endian machines 3644 */ 3645 src_qword = *(u64 *)from; 3646 src_qword &= mask; 3647 3648 /* shift to correct alignment */ 3649 mask <<= shift_width; 3650 src_qword <<= shift_width; 3651 3652 /* get the current bits from the target bit string */ 3653 dest = dest_ctx + (ce_info->lsb / 8); 3654 3655 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA); 3656 3657 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */ 3658 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */ 3659 3660 /* put it all back */ 3661 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 3662 } 3663 3664 /** 3665 * ice_set_ctx - set context bits in packed structure 3666 * @hw: pointer to the hardware structure 3667 * @src_ctx: pointer to a generic non-packed context structure 3668 * @dest_ctx: pointer to memory for the packed structure 3669 * @ce_info: a description of the structure to be transformed 3670 */ 3671 enum ice_status 3672 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 3673 const struct ice_ctx_ele *ce_info) 3674 { 3675 int f; 3676 3677 for (f = 0; ce_info[f].width; f++) { 3678 /* We have to deal with each element of the FW response 3679 * using the correct size so that we are correct regardless 3680 * of the endianness of the machine. 3681 */ 3682 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 3683 ice_debug(hw, ICE_DBG_QCTX, 3684 "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 3685 f, ce_info[f].width, ce_info[f].size_of); 3686 continue; 3687 } 3688 switch (ce_info[f].size_of) { 3689 case sizeof(u8): 3690 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 3691 break; 3692 case sizeof(u16): 3693 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 3694 break; 3695 case sizeof(u32): 3696 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 3697 break; 3698 case sizeof(u64): 3699 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 3700 break; 3701 default: 3702 return ICE_ERR_INVAL_SIZE; 3703 } 3704 } 3705 3706 return ICE_SUCCESS; 3707 } 3708 3709 /** 3710 * ice_read_byte - read context byte into struct 3711 * @src_ctx: the context structure to read from 3712 * @dest_ctx: the context to be written to 3713 * @ce_info: a description of the struct to be filled 3714 */ 3715 static void 3716 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 3717 { 3718 u8 dest_byte, mask; 3719 u8 *src, *target; 3720 u16 shift_width; 3721 3722 /* prepare the bits and mask */ 3723 shift_width = ce_info->lsb % 8; 3724 mask = (u8)(BIT(ce_info->width) - 1); 3725 3726 /* shift to correct alignment */ 3727 mask <<= shift_width; 3728 3729 /* get the current bits from the src bit string */ 3730 src = src_ctx + (ce_info->lsb / 8); 3731 3732 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 3733 3734 dest_byte &= ~(mask); 3735 3736 dest_byte >>= shift_width; 3737 3738 /* get the address from the struct field */ 3739 target = dest_ctx + ce_info->offset; 3740 3741 /* put it back in the struct */ 3742 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 3743 } 3744 3745 /** 3746 * ice_read_word - read context word into struct 3747 * @src_ctx: the context structure to read from 3748 * @dest_ctx: the context to be written to 3749 * @ce_info: a description of the struct to be filled 3750 */ 3751 static void 3752 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 3753 { 3754 u16 dest_word, mask; 3755 u8 *src, *target; 3756 __le16 src_word; 3757 u16 shift_width; 3758 3759 /* prepare the bits and mask */ 3760 shift_width = ce_info->lsb % 8; 3761 mask = BIT(ce_info->width) - 1; 3762 3763 /* shift to correct alignment */ 3764 mask <<= shift_width; 3765 3766 /* get the current bits from the src bit string */ 3767 src = src_ctx + (ce_info->lsb / 8); 3768 3769 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA); 3770 3771 /* the data in the memory is stored as little endian so mask it 3772 * correctly 3773 */ 3774 src_word &= ~(CPU_TO_LE16(mask)); 3775 3776 /* get the data back into host order before shifting */ 3777 dest_word = LE16_TO_CPU(src_word); 3778 3779 dest_word >>= shift_width; 3780 3781 /* get the address from the struct field */ 3782 target = dest_ctx + ce_info->offset; 3783 3784 /* put it back in the struct */ 3785 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 3786 } 3787 3788 /** 3789 * ice_read_dword - read context dword into struct 3790 * @src_ctx: the context structure to read from 3791 * @dest_ctx: the context to be written to 3792 * @ce_info: a description of the struct to be filled 3793 */ 3794 static void 3795 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 3796 { 3797 u32 dest_dword, mask; 3798 __le32 src_dword; 3799 u8 *src, *target; 3800 u16 shift_width; 3801 3802 /* prepare the bits and mask */ 3803 shift_width = ce_info->lsb % 8; 3804 3805 /* if the field width is exactly 32 on an x86 machine, then the shift 3806 * operation will not work because the SHL instructions count is masked 3807 * to 5 bits so the shift will do nothing 3808 */ 3809 if (ce_info->width < 32) 3810 mask = BIT(ce_info->width) - 1; 3811 else 3812 mask = (u32)~0; 3813 3814 /* shift to correct alignment */ 3815 mask <<= shift_width; 3816 3817 /* get the current bits from the src bit string */ 3818 src = src_ctx + (ce_info->lsb / 8); 3819 3820 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA); 3821 3822 /* the data in the memory is stored as little endian so mask it 3823 * correctly 3824 */ 3825 src_dword &= ~(CPU_TO_LE32(mask)); 3826 3827 /* get the data back into host order before shifting */ 3828 dest_dword = LE32_TO_CPU(src_dword); 3829 3830 dest_dword >>= shift_width; 3831 3832 /* get the address from the struct field */ 3833 target = dest_ctx + ce_info->offset; 3834 3835 /* put it back in the struct */ 3836 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 3837 } 3838 3839 /** 3840 * ice_read_qword - read context qword into struct 3841 * @src_ctx: the context structure to read from 3842 * @dest_ctx: the context to be written to 3843 * @ce_info: a description of the struct to be filled 3844 */ 3845 static void 3846 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 3847 { 3848 u64 dest_qword, mask; 3849 __le64 src_qword; 3850 u8 *src, *target; 3851 u16 shift_width; 3852 3853 /* prepare the bits and mask */ 3854 shift_width = ce_info->lsb % 8; 3855 3856 /* if the field width is exactly 64 on an x86 machine, then the shift 3857 * operation will not work because the SHL instructions count is masked 3858 * to 6 bits so the shift will do nothing 3859 */ 3860 if (ce_info->width < 64) 3861 mask = BIT_ULL(ce_info->width) - 1; 3862 else 3863 mask = (u64)~0; 3864 3865 /* shift to correct alignment */ 3866 mask <<= shift_width; 3867 3868 /* get the current bits from the src bit string */ 3869 src = src_ctx + (ce_info->lsb / 8); 3870 3871 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA); 3872 3873 /* the data in the memory is stored as little endian so mask it 3874 * correctly 3875 */ 3876 src_qword &= ~(CPU_TO_LE64(mask)); 3877 3878 /* get the data back into host order before shifting */ 3879 dest_qword = LE64_TO_CPU(src_qword); 3880 3881 dest_qword >>= shift_width; 3882 3883 /* get the address from the struct field */ 3884 target = dest_ctx + ce_info->offset; 3885 3886 /* put it back in the struct */ 3887 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 3888 } 3889 3890 /** 3891 * ice_get_ctx - extract context bits from a packed structure 3892 * @src_ctx: pointer to a generic packed context structure 3893 * @dest_ctx: pointer to a generic non-packed context structure 3894 * @ce_info: a description of the structure to be read from 3895 */ 3896 enum ice_status 3897 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 3898 { 3899 int f; 3900 3901 for (f = 0; ce_info[f].width; f++) { 3902 switch (ce_info[f].size_of) { 3903 case 1: 3904 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]); 3905 break; 3906 case 2: 3907 ice_read_word(src_ctx, dest_ctx, &ce_info[f]); 3908 break; 3909 case 4: 3910 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]); 3911 break; 3912 case 8: 3913 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]); 3914 break; 3915 default: 3916 /* nothing to do, just keep going */ 3917 break; 3918 } 3919 } 3920 3921 return ICE_SUCCESS; 3922 } 3923 3924 /** 3925 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 3926 * @hw: pointer to the HW struct 3927 * @vsi_handle: software VSI handle 3928 * @tc: TC number 3929 * @q_handle: software queue handle 3930 */ 3931 struct ice_q_ctx * 3932 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 3933 { 3934 struct ice_vsi_ctx *vsi; 3935 struct ice_q_ctx *q_ctx; 3936 3937 vsi = ice_get_vsi_ctx(hw, vsi_handle); 3938 if (!vsi) 3939 return NULL; 3940 if (q_handle >= vsi->num_lan_q_entries[tc]) 3941 return NULL; 3942 if (!vsi->lan_q_ctx[tc]) 3943 return NULL; 3944 q_ctx = vsi->lan_q_ctx[tc]; 3945 return &q_ctx[q_handle]; 3946 } 3947 3948 /** 3949 * ice_ena_vsi_txq 3950 * @pi: port information structure 3951 * @vsi_handle: software VSI handle 3952 * @tc: TC number 3953 * @q_handle: software queue handle 3954 * @num_qgrps: Number of added queue groups 3955 * @buf: list of queue groups to be added 3956 * @buf_size: size of buffer for indirect command 3957 * @cd: pointer to command details structure or NULL 3958 * 3959 * This function adds one LAN queue 3960 */ 3961 enum ice_status 3962 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 3963 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 3964 struct ice_sq_cd *cd) 3965 { 3966 struct ice_aqc_txsched_elem_data node = { 0 }; 3967 struct ice_sched_node *parent; 3968 struct ice_q_ctx *q_ctx; 3969 enum ice_status status; 3970 struct ice_hw *hw; 3971 3972 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3973 return ICE_ERR_CFG; 3974 3975 if (num_qgrps > 1 || buf->num_txqs > 1) 3976 return ICE_ERR_MAX_LIMIT; 3977 3978 hw = pi->hw; 3979 3980 if (!ice_is_vsi_valid(hw, vsi_handle)) 3981 return ICE_ERR_PARAM; 3982 3983 ice_acquire_lock(&pi->sched_lock); 3984 3985 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 3986 if (!q_ctx) { 3987 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 3988 q_handle); 3989 status = ICE_ERR_PARAM; 3990 goto ena_txq_exit; 3991 } 3992 3993 /* find a parent node */ 3994 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 3995 ICE_SCHED_NODE_OWNER_LAN); 3996 if (!parent) { 3997 status = ICE_ERR_PARAM; 3998 goto ena_txq_exit; 3999 } 4000 4001 buf->parent_teid = parent->info.node_teid; 4002 node.parent_teid = parent->info.node_teid; 4003 /* Mark that the values in the "generic" section as valid. The default 4004 * value in the "generic" section is zero. This means that : 4005 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4006 * - 0 priority among siblings, indicated by Bit 1-3. 4007 * - WFQ, indicated by Bit 4. 4008 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4009 * Bit 5-6. 4010 * - Bit 7 is reserved. 4011 * Without setting the generic section as valid in valid_sections, the 4012 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4013 */ 4014 buf->txqs[0].info.valid_sections = 4015 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4016 ICE_AQC_ELEM_VALID_EIR; 4017 buf->txqs[0].info.generic = 0; 4018 buf->txqs[0].info.cir_bw.bw_profile_idx = 4019 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 4020 buf->txqs[0].info.cir_bw.bw_alloc = 4021 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 4022 buf->txqs[0].info.eir_bw.bw_profile_idx = 4023 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 4024 buf->txqs[0].info.eir_bw.bw_alloc = 4025 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 4026 4027 /* add the LAN queue */ 4028 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4029 if (status != ICE_SUCCESS) { 4030 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4031 LE16_TO_CPU(buf->txqs[0].txq_id), 4032 hw->adminq.sq_last_status); 4033 goto ena_txq_exit; 4034 } 4035 4036 node.node_teid = buf->txqs[0].q_teid; 4037 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4038 q_ctx->q_handle = q_handle; 4039 q_ctx->q_teid = LE32_TO_CPU(node.node_teid); 4040 4041 /* add a leaf node into scheduler tree queue layer */ 4042 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 4043 if (!status) 4044 status = ice_sched_replay_q_bw(pi, q_ctx); 4045 4046 ena_txq_exit: 4047 ice_release_lock(&pi->sched_lock); 4048 return status; 4049 } 4050 4051 /** 4052 * ice_dis_vsi_txq 4053 * @pi: port information structure 4054 * @vsi_handle: software VSI handle 4055 * @tc: TC number 4056 * @num_queues: number of queues 4057 * @q_handles: pointer to software queue handle array 4058 * @q_ids: pointer to the q_id array 4059 * @q_teids: pointer to queue node teids 4060 * @rst_src: if called due to reset, specifies the reset source 4061 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4062 * @cd: pointer to command details structure or NULL 4063 * 4064 * This function removes queues and their corresponding nodes in SW DB 4065 */ 4066 enum ice_status 4067 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4068 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4069 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4070 struct ice_sq_cd *cd) 4071 { 4072 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 4073 struct ice_aqc_dis_txq_item qg_list; 4074 struct ice_q_ctx *q_ctx; 4075 u16 i; 4076 4077 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4078 return ICE_ERR_CFG; 4079 4080 if (!num_queues) { 4081 /* if queue is disabled already yet the disable queue command 4082 * has to be sent to complete the VF reset, then call 4083 * ice_aq_dis_lan_txq without any queue information 4084 */ 4085 if (rst_src) 4086 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src, 4087 vmvf_num, NULL); 4088 return ICE_ERR_CFG; 4089 } 4090 4091 ice_acquire_lock(&pi->sched_lock); 4092 4093 for (i = 0; i < num_queues; i++) { 4094 struct ice_sched_node *node; 4095 4096 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4097 if (!node) 4098 continue; 4099 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]); 4100 if (!q_ctx) { 4101 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4102 q_handles[i]); 4103 continue; 4104 } 4105 if (q_ctx->q_handle != q_handles[i]) { 4106 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4107 q_ctx->q_handle, q_handles[i]); 4108 continue; 4109 } 4110 qg_list.parent_teid = node->info.parent_teid; 4111 qg_list.num_qs = 1; 4112 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]); 4113 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list, 4114 sizeof(qg_list), rst_src, vmvf_num, 4115 cd); 4116 4117 if (status != ICE_SUCCESS) 4118 break; 4119 ice_free_sched_node(pi, node); 4120 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 4121 } 4122 ice_release_lock(&pi->sched_lock); 4123 return status; 4124 } 4125 4126 /** 4127 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4128 * @pi: port information structure 4129 * @vsi_handle: software VSI handle 4130 * @tc_bitmap: TC bitmap 4131 * @maxqs: max queues array per TC 4132 * @owner: LAN or RDMA 4133 * 4134 * This function adds/updates the VSI queues per TC. 4135 */ 4136 static enum ice_status 4137 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4138 u16 *maxqs, u8 owner) 4139 { 4140 enum ice_status status = ICE_SUCCESS; 4141 u8 i; 4142 4143 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4144 return ICE_ERR_CFG; 4145 4146 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4147 return ICE_ERR_PARAM; 4148 4149 ice_acquire_lock(&pi->sched_lock); 4150 4151 ice_for_each_traffic_class(i) { 4152 /* configuration is possible only if TC node is present */ 4153 if (!ice_sched_get_tc_node(pi, i)) 4154 continue; 4155 4156 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4157 ice_is_tc_ena(tc_bitmap, i)); 4158 if (status) 4159 break; 4160 } 4161 4162 ice_release_lock(&pi->sched_lock); 4163 return status; 4164 } 4165 4166 /** 4167 * ice_cfg_vsi_lan - configure VSI LAN queues 4168 * @pi: port information structure 4169 * @vsi_handle: software VSI handle 4170 * @tc_bitmap: TC bitmap 4171 * @max_lanqs: max LAN queues array per TC 4172 * 4173 * This function adds/updates the VSI LAN queues per TC. 4174 */ 4175 enum ice_status 4176 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4177 u16 *max_lanqs) 4178 { 4179 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4180 ICE_SCHED_NODE_OWNER_LAN); 4181 } 4182 4183 /** 4184 * ice_is_main_vsi - checks whether the VSI is main VSI 4185 * @hw: pointer to the HW struct 4186 * @vsi_handle: VSI handle 4187 * 4188 * Checks whether the VSI is the main VSI (the first PF VSI created on 4189 * given PF). 4190 */ 4191 static bool ice_is_main_vsi(struct ice_hw *hw, u16 vsi_handle) 4192 { 4193 return vsi_handle == ICE_MAIN_VSI_HANDLE && hw->vsi_ctx[vsi_handle]; 4194 } 4195 4196 /** 4197 * ice_replay_pre_init - replay pre initialization 4198 * @hw: pointer to the HW struct 4199 * @sw: pointer to switch info struct for which function initializes filters 4200 * 4201 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 4202 */ 4203 static enum ice_status 4204 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw) 4205 { 4206 u8 i; 4207 4208 /* Delete old entries from replay filter list head if there is any */ 4209 ice_rm_sw_replay_rule_info(hw, sw); 4210 /* In start of replay, move entries into replay_rules list, it 4211 * will allow adding rules entries back to filt_rules list, 4212 * which is operational list. 4213 */ 4214 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 4215 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules, 4216 &sw->recp_list[i].filt_replay_rules); 4217 ice_sched_replay_agg_vsi_preinit(hw); 4218 4219 return ice_sched_replay_tc_node_bw(hw->port_info); 4220 } 4221 4222 /** 4223 * ice_replay_vsi - replay VSI configuration 4224 * @hw: pointer to the HW struct 4225 * @vsi_handle: driver VSI handle 4226 * 4227 * Restore all VSI configuration after reset. It is required to call this 4228 * function with main VSI first. 4229 */ 4230 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 4231 { 4232 struct ice_switch_info *sw = hw->switch_info; 4233 struct ice_port_info *pi = hw->port_info; 4234 enum ice_status status; 4235 4236 if (!ice_is_vsi_valid(hw, vsi_handle)) 4237 return ICE_ERR_PARAM; 4238 4239 /* Replay pre-initialization if there is any */ 4240 if (ice_is_main_vsi(hw, vsi_handle)) { 4241 status = ice_replay_pre_init(hw, sw); 4242 if (status) 4243 return status; 4244 } 4245 /* Replay per VSI all RSS configurations */ 4246 status = ice_replay_rss_cfg(hw, vsi_handle); 4247 if (status) 4248 return status; 4249 /* Replay per VSI all filters */ 4250 status = ice_replay_vsi_all_fltr(hw, pi, vsi_handle); 4251 if (!status) 4252 status = ice_replay_vsi_agg(hw, vsi_handle); 4253 return status; 4254 } 4255 4256 /** 4257 * ice_replay_post - post replay configuration cleanup 4258 * @hw: pointer to the HW struct 4259 * 4260 * Post replay cleanup. 4261 */ 4262 void ice_replay_post(struct ice_hw *hw) 4263 { 4264 /* Delete old entries from replay filter list head */ 4265 ice_rm_all_sw_replay_rule_info(hw); 4266 ice_sched_replay_agg(hw); 4267 } 4268 4269 /** 4270 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 4271 * @hw: ptr to the hardware info 4272 * @reg: offset of 64 bit HW register to read from 4273 * @prev_stat_loaded: bool to specify if previous stats are loaded 4274 * @prev_stat: ptr to previous loaded stat value 4275 * @cur_stat: ptr to current stat value 4276 */ 4277 void 4278 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4279 u64 *prev_stat, u64 *cur_stat) 4280 { 4281 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 4282 4283 /* device stats are not reset at PFR, they likely will not be zeroed 4284 * when the driver starts. Thus, save the value from the first read 4285 * without adding to the statistic value so that we report stats which 4286 * count up from zero. 4287 */ 4288 if (!prev_stat_loaded) { 4289 *prev_stat = new_data; 4290 return; 4291 } 4292 4293 /* Calculate the difference between the new and old values, and then 4294 * add it to the software stat value. 4295 */ 4296 if (new_data >= *prev_stat) 4297 *cur_stat += new_data - *prev_stat; 4298 else 4299 /* to manage the potential roll-over */ 4300 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 4301 4302 /* Update the previously stored value to prepare for next read */ 4303 *prev_stat = new_data; 4304 } 4305 4306 /** 4307 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 4308 * @hw: ptr to the hardware info 4309 * @reg: offset of HW register to read from 4310 * @prev_stat_loaded: bool to specify if previous stats are loaded 4311 * @prev_stat: ptr to previous loaded stat value 4312 * @cur_stat: ptr to current stat value 4313 */ 4314 void 4315 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4316 u64 *prev_stat, u64 *cur_stat) 4317 { 4318 u32 new_data; 4319 4320 new_data = rd32(hw, reg); 4321 4322 /* device stats are not reset at PFR, they likely will not be zeroed 4323 * when the driver starts. Thus, save the value from the first read 4324 * without adding to the statistic value so that we report stats which 4325 * count up from zero. 4326 */ 4327 if (!prev_stat_loaded) { 4328 *prev_stat = new_data; 4329 return; 4330 } 4331 4332 /* Calculate the difference between the new and old values, and then 4333 * add it to the software stat value. 4334 */ 4335 if (new_data >= *prev_stat) 4336 *cur_stat += new_data - *prev_stat; 4337 else 4338 /* to manage the potential roll-over */ 4339 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 4340 4341 /* Update the previously stored value to prepare for next read */ 4342 *prev_stat = new_data; 4343 } 4344 4345 /** 4346 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values 4347 * @hw: ptr to the hardware info 4348 * @vsi_handle: VSI handle 4349 * @prev_stat_loaded: bool to specify if the previous stat values are loaded 4350 * @cur_stats: ptr to current stats structure 4351 * 4352 * The GLV_REPC statistic register actually tracks two 16bit statistics, and 4353 * thus cannot be read using the normal ice_stat_update32 function. 4354 * 4355 * Read the GLV_REPC register associated with the given VSI, and update the 4356 * rx_no_desc and rx_error values in the ice_eth_stats structure. 4357 * 4358 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be 4359 * cleared each time it's read. 4360 * 4361 * Note that the GLV_RDPC register also counts the causes that would trigger 4362 * GLV_REPC. However, it does not give the finer grained detail about why the 4363 * packets are being dropped. The GLV_REPC values can be used to distinguish 4364 * whether Rx packets are dropped due to errors or due to no available 4365 * descriptors. 4366 */ 4367 void 4368 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded, 4369 struct ice_eth_stats *cur_stats) 4370 { 4371 u16 vsi_num, no_desc, error_cnt; 4372 u32 repc; 4373 4374 if (!ice_is_vsi_valid(hw, vsi_handle)) 4375 return; 4376 4377 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle); 4378 4379 /* If we haven't loaded stats yet, just clear the current value */ 4380 if (!prev_stat_loaded) { 4381 wr32(hw, GLV_REPC(vsi_num), 0); 4382 return; 4383 } 4384 4385 repc = rd32(hw, GLV_REPC(vsi_num)); 4386 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S; 4387 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S; 4388 4389 /* Clear the count by writing to the stats register */ 4390 wr32(hw, GLV_REPC(vsi_num), 0); 4391 4392 cur_stats->rx_no_desc += no_desc; 4393 cur_stats->rx_errors += error_cnt; 4394 } 4395 4396 /** 4397 * ice_sched_query_elem - query element information from HW 4398 * @hw: pointer to the HW struct 4399 * @node_teid: node TEID to be queried 4400 * @buf: buffer to element information 4401 * 4402 * This function queries HW element information 4403 */ 4404 enum ice_status 4405 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 4406 struct ice_aqc_get_elem *buf) 4407 { 4408 u16 buf_size, num_elem_ret = 0; 4409 enum ice_status status; 4410 4411 buf_size = sizeof(*buf); 4412 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM); 4413 buf->generic[0].node_teid = CPU_TO_LE32(node_teid); 4414 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 4415 NULL); 4416 if (status != ICE_SUCCESS || num_elem_ret != 1) 4417 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 4418 return status; 4419 } 4420 4421 /** 4422 * ice_get_fw_mode - returns FW mode 4423 * @hw: pointer to the HW struct 4424 */ 4425 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw) 4426 { 4427 #define ICE_FW_MODE_DBG_M BIT(0) 4428 #define ICE_FW_MODE_REC_M BIT(1) 4429 #define ICE_FW_MODE_ROLLBACK_M BIT(2) 4430 u32 fw_mode; 4431 4432 /* check the current FW mode */ 4433 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M; 4434 4435 if (fw_mode & ICE_FW_MODE_DBG_M) 4436 return ICE_FW_MODE_DBG; 4437 else if (fw_mode & ICE_FW_MODE_REC_M) 4438 return ICE_FW_MODE_REC; 4439 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M) 4440 return ICE_FW_MODE_ROLLBACK; 4441 else 4442 return ICE_FW_MODE_NORMAL; 4443 } 4444 4445 /** 4446 * ice_fw_supports_link_override 4447 * @hw: pointer to the hardware structure 4448 * 4449 * Checks if the firmware supports link override 4450 */ 4451 bool ice_fw_supports_link_override(struct ice_hw *hw) 4452 { 4453 /* Currently, only supported for E810 devices */ 4454 if (hw->mac_type != ICE_MAC_E810) 4455 return false; 4456 4457 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) { 4458 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN) 4459 return true; 4460 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN && 4461 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH) 4462 return true; 4463 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) { 4464 return true; 4465 } 4466 4467 return false; 4468 } 4469 4470 /** 4471 * ice_get_link_default_override 4472 * @ldo: pointer to the link default override struct 4473 * @pi: pointer to the port info struct 4474 * 4475 * Gets the link default override for a port 4476 */ 4477 enum ice_status 4478 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 4479 struct ice_port_info *pi) 4480 { 4481 u16 i, tlv, tlv_len, tlv_start, buf, offset; 4482 struct ice_hw *hw = pi->hw; 4483 enum ice_status status; 4484 4485 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 4486 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 4487 if (status) { 4488 ice_debug(hw, ICE_DBG_INIT, 4489 "Failed to read link override TLV.\n"); 4490 return status; 4491 } 4492 4493 /* Each port has its own config; calculate for our port */ 4494 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 4495 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 4496 4497 /* link options first */ 4498 status = ice_read_sr_word(hw, tlv_start, &buf); 4499 if (status) { 4500 ice_debug(hw, ICE_DBG_INIT, 4501 "Failed to read override link options.\n"); 4502 return status; 4503 } 4504 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 4505 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 4506 ICE_LINK_OVERRIDE_PHY_CFG_S; 4507 4508 /* link PHY config */ 4509 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 4510 status = ice_read_sr_word(hw, offset, &buf); 4511 if (status) { 4512 ice_debug(hw, ICE_DBG_INIT, 4513 "Failed to read override phy config.\n"); 4514 return status; 4515 } 4516 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 4517 4518 /* PHY types low */ 4519 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 4520 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4521 status = ice_read_sr_word(hw, (offset + i), &buf); 4522 if (status) { 4523 ice_debug(hw, ICE_DBG_INIT, 4524 "Failed to read override link options.\n"); 4525 return status; 4526 } 4527 /* shift 16 bits at a time to fill 64 bits */ 4528 ldo->phy_type_low |= ((u64)buf << (i * 16)); 4529 } 4530 4531 /* PHY types high */ 4532 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 4533 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 4534 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4535 status = ice_read_sr_word(hw, (offset + i), &buf); 4536 if (status) { 4537 ice_debug(hw, ICE_DBG_INIT, 4538 "Failed to read override link options.\n"); 4539 return status; 4540 } 4541 /* shift 16 bits at a time to fill 64 bits */ 4542 ldo->phy_type_high |= ((u64)buf << (i * 16)); 4543 } 4544 4545 return status; 4546 } 4547 4548 /** 4549 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 4550 * @caps: get PHY capability data 4551 */ 4552 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 4553 { 4554 if (caps->caps & ICE_AQC_PHY_AN_MODE || 4555 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 4556 ICE_AQC_PHY_AN_EN_CLAUSE73 | 4557 ICE_AQC_PHY_AN_EN_CLAUSE37)) 4558 return true; 4559 4560 return false; 4561 } 4562