1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2021 Intel Corporation 3 */ 4 5 #include "ice_common.h" 6 #include "ice_sched.h" 7 #include "ice_adminq_cmd.h" 8 9 #include "ice_flow.h" 10 #include "ice_switch.h" 11 12 #define ICE_PF_RESET_WAIT_COUNT 300 13 14 /** 15 * ice_set_mac_type - Sets MAC type 16 * @hw: pointer to the HW structure 17 * 18 * This function sets the MAC type of the adapter based on the 19 * vendor ID and device ID stored in the HW structure. 20 */ 21 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 22 { 23 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 24 25 if (hw->vendor_id != ICE_INTEL_VENDOR_ID) 26 return ICE_ERR_DEVICE_NOT_SUPPORTED; 27 28 switch (hw->device_id) { 29 case ICE_DEV_ID_E810C_BACKPLANE: 30 case ICE_DEV_ID_E810C_QSFP: 31 case ICE_DEV_ID_E810C_SFP: 32 case ICE_DEV_ID_E810_XXV_BACKPLANE: 33 case ICE_DEV_ID_E810_XXV_QSFP: 34 case ICE_DEV_ID_E810_XXV_SFP: 35 hw->mac_type = ICE_MAC_E810; 36 break; 37 case ICE_DEV_ID_E822C_10G_BASE_T: 38 case ICE_DEV_ID_E822C_BACKPLANE: 39 case ICE_DEV_ID_E822C_QSFP: 40 case ICE_DEV_ID_E822C_SFP: 41 case ICE_DEV_ID_E822C_SGMII: 42 case ICE_DEV_ID_E822L_10G_BASE_T: 43 case ICE_DEV_ID_E822L_BACKPLANE: 44 case ICE_DEV_ID_E822L_SFP: 45 case ICE_DEV_ID_E822L_SGMII: 46 case ICE_DEV_ID_E823L_10G_BASE_T: 47 case ICE_DEV_ID_E823L_1GBE: 48 case ICE_DEV_ID_E823L_BACKPLANE: 49 case ICE_DEV_ID_E823L_QSFP: 50 case ICE_DEV_ID_E823L_SFP: 51 hw->mac_type = ICE_MAC_GENERIC; 52 break; 53 default: 54 hw->mac_type = ICE_MAC_UNKNOWN; 55 break; 56 } 57 58 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 59 return ICE_SUCCESS; 60 } 61 62 /** 63 * ice_clear_pf_cfg - Clear PF configuration 64 * @hw: pointer to the hardware structure 65 * 66 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 67 * configuration, flow director filters, etc.). 68 */ 69 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 70 { 71 struct ice_aq_desc desc; 72 73 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 74 75 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 76 } 77 78 /** 79 * ice_aq_manage_mac_read - manage MAC address read command 80 * @hw: pointer to the HW struct 81 * @buf: a virtual buffer to hold the manage MAC read response 82 * @buf_size: Size of the virtual buffer 83 * @cd: pointer to command details structure or NULL 84 * 85 * This function is used to return per PF station MAC address (0x0107). 86 * NOTE: Upon successful completion of this command, MAC address information 87 * is returned in user specified buffer. Please interpret user specified 88 * buffer as "manage_mac_read" response. 89 * Response such as various MAC addresses are stored in HW struct (port.mac) 90 * ice_discover_dev_caps is expected to be called before this function is 91 * called. 92 */ 93 static enum ice_status 94 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 95 struct ice_sq_cd *cd) 96 { 97 struct ice_aqc_manage_mac_read_resp *resp; 98 struct ice_aqc_manage_mac_read *cmd; 99 struct ice_aq_desc desc; 100 enum ice_status status; 101 u16 flags; 102 u8 i; 103 104 cmd = &desc.params.mac_read; 105 106 if (buf_size < sizeof(*resp)) 107 return ICE_ERR_BUF_TOO_SHORT; 108 109 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 110 111 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 112 if (status) 113 return status; 114 115 resp = (struct ice_aqc_manage_mac_read_resp *)buf; 116 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 117 118 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 119 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 120 return ICE_ERR_CFG; 121 } 122 123 /* A single port can report up to two (LAN and WoL) addresses */ 124 for (i = 0; i < cmd->num_addr; i++) 125 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 126 ice_memcpy(hw->port_info->mac.lan_addr, 127 resp[i].mac_addr, ETH_ALEN, 128 ICE_DMA_TO_NONDMA); 129 ice_memcpy(hw->port_info->mac.perm_addr, 130 resp[i].mac_addr, 131 ETH_ALEN, ICE_DMA_TO_NONDMA); 132 break; 133 } 134 return ICE_SUCCESS; 135 } 136 137 /** 138 * ice_aq_get_phy_caps - returns PHY capabilities 139 * @pi: port information structure 140 * @qual_mods: report qualified modules 141 * @report_mode: report mode capabilities 142 * @pcaps: structure for PHY capabilities to be filled 143 * @cd: pointer to command details structure or NULL 144 * 145 * Returns the various PHY capabilities supported on the Port (0x0600) 146 */ 147 enum ice_status 148 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 149 struct ice_aqc_get_phy_caps_data *pcaps, 150 struct ice_sq_cd *cd) 151 { 152 struct ice_aqc_get_phy_caps *cmd; 153 u16 pcaps_size = sizeof(*pcaps); 154 struct ice_aq_desc desc; 155 enum ice_status status; 156 struct ice_hw *hw; 157 158 cmd = &desc.params.get_phy; 159 160 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 161 return ICE_ERR_PARAM; 162 hw = pi->hw; 163 164 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 165 !ice_fw_supports_report_dflt_cfg(hw)) 166 return ICE_ERR_PARAM; 167 168 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 169 170 if (qual_mods) 171 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM); 172 173 cmd->param0 |= CPU_TO_LE16(report_mode); 174 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 175 176 ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n", 177 report_mode); 178 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 179 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_low)); 180 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 181 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_high)); 182 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps); 183 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 184 pcaps->low_power_ctrl_an); 185 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap); 186 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", 187 pcaps->eeer_value); 188 ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n", 189 pcaps->link_fec_options); 190 ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n", 191 pcaps->module_compliance_enforcement); 192 ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n", 193 pcaps->extended_compliance_code); 194 ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n", 195 pcaps->module_type[0]); 196 ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n", 197 pcaps->module_type[1]); 198 ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n", 199 pcaps->module_type[2]); 200 201 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 202 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low); 203 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high); 204 ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 205 sizeof(pi->phy.link_info.module_type), 206 ICE_NONDMA_TO_NONDMA); 207 } 208 209 return status; 210 } 211 212 /** 213 * ice_aq_get_link_topo_handle - get link topology node return status 214 * @pi: port information structure 215 * @node_type: requested node type 216 * @cd: pointer to command details structure or NULL 217 * 218 * Get link topology node return status for specified node type (0x06E0) 219 * 220 * Node type cage can be used to determine if cage is present. If AQC 221 * returns error (ENOENT), then no cage present. If no cage present, then 222 * connection type is backplane or BASE-T. 223 */ 224 static enum ice_status 225 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 226 struct ice_sq_cd *cd) 227 { 228 struct ice_aqc_get_link_topo *cmd; 229 struct ice_aq_desc desc; 230 231 cmd = &desc.params.get_link_topo; 232 233 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 234 235 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 236 ICE_AQC_LINK_TOPO_NODE_CTX_S); 237 238 /* set node type */ 239 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 240 241 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 242 } 243 244 /** 245 * ice_is_media_cage_present 246 * @pi: port information structure 247 * 248 * Returns true if media cage is present, else false. If no cage, then 249 * media type is backplane or BASE-T. 250 */ 251 static bool ice_is_media_cage_present(struct ice_port_info *pi) 252 { 253 /* Node type cage can be used to determine if cage is present. If AQC 254 * returns error (ENOENT), then no cage present. If no cage present then 255 * connection type is backplane or BASE-T. 256 */ 257 return !ice_aq_get_link_topo_handle(pi, 258 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 259 NULL); 260 } 261 262 /** 263 * ice_get_media_type - Gets media type 264 * @pi: port information structure 265 */ 266 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 267 { 268 struct ice_link_status *hw_link_info; 269 270 if (!pi) 271 return ICE_MEDIA_UNKNOWN; 272 273 hw_link_info = &pi->phy.link_info; 274 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 275 /* If more than one media type is selected, report unknown */ 276 return ICE_MEDIA_UNKNOWN; 277 278 if (hw_link_info->phy_type_low) { 279 /* 1G SGMII is a special case where some DA cable PHYs 280 * may show this as an option when it really shouldn't 281 * be since SGMII is meant to be between a MAC and a PHY 282 * in a backplane. Try to detect this case and handle it 283 */ 284 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 285 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 286 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 287 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 288 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 289 return ICE_MEDIA_DA; 290 291 switch (hw_link_info->phy_type_low) { 292 case ICE_PHY_TYPE_LOW_1000BASE_SX: 293 case ICE_PHY_TYPE_LOW_1000BASE_LX: 294 case ICE_PHY_TYPE_LOW_10GBASE_SR: 295 case ICE_PHY_TYPE_LOW_10GBASE_LR: 296 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 297 case ICE_PHY_TYPE_LOW_25GBASE_SR: 298 case ICE_PHY_TYPE_LOW_25GBASE_LR: 299 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 300 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 301 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 302 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 303 case ICE_PHY_TYPE_LOW_50GBASE_SR: 304 case ICE_PHY_TYPE_LOW_50GBASE_FR: 305 case ICE_PHY_TYPE_LOW_50GBASE_LR: 306 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 307 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 308 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 309 case ICE_PHY_TYPE_LOW_100GBASE_DR: 310 return ICE_MEDIA_FIBER; 311 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 312 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 313 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 314 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 315 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 316 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 317 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 318 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 319 return ICE_MEDIA_FIBER; 320 case ICE_PHY_TYPE_LOW_100BASE_TX: 321 case ICE_PHY_TYPE_LOW_1000BASE_T: 322 case ICE_PHY_TYPE_LOW_2500BASE_T: 323 case ICE_PHY_TYPE_LOW_5GBASE_T: 324 case ICE_PHY_TYPE_LOW_10GBASE_T: 325 case ICE_PHY_TYPE_LOW_25GBASE_T: 326 return ICE_MEDIA_BASET; 327 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 328 case ICE_PHY_TYPE_LOW_25GBASE_CR: 329 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 330 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 331 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 332 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 333 case ICE_PHY_TYPE_LOW_50GBASE_CP: 334 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 335 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 336 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 337 return ICE_MEDIA_DA; 338 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 339 case ICE_PHY_TYPE_LOW_40G_XLAUI: 340 case ICE_PHY_TYPE_LOW_50G_LAUI2: 341 case ICE_PHY_TYPE_LOW_50G_AUI2: 342 case ICE_PHY_TYPE_LOW_50G_AUI1: 343 case ICE_PHY_TYPE_LOW_100G_AUI4: 344 case ICE_PHY_TYPE_LOW_100G_CAUI4: 345 if (ice_is_media_cage_present(pi)) 346 return ICE_MEDIA_AUI; 347 /* fall-through */ 348 case ICE_PHY_TYPE_LOW_1000BASE_KX: 349 case ICE_PHY_TYPE_LOW_2500BASE_KX: 350 case ICE_PHY_TYPE_LOW_2500BASE_X: 351 case ICE_PHY_TYPE_LOW_5GBASE_KR: 352 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 353 case ICE_PHY_TYPE_LOW_25GBASE_KR: 354 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 355 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 356 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 357 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 358 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 359 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 360 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 361 return ICE_MEDIA_BACKPLANE; 362 } 363 } else { 364 switch (hw_link_info->phy_type_high) { 365 case ICE_PHY_TYPE_HIGH_100G_AUI2: 366 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 367 if (ice_is_media_cage_present(pi)) 368 return ICE_MEDIA_AUI; 369 /* fall-through */ 370 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 371 return ICE_MEDIA_BACKPLANE; 372 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 373 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 374 return ICE_MEDIA_FIBER; 375 } 376 } 377 return ICE_MEDIA_UNKNOWN; 378 } 379 380 /** 381 * ice_aq_get_link_info 382 * @pi: port information structure 383 * @ena_lse: enable/disable LinkStatusEvent reporting 384 * @link: pointer to link status structure - optional 385 * @cd: pointer to command details structure or NULL 386 * 387 * Get Link Status (0x607). Returns the link status of the adapter. 388 */ 389 enum ice_status 390 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 391 struct ice_link_status *link, struct ice_sq_cd *cd) 392 { 393 struct ice_aqc_get_link_status_data link_data = { 0 }; 394 struct ice_aqc_get_link_status *resp; 395 struct ice_link_status *li_old, *li; 396 enum ice_media_type *hw_media_type; 397 struct ice_fc_info *hw_fc_info; 398 bool tx_pause, rx_pause; 399 struct ice_aq_desc desc; 400 enum ice_status status; 401 struct ice_hw *hw; 402 u16 cmd_flags; 403 404 if (!pi) 405 return ICE_ERR_PARAM; 406 hw = pi->hw; 407 li_old = &pi->phy.link_info_old; 408 hw_media_type = &pi->phy.media_type; 409 li = &pi->phy.link_info; 410 hw_fc_info = &pi->fc; 411 412 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 413 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 414 resp = &desc.params.get_link_status; 415 resp->cmd_flags = CPU_TO_LE16(cmd_flags); 416 resp->lport_num = pi->lport; 417 418 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 419 420 if (status != ICE_SUCCESS) 421 return status; 422 423 /* save off old link status information */ 424 *li_old = *li; 425 426 /* update current link status information */ 427 li->link_speed = LE16_TO_CPU(link_data.link_speed); 428 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low); 429 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high); 430 *hw_media_type = ice_get_media_type(pi); 431 li->link_info = link_data.link_info; 432 li->link_cfg_err = link_data.link_cfg_err; 433 li->an_info = link_data.an_info; 434 li->ext_info = link_data.ext_info; 435 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size); 436 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 437 li->topo_media_conflict = link_data.topo_media_conflict; 438 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 439 ICE_AQ_CFG_PACING_TYPE_M); 440 441 /* update fc info */ 442 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 443 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 444 if (tx_pause && rx_pause) 445 hw_fc_info->current_mode = ICE_FC_FULL; 446 else if (tx_pause) 447 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 448 else if (rx_pause) 449 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 450 else 451 hw_fc_info->current_mode = ICE_FC_NONE; 452 453 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED)); 454 455 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 456 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 457 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 458 (unsigned long long)li->phy_type_low); 459 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 460 (unsigned long long)li->phy_type_high); 461 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 462 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 463 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 464 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 465 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 466 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 467 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 468 li->max_frame_size); 469 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 470 471 /* save link status information */ 472 if (link) 473 *link = *li; 474 475 /* flag cleared so calling functions don't call AQ again */ 476 pi->phy.get_link_info = false; 477 478 return ICE_SUCCESS; 479 } 480 481 /** 482 * ice_fill_tx_timer_and_fc_thresh 483 * @hw: pointer to the HW struct 484 * @cmd: pointer to MAC cfg structure 485 * 486 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 487 * descriptor 488 */ 489 static void 490 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 491 struct ice_aqc_set_mac_cfg *cmd) 492 { 493 u16 fc_thres_val, tx_timer_val; 494 u32 val; 495 496 /* We read back the transmit timer and fc threshold value of 497 * LFC. Thus, we will use index = 498 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 499 * 500 * Also, because we are opearating on transmit timer and fc 501 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 502 */ 503 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 504 505 /* Retrieve the transmit timer */ 506 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 507 tx_timer_val = val & 508 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 509 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val); 510 511 /* Retrieve the fc threshold */ 512 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 513 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 514 515 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val); 516 } 517 518 /** 519 * ice_aq_set_mac_cfg 520 * @hw: pointer to the HW struct 521 * @max_frame_size: Maximum Frame Size to be supported 522 * @cd: pointer to command details structure or NULL 523 * 524 * Set MAC configuration (0x0603) 525 */ 526 enum ice_status 527 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 528 { 529 struct ice_aqc_set_mac_cfg *cmd; 530 struct ice_aq_desc desc; 531 532 cmd = &desc.params.set_mac_cfg; 533 534 if (max_frame_size == 0) 535 return ICE_ERR_PARAM; 536 537 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 538 539 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 540 541 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 542 543 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 544 } 545 546 /** 547 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 548 * @hw: pointer to the HW struct 549 */ 550 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 551 { 552 struct ice_switch_info *sw; 553 enum ice_status status; 554 555 hw->switch_info = (struct ice_switch_info *) 556 ice_malloc(hw, sizeof(*hw->switch_info)); 557 558 sw = hw->switch_info; 559 560 if (!sw) 561 return ICE_ERR_NO_MEMORY; 562 563 INIT_LIST_HEAD(&sw->vsi_list_map_head); 564 sw->prof_res_bm_init = 0; 565 566 status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list); 567 if (status) { 568 ice_free(hw, hw->switch_info); 569 return status; 570 } 571 return ICE_SUCCESS; 572 } 573 574 /** 575 * ice_cleanup_fltr_mgmt_single - clears single filter mngt struct 576 * @hw: pointer to the HW struct 577 * @sw: pointer to switch info struct for which function clears filters 578 */ 579 static void 580 ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw) 581 { 582 struct ice_vsi_list_map_info *v_pos_map; 583 struct ice_vsi_list_map_info *v_tmp_map; 584 struct ice_sw_recipe *recps; 585 u8 i; 586 587 if (!sw) 588 return; 589 590 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 591 ice_vsi_list_map_info, list_entry) { 592 LIST_DEL(&v_pos_map->list_entry); 593 ice_free(hw, v_pos_map); 594 } 595 recps = sw->recp_list; 596 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 597 struct ice_recp_grp_entry *rg_entry, *tmprg_entry; 598 599 recps[i].root_rid = i; 600 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry, 601 &recps[i].rg_list, ice_recp_grp_entry, 602 l_entry) { 603 LIST_DEL(&rg_entry->l_entry); 604 ice_free(hw, rg_entry); 605 } 606 607 if (recps[i].adv_rule) { 608 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 609 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 610 611 ice_destroy_lock(&recps[i].filt_rule_lock); 612 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 613 &recps[i].filt_rules, 614 ice_adv_fltr_mgmt_list_entry, 615 list_entry) { 616 LIST_DEL(&lst_itr->list_entry); 617 ice_free(hw, lst_itr->lkups); 618 ice_free(hw, lst_itr); 619 } 620 } else { 621 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 622 623 ice_destroy_lock(&recps[i].filt_rule_lock); 624 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 625 &recps[i].filt_rules, 626 ice_fltr_mgmt_list_entry, 627 list_entry) { 628 LIST_DEL(&lst_itr->list_entry); 629 ice_free(hw, lst_itr); 630 } 631 } 632 if (recps[i].root_buf) 633 ice_free(hw, recps[i].root_buf); 634 } 635 ice_rm_sw_replay_rule_info(hw, sw); 636 ice_free(hw, sw->recp_list); 637 ice_free(hw, sw); 638 } 639 640 /** 641 * ice_cleanup_all_fltr_mgmt - cleanup filter management list and locks 642 * @hw: pointer to the HW struct 643 */ 644 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 645 { 646 ice_cleanup_fltr_mgmt_single(hw, hw->switch_info); 647 } 648 649 /** 650 * ice_get_itr_intrl_gran 651 * @hw: pointer to the HW struct 652 * 653 * Determines the ITR/INTRL granularities based on the maximum aggregate 654 * bandwidth according to the device's configuration during power-on. 655 */ 656 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 657 { 658 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 659 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 660 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 661 662 switch (max_agg_bw) { 663 case ICE_MAX_AGG_BW_200G: 664 case ICE_MAX_AGG_BW_100G: 665 case ICE_MAX_AGG_BW_50G: 666 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 667 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 668 break; 669 case ICE_MAX_AGG_BW_25G: 670 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 671 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 672 break; 673 } 674 } 675 676 /** 677 * ice_print_rollback_msg - print FW rollback message 678 * @hw: pointer to the hardware structure 679 */ 680 void ice_print_rollback_msg(struct ice_hw *hw) 681 { 682 char nvm_str[ICE_NVM_VER_LEN] = { 0 }; 683 struct ice_orom_info *orom; 684 struct ice_nvm_info *nvm; 685 686 orom = &hw->flash.orom; 687 nvm = &hw->flash.nvm; 688 689 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", 690 nvm->major, nvm->minor, nvm->eetrack, orom->major, 691 orom->build, orom->patch); 692 ice_warn(hw, 693 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n", 694 nvm_str, hw->fw_maj_ver, hw->fw_min_ver); 695 } 696 697 /** 698 * ice_init_hw - main hardware initialization routine 699 * @hw: pointer to the hardware structure 700 */ 701 enum ice_status ice_init_hw(struct ice_hw *hw) 702 { 703 struct ice_aqc_get_phy_caps_data *pcaps; 704 enum ice_status status; 705 u16 mac_buf_len; 706 void *mac_buf; 707 708 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 709 710 /* Set MAC type based on DeviceID */ 711 status = ice_set_mac_type(hw); 712 if (status) 713 return status; 714 715 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 716 PF_FUNC_RID_FUNCTION_NUMBER_M) >> 717 PF_FUNC_RID_FUNCTION_NUMBER_S; 718 719 status = ice_reset(hw, ICE_RESET_PFR); 720 if (status) 721 return status; 722 723 ice_get_itr_intrl_gran(hw); 724 725 status = ice_create_all_ctrlq(hw); 726 if (status) 727 goto err_unroll_cqinit; 728 729 status = ice_init_nvm(hw); 730 if (status) 731 goto err_unroll_cqinit; 732 733 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK) 734 ice_print_rollback_msg(hw); 735 736 status = ice_clear_pf_cfg(hw); 737 if (status) 738 goto err_unroll_cqinit; 739 740 /* Set bit to enable Flow Director filters */ 741 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 742 INIT_LIST_HEAD(&hw->fdir_list_head); 743 744 ice_clear_pxe_mode(hw); 745 746 status = ice_get_caps(hw); 747 if (status) 748 goto err_unroll_cqinit; 749 750 hw->port_info = (struct ice_port_info *) 751 ice_malloc(hw, sizeof(*hw->port_info)); 752 if (!hw->port_info) { 753 status = ICE_ERR_NO_MEMORY; 754 goto err_unroll_cqinit; 755 } 756 757 /* set the back pointer to HW */ 758 hw->port_info->hw = hw; 759 760 /* Initialize port_info struct with switch configuration data */ 761 status = ice_get_initial_sw_cfg(hw); 762 if (status) 763 goto err_unroll_alloc; 764 765 hw->evb_veb = true; 766 /* Query the allocated resources for Tx scheduler */ 767 status = ice_sched_query_res_alloc(hw); 768 if (status) { 769 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 770 goto err_unroll_alloc; 771 } 772 ice_sched_get_psm_clk_freq(hw); 773 774 /* Initialize port_info struct with scheduler data */ 775 status = ice_sched_init_port(hw->port_info); 776 if (status) 777 goto err_unroll_sched; 778 pcaps = (struct ice_aqc_get_phy_caps_data *) 779 ice_malloc(hw, sizeof(*pcaps)); 780 if (!pcaps) { 781 status = ICE_ERR_NO_MEMORY; 782 goto err_unroll_sched; 783 } 784 785 /* Initialize port_info struct with PHY capabilities */ 786 status = ice_aq_get_phy_caps(hw->port_info, false, 787 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, NULL); 788 ice_free(hw, pcaps); 789 if (status) 790 ice_warn(hw, "Get PHY capabilities failed status = %d, continuing anyway\n", 791 status); 792 793 /* Initialize port_info struct with link information */ 794 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 795 if (status) 796 goto err_unroll_sched; 797 /* need a valid SW entry point to build a Tx tree */ 798 if (!hw->sw_entry_point_layer) { 799 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 800 status = ICE_ERR_CFG; 801 goto err_unroll_sched; 802 } 803 INIT_LIST_HEAD(&hw->agg_list); 804 /* Initialize max burst size */ 805 if (!hw->max_burst_size) 806 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 807 status = ice_init_fltr_mgmt_struct(hw); 808 if (status) 809 goto err_unroll_sched; 810 811 /* Get MAC information */ 812 /* A single port can report up to two (LAN and WoL) addresses */ 813 mac_buf = ice_calloc(hw, 2, 814 sizeof(struct ice_aqc_manage_mac_read_resp)); 815 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 816 817 if (!mac_buf) { 818 status = ICE_ERR_NO_MEMORY; 819 goto err_unroll_fltr_mgmt_struct; 820 } 821 822 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 823 ice_free(hw, mac_buf); 824 825 if (status) 826 goto err_unroll_fltr_mgmt_struct; 827 /* enable jumbo frame support at MAC level */ 828 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 829 if (status) 830 goto err_unroll_fltr_mgmt_struct; 831 /* Obtain counter base index which would be used by flow director */ 832 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 833 if (status) 834 goto err_unroll_fltr_mgmt_struct; 835 status = ice_init_hw_tbls(hw); 836 if (status) 837 goto err_unroll_fltr_mgmt_struct; 838 ice_init_lock(&hw->tnl_lock); 839 840 return ICE_SUCCESS; 841 842 err_unroll_fltr_mgmt_struct: 843 ice_cleanup_fltr_mgmt_struct(hw); 844 err_unroll_sched: 845 ice_sched_cleanup_all(hw); 846 err_unroll_alloc: 847 ice_free(hw, hw->port_info); 848 hw->port_info = NULL; 849 err_unroll_cqinit: 850 ice_destroy_all_ctrlq(hw); 851 return status; 852 } 853 854 /** 855 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 856 * @hw: pointer to the hardware structure 857 * 858 * This should be called only during nominal operation, not as a result of 859 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 860 * applicable initializations if it fails for any reason. 861 */ 862 void ice_deinit_hw(struct ice_hw *hw) 863 { 864 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 865 ice_cleanup_fltr_mgmt_struct(hw); 866 867 ice_sched_cleanup_all(hw); 868 ice_sched_clear_agg(hw); 869 ice_free_seg(hw); 870 ice_free_hw_tbls(hw); 871 ice_destroy_lock(&hw->tnl_lock); 872 873 if (hw->port_info) { 874 ice_free(hw, hw->port_info); 875 hw->port_info = NULL; 876 } 877 878 ice_destroy_all_ctrlq(hw); 879 880 /* Clear VSI contexts if not already cleared */ 881 ice_clear_all_vsi_ctx(hw); 882 } 883 884 /** 885 * ice_check_reset - Check to see if a global reset is complete 886 * @hw: pointer to the hardware structure 887 */ 888 enum ice_status ice_check_reset(struct ice_hw *hw) 889 { 890 u32 cnt, reg = 0, grst_timeout, uld_mask; 891 892 /* Poll for Device Active state in case a recent CORER, GLOBR, 893 * or EMPR has occurred. The grst delay value is in 100ms units. 894 * Add 1sec for outstanding AQ commands that can take a long time. 895 */ 896 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 897 GLGEN_RSTCTL_GRSTDEL_S) + 10; 898 899 for (cnt = 0; cnt < grst_timeout; cnt++) { 900 ice_msec_delay(100, true); 901 reg = rd32(hw, GLGEN_RSTAT); 902 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 903 break; 904 } 905 906 if (cnt == grst_timeout) { 907 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 908 return ICE_ERR_RESET_FAILED; 909 } 910 911 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 912 GLNVM_ULD_PCIER_DONE_1_M |\ 913 GLNVM_ULD_CORER_DONE_M |\ 914 GLNVM_ULD_GLOBR_DONE_M |\ 915 GLNVM_ULD_POR_DONE_M |\ 916 GLNVM_ULD_POR_DONE_1_M |\ 917 GLNVM_ULD_PCIER_DONE_2_M) 918 919 uld_mask = ICE_RESET_DONE_MASK; 920 921 /* Device is Active; check Global Reset processes are done */ 922 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 923 reg = rd32(hw, GLNVM_ULD) & uld_mask; 924 if (reg == uld_mask) { 925 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 926 break; 927 } 928 ice_msec_delay(10, true); 929 } 930 931 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 932 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 933 reg); 934 return ICE_ERR_RESET_FAILED; 935 } 936 937 return ICE_SUCCESS; 938 } 939 940 /** 941 * ice_pf_reset - Reset the PF 942 * @hw: pointer to the hardware structure 943 * 944 * If a global reset has been triggered, this function checks 945 * for its completion and then issues the PF reset 946 */ 947 static enum ice_status ice_pf_reset(struct ice_hw *hw) 948 { 949 u32 cnt, reg; 950 951 /* If at function entry a global reset was already in progress, i.e. 952 * state is not 'device active' or any of the reset done bits are not 953 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 954 * global reset is done. 955 */ 956 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 957 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 958 /* poll on global reset currently in progress until done */ 959 if (ice_check_reset(hw)) 960 return ICE_ERR_RESET_FAILED; 961 962 return ICE_SUCCESS; 963 } 964 965 /* Reset the PF */ 966 reg = rd32(hw, PFGEN_CTRL); 967 968 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 969 970 /* Wait for the PFR to complete. The wait time is the global config lock 971 * timeout plus the PFR timeout which will account for a possible reset 972 * that is occurring during a download package operation. 973 */ 974 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 975 ICE_PF_RESET_WAIT_COUNT; cnt++) { 976 reg = rd32(hw, PFGEN_CTRL); 977 if (!(reg & PFGEN_CTRL_PFSWR_M)) 978 break; 979 980 ice_msec_delay(1, true); 981 } 982 983 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 984 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 985 return ICE_ERR_RESET_FAILED; 986 } 987 988 return ICE_SUCCESS; 989 } 990 991 /** 992 * ice_reset - Perform different types of reset 993 * @hw: pointer to the hardware structure 994 * @req: reset request 995 * 996 * This function triggers a reset as specified by the req parameter. 997 * 998 * Note: 999 * If anything other than a PF reset is triggered, PXE mode is restored. 1000 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1001 * interface has been restored in the rebuild flow. 1002 */ 1003 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1004 { 1005 u32 val = 0; 1006 1007 switch (req) { 1008 case ICE_RESET_PFR: 1009 return ice_pf_reset(hw); 1010 case ICE_RESET_CORER: 1011 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1012 val = GLGEN_RTRIG_CORER_M; 1013 break; 1014 case ICE_RESET_GLOBR: 1015 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1016 val = GLGEN_RTRIG_GLOBR_M; 1017 break; 1018 default: 1019 return ICE_ERR_PARAM; 1020 } 1021 1022 val |= rd32(hw, GLGEN_RTRIG); 1023 wr32(hw, GLGEN_RTRIG, val); 1024 ice_flush(hw); 1025 1026 /* wait for the FW to be ready */ 1027 return ice_check_reset(hw); 1028 } 1029 1030 /** 1031 * ice_copy_rxq_ctx_to_hw 1032 * @hw: pointer to the hardware structure 1033 * @ice_rxq_ctx: pointer to the rxq context 1034 * @rxq_index: the index of the Rx queue 1035 * 1036 * Copies rxq context from dense structure to HW register space 1037 */ 1038 static enum ice_status 1039 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1040 { 1041 u8 i; 1042 1043 if (!ice_rxq_ctx) 1044 return ICE_ERR_BAD_PTR; 1045 1046 if (rxq_index > QRX_CTRL_MAX_INDEX) 1047 return ICE_ERR_PARAM; 1048 1049 /* Copy each dword separately to HW */ 1050 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1051 wr32(hw, QRX_CONTEXT(i, rxq_index), 1052 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1053 1054 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1055 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1056 } 1057 1058 return ICE_SUCCESS; 1059 } 1060 1061 /* LAN Rx Queue Context */ 1062 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1063 /* Field Width LSB */ 1064 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1065 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1066 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1067 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1068 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1069 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1070 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1071 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1072 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1073 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1074 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1075 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1076 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1077 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1078 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1079 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1080 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1081 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1082 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1083 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1084 { 0 } 1085 }; 1086 1087 /** 1088 * ice_write_rxq_ctx 1089 * @hw: pointer to the hardware structure 1090 * @rlan_ctx: pointer to the rxq context 1091 * @rxq_index: the index of the Rx queue 1092 * 1093 * Converts rxq context from sparse to dense structure and then writes 1094 * it to HW register space and enables the hardware to prefetch descriptors 1095 * instead of only fetching them on demand 1096 */ 1097 enum ice_status 1098 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1099 u32 rxq_index) 1100 { 1101 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1102 1103 if (!rlan_ctx) 1104 return ICE_ERR_BAD_PTR; 1105 1106 rlan_ctx->prefena = 1; 1107 1108 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1109 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1110 } 1111 1112 /** 1113 * ice_clear_rxq_ctx 1114 * @hw: pointer to the hardware structure 1115 * @rxq_index: the index of the Rx queue to clear 1116 * 1117 * Clears rxq context in HW register space 1118 */ 1119 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index) 1120 { 1121 u8 i; 1122 1123 if (rxq_index > QRX_CTRL_MAX_INDEX) 1124 return ICE_ERR_PARAM; 1125 1126 /* Clear each dword register separately */ 1127 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) 1128 wr32(hw, QRX_CONTEXT(i, rxq_index), 0); 1129 1130 return ICE_SUCCESS; 1131 } 1132 1133 /* LAN Tx Queue Context */ 1134 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1135 /* Field Width LSB */ 1136 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1137 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1138 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1139 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1140 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1141 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1142 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1143 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1144 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1145 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1146 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1147 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1148 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1149 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1150 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1151 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1152 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1153 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1154 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1155 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1156 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1157 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1158 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1159 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1160 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1161 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1162 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1163 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1164 { 0 } 1165 }; 1166 1167 /** 1168 * ice_copy_tx_cmpltnq_ctx_to_hw 1169 * @hw: pointer to the hardware structure 1170 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context 1171 * @tx_cmpltnq_index: the index of the completion queue 1172 * 1173 * Copies Tx completion queue context from dense structure to HW register space 1174 */ 1175 static enum ice_status 1176 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx, 1177 u32 tx_cmpltnq_index) 1178 { 1179 u8 i; 1180 1181 if (!ice_tx_cmpltnq_ctx) 1182 return ICE_ERR_BAD_PTR; 1183 1184 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 1185 return ICE_ERR_PARAM; 1186 1187 /* Copy each dword separately to HW */ 1188 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) { 1189 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 1190 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 1191 1192 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i, 1193 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 1194 } 1195 1196 return ICE_SUCCESS; 1197 } 1198 1199 /* LAN Tx Completion Queue Context */ 1200 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = { 1201 /* Field Width LSB */ 1202 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0), 1203 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64), 1204 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96), 1205 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97), 1206 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128), 1207 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131), 1208 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141), 1209 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160), 1210 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161), 1211 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192), 1212 { 0 } 1213 }; 1214 1215 /** 1216 * ice_write_tx_cmpltnq_ctx 1217 * @hw: pointer to the hardware structure 1218 * @tx_cmpltnq_ctx: pointer to the completion queue context 1219 * @tx_cmpltnq_index: the index of the completion queue 1220 * 1221 * Converts completion queue context from sparse to dense structure and then 1222 * writes it to HW register space 1223 */ 1224 enum ice_status 1225 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw, 1226 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx, 1227 u32 tx_cmpltnq_index) 1228 { 1229 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 1230 1231 ice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info); 1232 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index); 1233 } 1234 1235 /** 1236 * ice_clear_tx_cmpltnq_ctx 1237 * @hw: pointer to the hardware structure 1238 * @tx_cmpltnq_index: the index of the completion queue to clear 1239 * 1240 * Clears Tx completion queue context in HW register space 1241 */ 1242 enum ice_status 1243 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index) 1244 { 1245 u8 i; 1246 1247 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 1248 return ICE_ERR_PARAM; 1249 1250 /* Clear each dword register separately */ 1251 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) 1252 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0); 1253 1254 return ICE_SUCCESS; 1255 } 1256 1257 /** 1258 * ice_copy_tx_drbell_q_ctx_to_hw 1259 * @hw: pointer to the hardware structure 1260 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context 1261 * @tx_drbell_q_index: the index of the doorbell queue 1262 * 1263 * Copies doorbell queue context from dense structure to HW register space 1264 */ 1265 static enum ice_status 1266 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx, 1267 u32 tx_drbell_q_index) 1268 { 1269 u8 i; 1270 1271 if (!ice_tx_drbell_q_ctx) 1272 return ICE_ERR_BAD_PTR; 1273 1274 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 1275 return ICE_ERR_PARAM; 1276 1277 /* Copy each dword separately to HW */ 1278 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) { 1279 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 1280 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 1281 1282 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i, 1283 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 1284 } 1285 1286 return ICE_SUCCESS; 1287 } 1288 1289 /* LAN Tx Doorbell Queue Context info */ 1290 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = { 1291 /* Field Width LSB */ 1292 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0), 1293 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64), 1294 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80), 1295 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84), 1296 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94), 1297 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96), 1298 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104), 1299 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108), 1300 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112), 1301 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128), 1302 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144), 1303 { 0 } 1304 }; 1305 1306 /** 1307 * ice_write_tx_drbell_q_ctx 1308 * @hw: pointer to the hardware structure 1309 * @tx_drbell_q_ctx: pointer to the doorbell queue context 1310 * @tx_drbell_q_index: the index of the doorbell queue 1311 * 1312 * Converts doorbell queue context from sparse to dense structure and then 1313 * writes it to HW register space 1314 */ 1315 enum ice_status 1316 ice_write_tx_drbell_q_ctx(struct ice_hw *hw, 1317 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx, 1318 u32 tx_drbell_q_index) 1319 { 1320 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 1321 1322 ice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf, 1323 ice_tx_drbell_q_ctx_info); 1324 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index); 1325 } 1326 1327 /** 1328 * ice_clear_tx_drbell_q_ctx 1329 * @hw: pointer to the hardware structure 1330 * @tx_drbell_q_index: the index of the doorbell queue to clear 1331 * 1332 * Clears doorbell queue context in HW register space 1333 */ 1334 enum ice_status 1335 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index) 1336 { 1337 u8 i; 1338 1339 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 1340 return ICE_ERR_PARAM; 1341 1342 /* Clear each dword register separately */ 1343 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) 1344 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0); 1345 1346 return ICE_SUCCESS; 1347 } 1348 1349 /* FW Admin Queue command wrappers */ 1350 1351 /** 1352 * ice_should_retry_sq_send_cmd 1353 * @opcode: AQ opcode 1354 * 1355 * Decide if we should retry the send command routine for the ATQ, depending 1356 * on the opcode. 1357 */ 1358 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1359 { 1360 switch (opcode) { 1361 case ice_aqc_opc_get_link_topo: 1362 case ice_aqc_opc_lldp_stop: 1363 case ice_aqc_opc_lldp_start: 1364 case ice_aqc_opc_lldp_filter_ctrl: 1365 return true; 1366 } 1367 1368 return false; 1369 } 1370 1371 /** 1372 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1373 * @hw: pointer to the HW struct 1374 * @cq: pointer to the specific Control queue 1375 * @desc: prefilled descriptor describing the command 1376 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1377 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1378 * @cd: pointer to command details structure 1379 * 1380 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1381 * Queue if the EBUSY AQ error is returned. 1382 */ 1383 static enum ice_status 1384 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1385 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1386 struct ice_sq_cd *cd) 1387 { 1388 struct ice_aq_desc desc_cpy; 1389 enum ice_status status; 1390 bool is_cmd_for_retry; 1391 u8 *buf_cpy = NULL; 1392 u8 idx = 0; 1393 u16 opcode; 1394 1395 opcode = LE16_TO_CPU(desc->opcode); 1396 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1397 ice_memset(&desc_cpy, 0, sizeof(desc_cpy), ICE_NONDMA_MEM); 1398 1399 if (is_cmd_for_retry) { 1400 if (buf) { 1401 buf_cpy = (u8 *)ice_malloc(hw, buf_size); 1402 if (!buf_cpy) 1403 return ICE_ERR_NO_MEMORY; 1404 } 1405 1406 ice_memcpy(&desc_cpy, desc, sizeof(desc_cpy), 1407 ICE_NONDMA_TO_NONDMA); 1408 } 1409 1410 do { 1411 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1412 1413 if (!is_cmd_for_retry || status == ICE_SUCCESS || 1414 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1415 break; 1416 1417 if (buf_cpy) 1418 ice_memcpy(buf, buf_cpy, buf_size, 1419 ICE_NONDMA_TO_NONDMA); 1420 1421 ice_memcpy(desc, &desc_cpy, sizeof(desc_cpy), 1422 ICE_NONDMA_TO_NONDMA); 1423 1424 ice_msec_delay(ICE_SQ_SEND_DELAY_TIME_MS, false); 1425 1426 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1427 1428 if (buf_cpy) 1429 ice_free(hw, buf_cpy); 1430 1431 return status; 1432 } 1433 1434 /** 1435 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1436 * @hw: pointer to the HW struct 1437 * @desc: descriptor describing the command 1438 * @buf: buffer to use for indirect commands (NULL for direct commands) 1439 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1440 * @cd: pointer to command details structure 1441 * 1442 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1443 */ 1444 enum ice_status 1445 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1446 u16 buf_size, struct ice_sq_cd *cd) 1447 { 1448 if (hw->aq_send_cmd_fn) { 1449 enum ice_status status = ICE_ERR_NOT_READY; 1450 u16 retval = ICE_AQ_RC_OK; 1451 1452 ice_acquire_lock(&hw->adminq.sq_lock); 1453 if (!hw->aq_send_cmd_fn(hw->aq_send_cmd_param, desc, 1454 buf, buf_size)) { 1455 retval = LE16_TO_CPU(desc->retval); 1456 /* strip off FW internal code */ 1457 if (retval) 1458 retval &= 0xff; 1459 if (retval == ICE_AQ_RC_OK) 1460 status = ICE_SUCCESS; 1461 else 1462 status = ICE_ERR_AQ_ERROR; 1463 } 1464 1465 hw->adminq.sq_last_status = (enum ice_aq_err)retval; 1466 ice_release_lock(&hw->adminq.sq_lock); 1467 1468 return status; 1469 } 1470 return ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1471 } 1472 1473 /** 1474 * ice_aq_get_fw_ver 1475 * @hw: pointer to the HW struct 1476 * @cd: pointer to command details structure or NULL 1477 * 1478 * Get the firmware version (0x0001) from the admin queue commands 1479 */ 1480 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1481 { 1482 struct ice_aqc_get_ver *resp; 1483 struct ice_aq_desc desc; 1484 enum ice_status status; 1485 1486 resp = &desc.params.get_ver; 1487 1488 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1489 1490 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1491 1492 if (!status) { 1493 hw->fw_branch = resp->fw_branch; 1494 hw->fw_maj_ver = resp->fw_major; 1495 hw->fw_min_ver = resp->fw_minor; 1496 hw->fw_patch = resp->fw_patch; 1497 hw->fw_build = LE32_TO_CPU(resp->fw_build); 1498 hw->api_branch = resp->api_branch; 1499 hw->api_maj_ver = resp->api_major; 1500 hw->api_min_ver = resp->api_minor; 1501 hw->api_patch = resp->api_patch; 1502 } 1503 1504 return status; 1505 } 1506 1507 /** 1508 * ice_aq_send_driver_ver 1509 * @hw: pointer to the HW struct 1510 * @dv: driver's major, minor version 1511 * @cd: pointer to command details structure or NULL 1512 * 1513 * Send the driver version (0x0002) to the firmware 1514 */ 1515 enum ice_status 1516 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1517 struct ice_sq_cd *cd) 1518 { 1519 struct ice_aqc_driver_ver *cmd; 1520 struct ice_aq_desc desc; 1521 u16 len; 1522 1523 cmd = &desc.params.driver_ver; 1524 1525 if (!dv) 1526 return ICE_ERR_PARAM; 1527 1528 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1529 1530 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 1531 cmd->major_ver = dv->major_ver; 1532 cmd->minor_ver = dv->minor_ver; 1533 cmd->build_ver = dv->build_ver; 1534 cmd->subbuild_ver = dv->subbuild_ver; 1535 1536 len = 0; 1537 while (len < sizeof(dv->driver_string) && 1538 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len]) 1539 len++; 1540 1541 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1542 } 1543 1544 /** 1545 * ice_aq_q_shutdown 1546 * @hw: pointer to the HW struct 1547 * @unloading: is the driver unloading itself 1548 * 1549 * Tell the Firmware that we're shutting down the AdminQ and whether 1550 * or not the driver is unloading as well (0x0003). 1551 */ 1552 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1553 { 1554 struct ice_aqc_q_shutdown *cmd; 1555 struct ice_aq_desc desc; 1556 1557 cmd = &desc.params.q_shutdown; 1558 1559 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1560 1561 if (unloading) 1562 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1563 1564 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1565 } 1566 1567 /** 1568 * ice_aq_req_res 1569 * @hw: pointer to the HW struct 1570 * @res: resource ID 1571 * @access: access type 1572 * @sdp_number: resource number 1573 * @timeout: the maximum time in ms that the driver may hold the resource 1574 * @cd: pointer to command details structure or NULL 1575 * 1576 * Requests common resource using the admin queue commands (0x0008). 1577 * When attempting to acquire the Global Config Lock, the driver can 1578 * learn of three states: 1579 * 1) ICE_SUCCESS - acquired lock, and can perform download package 1580 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1581 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1582 * successfully downloaded the package; the driver does 1583 * not have to download the package and can continue 1584 * loading 1585 * 1586 * Note that if the caller is in an acquire lock, perform action, release lock 1587 * phase of operation, it is possible that the FW may detect a timeout and issue 1588 * a CORER. In this case, the driver will receive a CORER interrupt and will 1589 * have to determine its cause. The calling thread that is handling this flow 1590 * will likely get an error propagated back to it indicating the Download 1591 * Package, Update Package or the Release Resource AQ commands timed out. 1592 */ 1593 static enum ice_status 1594 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1595 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1596 struct ice_sq_cd *cd) 1597 { 1598 struct ice_aqc_req_res *cmd_resp; 1599 struct ice_aq_desc desc; 1600 enum ice_status status; 1601 1602 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1603 1604 cmd_resp = &desc.params.res_owner; 1605 1606 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1607 1608 cmd_resp->res_id = CPU_TO_LE16(res); 1609 cmd_resp->access_type = CPU_TO_LE16(access); 1610 cmd_resp->res_number = CPU_TO_LE32(sdp_number); 1611 cmd_resp->timeout = CPU_TO_LE32(*timeout); 1612 *timeout = 0; 1613 1614 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1615 1616 /* The completion specifies the maximum time in ms that the driver 1617 * may hold the resource in the Timeout field. 1618 */ 1619 1620 /* Global config lock response utilizes an additional status field. 1621 * 1622 * If the Global config lock resource is held by some other driver, the 1623 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1624 * and the timeout field indicates the maximum time the current owner 1625 * of the resource has to free it. 1626 */ 1627 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1628 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1629 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1630 return ICE_SUCCESS; 1631 } else if (LE16_TO_CPU(cmd_resp->status) == 1632 ICE_AQ_RES_GLBL_IN_PROG) { 1633 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1634 return ICE_ERR_AQ_ERROR; 1635 } else if (LE16_TO_CPU(cmd_resp->status) == 1636 ICE_AQ_RES_GLBL_DONE) { 1637 return ICE_ERR_AQ_NO_WORK; 1638 } 1639 1640 /* invalid FW response, force a timeout immediately */ 1641 *timeout = 0; 1642 return ICE_ERR_AQ_ERROR; 1643 } 1644 1645 /* If the resource is held by some other driver, the command completes 1646 * with a busy return value and the timeout field indicates the maximum 1647 * time the current owner of the resource has to free it. 1648 */ 1649 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1650 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1651 1652 return status; 1653 } 1654 1655 /** 1656 * ice_aq_release_res 1657 * @hw: pointer to the HW struct 1658 * @res: resource ID 1659 * @sdp_number: resource number 1660 * @cd: pointer to command details structure or NULL 1661 * 1662 * release common resource using the admin queue commands (0x0009) 1663 */ 1664 static enum ice_status 1665 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1666 struct ice_sq_cd *cd) 1667 { 1668 struct ice_aqc_req_res *cmd; 1669 struct ice_aq_desc desc; 1670 1671 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1672 1673 cmd = &desc.params.res_owner; 1674 1675 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1676 1677 cmd->res_id = CPU_TO_LE16(res); 1678 cmd->res_number = CPU_TO_LE32(sdp_number); 1679 1680 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1681 } 1682 1683 /** 1684 * ice_acquire_res 1685 * @hw: pointer to the HW structure 1686 * @res: resource ID 1687 * @access: access type (read or write) 1688 * @timeout: timeout in milliseconds 1689 * 1690 * This function will attempt to acquire the ownership of a resource. 1691 */ 1692 enum ice_status 1693 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1694 enum ice_aq_res_access_type access, u32 timeout) 1695 { 1696 #define ICE_RES_POLLING_DELAY_MS 10 1697 u32 delay = ICE_RES_POLLING_DELAY_MS; 1698 u32 time_left = timeout; 1699 enum ice_status status; 1700 1701 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1702 1703 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1704 1705 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 1706 * previously acquired the resource and performed any necessary updates; 1707 * in this case the caller does not obtain the resource and has no 1708 * further work to do. 1709 */ 1710 if (status == ICE_ERR_AQ_NO_WORK) 1711 goto ice_acquire_res_exit; 1712 1713 if (status) 1714 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 1715 1716 /* If necessary, poll until the current lock owner timeouts */ 1717 timeout = time_left; 1718 while (status && timeout && time_left) { 1719 ice_msec_delay(delay, true); 1720 timeout = (timeout > delay) ? timeout - delay : 0; 1721 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1722 1723 if (status == ICE_ERR_AQ_NO_WORK) 1724 /* lock free, but no work to do */ 1725 break; 1726 1727 if (!status) 1728 /* lock acquired */ 1729 break; 1730 } 1731 if (status && status != ICE_ERR_AQ_NO_WORK) 1732 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1733 1734 ice_acquire_res_exit: 1735 if (status == ICE_ERR_AQ_NO_WORK) { 1736 if (access == ICE_RES_WRITE) 1737 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 1738 else 1739 ice_debug(hw, ICE_DBG_RES, "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1740 } 1741 return status; 1742 } 1743 1744 /** 1745 * ice_release_res 1746 * @hw: pointer to the HW structure 1747 * @res: resource ID 1748 * 1749 * This function will release a resource using the proper Admin Command. 1750 */ 1751 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1752 { 1753 enum ice_status status; 1754 u32 total_delay = 0; 1755 1756 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1757 1758 status = ice_aq_release_res(hw, res, 0, NULL); 1759 1760 /* there are some rare cases when trying to release the resource 1761 * results in an admin queue timeout, so handle them correctly 1762 */ 1763 while ((status == ICE_ERR_AQ_TIMEOUT) && 1764 (total_delay < hw->adminq.sq_cmd_timeout)) { 1765 ice_msec_delay(1, true); 1766 status = ice_aq_release_res(hw, res, 0, NULL); 1767 total_delay++; 1768 } 1769 } 1770 1771 /** 1772 * ice_aq_alloc_free_res - command to allocate/free resources 1773 * @hw: pointer to the HW struct 1774 * @num_entries: number of resource entries in buffer 1775 * @buf: Indirect buffer to hold data parameters and response 1776 * @buf_size: size of buffer for indirect commands 1777 * @opc: pass in the command opcode 1778 * @cd: pointer to command details structure or NULL 1779 * 1780 * Helper function to allocate/free resources using the admin queue commands 1781 */ 1782 enum ice_status 1783 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 1784 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1785 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1786 { 1787 struct ice_aqc_alloc_free_res_cmd *cmd; 1788 struct ice_aq_desc desc; 1789 1790 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1791 1792 cmd = &desc.params.sw_res_ctrl; 1793 1794 if (!buf) 1795 return ICE_ERR_PARAM; 1796 1797 if (buf_size < FLEX_ARRAY_SIZE(buf, elem, num_entries)) 1798 return ICE_ERR_PARAM; 1799 1800 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1801 1802 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 1803 1804 cmd->num_entries = CPU_TO_LE16(num_entries); 1805 1806 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1807 } 1808 1809 /** 1810 * ice_alloc_hw_res - allocate resource 1811 * @hw: pointer to the HW struct 1812 * @type: type of resource 1813 * @num: number of resources to allocate 1814 * @btm: allocate from bottom 1815 * @res: pointer to array that will receive the resources 1816 */ 1817 enum ice_status 1818 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 1819 { 1820 struct ice_aqc_alloc_free_res_elem *buf; 1821 enum ice_status status; 1822 u16 buf_len; 1823 1824 buf_len = ice_struct_size(buf, elem, num); 1825 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); 1826 if (!buf) 1827 return ICE_ERR_NO_MEMORY; 1828 1829 /* Prepare buffer to allocate resource. */ 1830 buf->num_elems = CPU_TO_LE16(num); 1831 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 1832 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 1833 if (btm) 1834 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 1835 1836 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 1837 ice_aqc_opc_alloc_res, NULL); 1838 if (status) 1839 goto ice_alloc_res_exit; 1840 1841 ice_memcpy(res, buf->elem, sizeof(*buf->elem) * num, 1842 ICE_NONDMA_TO_NONDMA); 1843 1844 ice_alloc_res_exit: 1845 ice_free(hw, buf); 1846 return status; 1847 } 1848 1849 /** 1850 * ice_free_hw_res - free allocated HW resource 1851 * @hw: pointer to the HW struct 1852 * @type: type of resource to free 1853 * @num: number of resources 1854 * @res: pointer to array that contains the resources to free 1855 */ 1856 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 1857 { 1858 struct ice_aqc_alloc_free_res_elem *buf; 1859 enum ice_status status; 1860 u16 buf_len; 1861 1862 buf_len = ice_struct_size(buf, elem, num); 1863 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); 1864 if (!buf) 1865 return ICE_ERR_NO_MEMORY; 1866 1867 /* Prepare buffer to free resource. */ 1868 buf->num_elems = CPU_TO_LE16(num); 1869 buf->res_type = CPU_TO_LE16(type); 1870 ice_memcpy(buf->elem, res, sizeof(*buf->elem) * num, 1871 ICE_NONDMA_TO_NONDMA); 1872 1873 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 1874 ice_aqc_opc_free_res, NULL); 1875 if (status) 1876 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 1877 1878 ice_free(hw, buf); 1879 return status; 1880 } 1881 1882 /** 1883 * ice_get_num_per_func - determine number of resources per PF 1884 * @hw: pointer to the HW structure 1885 * @max: value to be evenly split between each PF 1886 * 1887 * Determine the number of valid functions by going through the bitmap returned 1888 * from parsing capabilities and use this to calculate the number of resources 1889 * per PF based on the max value passed in. 1890 */ 1891 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 1892 { 1893 u8 funcs; 1894 1895 #define ICE_CAPS_VALID_FUNCS_M 0xFF 1896 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions & 1897 ICE_CAPS_VALID_FUNCS_M); 1898 1899 if (!funcs) 1900 return 0; 1901 1902 return max / funcs; 1903 } 1904 1905 /** 1906 * ice_parse_common_caps - parse common device/function capabilities 1907 * @hw: pointer to the HW struct 1908 * @caps: pointer to common capabilities structure 1909 * @elem: the capability element to parse 1910 * @prefix: message prefix for tracing capabilities 1911 * 1912 * Given a capability element, extract relevant details into the common 1913 * capability structure. 1914 * 1915 * Returns: true if the capability matches one of the common capability ids, 1916 * false otherwise. 1917 */ 1918 static bool 1919 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 1920 struct ice_aqc_list_caps_elem *elem, const char *prefix) 1921 { 1922 u32 logical_id = LE32_TO_CPU(elem->logical_id); 1923 u32 phys_id = LE32_TO_CPU(elem->phys_id); 1924 u32 number = LE32_TO_CPU(elem->number); 1925 u16 cap = LE16_TO_CPU(elem->cap); 1926 bool found = true; 1927 1928 switch (cap) { 1929 case ICE_AQC_CAPS_VALID_FUNCTIONS: 1930 caps->valid_functions = number; 1931 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 1932 caps->valid_functions); 1933 break; 1934 case ICE_AQC_CAPS_DCB: 1935 caps->dcb = (number == 1); 1936 caps->active_tc_bitmap = logical_id; 1937 caps->maxtc = phys_id; 1938 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 1939 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 1940 caps->active_tc_bitmap); 1941 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 1942 break; 1943 case ICE_AQC_CAPS_RSS: 1944 caps->rss_table_size = number; 1945 caps->rss_table_entry_width = logical_id; 1946 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 1947 caps->rss_table_size); 1948 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 1949 caps->rss_table_entry_width); 1950 break; 1951 case ICE_AQC_CAPS_RXQS: 1952 caps->num_rxq = number; 1953 caps->rxq_first_id = phys_id; 1954 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 1955 caps->num_rxq); 1956 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 1957 caps->rxq_first_id); 1958 break; 1959 case ICE_AQC_CAPS_TXQS: 1960 caps->num_txq = number; 1961 caps->txq_first_id = phys_id; 1962 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 1963 caps->num_txq); 1964 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 1965 caps->txq_first_id); 1966 break; 1967 case ICE_AQC_CAPS_MSIX: 1968 caps->num_msix_vectors = number; 1969 caps->msix_vector_first_id = phys_id; 1970 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 1971 caps->num_msix_vectors); 1972 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 1973 caps->msix_vector_first_id); 1974 break; 1975 case ICE_AQC_CAPS_NVM_MGMT: 1976 caps->sec_rev_disabled = 1977 (number & ICE_NVM_MGMT_SEC_REV_DISABLED) ? 1978 true : false; 1979 ice_debug(hw, ICE_DBG_INIT, "%s: sec_rev_disabled = %d\n", prefix, 1980 caps->sec_rev_disabled); 1981 caps->update_disabled = 1982 (number & ICE_NVM_MGMT_UPDATE_DISABLED) ? 1983 true : false; 1984 ice_debug(hw, ICE_DBG_INIT, "%s: update_disabled = %d\n", prefix, 1985 caps->update_disabled); 1986 caps->nvm_unified_update = 1987 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 1988 true : false; 1989 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 1990 caps->nvm_unified_update); 1991 break; 1992 case ICE_AQC_CAPS_MAX_MTU: 1993 caps->max_mtu = number; 1994 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 1995 prefix, caps->max_mtu); 1996 break; 1997 default: 1998 /* Not one of the recognized common capabilities */ 1999 found = false; 2000 } 2001 2002 return found; 2003 } 2004 2005 /** 2006 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2007 * @hw: pointer to the HW structure 2008 * @caps: pointer to capabilities structure to fix 2009 * 2010 * Re-calculate the capabilities that are dependent on the number of physical 2011 * ports; i.e. some features are not supported or function differently on 2012 * devices with more than 4 ports. 2013 */ 2014 static void 2015 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2016 { 2017 /* This assumes device capabilities are always scanned before function 2018 * capabilities during the initialization flow. 2019 */ 2020 if (hw->dev_caps.num_funcs > 4) { 2021 /* Max 4 TCs per port */ 2022 caps->maxtc = 4; 2023 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2024 caps->maxtc); 2025 } 2026 } 2027 2028 /** 2029 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2030 * @hw: pointer to the HW struct 2031 * @func_p: pointer to function capabilities structure 2032 * @cap: pointer to the capability element to parse 2033 * 2034 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2035 */ 2036 static void 2037 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2038 struct ice_aqc_list_caps_elem *cap) 2039 { 2040 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2041 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2042 LE32_TO_CPU(cap->number)); 2043 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2044 func_p->guar_num_vsi); 2045 } 2046 2047 /** 2048 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2049 * @hw: pointer to the HW struct 2050 * @func_p: pointer to function capabilities structure 2051 * 2052 * Extract function capabilities for ICE_AQC_CAPS_FD. 2053 */ 2054 static void 2055 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2056 { 2057 u32 reg_val, val; 2058 2059 if (hw->dcf_enabled) 2060 return; 2061 reg_val = rd32(hw, GLQF_FD_SIZE); 2062 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 2063 GLQF_FD_SIZE_FD_GSIZE_S; 2064 func_p->fd_fltr_guar = 2065 ice_get_num_per_func(hw, val); 2066 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 2067 GLQF_FD_SIZE_FD_BSIZE_S; 2068 func_p->fd_fltr_best_effort = val; 2069 2070 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2071 func_p->fd_fltr_guar); 2072 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2073 func_p->fd_fltr_best_effort); 2074 } 2075 2076 /** 2077 * ice_parse_func_caps - Parse function capabilities 2078 * @hw: pointer to the HW struct 2079 * @func_p: pointer to function capabilities structure 2080 * @buf: buffer containing the function capability records 2081 * @cap_count: the number of capabilities 2082 * 2083 * Helper function to parse function (0x000A) capabilities list. For 2084 * capabilities shared between device and function, this relies on 2085 * ice_parse_common_caps. 2086 * 2087 * Loop through the list of provided capabilities and extract the relevant 2088 * data into the function capabilities structured. 2089 */ 2090 static void 2091 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2092 void *buf, u32 cap_count) 2093 { 2094 struct ice_aqc_list_caps_elem *cap_resp; 2095 u32 i; 2096 2097 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 2098 2099 ice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM); 2100 2101 for (i = 0; i < cap_count; i++) { 2102 u16 cap = LE16_TO_CPU(cap_resp[i].cap); 2103 bool found; 2104 2105 found = ice_parse_common_caps(hw, &func_p->common_cap, 2106 &cap_resp[i], "func caps"); 2107 2108 switch (cap) { 2109 case ICE_AQC_CAPS_VSI: 2110 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2111 break; 2112 case ICE_AQC_CAPS_FD: 2113 ice_parse_fdir_func_caps(hw, func_p); 2114 break; 2115 default: 2116 /* Don't list common capabilities as unknown */ 2117 if (!found) 2118 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2119 i, cap); 2120 break; 2121 } 2122 } 2123 2124 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2125 } 2126 2127 /** 2128 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2129 * @hw: pointer to the HW struct 2130 * @dev_p: pointer to device capabilities structure 2131 * @cap: capability element to parse 2132 * 2133 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2134 */ 2135 static void 2136 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2137 struct ice_aqc_list_caps_elem *cap) 2138 { 2139 u32 number = LE32_TO_CPU(cap->number); 2140 2141 dev_p->num_funcs = ice_hweight32(number); 2142 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2143 dev_p->num_funcs); 2144 } 2145 2146 /** 2147 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2148 * @hw: pointer to the HW struct 2149 * @dev_p: pointer to device capabilities structure 2150 * @cap: capability element to parse 2151 * 2152 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2153 */ 2154 static void 2155 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2156 struct ice_aqc_list_caps_elem *cap) 2157 { 2158 u32 number = LE32_TO_CPU(cap->number); 2159 2160 dev_p->num_vsi_allocd_to_host = number; 2161 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2162 dev_p->num_vsi_allocd_to_host); 2163 } 2164 2165 /** 2166 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2167 * @hw: pointer to the HW struct 2168 * @dev_p: pointer to device capabilities structure 2169 * @cap: capability element to parse 2170 * 2171 * Parse ICE_AQC_CAPS_FD for device capabilities. 2172 */ 2173 static void 2174 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2175 struct ice_aqc_list_caps_elem *cap) 2176 { 2177 u32 number = LE32_TO_CPU(cap->number); 2178 2179 dev_p->num_flow_director_fltr = number; 2180 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2181 dev_p->num_flow_director_fltr); 2182 } 2183 2184 /** 2185 * ice_parse_dev_caps - Parse device capabilities 2186 * @hw: pointer to the HW struct 2187 * @dev_p: pointer to device capabilities structure 2188 * @buf: buffer containing the device capability records 2189 * @cap_count: the number of capabilities 2190 * 2191 * Helper device to parse device (0x000B) capabilities list. For 2192 * capabilities shared between device and function, this relies on 2193 * ice_parse_common_caps. 2194 * 2195 * Loop through the list of provided capabilities and extract the relevant 2196 * data into the device capabilities structured. 2197 */ 2198 static void 2199 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2200 void *buf, u32 cap_count) 2201 { 2202 struct ice_aqc_list_caps_elem *cap_resp; 2203 u32 i; 2204 2205 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 2206 2207 ice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM); 2208 2209 for (i = 0; i < cap_count; i++) { 2210 u16 cap = LE16_TO_CPU(cap_resp[i].cap); 2211 bool found; 2212 2213 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2214 &cap_resp[i], "dev caps"); 2215 2216 switch (cap) { 2217 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2218 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2219 break; 2220 case ICE_AQC_CAPS_VSI: 2221 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2222 break; 2223 case ICE_AQC_CAPS_FD: 2224 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2225 break; 2226 default: 2227 /* Don't list common capabilities as unknown */ 2228 if (!found) 2229 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2230 i, cap); 2231 break; 2232 } 2233 } 2234 2235 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2236 } 2237 2238 /** 2239 * ice_aq_list_caps - query function/device capabilities 2240 * @hw: pointer to the HW struct 2241 * @buf: a buffer to hold the capabilities 2242 * @buf_size: size of the buffer 2243 * @cap_count: if not NULL, set to the number of capabilities reported 2244 * @opc: capabilities type to discover, device or function 2245 * @cd: pointer to command details structure or NULL 2246 * 2247 * Get the function (0x000A) or device (0x000B) capabilities description from 2248 * firmware and store it in the buffer. 2249 * 2250 * If the cap_count pointer is not NULL, then it is set to the number of 2251 * capabilities firmware will report. Note that if the buffer size is too 2252 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2253 * cap_count will still be updated in this case. It is recommended that the 2254 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2255 * firmware could return) to avoid this. 2256 */ 2257 static enum ice_status 2258 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2259 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2260 { 2261 struct ice_aqc_list_caps *cmd; 2262 struct ice_aq_desc desc; 2263 enum ice_status status; 2264 2265 cmd = &desc.params.get_cap; 2266 2267 if (opc != ice_aqc_opc_list_func_caps && 2268 opc != ice_aqc_opc_list_dev_caps) 2269 return ICE_ERR_PARAM; 2270 2271 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2272 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2273 2274 if (cap_count) 2275 *cap_count = LE32_TO_CPU(cmd->count); 2276 2277 return status; 2278 } 2279 2280 /** 2281 * ice_discover_dev_caps - Read and extract device capabilities 2282 * @hw: pointer to the hardware structure 2283 * @dev_caps: pointer to device capabilities structure 2284 * 2285 * Read the device capabilities and extract them into the dev_caps structure 2286 * for later use. 2287 */ 2288 static enum ice_status 2289 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2290 { 2291 enum ice_status status; 2292 u32 cap_count = 0; 2293 void *cbuf; 2294 2295 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN); 2296 if (!cbuf) 2297 return ICE_ERR_NO_MEMORY; 2298 2299 /* Although the driver doesn't know the number of capabilities the 2300 * device will return, we can simply send a 4KB buffer, the maximum 2301 * possible size that firmware can return. 2302 */ 2303 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2304 2305 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2306 ice_aqc_opc_list_dev_caps, NULL); 2307 if (!status) 2308 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2309 ice_free(hw, cbuf); 2310 2311 return status; 2312 } 2313 2314 /** 2315 * ice_discover_func_caps - Read and extract function capabilities 2316 * @hw: pointer to the hardware structure 2317 * @func_caps: pointer to function capabilities structure 2318 * 2319 * Read the function capabilities and extract them into the func_caps structure 2320 * for later use. 2321 */ 2322 static enum ice_status 2323 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2324 { 2325 enum ice_status status; 2326 u32 cap_count = 0; 2327 void *cbuf; 2328 2329 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN); 2330 if (!cbuf) 2331 return ICE_ERR_NO_MEMORY; 2332 2333 /* Although the driver doesn't know the number of capabilities the 2334 * device will return, we can simply send a 4KB buffer, the maximum 2335 * possible size that firmware can return. 2336 */ 2337 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2338 2339 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2340 ice_aqc_opc_list_func_caps, NULL); 2341 if (!status) 2342 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2343 ice_free(hw, cbuf); 2344 2345 return status; 2346 } 2347 2348 /** 2349 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2350 * @hw: pointer to the hardware structure 2351 */ 2352 void ice_set_safe_mode_caps(struct ice_hw *hw) 2353 { 2354 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2355 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2356 struct ice_hw_common_caps cached_caps; 2357 u32 num_funcs; 2358 2359 /* cache some func_caps values that should be restored after memset */ 2360 cached_caps = func_caps->common_cap; 2361 2362 /* unset func capabilities */ 2363 memset(func_caps, 0, sizeof(*func_caps)); 2364 2365 #define ICE_RESTORE_FUNC_CAP(name) \ 2366 func_caps->common_cap.name = cached_caps.name 2367 2368 /* restore cached values */ 2369 ICE_RESTORE_FUNC_CAP(valid_functions); 2370 ICE_RESTORE_FUNC_CAP(txq_first_id); 2371 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2372 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2373 ICE_RESTORE_FUNC_CAP(max_mtu); 2374 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2375 2376 /* one Tx and one Rx queue in safe mode */ 2377 func_caps->common_cap.num_rxq = 1; 2378 func_caps->common_cap.num_txq = 1; 2379 2380 /* two MSIX vectors, one for traffic and one for misc causes */ 2381 func_caps->common_cap.num_msix_vectors = 2; 2382 func_caps->guar_num_vsi = 1; 2383 2384 /* cache some dev_caps values that should be restored after memset */ 2385 cached_caps = dev_caps->common_cap; 2386 num_funcs = dev_caps->num_funcs; 2387 2388 /* unset dev capabilities */ 2389 memset(dev_caps, 0, sizeof(*dev_caps)); 2390 2391 #define ICE_RESTORE_DEV_CAP(name) \ 2392 dev_caps->common_cap.name = cached_caps.name 2393 2394 /* restore cached values */ 2395 ICE_RESTORE_DEV_CAP(valid_functions); 2396 ICE_RESTORE_DEV_CAP(txq_first_id); 2397 ICE_RESTORE_DEV_CAP(rxq_first_id); 2398 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2399 ICE_RESTORE_DEV_CAP(max_mtu); 2400 ICE_RESTORE_DEV_CAP(nvm_unified_update); 2401 dev_caps->num_funcs = num_funcs; 2402 2403 /* one Tx and one Rx queue per function in safe mode */ 2404 dev_caps->common_cap.num_rxq = num_funcs; 2405 dev_caps->common_cap.num_txq = num_funcs; 2406 2407 /* two MSIX vectors per function */ 2408 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2409 } 2410 2411 /** 2412 * ice_get_caps - get info about the HW 2413 * @hw: pointer to the hardware structure 2414 */ 2415 enum ice_status ice_get_caps(struct ice_hw *hw) 2416 { 2417 enum ice_status status; 2418 2419 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2420 if (status) 2421 return status; 2422 2423 return ice_discover_func_caps(hw, &hw->func_caps); 2424 } 2425 2426 /** 2427 * ice_aq_manage_mac_write - manage MAC address write command 2428 * @hw: pointer to the HW struct 2429 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2430 * @flags: flags to control write behavior 2431 * @cd: pointer to command details structure or NULL 2432 * 2433 * This function is used to write MAC address to the NVM (0x0108). 2434 */ 2435 enum ice_status 2436 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2437 struct ice_sq_cd *cd) 2438 { 2439 struct ice_aqc_manage_mac_write *cmd; 2440 struct ice_aq_desc desc; 2441 2442 cmd = &desc.params.mac_write; 2443 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2444 2445 cmd->flags = flags; 2446 ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 2447 2448 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2449 } 2450 2451 /** 2452 * ice_aq_clear_pxe_mode 2453 * @hw: pointer to the HW struct 2454 * 2455 * Tell the firmware that the driver is taking over from PXE (0x0110). 2456 */ 2457 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 2458 { 2459 struct ice_aq_desc desc; 2460 2461 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2462 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2463 2464 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2465 } 2466 2467 /** 2468 * ice_clear_pxe_mode - clear pxe operations mode 2469 * @hw: pointer to the HW struct 2470 * 2471 * Make sure all PXE mode settings are cleared, including things 2472 * like descriptor fetch/write-back mode. 2473 */ 2474 void ice_clear_pxe_mode(struct ice_hw *hw) 2475 { 2476 if (ice_check_sq_alive(hw, &hw->adminq)) 2477 ice_aq_clear_pxe_mode(hw); 2478 } 2479 2480 /** 2481 * ice_aq_set_port_params - set physical port parameters. 2482 * @pi: pointer to the port info struct 2483 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 2484 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 2485 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 2486 * @double_vlan: if set double VLAN is enabled 2487 * @cd: pointer to command details structure or NULL 2488 * 2489 * Set Physical port parameters (0x0203) 2490 */ 2491 enum ice_status 2492 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi, 2493 bool save_bad_pac, bool pad_short_pac, bool double_vlan, 2494 struct ice_sq_cd *cd) 2495 2496 { 2497 struct ice_aqc_set_port_params *cmd; 2498 struct ice_hw *hw = pi->hw; 2499 struct ice_aq_desc desc; 2500 u16 cmd_flags = 0; 2501 2502 cmd = &desc.params.set_port_params; 2503 2504 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 2505 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 2506 if (save_bad_pac) 2507 cmd_flags |= ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS; 2508 if (pad_short_pac) 2509 cmd_flags |= ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS; 2510 if (double_vlan) 2511 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 2512 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 2513 2514 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2515 } 2516 2517 /** 2518 * ice_get_link_speed_based_on_phy_type - returns link speed 2519 * @phy_type_low: lower part of phy_type 2520 * @phy_type_high: higher part of phy_type 2521 * 2522 * This helper function will convert an entry in PHY type structure 2523 * [phy_type_low, phy_type_high] to its corresponding link speed. 2524 * Note: In the structure of [phy_type_low, phy_type_high], there should 2525 * be one bit set, as this function will convert one PHY type to its 2526 * speed. 2527 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2528 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2529 */ 2530 static u16 2531 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 2532 { 2533 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2534 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2535 2536 switch (phy_type_low) { 2537 case ICE_PHY_TYPE_LOW_100BASE_TX: 2538 case ICE_PHY_TYPE_LOW_100M_SGMII: 2539 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 2540 break; 2541 case ICE_PHY_TYPE_LOW_1000BASE_T: 2542 case ICE_PHY_TYPE_LOW_1000BASE_SX: 2543 case ICE_PHY_TYPE_LOW_1000BASE_LX: 2544 case ICE_PHY_TYPE_LOW_1000BASE_KX: 2545 case ICE_PHY_TYPE_LOW_1G_SGMII: 2546 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 2547 break; 2548 case ICE_PHY_TYPE_LOW_2500BASE_T: 2549 case ICE_PHY_TYPE_LOW_2500BASE_X: 2550 case ICE_PHY_TYPE_LOW_2500BASE_KX: 2551 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 2552 break; 2553 case ICE_PHY_TYPE_LOW_5GBASE_T: 2554 case ICE_PHY_TYPE_LOW_5GBASE_KR: 2555 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 2556 break; 2557 case ICE_PHY_TYPE_LOW_10GBASE_T: 2558 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 2559 case ICE_PHY_TYPE_LOW_10GBASE_SR: 2560 case ICE_PHY_TYPE_LOW_10GBASE_LR: 2561 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 2562 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 2563 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 2564 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 2565 break; 2566 case ICE_PHY_TYPE_LOW_25GBASE_T: 2567 case ICE_PHY_TYPE_LOW_25GBASE_CR: 2568 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 2569 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 2570 case ICE_PHY_TYPE_LOW_25GBASE_SR: 2571 case ICE_PHY_TYPE_LOW_25GBASE_LR: 2572 case ICE_PHY_TYPE_LOW_25GBASE_KR: 2573 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 2574 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 2575 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 2576 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 2577 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 2578 break; 2579 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 2580 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 2581 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 2582 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 2583 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 2584 case ICE_PHY_TYPE_LOW_40G_XLAUI: 2585 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 2586 break; 2587 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 2588 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 2589 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 2590 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 2591 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 2592 case ICE_PHY_TYPE_LOW_50G_LAUI2: 2593 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 2594 case ICE_PHY_TYPE_LOW_50G_AUI2: 2595 case ICE_PHY_TYPE_LOW_50GBASE_CP: 2596 case ICE_PHY_TYPE_LOW_50GBASE_SR: 2597 case ICE_PHY_TYPE_LOW_50GBASE_FR: 2598 case ICE_PHY_TYPE_LOW_50GBASE_LR: 2599 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 2600 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 2601 case ICE_PHY_TYPE_LOW_50G_AUI1: 2602 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 2603 break; 2604 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 2605 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 2606 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 2607 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 2608 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 2609 case ICE_PHY_TYPE_LOW_100G_CAUI4: 2610 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 2611 case ICE_PHY_TYPE_LOW_100G_AUI4: 2612 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 2613 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 2614 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 2615 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 2616 case ICE_PHY_TYPE_LOW_100GBASE_DR: 2617 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 2618 break; 2619 default: 2620 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2621 break; 2622 } 2623 2624 switch (phy_type_high) { 2625 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 2626 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 2627 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 2628 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 2629 case ICE_PHY_TYPE_HIGH_100G_AUI2: 2630 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 2631 break; 2632 default: 2633 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2634 break; 2635 } 2636 2637 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 2638 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2639 return ICE_AQ_LINK_SPEED_UNKNOWN; 2640 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2641 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 2642 return ICE_AQ_LINK_SPEED_UNKNOWN; 2643 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2644 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2645 return speed_phy_type_low; 2646 else 2647 return speed_phy_type_high; 2648 } 2649 2650 /** 2651 * ice_update_phy_type 2652 * @phy_type_low: pointer to the lower part of phy_type 2653 * @phy_type_high: pointer to the higher part of phy_type 2654 * @link_speeds_bitmap: targeted link speeds bitmap 2655 * 2656 * Note: For the link_speeds_bitmap structure, you can check it at 2657 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 2658 * link_speeds_bitmap include multiple speeds. 2659 * 2660 * Each entry in this [phy_type_low, phy_type_high] structure will 2661 * present a certain link speed. This helper function will turn on bits 2662 * in [phy_type_low, phy_type_high] structure based on the value of 2663 * link_speeds_bitmap input parameter. 2664 */ 2665 void 2666 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 2667 u16 link_speeds_bitmap) 2668 { 2669 u64 pt_high; 2670 u64 pt_low; 2671 int index; 2672 u16 speed; 2673 2674 /* We first check with low part of phy_type */ 2675 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 2676 pt_low = BIT_ULL(index); 2677 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 2678 2679 if (link_speeds_bitmap & speed) 2680 *phy_type_low |= BIT_ULL(index); 2681 } 2682 2683 /* We then check with high part of phy_type */ 2684 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 2685 pt_high = BIT_ULL(index); 2686 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 2687 2688 if (link_speeds_bitmap & speed) 2689 *phy_type_high |= BIT_ULL(index); 2690 } 2691 } 2692 2693 /** 2694 * ice_aq_set_phy_cfg 2695 * @hw: pointer to the HW struct 2696 * @pi: port info structure of the interested logical port 2697 * @cfg: structure with PHY configuration data to be set 2698 * @cd: pointer to command details structure or NULL 2699 * 2700 * Set the various PHY configuration parameters supported on the Port. 2701 * One or more of the Set PHY config parameters may be ignored in an MFP 2702 * mode as the PF may not have the privilege to set some of the PHY Config 2703 * parameters. This status will be indicated by the command response (0x0601). 2704 */ 2705 enum ice_status 2706 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 2707 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 2708 { 2709 struct ice_aq_desc desc; 2710 enum ice_status status; 2711 2712 if (!cfg) 2713 return ICE_ERR_PARAM; 2714 2715 /* Ensure that only valid bits of cfg->caps can be turned on. */ 2716 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 2717 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 2718 cfg->caps); 2719 2720 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 2721 } 2722 2723 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 2724 desc.params.set_phy.lport_num = pi->lport; 2725 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 2726 2727 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 2728 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 2729 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low)); 2730 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 2731 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high)); 2732 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 2733 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 2734 cfg->low_power_ctrl_an); 2735 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 2736 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 2737 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 2738 cfg->link_fec_opt); 2739 2740 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 2741 2742 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 2743 status = ICE_SUCCESS; 2744 2745 if (!status) 2746 pi->phy.curr_user_phy_cfg = *cfg; 2747 2748 return status; 2749 } 2750 2751 /** 2752 * ice_update_link_info - update status of the HW network link 2753 * @pi: port info structure of the interested logical port 2754 */ 2755 enum ice_status ice_update_link_info(struct ice_port_info *pi) 2756 { 2757 struct ice_link_status *li; 2758 enum ice_status status; 2759 2760 if (!pi) 2761 return ICE_ERR_PARAM; 2762 2763 li = &pi->phy.link_info; 2764 2765 status = ice_aq_get_link_info(pi, true, NULL, NULL); 2766 if (status) 2767 return status; 2768 2769 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 2770 struct ice_aqc_get_phy_caps_data *pcaps; 2771 struct ice_hw *hw; 2772 2773 hw = pi->hw; 2774 pcaps = (struct ice_aqc_get_phy_caps_data *) 2775 ice_malloc(hw, sizeof(*pcaps)); 2776 if (!pcaps) 2777 return ICE_ERR_NO_MEMORY; 2778 2779 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 2780 pcaps, NULL); 2781 2782 if (status == ICE_SUCCESS) 2783 ice_memcpy(li->module_type, &pcaps->module_type, 2784 sizeof(li->module_type), 2785 ICE_NONDMA_TO_NONDMA); 2786 2787 ice_free(hw, pcaps); 2788 } 2789 2790 return status; 2791 } 2792 2793 /** 2794 * ice_cache_phy_user_req 2795 * @pi: port information structure 2796 * @cache_data: PHY logging data 2797 * @cache_mode: PHY logging mode 2798 * 2799 * Log the user request on (FC, FEC, SPEED) for later user. 2800 */ 2801 static void 2802 ice_cache_phy_user_req(struct ice_port_info *pi, 2803 struct ice_phy_cache_mode_data cache_data, 2804 enum ice_phy_cache_mode cache_mode) 2805 { 2806 if (!pi) 2807 return; 2808 2809 switch (cache_mode) { 2810 case ICE_FC_MODE: 2811 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 2812 break; 2813 case ICE_SPEED_MODE: 2814 pi->phy.curr_user_speed_req = 2815 cache_data.data.curr_user_speed_req; 2816 break; 2817 case ICE_FEC_MODE: 2818 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 2819 break; 2820 default: 2821 break; 2822 } 2823 } 2824 2825 /** 2826 * ice_caps_to_fc_mode 2827 * @caps: PHY capabilities 2828 * 2829 * Convert PHY FC capabilities to ice FC mode 2830 */ 2831 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 2832 { 2833 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 2834 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2835 return ICE_FC_FULL; 2836 2837 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 2838 return ICE_FC_TX_PAUSE; 2839 2840 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2841 return ICE_FC_RX_PAUSE; 2842 2843 return ICE_FC_NONE; 2844 } 2845 2846 /** 2847 * ice_caps_to_fec_mode 2848 * @caps: PHY capabilities 2849 * @fec_options: Link FEC options 2850 * 2851 * Convert PHY FEC capabilities to ice FEC mode 2852 */ 2853 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 2854 { 2855 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 2856 return ICE_FEC_AUTO; 2857 2858 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2859 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 2860 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 2861 ICE_AQC_PHY_FEC_25G_KR_REQ)) 2862 return ICE_FEC_BASER; 2863 2864 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 2865 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 2866 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 2867 return ICE_FEC_RS; 2868 2869 return ICE_FEC_NONE; 2870 } 2871 2872 /** 2873 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 2874 * @pi: port information structure 2875 * @cfg: PHY configuration data to set FC mode 2876 * @req_mode: FC mode to configure 2877 */ 2878 static enum ice_status 2879 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 2880 enum ice_fc_mode req_mode) 2881 { 2882 struct ice_phy_cache_mode_data cache_data; 2883 u8 pause_mask = 0x0; 2884 2885 if (!pi || !cfg) 2886 return ICE_ERR_BAD_PTR; 2887 2888 switch (req_mode) { 2889 case ICE_FC_AUTO: 2890 { 2891 struct ice_aqc_get_phy_caps_data *pcaps; 2892 enum ice_status status; 2893 2894 pcaps = (struct ice_aqc_get_phy_caps_data *) 2895 ice_malloc(pi->hw, sizeof(*pcaps)); 2896 if (!pcaps) 2897 return ICE_ERR_NO_MEMORY; 2898 2899 /* Query the value of FC that both the NIC and attached media 2900 * can do. 2901 */ 2902 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 2903 pcaps, NULL); 2904 if (status) { 2905 ice_free(pi->hw, pcaps); 2906 return status; 2907 } 2908 2909 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2910 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2911 2912 ice_free(pi->hw, pcaps); 2913 break; 2914 } 2915 case ICE_FC_FULL: 2916 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2917 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2918 break; 2919 case ICE_FC_RX_PAUSE: 2920 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2921 break; 2922 case ICE_FC_TX_PAUSE: 2923 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2924 break; 2925 default: 2926 break; 2927 } 2928 2929 /* clear the old pause settings */ 2930 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 2931 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 2932 2933 /* set the new capabilities */ 2934 cfg->caps |= pause_mask; 2935 2936 /* Cache user FC request */ 2937 cache_data.data.curr_user_fc_req = req_mode; 2938 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 2939 2940 return ICE_SUCCESS; 2941 } 2942 2943 /** 2944 * ice_set_fc 2945 * @pi: port information structure 2946 * @aq_failures: pointer to status code, specific to ice_set_fc routine 2947 * @ena_auto_link_update: enable automatic link update 2948 * 2949 * Set the requested flow control mode. 2950 */ 2951 enum ice_status 2952 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 2953 { 2954 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 2955 struct ice_aqc_get_phy_caps_data *pcaps; 2956 enum ice_status status; 2957 struct ice_hw *hw; 2958 2959 if (!pi || !aq_failures) 2960 return ICE_ERR_BAD_PTR; 2961 2962 *aq_failures = 0; 2963 hw = pi->hw; 2964 2965 pcaps = (struct ice_aqc_get_phy_caps_data *) 2966 ice_malloc(hw, sizeof(*pcaps)); 2967 if (!pcaps) 2968 return ICE_ERR_NO_MEMORY; 2969 2970 /* Get the current PHY config */ 2971 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 2972 pcaps, NULL); 2973 2974 if (status) { 2975 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2976 goto out; 2977 } 2978 2979 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 2980 2981 /* Configure the set PHY data */ 2982 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 2983 if (status) { 2984 if (status != ICE_ERR_BAD_PTR) 2985 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2986 2987 goto out; 2988 } 2989 2990 /* If the capabilities have changed, then set the new config */ 2991 if (cfg.caps != pcaps->caps) { 2992 int retry_count, retry_max = 10; 2993 2994 /* Auto restart link so settings take effect */ 2995 if (ena_auto_link_update) 2996 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2997 2998 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 2999 if (status) { 3000 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3001 goto out; 3002 } 3003 3004 /* Update the link info 3005 * It sometimes takes a really long time for link to 3006 * come back from the atomic reset. Thus, we wait a 3007 * little bit. 3008 */ 3009 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3010 status = ice_update_link_info(pi); 3011 3012 if (status == ICE_SUCCESS) 3013 break; 3014 3015 ice_msec_delay(100, true); 3016 } 3017 3018 if (status) 3019 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3020 } 3021 3022 out: 3023 ice_free(hw, pcaps); 3024 return status; 3025 } 3026 3027 /** 3028 * ice_phy_caps_equals_cfg 3029 * @phy_caps: PHY capabilities 3030 * @phy_cfg: PHY configuration 3031 * 3032 * Helper function to determine if PHY capabilities matches PHY 3033 * configuration 3034 */ 3035 bool 3036 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3037 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3038 { 3039 u8 caps_mask, cfg_mask; 3040 3041 if (!phy_caps || !phy_cfg) 3042 return false; 3043 3044 /* These bits are not common between capabilities and configuration. 3045 * Do not use them to determine equality. 3046 */ 3047 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3048 ICE_AQC_PHY_EN_MOD_QUAL); 3049 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3050 3051 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3052 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3053 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3054 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3055 phy_caps->eee_cap != phy_cfg->eee_cap || 3056 phy_caps->eeer_value != phy_cfg->eeer_value || 3057 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3058 return false; 3059 3060 return true; 3061 } 3062 3063 /** 3064 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3065 * @pi: port information structure 3066 * @caps: PHY ability structure to copy date from 3067 * @cfg: PHY configuration structure to copy data to 3068 * 3069 * Helper function to copy AQC PHY get ability data to PHY set configuration 3070 * data structure 3071 */ 3072 void 3073 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3074 struct ice_aqc_get_phy_caps_data *caps, 3075 struct ice_aqc_set_phy_cfg_data *cfg) 3076 { 3077 if (!pi || !caps || !cfg) 3078 return; 3079 3080 ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM); 3081 cfg->phy_type_low = caps->phy_type_low; 3082 cfg->phy_type_high = caps->phy_type_high; 3083 cfg->caps = caps->caps; 3084 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3085 cfg->eee_cap = caps->eee_cap; 3086 cfg->eeer_value = caps->eeer_value; 3087 cfg->link_fec_opt = caps->link_fec_options; 3088 cfg->module_compliance_enforcement = 3089 caps->module_compliance_enforcement; 3090 } 3091 3092 /** 3093 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3094 * @pi: port information structure 3095 * @cfg: PHY configuration data to set FEC mode 3096 * @fec: FEC mode to configure 3097 */ 3098 enum ice_status 3099 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3100 enum ice_fec_mode fec) 3101 { 3102 struct ice_aqc_get_phy_caps_data *pcaps; 3103 enum ice_status status = ICE_SUCCESS; 3104 struct ice_hw *hw; 3105 3106 if (!pi || !cfg) 3107 return ICE_ERR_BAD_PTR; 3108 3109 hw = pi->hw; 3110 3111 pcaps = (struct ice_aqc_get_phy_caps_data *) 3112 ice_malloc(hw, sizeof(*pcaps)); 3113 if (!pcaps) 3114 return ICE_ERR_NO_MEMORY; 3115 3116 status = ice_aq_get_phy_caps(pi, false, 3117 (ice_fw_supports_report_dflt_cfg(hw) ? 3118 ICE_AQC_REPORT_DFLT_CFG : 3119 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3120 3121 if (status) 3122 goto out; 3123 3124 cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC); 3125 cfg->link_fec_opt = pcaps->link_fec_options; 3126 3127 switch (fec) { 3128 case ICE_FEC_BASER: 3129 /* Clear RS bits, and AND BASE-R ability 3130 * bits and OR request bits. 3131 */ 3132 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3133 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3134 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3135 ICE_AQC_PHY_FEC_25G_KR_REQ; 3136 break; 3137 case ICE_FEC_RS: 3138 /* Clear BASE-R bits, and AND RS ability 3139 * bits and OR request bits. 3140 */ 3141 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3142 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3143 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3144 break; 3145 case ICE_FEC_NONE: 3146 /* Clear all FEC option bits. */ 3147 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3148 break; 3149 case ICE_FEC_AUTO: 3150 /* AND auto FEC bit, and all caps bits. */ 3151 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 3152 cfg->link_fec_opt |= pcaps->link_fec_options; 3153 break; 3154 default: 3155 status = ICE_ERR_PARAM; 3156 break; 3157 } 3158 3159 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw) && 3160 !ice_fw_supports_report_dflt_cfg(pi->hw)) { 3161 struct ice_link_default_override_tlv tlv; 3162 3163 if (ice_get_link_default_override(&tlv, pi)) 3164 goto out; 3165 3166 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3167 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3168 cfg->link_fec_opt = tlv.fec_options; 3169 } 3170 3171 out: 3172 ice_free(hw, pcaps); 3173 3174 return status; 3175 } 3176 3177 /** 3178 * ice_get_link_status - get status of the HW network link 3179 * @pi: port information structure 3180 * @link_up: pointer to bool (true/false = linkup/linkdown) 3181 * 3182 * Variable link_up is true if link is up, false if link is down. 3183 * The variable link_up is invalid if status is non zero. As a 3184 * result of this call, link status reporting becomes enabled 3185 */ 3186 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3187 { 3188 struct ice_phy_info *phy_info; 3189 enum ice_status status = ICE_SUCCESS; 3190 3191 if (!pi || !link_up) 3192 return ICE_ERR_PARAM; 3193 3194 phy_info = &pi->phy; 3195 3196 if (phy_info->get_link_info) { 3197 status = ice_update_link_info(pi); 3198 3199 if (status) 3200 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3201 status); 3202 } 3203 3204 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3205 3206 return status; 3207 } 3208 3209 /** 3210 * ice_aq_set_link_restart_an 3211 * @pi: pointer to the port information structure 3212 * @ena_link: if true: enable link, if false: disable link 3213 * @cd: pointer to command details structure or NULL 3214 * 3215 * Sets up the link and restarts the Auto-Negotiation over the link. 3216 */ 3217 enum ice_status 3218 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3219 struct ice_sq_cd *cd) 3220 { 3221 struct ice_aqc_restart_an *cmd; 3222 struct ice_aq_desc desc; 3223 3224 cmd = &desc.params.restart_an; 3225 3226 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3227 3228 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3229 cmd->lport_num = pi->lport; 3230 if (ena_link) 3231 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3232 else 3233 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3234 3235 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3236 } 3237 3238 /** 3239 * ice_aq_set_event_mask 3240 * @hw: pointer to the HW struct 3241 * @port_num: port number of the physical function 3242 * @mask: event mask to be set 3243 * @cd: pointer to command details structure or NULL 3244 * 3245 * Set event mask (0x0613) 3246 */ 3247 enum ice_status 3248 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3249 struct ice_sq_cd *cd) 3250 { 3251 struct ice_aqc_set_event_mask *cmd; 3252 struct ice_aq_desc desc; 3253 3254 cmd = &desc.params.set_event_mask; 3255 3256 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3257 3258 cmd->lport_num = port_num; 3259 3260 cmd->event_mask = CPU_TO_LE16(mask); 3261 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3262 } 3263 3264 /** 3265 * ice_aq_set_mac_loopback 3266 * @hw: pointer to the HW struct 3267 * @ena_lpbk: Enable or Disable loopback 3268 * @cd: pointer to command details structure or NULL 3269 * 3270 * Enable/disable loopback on a given port 3271 */ 3272 enum ice_status 3273 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3274 { 3275 struct ice_aqc_set_mac_lb *cmd; 3276 struct ice_aq_desc desc; 3277 3278 cmd = &desc.params.set_mac_lb; 3279 3280 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3281 if (ena_lpbk) 3282 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3283 3284 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3285 } 3286 3287 /** 3288 * ice_aq_set_port_id_led 3289 * @pi: pointer to the port information 3290 * @is_orig_mode: is this LED set to original mode (by the net-list) 3291 * @cd: pointer to command details structure or NULL 3292 * 3293 * Set LED value for the given port (0x06e9) 3294 */ 3295 enum ice_status 3296 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3297 struct ice_sq_cd *cd) 3298 { 3299 struct ice_aqc_set_port_id_led *cmd; 3300 struct ice_hw *hw = pi->hw; 3301 struct ice_aq_desc desc; 3302 3303 cmd = &desc.params.set_port_id_led; 3304 3305 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3306 3307 if (is_orig_mode) 3308 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3309 else 3310 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3311 3312 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3313 } 3314 3315 /** 3316 * ice_aq_sff_eeprom 3317 * @hw: pointer to the HW struct 3318 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3319 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3320 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3321 * @page: QSFP page 3322 * @set_page: set or ignore the page 3323 * @data: pointer to data buffer to be read/written to the I2C device. 3324 * @length: 1-16 for read, 1 for write. 3325 * @write: 0 read, 1 for write. 3326 * @cd: pointer to command details structure or NULL 3327 * 3328 * Read/Write SFF EEPROM (0x06EE) 3329 */ 3330 enum ice_status 3331 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3332 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3333 bool write, struct ice_sq_cd *cd) 3334 { 3335 struct ice_aqc_sff_eeprom *cmd; 3336 struct ice_aq_desc desc; 3337 enum ice_status status; 3338 3339 if (!data || (mem_addr & 0xff00)) 3340 return ICE_ERR_PARAM; 3341 3342 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3343 cmd = &desc.params.read_write_sff_param; 3344 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD); 3345 cmd->lport_num = (u8)(lport & 0xff); 3346 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3347 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) & 3348 ICE_AQC_SFF_I2CBUS_7BIT_M) | 3349 ((set_page << 3350 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3351 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3352 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff); 3353 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3354 if (write) 3355 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE); 3356 3357 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3358 return status; 3359 } 3360 3361 /** 3362 * __ice_aq_get_set_rss_lut 3363 * @hw: pointer to the hardware structure 3364 * @params: RSS LUT parameters 3365 * @set: set true to set the table, false to get the table 3366 * 3367 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3368 */ 3369 static enum ice_status 3370 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set) 3371 { 3372 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle; 3373 struct ice_aqc_get_set_rss_lut *cmd_resp; 3374 struct ice_aq_desc desc; 3375 enum ice_status status; 3376 u8 *lut; 3377 3378 if (!params) 3379 return ICE_ERR_PARAM; 3380 3381 vsi_handle = params->vsi_handle; 3382 lut = params->lut; 3383 3384 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3385 return ICE_ERR_PARAM; 3386 3387 lut_size = params->lut_size; 3388 lut_type = params->lut_type; 3389 glob_lut_idx = params->global_lut_id; 3390 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 3391 3392 cmd_resp = &desc.params.get_set_rss_lut; 3393 3394 if (set) { 3395 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 3396 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3397 } else { 3398 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 3399 } 3400 3401 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 3402 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 3403 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 3404 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 3405 3406 switch (lut_type) { 3407 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 3408 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 3409 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 3410 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 3411 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 3412 break; 3413 default: 3414 status = ICE_ERR_PARAM; 3415 goto ice_aq_get_set_rss_lut_exit; 3416 } 3417 3418 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 3419 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 3420 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 3421 3422 if (!set) 3423 goto ice_aq_get_set_rss_lut_send; 3424 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3425 if (!set) 3426 goto ice_aq_get_set_rss_lut_send; 3427 } else { 3428 goto ice_aq_get_set_rss_lut_send; 3429 } 3430 3431 /* LUT size is only valid for Global and PF table types */ 3432 switch (lut_size) { 3433 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 3434 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG << 3435 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3436 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3437 break; 3438 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 3439 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 3440 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3441 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3442 break; 3443 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 3444 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3445 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 3446 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3447 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3448 break; 3449 } 3450 /* fall-through */ 3451 default: 3452 status = ICE_ERR_PARAM; 3453 goto ice_aq_get_set_rss_lut_exit; 3454 } 3455 3456 ice_aq_get_set_rss_lut_send: 3457 cmd_resp->flags = CPU_TO_LE16(flags); 3458 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 3459 3460 ice_aq_get_set_rss_lut_exit: 3461 return status; 3462 } 3463 3464 /** 3465 * ice_aq_get_rss_lut 3466 * @hw: pointer to the hardware structure 3467 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 3468 * 3469 * get the RSS lookup table, PF or VSI type 3470 */ 3471 enum ice_status 3472 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 3473 { 3474 return __ice_aq_get_set_rss_lut(hw, get_params, false); 3475 } 3476 3477 /** 3478 * ice_aq_set_rss_lut 3479 * @hw: pointer to the hardware structure 3480 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 3481 * 3482 * set the RSS lookup table, PF or VSI type 3483 */ 3484 enum ice_status 3485 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 3486 { 3487 return __ice_aq_get_set_rss_lut(hw, set_params, true); 3488 } 3489 3490 /** 3491 * __ice_aq_get_set_rss_key 3492 * @hw: pointer to the HW struct 3493 * @vsi_id: VSI FW index 3494 * @key: pointer to key info struct 3495 * @set: set true to set the key, false to get the key 3496 * 3497 * get (0x0B04) or set (0x0B02) the RSS key per VSI 3498 */ 3499 static enum 3500 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 3501 struct ice_aqc_get_set_rss_keys *key, 3502 bool set) 3503 { 3504 struct ice_aqc_get_set_rss_key *cmd_resp; 3505 u16 key_size = sizeof(*key); 3506 struct ice_aq_desc desc; 3507 3508 cmd_resp = &desc.params.get_set_rss_key; 3509 3510 if (set) { 3511 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 3512 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3513 } else { 3514 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 3515 } 3516 3517 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 3518 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 3519 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 3520 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 3521 3522 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 3523 } 3524 3525 /** 3526 * ice_aq_get_rss_key 3527 * @hw: pointer to the HW struct 3528 * @vsi_handle: software VSI handle 3529 * @key: pointer to key info struct 3530 * 3531 * get the RSS key per VSI 3532 */ 3533 enum ice_status 3534 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 3535 struct ice_aqc_get_set_rss_keys *key) 3536 { 3537 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 3538 return ICE_ERR_PARAM; 3539 3540 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3541 key, false); 3542 } 3543 3544 /** 3545 * ice_aq_set_rss_key 3546 * @hw: pointer to the HW struct 3547 * @vsi_handle: software VSI handle 3548 * @keys: pointer to key info struct 3549 * 3550 * set the RSS key per VSI 3551 */ 3552 enum ice_status 3553 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 3554 struct ice_aqc_get_set_rss_keys *keys) 3555 { 3556 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 3557 return ICE_ERR_PARAM; 3558 3559 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3560 keys, true); 3561 } 3562 3563 /** 3564 * ice_aq_add_lan_txq 3565 * @hw: pointer to the hardware structure 3566 * @num_qgrps: Number of added queue groups 3567 * @qg_list: list of queue groups to be added 3568 * @buf_size: size of buffer for indirect command 3569 * @cd: pointer to command details structure or NULL 3570 * 3571 * Add Tx LAN queue (0x0C30) 3572 * 3573 * NOTE: 3574 * Prior to calling add Tx LAN queue: 3575 * Initialize the following as part of the Tx queue context: 3576 * Completion queue ID if the queue uses Completion queue, Quanta profile, 3577 * Cache profile and Packet shaper profile. 3578 * 3579 * After add Tx LAN queue AQ command is completed: 3580 * Interrupts should be associated with specific queues, 3581 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 3582 * flow. 3583 */ 3584 enum ice_status 3585 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3586 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 3587 struct ice_sq_cd *cd) 3588 { 3589 struct ice_aqc_add_tx_qgrp *list; 3590 struct ice_aqc_add_txqs *cmd; 3591 struct ice_aq_desc desc; 3592 u16 i, sum_size = 0; 3593 3594 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 3595 3596 cmd = &desc.params.add_txqs; 3597 3598 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 3599 3600 if (!qg_list) 3601 return ICE_ERR_PARAM; 3602 3603 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3604 return ICE_ERR_PARAM; 3605 3606 for (i = 0, list = qg_list; i < num_qgrps; i++) { 3607 sum_size += ice_struct_size(list, txqs, list->num_txqs); 3608 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 3609 list->num_txqs); 3610 } 3611 3612 if (buf_size != sum_size) 3613 return ICE_ERR_PARAM; 3614 3615 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3616 3617 cmd->num_qgrps = num_qgrps; 3618 3619 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3620 } 3621 3622 /** 3623 * ice_aq_dis_lan_txq 3624 * @hw: pointer to the hardware structure 3625 * @num_qgrps: number of groups in the list 3626 * @qg_list: the list of groups to disable 3627 * @buf_size: the total size of the qg_list buffer in bytes 3628 * @rst_src: if called due to reset, specifies the reset source 3629 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3630 * @cd: pointer to command details structure or NULL 3631 * 3632 * Disable LAN Tx queue (0x0C31) 3633 */ 3634 static enum ice_status 3635 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3636 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 3637 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3638 struct ice_sq_cd *cd) 3639 { 3640 struct ice_aqc_dis_txq_item *item; 3641 struct ice_aqc_dis_txqs *cmd; 3642 struct ice_aq_desc desc; 3643 enum ice_status status; 3644 u16 i, sz = 0; 3645 3646 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 3647 cmd = &desc.params.dis_txqs; 3648 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 3649 3650 /* qg_list can be NULL only in VM/VF reset flow */ 3651 if (!qg_list && !rst_src) 3652 return ICE_ERR_PARAM; 3653 3654 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3655 return ICE_ERR_PARAM; 3656 3657 cmd->num_entries = num_qgrps; 3658 3659 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 3660 ICE_AQC_Q_DIS_TIMEOUT_M); 3661 3662 switch (rst_src) { 3663 case ICE_VM_RESET: 3664 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 3665 cmd->vmvf_and_timeout |= 3666 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 3667 break; 3668 case ICE_NO_RESET: 3669 default: 3670 break; 3671 } 3672 3673 /* flush pipe on time out */ 3674 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 3675 /* If no queue group info, we are in a reset flow. Issue the AQ */ 3676 if (!qg_list) 3677 goto do_aq; 3678 3679 /* set RD bit to indicate that command buffer is provided by the driver 3680 * and it needs to be read by the firmware 3681 */ 3682 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3683 3684 for (i = 0, item = qg_list; i < num_qgrps; i++) { 3685 u16 item_size = ice_struct_size(item, q_id, item->num_qs); 3686 3687 /* If the num of queues is even, add 2 bytes of padding */ 3688 if ((item->num_qs % 2) == 0) 3689 item_size += 2; 3690 3691 sz += item_size; 3692 3693 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 3694 } 3695 3696 if (buf_size != sz) 3697 return ICE_ERR_PARAM; 3698 3699 do_aq: 3700 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3701 if (status) { 3702 if (!qg_list) 3703 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 3704 vmvf_num, hw->adminq.sq_last_status); 3705 else 3706 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 3707 LE16_TO_CPU(qg_list[0].q_id[0]), 3708 hw->adminq.sq_last_status); 3709 } 3710 return status; 3711 } 3712 3713 /** 3714 * ice_aq_move_recfg_lan_txq 3715 * @hw: pointer to the hardware structure 3716 * @num_qs: number of queues to move/reconfigure 3717 * @is_move: true if this operation involves node movement 3718 * @is_tc_change: true if this operation involves a TC change 3719 * @subseq_call: true if this operation is a subsequent call 3720 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN 3721 * @timeout: timeout in units of 100 usec (valid values 0-50) 3722 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN 3723 * @buf: struct containing src/dest TEID and per-queue info 3724 * @buf_size: size of buffer for indirect command 3725 * @txqs_moved: out param, number of queues successfully moved 3726 * @cd: pointer to command details structure or NULL 3727 * 3728 * Move / Reconfigure Tx LAN queues (0x0C32) 3729 */ 3730 enum ice_status 3731 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move, 3732 bool is_tc_change, bool subseq_call, bool flush_pipe, 3733 u8 timeout, u32 *blocked_cgds, 3734 struct ice_aqc_move_txqs_data *buf, u16 buf_size, 3735 u8 *txqs_moved, struct ice_sq_cd *cd) 3736 { 3737 struct ice_aqc_move_txqs *cmd; 3738 struct ice_aq_desc desc; 3739 enum ice_status status; 3740 3741 cmd = &desc.params.move_txqs; 3742 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs); 3743 3744 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50 3745 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX) 3746 return ICE_ERR_PARAM; 3747 3748 if (is_tc_change && !flush_pipe && !blocked_cgds) 3749 return ICE_ERR_PARAM; 3750 3751 if (!is_move && !is_tc_change) 3752 return ICE_ERR_PARAM; 3753 3754 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3755 3756 if (is_move) 3757 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE; 3758 3759 if (is_tc_change) 3760 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE; 3761 3762 if (subseq_call) 3763 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL; 3764 3765 if (flush_pipe) 3766 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE; 3767 3768 cmd->num_qs = num_qs; 3769 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) & 3770 ICE_AQC_Q_CMD_TIMEOUT_M); 3771 3772 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 3773 3774 if (!status && txqs_moved) 3775 *txqs_moved = cmd->num_qs; 3776 3777 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN && 3778 is_tc_change && !flush_pipe) 3779 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds); 3780 3781 return status; 3782 } 3783 3784 /* End of FW Admin Queue command wrappers */ 3785 3786 /** 3787 * ice_write_byte - write a byte to a packed context structure 3788 * @src_ctx: the context structure to read from 3789 * @dest_ctx: the context to be written to 3790 * @ce_info: a description of the struct to be filled 3791 */ 3792 static void 3793 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3794 { 3795 u8 src_byte, dest_byte, mask; 3796 u8 *from, *dest; 3797 u16 shift_width; 3798 3799 /* copy from the next struct field */ 3800 from = src_ctx + ce_info->offset; 3801 3802 /* prepare the bits and mask */ 3803 shift_width = ce_info->lsb % 8; 3804 mask = (u8)(BIT(ce_info->width) - 1); 3805 3806 src_byte = *from; 3807 src_byte &= mask; 3808 3809 /* shift to correct alignment */ 3810 mask <<= shift_width; 3811 src_byte <<= shift_width; 3812 3813 /* get the current bits from the target bit string */ 3814 dest = dest_ctx + (ce_info->lsb / 8); 3815 3816 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 3817 3818 dest_byte &= ~mask; /* get the bits not changing */ 3819 dest_byte |= src_byte; /* add in the new bits */ 3820 3821 /* put it all back */ 3822 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 3823 } 3824 3825 /** 3826 * ice_write_word - write a word to a packed context structure 3827 * @src_ctx: the context structure to read from 3828 * @dest_ctx: the context to be written to 3829 * @ce_info: a description of the struct to be filled 3830 */ 3831 static void 3832 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3833 { 3834 u16 src_word, mask; 3835 __le16 dest_word; 3836 u8 *from, *dest; 3837 u16 shift_width; 3838 3839 /* copy from the next struct field */ 3840 from = src_ctx + ce_info->offset; 3841 3842 /* prepare the bits and mask */ 3843 shift_width = ce_info->lsb % 8; 3844 mask = BIT(ce_info->width) - 1; 3845 3846 /* don't swizzle the bits until after the mask because the mask bits 3847 * will be in a different bit position on big endian machines 3848 */ 3849 src_word = *(u16 *)from; 3850 src_word &= mask; 3851 3852 /* shift to correct alignment */ 3853 mask <<= shift_width; 3854 src_word <<= shift_width; 3855 3856 /* get the current bits from the target bit string */ 3857 dest = dest_ctx + (ce_info->lsb / 8); 3858 3859 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA); 3860 3861 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */ 3862 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */ 3863 3864 /* put it all back */ 3865 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 3866 } 3867 3868 /** 3869 * ice_write_dword - write a dword to a packed context structure 3870 * @src_ctx: the context structure to read from 3871 * @dest_ctx: the context to be written to 3872 * @ce_info: a description of the struct to be filled 3873 */ 3874 static void 3875 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3876 { 3877 u32 src_dword, mask; 3878 __le32 dest_dword; 3879 u8 *from, *dest; 3880 u16 shift_width; 3881 3882 /* copy from the next struct field */ 3883 from = src_ctx + ce_info->offset; 3884 3885 /* prepare the bits and mask */ 3886 shift_width = ce_info->lsb % 8; 3887 3888 /* if the field width is exactly 32 on an x86 machine, then the shift 3889 * operation will not work because the SHL instructions count is masked 3890 * to 5 bits so the shift will do nothing 3891 */ 3892 if (ce_info->width < 32) 3893 mask = BIT(ce_info->width) - 1; 3894 else 3895 mask = (u32)~0; 3896 3897 /* don't swizzle the bits until after the mask because the mask bits 3898 * will be in a different bit position on big endian machines 3899 */ 3900 src_dword = *(u32 *)from; 3901 src_dword &= mask; 3902 3903 /* shift to correct alignment */ 3904 mask <<= shift_width; 3905 src_dword <<= shift_width; 3906 3907 /* get the current bits from the target bit string */ 3908 dest = dest_ctx + (ce_info->lsb / 8); 3909 3910 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA); 3911 3912 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */ 3913 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */ 3914 3915 /* put it all back */ 3916 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 3917 } 3918 3919 /** 3920 * ice_write_qword - write a qword to a packed context structure 3921 * @src_ctx: the context structure to read from 3922 * @dest_ctx: the context to be written to 3923 * @ce_info: a description of the struct to be filled 3924 */ 3925 static void 3926 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3927 { 3928 u64 src_qword, mask; 3929 __le64 dest_qword; 3930 u8 *from, *dest; 3931 u16 shift_width; 3932 3933 /* copy from the next struct field */ 3934 from = src_ctx + ce_info->offset; 3935 3936 /* prepare the bits and mask */ 3937 shift_width = ce_info->lsb % 8; 3938 3939 /* if the field width is exactly 64 on an x86 machine, then the shift 3940 * operation will not work because the SHL instructions count is masked 3941 * to 6 bits so the shift will do nothing 3942 */ 3943 if (ce_info->width < 64) 3944 mask = BIT_ULL(ce_info->width) - 1; 3945 else 3946 mask = (u64)~0; 3947 3948 /* don't swizzle the bits until after the mask because the mask bits 3949 * will be in a different bit position on big endian machines 3950 */ 3951 src_qword = *(u64 *)from; 3952 src_qword &= mask; 3953 3954 /* shift to correct alignment */ 3955 mask <<= shift_width; 3956 src_qword <<= shift_width; 3957 3958 /* get the current bits from the target bit string */ 3959 dest = dest_ctx + (ce_info->lsb / 8); 3960 3961 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA); 3962 3963 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */ 3964 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */ 3965 3966 /* put it all back */ 3967 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 3968 } 3969 3970 /** 3971 * ice_set_ctx - set context bits in packed structure 3972 * @hw: pointer to the hardware structure 3973 * @src_ctx: pointer to a generic non-packed context structure 3974 * @dest_ctx: pointer to memory for the packed structure 3975 * @ce_info: a description of the structure to be transformed 3976 */ 3977 enum ice_status 3978 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 3979 const struct ice_ctx_ele *ce_info) 3980 { 3981 int f; 3982 3983 for (f = 0; ce_info[f].width; f++) { 3984 /* We have to deal with each element of the FW response 3985 * using the correct size so that we are correct regardless 3986 * of the endianness of the machine. 3987 */ 3988 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 3989 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 3990 f, ce_info[f].width, ce_info[f].size_of); 3991 continue; 3992 } 3993 switch (ce_info[f].size_of) { 3994 case sizeof(u8): 3995 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 3996 break; 3997 case sizeof(u16): 3998 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 3999 break; 4000 case sizeof(u32): 4001 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 4002 break; 4003 case sizeof(u64): 4004 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 4005 break; 4006 default: 4007 return ICE_ERR_INVAL_SIZE; 4008 } 4009 } 4010 4011 return ICE_SUCCESS; 4012 } 4013 4014 /** 4015 * ice_read_byte - read context byte into struct 4016 * @src_ctx: the context structure to read from 4017 * @dest_ctx: the context to be written to 4018 * @ce_info: a description of the struct to be filled 4019 */ 4020 static void 4021 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4022 { 4023 u8 dest_byte, mask; 4024 u8 *src, *target; 4025 u16 shift_width; 4026 4027 /* prepare the bits and mask */ 4028 shift_width = ce_info->lsb % 8; 4029 mask = (u8)(BIT(ce_info->width) - 1); 4030 4031 /* shift to correct alignment */ 4032 mask <<= shift_width; 4033 4034 /* get the current bits from the src bit string */ 4035 src = src_ctx + (ce_info->lsb / 8); 4036 4037 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 4038 4039 dest_byte &= ~(mask); 4040 4041 dest_byte >>= shift_width; 4042 4043 /* get the address from the struct field */ 4044 target = dest_ctx + ce_info->offset; 4045 4046 /* put it back in the struct */ 4047 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 4048 } 4049 4050 /** 4051 * ice_read_word - read context word into struct 4052 * @src_ctx: the context structure to read from 4053 * @dest_ctx: the context to be written to 4054 * @ce_info: a description of the struct to be filled 4055 */ 4056 static void 4057 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4058 { 4059 u16 dest_word, mask; 4060 u8 *src, *target; 4061 __le16 src_word; 4062 u16 shift_width; 4063 4064 /* prepare the bits and mask */ 4065 shift_width = ce_info->lsb % 8; 4066 mask = BIT(ce_info->width) - 1; 4067 4068 /* shift to correct alignment */ 4069 mask <<= shift_width; 4070 4071 /* get the current bits from the src bit string */ 4072 src = src_ctx + (ce_info->lsb / 8); 4073 4074 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA); 4075 4076 /* the data in the memory is stored as little endian so mask it 4077 * correctly 4078 */ 4079 src_word &= ~(CPU_TO_LE16(mask)); 4080 4081 /* get the data back into host order before shifting */ 4082 dest_word = LE16_TO_CPU(src_word); 4083 4084 dest_word >>= shift_width; 4085 4086 /* get the address from the struct field */ 4087 target = dest_ctx + ce_info->offset; 4088 4089 /* put it back in the struct */ 4090 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 4091 } 4092 4093 /** 4094 * ice_read_dword - read context dword into struct 4095 * @src_ctx: the context structure to read from 4096 * @dest_ctx: the context to be written to 4097 * @ce_info: a description of the struct to be filled 4098 */ 4099 static void 4100 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4101 { 4102 u32 dest_dword, mask; 4103 __le32 src_dword; 4104 u8 *src, *target; 4105 u16 shift_width; 4106 4107 /* prepare the bits and mask */ 4108 shift_width = ce_info->lsb % 8; 4109 4110 /* if the field width is exactly 32 on an x86 machine, then the shift 4111 * operation will not work because the SHL instructions count is masked 4112 * to 5 bits so the shift will do nothing 4113 */ 4114 if (ce_info->width < 32) 4115 mask = BIT(ce_info->width) - 1; 4116 else 4117 mask = (u32)~0; 4118 4119 /* shift to correct alignment */ 4120 mask <<= shift_width; 4121 4122 /* get the current bits from the src bit string */ 4123 src = src_ctx + (ce_info->lsb / 8); 4124 4125 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA); 4126 4127 /* the data in the memory is stored as little endian so mask it 4128 * correctly 4129 */ 4130 src_dword &= ~(CPU_TO_LE32(mask)); 4131 4132 /* get the data back into host order before shifting */ 4133 dest_dword = LE32_TO_CPU(src_dword); 4134 4135 dest_dword >>= shift_width; 4136 4137 /* get the address from the struct field */ 4138 target = dest_ctx + ce_info->offset; 4139 4140 /* put it back in the struct */ 4141 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 4142 } 4143 4144 /** 4145 * ice_read_qword - read context qword into struct 4146 * @src_ctx: the context structure to read from 4147 * @dest_ctx: the context to be written to 4148 * @ce_info: a description of the struct to be filled 4149 */ 4150 static void 4151 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4152 { 4153 u64 dest_qword, mask; 4154 __le64 src_qword; 4155 u8 *src, *target; 4156 u16 shift_width; 4157 4158 /* prepare the bits and mask */ 4159 shift_width = ce_info->lsb % 8; 4160 4161 /* if the field width is exactly 64 on an x86 machine, then the shift 4162 * operation will not work because the SHL instructions count is masked 4163 * to 6 bits so the shift will do nothing 4164 */ 4165 if (ce_info->width < 64) 4166 mask = BIT_ULL(ce_info->width) - 1; 4167 else 4168 mask = (u64)~0; 4169 4170 /* shift to correct alignment */ 4171 mask <<= shift_width; 4172 4173 /* get the current bits from the src bit string */ 4174 src = src_ctx + (ce_info->lsb / 8); 4175 4176 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA); 4177 4178 /* the data in the memory is stored as little endian so mask it 4179 * correctly 4180 */ 4181 src_qword &= ~(CPU_TO_LE64(mask)); 4182 4183 /* get the data back into host order before shifting */ 4184 dest_qword = LE64_TO_CPU(src_qword); 4185 4186 dest_qword >>= shift_width; 4187 4188 /* get the address from the struct field */ 4189 target = dest_ctx + ce_info->offset; 4190 4191 /* put it back in the struct */ 4192 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 4193 } 4194 4195 /** 4196 * ice_get_ctx - extract context bits from a packed structure 4197 * @src_ctx: pointer to a generic packed context structure 4198 * @dest_ctx: pointer to a generic non-packed context structure 4199 * @ce_info: a description of the structure to be read from 4200 */ 4201 enum ice_status 4202 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4203 { 4204 int f; 4205 4206 for (f = 0; ce_info[f].width; f++) { 4207 switch (ce_info[f].size_of) { 4208 case 1: 4209 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]); 4210 break; 4211 case 2: 4212 ice_read_word(src_ctx, dest_ctx, &ce_info[f]); 4213 break; 4214 case 4: 4215 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]); 4216 break; 4217 case 8: 4218 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]); 4219 break; 4220 default: 4221 /* nothing to do, just keep going */ 4222 break; 4223 } 4224 } 4225 4226 return ICE_SUCCESS; 4227 } 4228 4229 /** 4230 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4231 * @hw: pointer to the HW struct 4232 * @vsi_handle: software VSI handle 4233 * @tc: TC number 4234 * @q_handle: software queue handle 4235 */ 4236 struct ice_q_ctx * 4237 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4238 { 4239 struct ice_vsi_ctx *vsi; 4240 struct ice_q_ctx *q_ctx; 4241 4242 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4243 if (!vsi) 4244 return NULL; 4245 if (q_handle >= vsi->num_lan_q_entries[tc]) 4246 return NULL; 4247 if (!vsi->lan_q_ctx[tc]) 4248 return NULL; 4249 q_ctx = vsi->lan_q_ctx[tc]; 4250 return &q_ctx[q_handle]; 4251 } 4252 4253 /** 4254 * ice_ena_vsi_txq 4255 * @pi: port information structure 4256 * @vsi_handle: software VSI handle 4257 * @tc: TC number 4258 * @q_handle: software queue handle 4259 * @num_qgrps: Number of added queue groups 4260 * @buf: list of queue groups to be added 4261 * @buf_size: size of buffer for indirect command 4262 * @cd: pointer to command details structure or NULL 4263 * 4264 * This function adds one LAN queue 4265 */ 4266 enum ice_status 4267 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4268 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4269 struct ice_sq_cd *cd) 4270 { 4271 struct ice_aqc_txsched_elem_data node = { 0 }; 4272 struct ice_sched_node *parent; 4273 struct ice_q_ctx *q_ctx; 4274 enum ice_status status; 4275 struct ice_hw *hw; 4276 4277 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4278 return ICE_ERR_CFG; 4279 4280 if (num_qgrps > 1 || buf->num_txqs > 1) 4281 return ICE_ERR_MAX_LIMIT; 4282 4283 hw = pi->hw; 4284 4285 if (!ice_is_vsi_valid(hw, vsi_handle)) 4286 return ICE_ERR_PARAM; 4287 4288 ice_acquire_lock(&pi->sched_lock); 4289 4290 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4291 if (!q_ctx) { 4292 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4293 q_handle); 4294 status = ICE_ERR_PARAM; 4295 goto ena_txq_exit; 4296 } 4297 4298 /* find a parent node */ 4299 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4300 ICE_SCHED_NODE_OWNER_LAN); 4301 if (!parent) { 4302 status = ICE_ERR_PARAM; 4303 goto ena_txq_exit; 4304 } 4305 4306 buf->parent_teid = parent->info.node_teid; 4307 node.parent_teid = parent->info.node_teid; 4308 /* Mark that the values in the "generic" section as valid. The default 4309 * value in the "generic" section is zero. This means that : 4310 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4311 * - 0 priority among siblings, indicated by Bit 1-3. 4312 * - WFQ, indicated by Bit 4. 4313 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4314 * Bit 5-6. 4315 * - Bit 7 is reserved. 4316 * Without setting the generic section as valid in valid_sections, the 4317 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4318 */ 4319 buf->txqs[0].info.valid_sections = 4320 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4321 ICE_AQC_ELEM_VALID_EIR; 4322 buf->txqs[0].info.generic = 0; 4323 buf->txqs[0].info.cir_bw.bw_profile_idx = 4324 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 4325 buf->txqs[0].info.cir_bw.bw_alloc = 4326 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 4327 buf->txqs[0].info.eir_bw.bw_profile_idx = 4328 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 4329 buf->txqs[0].info.eir_bw.bw_alloc = 4330 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 4331 4332 /* add the LAN queue */ 4333 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4334 if (status != ICE_SUCCESS) { 4335 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4336 LE16_TO_CPU(buf->txqs[0].txq_id), 4337 hw->adminq.sq_last_status); 4338 goto ena_txq_exit; 4339 } 4340 4341 node.node_teid = buf->txqs[0].q_teid; 4342 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4343 q_ctx->q_handle = q_handle; 4344 q_ctx->q_teid = LE32_TO_CPU(node.node_teid); 4345 4346 /* add a leaf node into scheduler tree queue layer */ 4347 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 4348 if (!status) 4349 status = ice_sched_replay_q_bw(pi, q_ctx); 4350 4351 ena_txq_exit: 4352 ice_release_lock(&pi->sched_lock); 4353 return status; 4354 } 4355 4356 /** 4357 * ice_dis_vsi_txq 4358 * @pi: port information structure 4359 * @vsi_handle: software VSI handle 4360 * @tc: TC number 4361 * @num_queues: number of queues 4362 * @q_handles: pointer to software queue handle array 4363 * @q_ids: pointer to the q_id array 4364 * @q_teids: pointer to queue node teids 4365 * @rst_src: if called due to reset, specifies the reset source 4366 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4367 * @cd: pointer to command details structure or NULL 4368 * 4369 * This function removes queues and their corresponding nodes in SW DB 4370 */ 4371 enum ice_status 4372 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4373 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4374 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4375 struct ice_sq_cd *cd) 4376 { 4377 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 4378 struct ice_aqc_dis_txq_item *qg_list; 4379 struct ice_q_ctx *q_ctx; 4380 struct ice_hw *hw; 4381 u16 i, buf_size; 4382 4383 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4384 return ICE_ERR_CFG; 4385 4386 hw = pi->hw; 4387 4388 if (!num_queues) { 4389 /* if queue is disabled already yet the disable queue command 4390 * has to be sent to complete the VF reset, then call 4391 * ice_aq_dis_lan_txq without any queue information 4392 */ 4393 if (rst_src) 4394 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4395 vmvf_num, NULL); 4396 return ICE_ERR_CFG; 4397 } 4398 4399 buf_size = ice_struct_size(qg_list, q_id, 1); 4400 qg_list = (struct ice_aqc_dis_txq_item *)ice_malloc(hw, buf_size); 4401 if (!qg_list) 4402 return ICE_ERR_NO_MEMORY; 4403 4404 ice_acquire_lock(&pi->sched_lock); 4405 4406 for (i = 0; i < num_queues; i++) { 4407 struct ice_sched_node *node; 4408 4409 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4410 if (!node) 4411 continue; 4412 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4413 if (!q_ctx) { 4414 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4415 q_handles[i]); 4416 continue; 4417 } 4418 if (q_ctx->q_handle != q_handles[i]) { 4419 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4420 q_ctx->q_handle, q_handles[i]); 4421 continue; 4422 } 4423 qg_list->parent_teid = node->info.parent_teid; 4424 qg_list->num_qs = 1; 4425 qg_list->q_id[0] = CPU_TO_LE16(q_ids[i]); 4426 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4427 vmvf_num, cd); 4428 4429 if (status != ICE_SUCCESS) 4430 break; 4431 ice_free_sched_node(pi, node); 4432 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 4433 } 4434 ice_release_lock(&pi->sched_lock); 4435 ice_free(hw, qg_list); 4436 return status; 4437 } 4438 4439 /** 4440 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4441 * @pi: port information structure 4442 * @vsi_handle: software VSI handle 4443 * @tc_bitmap: TC bitmap 4444 * @maxqs: max queues array per TC 4445 * @owner: LAN or RDMA 4446 * 4447 * This function adds/updates the VSI queues per TC. 4448 */ 4449 static enum ice_status 4450 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4451 u16 *maxqs, u8 owner) 4452 { 4453 enum ice_status status = ICE_SUCCESS; 4454 u8 i; 4455 4456 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4457 return ICE_ERR_CFG; 4458 4459 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4460 return ICE_ERR_PARAM; 4461 4462 ice_acquire_lock(&pi->sched_lock); 4463 4464 ice_for_each_traffic_class(i) { 4465 /* configuration is possible only if TC node is present */ 4466 if (!ice_sched_get_tc_node(pi, i)) 4467 continue; 4468 4469 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4470 ice_is_tc_ena(tc_bitmap, i)); 4471 if (status) 4472 break; 4473 } 4474 4475 ice_release_lock(&pi->sched_lock); 4476 return status; 4477 } 4478 4479 /** 4480 * ice_cfg_vsi_lan - configure VSI LAN queues 4481 * @pi: port information structure 4482 * @vsi_handle: software VSI handle 4483 * @tc_bitmap: TC bitmap 4484 * @max_lanqs: max LAN queues array per TC 4485 * 4486 * This function adds/updates the VSI LAN queues per TC. 4487 */ 4488 enum ice_status 4489 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4490 u16 *max_lanqs) 4491 { 4492 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4493 ICE_SCHED_NODE_OWNER_LAN); 4494 } 4495 4496 /** 4497 * ice_is_main_vsi - checks whether the VSI is main VSI 4498 * @hw: pointer to the HW struct 4499 * @vsi_handle: VSI handle 4500 * 4501 * Checks whether the VSI is the main VSI (the first PF VSI created on 4502 * given PF). 4503 */ 4504 static bool ice_is_main_vsi(struct ice_hw *hw, u16 vsi_handle) 4505 { 4506 return vsi_handle == ICE_MAIN_VSI_HANDLE && hw->vsi_ctx[vsi_handle]; 4507 } 4508 4509 /** 4510 * ice_replay_pre_init - replay pre initialization 4511 * @hw: pointer to the HW struct 4512 * @sw: pointer to switch info struct for which function initializes filters 4513 * 4514 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 4515 */ 4516 static enum ice_status 4517 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw) 4518 { 4519 enum ice_status status; 4520 u8 i; 4521 4522 /* Delete old entries from replay filter list head if there is any */ 4523 ice_rm_sw_replay_rule_info(hw, sw); 4524 /* In start of replay, move entries into replay_rules list, it 4525 * will allow adding rules entries back to filt_rules list, 4526 * which is operational list. 4527 */ 4528 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 4529 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules, 4530 &sw->recp_list[i].filt_replay_rules); 4531 ice_sched_replay_agg_vsi_preinit(hw); 4532 4533 status = ice_sched_replay_root_node_bw(hw->port_info); 4534 if (status) 4535 return status; 4536 4537 return ice_sched_replay_tc_node_bw(hw->port_info); 4538 } 4539 4540 /** 4541 * ice_replay_vsi - replay VSI configuration 4542 * @hw: pointer to the HW struct 4543 * @vsi_handle: driver VSI handle 4544 * 4545 * Restore all VSI configuration after reset. It is required to call this 4546 * function with main VSI first. 4547 */ 4548 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 4549 { 4550 struct ice_switch_info *sw = hw->switch_info; 4551 struct ice_port_info *pi = hw->port_info; 4552 enum ice_status status; 4553 4554 if (!ice_is_vsi_valid(hw, vsi_handle)) 4555 return ICE_ERR_PARAM; 4556 4557 /* Replay pre-initialization if there is any */ 4558 if (ice_is_main_vsi(hw, vsi_handle)) { 4559 status = ice_replay_pre_init(hw, sw); 4560 if (status) 4561 return status; 4562 } 4563 /* Replay per VSI all RSS configurations */ 4564 status = ice_replay_rss_cfg(hw, vsi_handle); 4565 if (status) 4566 return status; 4567 /* Replay per VSI all filters */ 4568 status = ice_replay_vsi_all_fltr(hw, pi, vsi_handle); 4569 if (!status) 4570 status = ice_replay_vsi_agg(hw, vsi_handle); 4571 return status; 4572 } 4573 4574 /** 4575 * ice_replay_post - post replay configuration cleanup 4576 * @hw: pointer to the HW struct 4577 * 4578 * Post replay cleanup. 4579 */ 4580 void ice_replay_post(struct ice_hw *hw) 4581 { 4582 /* Delete old entries from replay filter list head */ 4583 ice_rm_all_sw_replay_rule_info(hw); 4584 ice_sched_replay_agg(hw); 4585 } 4586 4587 /** 4588 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 4589 * @hw: ptr to the hardware info 4590 * @reg: offset of 64 bit HW register to read from 4591 * @prev_stat_loaded: bool to specify if previous stats are loaded 4592 * @prev_stat: ptr to previous loaded stat value 4593 * @cur_stat: ptr to current stat value 4594 */ 4595 void 4596 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4597 u64 *prev_stat, u64 *cur_stat) 4598 { 4599 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 4600 4601 /* device stats are not reset at PFR, they likely will not be zeroed 4602 * when the driver starts. Thus, save the value from the first read 4603 * without adding to the statistic value so that we report stats which 4604 * count up from zero. 4605 */ 4606 if (!prev_stat_loaded) { 4607 *prev_stat = new_data; 4608 return; 4609 } 4610 4611 /* Calculate the difference between the new and old values, and then 4612 * add it to the software stat value. 4613 */ 4614 if (new_data >= *prev_stat) 4615 *cur_stat += new_data - *prev_stat; 4616 else 4617 /* to manage the potential roll-over */ 4618 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 4619 4620 /* Update the previously stored value to prepare for next read */ 4621 *prev_stat = new_data; 4622 } 4623 4624 /** 4625 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 4626 * @hw: ptr to the hardware info 4627 * @reg: offset of HW register to read from 4628 * @prev_stat_loaded: bool to specify if previous stats are loaded 4629 * @prev_stat: ptr to previous loaded stat value 4630 * @cur_stat: ptr to current stat value 4631 */ 4632 void 4633 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4634 u64 *prev_stat, u64 *cur_stat) 4635 { 4636 u32 new_data; 4637 4638 new_data = rd32(hw, reg); 4639 4640 /* device stats are not reset at PFR, they likely will not be zeroed 4641 * when the driver starts. Thus, save the value from the first read 4642 * without adding to the statistic value so that we report stats which 4643 * count up from zero. 4644 */ 4645 if (!prev_stat_loaded) { 4646 *prev_stat = new_data; 4647 return; 4648 } 4649 4650 /* Calculate the difference between the new and old values, and then 4651 * add it to the software stat value. 4652 */ 4653 if (new_data >= *prev_stat) 4654 *cur_stat += new_data - *prev_stat; 4655 else 4656 /* to manage the potential roll-over */ 4657 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 4658 4659 /* Update the previously stored value to prepare for next read */ 4660 *prev_stat = new_data; 4661 } 4662 4663 /** 4664 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values 4665 * @hw: ptr to the hardware info 4666 * @vsi_handle: VSI handle 4667 * @prev_stat_loaded: bool to specify if the previous stat values are loaded 4668 * @cur_stats: ptr to current stats structure 4669 * 4670 * The GLV_REPC statistic register actually tracks two 16bit statistics, and 4671 * thus cannot be read using the normal ice_stat_update32 function. 4672 * 4673 * Read the GLV_REPC register associated with the given VSI, and update the 4674 * rx_no_desc and rx_error values in the ice_eth_stats structure. 4675 * 4676 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be 4677 * cleared each time it's read. 4678 * 4679 * Note that the GLV_RDPC register also counts the causes that would trigger 4680 * GLV_REPC. However, it does not give the finer grained detail about why the 4681 * packets are being dropped. The GLV_REPC values can be used to distinguish 4682 * whether Rx packets are dropped due to errors or due to no available 4683 * descriptors. 4684 */ 4685 void 4686 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded, 4687 struct ice_eth_stats *cur_stats) 4688 { 4689 u16 vsi_num, no_desc, error_cnt; 4690 u32 repc; 4691 4692 if (!ice_is_vsi_valid(hw, vsi_handle)) 4693 return; 4694 4695 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle); 4696 4697 /* If we haven't loaded stats yet, just clear the current value */ 4698 if (!prev_stat_loaded) { 4699 wr32(hw, GLV_REPC(vsi_num), 0); 4700 return; 4701 } 4702 4703 repc = rd32(hw, GLV_REPC(vsi_num)); 4704 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S; 4705 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S; 4706 4707 /* Clear the count by writing to the stats register */ 4708 wr32(hw, GLV_REPC(vsi_num), 0); 4709 4710 cur_stats->rx_no_desc += no_desc; 4711 cur_stats->rx_errors += error_cnt; 4712 } 4713 4714 /** 4715 * ice_sched_query_elem - query element information from HW 4716 * @hw: pointer to the HW struct 4717 * @node_teid: node TEID to be queried 4718 * @buf: buffer to element information 4719 * 4720 * This function queries HW element information 4721 */ 4722 enum ice_status 4723 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 4724 struct ice_aqc_txsched_elem_data *buf) 4725 { 4726 u16 buf_size, num_elem_ret = 0; 4727 enum ice_status status; 4728 4729 buf_size = sizeof(*buf); 4730 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM); 4731 buf->node_teid = CPU_TO_LE32(node_teid); 4732 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 4733 NULL); 4734 if (status != ICE_SUCCESS || num_elem_ret != 1) 4735 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 4736 return status; 4737 } 4738 4739 /** 4740 * ice_get_fw_mode - returns FW mode 4741 * @hw: pointer to the HW struct 4742 */ 4743 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw) 4744 { 4745 #define ICE_FW_MODE_DBG_M BIT(0) 4746 #define ICE_FW_MODE_REC_M BIT(1) 4747 #define ICE_FW_MODE_ROLLBACK_M BIT(2) 4748 u32 fw_mode; 4749 4750 /* check the current FW mode */ 4751 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M; 4752 4753 if (fw_mode & ICE_FW_MODE_DBG_M) 4754 return ICE_FW_MODE_DBG; 4755 else if (fw_mode & ICE_FW_MODE_REC_M) 4756 return ICE_FW_MODE_REC; 4757 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M) 4758 return ICE_FW_MODE_ROLLBACK; 4759 else 4760 return ICE_FW_MODE_NORMAL; 4761 } 4762 4763 /** 4764 * ice_fw_supports_link_override 4765 * @hw: pointer to the hardware structure 4766 * 4767 * Checks if the firmware supports link override 4768 */ 4769 bool ice_fw_supports_link_override(struct ice_hw *hw) 4770 { 4771 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) { 4772 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN) 4773 return true; 4774 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN && 4775 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH) 4776 return true; 4777 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) { 4778 return true; 4779 } 4780 4781 return false; 4782 } 4783 4784 /** 4785 * ice_get_link_default_override 4786 * @ldo: pointer to the link default override struct 4787 * @pi: pointer to the port info struct 4788 * 4789 * Gets the link default override for a port 4790 */ 4791 enum ice_status 4792 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 4793 struct ice_port_info *pi) 4794 { 4795 u16 i, tlv, tlv_len, tlv_start, buf, offset; 4796 struct ice_hw *hw = pi->hw; 4797 enum ice_status status; 4798 4799 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 4800 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 4801 if (status) { 4802 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 4803 return status; 4804 } 4805 4806 /* Each port has its own config; calculate for our port */ 4807 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 4808 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 4809 4810 /* link options first */ 4811 status = ice_read_sr_word(hw, tlv_start, &buf); 4812 if (status) { 4813 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4814 return status; 4815 } 4816 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 4817 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 4818 ICE_LINK_OVERRIDE_PHY_CFG_S; 4819 4820 /* link PHY config */ 4821 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 4822 status = ice_read_sr_word(hw, offset, &buf); 4823 if (status) { 4824 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 4825 return status; 4826 } 4827 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 4828 4829 /* PHY types low */ 4830 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 4831 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4832 status = ice_read_sr_word(hw, (offset + i), &buf); 4833 if (status) { 4834 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4835 return status; 4836 } 4837 /* shift 16 bits at a time to fill 64 bits */ 4838 ldo->phy_type_low |= ((u64)buf << (i * 16)); 4839 } 4840 4841 /* PHY types high */ 4842 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 4843 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 4844 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4845 status = ice_read_sr_word(hw, (offset + i), &buf); 4846 if (status) { 4847 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4848 return status; 4849 } 4850 /* shift 16 bits at a time to fill 64 bits */ 4851 ldo->phy_type_high |= ((u64)buf << (i * 16)); 4852 } 4853 4854 return status; 4855 } 4856 4857 /** 4858 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 4859 * @caps: get PHY capability data 4860 */ 4861 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 4862 { 4863 if (caps->caps & ICE_AQC_PHY_AN_MODE || 4864 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 4865 ICE_AQC_PHY_AN_EN_CLAUSE73 | 4866 ICE_AQC_PHY_AN_EN_CLAUSE37)) 4867 return true; 4868 4869 return false; 4870 } 4871 4872 /** 4873 * ice_aq_set_lldp_mib - Set the LLDP MIB 4874 * @hw: pointer to the HW struct 4875 * @mib_type: Local, Remote or both Local and Remote MIBs 4876 * @buf: pointer to the caller-supplied buffer to store the MIB block 4877 * @buf_size: size of the buffer (in bytes) 4878 * @cd: pointer to command details structure or NULL 4879 * 4880 * Set the LLDP MIB. (0x0A08) 4881 */ 4882 enum ice_status 4883 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 4884 struct ice_sq_cd *cd) 4885 { 4886 struct ice_aqc_lldp_set_local_mib *cmd; 4887 struct ice_aq_desc desc; 4888 4889 cmd = &desc.params.lldp_set_mib; 4890 4891 if (buf_size == 0 || !buf) 4892 return ICE_ERR_PARAM; 4893 4894 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 4895 4896 desc.flags |= CPU_TO_LE16((u16)ICE_AQ_FLAG_RD); 4897 desc.datalen = CPU_TO_LE16(buf_size); 4898 4899 cmd->type = mib_type; 4900 cmd->length = CPU_TO_LE16(buf_size); 4901 4902 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4903 } 4904 4905 /** 4906 * ice_fw_supports_lldp_fltr - check NVM version supports lldp_fltr_ctrl 4907 * @hw: pointer to HW struct 4908 */ 4909 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 4910 { 4911 if (hw->mac_type != ICE_MAC_E810) 4912 return false; 4913 4914 if (hw->api_maj_ver == ICE_FW_API_LLDP_FLTR_MAJ) { 4915 if (hw->api_min_ver > ICE_FW_API_LLDP_FLTR_MIN) 4916 return true; 4917 if (hw->api_min_ver == ICE_FW_API_LLDP_FLTR_MIN && 4918 hw->api_patch >= ICE_FW_API_LLDP_FLTR_PATCH) 4919 return true; 4920 } else if (hw->api_maj_ver > ICE_FW_API_LLDP_FLTR_MAJ) { 4921 return true; 4922 } 4923 return false; 4924 } 4925 4926 /** 4927 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 4928 * @hw: pointer to HW struct 4929 * @vsi_num: absolute HW index for VSI 4930 * @add: boolean for if adding or removing a filter 4931 */ 4932 enum ice_status 4933 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 4934 { 4935 struct ice_aqc_lldp_filter_ctrl *cmd; 4936 struct ice_aq_desc desc; 4937 4938 cmd = &desc.params.lldp_filter_ctrl; 4939 4940 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 4941 4942 if (add) 4943 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 4944 else 4945 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 4946 4947 cmd->vsi_num = CPU_TO_LE16(vsi_num); 4948 4949 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4950 } 4951 4952 /** 4953 * ice_fw_supports_report_dflt_cfg 4954 * @hw: pointer to the hardware structure 4955 * 4956 * Checks if the firmware supports report default configuration 4957 */ 4958 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 4959 { 4960 if (hw->api_maj_ver == ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 4961 if (hw->api_min_ver > ICE_FW_API_REPORT_DFLT_CFG_MIN) 4962 return true; 4963 if (hw->api_min_ver == ICE_FW_API_REPORT_DFLT_CFG_MIN && 4964 hw->api_patch >= ICE_FW_API_REPORT_DFLT_CFG_PATCH) 4965 return true; 4966 } else if (hw->api_maj_ver > ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 4967 return true; 4968 } 4969 return false; 4970 } 4971